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author | Alex Rønne Petersen <alexrp@xamarin.com> | 2013-10-18 02:26:58 +0200 |
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committer | Jo Shields <directhex@apebox.org> | 2013-10-23 15:15:12 +0100 |
commit | bfe9881397d4c41980d4405830b4075418a8f147 (patch) | |
tree | 3a24cd735c2c06f02b7ba6072f01cdd5a2de4a6a | |
parent | 95998569b0293376e80e8895d19725f57366ed55 (diff) | |
download | mono-bfe9881397d4c41980d4405830b4075418a8f147.tar.gz |
Use slow 64-bit cmpxchg for 32-bit ARM, MIPS, and PowerPC.
GCC doesn't provide a 64-bit __sync_val_compare_and_swap intrinsic
for these architectures.
(cherry picked from commit 1b9ca03c22742450102f5c9c53eb953365212973)
-rwxr-xr-x | mono/utils/atomic.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/mono/utils/atomic.h b/mono/utils/atomic.h index bf7f559114..f701a442d2 100755 --- a/mono/utils/atomic.h +++ b/mono/utils/atomic.h @@ -121,7 +121,7 @@ static inline void InterlockedWrite(volatile gint32 *dst, gint32 val) InterlockedExchange (dst, val); } -#if defined (TARGET_OSX) +#if defined (TARGET_OSX) || defined (__arm__) || (defined (__mips__) && !defined (__mips64)) || (defined (__powerpc__) && !defined (__powerpc64__)) #define BROKEN_64BIT_ATOMICS_INTRINSIC 1 #endif |