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-rw-r--r--tests/expected/lscpu/lscpu-ia64-hpmatterhorn29
1 files changed, 29 insertions, 0 deletions
diff --git a/tests/expected/lscpu/lscpu-ia64-hpmatterhorn b/tests/expected/lscpu/lscpu-ia64-hpmatterhorn
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+CPU(s): 8
+Thread(s) per core: 1
+Core(s) per socket: 1
+Socket(s): 8
+NUMA node(s): 3
+Vendor ID: GenuineIntel
+CPU family: Itanium 2
+Model: 1
+CPU MHz: 1300.000000
+L1d cache: 16K
+L1i cache: 16K
+L2 cache: 256K
+L3 cache: 3072K
+NUMA node0 CPU(s): 4-7
+NUMA node1 CPU(s): 0-3
+NUMA node2 CPU(s):
+
+# The following is the parsable format, which can be fed to other
+# programs. Each different item in every column has an unique ID
+# starting from zero.
+# CPU,Core,Socket,Node,,L1d,L1i,L2,L3
+0,0,0,1,,0,0,0,0
+1,1,1,1,,1,1,1,1
+2,2,2,1,,2,2,2,2
+3,3,3,1,,3,3,3,3
+4,4,4,0,,4,4,4,4
+5,5,5,0,,5,5,5,5
+6,6,6,0,,6,6,6,6
+7,7,7,0,,7,7,7,7