* Update to SVN 20140516 (r210514) from the gcc-4_8-branch.

git-svn-id: svn://svn.debian.org/svn/gcccvs/branches/sid/gcc-4.8@7381 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca

3 files changed, 450 insertions, 22 deletions

diff --git a/debian/changelog b/debian/changelog
index e1f50ff..a8f8aac 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,9 +1,10 @@
-gcc-4.8 (4.8.2-23) UNRELEASED; urgency=medium
+gcc-4.8 (4.8.2-23) unstable; urgency=medium
 
-  * Update to SVN 20140514 (r210436) from the gcc-4_8-branch.
+  * GCC 4.8.3 release candidate 1.
+  * Update to SVN 20140516 (r210514) from the gcc-4_8-branch.
   * Apply the proposed patch for PR driver/61126.
 
- -- Matthias Klose <doko@debian.org>  Wed, 14 May 2014 14:21:37 +0200
+ -- Matthias Klose <doko@debian.org>  Sun, 18 May 2014 13:50:27 +0200
 
 gcc-4.8 (4.8.2-22) unstable; urgency=medium
 
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index ad059e3..c427f45 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 4.8 branch upto 20140514 (r210436).
+# DP: updates from the 4.8 branch upto 20140516 (r210514).
 
 last_updated()
 {
 	cat > ${dir}LAST_UPDATED <<EOF
-Wed May 14 18:55:18 CEST 2014
-Wed May 14 16:55:18 UTC 2014 (revision 210436)
+Fri May 16 13:28:00 CEST 2014
+Fri May 16 11:28:00 UTC 2014 (revision 210514)
 EOF
 }
 
@@ -9223,7 +9223,7 @@ Index: gcc/DATESTAMP
 +++ b/src/gcc/DATESTAMP	(.../branches/gcc-4_8-branch)
 @@ -1 +1 @@
 -20131016
-+20140514
++20140516
 Index: gcc/value-prof.c
 ===================================================================
 --- a/src/gcc/value-prof.c	(.../tags/gcc_4_8_2_release)
@@ -10220,7 +10220,41 @@ Index: gcc/ChangeLog
 ===================================================================
 --- a/src/gcc/ChangeLog	(.../tags/gcc_4_8_2_release)
 +++ b/src/gcc/ChangeLog	(.../branches/gcc-4_8-branch)
-@@ -1,3 +1,5440 @@
+@@ -1,3 +1,5474 @@
++2014-05-15  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2014-05-15  Peter Bergner  <bergner@vnet.ibm.com>
++
++	PR target/61193
++	* config/rs6000/htmxlintrin.h (_HTM_TBEGIN_STARTED): New define.
++	(__TM_simple_begin): Use it.
++	(__TM_begin): Likewise.
++
++2014-05-14  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* config/sparc/sparc-protos.h (sparc_absnegfloat_split_legitimate):
++	Delete.
++	* config/sparc/sparc.c (sparc_absnegfloat_split_legitimate): Likewise.
++	* config/sparc/sparc.md (fptype_ut699): New attribute.
++	(in_branch_delay): Return false if -mfix-ut699 is specified and
++	fptype_ut699 is set to single.
++	(truncdfsf2): Add fptype_ut699 attribute.
++	(fix_truncdfsi2): Likewise.
++	(floatsisf2): Change fptype attribute.
++	(fix_truncsfsi2): Likewise.
++	(negtf2_notv9): Delete.
++	(negtf2_v9): Likewise.
++	(negtf2_hq): New instruction.
++	(negtf2): New instruction and splitter.
++	(negdf2_notv9): Rewrite.
++	(abstf2_notv9): Delete.
++	(abstf2_hq_v9): Likewise.
++	(abstf2_v9): Likewise.
++	(abstf2_hq): New instruction.
++	(abstf2): New instruction and splitter.
++	(absdf2_notv9): Rewrite.
++
 +2014-05-14  Matthias Klose  <doko@ubuntu.com>
 +
 +	Revert:
@@ -15661,7 +15695,7 @@ Index: gcc/ChangeLog
  2013-10-16  Release Manager
  
  	* GCC 4.8.2 released.
-@@ -639,7 +6081,7 @@
+@@ -639,7 +6115,7 @@
  2013-07-31  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  
  	Backport from mainline
@@ -48622,7 +48656,18 @@ Index: gcc/config/sparc/sparc.md
  ;; Length (in # of insns).
  ;; Beware that setting a length greater or equal to 3 for conditional branches
  ;; has a side-effect (see output_cbranch and output_v9branch).
-@@ -420,32 +426,18 @@
+@@ -412,6 +418,10 @@
+ (define_attr "fptype" "single,double"
+   (const_string "single"))
+ 
++;; FP precision specific to the UT699.
++(define_attr "fptype_ut699" "none,single"
++  (const_string "none"))
++
+ ;; UltraSPARC-III integer load type.
+ (define_attr "us3load_type" "2cycle,3cycle"
+   (const_string "2cycle"))
+@@ -420,32 +430,18 @@
    [(set_attr "length" "2")
     (set_attr "type" "multi")])
  
@@ -48662,7 +48707,7 @@ Index: gcc/config/sparc/sparc.md
  
  ;; ??? !v9: Should implement the notion of predelay slots for floating-point
  ;; branches.  This would allow us to remove the nop always inserted before
-@@ -460,41 +452,34 @@
+@@ -460,41 +456,35 @@
  ;; because it prevents us from moving back the final store of inner loops.
  
  (define_attr "in_branch_delay" "false,true"
@@ -48676,7 +48721,8 @@ Index: gcc/config/sparc/sparc.md
 +	   (const_string "false")
 +	 (and (eq_attr "fix_ut699" "true")
 +	      (and (eq_attr "type" "fpload,fp,fpmove,fpmul,fpdivs,fpsqrts")
-+		   (eq_attr "fptype" "single")))
++		   (ior (eq_attr "fptype" "single")
++		        (eq_attr "fptype_ut699" "single"))))
 +	   (const_string "false")
 +	 (eq_attr "length" "1")
 +	   (const_string "true")
@@ -48721,7 +48767,45 @@ Index: gcc/config/sparc/sparc.md
  ;; Include SPARC DFA schedulers
  
  (include "cypress.md")
-@@ -5548,7 +5533,7 @@
+@@ -3513,7 +3503,8 @@
+   "TARGET_FPU"
+   "fdtos\t%1, %0"
+   [(set_attr "type" "fp")
+-   (set_attr "fptype" "double")])
++   (set_attr "fptype" "double")
++   (set_attr "fptype_ut699" "single")])
+ 
+ (define_expand "trunctfsf2"
+   [(set (match_operand:SF 0 "register_operand" "")
+@@ -3554,7 +3545,7 @@
+   "TARGET_FPU"
+   "fitos\t%1, %0"
+   [(set_attr "type" "fp")
+-   (set_attr "fptype" "double")])
++   (set_attr "fptype" "single")])
+ 
+ (define_insn "floatsidf2"
+   [(set (match_operand:DF 0 "register_operand" "=e")
+@@ -3641,7 +3632,7 @@
+   "TARGET_FPU"
+   "fstoi\t%1, %0"
+   [(set_attr "type" "fp")
+-   (set_attr "fptype" "double")])
++   (set_attr "fptype" "single")])
+ 
+ (define_insn "fix_truncdfsi2"
+   [(set (match_operand:SI 0 "register_operand" "=f")
+@@ -3649,7 +3640,8 @@
+   "TARGET_FPU"
+   "fdtoi\t%1, %0"
+   [(set_attr "type" "fp")
+-   (set_attr "fptype" "double")])
++   (set_attr "fptype" "double")
++   (set_attr "fptype_ut699" "single")])
+ 
+ (define_expand "fix_trunctfsi2"
+   [(set (match_operand:SI 0 "register_operand" "")
+@@ -5548,7 +5540,7 @@
    [(set (match_operand:DF 0 "register_operand" "=e")
  	(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
  		 (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
@@ -48730,7 +48814,7 @@ Index: gcc/config/sparc/sparc.md
    "fsmuld\t%1, %2, %0"
    [(set_attr "type" "fpmul")
     (set_attr "fptype" "double")])
-@@ -5575,22 +5560,39 @@
+@@ -5575,74 +5567,90 @@
  		(match_operand:TF 2 "register_operand" "e")))]
    "TARGET_FPU && TARGET_HARD_QUAD"
    "fdivq\t%1, %2, %0"
@@ -48773,7 +48857,312 @@ Index: gcc/config/sparc/sparc.md
    "fdivs\t%1, %2, %0"
    [(set_attr "type" "fpdivs")])
  
-@@ -5789,20 +5791,35 @@
+ (define_expand "negtf2"
+-  [(set (match_operand:TF 0 "register_operand" "=e,e")
+-	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
++  [(set (match_operand:TF 0 "register_operand" "")
++	(neg:TF (match_operand:TF 1 "register_operand" "")))]
+   "TARGET_FPU"
+   "")
+ 
+-(define_insn_and_split "*negtf2_notv9"
+-  [(set (match_operand:TF 0 "register_operand" "=e,e")
+-	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
+-  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
+-  "TARGET_FPU
+-   && ! TARGET_V9"
+-  "@
+-  fnegs\t%0, %0
+-  #"
+-  "&& reload_completed
+-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+-  [(set (match_dup 2) (neg:SF (match_dup 3)))
+-   (set (match_dup 4) (match_dup 5))
+-   (set (match_dup 6) (match_dup 7))]
+-  "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
+-   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
+-   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
+-   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
+-   operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
+-   operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
+-  [(set_attr "type" "fpmove,*")
+-   (set_attr "length" "*,2")])
++(define_insn "*negtf2_hq"
++  [(set (match_operand:TF 0 "register_operand" "=e")
++	(neg:TF (match_operand:TF 1 "register_operand" "e")))]
++  "TARGET_FPU && TARGET_HARD_QUAD"
++  "fnegq\t%1, %0"
++  [(set_attr "type" "fpmove")])
+ 
+-(define_insn_and_split "*negtf2_v9"
+-  [(set (match_operand:TF 0 "register_operand" "=e,e")
+-	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
+-  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
+-  "TARGET_FPU && TARGET_V9"
+-  "@
+-  fnegd\t%0, %0
+-  #"
+-  "&& reload_completed
+-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+-  [(set (match_dup 2) (neg:DF (match_dup 3)))
+-   (set (match_dup 4) (match_dup 5))]
+-  "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
+-   operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
+-   operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
+-   operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
+-  [(set_attr "type" "fpmove,*")
+-   (set_attr "length" "*,2")
+-   (set_attr "fptype" "double")])
++(define_insn_and_split "*negtf2"
++  [(set (match_operand:TF 0 "register_operand" "=e")
++	(neg:TF (match_operand:TF 1 "register_operand" "e")))]
++  "TARGET_FPU && !TARGET_HARD_QUAD"
++  "#"
++  "&& reload_completed"
++  [(clobber (const_int 0))]
++{
++  rtx set_dest = operands[0];
++  rtx set_src = operands[1];
++  rtx dest1, dest2;
++  rtx src1, src2;
+ 
++  dest1 = gen_df_reg (set_dest, 0);
++  dest2 = gen_df_reg (set_dest, 1);
++  src1 = gen_df_reg (set_src, 0);
++  src2 = gen_df_reg (set_src, 1);
++
++  /* Now emit using the real source and destination we found, swapping
++     the order if we detect overlap.  */
++  if (reg_overlap_mentioned_p (dest1, src2))
++    {
++      emit_insn (gen_movdf (dest2, src2));
++      emit_insn (gen_negdf2 (dest1, src1));
++    }
++  else
++    {
++      emit_insn (gen_negdf2 (dest1, src1));
++      if (REGNO (dest2) != REGNO (src2))
++	emit_insn (gen_movdf (dest2, src2));
++    }
++  DONE;
++}
++  [(set_attr "length" "2")])
++
+ (define_expand "negdf2"
+   [(set (match_operand:DF 0 "register_operand" "")
+ 	(neg:DF (match_operand:DF 1 "register_operand" "")))]
+@@ -5650,23 +5658,40 @@
+   "")
+ 
+ (define_insn_and_split "*negdf2_notv9"
+-  [(set (match_operand:DF 0 "register_operand" "=e,e")
+-	(neg:DF (match_operand:DF 1 "register_operand" "0,e")))]
+-  "TARGET_FPU && ! TARGET_V9"
+-  "@
+-  fnegs\t%0, %0
+-  #"
+-  "&& reload_completed
+-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+-  [(set (match_dup 2) (neg:SF (match_dup 3)))
+-   (set (match_dup 4) (match_dup 5))]
+-  "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
+-   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
+-   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
+-   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
+-  [(set_attr "type" "fpmove,*")
+-   (set_attr "length" "*,2")])
++  [(set (match_operand:DF 0 "register_operand" "=e")
++	(neg:DF (match_operand:DF 1 "register_operand" "e")))]
++  "TARGET_FPU && !TARGET_V9"
++  "#"
++  "&& reload_completed"
++  [(clobber (const_int 0))]
++{
++  rtx set_dest = operands[0];
++  rtx set_src = operands[1];
++  rtx dest1, dest2;
++  rtx src1, src2;
+ 
++  dest1 = gen_highpart (SFmode, set_dest);
++  dest2 = gen_lowpart (SFmode, set_dest);
++  src1 = gen_highpart (SFmode, set_src);
++  src2 = gen_lowpart (SFmode, set_src);
++
++  /* Now emit using the real source and destination we found, swapping
++     the order if we detect overlap.  */
++  if (reg_overlap_mentioned_p (dest1, src2))
++    {
++      emit_insn (gen_movsf (dest2, src2));
++      emit_insn (gen_negsf2 (dest1, src1));
++    }
++  else
++    {
++      emit_insn (gen_negsf2 (dest1, src1));
++      if (REGNO (dest2) != REGNO (src2))
++	emit_insn (gen_movsf (dest2, src2));
++    }
++  DONE;
++}
++  [(set_attr "length" "2")])
++
+ (define_insn "*negdf2_v9"
+   [(set (match_operand:DF 0 "register_operand" "=e")
+ 	(neg:DF (match_operand:DF 1 "register_operand" "e")))]
+@@ -5688,57 +5713,48 @@
+   "TARGET_FPU"
+   "")
+ 
+-(define_insn_and_split "*abstf2_notv9"
+-  [(set (match_operand:TF 0 "register_operand" "=e,e")
+-	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
+-  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
+-  "TARGET_FPU && ! TARGET_V9"
+-  "@
+-  fabss\t%0, %0
+-  #"
+-  "&& reload_completed
+-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+-  [(set (match_dup 2) (abs:SF (match_dup 3)))
+-   (set (match_dup 4) (match_dup 5))
+-   (set (match_dup 6) (match_dup 7))]
+-  "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
+-   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
+-   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
+-   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
+-   operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
+-   operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
+-  [(set_attr "type" "fpmove,*")
+-   (set_attr "length" "*,2")])
++(define_insn "*abstf2_hq"
++  [(set (match_operand:TF 0 "register_operand" "=e")
++	(abs:TF (match_operand:TF 1 "register_operand" "e")))]
++  "TARGET_FPU && TARGET_HARD_QUAD"
++  "fabsq\t%1, %0"
++  [(set_attr "type" "fpmove")])
+ 
+-(define_insn "*abstf2_hq_v9"
+-  [(set (match_operand:TF 0 "register_operand" "=e,e")
+-	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
+-  "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD"
+-  "@
+-  fabsd\t%0, %0
+-  fabsq\t%1, %0"
+-  [(set_attr "type" "fpmove")
+-   (set_attr "fptype" "double,*")])
++(define_insn_and_split "*abstf2"
++  [(set (match_operand:TF 0 "register_operand" "=e")
++	(abs:TF (match_operand:TF 1 "register_operand" "e")))]
++  "TARGET_FPU && !TARGET_HARD_QUAD"
++  "#"
++  "&& reload_completed"
++  [(clobber (const_int 0))]
++{
++  rtx set_dest = operands[0];
++  rtx set_src = operands[1];
++  rtx dest1, dest2;
++  rtx src1, src2;
+ 
+-(define_insn_and_split "*abstf2_v9"
+-  [(set (match_operand:TF 0 "register_operand" "=e,e")
+-	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
+-  "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD"
+-  "@
+-  fabsd\t%0, %0
+-  #"
+-  "&& reload_completed
+-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+-  [(set (match_dup 2) (abs:DF (match_dup 3)))
+-   (set (match_dup 4) (match_dup 5))]
+-  "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
+-   operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
+-   operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
+-   operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
+-  [(set_attr "type" "fpmove,*")
+-   (set_attr "length" "*,2")
+-   (set_attr "fptype" "double,*")])
++  dest1 = gen_df_reg (set_dest, 0);
++  dest2 = gen_df_reg (set_dest, 1);
++  src1 = gen_df_reg (set_src, 0);
++  src2 = gen_df_reg (set_src, 1);
+ 
++  /* Now emit using the real source and destination we found, swapping
++     the order if we detect overlap.  */
++  if (reg_overlap_mentioned_p (dest1, src2))
++    {
++      emit_insn (gen_movdf (dest2, src2));
++      emit_insn (gen_absdf2 (dest1, src1));
++    }
++  else
++    {
++      emit_insn (gen_absdf2 (dest1, src1));
++      if (REGNO (dest2) != REGNO (src2))
++	emit_insn (gen_movdf (dest2, src2));
++    }
++  DONE;
++}
++  [(set_attr "length" "2")])
++
+ (define_expand "absdf2"
+   [(set (match_operand:DF 0 "register_operand" "")
+ 	(abs:DF (match_operand:DF 1 "register_operand" "")))]
+@@ -5746,23 +5762,40 @@
+   "")
+ 
+ (define_insn_and_split "*absdf2_notv9"
+-  [(set (match_operand:DF 0 "register_operand" "=e,e")
+-	(abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
+-  "TARGET_FPU && ! TARGET_V9"
+-  "@
+-  fabss\t%0, %0
+-  #"
+-  "&& reload_completed
+-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+-  [(set (match_dup 2) (abs:SF (match_dup 3)))
+-   (set (match_dup 4) (match_dup 5))]
+-  "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
+-   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
+-   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
+-   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
+-  [(set_attr "type" "fpmove,*")
+-   (set_attr "length" "*,2")])
++  [(set (match_operand:DF 0 "register_operand" "=e")
++	(abs:DF (match_operand:DF 1 "register_operand" "e")))]
++  "TARGET_FPU && !TARGET_V9"
++  "#"
++  "&& reload_completed"
++  [(clobber (const_int 0))]
++{
++  rtx set_dest = operands[0];
++  rtx set_src = operands[1];
++  rtx dest1, dest2;
++  rtx src1, src2;
+ 
++  dest1 = gen_highpart (SFmode, set_dest);
++  dest2 = gen_lowpart (SFmode, set_dest);
++  src1 = gen_highpart (SFmode, set_src);
++  src2 = gen_lowpart (SFmode, set_src);
++
++  /* Now emit using the real source and destination we found, swapping
++     the order if we detect overlap.  */
++  if (reg_overlap_mentioned_p (dest1, src2))
++    {
++      emit_insn (gen_movsf (dest2, src2));
++      emit_insn (gen_abssf2 (dest1, src1));
++    }
++  else
++    {
++      emit_insn (gen_abssf2 (dest1, src1));
++      if (REGNO (dest2) != REGNO (src2))
++	emit_insn (gen_movsf (dest2, src2));
++    }
++  DONE;
++}
++  [(set_attr "length" "2")])
++
+ (define_insn "*absdf2_v9"
+   [(set (match_operand:DF 0 "register_operand" "=e")
+ 	(abs:DF (match_operand:DF 1 "register_operand" "e")))]
+@@ -5789,20 +5822,35 @@
  	(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
    "TARGET_FPU && TARGET_HARD_QUAD"
    "fsqrtq\t%1, %0"
@@ -48812,7 +49201,7 @@ Index: gcc/config/sparc/sparc.md
    "fsqrts\t%1, %0"
    [(set_attr "type" "fpsqrts")])
  
-@@ -5821,19 +5838,6 @@
+@@ -5821,19 +5869,6 @@
  }
    [(set_attr "type" "shift")])
  
@@ -48993,7 +49382,15 @@ Index: gcc/config/sparc/sparc-protos.h
 ===================================================================
 --- a/src/gcc/config/sparc/sparc-protos.h	(.../tags/gcc_4_8_2_release)
 +++ b/src/gcc/config/sparc/sparc-protos.h	(.../branches/gcc-4_8-branch)
-@@ -84,9 +84,9 @@
+@@ -69,7 +69,6 @@
+ extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx);
+ extern int sparc_splitdi_legitimate (rtx, rtx);
+ extern int sparc_split_regreg_legitimate (rtx, rtx);
+-extern int sparc_absnegfloat_split_legitimate (rtx, rtx);
+ extern const char *output_ubranch (rtx, rtx);
+ extern const char *output_cbranch (rtx, rtx, int, int, int, rtx);
+ extern const char *output_return (rtx);
+@@ -84,9 +83,9 @@
  extern int mems_ok_for_ldd_peep (rtx, rtx, rtx);
  extern int empty_delay_slot (rtx);
  extern int emit_cbcond_nop (rtx);
@@ -49549,7 +49946,30 @@ Index: gcc/config/sparc/sparc.c
    /* Otherwise, only operations which can be done in tandem with
       a `restore' insn can go into the delay slot.  */
    if (GET_CODE (SET_DEST (pat)) != REG
-@@ -10355,7 +10690,8 @@
+@@ -8134,22 +8469,6 @@
+   return 0;
+ }
+ 
+-/* Return 1 if x and y are some kind of REG and they refer to
+-   different hard registers.  This test is guaranteed to be
+-   run after reload.  */
+-
+-int
+-sparc_absnegfloat_split_legitimate (rtx x, rtx y)
+-{
+-  if (GET_CODE (x) != REG)
+-    return 0;
+-  if (GET_CODE (y) != REG)
+-    return 0;
+-  if (REGNO (x) == REGNO (y))
+-    return 0;
+-  return 1;
+-}
+-
+ /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
+    This makes them candidates for using ldd and std insns.
+ 
+@@ -10355,7 +10674,8 @@
  	      tmp = e0.add_with_sign (tmp, false, &add1_ovf);
  	      if (tmp.is_negative ())
  		tmp = tmp.neg_with_overflow (&neg2_ovf);
@@ -49559,7 +49979,7 @@ Index: gcc/config/sparc/sparc.c
  	      result = result.add_with_sign (tmp, false, &add2_ovf);
  	      overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf;
  	    }
-@@ -10897,107 +11233,6 @@
+@@ -10897,107 +11217,6 @@
    return (vcall_offset >= -32768 || ! fixed_regs[5]);
  }
  
@@ -55781,7 +56201,7 @@ Index: gcc/config/rs6000/htmxlintrin.h
 ===================================================================
 --- a/src/gcc/config/rs6000/htmxlintrin.h	(.../tags/gcc_4_8_2_release)
 +++ b/src/gcc/config/rs6000/htmxlintrin.h	(.../branches/gcc-4_8-branch)
-@@ -0,0 +1,208 @@
+@@ -0,0 +1,213 @@
 +/* XL compiler Hardware Transactional Memory (HTM) execution intrinsics.
 +   Copyright (C) 2013 Free Software Foundation, Inc.
 +   Contributed by Peter Bergner <bergner@vnet.ibm.com>.
@@ -55830,12 +56250,17 @@ Index: gcc/config/rs6000/htmxlintrin.h
 +
 +typedef char TM_buff_type[16];
 +
++/* Compatibility macro with s390.  This macro can be used to determine
++   whether a transaction was successfully started from the __TM_begin()
++   and __TM_simple_begin() intrinsic functions below.  */
++#define _HTM_TBEGIN_STARTED     1
++
 +extern __inline long
 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 +__TM_simple_begin (void)
 +{
 +  if (__builtin_expect (__builtin_tbegin (0), 1))
-+    return 1;
++    return _HTM_TBEGIN_STARTED;
 +  return 0;
 +}
 +
@@ -55845,7 +56270,7 @@ Index: gcc/config/rs6000/htmxlintrin.h
 +{
 +  *_TEXASRL_PTR (TM_buff) = 0;
 +  if (__builtin_expect (__builtin_tbegin (0), 1))
-+    return 1;
++    return _HTM_TBEGIN_STARTED;
 +#ifdef __powerpc64__
 +  *_TEXASR_PTR (TM_buff) = __builtin_get_texasr ();
 +#else
diff --git a/debian/rules2 b/debian/rules2
index 0befd10..a7525fa 100644
--- a/debian/rules2
+++ b/debian/rules2
@@ -1439,6 +1439,7 @@ $(check_stamp): $(build_stamp) $(build_locale_stamp)
 	ln -sf gcc $(builddir)/prev-gcc
 	ln -sf $(DEB_TARGET_GNU_TYPE) $(builddir)/prev-$(DEB_TARGET_GNU_TYPE)
 
+ifeq (0,1)
 ifneq ($(with_common_libs),yes)
   ifeq ($(with_cxx),yes)
 	: # libstdc++6 built from newer gcc-4.x source, run testsuite against the installed lib
@@ -1471,6 +1472,7 @@ ifneq ($(with_common_libs),yes)
 	  | xargs -r rm -f
   endif
 endif
+endif
 
 ifeq ($(start_logwatch),yes)
 	: # start logwatch script for regular output during test runs