diff options
| author | doko <doko@6ca36cf4-e1d1-0310-8c6f-e303bb2178ca> | 2013-06-11 11:41:32 +0000 |
|---|---|---|
| committer | doko <doko@6ca36cf4-e1d1-0310-8c6f-e303bb2178ca> | 2013-06-11 11:41:32 +0000 |
| commit | 5e137147eba3e338df5fba7a1b6404d7eb5db72f (patch) | |
| tree | 11d00fd8e2f2867c3ec89a915d19b4ac618272f8 /debian/patches/gcc-linaro.diff | |
| parent | f44058698ef8e5823eca52687d70d32391b4014b (diff) | |
| download | gcc-48-5e137147eba3e338df5fba7a1b6404d7eb5db72f.tar.gz | |
* Update the Linaro support to the 4.8-2013.06 release.
git-svn-id: svn://svn.debian.org/svn/gcccvs/branches/sid/gcc-4.8@6823 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
Diffstat (limited to 'debian/patches/gcc-linaro.diff')
| -rw-r--r-- | debian/patches/gcc-linaro.diff | 5525 |
1 files changed, 5212 insertions, 313 deletions
diff --git a/debian/patches/gcc-linaro.diff b/debian/patches/gcc-linaro.diff index ef2ad7f..c707e1d 100644 --- a/debian/patches/gcc-linaro.diff +++ b/debian/patches/gcc-linaro.diff @@ -1,66 +1,127 @@ -# DP: Changes for the Linaro 4.8-2013.05 release. +# DP: Changes for the Linaro 4.8-2013.06 release. -LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ - svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@r198871 \ +LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@r199923 \ | filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/ --- a/src/libitm/ChangeLog.linaro +++ b/src/libitm/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libgomp/ChangeLog.linaro +++ b/src/libgomp/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libquadmath/ChangeLog.linaro +++ b/src/libquadmath/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. +--- a/src/libsanitizer/sanitizer_common/sanitizer_linux.cc ++++ b/src/libsanitizer/sanitizer_common/sanitizer_linux.cc +@@ -410,7 +410,9 @@ + CHECK_EQ(*current_++, ' '); + while (IsDecimal(*current_)) + current_++; +- CHECK_EQ(*current_++, ' '); ++ // Qemu may lack the trailing space. ++ // http://code.google.com/p/address-sanitizer/issues/detail?id=160 ++ // CHECK_EQ(*current_++, ' '); + // Skip spaces. + while (current_ < next_line && *current_ == ' ') + current_++; --- a/src/libsanitizer/ChangeLog.linaro +++ b/src/libsanitizer/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,15 @@ ++2013-06-04 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r199606. ++ 2013-06-03 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ * sanitizer_common/sanitizer_linux.cc (MemoryMappingLayout::Next): ++ Cherry pick upstream r182922. ++ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/zlib/ChangeLog.linaro +++ b/src/zlib/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libstdc++-v3/ChangeLog.linaro +++ b/src/libstdc++-v3/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/intl/ChangeLog.linaro +++ b/src/intl/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/ChangeLog.linaro +++ b/src/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libmudflap/ChangeLog.linaro +++ b/src/libmudflap/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/boehm-gc/ChangeLog.linaro +++ b/src/boehm-gc/ChangeLog.linaro -@@ -0,0 +1,16 @@ +@@ -0,0 +1,20 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-05-02 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + Backport from trunk r197770. @@ -147,25 +208,41 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ # define MACH_TYPE "ARM32" --- a/src/include/ChangeLog.linaro +++ b/src/include/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libiberty/ChangeLog.linaro +++ b/src/libiberty/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/lto-plugin/ChangeLog.linaro +++ b/src/lto-plugin/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/regression/ChangeLog.linaro +++ b/src/contrib/regression/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. @@ -183,7 +260,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ arm-linux-androideabi arm-uclinux_eabi arm-eabi \ --- a/src/contrib/ChangeLog.linaro +++ b/src/contrib/ChangeLog.linaro -@@ -0,0 +1,10 @@ +@@ -0,0 +1,14 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-05-02 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + Backport from trunk r198443. @@ -196,61 +277,101 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/reghunt/ChangeLog.linaro +++ b/src/contrib/reghunt/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libatomic/ChangeLog.linaro +++ b/src/libatomic/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/config/ChangeLog.linaro +++ b/src/config/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libbacktrace/ChangeLog.linaro +++ b/src/libbacktrace/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/libltdl/ChangeLog.linaro +++ b/src/libjava/libltdl/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/ChangeLog.linaro +++ b/src/libjava/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/classpath/ChangeLog.linaro +++ b/src/libjava/classpath/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/gnattools/ChangeLog.linaro +++ b/src/gnattools/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/maintainer-scripts/ChangeLog.linaro +++ b/src/maintainer-scripts/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libgcc/ChangeLog.linaro +++ b/src/libgcc/ChangeLog.linaro -@@ -0,0 +1,13 @@ +@@ -0,0 +1,17 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-05-02 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + Backport from trunk r198090. @@ -279,20 +400,28 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ typedef int TItype __attribute__ ((mode (TI))); --- a/src/libgcc/config/libbid/ChangeLog.linaro +++ b/src/libgcc/config/libbid/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libdecnumber/ChangeLog.linaro +++ b/src/libdecnumber/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/LINARO-VERSION +++ b/src/gcc/LINARO-VERSION @@ -0,0 +1 @@ -+4.8-2013.05 ++4.8-2013.05-1~dev --- a/src/gcc/hooks.c +++ b/src/gcc/hooks.c @@ -147,6 +147,14 @@ @@ -322,19 +451,31 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ HOST_WIDE_INT, --- a/src/gcc/c-family/ChangeLog.linaro +++ b/src/gcc/c-family/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/java/ChangeLog.linaro +++ b/src/gcc/java/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/c/ChangeLog.linaro +++ b/src/gcc/c/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. @@ -389,13 +530,360 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ --- a/src/gcc/objc/ChangeLog.linaro +++ b/src/gcc/objc/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/ChangeLog.linaro +++ b/src/gcc/ChangeLog.linaro -@@ -0,0 +1,732 @@ +@@ -0,0 +1,1075 @@ ++2013-06-06 Zhenqiang Chen <zhenqiang.chen@linaro.org> ++ ++ Backport from mainline (r199438, r199439) ++ 2013-05-30 Zhenqiang Chen <zhenqiang.chen@linaro.org> ++ ++ * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added. ++ (arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes. ++ (arm_emit_vfp_multi_reg_pop): Likewise. ++ (thumb2_emit_ldrd_pop): Likewise. ++ (arm_expand_epilogue): Add misc REG_CFA notes. ++ (arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE. ++ ++ 2013-05-30 Bernd Schmidt <bernds@codesourcery.com> ++ Zhenqiang Chen <zhenqiang.chen@linaro.org> ++ ++ * config/arm/arm-protos.h: Add and update function protos. ++ * config/arm/arm.c (use_simple_return_p): New added. ++ (thumb2_expand_return): Check simple_return flag. ++ * config/arm/arm.md: Add simple_return and conditional simple_return. ++ * config/arm/iterators.md: Add iterator for return and simple_return. ++ * gcc.dg/shrink-wrap-alloca.c: New added. ++ * gcc.dg/shrink-wrap-pretend.c: New added. ++ * gcc.dg/shrink-wrap-sibcall.c: New added. ++ ++2013-06-06 Kugan Vivekanandarajah <kuganv@linaro.org> ++ ++ Backport from mainline r198879: ++ ++ 2013-05-14 Chung-Lin Tang <cltang@codesourcery.com> ++ PR target/42017 ++ * config/arm/arm.h (EPILOGUE_USES): Only return true ++ for LR_REGNUM after epilogue_completed. ++ ++2013-06-05 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r199652,199653,199656,199657,199658. ++ ++ 2013-06-04 Ian Bolton <ian.bolton@arm.com> ++ ++ * config/aarch64/aarch64.md (*mov<mode>_aarch64): Call ++ into function to generate MOVI instruction. ++ * config/aarch64/aarch64.c (aarch64_simd_container_mode): ++ New function. ++ (aarch64_preferred_simd_mode): Turn into wrapper. ++ (aarch64_output_scalar_simd_mov_immediate): New function. ++ * config/aarch64/aarch64-protos.h: Add prototype for above. ++ ++ 2013-06-04 Ian Bolton <ian.bolton@arm.com> ++ ++ * config/aarch64/aarch64.c (simd_immediate_info): Remove ++ element_char member. ++ (sizetochar): Return signed char. ++ (aarch64_simd_valid_immediate): Remove elchar and other ++ unnecessary variables. ++ (aarch64_output_simd_mov_immediate): Take rtx instead of &rtx. ++ Calculate element_char as required. ++ * config/aarch64/aarch64-protos.h: Update and move prototype ++ for aarch64_output_simd_mov_immediate. ++ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): ++ Update arguments. ++ ++ 2013-06-04 Ian Bolton <ian.bolton@arm.com> ++ ++ * config/aarch64/aarch64.c (simd_immediate_info): Struct to hold ++ information completed by aarch64_simd_valid_immediate. ++ (aarch64_legitimate_constant_p): Update arguments. ++ (aarch64_simd_valid_immediate): Work with struct rather than many ++ pointers. ++ (aarch64_simd_scalar_immediate_valid_for_move): Update arguments. ++ (aarch64_simd_make_constant): Update arguments. ++ (aarch64_output_simd_mov_immediate): Work with struct rather than ++ many pointers. Output immediate directly rather than as operand. ++ * config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate): ++ Update prototype. ++ * config/aarch64/constraints.md (Dn): Update arguments. ++ ++ 2013-06-04 Ian Bolton <ian.bolton@arm.com> ++ ++ * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): No ++ longer static. ++ (aarch64_simd_immediate_valid_for_move): Remove. ++ (aarch64_simd_scalar_immediate_valid_for_move): Update call. ++ (aarch64_simd_make_constant): Update call. ++ (aarch64_output_simd_mov_immediate): Update call. ++ * config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate): ++ Add prototype. ++ * config/aarch64/constraints.md (Dn): Update call. ++ ++ 2013-06-04 Ian Bolton <ian.bolton@arm.com> ++ ++ * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Change ++ return type to bool for prototype. ++ (aarch64_legitimate_constant_p): Check for true instead of not -1. ++ (aarch64_simd_valid_immediate): Fix up each return to return a bool. ++ (aarch64_simd_immediate_valid_for_move): Update retval for bool. ++ ++2013-06-04 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r199261. ++ 2013-05-23 Christian Bruel <christian.bruel@st.com> ++ ++ PR debug/57351 ++ * config/arm/arm.c (arm_dwarf_register_span): Do not use dbx number. ++ ++2013-06-03 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk ++ r198890,199254,199259,199260,199293,199407,199408,199454,199544,199545. ++ ++ 2013-05-31 Marcus Shawcroft <marcus.shawcroft@arm.com> ++ ++ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): ++ Remove un-necessary braces. ++ ++ 2013-05-31 Marcus Shawcroft <marcus.shawcroft@arm.com> ++ ++ * config/aarch64/aarch64.c (aarch64_classify_symbol): ++ Use SYMBOL_TINY_ABSOLUTE for AARCH64_CMODEL_TINY_PIC. ++ ++ 2013-05-30 Ian Bolton <ian.bolton@arm.com> ++ ++ * config/aarch64/aarch64.md (insv<mode>): New define_expand. ++ (*insv_reg<mode>): New define_insn. ++ ++ 2012-05-29 Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com> ++ Marcus Shawcroft <marcus.shawcroft@arm.com> ++ ++ * config/aarch64/aarch64-protos.h (aarch64_symbol_type): Define ++ SYMBOL_TINY_ABSOLUTE. ++ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Handle ++ SYMBOL_TINY_ABSOLUTE. ++ (aarch64_expand_mov_immediate): Likewise. ++ (aarch64_classify_symbol): Likewise. ++ (aarch64_mov_operand_p): Remove ATTRIBUTE_UNUSED. ++ Permit SYMBOL_TINY_ABSOLUTE. ++ * config/aarch64/predicates.md (aarch64_mov_operand): Permit CONST. ++ ++ 2013-05-29 Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com> ++ Marcus Shawcroft <marcus.shawcroft@arm.com> ++ ++ * config/aarch64/aarch64.c (aarch64_classify_symbol): Remove comment. ++ Refactor if/switch. Replace gcc_assert with if. ++ ++ 2013-05-24 Ian Bolton <ian.bolton@arm.com> ++ ++ * config/aarch64/aarch64.c (aarch64_print_operand): Change the ++ X format specifier to only display bottom 16 bits. ++ * config/aarch64/aarch64.md (insv_imm<mode>): Allow any size of ++ immediate to match for operand 2, since it will be masked. ++ ++ 2013-05-23 Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com> ++ Marcus Shawcroft <marcus.shawcroft@arm.com> ++ ++ * config/aarch64/aarch64.md (*movdi_aarch64): Replace Usa with S. ++ * config/aarch64/constraints.md (Usa): Remove. ++ * doc/md.texi (AArch64 Usa): Remove. ++ ++ 2013-05-23 Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com> ++ Marcus Shawcroft <marcus.shawcroft@arm.com> ++ ++ * config/aarch64/aarch64-protos.h (aarch64_mov_operand_p): Define. ++ * config/aarch64/aarch64.c (aarch64_mov_operand_p): Define. ++ * config/aarch64/predicates.md (aarch64_const_address): Remove. ++ (aarch64_mov_operand): Use aarch64_mov_operand_p. ++ ++ 2013-05-23 Vidya Praveen <vidyapraveen@arm.com> ++ ++ * config/aarch64/aarch64-simd.md (clzv4si2): Support for CLZ ++ instruction (AdvSIMD). ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_builtin_vectorized_function): Handler for BUILT_IN_CLZ. ++ * config/aarch64/aarch-simd-builtins.def: Entry for CLZ. ++ ++ 2013-05-14 James Greenhalgh <james.greenhalgh@arm.com> ++ ++ * config/aarch64/aarch64-simd.md ++ (aarch64_vcond_internal<mode>): Rename to... ++ (aarch64_vcond_internal<mode><mode>): ...This, for integer modes. ++ (aarch64_vcond_internal<VDQF_COND:mode><VDQF:mode>): ...This for ++ float modes. Clarify all iterator modes. ++ (vcond<mode><mode>): Use new name for vcond expanders. ++ (vcond<v_cmp_result><mode>): Likewise. ++ (vcondu<mode><mode>: Likewise. ++ * config/aarch64/iterators.md (VDQF_COND): New. ++ ++2013-05-29 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198928,198973,199203. ++ 2013-05-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> ++ ++ PR target/19599 ++ PR target/57340 ++ * config/arm/arm.c (any_sibcall_uses_r3): Rename to .. ++ (any_sibcall_could_use_r3): this and handle indirect calls. ++ (arm_get_frame_offsets): Rename use of any_sibcall_uses_r3. ++ ++ 2013-05-16 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> ++ ++ PR target/19599 ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Add check ++ for NULL decl. ++ ++ 2013-05-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> ++ ++ PR target/19599 ++ * config/arm/predicates.md (call_insn_operand): New predicate. ++ * config/arm/constraints.md ("Cs", "Ss"): New constraints. ++ * config/arm/arm.md (*call_insn, *call_value_insn): Match only ++ if insn is not a tail call. ++ (*sibcall_insn, *sibcall_value_insn): Adjust for tailcalling through ++ registers. ++ * config/arm/arm.h (enum reg_class): New caller save register class. ++ (REG_CLASS_NAMES): Likewise. ++ (REG_CLASS_CONTENTS): Likewise. ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling ++ without decls. ++ ++2013-05-28 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198680. ++ 2013-05-07 Sofiane Naci <sofiane.naci@arm.com> ++ ++ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): call splitter. ++ (aarch64_simd_mov<mode>): New expander. ++ (aarch64_simd_mov_to_<mode>low): New instruction pattern. ++ (aarch64_simd_mov_to_<mode>high): Likewise. ++ (aarch64_simd_mov_from_<mode>low): Likewise. ++ (aarch64_simd_mov_from_<mode>high): Likewise. ++ (aarch64_dup_lane<mode>): Update. ++ (aarch64_dup_lanedi): New instruction pattern. ++ * config/aarch64/aarch64-protos.h (aarch64_split_simd_move): New prototype. ++ * config/aarch64/aarch64.c (aarch64_split_simd_move): New function. ++ ++2013-05-28 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198497-198500. ++ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com> ++ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_gimple_fold_builtin.c): Fold more modes for reduc_splus_. ++ * config/aarch64/aarch64-simd-builtins.def ++ (reduc_splus_): Add new modes. ++ (reduc_uplus_): New. ++ * config/aarch64/aarch64-simd.md (aarch64_addvv4sf): Remove. ++ (reduc_uplus_v4sf): Likewise. ++ (reduc_splus_v4sf): Likewise. ++ (aarch64_addv<mode>): Likewise. ++ (reduc_uplus_<mode>): Likewise. ++ (reduc_splus_<mode>): Likewise. ++ (aarch64_addvv2di): Likewise. ++ (reduc_uplus_v2di): Likewise. ++ (reduc_splus_v2di): Likewise. ++ (aarch64_addvv2si): Likewise. ++ (reduc_uplus_v2si): Likewise. ++ (reduc_splus_v2si): Likewise. ++ (reduc_<sur>plus_<mode>): New. ++ (reduc_<sur>plus_v2di): Likewise. ++ (reduc_<sur>plus_v2si): Likewise. ++ (reduc_<sur>plus_v4sf): Likewise. ++ (aarch64_addpv4sf): Likewise. ++ * config/aarch64/arm_neon.h ++ (vaddv<q>_<s,u,f><8, 16, 32, 64): Rewrite using builtins. ++ * config/aarch64/iterators.md (unspec): Remove UNSPEC_ADDV, ++ add UNSPEC_SADDV, UNSPEC_UADDV. ++ (SUADDV): New. ++ (sur): Add UNSPEC_SADDV, UNSPEC_UADDV. ++ ++ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com> ++ ++ * config/aarch64/arm_neon.h ++ (v<max,min><nm><q><v>_<sfu><8, 16, 32, 64>): Rewrite using builtins. ++ ++ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com> ++ ++ * config/aarch64/aarch64-builtins ++ (aarch64_gimple_fold_builtin): Fold reduc_<su><maxmin>_ builtins. ++ ++ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com> ++ ++ * config/aarch64/aarch64-simd-builtins.def ++ (reduc_smax_): New. ++ (reduc_smin_): Likewise. ++ (reduc_umax_): Likewise. ++ (reduc_umin_): Likewise. ++ (reduc_smax_nan_): Likewise. ++ (reduc_smin_nan_): Likewise. ++ (fmax): Remove. ++ (fmin): Likewise. ++ (smax): Update for V2SF, V4SF and V2DF modes. ++ (smin): Likewise. ++ (smax_nan): New. ++ (smin_nan): Likewise. ++ * config/aarch64/aarch64-simd.md (<maxmin><mode>3): Rename to... ++ (<su><maxmin><mode>3): ...This, refactor. ++ (s<maxmin><mode>3): New. ++ (<maxmin_uns><mode>3): Likewise. ++ (reduc_<maxmin_uns>_<mode>): Refactor. ++ (reduc_<maxmin_uns>_v4sf): Likewise. ++ (reduc_<maxmin_uns>_v2si): Likewise. ++ (aarch64_<fmaxmin><mode>: Remove. ++ * config/aarch64/arm_neon.h (vmax<q>_f<32,64>): Rewrite to use ++ new builtin names. ++ (vmin<q>_f<32,64>): Likewise. ++ * config/iterators.md (unspec): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. ++ (FMAXMIN): New. ++ (su): Add mappings for smax, smin, umax, umin. ++ (maxmin): New. ++ (FMAXMINV): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. ++ (FMAXMIN): Rename as... ++ (FMAXMIN_UNS): ...This. ++ (maxminv): Remove. ++ (fmaxminv): Likewise. ++ (fmaxmin): Likewise. ++ (maxmin_uns): New. ++ (maxmin_uns_op): Likewise. ++ ++2013-05-28 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r199241. ++ 2013-05-23 James Greenhalgh <james.greenhalgh@arm.com> ++ ++ * config/aarch64/aarch64-simd.md ++ (aarch64_cm<optab>di): Add clobber of CC_REGNUM to unsplit pattern. ++ ++2013-05-23 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198970. ++ 2013-05-16 Greta Yorsh <Greta.Yorsh@arm.com> ++ ++ * config/arm/arm-protos.h (gen_movmem_ldrd_strd): New declaration. ++ * config/arm/arm.c (next_consecutive_mem): New function. ++ (gen_movmem_ldrd_strd): Likewise. ++ * config/arm/arm.md (movmemqi): Update condition and code. ++ (unaligned_loaddi, unaligned_storedi): New patterns. ++ ++2013-05-19 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ * LINARO-VERSION: Bump version number. ++ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + Backport from trunk r198677. @@ -1313,6 +1801,19 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "stlex" 4 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr19599.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr19599.c +@@ -0,0 +1,10 @@ ++/* { dg-skip-if "need at least armv5te" { *-*-* } { "-march=armv[234]*" } { "" } } */ ++/* { dg-options "-O2 -march=armv5te -marm" } */ ++/* { dg-final { scan-assembler "bx" } } */ ++ ++int (*indirect_func)(); ++ ++int indirect_call() ++{ ++ return indirect_func(); ++} --- a/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c +++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c @@ -0,0 +1,10 @@ @@ -1539,6 +2040,20 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +/* { dg-final {scan-assembler-times "vorr" 0} } */ +/* { dg-final {scan-assembler-times "veor" 0} } */ +/* { dg-final {scan-assembler-times "vshr" 0} } */ +--- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c +@@ -14,7 +14,10 @@ + /* Expect a multi-word store for the main part of the copy, but subword + loads/stores for the remainder. */ + +-/* { dg-final { scan-assembler-times "stmia" 1 } } */ ++/* { dg-final { scan-assembler-times "ldmia" 0 } } */ ++/* { dg-final { scan-assembler-times "ldrd" 0 } } */ ++/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ ++/* { dg-final { scan-assembler-times "strd" 1 { target { arm_prefer_ldrd_strd } } } } */ + /* { dg-final { scan-assembler-times "ldrh" 1 } } */ + /* { dg-final { scan-assembler-times "strh" 1 } } */ + /* { dg-final { scan-assembler-times "ldrb" 1 } } */ --- a/src/gcc/testsuite/gcc.target/arm/negdi-3.c +++ b/src/gcc/testsuite/gcc.target/arm/negdi-3.c @@ -0,0 +1,17 @@ @@ -1731,6 +2246,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +} + +/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c ++++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c +@@ -14,8 +14,11 @@ + /* Expect a multi-word load for the main part of the copy, but subword + loads/stores for the remainder. */ + +-/* { dg-final { scan-assembler-times "ldmia" 1 } } */ +-/* { dg-final { scan-assembler-times "ldrh" 1 } } */ ++/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ ++/* { dg-final { scan-assembler-times "ldrd" 1 { target { arm_prefer_ldrd_strd } } } } */ ++/* { dg-final { scan-assembler-times "strd" 0 } } */ ++/* { dg-final { scan-assembler-times "stm" 0 } } */ ++/* { dg-final { scan-assembler-times "ldrh" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ + /* { dg-final { scan-assembler-times "strh" 1 } } */ +-/* { dg-final { scan-assembler-times "ldrb" 1 } } */ ++/* { dg-final { scan-assembler-times "ldrb" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ + /* { dg-final { scan-assembler-times "strb" 1 } } */ --- a/src/gcc/testsuite/gcc.target/arm/anddi3-opt2.c +++ b/src/gcc/testsuite/gcc.target/arm/anddi3-opt2.c @@ -0,0 +1,9 @@ @@ -1778,6 +2310,20 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +} + +/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c ++++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c +@@ -14,5 +14,9 @@ + + /* We know both src and dest to be aligned: expect multiword loads/stores. */ + +-/* { dg-final { scan-assembler-times "ldmia" 1 } } */ +-/* { dg-final { scan-assembler-times "stmia" 1 } } */ ++/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ ++/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ ++/* { dg-final { scan-assembler "ldrd" { target { arm_prefer_ldrd_strd } } } } */ ++/* { dg-final { scan-assembler-times "ldm" 0 { target { arm_prefer_ldrd_strd } } } } */ ++/* { dg-final { scan-assembler "strd" { target { arm_prefer_ldrd_strd } } } } */ ++/* { dg-final { scan-assembler-times "stm" 0 { target { arm_prefer_ldrd_strd } } } } */ --- a/src/gcc/testsuite/gcc.target/arm/vseleqdf.c +++ b/src/gcc/testsuite/gcc.target/arm/vseleqdf.c @@ -0,0 +1,13 @@ @@ -1849,6 +2395,20 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr40887.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr40887.c +@@ -2,9 +2,9 @@ + /* { dg-options "-O2 -march=armv5te" } */ + /* { dg-final { scan-assembler "blx" } } */ + +-int (*indirect_func)(); ++int (*indirect_func)(int x); + + int indirect_call() + { +- return indirect_func(); ++ return indirect_func(20) + indirect_func (40); + } --- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c +++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c @@ -0,0 +1,18 @@ @@ -2211,6 +2771,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +/* { dg-final { scan-assembler "saba" } } */ /* { dg-final { scan-assembler-times "addv" 2} } */ /* { dg-final { scan-assembler-times "addp" 2} } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE double ++#define ITYPE long + #define OP == + #define INV_OP != + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ + /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/adds3.c +++ b/src/gcc/testsuite/gcc.target/aarch64/adds3.c @@ -0,0 +1,61 @@ @@ -2433,6 +3010,126 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +} + +/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c +@@ -0,0 +1,117 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps -ffast-math" } */ ++ ++#include <arm_neon.h> ++ ++extern void abort (void); ++ ++#define NUM_TESTS 16 ++#define DELTA 0.000001 ++ ++int8_t input_int8[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++int16_t input_int16[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++int32_t input_int32[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++ ++uint8_t input_uint8[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; ++uint16_t input_uint16[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; ++uint32_t input_uint32[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; ++ ++#define EQUAL(a, b) (a == b) ++ ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES) \ ++int \ ++test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void) \ ++{ \ ++ int i, j; \ ++ int moves = (NUM_TESTS - LANES) + 1; \ ++ TYPE##_t out_l[NUM_TESTS]; \ ++ TYPE##_t out_v[NUM_TESTS]; \ ++ \ ++ /* Calculate linearly. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ out_l[i] = input_##TYPE[i]; \ ++ for (j = 0; j < LANES; j++) \ ++ out_l[i] = input_##TYPE[i + j] CMP_OP out_l[i] ? \ ++ input_##TYPE[i + j] : out_l[i]; \ ++ } \ ++ \ ++ /* Calculate using vector reduction intrinsics. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ ++ out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1); \ ++ } \ ++ \ ++ /* Compare. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ if (!EQUAL (out_v[i], out_l[i])) \ ++ return 0; \ ++ } \ ++ return 1; \ ++} ++ ++#define BUILD_VARIANTS(TYPE, STYPE, W32, W64) \ ++TEST (max, >, STYPE, , TYPE, W32) \ ++TEST (max, >, STYPE, q, TYPE, W64) \ ++TEST (min, <, STYPE, , TYPE, W32) \ ++TEST (min, <, STYPE, q, TYPE, W64) ++ ++BUILD_VARIANTS (int8, s8, 8, 16) ++/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++BUILD_VARIANTS (uint8, u8, 8, 16) ++/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++BUILD_VARIANTS (int16, s16, 4, 8) ++/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++BUILD_VARIANTS (uint16, u16, 4, 8) ++/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++BUILD_VARIANTS (int32, s32, 2, 4) ++/* { dg-final { scan-assembler "smaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "sminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "smaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "sminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++BUILD_VARIANTS (uint32, u32, 2, 4) ++/* { dg-final { scan-assembler "umaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "uminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "umaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "uminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++ ++#undef TEST ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES) \ ++{ \ ++ if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ()) \ ++ abort (); \ ++} ++ ++int ++main (int argc, char **argv) ++{ ++ BUILD_VARIANTS (int8, s8, 8, 16) ++ BUILD_VARIANTS (uint8, u8, 8, 16) ++ BUILD_VARIANTS (int16, s16, 4, 8) ++ BUILD_VARIANTS (uint16, u16, 4, 8) ++ BUILD_VARIANTS (int32, s32, 2, 4) ++ BUILD_VARIANTS (uint32, u32, 2, 4) ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/vrecpx.c +++ b/src/gcc/testsuite/gcc.target/aarch64/vrecpx.c @@ -0,0 +1,54 @@ @@ -2749,6 +3446,88 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ - /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm.x +@@ -13,6 +13,8 @@ + 2.0, -4.0, 8.0, -16.0, + -2.125, 4.25, -8.5, 17.0}; + ++/* Float comparisons, float results. */ ++ + void + foo (FTYPE *in1, FTYPE *in2, FTYPE *output) + { +@@ -49,11 +51,52 @@ + output[i] = (in1[i] INV_OP 0.0) ? 4.0 : 2.0; + } + ++/* Float comparisons, int results. */ ++ ++void ++foo_int (FTYPE *in1, FTYPE *in2, ITYPE *output) ++{ ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = (in1[i] OP in2[i]) ? 2 : 4; ++} ++ ++void ++bar_int (FTYPE *in1, FTYPE *in2, ITYPE *output) ++{ ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = (in1[i] INV_OP in2[i]) ? 4 : 2; ++} ++ ++void ++foobar_int (FTYPE *in1, FTYPE *in2, ITYPE *output) ++{ ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = (in1[i] OP 0.0) ? 4 : 2; ++} ++ ++void ++foobarbar_int (FTYPE *in1, FTYPE *in2, ITYPE *output) ++{ ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = (in1[i] INV_OP 0.0) ? 4 : 2; ++} ++ + int + main (int argc, char **argv) + { + FTYPE out1[N]; + FTYPE out2[N]; ++ ITYPE outi1[N]; ++ ITYPE outi2[N]; ++ + int i = 0; + foo (input1, input2, out1); + bar (input1, input2, out2); +@@ -65,6 +108,17 @@ + for (i = 0; i < N; i++) + if (out1[i] == out2[i]) + abort (); ++ ++ foo_int (input1, input2, outi1); ++ bar_int (input1, input2, outi2); ++ for (i = 0; i < N; i++) ++ if (outi1[i] != outi2[i]) ++ abort (); ++ foobar_int (input1, input2, outi1); ++ foobarbar_int (input1, input2, outi2); ++ for (i = 0; i < N; i++) ++ if (outi1[i] == outi2[i]) ++ abort (); + return 0; + } + --- a/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c +++ b/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c @@ -0,0 +1,11 @@ @@ -2763,6 +3542,22 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+"} } */ +/* { dg-final { scan-assembler-times "faddp\\tv\[0-9\]+\.4s" 2} } */ +/* { dg-final { scan-assembler "faddp\\td\[0-9\]+"} } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/movi_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/movi_1.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++void ++dummy (short* b) ++{ ++ /* { dg-final { scan-assembler "movi\tv\[0-9\]+\.4h, 0x4, lsl 8" } } */ ++ /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 0x400" } } */ ++ /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 1024" } } */ ++ register short x asm ("h8") = 1024; ++ asm volatile ("" : : "w" (x)); ++ *b = x; ++} --- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x +++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x @@ -0,0 +1,37 @@ @@ -2835,6 +3630,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + char buf[256]; + buf[256 - 1] = '\0'; +} +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE double ++#define ITYPE long + #define OP >= + #define INV_OP < + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ + /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ + /* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c +++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c @@ -1,43 +1,7 @@ @@ -2947,6 +3759,61 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + for (i = 0; i < 16; i++) + c[i] += abs (a[i] - b[i]); +} +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c +@@ -0,0 +1,35 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 -save-temps -fno-inline" } */ ++ ++extern void abort (); ++ ++void ++count_lz_v4si (unsigned *__restrict a, int *__restrict b) ++{ ++ int i; ++ ++ for (i = 0; i < 4; i++) ++ b[i] = __builtin_clz (a[i]); ++} ++ ++/* { dg-final { scan-assembler "clz\tv\[0-9\]+\.4s" } } */ ++ ++int ++main () ++{ ++ unsigned int x[4] = { 0x0, 0xFFFF, 0x1FFFF, 0xFFFFFFFF }; ++ int r[4] = { 32, 16, 15, 0 }; ++ int d[4], i; ++ ++ count_lz_v4si (x, d); ++ ++ for (i = 0; i < 4; i++) ++ { ++ if (d[i] != r[i]) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE float ++#define ITYPE int + #define OP > + #define INV_OP <= + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ + /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ + /* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/subs3.c +++ b/src/gcc/testsuite/gcc.target/aarch64/subs3.c @@ -0,0 +1,61 @@ @@ -3175,7 +4042,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +#include <arm_neon.h> +/* Used to force a variable to a SIMD register. */ -+#define force_simd(V1) asm volatile ("mov %d0, %d1" \ ++#define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \ + : "=w"(V1) \ + : "w"(V1) \ + : /* No clobbers */); @@ -3346,6 +4213,28 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ } /* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */ +@@ -160,18 +223,18 @@ + return vdups_lane_u32 (a, 2); + } + +-/* { dg-final { scan-assembler-times "\\tdup\\td\[0-9\]+, v\[0-9\]+\.d" 2 } } */ ++/* { dg-final { scan-assembler-times "\\tumov\\tx\[0-9\]+, v\[0-9\]+\.d" 2 } } */ + + int64x1_t + test_vdupd_lane_s64 (int64x2_t a) + { +- return vdupd_lane_s64 (a, 2); ++ return vdupd_lane_s64 (a, 1); + } + + uint64x1_t + test_vdupd_lane_u64 (uint64x2_t a) + { +- return vdupd_lane_u64 (a, 2); ++ return vdupd_lane_u64 (a, 1); + } + + /* { dg-final { scan-assembler-times "\\tcmtst\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ @@ -179,13 +242,23 @@ int64x1_t test_vtst_s64 (int64x1_t a, int64x1_t b) @@ -3667,6 +4556,137 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ - /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c +@@ -0,0 +1,128 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps -ffast-math" } */ ++ ++#include <arm_neon.h> ++ ++extern void abort (void); ++extern float fabsf (float); ++extern double fabs (double); ++ ++#define NUM_TESTS 16 ++#define DELTA 0.000001 ++ ++int8_t input_int8[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++int16_t input_int16[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++int32_t input_int32[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++int64_t input_int64[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++ ++uint8_t input_uint8[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; ++uint16_t input_uint16[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; ++uint32_t input_uint32[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; ++ ++uint64_t input_uint64[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; ++ ++float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f, ++ 200.0f, -800.0f, -13.0f, -0.5f, ++ 7.9f, -870.0f, 10.4f, 310.11f, ++ 0.0f, -865.0f, -2213.0f, -1.5f}; ++ ++double input_float64[] = {0.1, -0.1, 0.4, 10.3, ++ 200.0, -800.0, -13.0, -0.5, ++ 7.9, -870.0, 10.4, 310.11, ++ 0.0, -865.0, -2213.0, -1.5}; ++ ++#define EQUALF(a, b) (fabsf (a - b) < DELTA) ++#define EQUALD(a, b) (fabs (a - b) < DELTA) ++#define EQUALL(a, b) (a == b) ++ ++#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT) \ ++int \ ++test_vaddv##SUFFIX##_##TYPE##x##LANES##_t (void) \ ++{ \ ++ int i, j; \ ++ int moves = (NUM_TESTS - LANES) + 1; \ ++ TYPE##_t out_l[NUM_TESTS]; \ ++ TYPE##_t out_v[NUM_TESTS]; \ ++ \ ++ /* Calculate linearly. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ out_l[i] = input_##TYPE[i]; \ ++ for (j = 1; j < LANES; j++) \ ++ out_l[i] += input_##TYPE[i + j]; \ ++ } \ ++ \ ++ /* Calculate using vector reduction intrinsics. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ ++ out_v[i] = vaddv##Q##_##SUFFIX (t1); \ ++ } \ ++ \ ++ /* Compare. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ if (!EQUAL##FLOAT (out_v[i], out_l[i])) \ ++ return 0; \ ++ } \ ++ return 1; \ ++} ++ ++#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F) \ ++TEST (STYPE, , TYPE, W32, F) \ ++TEST (STYPE, q, TYPE, W64, F) \ ++ ++BUILD_VARIANTS (int8, s8, 8, 16, L) ++BUILD_VARIANTS (uint8, u8, 8, 16, L) ++/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++BUILD_VARIANTS (int16, s16, 4, 8, L) ++BUILD_VARIANTS (uint16, u16, 4, 8, L) ++/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++BUILD_VARIANTS (int32, s32, 2, 4, L) ++BUILD_VARIANTS (uint32, u32, 2, 4, L) ++/* { dg-final { scan-assembler "addp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "addv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++TEST (s64, q, int64, 2, D) ++TEST (u64, q, uint64, 2, D) ++/* { dg-final { scan-assembler "addp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */ ++ ++BUILD_VARIANTS (float32, f32, 2, 4, F) ++/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "faddp\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++TEST (f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "faddp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */ ++ ++#undef TEST ++#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT) \ ++{ \ ++ if (!test_vaddv##SUFFIX##_##TYPE##x##LANES##_t ()) \ ++ abort (); \ ++} ++ ++int ++main (int argc, char **argv) ++{ ++BUILD_VARIANTS (int8, s8, 8, 16, L) ++BUILD_VARIANTS (uint8, u8, 8, 16, L) ++BUILD_VARIANTS (int16, s16, 4, 8, L) ++BUILD_VARIANTS (uint16, u16, 4, 8, L) ++BUILD_VARIANTS (int32, s32, 2, 4, L) ++BUILD_VARIANTS (uint32, u32, 2, 4, L) ++ ++BUILD_VARIANTS (float32, f32, 2, 4, F) ++TEST (f64, q, float64, 2, D) ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c +++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c @@ -1,43 +1,7 @@ @@ -3928,6 +4948,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* { dg-final { scan-assembler "fneg\\tv" } } */ /* { dg-final { scan-assembler "fabs\\tv" } } */ +/* { dg-final { scan-assembler "fabd\\tv" } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE float ++#define ITYPE int + #define OP == + #define INV_OP != + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ + /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/adds1.c +++ b/src/gcc/testsuite/gcc.target/aarch64/adds1.c @@ -0,0 +1,149 @@ @@ -4080,6 +5117,93 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +} + +/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/insv_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/insv_1.c +@@ -0,0 +1,84 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++ ++extern void abort (void); ++ ++typedef struct bitfield ++{ ++ unsigned short eight: 8; ++ unsigned short four: 4; ++ unsigned short five: 5; ++ unsigned short seven: 7; ++ unsigned int sixteen: 16; ++} bitfield; ++ ++bitfield ++bfi1 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 0, 8" } } */ ++ a.eight = 3; ++ return a; ++} ++ ++bitfield ++bfi2 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 16, 5" } } */ ++ a.five = 7; ++ return a; ++} ++ ++bitfield ++movk (bitfield a) ++{ ++ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 32" } } */ ++ a.sixteen = 7531; ++ return a; ++} ++ ++bitfield ++set1 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 2031616" } } */ ++ a.five = 0x1f; ++ return a; ++} ++ ++bitfield ++set0 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -2031617" } } */ ++ a.five = 0; ++ return a; ++} ++ ++ ++int ++main (int argc, char** argv) ++{ ++ static bitfield a; ++ bitfield b = bfi1 (a); ++ bitfield c = bfi2 (b); ++ bitfield d = movk (c); ++ ++ if (d.eight != 3) ++ abort (); ++ ++ if (d.five != 7) ++ abort (); ++ ++ if (d.sixteen != 7531) ++ abort (); ++ ++ d = set1 (d); ++ if (d.five != 0x1f) ++ abort (); ++ ++ d = set0 (d); ++ if (d.five != 0) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/ror.c +++ b/src/gcc/testsuite/gcc.target/aarch64/ror.c @@ -0,0 +1,34 @@ @@ -4164,6 +5288,178 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ - /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c +@@ -0,0 +1,169 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps -ffast-math" } */ ++ ++#include <arm_neon.h> ++ ++extern void abort (void); ++ ++extern float fabsf (float); ++extern double fabs (double); ++extern int isnan (double); ++extern float fmaxf (float, float); ++extern float fminf (float, float); ++extern double fmax (double, double); ++extern double fmin (double, double); ++ ++#define NUM_TESTS 16 ++#define DELTA 0.000001 ++#define NAN (0.0 / 0.0) ++ ++float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f, ++ 200.0f, -800.0f, -13.0f, -0.5f, ++ NAN, -870.0f, 10.4f, 310.11f, ++ 0.0f, -865.0f, -2213.0f, -1.5f}; ++ ++double input_float64[] = {0.1, -0.1, 0.4, 10.3, ++ 200.0, -800.0, -13.0, -0.5, ++ NAN, -870.0, 10.4, 310.11, ++ 0.0, -865.0, -2213.0, -1.5}; ++ ++#define EQUALF(a, b) (fabsf (a - b) < DELTA) ++#define EQUALD(a, b) (fabs (a - b) < DELTA) ++ ++/* Floating point 'unordered' variants. */ ++ ++#undef TEST ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \ ++int \ ++test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void) \ ++{ \ ++ int i, j; \ ++ int moves = (NUM_TESTS - LANES) + 1; \ ++ TYPE##_t out_l[NUM_TESTS]; \ ++ TYPE##_t out_v[NUM_TESTS]; \ ++ \ ++ /* Calculate linearly. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ out_l[i] = input_##TYPE[i]; \ ++ for (j = 0; j < LANES; j++) \ ++ { \ ++ if (isnan (out_l[i])) \ ++ continue; \ ++ if (isnan (input_##TYPE[i + j]) \ ++ || input_##TYPE[i + j] CMP_OP out_l[i]) \ ++ out_l[i] = input_##TYPE[i + j]; \ ++ } \ ++ } \ ++ \ ++ /* Calculate using vector reduction intrinsics. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ ++ out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1); \ ++ } \ ++ \ ++ /* Compare. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ if (!EQUAL##FLOAT (out_v[i], out_l[i]) \ ++ && !(isnan (out_v[i]) && isnan (out_l[i]))) \ ++ return 0; \ ++ } \ ++ return 1; \ ++} ++ ++#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F) \ ++TEST (max, >, STYPE, , TYPE, W32, F) \ ++TEST (max, >, STYPE, q, TYPE, W64, F) \ ++TEST (min, <, STYPE, , TYPE, W32, F) \ ++TEST (min, <, STYPE, q, TYPE, W64, F) ++ ++BUILD_VARIANTS (float32, f32, 2, 4, F) ++/* { dg-final { scan-assembler "fmaxp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fminp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fmaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++TEST (max, >, f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "fmaxp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ ++TEST (min, <, f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "fminp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ ++ ++/* Floating point 'nm' variants. */ ++ ++#undef TEST ++#define TEST(MAXMIN, F, SUFFIX, Q, TYPE, LANES, FLOAT) \ ++int \ ++test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t (void) \ ++{ \ ++ int i, j; \ ++ int moves = (NUM_TESTS - LANES) + 1; \ ++ TYPE##_t out_l[NUM_TESTS]; \ ++ TYPE##_t out_v[NUM_TESTS]; \ ++ \ ++ /* Calculate linearly. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ out_l[i] = input_##TYPE[i]; \ ++ for (j = 0; j < LANES; j++) \ ++ out_l[i] = f##MAXMIN##F (input_##TYPE[i + j], out_l[i]); \ ++ } \ ++ \ ++ /* Calculate using vector reduction intrinsics. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ ++ out_v[i] = v##MAXMIN##nmv##Q##_##SUFFIX (t1); \ ++ } \ ++ \ ++ /* Compare. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ if (!EQUAL##FLOAT (out_v[i], out_l[i])) \ ++ return 0; \ ++ } \ ++ return 1; \ ++} ++ ++TEST (max, f, f32, , float32, 2, D) ++/* { dg-final { scan-assembler "fmaxnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++TEST (min, f, f32, , float32, 2, D) ++/* { dg-final { scan-assembler "fminnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++TEST (max, f, f32, q, float32, 4, D) ++/* { dg-final { scan-assembler "fmaxnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++TEST (min, f, f32, q, float32, 4, D) ++/* { dg-final { scan-assembler "fminnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++TEST (max, , f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "fmaxnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ ++TEST (min, , f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "fminnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ ++ ++#undef TEST ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \ ++{ \ ++ if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ()) \ ++ abort (); \ ++} ++ ++int ++main (int argc, char **argv) ++{ ++ BUILD_VARIANTS (float32, f32, 2, 4, F) ++ TEST (max, >, f64, q, float64, 2, D) ++ TEST (min, <, f64, q, float64, 2, D) ++ ++#undef TEST ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \ ++{ \ ++ if (!test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t ()) \ ++ abort (); \ ++} ++ ++ BUILD_VARIANTS (float32, f32, 2, 4, F) ++ TEST (max, >, f64, q, float64, 2, D) ++ TEST (min, <, f64, q, float64, 2, D) ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x +++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x @@ -0,0 +1,37 @@ @@ -4580,6 +5876,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + +/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE float ++#define ITYPE int + #define OP >= + #define INV_OP < + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ + /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ + /* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x +++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x @@ -7,13 +7,23 @@ @@ -4987,6 +6300,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ +} + +/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE double ++#define ITYPE long + #define OP > + #define INV_OP <= + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ + /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ + /* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ --- a/src/gcc/testsuite/lib/target-supports.exp +++ b/src/gcc/testsuite/lib/target-supports.exp @@ -2012,6 +2012,7 @@ @@ -5137,7 +6467,91 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ proc check_effective_target_arm_neon { } { --- a/src/gcc/testsuite/ChangeLog.linaro +++ b/src/gcc/testsuite/ChangeLog.linaro -@@ -0,0 +1,290 @@ +@@ -0,0 +1,374 @@ ++2013-06-05 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r199658. ++ 2013-06-04 Ian Bolton <ian.bolton@arm.com> ++ ++ * gcc.target/aarch64/movi_1.c: New test. ++ ++2013-06-04 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r199261. ++ 2013-05-23 Christian Bruel <christian.bruel@st.com> ++ ++ PR debug/57351 ++ * gcc.dg/debug/pr57351.c: New test ++ ++2013-06-03 Christophe Lyon <christophe.lyon@linaro.org> ++ Backport from trunk r198890,199254,199294,199454. ++ ++ 2013-05-30 Ian Bolton <ian.bolton@arm.com> ++ ++ * gcc.target/aarch64/insv_1.c: New test. ++ ++ 2013-05-24 Ian Bolton <ian.bolton@arm.com> ++ ++ * gcc.target/aarch64/scalar_intrinsics.c ++ (force_simd): Use a valid instruction. ++ (test_vdupd_lane_s64): Pass a valid lane argument. ++ (test_vdupd_lane_u64): Likewise. ++ ++ 2013-05-23 Vidya Praveen <vidyapraveen@arm.com> ++ ++ * gcc.target/aarch64/vect-clz.c: New file. ++ ++ 2013-05-14 James Greenhalgh <james.greenhalgh@arm.com> ++ ++ * gcc.target/aarch64/vect-fcm.x: Add cases testing ++ FLOAT cmp FLOAT ? INT : INT. ++ * gcc.target/aarch64/vect-fcm-eq-d.c: Define IMODE. ++ * gcc.target/aarch64/vect-fcm-eq-f.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-ge-d.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-ge-f.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-gt-d.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-gt-f.c: Likewise. ++ ++2013-05-29 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198928. ++ 2013-05-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> ++ ++ PR target/19599 ++ * gcc.target/arm/pr40887.c: Adjust testcase. ++ * gcc.target/arm/pr19599.c: New test. ++ ++2013-05-28 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198680. ++ 2013-05-07 Sofiane Naci <sofiane.naci@arm.com> ++ ++ * gcc.target/aarch64/scalar_intrinsics.c: Update. ++ ++2013-05-28 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198499-198500. ++ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com> ++ * gcc.target/aarch64/vect-vaddv.c: New. ++ ++ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com> ++ ++ * gcc.target/aarch64/vect-vmaxv.c: New. ++ * gcc.target/aarch64/vect-vfmaxv.c: Likewise. ++ ++2013-05-23 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198970. ++ 2013-05-16 Greta Yorsh <Greta.Yorsh@arm.com> ++ ++ * gcc.target/arm/unaligned-memcpy-2.c: Adjust expected output. ++ * gcc.target/arm/unaligned-memcpy-3.c: Likewise. ++ * gcc.target/arm/unaligned-memcpy-4.c: Likewise. ++ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + Backport from trunk r198574-198575. @@ -5428,27 +6842,184 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + * gcc.target/aarch64/vect-fp-compile.c: Check for fabd + instruction in assembly. + * gcc.target/aarch64/vect-fp.x: Add fabd test function. +--- a/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c ++++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -g" } */ ++ ++extern int * alloca (int); ++ ++int *p; ++ ++void ++test (int a) ++{ ++ if (a > 0) ++ p = alloca (4); ++} +--- a/src/gcc/testsuite/gcc.dg/shrink-wrap-pretend.c ++++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-pretend.c +@@ -0,0 +1,36 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -g" } */ ++ ++#include <stdlib.h> ++#include <stdio.h> ++#include <stdarg.h> ++ ++#define DEBUG_BUFFER_SIZE 80 ++int unifi_debug = 5; ++ ++void ++unifi_trace (void* ospriv, int level, const char *fmt, ...) ++{ ++ static char s[DEBUG_BUFFER_SIZE]; ++ va_list args; ++ unsigned int len; ++ ++ if (!ospriv) ++ return; ++ ++ if (unifi_debug >= level) ++ { ++ va_start (args, fmt); ++ len = vsnprintf (&(s)[0], (DEBUG_BUFFER_SIZE), fmt, args); ++ va_end (args); ++ ++ if (len >= DEBUG_BUFFER_SIZE) ++ { ++ (s)[DEBUG_BUFFER_SIZE - 2] = '\n'; ++ (s)[DEBUG_BUFFER_SIZE - 1] = 0; ++ } ++ ++ printf ("%s", s); ++ } ++} ++ +--- a/src/gcc/testsuite/gcc.dg/debug/pr57351.c ++++ b/src/gcc/testsuite/gcc.dg/debug/pr57351.c +@@ -0,0 +1,54 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon } */ ++/* { dg-options "-std=c99 -Os -g -march=armv7-a" } */ ++/* { dg-add-options arm_neon } */ ++ ++typedef unsigned int size_t; ++typedef int ptrdiff_t; ++typedef signed char int8_t ; ++typedef signed long long int64_t; ++typedef int8_t GFC_INTEGER_1; ++typedef GFC_INTEGER_1 GFC_LOGICAL_1; ++typedef int64_t GFC_INTEGER_8; ++typedef GFC_INTEGER_8 GFC_LOGICAL_8; ++typedef ptrdiff_t index_type; ++typedef struct descriptor_dimension ++{ ++ index_type lower_bound; ++ index_type _ubound; ++} ++descriptor_dimension; ++typedef struct { GFC_LOGICAL_1 *base_addr; size_t offset; index_type dtype; descriptor_dimension dim[7];} gfc_array_l1; ++typedef struct { GFC_LOGICAL_8 *base_addr; size_t offset; index_type dtype; descriptor_dimension dim[7];} gfc_array_l8; ++void ++all_l8 (gfc_array_l8 * const restrict retarray, ++ gfc_array_l1 * const restrict array, ++ const index_type * const restrict pdim) ++{ ++ GFC_LOGICAL_8 * restrict dest; ++ index_type n; ++ index_type len; ++ index_type delta; ++ index_type dim; ++ dim = (*pdim) - 1; ++ len = ((array)->dim[dim]._ubound + 1 - (array)->dim[dim].lower_bound); ++ for (n = 0; n < dim; n++) ++ { ++ const GFC_LOGICAL_1 * restrict src; ++ GFC_LOGICAL_8 result; ++ { ++ result = 1; ++ { ++ for (n = 0; n < len; n++, src += delta) ++ { ++ if (! *src) ++ { ++ result = 0; ++ break; ++ } ++ } ++ *dest = result; ++ } ++ } ++ } ++} +--- a/src/gcc/testsuite/gcc.dg/shrink-wrap-sibcall.c ++++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-sibcall.c +@@ -0,0 +1,26 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -g" } */ ++ ++unsigned char a, b, d, f, g; ++ ++int test (void); ++ ++int ++baz (int c) ++{ ++ if (c == 0) return test (); ++ if (b & 1) ++ { ++ g = 0; ++ int e = (a & 0x0f) - (g & 0x0f); ++ ++ if (!a) b |= 0x80; ++ a = e + test (); ++ f = g/5 + a*3879 + b *2985; ++ } ++ else ++ { ++ f = g + a*39879 + b *25; ++ } ++ return test (); ++} --- a/src/gcc/objcp/ChangeLog.linaro +++ b/src/gcc/objcp/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/cp/ChangeLog.linaro +++ b/src/gcc/cp/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/go/ChangeLog.linaro +++ b/src/gcc/go/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/ada/ChangeLog.linaro +++ b/src/gcc/ada/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. @@ -5465,7 +7036,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ --- a/src/gcc/fortran/ChangeLog.linaro +++ b/src/gcc/fortran/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. @@ -5504,13 +7079,21 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ return changed; --- a/src/gcc/lto/ChangeLog.linaro +++ b/src/gcc/lto/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/po/ChangeLog.linaro +++ b/src/gcc/po/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. @@ -5600,7 +7183,170 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (eq_attr "simd_type" "none") (const_string "none") ] (const_string "unknown"))) -@@ -503,8 +505,8 @@ +@@ -356,7 +358,7 @@ + ) + + (define_insn "aarch64_dup_lane<mode>" +- [(set (match_operand:SDQ_I 0 "register_operand" "=w") ++ [(set (match_operand:ALLX 0 "register_operand" "=w") + (vec_select:<VEL> + (match_operand:<VCON> 1 "register_operand" "w") + (parallel [(match_operand:SI 2 "immediate_operand" "i")]) +@@ -367,6 +369,19 @@ + (set_attr "simd_mode" "<MODE>")] + ) + ++(define_insn "aarch64_dup_lanedi" ++ [(set (match_operand:DI 0 "register_operand" "=w,r") ++ (vec_select:DI ++ (match_operand:V2DI 1 "register_operand" "w,w") ++ (parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))] ++ "TARGET_SIMD" ++ "@ ++ dup\\t%<v>0<Vmtype>, %1.<Vetype>[%2] ++ umov\t%0, %1.d[%2]" ++ [(set_attr "simd_type" "simd_dup") ++ (set_attr "simd_mode" "DI")] ++) ++ + (define_insn "aarch64_simd_dup<mode>" + [(set (match_operand:VDQF 0 "register_operand" "=w") + (vec_duplicate:VDQF (match_operand:<VEL> 1 "register_operand" "w")))] +@@ -394,7 +409,7 @@ + case 4: return "ins\t%0.d[0], %1"; + case 5: return "mov\t%0, %1"; + case 6: +- return aarch64_output_simd_mov_immediate (&operands[1], ++ return aarch64_output_simd_mov_immediate (operands[1], + <MODE>mode, 64); + default: gcc_unreachable (); + } +@@ -417,13 +432,13 @@ + case 0: return "ld1\t{%0.<Vtype>}, %1"; + case 1: return "st1\t{%1.<Vtype>}, %0"; + case 2: return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>"; +- case 3: return "umov\t%0, %1.d[0]\;umov\t%H0, %1.d[1]"; +- case 4: return "ins\t%0.d[0], %1\;ins\t%0.d[1], %H1"; ++ case 3: return "#"; ++ case 4: return "#"; + case 5: return "#"; + case 6: +- return aarch64_output_simd_mov_immediate (&operands[1], +- <MODE>mode, 128); +- default: gcc_unreachable (); ++ return aarch64_output_simd_mov_immediate (operands[1], <MODE>mode, 128); ++ default: ++ gcc_unreachable (); + } + } + [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm") +@@ -452,6 +467,105 @@ + aarch64_simd_disambiguate_copy (operands, dest, src, 2); + }) + ++(define_split ++ [(set (match_operand:VQ 0 "register_operand" "") ++ (match_operand:VQ 1 "register_operand" ""))] ++ "TARGET_SIMD && reload_completed ++ && ((FP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))) ++ || (GP_REGNUM_P (REGNO (operands[0])) && FP_REGNUM_P (REGNO (operands[1]))))" ++ [(const_int 0)] ++{ ++ aarch64_split_simd_move (operands[0], operands[1]); ++ DONE; ++}) ++ ++(define_expand "aarch64_simd_mov<mode>" ++ [(set (match_operand:VQ 0) ++ (match_operand:VQ 1))] ++ "TARGET_SIMD" ++ { ++ rtx dst = operands[0]; ++ rtx src = operands[1]; ++ ++ if (GP_REGNUM_P (REGNO (src))) ++ { ++ rtx low_part = gen_lowpart (<VHALF>mode, src); ++ rtx high_part = gen_highpart (<VHALF>mode, src); ++ ++ emit_insn ++ (gen_aarch64_simd_mov_to_<mode>low (dst, low_part)); ++ emit_insn ++ (gen_aarch64_simd_mov_to_<mode>high (dst, high_part)); ++ } ++ ++ else ++ { ++ rtx low_half = aarch64_simd_vect_par_cnst_half (<MODE>mode, false); ++ rtx high_half = aarch64_simd_vect_par_cnst_half (<MODE>mode, true); ++ rtx low_part = gen_lowpart (<VHALF>mode, dst); ++ rtx high_part = gen_highpart (<VHALF>mode, dst); ++ ++ emit_insn ++ (gen_aarch64_simd_mov_from_<mode>low (low_part, src, low_half)); ++ emit_insn ++ (gen_aarch64_simd_mov_from_<mode>high (high_part, src, high_half)); ++ } ++ DONE; ++ } ++) ++ ++(define_insn "aarch64_simd_mov_to_<mode>low" ++ [(set (zero_extract:VQ ++ (match_operand:VQ 0 "register_operand" "+w") ++ (const_int 64) (const_int 0)) ++ (vec_concat:VQ ++ (match_operand:<VHALF> 1 "register_operand" "r") ++ (vec_duplicate:<VHALF> (const_int 0))))] ++ "TARGET_SIMD && reload_completed" ++ "ins\t%0.d[0], %1" ++ [(set_attr "simd_type" "simd_move") ++ (set_attr "simd_mode" "<MODE>") ++ (set_attr "length" "4") ++ ]) ++ ++(define_insn "aarch64_simd_mov_to_<mode>high" ++ [(set (zero_extract:VQ ++ (match_operand:VQ 0 "register_operand" "+w") ++ (const_int 64) (const_int 64)) ++ (vec_concat:VQ ++ (match_operand:<VHALF> 1 "register_operand" "r") ++ (vec_duplicate:<VHALF> (const_int 0))))] ++ "TARGET_SIMD && reload_completed" ++ "ins\t%0.d[1], %1" ++ [(set_attr "simd_type" "simd_move") ++ (set_attr "simd_mode" "<MODE>") ++ (set_attr "length" "4") ++ ]) ++ ++(define_insn "aarch64_simd_mov_from_<mode>low" ++ [(set (match_operand:<VHALF> 0 "register_operand" "=r") ++ (vec_select:<VHALF> ++ (match_operand:VQ 1 "register_operand" "w") ++ (match_operand:VQ 2 "vect_par_cnst_lo_half" "")))] ++ "TARGET_SIMD && reload_completed" ++ "umov\t%0, %1.d[0]" ++ [(set_attr "simd_type" "simd_move") ++ (set_attr "simd_mode" "<MODE>") ++ (set_attr "length" "4") ++ ]) ++ ++(define_insn "aarch64_simd_mov_from_<mode>high" ++ [(set (match_operand:<VHALF> 0 "register_operand" "=r") ++ (vec_select:<VHALF> ++ (match_operand:VQ 1 "register_operand" "w") ++ (match_operand:VQ 2 "vect_par_cnst_hi_half" "")))] ++ "TARGET_SIMD && reload_completed" ++ "umov\t%0, %1.d[1]" ++ [(set_attr "simd_type" "simd_move") ++ (set_attr "simd_mode" "<MODE>") ++ (set_attr "length" "4") ++ ]) ++ + (define_insn "orn<mode>3" + [(set (match_operand:VDQ 0 "register_operand" "=w") + (ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w")) +@@ -503,8 +617,8 @@ ) (define_insn "neg<mode>2" @@ -5611,7 +7357,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ "TARGET_SIMD" "neg\t%0.<Vtype>, %1.<Vtype>" [(set_attr "simd_type" "simd_negabs") -@@ -520,6 +522,51 @@ +@@ -520,6 +634,51 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -5663,7 +7409,22 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "and<mode>3" [(set (match_operand:VDQ 0 "register_operand" "=w") (and:VDQ (match_operand:VDQ 1 "register_operand" "w") -@@ -1196,7 +1243,9 @@ +@@ -904,12 +1063,12 @@ + ) + + ;; Max/Min operations. +-(define_insn "<maxmin><mode>3" ++(define_insn "<su><maxmin><mode>3" + [(set (match_operand:VQ_S 0 "register_operand" "=w") + (MAXMIN:VQ_S (match_operand:VQ_S 1 "register_operand" "w") + (match_operand:VQ_S 2 "register_operand" "w")))] + "TARGET_SIMD" +- "<maxmin>\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>" ++ "<su><maxmin>\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>" + [(set_attr "simd_type" "simd_minmax") + (set_attr "simd_mode" "<MODE>")] + ) +@@ -1196,7 +1355,9 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -5674,7 +7435,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set (match_operand:VDQF 0 "register_operand" "=w") (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")] FRINT))] -@@ -1206,16 +1255,9 @@ +@@ -1206,16 +1367,9 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -5694,7 +7455,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set (match_operand:<FCVT_TARGET> 0 "register_operand" "=w") (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET> [(match_operand:VDQF 1 "register_operand" "w")] -@@ -1226,16 +1268,141 @@ +@@ -1226,16 +1380,141 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -5840,16 +7601,110 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "aarch64_vmls<mode>" [(set (match_operand:VDQF 0 "register_operand" "=w") (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") -@@ -1305,7 +1472,7 @@ +@@ -1261,51 +1540,70 @@ + ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring + ;; NaNs. + +-(define_insn "smax<mode>3" ++(define_insn "<su><maxmin><mode>3" + [(set (match_operand:VDQF 0 "register_operand" "=w") +- (smax:VDQF (match_operand:VDQF 1 "register_operand" "w") ++ (FMAXMIN:VDQF (match_operand:VDQF 1 "register_operand" "w") + (match_operand:VDQF 2 "register_operand" "w")))] + "TARGET_SIMD" +- "fmaxnm\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>" ++ "f<maxmin>nm\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>" + [(set_attr "simd_type" "simd_fminmax") + (set_attr "simd_mode" "<MODE>")] + ) + +-(define_insn "smin<mode>3" ++(define_insn "<maxmin_uns><mode>3" + [(set (match_operand:VDQF 0 "register_operand" "=w") +- (smin:VDQF (match_operand:VDQF 1 "register_operand" "w") +- (match_operand:VDQF 2 "register_operand" "w")))] ++ (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w") ++ (match_operand:VDQF 2 "register_operand" "w")] ++ FMAXMIN_UNS))] + "TARGET_SIMD" +- "fminnm\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>" ++ "<maxmin_uns_op>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>" + [(set_attr "simd_type" "simd_fminmax") + (set_attr "simd_mode" "<MODE>")] + ) + +-;; FP 'across lanes' max and min ops. ++;; 'across lanes' add. + +-(define_insn "reduc_s<fmaxminv>_v4sf" +- [(set (match_operand:V4SF 0 "register_operand" "=w") +- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] +- FMAXMINV))] ++(define_insn "reduc_<sur>plus_<mode>" ++ [(set (match_operand:VDQV 0 "register_operand" "=w") ++ (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] ++ SUADDV))] + "TARGET_SIMD" +- "f<fmaxminv>nmv\\t%s0, %1.4s"; +- [(set_attr "simd_type" "simd_fminmaxv") +- (set_attr "simd_mode" "V4SF")] ++ "addv\\t%<Vetype>0, %1.<Vtype>" ++ [(set_attr "simd_type" "simd_addv") ++ (set_attr "simd_mode" "<MODE>")] + ) - ;; FP 'across lanes' add. +-(define_insn "reduc_s<fmaxminv>_<mode>" ++(define_insn "reduc_<sur>plus_v2di" ++ [(set (match_operand:V2DI 0 "register_operand" "=w") ++ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")] ++ SUADDV))] ++ "TARGET_SIMD" ++ "addp\\t%d0, %1.2d" ++ [(set_attr "simd_type" "simd_addv") ++ (set_attr "simd_mode" "V2DI")] ++) ++ ++(define_insn "reduc_<sur>plus_v2si" ++ [(set (match_operand:V2SI 0 "register_operand" "=w") ++ (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] ++ SUADDV))] ++ "TARGET_SIMD" ++ "addp\\t%0.2s, %1.2s, %1.2s" ++ [(set_attr "simd_type" "simd_addv") ++ (set_attr "simd_mode" "V2SI")] ++) ++ ++(define_insn "reduc_<sur>plus_<mode>" + [(set (match_operand:V2F 0 "register_operand" "=w") + (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] +- FMAXMINV))] ++ SUADDV))] + "TARGET_SIMD" +- "f<fmaxminv>nmp\\t%0.<Vtype>, %1.<Vtype>, %1.<Vtype>"; +- [(set_attr "simd_type" "simd_fminmax") ++ "faddp\\t%<Vetype>0, %1.<Vtype>" ++ [(set_attr "simd_type" "simd_fadd") + (set_attr "simd_mode" "<MODE>")] + ) +-;; FP 'across lanes' add. +- -(define_insn "aarch64_addvv4sf" +(define_insn "aarch64_addpv4sf" [(set (match_operand:V4SF 0 "register_operand" "=w") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] UNSPEC_FADDV))] -@@ -1321,8 +1488,8 @@ +@@ -1315,169 +1613,106 @@ + (set_attr "simd_mode" "V4SF")] + ) + +-(define_expand "reduc_uplus_v4sf" +- [(set (match_operand:V4SF 0 "register_operand" "=w") +- (match_operand:V4SF 1 "register_operand" "w"))] ++(define_expand "reduc_<sur>plus_v4sf" ++ [(set (match_operand:V4SF 0 "register_operand") ++ (unspec:V4SF [(match_operand:V4SF 1 "register_operand")] ++ SUADDV))] "TARGET_SIMD" { rtx tmp = gen_reg_rtx (V4SFmode); @@ -5860,34 +7715,175 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ DONE; }) -@@ -1332,11 +1499,21 @@ +-(define_expand "reduc_splus_v4sf" +- [(set (match_operand:V4SF 0 "register_operand" "=w") +- (match_operand:V4SF 1 "register_operand" "w"))] ++(define_insn "clz<mode>2" ++ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") ++ (clz:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w")))] "TARGET_SIMD" - { - rtx tmp = gen_reg_rtx (V4SFmode); +-{ +- rtx tmp = gen_reg_rtx (V4SFmode); - emit_insn (gen_aarch64_addvv4sf (tmp, operands[1])); - emit_insn (gen_aarch64_addvv4sf (operands[0], tmp)); -+ emit_insn (gen_aarch64_addpv4sf (tmp, operands[1])); -+ emit_insn (gen_aarch64_addpv4sf (operands[0], tmp)); - DONE; - }) +- DONE; +-}) +- +-(define_insn "aarch64_addv<mode>" +- [(set (match_operand:V2F 0 "register_operand" "=w") +- (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] +- UNSPEC_FADDV))] +- "TARGET_SIMD" +- "faddp\\t%<Vetype>0, %1.<Vtype>" +- [(set_attr "simd_type" "simd_fadd") +- (set_attr "simd_mode" "<MODE>")] ++ "clz\\t%0.<Vtype>, %1.<Vtype>" ++ [(set_attr "simd_type" "simd_cls") ++ (set_attr "simd_mode" "<MODE>")] + ) -+(define_expand "aarch64_addvv4sf" -+ [(set (match_operand:V4SF 0 "register_operand" "=w") -+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] -+ UNSPEC_FADDV))] -+ "TARGET_SIMD" -+{ -+ emit_insn (gen_reduc_splus_v4sf (operands[0], operands[1])); -+ DONE; -+}) -+ - (define_insn "aarch64_addv<mode>" - [(set (match_operand:V2F 0 "register_operand" "=w") - (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] -@@ -1463,21 +1640,33 @@ +-(define_expand "reduc_uplus_<mode>" +- [(set (match_operand:V2F 0 "register_operand" "=w") +- (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] +- UNSPEC_FADDV))] +- "TARGET_SIMD" +- "" +-) ++;; 'across lanes' max and min ops. + +-(define_expand "reduc_splus_<mode>" +- [(set (match_operand:V2F 0 "register_operand" "=w") +- (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] +- UNSPEC_FADDV))] +- "TARGET_SIMD" +- "" +-) +- +-;; Reduction across lanes. +- +-(define_insn "aarch64_addv<mode>" ++(define_insn "reduc_<maxmin_uns>_<mode>" + [(set (match_operand:VDQV 0 "register_operand" "=w") + (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] +- UNSPEC_ADDV))] ++ MAXMINV))] + "TARGET_SIMD" +- "addv\\t%<Vetype>0, %1.<Vtype>" +- [(set_attr "simd_type" "simd_addv") ++ "<maxmin_uns_op>v\\t%<Vetype>0, %1.<Vtype>" ++ [(set_attr "simd_type" "simd_minmaxv") + (set_attr "simd_mode" "<MODE>")] + ) + +-(define_expand "reduc_splus_<mode>" +- [(set (match_operand:VDQV 0 "register_operand" "=w") +- (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] +- UNSPEC_ADDV))] +- "TARGET_SIMD" +- "" +-) +- +-(define_expand "reduc_uplus_<mode>" +- [(set (match_operand:VDQV 0 "register_operand" "=w") +- (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] +- UNSPEC_ADDV))] +- "TARGET_SIMD" +- "" +-) +- +-(define_insn "aarch64_addvv2di" ++(define_insn "reduc_<maxmin_uns>_v2di" + [(set (match_operand:V2DI 0 "register_operand" "=w") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")] +- UNSPEC_ADDV))] ++ MAXMINV))] + "TARGET_SIMD" +- "addp\\t%d0, %1.2d" +- [(set_attr "simd_type" "simd_add") ++ "<maxmin_uns_op>p\\t%d0, %1.2d" ++ [(set_attr "simd_type" "simd_minmaxv") + (set_attr "simd_mode" "V2DI")] + ) + +-(define_expand "reduc_uplus_v2di" +- [(set (match_operand:V2DI 0 "register_operand" "=w") +- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")] +- UNSPEC_ADDV))] +- "TARGET_SIMD" +- "" +-) +- +-(define_expand "reduc_splus_v2di" +- [(set (match_operand:V2DI 0 "register_operand" "=w") +- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")] +- UNSPEC_ADDV))] +- "TARGET_SIMD" +- "" +-) +- +-(define_insn "aarch64_addvv2si" ++(define_insn "reduc_<maxmin_uns>_v2si" + [(set (match_operand:V2SI 0 "register_operand" "=w") + (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] +- UNSPEC_ADDV))] ++ MAXMINV))] + "TARGET_SIMD" +- "addp\\t%0.2s, %1.2s, %1.2s" +- [(set_attr "simd_type" "simd_add") ++ "<maxmin_uns_op>p\\t%0.2s, %1.2s, %1.2s" ++ [(set_attr "simd_type" "simd_minmaxv") (set_attr "simd_mode" "V2SI")] ) +-(define_expand "reduc_uplus_v2si" +- [(set (match_operand:V2SI 0 "register_operand" "=w") +- (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] +- UNSPEC_ADDV))] ++(define_insn "reduc_<maxmin_uns>_<mode>" ++ [(set (match_operand:V2F 0 "register_operand" "=w") ++ (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] ++ FMAXMINV))] + "TARGET_SIMD" +- "" +-) +- +-(define_expand "reduc_splus_v2si" +- [(set (match_operand:V2SI 0 "register_operand" "=w") +- (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] +- UNSPEC_ADDV))] +- "TARGET_SIMD" +- "" +-) +- +-(define_insn "reduc_<maxminv>_<mode>" +- [(set (match_operand:VDQV 0 "register_operand" "=w") +- (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] +- MAXMINV))] +- "TARGET_SIMD" +- "<maxminv>v\\t%<Vetype>0, %1.<Vtype>" +- [(set_attr "simd_type" "simd_minmaxv") ++ "<maxmin_uns_op>p\\t%<Vetype>0, %1.<Vtype>" ++ [(set_attr "simd_type" "simd_fminmaxv") + (set_attr "simd_mode" "<MODE>")] + ) + +-(define_insn "reduc_<maxminv>_v2si" +- [(set (match_operand:V2SI 0 "register_operand" "=w") +- (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] +- MAXMINV))] ++(define_insn "reduc_<maxmin_uns>_v4sf" ++ [(set (match_operand:V4SF 0 "register_operand" "=w") ++ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] ++ FMAXMINV))] + "TARGET_SIMD" +- "<maxminv>p\\t%0.2s, %1.2s, %1.2s" +- [(set_attr "simd_type" "simd_minmax") +- (set_attr "simd_mode" "V2SI")] ++ "<maxmin_uns_op>v\\t%s0, %1.4s" ++ [(set_attr "simd_type" "simd_fminmaxv") ++ (set_attr "simd_mode" "V4SF")] + ) + -;; vbsl_* intrinsics may compile to any of bsl/bif/bit depending on register -;; allocation. For an intrinsic of form: -;; vD = bsl_* (vS, vN, vM) @@ -5929,7 +7925,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ "TARGET_SIMD" "@ bsl\\t%0.<Vbtype>, %2.<Vbtype>, %3.<Vbtype> -@@ -1486,15 +1675,17 @@ +@@ -1486,28 +1721,32 @@ ) (define_expand "aarch64_simd_bsl<mode>" @@ -5952,8 +7948,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + DONE; }) - (define_expand "aarch64_vcond_internal<mode>" -@@ -1503,11 +1694,13 @@ +-(define_expand "aarch64_vcond_internal<mode>" ++(define_expand "aarch64_vcond_internal<mode><mode>" + [(set (match_operand:VDQ 0 "register_operand") + (if_then_else:VDQ (match_operator 3 "comparison_operator" [(match_operand:VDQ 4 "register_operand") (match_operand:VDQ 5 "nonmemory_operand")]) @@ -5969,7 +7967,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ rtx mask = gen_reg_rtx (<MODE>mode); switch (GET_CODE (operands[3])) -@@ -1548,12 +1741,12 @@ +@@ -1548,12 +1787,12 @@ case LTU: case GEU: @@ -5984,7 +7982,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ break; case NE: -@@ -1566,12 +1759,27 @@ +@@ -1566,30 +1805,47 @@ } if (inverse) @@ -6017,25 +8015,110 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ DONE; }) -@@ -1581,13 +1789,15 @@ +-(define_expand "aarch64_vcond_internal<mode>" +- [(set (match_operand:VDQF 0 "register_operand") ++(define_expand "aarch64_vcond_internal<VDQF_COND:mode><VDQF:mode>" ++ [(set (match_operand:VDQF_COND 0 "register_operand") + (if_then_else:VDQF (match_operator 3 "comparison_operator" [(match_operand:VDQF 4 "register_operand") (match_operand:VDQF 5 "nonmemory_operand")]) - (match_operand:VDQF 1 "register_operand") - (match_operand:VDQF 2 "register_operand")))] -+ (match_operand:VDQF 1 "nonmemory_operand") -+ (match_operand:VDQF 2 "nonmemory_operand")))] ++ (match_operand:VDQF_COND 1 "nonmemory_operand") ++ (match_operand:VDQF_COND 2 "nonmemory_operand")))] "TARGET_SIMD" { int inverse = 0; int use_zero_form = 0; int swap_bsl_operands = 0; +- rtx mask = gen_reg_rtx (<V_cmp_result>mode); +- rtx tmp = gen_reg_rtx (<V_cmp_result>mode); + rtx op1 = operands[1]; + rtx op2 = operands[2]; - rtx mask = gen_reg_rtx (<V_cmp_result>mode); - rtx tmp = gen_reg_rtx (<V_cmp_result>mode); ++ rtx mask = gen_reg_rtx (<VDQF_COND:V_cmp_result>mode); ++ rtx tmp = gen_reg_rtx (<VDQF_COND:V_cmp_result>mode); + + rtx (*base_comparison) (rtx, rtx, rtx); + rtx (*complimentary_comparison) (rtx, rtx, rtx); +@@ -1609,7 +1865,7 @@ + /* Fall through. */ + default: + if (!REG_P (operands[5])) +- operands[5] = force_reg (<MODE>mode, operands[5]); ++ operands[5] = force_reg (<VDQF:MODE>mode, operands[5]); + } -@@ -1732,11 +1942,27 @@ + switch (GET_CODE (operands[3])) +@@ -1622,8 +1878,8 @@ + case UNGE: + case ORDERED: + case UNORDERED: +- base_comparison = gen_aarch64_cmge<mode>; +- complimentary_comparison = gen_aarch64_cmgt<mode>; ++ base_comparison = gen_aarch64_cmge<VDQF:mode>; ++ complimentary_comparison = gen_aarch64_cmgt<VDQF:mode>; + break; + case LE: + case UNLE: +@@ -1631,14 +1887,14 @@ + /* Fall through. */ + case GT: + case UNGT: +- base_comparison = gen_aarch64_cmgt<mode>; +- complimentary_comparison = gen_aarch64_cmge<mode>; ++ base_comparison = gen_aarch64_cmgt<VDQF:mode>; ++ complimentary_comparison = gen_aarch64_cmge<VDQF:mode>; + break; + case EQ: + case NE: + case UNEQ: +- base_comparison = gen_aarch64_cmeq<mode>; +- complimentary_comparison = gen_aarch64_cmeq<mode>; ++ base_comparison = gen_aarch64_cmeq<VDQF:mode>; ++ complimentary_comparison = gen_aarch64_cmeq<VDQF:mode>; + break; + default: + gcc_unreachable (); +@@ -1666,10 +1922,10 @@ + switch (GET_CODE (operands[3])) + { + case LT: +- base_comparison = gen_aarch64_cmlt<mode>; ++ base_comparison = gen_aarch64_cmlt<VDQF:mode>; + break; + case LE: +- base_comparison = gen_aarch64_cmle<mode>; ++ base_comparison = gen_aarch64_cmle<VDQF:mode>; + break; + default: + /* Do nothing, other zero form cases already have the correct +@@ -1712,9 +1968,9 @@ + true iff !(a != b && a ORDERED b), swapping the operands to BSL + will then give us (a == b || a UNORDERED b) as intended. */ + +- emit_insn (gen_aarch64_cmgt<mode> (mask, operands[4], operands[5])); +- emit_insn (gen_aarch64_cmgt<mode> (tmp, operands[5], operands[4])); +- emit_insn (gen_ior<v_cmp_result>3 (mask, mask, tmp)); ++ emit_insn (gen_aarch64_cmgt<VDQF:mode> (mask, operands[4], operands[5])); ++ emit_insn (gen_aarch64_cmgt<VDQF:mode> (tmp, operands[5], operands[4])); ++ emit_insn (gen_ior<VDQF_COND:v_cmp_result>3 (mask, mask, tmp)); + swap_bsl_operands = 1; + break; + case UNORDERED: +@@ -1723,20 +1979,36 @@ + swap_bsl_operands = 1; + /* Fall through. */ + case ORDERED: +- emit_insn (gen_aarch64_cmgt<mode> (tmp, operands[4], operands[5])); +- emit_insn (gen_aarch64_cmge<mode> (mask, operands[5], operands[4])); +- emit_insn (gen_ior<v_cmp_result>3 (mask, mask, tmp)); ++ emit_insn (gen_aarch64_cmgt<VDQF:mode> (tmp, operands[4], operands[5])); ++ emit_insn (gen_aarch64_cmge<VDQF:mode> (mask, operands[5], operands[4])); ++ emit_insn (gen_ior<VDQF_COND:v_cmp_result>3 (mask, mask, tmp)); + break; + default: + gcc_unreachable (); } if (swap_bsl_operands) @@ -6052,23 +8135,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + /* If we have (a = (b CMP c) ? -1 : 0); + Then we can simply move the generated mask. */ + -+ if (op1 == CONSTM1_RTX (<V_cmp_result>mode) -+ && op2 == CONST0_RTX (<V_cmp_result>mode)) ++ if (op1 == CONSTM1_RTX (<VDQF_COND:V_cmp_result>mode) ++ && op2 == CONST0_RTX (<VDQF_COND:V_cmp_result>mode)) + emit_move_insn (operands[0], mask); + else + { + if (!REG_P (op1)) -+ op1 = force_reg (<MODE>mode, op1); ++ op1 = force_reg (<VDQF_COND:MODE>mode, op1); + if (!REG_P (op2)) -+ op2 = force_reg (<MODE>mode, op2); -+ emit_insn (gen_aarch64_simd_bsl<mode> (operands[0], mask, ++ op2 = force_reg (<VDQF_COND:MODE>mode, op2); ++ emit_insn (gen_aarch64_simd_bsl<VDQF_COND:mode> (operands[0], mask, + op1, op2)); + } + DONE; }) -@@ -1746,8 +1972,8 @@ +@@ -1746,16 +2018,32 @@ (match_operator 3 "comparison_operator" [(match_operand:VALL 4 "register_operand") (match_operand:VALL 5 "nonmemory_operand")]) @@ -6078,8 +8161,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + (match_operand:VALL 2 "nonmemory_operand")))] "TARGET_SIMD" { - emit_insn (gen_aarch64_vcond_internal<mode> (operands[0], operands[1], -@@ -1756,6 +1982,22 @@ +- emit_insn (gen_aarch64_vcond_internal<mode> (operands[0], operands[1], ++ emit_insn (gen_aarch64_vcond_internal<mode><mode> (operands[0], operands[1], + operands[2], operands[3], + operands[4], operands[5])); DONE; }) @@ -6093,7 +8178,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + (match_operand:<V_cmp_result> 2 "nonmemory_operand")))] + "TARGET_SIMD" +{ -+ emit_insn (gen_aarch64_vcond_internal<v_cmp_result> ( ++ emit_insn (gen_aarch64_vcond_internal<v_cmp_result><mode> ( + operands[0], operands[1], + operands[2], operands[3], + operands[4], operands[5])); @@ -6102,7 +8187,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_expand "vcondu<mode><mode>" [(set (match_operand:VDQ 0 "register_operand") -@@ -1763,8 +2005,8 @@ +@@ -1763,11 +2051,11 @@ (match_operator 3 "comparison_operator" [(match_operand:VDQ 4 "register_operand") (match_operand:VDQ 5 "nonmemory_operand")]) @@ -6112,8 +8197,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + (match_operand:VDQ 2 "nonmemory_operand")))] "TARGET_SIMD" { - emit_insn (gen_aarch64_vcond_internal<mode> (operands[0], operands[1], -@@ -2861,28 +3103,6 @@ +- emit_insn (gen_aarch64_vcond_internal<mode> (operands[0], operands[1], ++ emit_insn (gen_aarch64_vcond_internal<mode><mode> (operands[0], operands[1], + operands[2], operands[3], + operands[4], operands[5])); + DONE; +@@ -2861,28 +3149,6 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -6142,7 +8231,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; vshll_n (define_insn "aarch64_<sur>shll_n<mode>" -@@ -2927,28 +3147,6 @@ +@@ -2927,28 +3193,6 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -6171,7 +8260,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; vrshr_n (define_insn "aarch64_<sur>shr_n<mode>" -@@ -3034,52 +3232,202 @@ +@@ -3034,52 +3278,180 @@ ) @@ -6209,7 +8298,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + (COMPARISONS:DI + (match_operand:DI 1 "register_operand" "w,w,r") + (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz,r") -+ )))] ++ ))) ++ (clobber (reg:CC CC_REGNUM))] + "TARGET_SIMD" + "@ + cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2> @@ -6220,15 +8310,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + happening in the 'w' constraint cases. */ + && GP_REGNUM_P (REGNO (operands[0])) + && GP_REGNUM_P (REGNO (operands[1]))" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC -+ (match_dup 1) -+ (match_dup 2))) -+ (set (match_dup 0) -+ (neg:DI -+ (COMPARISONS:DI -+ (match_operand 3 "cc_register" "") -+ (const_int 0))))] ++ [(const_int 0)] + { + enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]); + rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]); @@ -6268,7 +8350,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + (UCOMPARISONS:DI + (match_operand:DI 1 "register_operand" "w,r") + (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,r") -+ )))] ++ ))) ++ (clobber (reg:CC CC_REGNUM))] + "TARGET_SIMD" + "@ + cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2> @@ -6278,17 +8361,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + happening in the 'w' constraint cases. */ + && GP_REGNUM_P (REGNO (operands[0])) + && GP_REGNUM_P (REGNO (operands[1]))" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC -+ (match_dup 1) -+ (match_dup 2))) -+ (set (match_dup 0) -+ (neg:DI -+ (UCOMPARISONS:DI -+ (match_operand 3 "cc_register" "") -+ (const_int 0))))] ++ [(const_int 0)] + { -+ enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]); ++ enum machine_mode mode = CCmode; + rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]); + rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]); + emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); @@ -6322,7 +8397,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + (and:DI + (match_operand:DI 1 "register_operand" "w,r") + (match_operand:DI 2 "register_operand" "w,r")) -+ (const_int 0))))] ++ (const_int 0)))) ++ (clobber (reg:CC CC_REGNUM))] + "TARGET_SIMD" + "@ + cmtst\t%d0, %d1, %d2 @@ -6332,16 +8408,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + happening in the 'w' constraint cases. */ + && GP_REGNUM_P (REGNO (operands[0])) + && GP_REGNUM_P (REGNO (operands[1]))" -+ [(set (reg:CC_NZ CC_REGNUM) -+ (compare:CC_NZ -+ (and:DI (match_dup 1) -+ (match_dup 2)) -+ (const_int 0))) -+ (set (match_dup 0) -+ (neg:DI -+ (ne:DI -+ (match_operand 3 "cc_register" "") -+ (const_int 0))))] ++ [(const_int 0)] + { + rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]); + enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx); @@ -6397,7 +8464,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; addp (define_insn "aarch64_addp<mode>" -@@ -3105,19 +3453,6 @@ +@@ -3105,30 +3477,6 @@ (set_attr "simd_mode" "DI")] ) @@ -6414,10 +8481,21 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ -}) - - - (define_insn "aarch64_<fmaxmin><mode>" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w") -@@ -3140,16 +3475,6 @@ +-(define_insn "aarch64_<fmaxmin><mode>" +- [(set (match_operand:VDQF 0 "register_operand" "=w") +- (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w") +- (match_operand:VDQF 2 "register_operand" "w")] +- FMAXMIN))] +- "TARGET_SIMD" +- "<fmaxmin>\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>" +- [(set_attr "simd_type" "simd_fminmax") +- (set_attr "simd_mode" "<MODE>")] +-) +- + ;; sqrt + + (define_insn "sqrt<mode>2" +@@ -3140,16 +3488,6 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -6434,7 +8512,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; Patterns for vector struct loads and stores. (define_insn "vec_load_lanesoi<mode>" -@@ -3714,3 +4039,25 @@ +@@ -3714,3 +4052,25 @@ "ld1r\\t{%0.<Vtype>}, %1" [(set_attr "simd_type" "simd_load1r") (set_attr "simd_mode" "<MODE>")]) @@ -6474,6 +8552,35 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_predicate "aarch64_reg_zero_or_m1_or_1" (and (match_code "reg,subreg,const_int") (ior (match_operand 0 "register_operand") +@@ -110,10 +115,6 @@ + (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL, + 0)"))) + +-(define_predicate "aarch64_const_address" +- (and (match_code "symbol_ref") +- (match_test "mode == DImode && CONSTANT_ADDRESS_P (op)"))) +- + (define_predicate "aarch64_valid_symref" + (match_code "const, symbol_ref, label_ref") + { +@@ -165,15 +166,10 @@ + }) + + (define_predicate "aarch64_mov_operand" +- (and (match_code "reg,subreg,mem,const_int,symbol_ref,high") ++ (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high") + (ior (match_operand 0 "register_operand") + (ior (match_operand 0 "memory_operand") +- (ior (match_test "GET_CODE (op) == HIGH +- && aarch64_valid_symref (XEXP (op, 0), +- GET_MODE (XEXP (op, 0)))") +- (ior (match_test "CONST_INT_P (op) +- && aarch64_move_imm (INTVAL (op), mode)") +- (match_test "aarch64_const_address (op, mode)"))))))) ++ (match_test "aarch64_mov_operand_p (op, SYMBOL_CONTEXT_ADR, mode)"))))) + + (define_predicate "aarch64_movti_operand" + (and (match_code "reg,subreg,mem,const_int") --- a/src/gcc/config/aarch64/aarch64-elf.h +++ b/src/gcc/config/aarch64/aarch64-elf.h @@ -106,7 +106,6 @@ @@ -6584,7 +8691,124 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ __extension__ static __inline int16_t __attribute__ ((__always_inline__)) vaddlv_s8 (int8x8_t a) { -@@ -5095,358 +5018,6 @@ +@@ -4732,116 +4655,6 @@ + return result; + } + +-__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +-vaddv_s8 (int8x8_t a) +-{ +- int8_t result; +- __asm__ ("addv %b0,%1.8b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +-vaddv_s16 (int16x4_t a) +-{ +- int16_t result; +- __asm__ ("addv %h0,%1.4h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +-vaddv_u8 (uint8x8_t a) +-{ +- uint8_t result; +- __asm__ ("addv %b0,%1.8b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +-vaddv_u16 (uint16x4_t a) +-{ +- uint16_t result; +- __asm__ ("addv %h0,%1.4h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +-vaddvq_s8 (int8x16_t a) +-{ +- int8_t result; +- __asm__ ("addv %b0,%1.16b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +-vaddvq_s16 (int16x8_t a) +-{ +- int16_t result; +- __asm__ ("addv %h0,%1.8h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +-vaddvq_s32 (int32x4_t a) +-{ +- int32_t result; +- __asm__ ("addv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +-vaddvq_u8 (uint8x16_t a) +-{ +- uint8_t result; +- __asm__ ("addv %b0,%1.16b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +-vaddvq_u16 (uint16x8_t a) +-{ +- uint16_t result; +- __asm__ ("addv %h0,%1.8h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +-vaddvq_u32 (uint32x4_t a) +-{ +- uint32_t result; +- __asm__ ("addv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vbsl_f32 (uint32x2_t a, float32x2_t b, float32x2_t c) + { +@@ -5095,358 +4908,6 @@ return result; } @@ -6943,7 +9167,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vcls_s8 (int8x8_t a) { -@@ -5513,50 +5084,6 @@ +@@ -5513,50 +4974,6 @@ return result; } @@ -6994,7 +9218,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vclz_s8 (int8x8_t a) { -@@ -5915,100 +5442,12 @@ +@@ -5915,100 +5332,12 @@ /* vcvt_f32_f16 not supported */ @@ -7095,7 +9319,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ #define vcvt_n_f32_s32(a, b) \ __extension__ \ ({ \ -@@ -6057,160 +5496,6 @@ +@@ -6057,160 +5386,6 @@ result; \ }) @@ -7256,7 +9480,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ #define vcvtd_n_f64_s64(a, b) \ __extension__ \ ({ \ -@@ -6259,402 +5544,6 @@ +@@ -6259,402 +5434,6 @@ result; \ }) @@ -7659,7 +9883,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ #define vcvtq_n_f32_s32(a, b) \ __extension__ \ ({ \ -@@ -6751,72 +5640,6 @@ +@@ -6751,72 +5530,6 @@ result; \ }) @@ -7732,7 +9956,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ #define vcvts_n_f32_s32(a, b) \ __extension__ \ ({ \ -@@ -6865,28 +5688,6 @@ +@@ -6865,28 +5578,6 @@ result; \ }) @@ -7761,7 +9985,311 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vcvtx_f32_f64 (float64x2_t a) { -@@ -14556,17 +13357,6 @@ +@@ -9226,303 +7917,6 @@ + return result; + } + +-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +-vmaxnm_f32 (float32x2_t a, float32x2_t b) +-{ +- float32x2_t result; +- __asm__ ("fmaxnm %0.2s,%1.2s,%2.2s" +- : "=w"(result) +- : "w"(a), "w"(b) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +-vmaxnmq_f32 (float32x4_t a, float32x4_t b) +-{ +- float32x4_t result; +- __asm__ ("fmaxnm %0.4s,%1.4s,%2.4s" +- : "=w"(result) +- : "w"(a), "w"(b) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) +-vmaxnmq_f64 (float64x2_t a, float64x2_t b) +-{ +- float64x2_t result; +- __asm__ ("fmaxnm %0.2d,%1.2d,%2.2d" +- : "=w"(result) +- : "w"(a), "w"(b) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vmaxnmvq_f32 (float32x4_t a) +-{ +- float32_t result; +- __asm__ ("fmaxnmv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +-vmaxv_s8 (int8x8_t a) +-{ +- int8_t result; +- __asm__ ("smaxv %b0,%1.8b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +-vmaxv_s16 (int16x4_t a) +-{ +- int16_t result; +- __asm__ ("smaxv %h0,%1.4h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +-vmaxv_u8 (uint8x8_t a) +-{ +- uint8_t result; +- __asm__ ("umaxv %b0,%1.8b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +-vmaxv_u16 (uint16x4_t a) +-{ +- uint16_t result; +- __asm__ ("umaxv %h0,%1.4h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vmaxvq_f32 (float32x4_t a) +-{ +- float32_t result; +- __asm__ ("fmaxv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +-vmaxvq_s8 (int8x16_t a) +-{ +- int8_t result; +- __asm__ ("smaxv %b0,%1.16b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +-vmaxvq_s16 (int16x8_t a) +-{ +- int16_t result; +- __asm__ ("smaxv %h0,%1.8h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +-vmaxvq_s32 (int32x4_t a) +-{ +- int32_t result; +- __asm__ ("smaxv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +-vmaxvq_u8 (uint8x16_t a) +-{ +- uint8_t result; +- __asm__ ("umaxv %b0,%1.16b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +-vmaxvq_u16 (uint16x8_t a) +-{ +- uint16_t result; +- __asm__ ("umaxv %h0,%1.8h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +-vmaxvq_u32 (uint32x4_t a) +-{ +- uint32_t result; +- __asm__ ("umaxv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vminnmvq_f32 (float32x4_t a) +-{ +- float32_t result; +- __asm__ ("fminnmv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +-vminv_s8 (int8x8_t a) +-{ +- int8_t result; +- __asm__ ("sminv %b0,%1.8b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +-vminv_s16 (int16x4_t a) +-{ +- int16_t result; +- __asm__ ("sminv %h0,%1.4h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +-vminv_u8 (uint8x8_t a) +-{ +- uint8_t result; +- __asm__ ("uminv %b0,%1.8b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +-vminv_u16 (uint16x4_t a) +-{ +- uint16_t result; +- __asm__ ("uminv %h0,%1.4h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vminvq_f32 (float32x4_t a) +-{ +- float32_t result; +- __asm__ ("fminv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +-vminvq_s8 (int8x16_t a) +-{ +- int8_t result; +- __asm__ ("sminv %b0,%1.16b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +-vminvq_s16 (int16x8_t a) +-{ +- int16_t result; +- __asm__ ("sminv %h0,%1.8h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +-vminvq_s32 (int32x4_t a) +-{ +- int32_t result; +- __asm__ ("sminv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +-vminvq_u8 (uint8x16_t a) +-{ +- uint8_t result; +- __asm__ ("uminv %b0,%1.16b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +-vminvq_u16 (uint16x8_t a) +-{ +- uint16_t result; +- __asm__ ("uminv %h0,%1.8h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +-vminvq_u32 (uint32x4_t a) +-{ +- uint32_t result; +- __asm__ ("uminv %s0,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- + #define vmla_lane_f32(a, b, c, d) \ + __extension__ \ + ({ \ +@@ -14556,17 +12950,6 @@ return result; } @@ -7779,7 +10307,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vrecpe_u32 (uint32x2_t a) { -@@ -14578,39 +13368,6 @@ +@@ -14578,39 +12961,6 @@ return result; } @@ -7819,7 +10347,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vrecpeq_u32 (uint32x4_t a) { -@@ -14622,94 +13379,6 @@ +@@ -14622,94 +12972,6 @@ return result; } @@ -7914,7 +10442,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) vrev16_p8 (poly8x8_t a) { -@@ -15106,171 +13775,6 @@ +@@ -15106,171 +13368,6 @@ return result; } @@ -8086,7 +10614,94 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ #define vrshrn_high_n_s16(a, b, c) \ __extension__ \ ({ \ -@@ -19849,6 +18353,26 @@ +@@ -18788,86 +16885,6 @@ + return result; + } + +-__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +-vaddv_s32 (int32x2_t a) +-{ +- int32_t result; +- __asm__ ("addp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); +- return result; +-} +- +-__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +-vaddv_u32 (uint32x2_t a) +-{ +- uint32_t result; +- __asm__ ("addp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); +- return result; +-} +- +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vmaxnmv_f32 (float32x2_t a) +-{ +- float32_t result; +- __asm__ ("fmaxnmp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); +- return result; +-} +- +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vminnmv_f32 (float32x2_t a) +-{ +- float32_t result; +- __asm__ ("fminnmp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); +- return result; +-} +- +-__extension__ static __inline float64_t __attribute__ ((__always_inline__)) +-vmaxnmvq_f64 (float64x2_t a) +-{ +- float64_t result; +- __asm__ ("fmaxnmp %0.2d, %1.2d, %1.2d" : "=w"(result) : "w"(a) : ); +- return result; +-} +- +-__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +-vmaxv_s32 (int32x2_t a) +-{ +- int32_t result; +- __asm__ ("smaxp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); +- return result; +-} +- +-__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +-vmaxv_u32 (uint32x2_t a) +-{ +- uint32_t result; +- __asm__ ("umaxp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); +- return result; +-} +- +-__extension__ static __inline float64_t __attribute__ ((__always_inline__)) +-vminnmvq_f64 (float64x2_t a) +-{ +- float64_t result; +- __asm__ ("fminnmp %0.2d, %1.2d, %1.2d" : "=w"(result) : "w"(a) : ); +- return result; +-} +- +-__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +-vminv_s32 (int32x2_t a) +-{ +- int32_t result; +- __asm__ ("sminp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); +- return result; +-} +- +-__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +-vminv_u32 (uint32x2_t a) +-{ +- uint32_t result; +- __asm__ ("uminp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); +- return result; +-} +- + __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) + vpaddd_s64 (int64x2_t __a) + { +@@ -19849,6 +17866,26 @@ /* Start of optimal implementations in approved order. */ @@ -8113,29 +10728,122 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* vadd */ __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -@@ -19863,8 +18387,145 @@ +@@ -19863,8 +17900,238 @@ return __a + __b; } -/* vceq */ ++/* vaddv */ + ++__extension__ static __inline int8_t __attribute__ ((__always_inline__)) ++vaddv_s8 (int8x8_t __a) ++{ ++ return vget_lane_s8 (__builtin_aarch64_reduc_splus_v8qi (__a), 0); ++} ++ ++__extension__ static __inline int16_t __attribute__ ((__always_inline__)) ++vaddv_s16 (int16x4_t __a) ++{ ++ return vget_lane_s16 (__builtin_aarch64_reduc_splus_v4hi (__a), 0); ++} ++ ++__extension__ static __inline int32_t __attribute__ ((__always_inline__)) ++vaddv_s32 (int32x2_t __a) ++{ ++ return vget_lane_s32 (__builtin_aarch64_reduc_splus_v2si (__a), 0); ++} ++ ++__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) ++vaddv_u8 (uint8x8_t __a) ++{ ++ return vget_lane_u8 ((uint8x8_t) ++ __builtin_aarch64_reduc_uplus_v8qi ((int8x8_t) __a), 0); ++} ++ ++__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) ++vaddv_u16 (uint16x4_t __a) ++{ ++ return vget_lane_u16 ((uint16x4_t) ++ __builtin_aarch64_reduc_uplus_v4hi ((int16x4_t) __a), 0); ++} ++ ++__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) ++vaddv_u32 (uint32x2_t __a) ++{ ++ return vget_lane_u32 ((uint32x2_t) ++ __builtin_aarch64_reduc_uplus_v2si ((int32x2_t) __a), 0); ++} ++ ++__extension__ static __inline int8_t __attribute__ ((__always_inline__)) ++vaddvq_s8 (int8x16_t __a) ++{ ++ return vgetq_lane_s8 (__builtin_aarch64_reduc_splus_v16qi (__a), 0); ++} ++ ++__extension__ static __inline int16_t __attribute__ ((__always_inline__)) ++vaddvq_s16 (int16x8_t __a) ++{ ++ return vgetq_lane_s16 (__builtin_aarch64_reduc_splus_v8hi (__a), 0); ++} ++ ++__extension__ static __inline int32_t __attribute__ ((__always_inline__)) ++vaddvq_s32 (int32x4_t __a) ++{ ++ return vgetq_lane_s32 (__builtin_aarch64_reduc_splus_v4si (__a), 0); ++} ++ ++__extension__ static __inline int32_t __attribute__ ((__always_inline__)) ++vaddvq_s64 (int64x2_t __a) ++{ ++ return vgetq_lane_s64 (__builtin_aarch64_reduc_splus_v2di (__a), 0); ++} ++ ++__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) ++vaddvq_u8 (uint8x16_t __a) ++{ ++ return vgetq_lane_u8 ((uint8x16_t) ++ __builtin_aarch64_reduc_uplus_v16qi ((int8x16_t) __a), 0); ++} ++ ++__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) ++vaddvq_u16 (uint16x8_t __a) ++{ ++ return vgetq_lane_u16 ((uint16x8_t) ++ __builtin_aarch64_reduc_uplus_v8hi ((int16x8_t) __a), 0); ++} ++ ++__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) ++vaddvq_u32 (uint32x4_t __a) ++{ ++ return vgetq_lane_u32 ((uint32x4_t) ++ __builtin_aarch64_reduc_uplus_v4si ((int32x4_t) __a), 0); ++} ++ ++__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) ++vaddvq_u64 (uint64x2_t __a) ++{ ++ return vgetq_lane_u64 ((uint64x2_t) ++ __builtin_aarch64_reduc_uplus_v2di ((int64x2_t) __a), 0); ++} ++ +__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +vaddv_f32 (float32x2_t __a) +{ -+ float32x2_t t = __builtin_aarch64_addvv2sf (__a); ++ float32x2_t t = __builtin_aarch64_reduc_splus_v2sf (__a); + return vget_lane_f32 (t, 0); +} - ++ +__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +vaddvq_f32 (float32x4_t __a) +{ -+ float32x4_t t = __builtin_aarch64_addvv4sf (__a); ++ float32x4_t t = __builtin_aarch64_reduc_splus_v4sf (__a); + return vgetq_lane_f32 (t, 0); +} + +__extension__ static __inline float64_t __attribute__ ((__always_inline__)) +vaddvq_f64 (float64x2_t __a) +{ -+ float64x2_t t = __builtin_aarch64_addvv2df (__a); ++ float64x2_t t = __builtin_aarch64_reduc_splus_v2df (__a); + return vgetq_lane_f64 (t, 0); +} + @@ -8260,7 +10968,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vceq_p8 (poly8x8_t __a, poly8x8_t __b) { -@@ -19893,7 +18554,7 @@ +@@ -19893,7 +18160,7 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceq_s64 (int64x1_t __a, int64x1_t __b) { @@ -8269,7 +10977,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -19920,10 +18581,21 @@ +@@ -19920,10 +18187,21 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceq_u64 (uint64x1_t __a, uint64x1_t __b) { @@ -8293,7 +11001,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vceqq_p8 (poly8x16_t __a, poly8x16_t __b) { -@@ -19983,27 +18655,245 @@ +@@ -19983,27 +18261,245 @@ (int64x2_t) __b); } @@ -8543,7 +11251,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ vcge_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgev8qi (__a, __b); -@@ -20024,38 +18914,56 @@ +@@ -20024,38 +18520,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcge_s64 (int64x1_t __a, int64x1_t __b) { @@ -8606,7 +11314,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ vcgeq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgev16qi (__a, __b); -@@ -20082,53 +18990,270 @@ +@@ -20082,53 +18596,270 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgeq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -8886,7 +11594,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ vcgt_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__a, __b); -@@ -20149,38 +19274,56 @@ +@@ -20149,38 +18880,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgt_s64 (int64x1_t __a, int64x1_t __b) { @@ -8949,7 +11657,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ vcgtq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__a, __b); -@@ -20207,53 +19350,270 @@ +@@ -20207,53 +18956,270 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgtq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -9229,7 +11937,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ vcle_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgev8qi (__b, __a); -@@ -20274,38 +19634,56 @@ +@@ -20274,38 +19240,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcle_s64 (int64x1_t __a, int64x1_t __b) { @@ -9292,7 +12000,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ vcleq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgev16qi (__b, __a); -@@ -20332,46 +19710,213 @@ +@@ -20332,46 +19316,213 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcleq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -9513,7 +12221,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ vclt_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__b, __a); -@@ -20392,38 +19937,56 @@ +@@ -20392,38 +19543,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vclt_s64 (int64x1_t __a, int64x1_t __b) { @@ -9576,7 +12284,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ vcltq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__b, __a); -@@ -20450,43 +20013,616 @@ +@@ -20450,43 +19619,616 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcltq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -10199,7 +12907,346 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* vdup */ __extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -@@ -23115,6 +23251,223 @@ +@@ -21408,7 +21150,7 @@ + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vmax_f32 (float32x2_t __a, float32x2_t __b) + { +- return __builtin_aarch64_fmaxv2sf (__a, __b); ++ return __builtin_aarch64_smax_nanv2sf (__a, __b); + } + + __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +@@ -21453,13 +21195,13 @@ + __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) + vmaxq_f32 (float32x4_t __a, float32x4_t __b) + { +- return __builtin_aarch64_fmaxv4sf (__a, __b); ++ return __builtin_aarch64_smax_nanv4sf (__a, __b); + } + + __extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) + vmaxq_f64 (float64x2_t __a, float64x2_t __b) + { +- return __builtin_aarch64_fmaxv2df (__a, __b); ++ return __builtin_aarch64_smax_nanv2df (__a, __b); + } + + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +@@ -21501,12 +21243,150 @@ + (int32x4_t) __b); + } + +-/* vmin */ ++/* vmaxnm */ + + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) ++vmaxnm_f32 (float32x2_t __a, float32x2_t __b) ++{ ++ return __builtin_aarch64_smaxv2sf (__a, __b); ++} ++ ++__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) ++vmaxnmq_f32 (float32x4_t __a, float32x4_t __b) ++{ ++ return __builtin_aarch64_smaxv4sf (__a, __b); ++} ++ ++__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) ++vmaxnmq_f64 (float64x2_t __a, float64x2_t __b) ++{ ++ return __builtin_aarch64_smaxv2df (__a, __b); ++} ++ ++/* vmaxv */ ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vmaxv_f32 (float32x2_t __a) ++{ ++ return vget_lane_f32 (__builtin_aarch64_reduc_smax_nan_v2sf (__a), 0); ++} ++ ++__extension__ static __inline int8_t __attribute__ ((__always_inline__)) ++vmaxv_s8 (int8x8_t __a) ++{ ++ return vget_lane_s8 (__builtin_aarch64_reduc_smax_v8qi (__a), 0); ++} ++ ++__extension__ static __inline int16_t __attribute__ ((__always_inline__)) ++vmaxv_s16 (int16x4_t __a) ++{ ++ return vget_lane_s16 (__builtin_aarch64_reduc_smax_v4hi (__a), 0); ++} ++ ++__extension__ static __inline int32_t __attribute__ ((__always_inline__)) ++vmaxv_s32 (int32x2_t __a) ++{ ++ return vget_lane_s32 (__builtin_aarch64_reduc_smax_v2si (__a), 0); ++} ++ ++__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) ++vmaxv_u8 (uint8x8_t __a) ++{ ++ return vget_lane_u8 ((uint8x8_t) ++ __builtin_aarch64_reduc_umax_v8qi ((int8x8_t) __a), 0); ++} ++ ++__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) ++vmaxv_u16 (uint16x4_t __a) ++{ ++ return vget_lane_u16 ((uint16x4_t) ++ __builtin_aarch64_reduc_umax_v4hi ((int16x4_t) __a), 0); ++} ++ ++__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) ++vmaxv_u32 (uint32x2_t __a) ++{ ++ return vget_lane_u32 ((uint32x2_t) ++ __builtin_aarch64_reduc_umax_v2si ((int32x2_t) __a), 0); ++} ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vmaxvq_f32 (float32x4_t __a) ++{ ++ return vgetq_lane_f32 (__builtin_aarch64_reduc_smax_nan_v4sf (__a), 0); ++} ++ ++__extension__ static __inline float64_t __attribute__ ((__always_inline__)) ++vmaxvq_f64 (float64x2_t __a) ++{ ++ return vgetq_lane_f64 (__builtin_aarch64_reduc_smax_nan_v2df (__a), 0); ++} ++ ++__extension__ static __inline int8_t __attribute__ ((__always_inline__)) ++vmaxvq_s8 (int8x16_t __a) ++{ ++ return vgetq_lane_s8 (__builtin_aarch64_reduc_smax_v16qi (__a), 0); ++} ++ ++__extension__ static __inline int16_t __attribute__ ((__always_inline__)) ++vmaxvq_s16 (int16x8_t __a) ++{ ++ return vgetq_lane_s16 (__builtin_aarch64_reduc_smax_v8hi (__a), 0); ++} ++ ++__extension__ static __inline int32_t __attribute__ ((__always_inline__)) ++vmaxvq_s32 (int32x4_t __a) ++{ ++ return vgetq_lane_s32 (__builtin_aarch64_reduc_smax_v4si (__a), 0); ++} ++ ++__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) ++vmaxvq_u8 (uint8x16_t __a) ++{ ++ return vgetq_lane_u8 ((uint8x16_t) ++ __builtin_aarch64_reduc_umax_v16qi ((int8x16_t) __a), 0); ++} ++ ++__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) ++vmaxvq_u16 (uint16x8_t __a) ++{ ++ return vgetq_lane_u16 ((uint16x8_t) ++ __builtin_aarch64_reduc_umax_v8hi ((int16x8_t) __a), 0); ++} ++ ++__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) ++vmaxvq_u32 (uint32x4_t __a) ++{ ++ return vgetq_lane_u32 ((uint32x4_t) ++ __builtin_aarch64_reduc_umax_v4si ((int32x4_t) __a), 0); ++} ++ ++/* vmaxnmv */ ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vmaxnmv_f32 (float32x2_t __a) ++{ ++ return vget_lane_f32 (__builtin_aarch64_reduc_smax_v2sf (__a), 0); ++} ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vmaxnmvq_f32 (float32x4_t __a) ++{ ++ return vgetq_lane_f32 (__builtin_aarch64_reduc_smax_v4sf (__a), 0); ++} ++ ++__extension__ static __inline float64_t __attribute__ ((__always_inline__)) ++vmaxnmvq_f64 (float64x2_t __a) ++{ ++ return vgetq_lane_f64 (__builtin_aarch64_reduc_smax_v2df (__a), 0); ++} ++ ++/* vmin */ ++ ++__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vmin_f32 (float32x2_t __a, float32x2_t __b) + { +- return __builtin_aarch64_fminv2sf (__a, __b); ++ return __builtin_aarch64_smin_nanv2sf (__a, __b); + } + + __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +@@ -21551,13 +21431,13 @@ + __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) + vminq_f32 (float32x4_t __a, float32x4_t __b) + { +- return __builtin_aarch64_fminv4sf (__a, __b); ++ return __builtin_aarch64_smin_nanv4sf (__a, __b); + } + + __extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) + vminq_f64 (float64x2_t __a, float64x2_t __b) + { +- return __builtin_aarch64_fminv2df (__a, __b); ++ return __builtin_aarch64_smin_nanv2df (__a, __b); + } + + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +@@ -21599,6 +21479,144 @@ + (int32x4_t) __b); + } + ++/* vminnm */ ++ ++__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) ++vminnm_f32 (float32x2_t __a, float32x2_t __b) ++{ ++ return __builtin_aarch64_sminv2sf (__a, __b); ++} ++ ++__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) ++vminnmq_f32 (float32x4_t __a, float32x4_t __b) ++{ ++ return __builtin_aarch64_sminv4sf (__a, __b); ++} ++ ++__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) ++vminnmq_f64 (float64x2_t __a, float64x2_t __b) ++{ ++ return __builtin_aarch64_sminv2df (__a, __b); ++} ++ ++/* vminv */ ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vminv_f32 (float32x2_t __a) ++{ ++ return vget_lane_f32 (__builtin_aarch64_reduc_smin_nan_v2sf (__a), 0); ++} ++ ++__extension__ static __inline int8_t __attribute__ ((__always_inline__)) ++vminv_s8 (int8x8_t __a) ++{ ++ return vget_lane_s8 (__builtin_aarch64_reduc_smin_v8qi (__a), 0); ++} ++ ++__extension__ static __inline int16_t __attribute__ ((__always_inline__)) ++vminv_s16 (int16x4_t __a) ++{ ++ return vget_lane_s16 (__builtin_aarch64_reduc_smin_v4hi (__a), 0); ++} ++ ++__extension__ static __inline int32_t __attribute__ ((__always_inline__)) ++vminv_s32 (int32x2_t __a) ++{ ++ return vget_lane_s32 (__builtin_aarch64_reduc_smin_v2si (__a), 0); ++} ++ ++__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) ++vminv_u8 (uint8x8_t __a) ++{ ++ return vget_lane_u8 ((uint8x8_t) ++ __builtin_aarch64_reduc_umin_v8qi ((int8x8_t) __a), 0); ++} ++ ++__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) ++vminv_u16 (uint16x4_t __a) ++{ ++ return vget_lane_u16 ((uint16x4_t) ++ __builtin_aarch64_reduc_umin_v4hi ((int16x4_t) __a), 0); ++} ++ ++__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) ++vminv_u32 (uint32x2_t __a) ++{ ++ return vget_lane_u32 ((uint32x2_t) ++ __builtin_aarch64_reduc_umin_v2si ((int32x2_t) __a), 0); ++} ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vminvq_f32 (float32x4_t __a) ++{ ++ return vgetq_lane_f32 (__builtin_aarch64_reduc_smin_nan_v4sf (__a), 0); ++} ++ ++__extension__ static __inline float64_t __attribute__ ((__always_inline__)) ++vminvq_f64 (float64x2_t __a) ++{ ++ return vgetq_lane_f64 (__builtin_aarch64_reduc_smin_nan_v2df (__a), 0); ++} ++ ++__extension__ static __inline int8_t __attribute__ ((__always_inline__)) ++vminvq_s8 (int8x16_t __a) ++{ ++ return vgetq_lane_s8 (__builtin_aarch64_reduc_smin_v16qi (__a), 0); ++} ++ ++__extension__ static __inline int16_t __attribute__ ((__always_inline__)) ++vminvq_s16 (int16x8_t __a) ++{ ++ return vgetq_lane_s16 (__builtin_aarch64_reduc_smin_v8hi (__a), 0); ++} ++ ++__extension__ static __inline int32_t __attribute__ ((__always_inline__)) ++vminvq_s32 (int32x4_t __a) ++{ ++ return vgetq_lane_s32 (__builtin_aarch64_reduc_smin_v4si (__a), 0); ++} ++ ++__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) ++vminvq_u8 (uint8x16_t __a) ++{ ++ return vgetq_lane_u8 ((uint8x16_t) ++ __builtin_aarch64_reduc_umin_v16qi ((int8x16_t) __a), 0); ++} ++ ++__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) ++vminvq_u16 (uint16x8_t __a) ++{ ++ return vgetq_lane_u16 ((uint16x8_t) ++ __builtin_aarch64_reduc_umin_v8hi ((int16x8_t) __a), 0); ++} ++ ++__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) ++vminvq_u32 (uint32x4_t __a) ++{ ++ return vgetq_lane_u32 ((uint32x4_t) ++ __builtin_aarch64_reduc_umin_v4si ((int32x4_t) __a), 0); ++} ++ ++/* vminnmv */ ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vminnmv_f32 (float32x2_t __a) ++{ ++ return vget_lane_f32 (__builtin_aarch64_reduc_smin_v2sf (__a), 0); ++} ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vminnmvq_f32 (float32x4_t __a) ++{ ++ return vgetq_lane_f32 (__builtin_aarch64_reduc_smin_v4sf (__a), 0); ++} ++ ++__extension__ static __inline float64_t __attribute__ ((__always_inline__)) ++vminnmvq_f64 (float64x2_t __a) ++{ ++ return vgetq_lane_f64 (__builtin_aarch64_reduc_smin_v2df (__a), 0); ++} ++ + /* vmla */ + + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +@@ -23115,6 +23133,223 @@ return (uint64x1_t) __builtin_aarch64_uqsubdi (__a, __b); } @@ -10423,7 +13470,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* vrshl */ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -23458,109 +23811,109 @@ +@@ -23458,109 +23693,109 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vshl_n_s8 (int8x8_t __a, const int __b) { @@ -10551,7 +13598,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ } __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -23748,109 +24101,109 @@ +@@ -23748,109 +23983,109 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vshr_n_s8 (int8x8_t __a, const int __b) { @@ -10679,7 +13726,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ } /* vsli */ -@@ -25320,7 +25673,7 @@ +@@ -25320,7 +25555,7 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtst_s64 (int64x1_t __a, int64x1_t __b) { @@ -10688,7 +13735,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -25347,8 +25700,7 @@ +@@ -25347,8 +25582,7 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtst_u64 (uint64x1_t __a, uint64x1_t __b) { @@ -10698,7 +13745,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -@@ -25406,14 +25758,13 @@ +@@ -25406,14 +25640,13 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtstd_s64 (int64x1_t __a, int64x1_t __b) { @@ -10741,7 +13788,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ frint,\ fsqrt,\ load_acq,\ -@@ -763,19 +770,24 @@ +@@ -763,19 +770,41 @@ ) (define_insn "*mov<mode>_aarch64" @@ -10751,27 +13798,50 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + (match_operand:SHORT 1 "general_operand" " r,M,D<hq>,m, m,rZ,*w,*w, r,*w"))] "(register_operand (operands[0], <MODE>mode) || aarch64_reg_or_zero (operands[1], <MODE>mode))" - "@ - mov\\t%w0, %w1 - mov\\t%w0, %1 -+ movi\\t%0.<Vallxd>, %1 - ldr<size>\\t%w0, %1 -+ ldr\\t%<size>0, %1 - str<size>\\t%w1, %0 -+ str\\t%<size>1, %0 - umov\\t%w0, %1.<v>[0] +- "@ +- mov\\t%w0, %w1 +- mov\\t%w0, %1 +- ldr<size>\\t%w0, %1 +- str<size>\\t%w1, %0 +- umov\\t%w0, %1.<v>[0] - dup\\t%0.<Vallxd>, %w1" - [(set_attr "v8type" "move,alu,load1,store1,*,*") - (set_attr "simd_type" "*,*,*,*,simd_movgp,simd_dupgp") -+ dup\\t%0.<Vallxd>, %w1 -+ dup\\t%0, %1.<v>[0]" ++{ ++ switch (which_alternative) ++ { ++ case 0: ++ return "mov\t%w0, %w1"; ++ case 1: ++ return "mov\t%w0, %1"; ++ case 2: ++ return aarch64_output_scalar_simd_mov_immediate (operands[1], ++ <MODE>mode); ++ case 3: ++ return "ldr<size>\t%w0, %1"; ++ case 4: ++ return "ldr\t%<size>0, %1"; ++ case 5: ++ return "str<size>\t%w1, %0"; ++ case 6: ++ return "str\t%<size>1, %0"; ++ case 7: ++ return "umov\t%w0, %1.<v>[0]"; ++ case 8: ++ return "dup\t%0.<Vallxd>, %w1"; ++ case 9: ++ return "dup\t%0, %1.<v>[0]"; ++ default: ++ gcc_unreachable (); ++ } ++} + [(set_attr "v8type" "move,alu,alu,load1,load1,store1,store1,*,*,*") + (set_attr "simd_type" "*,*,simd_move_imm,*,*,*,*,simd_movgp,simd_dupgp,simd_dup") + (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes") (set_attr "mode" "<MODE>") (set_attr "simd_mode" "<MODE>")] ) -@@ -797,26 +809,28 @@ +@@ -797,26 +826,28 @@ ) (define_insn "*movsi_aarch64" @@ -10801,12 +13871,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "*movdi_aarch64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,m, r, r, *w, r,*w,w") - (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,m,rZ,Usa,Ush,rZ,*w,*w,Dd"))] -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,*w,m, m,r, r, *w, r,*w,w") -+ (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,m, m,rZ,*w,Usa,Ush,rZ,*w,*w,Dd"))] ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,*w,m, m,r,r, *w, r,*w,w") ++ (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,m, m,rZ,*w,S,Ush,rZ,*w,*w,Dd"))] "(register_operand (operands[0], DImode) || aarch64_reg_or_zero (operands[1], DImode))" "@ -@@ -825,16 +839,18 @@ +@@ -825,16 +856,18 @@ mov\\t%x0, %1 mov\\t%x0, %1 ldr\\t%x0, %1 @@ -10827,7 +13897,19 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ) (define_insn "insv_imm<mode>" -@@ -1149,13 +1165,14 @@ +@@ -842,9 +875,8 @@ + (const_int 16) + (match_operand:GPI 1 "const_int_operand" "n")) + (match_operand:GPI 2 "const_int_operand" "n"))] +- "INTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode) +- && INTVAL (operands[1]) % 16 == 0 +- && UINTVAL (operands[2]) <= 0xffff" ++ "UINTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode) ++ && UINTVAL (operands[1]) % 16 == 0" + "movk\\t%<w>0, %X2, lsl %1" + [(set_attr "v8type" "movk") + (set_attr "mode" "<MODE>")] +@@ -1149,13 +1181,14 @@ ) (define_insn "*zero_extend<SHORT:mode><GPI:mode>2_aarch64" @@ -10846,7 +13928,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (set_attr "mode" "<GPI:MODE>")] ) -@@ -1286,6 +1303,112 @@ +@@ -1286,6 +1319,112 @@ (set_attr "mode" "SI")] ) @@ -10959,7 +14041,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "*add<mode>3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ -@@ -1790,6 +1913,34 @@ +@@ -1790,6 +1929,34 @@ (set_attr "mode" "SI")] ) @@ -10994,7 +14076,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "*sub_uxt<mode>_multp2" [(set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_operand:GPI 4 "register_operand" "r") -@@ -1843,6 +1994,27 @@ +@@ -1843,6 +2010,27 @@ (set_attr "mode" "SI")] ) @@ -11022,7 +14104,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "*neg<mode>2_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ (neg:GPI (match_operand:GPI 1 "register_operand" "r")) -@@ -1868,6 +2040,21 @@ +@@ -1868,6 +2056,21 @@ (set_attr "mode" "SI")] ) @@ -11044,7 +14126,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "*neg_<shift>_<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (neg:GPI (ASHIFT:GPI -@@ -2157,6 +2344,18 @@ +@@ -2157,6 +2360,18 @@ (set_attr "mode" "<GPI:MODE>")] ) @@ -11063,7 +14145,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; ------------------------------------------------------------------- ;; Store-flag and conditional select insns -@@ -2210,7 +2409,7 @@ +@@ -2210,7 +2425,7 @@ (set_attr "mode" "SI")] ) @@ -11072,7 +14154,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set (match_operand:ALLI 0 "register_operand" "=r") (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)])))] -@@ -2433,6 +2632,69 @@ +@@ -2433,6 +2648,69 @@ [(set_attr "v8type" "logic,logic_imm") (set_attr "mode" "SI")]) @@ -11142,7 +14224,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI -@@ -2703,6 +2965,62 @@ +@@ -2703,6 +2981,62 @@ (set_attr "mode" "<MODE>")] ) @@ -11205,7 +14287,58 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>" [(set (match_operand:GPI 0 "register_operand" "=r") (ANY_EXTEND:GPI -@@ -3089,6 +3407,27 @@ +@@ -2769,6 +3103,50 @@ + (set_attr "mode" "<MODE>")] + ) + ++;; Bitfield Insert (insv) ++(define_expand "insv<mode>" ++ [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand") ++ (match_operand 1 "const_int_operand") ++ (match_operand 2 "const_int_operand")) ++ (match_operand:GPI 3 "general_operand"))] ++ "" ++{ ++ unsigned HOST_WIDE_INT width = UINTVAL (operands[1]); ++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); ++ rtx value = operands[3]; ++ ++ if (width == 0 || (pos + width) > GET_MODE_BITSIZE (<MODE>mode)) ++ FAIL; ++ ++ if (CONST_INT_P (value)) ++ { ++ unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; ++ ++ /* Prefer AND/OR for inserting all zeros or all ones. */ ++ if ((UINTVAL (value) & mask) == 0 ++ || (UINTVAL (value) & mask) == mask) ++ FAIL; ++ ++ /* 16-bit aligned 16-bit wide insert is handled by insv_imm. */ ++ if (width == 16 && (pos % 16) == 0) ++ DONE; ++ } ++ operands[3] = force_reg (<MODE>mode, value); ++}) ++ ++(define_insn "*insv_reg<mode>" ++ [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") ++ (match_operand 1 "const_int_operand" "n") ++ (match_operand 2 "const_int_operand" "n")) ++ (match_operand:GPI 3 "register_operand" "r"))] ++ "!(UINTVAL (operands[1]) == 0 ++ || (UINTVAL (operands[2]) + UINTVAL (operands[1]) ++ > GET_MODE_BITSIZE (<MODE>mode)))" ++ "bfi\\t%<w>0, %<w>3, %2, %1" ++ [(set_attr "v8type" "bfm") ++ (set_attr "mode" "<MODE>")] ++) ++ + (define_insn "*<optab><ALLX:mode>_shft_<GPI:mode>" + [(set (match_operand:GPI 0 "register_operand" "=r") + (ashift:GPI (ANY_EXTEND:GPI +@@ -3089,6 +3467,27 @@ (set_attr "mode" "<MODE>")] ) @@ -11564,7 +14697,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ }; char namebuf[60]; tree ftype = NULL; -@@ -1258,19 +1227,19 @@ +@@ -1258,30 +1227,82 @@ && in_mode == N##Fmode && in_n == C) case BUILT_IN_FLOOR: case BUILT_IN_FLOORF: @@ -11589,7 +14722,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ case BUILT_IN_SQRT: case BUILT_IN_SQRTF: return AARCH64_FIND_FRINT_VARIANT (sqrt); -@@ -1279,9 +1248,51 @@ + #undef AARCH64_CHECK_BUILTIN_MODE + #define AARCH64_CHECK_BUILTIN_MODE(C, N) \ ++ (out_mode == SImode && out_n == C \ ++ && in_mode == N##Imode && in_n == C) ++ case BUILT_IN_CLZ: ++ { ++ if (AARCH64_CHECK_BUILTIN_MODE (4, S)) ++ return aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_clzv4si]; ++ return NULL_TREE; ++ } ++#undef AARCH64_CHECK_BUILTIN_MODE ++#define AARCH64_CHECK_BUILTIN_MODE(C, N) \ (out_mode == N##Imode && out_n == C \ && in_mode == N##Fmode && in_n == C) case BUILT_IN_LFLOOR: @@ -11643,7 +14787,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ default: return NULL_TREE; } -@@ -1289,5 +1300,145 @@ +@@ -1289,5 +1310,160 @@ return NULL_TREE; } @@ -11712,13 +14856,28 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + + switch (fcode) + { -+ BUILTIN_VDQF (UNOP, addv, 0) ++ BUILTIN_VALL (UNOP, reduc_splus_, 10) + new_stmt = gimple_build_assign_with_ops ( + REDUC_PLUS_EXPR, + gimple_call_lhs (stmt), + args[0], + NULL_TREE); + break; ++ BUILTIN_VDQIF (UNOP, reduc_smax_, 10) ++ new_stmt = gimple_build_assign_with_ops ( ++ REDUC_MAX_EXPR, ++ gimple_call_lhs (stmt), ++ args[0], ++ NULL_TREE); ++ break; ++ BUILTIN_VDQIF (UNOP, reduc_smin_, 10) ++ new_stmt = gimple_build_assign_with_ops ( ++ REDUC_MIN_EXPR, ++ gimple_call_lhs (stmt), ++ args[0], ++ NULL_TREE); ++ break; ++ + default: + break; + } @@ -11791,7 +14950,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + --- a/src/gcc/config/aarch64/aarch64-protos.h +++ b/src/gcc/config/aarch64/aarch64-protos.h -@@ -140,6 +140,7 @@ +@@ -81,6 +81,7 @@ + SYMBOL_SMALL_TLSDESC, + SYMBOL_SMALL_GOTTPREL, + SYMBOL_SMALL_TPREL, ++ SYMBOL_TINY_ABSOLUTE, + SYMBOL_FORCE_TO_MEM + }; + +@@ -140,18 +141,26 @@ bool aarch64_float_const_zero_rtx_p (rtx); bool aarch64_function_arg_regno_p (unsigned); bool aarch64_gen_movmemqi (rtx *); @@ -11799,15 +14966,26 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ bool aarch64_is_extend_from_extract (enum machine_mode, rtx, rtx); bool aarch64_is_long_call_p (rtx); bool aarch64_label_mentioned_p (rtx); -@@ -151,6 +152,7 @@ + bool aarch64_legitimate_pic_operand_p (rtx); + bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode); ++bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context, ++ enum machine_mode); ++char *aarch64_output_scalar_simd_mov_immediate (rtx, enum machine_mode); ++char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned); + bool aarch64_pad_arg_upward (enum machine_mode, const_tree); + bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool); + bool aarch64_regno_ok_for_base_p (int, bool); bool aarch64_regno_ok_for_index_p (int, bool); bool aarch64_simd_imm_scalar_p (rtx x, enum machine_mode mode); bool aarch64_simd_imm_zero_p (rtx, enum machine_mode); +bool aarch64_simd_scalar_immediate_valid_for_move (rtx, enum machine_mode); bool aarch64_simd_shift_imm_p (rtx, enum machine_mode, bool); ++bool aarch64_simd_valid_immediate (rtx, enum machine_mode, bool, ++ struct simd_immediate_info *); bool aarch64_symbolic_address_p (rtx); bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context, -@@ -177,6 +179,7 @@ + enum aarch64_symbol_type *); +@@ -177,6 +186,7 @@ bool aarch64_simd_mem_operand_p (rtx); rtx aarch64_simd_vect_par_cnst_half (enum machine_mode, bool); rtx aarch64_tls_get_addr (void); @@ -11815,9 +14993,25 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ unsigned aarch64_dbx_register_number (unsigned); unsigned aarch64_trampoline_size (void); void aarch64_asm_output_labelref (FILE *, const char *); +@@ -216,6 +226,8 @@ + + bool aarch64_split_128bit_move_p (rtx, rtx); + ++void aarch64_split_simd_move (rtx, rtx); ++ + /* Check for a legitimate floating point constant for FMOV. */ + bool aarch64_float_const_representable_p (rtx); + +@@ -249,6 +261,4 @@ + extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); + extern bool + aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); +- +-char* aarch64_output_simd_mov_immediate (rtx *, enum machine_mode, unsigned); + #endif /* GCC_AARCH64_PROTOS_H */ --- a/src/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def -@@ -18,241 +18,329 @@ +@@ -18,241 +18,339 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ @@ -11881,6 +15075,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + BUILTIN_VDQF (UNOP, sqrt, 2) + BUILTIN_VD_BHSI (BINOP, addp, 0) + VAR1 (UNOP, addp, 0, di) ++ VAR1 (UNOP, clz, 2, v4si) + + BUILTIN_VD_RE (REINTERP, reinterpretdi, 0) + BUILTIN_VDC (REINTERP, reinterpretv8qi, 0) @@ -12197,7 +15392,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0) + BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0) - /* Implemented by aarch64_<fmaxmin><mode>. */ +- /* Implemented by aarch64_<fmaxmin><mode>. */ - BUILTIN_VDQF (BINOP, fmax) - BUILTIN_VDQF (BINOP, fmin) - /* Implemented by aarch64_<maxmin><mode>. */ @@ -12205,8 +15400,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ - BUILTIN_VDQ_BHSI (BINOP, smin) - BUILTIN_VDQ_BHSI (BINOP, umax) - BUILTIN_VDQ_BHSI (BINOP, umin) -+ BUILTIN_VDQF (BINOP, fmax, 0) -+ BUILTIN_VDQF (BINOP, fmin, 0) ++ /* Implemented by reduc_<sur>plus_<mode>. */ ++ BUILTIN_VALL (UNOP, reduc_splus_, 10) ++ BUILTIN_VDQ (UNOP, reduc_uplus_, 10) - /* Implemented by aarch64_frint<frint_suffix><mode>. */ - BUILTIN_VDQF (UNOP, frintz) @@ -12215,8 +15411,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ - BUILTIN_VDQF (UNOP, frinti) - BUILTIN_VDQF (UNOP, frintx) - BUILTIN_VDQF (UNOP, frinta) -+ /* Implemented by aarch64_addv<mode>. */ -+ BUILTIN_VDQF (UNOP, addv, 0) ++ /* Implemented by reduc_<maxmin_uns>_<mode>. */ ++ BUILTIN_VDQIF (UNOP, reduc_smax_, 10) ++ BUILTIN_VDQIF (UNOP, reduc_smin_, 10) ++ BUILTIN_VDQ_BHSI (UNOP, reduc_umax_, 10) ++ BUILTIN_VDQ_BHSI (UNOP, reduc_umin_, 10) ++ BUILTIN_VDQF (UNOP, reduc_smax_nan_, 10) ++ BUILTIN_VDQF (UNOP, reduc_smin_nan_, 10) - /* Implemented by aarch64_fcvt<frint_suffix><su><mode>. */ - BUILTIN_VDQF (UNOP, fcvtzs) @@ -12227,11 +15428,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ - BUILTIN_VDQF (UNOP, fcvtpu) - BUILTIN_VDQF (UNOP, fcvtms) - BUILTIN_VDQF (UNOP, fcvtmu) -+ /* Implemented by <maxmin><mode>3. */ -+ BUILTIN_VDQ_BHSI (BINOP, smax, 3) -+ BUILTIN_VDQ_BHSI (BINOP, smin, 3) ++ /* Implemented by <maxmin><mode>3. ++ smax variants map to fmaxnm, ++ smax_nan variants map to fmax. */ ++ BUILTIN_VDQIF (BINOP, smax, 3) ++ BUILTIN_VDQIF (BINOP, smin, 3) + BUILTIN_VDQ_BHSI (BINOP, umax, 3) + BUILTIN_VDQ_BHSI (BINOP, umin, 3) ++ BUILTIN_VDQF (BINOP, smax_nan, 3) ++ BUILTIN_VDQF (BINOP, smin_nan, 3) + /* Implemented by <frint_pattern><mode>2. */ + BUILTIN_VDQF (UNOP, btrunc, 2) @@ -12338,9 +15543,27 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + VAR1 (UNOP, float_truncate_lo_, 0, v2sf) --- a/src/gcc/config/aarch64/constraints.md +++ b/src/gcc/config/aarch64/constraints.md -@@ -152,6 +152,22 @@ - NULL, NULL, NULL, - NULL, NULL) != 0"))) +@@ -75,11 +75,6 @@ + "Integer constant zero." + (match_test "op == const0_rtx")) + +-(define_constraint "Usa" +- "A constraint that matches an absolute symbolic address." +- (and (match_code "const,symbol_ref") +- (match_test "aarch64_symbolic_address_p (op)"))) +- + (define_constraint "Ush" + "A constraint that matches an absolute symbolic address high part." + (and (match_code "high") +@@ -148,10 +143,25 @@ + "@internal + A constraint that matches vector of immediates." + (and (match_code "const_vector") +- (match_test "aarch64_simd_immediate_valid_for_move (op, GET_MODE (op), +- NULL, NULL, NULL, +- NULL, NULL) != 0"))) ++ (match_test "aarch64_simd_valid_immediate (op, GET_MODE (op), ++ false, NULL)"))) +(define_constraint "Dh" + "@internal @@ -12363,7 +15586,106 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ A constraint that matches vector of immediates for left shifts." --- a/src/gcc/config/aarch64/aarch64.c +++ b/src/gcc/config/aarch64/aarch64.c -@@ -3087,7 +3087,8 @@ +@@ -87,6 +87,14 @@ + enum aarch64_symbol_type symbol_type; + }; + ++struct simd_immediate_info ++{ ++ rtx value; ++ int shift; ++ int element_width; ++ bool mvn; ++}; ++ + /* The current code model. */ + enum aarch64_code_model aarch64_cmodel; + +@@ -103,8 +111,6 @@ + static void aarch64_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; + static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; + static void aarch64_override_options_after_change (void); +-static int aarch64_simd_valid_immediate (rtx, enum machine_mode, int, rtx *, +- int *, unsigned char *, int *, int *); + static bool aarch64_vector_mode_supported_p (enum machine_mode); + static unsigned bit_count (unsigned HOST_WIDE_INT); + static bool aarch64_const_vec_all_same_int_p (rtx, +@@ -524,13 +530,15 @@ + return; + } + ++ case SYMBOL_TINY_ABSOLUTE: ++ emit_insn (gen_rtx_SET (Pmode, dest, imm)); ++ return; ++ + case SYMBOL_SMALL_GOT: + { + rtx tmp_reg = dest; + if (can_create_pseudo_p ()) +- { +- tmp_reg = gen_reg_rtx (Pmode); +- } ++ tmp_reg = gen_reg_rtx (Pmode); + emit_move_insn (tmp_reg, gen_rtx_HIGH (Pmode, imm)); + emit_insn (gen_ldr_got_small (dest, tmp_reg, imm)); + return; +@@ -656,6 +664,47 @@ + || ! (FP_REGNUM_P (REGNO (dst)) && FP_REGNUM_P (REGNO (src)))); + } + ++/* Split a complex SIMD move. */ ++ ++void ++aarch64_split_simd_move (rtx dst, rtx src) ++{ ++ enum machine_mode src_mode = GET_MODE (src); ++ enum machine_mode dst_mode = GET_MODE (dst); ++ ++ gcc_assert (VECTOR_MODE_P (dst_mode)); ++ ++ if (REG_P (dst) && REG_P (src)) ++ { ++ gcc_assert (VECTOR_MODE_P (src_mode)); ++ ++ switch (src_mode) ++ { ++ case V16QImode: ++ emit_insn (gen_aarch64_simd_movv16qi (dst, src)); ++ break; ++ case V8HImode: ++ emit_insn (gen_aarch64_simd_movv8hi (dst, src)); ++ break; ++ case V4SImode: ++ emit_insn (gen_aarch64_simd_movv4si (dst, src)); ++ break; ++ case V2DImode: ++ emit_insn (gen_aarch64_simd_movv2di (dst, src)); ++ break; ++ case V4SFmode: ++ emit_insn (gen_aarch64_simd_movv4sf (dst, src)); ++ break; ++ case V2DFmode: ++ emit_insn (gen_aarch64_simd_movv2df (dst, src)); ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ return; ++ } ++} ++ + static rtx + aarch64_force_temporary (rtx x, rtx value) + { +@@ -745,6 +794,7 @@ + + case SYMBOL_SMALL_TPREL: + case SYMBOL_SMALL_ABSOLUTE: ++ case SYMBOL_TINY_ABSOLUTE: + aarch64_load_symref_appropriately (dest, imm, sty); + return; + +@@ -3087,7 +3137,8 @@ if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) && y == const0_rtx && (code == EQ || code == NE || code == LT || code == GE) @@ -12373,7 +15695,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ return CC_NZmode; /* A compare with a shifted operand. Because of canonicalization, -@@ -3349,7 +3350,7 @@ +@@ -3349,7 +3400,7 @@ output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code); return; } @@ -12382,7 +15704,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ break; case 'S': -@@ -3362,8 +3363,7 @@ +@@ -3362,18 +3413,17 @@ output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code); return; } @@ -12392,7 +15714,19 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ break; case 'X': -@@ -3383,20 +3383,19 @@ +- /* Print integer constant in hex. */ ++ /* Print bottom 16 bits of integer constant in hex. */ + if (GET_CODE (x) != CONST_INT) + { + output_operand_lossage ("invalid operand for '%%%c'", code); + return; + } +- asm_fprintf (f, "0x%wx", UINTVAL (x)); ++ asm_fprintf (f, "0x%wx", UINTVAL (x) & 0xffff); + break; + + case 'w': +@@ -3383,20 +3433,19 @@ if (x == const0_rtx || (CONST_DOUBLE_P (x) && aarch64_float_const_zero_rtx_p (x))) { @@ -12416,7 +15750,408 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ break; } -@@ -6409,6 +6408,21 @@ +@@ -4956,6 +5005,7 @@ + + /* Return the method that should be used to access SYMBOL_REF or + LABEL_REF X in context CONTEXT. */ ++ + enum aarch64_symbol_type + aarch64_classify_symbol (rtx x, + enum aarch64_symbol_context context ATTRIBUTE_UNUSED) +@@ -4969,6 +5019,8 @@ + + case AARCH64_CMODEL_TINY_PIC: + case AARCH64_CMODEL_TINY: ++ return SYMBOL_TINY_ABSOLUTE; ++ + case AARCH64_CMODEL_SMALL_PIC: + case AARCH64_CMODEL_SMALL: + return SYMBOL_SMALL_ABSOLUTE; +@@ -4978,48 +5030,42 @@ + } + } + +- gcc_assert (GET_CODE (x) == SYMBOL_REF); +- +- switch (aarch64_cmodel) ++ if (GET_CODE (x) == SYMBOL_REF) + { +- case AARCH64_CMODEL_LARGE: +- return SYMBOL_FORCE_TO_MEM; +- +- case AARCH64_CMODEL_TINY: +- case AARCH64_CMODEL_SMALL: +- +- /* This is needed to get DFmode, TImode constants to be loaded off +- the constant pool. Is it necessary to dump TImode values into +- the constant pool. We don't handle TImode constant loads properly +- yet and hence need to use the constant pool. */ +- if (CONSTANT_POOL_ADDRESS_P (x)) ++ if (aarch64_cmodel == AARCH64_CMODEL_LARGE ++ || CONSTANT_POOL_ADDRESS_P (x)) + return SYMBOL_FORCE_TO_MEM; + + if (aarch64_tls_symbol_p (x)) + return aarch64_classify_tls_symbol (x); + +- if (SYMBOL_REF_WEAK (x)) +- return SYMBOL_FORCE_TO_MEM; ++ switch (aarch64_cmodel) ++ { ++ case AARCH64_CMODEL_TINY: ++ if (SYMBOL_REF_WEAK (x)) ++ return SYMBOL_FORCE_TO_MEM; ++ return SYMBOL_TINY_ABSOLUTE; + +- return SYMBOL_SMALL_ABSOLUTE; ++ case AARCH64_CMODEL_SMALL: ++ if (SYMBOL_REF_WEAK (x)) ++ return SYMBOL_FORCE_TO_MEM; ++ return SYMBOL_SMALL_ABSOLUTE; + +- case AARCH64_CMODEL_TINY_PIC: +- case AARCH64_CMODEL_SMALL_PIC: ++ case AARCH64_CMODEL_TINY_PIC: ++ if (!aarch64_symbol_binds_local_p (x)) ++ return SYMBOL_SMALL_GOT; ++ return SYMBOL_TINY_ABSOLUTE; + +- if (CONSTANT_POOL_ADDRESS_P (x)) +- return SYMBOL_FORCE_TO_MEM; ++ case AARCH64_CMODEL_SMALL_PIC: ++ if (!aarch64_symbol_binds_local_p (x)) ++ return SYMBOL_SMALL_GOT; ++ return SYMBOL_SMALL_ABSOLUTE; + +- if (aarch64_tls_symbol_p (x)) +- return aarch64_classify_tls_symbol (x); ++ default: ++ gcc_unreachable (); ++ } ++ } + +- if (!aarch64_symbol_binds_local_p (x)) +- return SYMBOL_SMALL_GOT; +- +- return SYMBOL_SMALL_ABSOLUTE; +- +- default: +- gcc_unreachable (); +- } + /* By default push everything into the constant pool. */ + return SYMBOL_FORCE_TO_MEM; + } +@@ -5092,8 +5138,7 @@ + /* This could probably go away because + we now decompose CONST_INTs according to expand_mov_immediate. */ + if ((GET_CODE (x) == CONST_VECTOR +- && aarch64_simd_valid_immediate (x, mode, false, +- NULL, NULL, NULL, NULL, NULL) != -1) ++ && aarch64_simd_valid_immediate (x, mode, false, NULL)) + || CONST_INT_P (x) || aarch64_valid_floating_const (mode, x)) + return !targetm.cannot_force_const_mem (mode, x); + +@@ -5924,32 +5969,57 @@ + return false; + } + +-/* Return quad mode as the preferred SIMD mode. */ ++/* Return appropriate SIMD container ++ for MODE within a vector of WIDTH bits. */ + static enum machine_mode +-aarch64_preferred_simd_mode (enum machine_mode mode) ++aarch64_simd_container_mode (enum machine_mode mode, unsigned width) + { ++ gcc_assert (width == 64 || width == 128); + if (TARGET_SIMD) +- switch (mode) +- { +- case DFmode: +- return V2DFmode; +- case SFmode: +- return V4SFmode; +- case SImode: +- return V4SImode; +- case HImode: +- return V8HImode; +- case QImode: +- return V16QImode; +- case DImode: +- return V2DImode; +- break; +- +- default:; +- } ++ { ++ if (width == 128) ++ switch (mode) ++ { ++ case DFmode: ++ return V2DFmode; ++ case SFmode: ++ return V4SFmode; ++ case SImode: ++ return V4SImode; ++ case HImode: ++ return V8HImode; ++ case QImode: ++ return V16QImode; ++ case DImode: ++ return V2DImode; ++ default: ++ break; ++ } ++ else ++ switch (mode) ++ { ++ case SFmode: ++ return V2SFmode; ++ case SImode: ++ return V2SImode; ++ case HImode: ++ return V4HImode; ++ case QImode: ++ return V8QImode; ++ default: ++ break; ++ } ++ } + return word_mode; + } + ++/* Return 128-bit container as the preferred SIMD mode for MODE. */ ++static enum machine_mode ++aarch64_preferred_simd_mode (enum machine_mode mode) ++{ ++ return aarch64_simd_container_mode (mode, 128); ++} ++ + /* Return the bitmask of possible vector sizes for the vectorizer + to iterate over. */ + static unsigned int +@@ -6037,7 +6107,7 @@ + } + + /* Return the equivalent letter for size. */ +-static unsigned char ++static char + sizetochar (int size) + { + switch (size) +@@ -6084,15 +6154,10 @@ + return aarch64_float_const_representable_p (x0); + } + +-/* TODO: This function returns values similar to those +- returned by neon_valid_immediate in gcc/config/arm/arm.c +- but the API here is different enough that these magic numbers +- are not used. It should be sufficient to return true or false. */ +-static int +-aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, int inverse, +- rtx *modconst, int *elementwidth, +- unsigned char *elementchar, +- int *mvn, int *shift) ++/* Return true for valid and false for invalid. */ ++bool ++aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse, ++ struct simd_immediate_info *info) + { + #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \ + matches = 1; \ +@@ -6103,7 +6168,6 @@ + { \ + immtype = (CLASS); \ + elsize = (ELSIZE); \ +- elchar = sizetochar (elsize); \ + eshift = (SHIFT); \ + emvn = (NEG); \ + break; \ +@@ -6112,36 +6176,25 @@ + unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); + unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); + unsigned char bytes[16]; +- unsigned char elchar = 0; + int immtype = -1, matches; + unsigned int invmask = inverse ? 0xff : 0; + int eshift, emvn; + + if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) + { +- bool simd_imm_zero = aarch64_simd_imm_zero_p (op, mode); +- int elem_width = GET_MODE_BITSIZE (GET_MODE (CONST_VECTOR_ELT (op, 0))); ++ if (! (aarch64_simd_imm_zero_p (op, mode) ++ || aarch64_vect_float_const_representable_p (op))) ++ return false; + +- if (!(simd_imm_zero +- || aarch64_vect_float_const_representable_p (op))) +- return -1; ++ if (info) ++ { ++ info->value = CONST_VECTOR_ELT (op, 0); ++ info->element_width = GET_MODE_BITSIZE (GET_MODE (info->value)); ++ info->mvn = false; ++ info->shift = 0; ++ } + +- if (modconst) +- *modconst = CONST_VECTOR_ELT (op, 0); +- +- if (elementwidth) +- *elementwidth = elem_width; +- +- if (elementchar) +- *elementchar = sizetochar (elem_width); +- +- if (shift) +- *shift = 0; +- +- if (simd_imm_zero) +- return 19; +- else +- return 18; ++ return true; + } + + /* Splat vector constant out into a byte vector. */ +@@ -6239,23 +6292,14 @@ + if (immtype == -1 + || (immtype >= 12 && immtype <= 15) + || immtype == 18) +- return -1; ++ return false; + ++ if (info) ++ { ++ info->element_width = elsize; ++ info->mvn = emvn != 0; ++ info->shift = eshift; + +- if (elementwidth) +- *elementwidth = elsize; +- +- if (elementchar) +- *elementchar = elchar; +- +- if (mvn) +- *mvn = emvn; +- +- if (shift) +- *shift = eshift; +- +- if (modconst) +- { + unsigned HOST_WIDE_INT imm = 0; + + /* Un-invert bytes of recognized vector, if necessary. */ +@@ -6272,68 +6316,27 @@ + imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) + << (i * BITS_PER_UNIT); + +- *modconst = GEN_INT (imm); +- } ++ ++ info->value = GEN_INT (imm); ++ } + else +- { +- unsigned HOST_WIDE_INT imm = 0; ++ { ++ for (i = 0; i < elsize / BITS_PER_UNIT; i++) ++ imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT); + +- for (i = 0; i < elsize / BITS_PER_UNIT; i++) +- imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT); +- + /* Construct 'abcdefgh' because the assembler cannot handle +- generic constants. */ +- gcc_assert (shift != NULL && mvn != NULL); +- if (*mvn) ++ generic constants. */ ++ if (info->mvn) + imm = ~imm; +- imm = (imm >> *shift) & 0xff; +- *modconst = GEN_INT (imm); +- } ++ imm = (imm >> info->shift) & 0xff; ++ info->value = GEN_INT (imm); ++ } + } + +- return immtype; ++ return true; + #undef CHECK + } + +-/* Return TRUE if rtx X is legal for use as either a AdvSIMD MOVI instruction +- (or, implicitly, MVNI) immediate. Write back width per element +- to *ELEMENTWIDTH, and a modified constant (whatever should be output +- for a MOVI instruction) in *MODCONST. */ +-int +-aarch64_simd_immediate_valid_for_move (rtx op, enum machine_mode mode, +- rtx *modconst, int *elementwidth, +- unsigned char *elementchar, +- int *mvn, int *shift) +-{ +- rtx tmpconst; +- int tmpwidth; +- unsigned char tmpwidthc; +- int tmpmvn = 0, tmpshift = 0; +- int retval = aarch64_simd_valid_immediate (op, mode, 0, &tmpconst, +- &tmpwidth, &tmpwidthc, +- &tmpmvn, &tmpshift); +- +- if (retval == -1) +- return 0; +- +- if (modconst) +- *modconst = tmpconst; +- +- if (elementwidth) +- *elementwidth = tmpwidth; +- +- if (elementchar) +- *elementchar = tmpwidthc; +- +- if (mvn) +- *mvn = tmpmvn; +- +- if (shift) +- *shift = tmpshift; +- +- return 1; +-} +- + static bool + aarch64_const_vec_all_same_int_p (rtx x, + HOST_WIDE_INT minval, +@@ -6395,6 +6398,25 @@ + return true; + } + ++bool ++aarch64_mov_operand_p (rtx x, ++ enum aarch64_symbol_context context, ++ enum machine_mode mode) ++{ ++ if (GET_CODE (x) == HIGH ++ && aarch64_valid_symref (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) ++ return true; ++ ++ if (CONST_INT_P (x) && aarch64_move_imm (INTVAL (x), mode)) ++ return true; ++ ++ if (GET_CODE (x) == SYMBOL_REF && mode == DImode && CONSTANT_ADDRESS_P (x)) ++ return true; ++ ++ return aarch64_classify_symbolic_expression (x, context) ++ == SYMBOL_TINY_ABSOLUTE; ++} ++ + /* Return a const_int vector of VAL. */ + rtx + aarch64_simd_gen_const_vector_dup (enum machine_mode mode, int val) +@@ -6409,6 +6431,19 @@ return gen_rtx_CONST_VECTOR (mode, v); } @@ -12430,15 +16165,125 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ + gcc_assert (!VECTOR_MODE_P (mode)); + vmode = aarch64_preferred_simd_mode (mode); + rtx op_v = aarch64_simd_gen_const_vector_dup (vmode, INTVAL (op)); -+ int retval = aarch64_simd_immediate_valid_for_move (op_v, vmode, 0, -+ NULL, NULL, NULL, NULL); -+ return retval; ++ return aarch64_simd_valid_immediate (op_v, vmode, false, NULL); +} + /* Construct and return a PARALLEL RTX vector. */ rtx aarch64_simd_vect_par_cnst_half (enum machine_mode mode, bool high) -@@ -7860,6 +7874,9 @@ +@@ -6634,8 +6669,7 @@ + gcc_unreachable (); + + if (const_vec != NULL_RTX +- && aarch64_simd_immediate_valid_for_move (const_vec, mode, NULL, NULL, +- NULL, NULL, NULL)) ++ && aarch64_simd_valid_immediate (const_vec, mode, false, NULL)) + /* Load using MOVI/MVNI. */ + return const_vec; + else if ((const_dup = aarch64_simd_dup_constant (vals)) != NULL_RTX) +@@ -7193,49 +7227,78 @@ + } + + char* +-aarch64_output_simd_mov_immediate (rtx *const_vector, ++aarch64_output_simd_mov_immediate (rtx const_vector, + enum machine_mode mode, + unsigned width) + { +- int is_valid; +- unsigned char widthc; +- int lane_width_bits; ++ bool is_valid; + static char templ[40]; +- int shift = 0, mvn = 0; + const char *mnemonic; + unsigned int lane_count = 0; ++ char element_char; + +- is_valid = +- aarch64_simd_immediate_valid_for_move (*const_vector, mode, +- const_vector, &lane_width_bits, +- &widthc, &mvn, &shift); ++ struct simd_immediate_info info; ++ ++ /* This will return true to show const_vector is legal for use as either ++ a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will ++ also update INFO to show how the immediate should be generated. */ ++ is_valid = aarch64_simd_valid_immediate (const_vector, mode, false, &info); + gcc_assert (is_valid); + ++ element_char = sizetochar (info.element_width); ++ lane_count = width / info.element_width; ++ + mode = GET_MODE_INNER (mode); + if (mode == SFmode || mode == DFmode) + { +- bool zero_p = +- aarch64_float_const_zero_rtx_p (*const_vector); +- gcc_assert (shift == 0); +- mnemonic = zero_p ? "movi" : "fmov"; ++ gcc_assert (info.shift == 0 && ! info.mvn); ++ if (aarch64_float_const_zero_rtx_p (info.value)) ++ info.value = GEN_INT (0); ++ else ++ { ++#define buf_size 20 ++ REAL_VALUE_TYPE r; ++ REAL_VALUE_FROM_CONST_DOUBLE (r, info.value); ++ char float_buf[buf_size] = {'\0'}; ++ real_to_decimal_for_mode (float_buf, &r, buf_size, buf_size, 1, mode); ++#undef buf_size ++ ++ if (lane_count == 1) ++ snprintf (templ, sizeof (templ), "fmov\t%%d0, %s", float_buf); ++ else ++ snprintf (templ, sizeof (templ), "fmov\t%%0.%d%c, %s", ++ lane_count, element_char, float_buf); ++ return templ; ++ } + } +- else +- mnemonic = mvn ? "mvni" : "movi"; + +- gcc_assert (lane_width_bits != 0); +- lane_count = width / lane_width_bits; ++ mnemonic = info.mvn ? "mvni" : "movi"; + + if (lane_count == 1) +- snprintf (templ, sizeof (templ), "%s\t%%d0, %%1", mnemonic); +- else if (shift) +- snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, %%1, lsl %d", +- mnemonic, lane_count, widthc, shift); ++ snprintf (templ, sizeof (templ), "%s\t%%d0, " HOST_WIDE_INT_PRINT_HEX, ++ mnemonic, UINTVAL (info.value)); ++ else if (info.shift) ++ snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX ++ ", lsl %d", mnemonic, lane_count, element_char, ++ UINTVAL (info.value), info.shift); + else +- snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, %%1", +- mnemonic, lane_count, widthc); ++ snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX, ++ mnemonic, lane_count, element_char, UINTVAL (info.value)); + return templ; + } + ++char* ++aarch64_output_scalar_simd_mov_immediate (rtx immediate, ++ enum machine_mode mode) ++{ ++ enum machine_mode vmode; ++ ++ gcc_assert (!VECTOR_MODE_P (mode)); ++ vmode = aarch64_simd_container_mode (mode, 64); ++ rtx v_op = aarch64_simd_gen_const_vector_dup (vmode, INTVAL (immediate)); ++ return aarch64_output_simd_mov_immediate (v_op, vmode, 64); ++} ++ + /* Split operands into moves from op[1] + op[2] into op[0]. */ + + void +@@ -7860,6 +7923,9 @@ #undef TARGET_EXPAND_BUILTIN_VA_START #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start @@ -12448,7 +16293,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ #undef TARGET_FUNCTION_ARG #define TARGET_FUNCTION_ARG aarch64_function_arg -@@ -7881,6 +7898,9 @@ +@@ -7881,6 +7947,9 @@ #undef TARGET_FRAME_POINTER_REQUIRED #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required @@ -12460,17 +16305,37 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ --- a/src/gcc/config/aarch64/iterators.md +++ b/src/gcc/config/aarch64/iterators.md -@@ -83,6 +83,9 @@ +@@ -83,6 +83,12 @@ ;; Vector Float modes. (define_mode_iterator VDQF [V2SF V4SF V2DF]) ++;; Modes suitable to use as the return type of a vcond expression. ++(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) ++ +;; All Float modes. +(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) + ;; Vector Float modes with 2 elements. (define_mode_iterator V2F [V2SF V2DF]) -@@ -213,13 +216,6 @@ +@@ -160,10 +166,15 @@ + [ + UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. + UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. ++ UNSPEC_FMAX ; Used in aarch64-simd.md. ++ UNSPEC_FMAXNMV ; Used in aarch64-simd.md. + UNSPEC_FMAXV ; Used in aarch64-simd.md. ++ UNSPEC_FMIN ; Used in aarch64-simd.md. ++ UNSPEC_FMINNMV ; Used in aarch64-simd.md. + UNSPEC_FMINV ; Used in aarch64-simd.md. + UNSPEC_FADDV ; Used in aarch64-simd.md. +- UNSPEC_ADDV ; Used in aarch64-simd.md. ++ UNSPEC_SADDV ; Used in aarch64-simd.md. ++ UNSPEC_UADDV ; Used in aarch64-simd.md. + UNSPEC_SMAXV ; Used in aarch64-simd.md. + UNSPEC_SMINV ; Used in aarch64-simd.md. + UNSPEC_UMAXV ; Used in aarch64-simd.md. +@@ -213,13 +224,6 @@ UNSPEC_URSHL ; Used in aarch64-simd.md. UNSPEC_SQRSHL ; Used in aarch64-simd.md. UNSPEC_UQRSHL ; Used in aarch64-simd.md. @@ -12484,18 +16349,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ UNSPEC_SSLI ; Used in aarch64-simd.md. UNSPEC_USLI ; Used in aarch64-simd.md. UNSPEC_SSRI ; Used in aarch64-simd.md. -@@ -227,10 +223,8 @@ +@@ -227,10 +231,6 @@ UNSPEC_SSHLL ; Used in aarch64-simd.md. UNSPEC_USHLL ; Used in aarch64-simd.md. UNSPEC_ADDP ; Used in aarch64-simd.md. - UNSPEC_CMTST ; Used in aarch64-simd.md. - UNSPEC_FMAX ; Used in aarch64-simd.md. - UNSPEC_FMIN ; Used in aarch64-simd.md. +- UNSPEC_FMAX ; Used in aarch64-simd.md. +- UNSPEC_FMIN ; Used in aarch64-simd.md. - UNSPEC_BSL ; Used in aarch64-simd.md. UNSPEC_TBL ; Used in vector permute patterns. UNSPEC_CONCAT ; Used in vector permute patterns. UNSPEC_ZIP1 ; Used in vector permute patterns. -@@ -249,8 +243,12 @@ +@@ -249,8 +249,12 @@ ;; 32-bit version and "%x0" in the 64-bit version. (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) @@ -12508,7 +16373,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (V8QI "") (V16QI "") (V4HI "") (V8HI "") (V2SI "") (V4SI "") -@@ -305,7 +303,8 @@ +@@ -305,7 +309,8 @@ (V4SF ".4s") (V2DF ".2d") (DI "") (SI "") (HI "") (QI "") @@ -12518,7 +16383,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; Register suffix narrowed modes for VQN. (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") -@@ -444,7 +443,8 @@ +@@ -444,7 +449,8 @@ (V2SI "V2SI") (V4SI "V4SI") (DI "DI") (V2DI "V2DI") (V2SF "V2SI") (V4SF "V4SI") @@ -12528,7 +16393,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; Lower case mode of results of comparison operations. (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") -@@ -452,7 +452,8 @@ +@@ -452,7 +458,8 @@ (V2SI "v2si") (V4SI "v4si") (DI "di") (V2DI "v2di") (V2SF "v2si") (V4SF "v4si") @@ -12538,7 +16403,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") -@@ -528,6 +529,9 @@ +@@ -528,9 +535,14 @@ ;; Iterator for integer conversions (define_code_iterator FIXUORS [fix unsigned_fix]) @@ -12548,7 +16413,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; Code iterator for variants of vector max and min. (define_code_iterator MAXMIN [smax smin umax umin]) -@@ -543,6 +547,15 @@ ++(define_code_iterator FMAXMIN [smax smin]) ++ + ;; Code iterator for variants of vector max and min. + (define_code_iterator ADDSUB [plus minus]) + +@@ -543,6 +555,15 @@ ;; Code iterator for signed variants of vector saturating binary ops. (define_code_iterator SBINQOPS [ss_plus ss_minus]) @@ -12564,7 +16434,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; ------------------------------------------------------------------- ;; Code Attributes ;; ------------------------------------------------------------------- -@@ -555,6 +568,10 @@ +@@ -555,6 +576,10 @@ (zero_extend "zero_extend") (sign_extract "extv") (zero_extract "extzv") @@ -12575,7 +16445,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (and "and") (ior "ior") (xor "xor") -@@ -571,12 +588,37 @@ +@@ -571,12 +596,37 @@ (eq "eq") (ne "ne") (lt "lt") @@ -12614,7 +16484,55 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (ss_plus "s") (us_plus "u") (ss_minus "s") (us_minus "u")]) -@@ -680,21 +722,19 @@ +@@ -601,7 +651,9 @@ + (define_code_attr su [(sign_extend "s") (zero_extend "u") + (sign_extract "s") (zero_extract "u") + (fix "s") (unsigned_fix "u") +- (div "s") (udiv "u")]) ++ (div "s") (udiv "u") ++ (smax "s") (umax "u") ++ (smin "s") (umin "u")]) + + ;; Emit cbz/cbnz depending on comparison type. + (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) +@@ -610,10 +662,10 @@ + (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) + + ;; Max/min attributes. +-(define_code_attr maxmin [(smax "smax") +- (smin "smin") +- (umax "umax") +- (umin "umin")]) ++(define_code_attr maxmin [(smax "max") ++ (smin "min") ++ (umax "max") ++ (umin "min")]) + + ;; MLA/MLS attributes. + (define_code_attr as [(ss_plus "a") (ss_minus "s")]) +@@ -635,8 +687,11 @@ + (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV + UNSPEC_SMAXV UNSPEC_SMINV]) + +-(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV]) ++(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV ++ UNSPEC_FMAXNMV UNSPEC_FMINNMV]) + ++(define_int_iterator SUADDV [UNSPEC_SADDV UNSPEC_UADDV]) ++ + (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD + UNSPEC_SRHADD UNSPEC_URHADD + UNSPEC_SHSUB UNSPEC_UHSUB +@@ -649,7 +704,7 @@ + (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 + UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) + +-(define_int_iterator FMAXMIN [UNSPEC_FMAX UNSPEC_FMIN]) ++(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN]) + + (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) + +@@ -680,35 +735,44 @@ UNSPEC_SQSHRN UNSPEC_UQSHRN UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) @@ -12641,7 +16559,49 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; ------------------------------------------------------------------- ;; Int Iterators Attributes. ;; ------------------------------------------------------------------- -@@ -768,12 +808,6 @@ +-(define_int_attr maxminv [(UNSPEC_UMAXV "umax") +- (UNSPEC_UMINV "umin") +- (UNSPEC_SMAXV "smax") +- (UNSPEC_SMINV "smin")]) ++(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") ++ (UNSPEC_UMINV "umin") ++ (UNSPEC_SMAXV "smax") ++ (UNSPEC_SMINV "smin") ++ (UNSPEC_FMAX "smax_nan") ++ (UNSPEC_FMAXNMV "smax") ++ (UNSPEC_FMAXV "smax_nan") ++ (UNSPEC_FMIN "smin_nan") ++ (UNSPEC_FMINNMV "smin") ++ (UNSPEC_FMINV "smin_nan")]) + +-(define_int_attr fmaxminv [(UNSPEC_FMAXV "max") +- (UNSPEC_FMINV "min")]) ++(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") ++ (UNSPEC_UMINV "umin") ++ (UNSPEC_SMAXV "smax") ++ (UNSPEC_SMINV "smin") ++ (UNSPEC_FMAX "fmax") ++ (UNSPEC_FMAXNMV "fmaxnm") ++ (UNSPEC_FMAXV "fmax") ++ (UNSPEC_FMIN "fmin") ++ (UNSPEC_FMINNMV "fminnm") ++ (UNSPEC_FMINV "fmin")]) + +-(define_int_attr fmaxmin [(UNSPEC_FMAX "fmax") +- (UNSPEC_FMIN "fmin")]) +- + (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") + (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") + (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") +@@ -719,6 +783,7 @@ + (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") + (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") + (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") ++ (UNSPEC_SADDV "s") (UNSPEC_UADDV "u") + (UNSPEC_SSLI "s") (UNSPEC_USLI "u") + (UNSPEC_SSRI "s") (UNSPEC_USRI "u") + (UNSPEC_USRA "u") (UNSPEC_SSRA "s") +@@ -768,12 +833,6 @@ (UNSPEC_RADDHN2 "add") (UNSPEC_RSUBHN2 "sub")]) @@ -12654,7 +16614,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) -@@ -783,15 +817,18 @@ +@@ -783,15 +842,18 @@ (UNSPEC_FRINTM "floor") (UNSPEC_FRINTI "nearbyint") (UNSPEC_FRINTX "rint") @@ -12676,7 +16636,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") -@@ -800,3 +837,5 @@ +@@ -800,3 +862,5 @@ (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) @@ -12846,7 +16806,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ }; -@@ -2129,6 +2153,12 @@ +@@ -2129,11 +2153,25 @@ global_options.x_param_values, global_options_set.x_param_values); @@ -12859,7 +16819,20 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* Use the alternative scheduling-pressure algorithm by default. */ maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2, global_options.x_param_values, -@@ -2382,6 +2412,10 @@ + global_options_set.x_param_values); + ++ /* Disable shrink-wrap when optimizing function for size, since it tends to ++ generate additional returns. */ ++ if (optimize_function_for_size_p (cfun) && TARGET_THUMB2) ++ flag_shrink_wrap = false; ++ /* TBD: Dwarf info for apcs frame is not handled yet. */ ++ if (TARGET_APCS_FRAME) ++ flag_shrink_wrap = false; ++ + /* Register global variables with the garbage collector. */ + arm_add_gc_roots (); + } +@@ -2382,6 +2420,10 @@ if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB)) return 0; @@ -12870,7 +16843,26 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ offsets = arm_get_frame_offsets (); stack_adjust = offsets->outgoing_args - offsets->saved_regs; -@@ -2617,6 +2651,9 @@ +@@ -2479,6 +2521,18 @@ + return 1; + } + ++/* Return TRUE if we should try to use a simple_return insn, i.e. perform ++ shrink-wrapping if possible. This is the case if we need to emit a ++ prologue, which we can test by looking at the offsets. */ ++bool ++use_simple_return_p (void) ++{ ++ arm_stack_offsets *offsets; ++ ++ offsets = arm_get_frame_offsets (); ++ return offsets->outgoing_args != 0; ++} ++ + /* Return TRUE if int I is a valid immediate ARM constant. */ + + int +@@ -2617,6 +2671,9 @@ switch (code) { @@ -12880,7 +16872,179 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ case PLUS: return arm_not_operand (hi, SImode) && arm_add_operand (lo, SImode); -@@ -12603,6 +12640,277 @@ +@@ -5335,9 +5392,8 @@ + if (cfun->machine->sibcall_blocked) + return false; + +- /* Never tailcall something for which we have no decl, or if we +- are generating code for Thumb-1. */ +- if (decl == NULL || TARGET_THUMB1) ++ /* Never tailcall something if we are generating code for Thumb-1. */ ++ if (TARGET_THUMB1) + return false; + + /* The PIC register is live on entry to VxWorks PLT entries, so we +@@ -5347,13 +5403,14 @@ + + /* Cannot tail-call to long calls, since these are out of range of + a branch instruction. */ +- if (arm_is_long_call_p (decl)) ++ if (decl && arm_is_long_call_p (decl)) + return false; + + /* If we are interworking and the function is not declared static + then we can't tail-call it unless we know that it exists in this + compilation unit (since it might be a Thumb routine). */ +- if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) ++ if (TARGET_INTERWORK && decl && TREE_PUBLIC (decl) ++ && !TREE_ASM_WRITTEN (decl)) + return false; + + func_type = arm_current_func_type (); +@@ -5385,6 +5442,7 @@ + sibling calls. */ + if (TARGET_AAPCS_BASED + && arm_abi == ARM_ABI_AAPCS ++ && decl + && DECL_WEAK (decl)) + return false; + +@@ -11803,6 +11861,134 @@ + return 1; + } + ++/* Helper for gen_movmem_ldrd_strd. Increase the address of memory rtx ++by mode size. */ ++inline static rtx ++next_consecutive_mem (rtx mem) ++{ ++ enum machine_mode mode = GET_MODE (mem); ++ HOST_WIDE_INT offset = GET_MODE_SIZE (mode); ++ rtx addr = plus_constant (Pmode, XEXP (mem, 0), offset); ++ ++ return adjust_automodify_address (mem, mode, addr, offset); ++} ++ ++/* Copy using LDRD/STRD instructions whenever possible. ++ Returns true upon success. */ ++bool ++gen_movmem_ldrd_strd (rtx *operands) ++{ ++ unsigned HOST_WIDE_INT len; ++ HOST_WIDE_INT align; ++ rtx src, dst, base; ++ rtx reg0; ++ bool src_aligned, dst_aligned; ++ bool src_volatile, dst_volatile; ++ ++ gcc_assert (CONST_INT_P (operands[2])); ++ gcc_assert (CONST_INT_P (operands[3])); ++ ++ len = UINTVAL (operands[2]); ++ if (len > 64) ++ return false; ++ ++ /* Maximum alignment we can assume for both src and dst buffers. */ ++ align = INTVAL (operands[3]); ++ ++ if ((!unaligned_access) && (len >= 4) && ((align & 3) != 0)) ++ return false; ++ ++ /* Place src and dst addresses in registers ++ and update the corresponding mem rtx. */ ++ dst = operands[0]; ++ dst_volatile = MEM_VOLATILE_P (dst); ++ dst_aligned = MEM_ALIGN (dst) >= BITS_PER_WORD; ++ base = copy_to_mode_reg (SImode, XEXP (dst, 0)); ++ dst = adjust_automodify_address (dst, VOIDmode, base, 0); ++ ++ src = operands[1]; ++ src_volatile = MEM_VOLATILE_P (src); ++ src_aligned = MEM_ALIGN (src) >= BITS_PER_WORD; ++ base = copy_to_mode_reg (SImode, XEXP (src, 0)); ++ src = adjust_automodify_address (src, VOIDmode, base, 0); ++ ++ if (!unaligned_access && !(src_aligned && dst_aligned)) ++ return false; ++ ++ if (src_volatile || dst_volatile) ++ return false; ++ ++ /* If we cannot generate any LDRD/STRD, try to generate LDM/STM. */ ++ if (!(dst_aligned || src_aligned)) ++ return arm_gen_movmemqi (operands); ++ ++ src = adjust_address (src, DImode, 0); ++ dst = adjust_address (dst, DImode, 0); ++ while (len >= 8) ++ { ++ len -= 8; ++ reg0 = gen_reg_rtx (DImode); ++ if (src_aligned) ++ emit_move_insn (reg0, src); ++ else ++ emit_insn (gen_unaligned_loaddi (reg0, src)); ++ ++ if (dst_aligned) ++ emit_move_insn (dst, reg0); ++ else ++ emit_insn (gen_unaligned_storedi (dst, reg0)); ++ ++ src = next_consecutive_mem (src); ++ dst = next_consecutive_mem (dst); ++ } ++ ++ gcc_assert (len < 8); ++ if (len >= 4) ++ { ++ /* More than a word but less than a double-word to copy. Copy a word. */ ++ reg0 = gen_reg_rtx (SImode); ++ src = adjust_address (src, SImode, 0); ++ dst = adjust_address (dst, SImode, 0); ++ if (src_aligned) ++ emit_move_insn (reg0, src); ++ else ++ emit_insn (gen_unaligned_loadsi (reg0, src)); ++ ++ if (dst_aligned) ++ emit_move_insn (dst, reg0); ++ else ++ emit_insn (gen_unaligned_storesi (dst, reg0)); ++ ++ src = next_consecutive_mem (src); ++ dst = next_consecutive_mem (dst); ++ len -= 4; ++ } ++ ++ if (len == 0) ++ return true; ++ ++ /* Copy the remaining bytes. */ ++ if (len >= 2) ++ { ++ dst = adjust_address (dst, HImode, 0); ++ src = adjust_address (src, HImode, 0); ++ reg0 = gen_reg_rtx (SImode); ++ emit_insn (gen_unaligned_loadhiu (reg0, src)); ++ emit_insn (gen_unaligned_storehi (dst, gen_lowpart (HImode, reg0))); ++ src = next_consecutive_mem (src); ++ dst = next_consecutive_mem (dst); ++ if (len == 2) ++ return true; ++ } ++ ++ dst = adjust_address (dst, QImode, 0); ++ src = adjust_address (src, QImode, 0); ++ reg0 = gen_reg_rtx (QImode); ++ emit_move_insn (reg0, src); ++ emit_move_insn (dst, reg0); ++ return true; ++} ++ + /* Select a dominance comparison mode if possible for a test of the general + form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. + COND_OR == DOM_CC_X_AND_Y => (X && Y) +@@ -12603,6 +12789,277 @@ return true; } @@ -13158,7 +17322,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* Print a symbolic form of X to the debug file, F. */ static void -@@ -14794,7 +15102,8 @@ +@@ -14794,7 +15251,8 @@ { /* Constraints should ensure this. */ gcc_assert (code0 == MEM && code1 == REG); @@ -13168,7 +17332,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ switch (GET_CODE (XEXP (operands[0], 0))) { -@@ -16387,6 +16696,148 @@ +@@ -16387,6 +16845,148 @@ return; } @@ -13317,7 +17481,27 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* Generate and emit an insn that we will recognize as a push_multi. Unfortunately, since this insn does not reflect very well the actual semantics of the operation, we need to annotate the insn for the benefit -@@ -16586,6 +17037,17 @@ +@@ -16529,6 +17129,19 @@ + return par; + } + ++/* Add a REG_CFA_ADJUST_CFA REG note to INSN. ++ SIZE is the offset to be adjusted. ++ DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx. */ ++static void ++arm_add_cfa_adjust_cfa_note (rtx insn, int size, rtx dest, rtx src) ++{ ++ rtx dwarf; ++ ++ RTX_FRAME_RELATED_P (insn) = 1; ++ dwarf = gen_rtx_SET (VOIDmode, dest, plus_constant (Pmode, src, size)); ++ add_reg_note (insn, REG_CFA_ADJUST_CFA, dwarf); ++} ++ + /* Generate and emit an insn pattern that we will recognize as a pop_multi. + SAVED_REGS_MASK shows which registers need to be restored. + +@@ -16586,6 +17199,17 @@ if (saved_regs_mask & (1 << i)) { reg = gen_rtx_REG (SImode, i); @@ -13335,7 +17519,62 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ tmp = gen_rtx_SET (VOIDmode, reg, gen_frame_mem -@@ -16817,6 +17279,129 @@ +@@ -16608,6 +17232,9 @@ + par = emit_insn (par); + + REG_NOTES (par) = dwarf; ++ if (!return_in_pc) ++ arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs, ++ stack_pointer_rtx, stack_pointer_rtx); + } + + /* Generate and emit an insn pattern that we will recognize as a pop_multi +@@ -16678,6 +17305,9 @@ + + par = emit_insn (par); + REG_NOTES (par) = dwarf; ++ ++ arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs, ++ base_reg, base_reg); + } + + /* Generate and emit a pattern that will be recognized as LDRD pattern. If even +@@ -16753,6 +17383,7 @@ + pattern can be emitted now. */ + par = emit_insn (par); + REG_NOTES (par) = dwarf; ++ RTX_FRAME_RELATED_P (par) = 1; + } + + i++; +@@ -16769,7 +17400,12 @@ + stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, 4 * i)); + RTX_FRAME_RELATED_P (tmp) = 1; +- emit_insn (tmp); ++ tmp = emit_insn (tmp); ++ if (!return_in_pc) ++ { ++ arm_add_cfa_adjust_cfa_note (tmp, UNITS_PER_WORD * i, ++ stack_pointer_rtx, stack_pointer_rtx); ++ } + + dwarf = NULL_RTX; + +@@ -16803,9 +17439,11 @@ + else + { + par = emit_insn (tmp); ++ REG_NOTES (par) = dwarf; ++ arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD, ++ stack_pointer_rtx, stack_pointer_rtx); + } + +- REG_NOTES (par) = dwarf; + } + else if ((num_regs % 2) == 1 && return_in_pc) + { +@@ -16817,6 +17455,129 @@ return; } @@ -13465,12 +17704,51 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* Calculate the size of the return value that is passed in registers. */ static unsigned arm_size_return_regs (void) -@@ -17026,9 +17611,10 @@ +@@ -16841,11 +17602,27 @@ + || df_regs_ever_live_p (LR_REGNUM)); + } + ++/* We do not know if r3 will be available because ++ we do have an indirect tailcall happening in this ++ particular case. */ ++static bool ++is_indirect_tailcall_p (rtx call) ++{ ++ rtx pat = PATTERN (call); + ++ /* Indirect tail call. */ ++ pat = XVECEXP (pat, 0, 0); ++ if (GET_CODE (pat) == SET) ++ pat = SET_SRC (pat); ++ ++ pat = XEXP (XEXP (pat, 0), 0); ++ return REG_P (pat); ++} ++ + /* Return true if r3 is used by any of the tail call insns in the + current function. */ + static bool +-any_sibcall_uses_r3 (void) ++any_sibcall_could_use_r3 (void) + { + edge_iterator ei; + edge e; +@@ -16859,7 +17636,8 @@ + if (!CALL_P (call)) + call = prev_nonnote_nondebug_insn (call); + gcc_assert (CALL_P (call) && SIBLING_CALL_P (call)); +- if (find_regno_fusage (call, USE, 3)) ++ if (find_regno_fusage (call, USE, 3) ++ || is_indirect_tailcall_p (call)) + return true; + } + return false; +@@ -17026,9 +17804,10 @@ /* If it is safe to use r3, then do so. This sometimes generates better code on Thumb-2 by avoiding the need to use 32-bit push/pop instructions. */ - if (! any_sibcall_uses_r3 () -+ if (! any_sibcall_uses_r3 () ++ if (! any_sibcall_could_use_r3 () && arm_size_return_regs () <= 12 - && (offsets->saved_regs_mask & (1 << 3)) == 0) + && (offsets->saved_regs_mask & (1 << 3)) == 0 @@ -13478,7 +17756,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ { reg = 3; } -@@ -17460,6 +18046,12 @@ +@@ -17460,6 +18239,12 @@ { thumb2_emit_strd_push (live_regs_mask); } @@ -13491,7 +17769,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ else { insn = emit_multi_reg_push (live_regs_mask); -@@ -19339,6 +19931,7 @@ +@@ -19339,6 +20124,7 @@ typedef enum { T_V8QI, T_V4HI, @@ -13499,7 +17777,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ T_V2SI, T_V2SF, T_DI, -@@ -19356,14 +19949,15 @@ +@@ -19356,14 +20142,15 @@ #define TYPE_MODE_BIT(X) (1 << (X)) #define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \ @@ -13517,7 +17795,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ #define v2si_UP T_V2SI #define v2sf_UP T_V2SF #define di_UP T_DI -@@ -19399,6 +19993,8 @@ +@@ -19399,6 +20186,8 @@ NEON_SCALARMULH, NEON_SCALARMAC, NEON_CONVERT, @@ -13526,7 +17804,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ NEON_FIXCONV, NEON_SELECT, NEON_RESULTPAIR, -@@ -19459,7 +20055,8 @@ +@@ -19459,7 +20248,8 @@ VAR9 (T, N, A, B, C, D, E, F, G, H, I), \ {#N, NEON_##T, UP (J), CF (N, J), 0} @@ -13536,7 +17814,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ instruction variant, i.e. equivalent to that which would be specified after the assembler mnemonic, which usually refers to the last vector operand. (Signed/unsigned/polynomial types are not differentiated between though, and -@@ -19469,196 +20066,7 @@ +@@ -19469,196 +20259,7 @@ static neon_builtin_datum neon_builtin_data[] = { @@ -13734,7 +18012,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ }; #undef CF -@@ -19673,9 +20081,36 @@ +@@ -19673,9 +20274,36 @@ #undef VAR9 #undef VAR10 @@ -13774,7 +18052,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ enum arm_builtins { ARM_BUILTIN_GETWCGR0, -@@ -19924,11 +20359,25 @@ +@@ -19924,11 +20552,25 @@ ARM_BUILTIN_WMERGE, @@ -13802,7 +18080,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX]; static void -@@ -19939,6 +20388,7 @@ +@@ -19939,6 +20581,7 @@ tree neon_intQI_type_node; tree neon_intHI_type_node; @@ -13810,7 +18088,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ tree neon_polyQI_type_node; tree neon_polyHI_type_node; tree neon_intSI_type_node; -@@ -19965,6 +20415,7 @@ +@@ -19965,6 +20608,7 @@ tree V8QI_type_node; tree V4HI_type_node; @@ -13818,7 +18096,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ tree V2SI_type_node; tree V2SF_type_node; tree V16QI_type_node; -@@ -20019,6 +20470,9 @@ +@@ -20019,6 +20663,9 @@ neon_float_type_node = make_node (REAL_TYPE); TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; layout_type (neon_float_type_node); @@ -13828,7 +18106,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* Define typedefs which exactly correspond to the modes we are basing vector types on. If you change these names you'll need to change -@@ -20027,6 +20481,8 @@ +@@ -20027,6 +20674,8 @@ "__builtin_neon_qi"); (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, "__builtin_neon_hi"); @@ -13837,7 +18115,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, "__builtin_neon_si"); (*lang_hooks.types.register_builtin_type) (neon_float_type_node, -@@ -20068,6 +20524,8 @@ +@@ -20068,6 +20717,8 @@ build_vector_type_for_mode (neon_intQI_type_node, V8QImode); V4HI_type_node = build_vector_type_for_mode (neon_intHI_type_node, V4HImode); @@ -13846,7 +18124,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ V2SI_type_node = build_vector_type_for_mode (neon_intSI_type_node, V2SImode); V2SF_type_node = -@@ -20190,7 +20648,7 @@ +@@ -20190,7 +20841,7 @@ neon_builtin_datum *d = &neon_builtin_data[i]; const char* const modenames[] = { @@ -13855,7 +18133,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ "v16qi", "v8hi", "v4si", "v4sf", "v2di", "ti", "ei", "oi" }; -@@ -20393,8 +20851,9 @@ +@@ -20393,8 +21044,9 @@ case NEON_REINTERP: { /* We iterate over 5 doubleword types, then 5 quadword @@ -13867,7 +18145,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ switch (insn_data[d->code].operand[0].mode) { case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; -@@ -20411,7 +20870,38 @@ +@@ -20411,7 +21063,38 @@ } } break; @@ -13906,7 +18184,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ default: gcc_unreachable (); } -@@ -21408,6 +21898,8 @@ +@@ -21408,6 +22091,8 @@ case NEON_DUP: case NEON_RINT: case NEON_SPLIT: @@ -13915,7 +18193,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ case NEON_REINTERP: return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); -@@ -21605,7 +22097,7 @@ +@@ -21605,7 +22290,7 @@ rtx op1; rtx op2; rtx pat; @@ -13924,7 +18202,119 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ size_t i; enum machine_mode tmode; enum machine_mode mode0; -@@ -23771,6 +24263,8 @@ +@@ -23322,7 +24007,7 @@ + all we really need to check here is if single register is to be + returned, or multiple register return. */ + void +-thumb2_expand_return (void) ++thumb2_expand_return (bool simple_return) + { + int i, num_regs; + unsigned long saved_regs_mask; +@@ -23335,7 +24020,7 @@ + if (saved_regs_mask & (1 << i)) + num_regs++; + +- if (saved_regs_mask) ++ if (!simple_return && saved_regs_mask) + { + if (num_regs == 1) + { +@@ -23613,6 +24298,7 @@ + + if (frame_pointer_needed) + { ++ rtx insn; + /* Restore stack pointer if necessary. */ + if (TARGET_ARM) + { +@@ -23623,9 +24309,12 @@ + /* Force out any pending memory operations that reference stacked data + before stack de-allocation occurs. */ + emit_insn (gen_blockage ()); +- emit_insn (gen_addsi3 (stack_pointer_rtx, +- hard_frame_pointer_rtx, +- GEN_INT (amount))); ++ insn = emit_insn (gen_addsi3 (stack_pointer_rtx, ++ hard_frame_pointer_rtx, ++ GEN_INT (amount))); ++ arm_add_cfa_adjust_cfa_note (insn, amount, ++ stack_pointer_rtx, ++ hard_frame_pointer_rtx); + + /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not + deleted. */ +@@ -23635,16 +24324,25 @@ + { + /* In Thumb-2 mode, the frame pointer points to the last saved + register. */ +- amount = offsets->locals_base - offsets->saved_regs; +- if (amount) +- emit_insn (gen_addsi3 (hard_frame_pointer_rtx, +- hard_frame_pointer_rtx, +- GEN_INT (amount))); ++ amount = offsets->locals_base - offsets->saved_regs; ++ if (amount) ++ { ++ insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ++ hard_frame_pointer_rtx, ++ GEN_INT (amount))); ++ arm_add_cfa_adjust_cfa_note (insn, amount, ++ hard_frame_pointer_rtx, ++ hard_frame_pointer_rtx); ++ } + + /* Force out any pending memory operations that reference stacked data + before stack de-allocation occurs. */ + emit_insn (gen_blockage ()); +- emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); ++ insn = emit_insn (gen_movsi (stack_pointer_rtx, ++ hard_frame_pointer_rtx)); ++ arm_add_cfa_adjust_cfa_note (insn, 0, ++ stack_pointer_rtx, ++ hard_frame_pointer_rtx); + /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not + deleted. */ + emit_insn (gen_force_register_use (stack_pointer_rtx)); +@@ -23657,12 +24355,15 @@ + amount = offsets->outgoing_args - offsets->saved_regs; + if (amount) + { ++ rtx tmp; + /* Force out any pending memory operations that reference stacked data + before stack de-allocation occurs. */ + emit_insn (gen_blockage ()); +- emit_insn (gen_addsi3 (stack_pointer_rtx, +- stack_pointer_rtx, +- GEN_INT (amount))); ++ tmp = emit_insn (gen_addsi3 (stack_pointer_rtx, ++ stack_pointer_rtx, ++ GEN_INT (amount))); ++ arm_add_cfa_adjust_cfa_note (tmp, amount, ++ stack_pointer_rtx, stack_pointer_rtx); + /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is + not deleted. */ + emit_insn (gen_force_register_use (stack_pointer_rtx)); +@@ -23715,6 +24416,8 @@ + REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, + gen_rtx_REG (V2SImode, i), + NULL_RTX); ++ arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, ++ stack_pointer_rtx, stack_pointer_rtx); + } + + if (saved_regs_mask) +@@ -23762,6 +24465,9 @@ + REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, + gen_rtx_REG (SImode, i), + NULL_RTX); ++ arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, ++ stack_pointer_rtx, ++ stack_pointer_rtx); + } + } + } +@@ -23772,6 +24478,8 @@ { if (TARGET_THUMB2) thumb2_emit_ldrd_pop (saved_regs_mask); @@ -13933,7 +18323,45 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ else arm_emit_multi_reg_pop (saved_regs_mask); } -@@ -25039,7 +25533,7 @@ +@@ -23784,10 +24492,34 @@ + } + + if (crtl->args.pretend_args_size) +- emit_insn (gen_addsi3 (stack_pointer_rtx, +- stack_pointer_rtx, +- GEN_INT (crtl->args.pretend_args_size))); ++ { ++ int i, j; ++ rtx dwarf = NULL_RTX; ++ rtx tmp = emit_insn (gen_addsi3 (stack_pointer_rtx, ++ stack_pointer_rtx, ++ GEN_INT (crtl->args.pretend_args_size))); + ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ ++ if (cfun->machine->uses_anonymous_args) ++ { ++ /* Restore pretend args. Refer arm_expand_prologue on how to save ++ pretend_args in stack. */ ++ int num_regs = crtl->args.pretend_args_size / 4; ++ saved_regs_mask = (0xf0 >> num_regs) & 0xf; ++ for (j = 0, i = 0; j < num_regs; i++) ++ if (saved_regs_mask & (1 << i)) ++ { ++ rtx reg = gen_rtx_REG (SImode, i); ++ dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); ++ j++; ++ } ++ REG_NOTES (tmp) = dwarf; ++ } ++ arm_add_cfa_adjust_cfa_note (tmp, crtl->args.pretend_args_size, ++ stack_pointer_rtx, stack_pointer_rtx); ++ } ++ + if (!really_return) + return; + +@@ -25040,7 +25772,7 @@ { /* Neon also supports V2SImode, etc. listed in the clause below. */ if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode @@ -13942,7 +18370,37 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ return true; if ((TARGET_NEON || TARGET_IWMMXT) -@@ -25854,6 +26348,7 @@ +@@ -25203,9 +25935,8 @@ + + nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8; + p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); +- regno = (regno - FIRST_VFP_REGNUM) / 2; + for (i = 0; i < nregs; i++) +- XVECEXP (p, 0, i) = gen_rtx_REG (DImode, 256 + regno + i); ++ XVECEXP (p, 0, i) = gen_rtx_REG (DImode, regno + i); + + return p; + } +@@ -25455,9 +26186,17 @@ + handled_one = true; + break; + ++ /* The INSN is generated in epilogue. It is set as RTX_FRAME_RELATED_P ++ to get correct dwarf information for shrink-wrap. We should not ++ emit unwind information for it because these are used either for ++ pretend arguments or notes to adjust sp and restore registers from ++ stack. */ ++ case REG_CFA_ADJUST_CFA: ++ case REG_CFA_RESTORE: ++ return; ++ + case REG_CFA_DEF_CFA: + case REG_CFA_EXPRESSION: +- case REG_CFA_ADJUST_CFA: + case REG_CFA_OFFSET: + /* ??? Only handling here what we actually emit. */ + gcc_unreachable (); +@@ -25855,6 +26594,7 @@ case cortexa7: case cortexa8: case cortexa9: @@ -13950,7 +18408,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ case fa726te: case marvell_pj4: return 2; -@@ -25882,6 +26377,7 @@ +@@ -25883,6 +26623,7 @@ { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, @@ -13958,7 +18416,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, -@@ -25980,6 +26476,60 @@ +@@ -25981,6 +26722,60 @@ return !TARGET_THUMB1; } @@ -14019,7 +18477,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* The AAPCS sets the maximum alignment of a vector to 64 bits. */ static HOST_WIDE_INT arm_vector_alignment (const_tree type) -@@ -26210,40 +26760,72 @@ +@@ -26211,40 +27006,72 @@ emit_insn (gen_memory_barrier ()); } @@ -14109,7 +18567,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ emit_insn (gen (bval, rval, mem)); } -@@ -26278,6 +26860,15 @@ +@@ -26279,6 +27106,15 @@ mod_f = operands[7]; mode = GET_MODE (mem); @@ -14125,7 +18583,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ switch (mode) { case QImode: -@@ -26352,8 +26943,20 @@ +@@ -26353,8 +27189,20 @@ scratch = operands[7]; mode = GET_MODE (mem); @@ -14147,7 +18605,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ label1 = NULL_RTX; if (!is_weak) { -@@ -26362,7 +26965,7 @@ +@@ -26363,7 +27211,7 @@ } label2 = gen_label_rtx (); @@ -14156,7 +18614,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ cond = arm_gen_compare_reg (NE, rval, oldval, scratch); x = gen_rtx_NE (VOIDmode, cond, const0_rtx); -@@ -26370,7 +26973,7 @@ +@@ -26371,7 +27219,7 @@ gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x)); @@ -14165,7 +18623,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* Weak or strong, we want EQ to be true for success, so that we match the flags that we got from the compare above. */ -@@ -26389,7 +26992,9 @@ +@@ -26390,7 +27238,9 @@ if (mod_f != MEMMODEL_RELAXED) emit_label (label2); @@ -14176,7 +18634,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ if (mod_f == MEMMODEL_RELAXED) emit_label (label2); -@@ -26404,8 +27009,20 @@ +@@ -26405,8 +27255,20 @@ enum machine_mode wmode = (mode == DImode ? DImode : SImode); rtx label, x; @@ -14198,7 +18656,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ label = gen_label_rtx (); emit_label (label); -@@ -26417,7 +27034,7 @@ +@@ -26418,7 +27280,7 @@ old_out = new_out; value = simplify_gen_subreg (wmode, value, mode, 0); @@ -14207,7 +18665,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ switch (code) { -@@ -26465,12 +27082,15 @@ +@@ -26466,12 +27328,15 @@ break; } @@ -14264,6 +18722,39 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ /* Modes valid for Neon Q registers. */ #define VALID_NEON_QREG_MODE(MODE) \ +@@ -1130,6 +1140,7 @@ + STACK_REG, + BASE_REGS, + HI_REGS, ++ CALLER_SAVE_REGS, + GENERAL_REGS, + CORE_REGS, + VFP_D0_D7_REGS, +@@ -1156,6 +1167,7 @@ + "STACK_REG", \ + "BASE_REGS", \ + "HI_REGS", \ ++ "CALLER_SAVE_REGS", \ + "GENERAL_REGS", \ + "CORE_REGS", \ + "VFP_D0_D7_REGS", \ +@@ -1181,6 +1193,7 @@ + { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ + { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ + { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ ++ { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ + { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ + { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ + { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ +@@ -1639,7 +1652,7 @@ + frame. */ + #define EXIT_IGNORE_STACK 1 + +-#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) ++#define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) + + /* Determine if the epilogue should be output as RTL. + You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ --- a/src/gcc/config/arm/unspecs.md +++ b/src/gcc/config/arm/unspecs.md @@ -83,6 +83,8 @@ @@ -14311,7 +18802,22 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (const (symbol_ref "((enum attr_tune) arm_tune)"))) --- a/src/gcc/config/arm/arm-protos.h +++ b/src/gcc/config/arm/arm-protos.h -@@ -78,6 +78,7 @@ +@@ -24,12 +24,13 @@ + + extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *); + extern int use_return_insn (int, rtx); ++extern bool use_simple_return_p (void); + extern enum reg_class arm_regno_class (int); + extern void arm_load_pic_register (unsigned long); + extern int arm_volatile_func (void); + extern void arm_expand_prologue (void); + extern void arm_expand_epilogue (bool); +-extern void thumb2_expand_return (void); ++extern void thumb2_expand_return (bool); + extern const char *arm_strip_name_encoding (const char *); + extern void arm_asm_output_labelref (FILE *, const char *); + extern void thumb2_asm_output_opcode (FILE *); +@@ -78,6 +79,7 @@ extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode, rtx (*) (rtx, rtx, rtx)); extern rtx neon_make_constant (rtx); @@ -14319,15 +18825,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ extern void neon_expand_vector_init (rtx, rtx); extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); -@@ -117,6 +118,7 @@ +@@ -117,7 +119,9 @@ extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT); extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool); +extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool); extern int arm_gen_movmemqi (rtx *); ++extern bool gen_movmem_ldrd_strd (rtx *); extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, -@@ -269,6 +271,8 @@ + HOST_WIDE_INT); +@@ -269,6 +273,8 @@ bool logical_op_non_short_circuit[2]; /* Vectorizer costs. */ const struct cpu_vec_costs* vec_costs; @@ -14929,7 +19437,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS" "@internal Thumb only. The union of the low registers and the stack register.") -@@ -248,6 +251,12 @@ +@@ -93,6 +96,9 @@ + (define_register_constraint "c" "CC_REG" + "@internal The condition code register.") + ++(define_register_constraint "Cs" "CALLER_SAVE_REGS" ++ "@internal The caller save registers. Useful for sibcalls.") ++ + (define_constraint "I" + "In ARM/Thumb-2 state a constant that can be used as an immediate value in a + Data Processing instruction. In Thumb-1 state a constant in the range +@@ -248,6 +254,12 @@ (and (match_code "const_int") (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)"))) @@ -14942,6 +19460,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_constraint "Di" "@internal In ARM/Thumb-2 state a const_int or const_double where both the high +@@ -391,3 +403,9 @@ + ;; Additionally, we used to have a Q constraint in Thumb state, but + ;; this wasn't really a valid memory constraint. Again, all uses of + ;; this now seem to have been removed. ++ ++(define_constraint "Ss" ++ "@internal ++ Ss is a symbol reference." ++ (match_code "symbol_ref") ++) --- a/src/gcc/config/arm/arm-arches.def +++ b/src/gcc/config/arm/arm-arches.def @@ -53,6 +53,6 @@ @@ -15327,6 +19855,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; Predicates for named expanders that overlap multiple ISAs. (define_predicate "cmpdi_operand" +@@ -617,3 +635,7 @@ + (define_predicate "mem_noofs_operand" + (and (match_code "mem") + (match_code "reg" "0"))) ++ ++(define_predicate "call_insn_operand" ++ (ior (match_code "symbol_ref") ++ (match_operand 0 "s_register_operand"))) --- a/src/gcc/config/arm/arm_neon.h +++ b/src/gcc/config/arm/arm_neon.h @@ -43,6 +43,7 @@ @@ -15677,6 +20213,20 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ |mcpu=marvell-pj4 \ |mcpu=generic-armv7-a \ |march=armv7-m|mcpu=cortex-m3 \ +--- a/src/gcc/config/arm/iterators.md ++++ b/src/gcc/config/arm/iterators.md +@@ -496,3 +496,11 @@ + (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") + (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") + (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) ++;; Both kinds of return insn. ++(define_code_iterator returns [return simple_return]) ++(define_code_attr return_str [(return "") (simple_return "simple_")]) ++(define_code_attr return_simple_p [(return "false") (simple_return "true")]) ++(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") ++ (simple_return " && use_simple_return_p ()")]) ++(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") ++ (simple_return " && use_simple_return_p ()")]) --- a/src/gcc/config/arm/sync.md +++ b/src/gcc/config/arm/sync.md @@ -65,6 +65,42 @@ @@ -16640,7 +21190,72 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (define_insn "*shiftsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (match_operator:SI 3 "shift_operator" -@@ -4154,12 +4466,24 @@ +@@ -4090,6 +4402,64 @@ + (set_attr "predicable" "yes") + (set_attr "type" "store1")]) + ++;; Unaligned double-word load and store. ++;; Split after reload into two unaligned single-word accesses. ++;; It prevents lower_subreg from splitting some other aligned ++;; double-word accesses too early. Used for internal memcpy. ++ ++(define_insn_and_split "unaligned_loaddi" ++ [(set (match_operand:DI 0 "s_register_operand" "=l,r") ++ (unspec:DI [(match_operand:DI 1 "memory_operand" "o,o")] ++ UNSPEC_UNALIGNED_LOAD))] ++ "unaligned_access && TARGET_32BIT" ++ "#" ++ "&& reload_completed" ++ [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_UNALIGNED_LOAD)) ++ (set (match_dup 2) (unspec:SI [(match_dup 3)] UNSPEC_UNALIGNED_LOAD))] ++ { ++ operands[2] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[3] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ ++ /* If the first destination register overlaps with the base address, ++ swap the order in which the loads are emitted. */ ++ if (reg_overlap_mentioned_p (operands[0], operands[1])) ++ { ++ rtx tmp = operands[1]; ++ operands[1] = operands[3]; ++ operands[3] = tmp; ++ tmp = operands[0]; ++ operands[0] = operands[2]; ++ operands[2] = tmp; ++ } ++ } ++ [(set_attr "arch" "t2,any") ++ (set_attr "length" "4,8") ++ (set_attr "predicable" "yes") ++ (set_attr "type" "load2")]) ++ ++(define_insn_and_split "unaligned_storedi" ++ [(set (match_operand:DI 0 "memory_operand" "=o,o") ++ (unspec:DI [(match_operand:DI 1 "s_register_operand" "l,r")] ++ UNSPEC_UNALIGNED_STORE))] ++ "unaligned_access && TARGET_32BIT" ++ "#" ++ "&& reload_completed" ++ [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_UNALIGNED_STORE)) ++ (set (match_dup 2) (unspec:SI [(match_dup 3)] UNSPEC_UNALIGNED_STORE))] ++ { ++ operands[2] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[3] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ } ++ [(set_attr "arch" "t2,any") ++ (set_attr "length" "4,8") ++ (set_attr "predicable" "yes") ++ (set_attr "type" "store2")]) ++ ++ + (define_insn "*extv_reg" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") +@@ -4154,12 +4524,24 @@ ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). ;; The first alternative allows the common case of a *full* overlap. @@ -16667,7 +21282,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set_attr "conds" "clob") (set_attr "length" "8")] ) -@@ -4209,6 +4533,73 @@ +@@ -4209,6 +4591,73 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "") @@ -16741,7 +21356,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ;; abssi2 doesn't really clobber the condition codes if a different register ;; is being set. To keep things simple, assume during rtl manipulations that ;; it does, but tell the final scan operator the truth. Similarly for -@@ -4227,14 +4618,67 @@ +@@ -4227,14 +4676,67 @@ operands[2] = gen_rtx_REG (CCmode, CC_REGNUM); ") @@ -16813,7 +21428,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set_attr "conds" "clob,*") (set_attr "shift" "1") (set_attr "predicable" "no, yes") -@@ -4255,14 +4699,56 @@ +@@ -4255,14 +4757,56 @@ [(set_attr "length" "6")] ) @@ -16874,7 +21489,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set_attr "conds" "clob,*") (set_attr "shift" "1") (set_attr "predicable" "no, yes") -@@ -4330,7 +4816,7 @@ +@@ -4330,7 +4874,7 @@ [(set_attr "length" "*,8,8,*") (set_attr "predicable" "no,yes,yes,no") (set_attr "neon_type" "neon_int_1,*,*,neon_int_1") @@ -16883,7 +21498,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ) (define_expand "one_cmplsi2" -@@ -4498,7 +4984,7 @@ +@@ -4498,7 +5042,7 @@ "TARGET_32BIT <qhs_zextenddi_cond>" "#" [(set_attr "length" "8,4,8,8") @@ -16892,7 +21507,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (set_attr "ce_count" "2") (set_attr "predicable" "yes")] ) -@@ -4513,7 +4999,7 @@ +@@ -4513,7 +5057,7 @@ (set_attr "ce_count" "2") (set_attr "shift" "1") (set_attr "predicable" "yes") @@ -16901,7 +21516,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ ) ;; Splits for all extensions to DImode -@@ -5313,8 +5799,8 @@ +@@ -5313,8 +5857,8 @@ ) (define_insn "*arm_movdi" @@ -16912,7 +21527,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_VFP) && !TARGET_IWMMXT -@@ -6738,8 +7224,8 @@ +@@ -6738,8 +7282,8 @@ ) (define_insn "*movdf_soft_insn" @@ -16923,7 +21538,27 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ "TARGET_32BIT && TARGET_SOFT_FLOAT && ( register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" -@@ -7617,23 +8103,64 @@ +@@ -6869,10 +7413,18 @@ + (match_operand:BLK 1 "general_operand" "") + (match_operand:SI 2 "const_int_operand" "") + (match_operand:SI 3 "const_int_operand" "")] +- "TARGET_EITHER" ++ "" + " + if (TARGET_32BIT) + { ++ if (TARGET_LDRD && current_tune->prefer_ldrd_strd ++ && !optimize_function_for_size_p (cfun)) ++ { ++ if (gen_movmem_ldrd_strd (operands)) ++ DONE; ++ FAIL; ++ } ++ + if (arm_gen_movmemqi (operands)) + DONE; + FAIL; +@@ -7617,23 +8169,64 @@ ;; if-conversion can not reduce to a conditional compare, so we do ;; that directly. @@ -16992,7 +21627,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set_attr "conds" "set") (set_attr "length" "8")] ) -@@ -7758,36 +8285,56 @@ +@@ -7758,36 +8351,56 @@ operands[3] = const0_rtx;" ) @@ -17058,7 +21693,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ (set_attr "length" "8")] ) -@@ -8110,7 +8657,40 @@ +@@ -8110,7 +8723,40 @@ }" ) @@ -17100,7 +21735,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r") (if_then_else:SI (match_operator 3 "arm_comparison_operator" -@@ -8123,10 +8703,45 @@ +@@ -8123,10 +8769,45 @@ mvn%D3\\t%0, #%B2 mov%d3\\t%0, %1 mvn%d3\\t%0, #%B1 @@ -17150,7 +21785,239 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set_attr "length" "4,4,4,4,8,8,8,8") (set_attr "conds" "use") (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn") -@@ -9095,27 +9710,64 @@ +@@ -8255,7 +8936,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && arm_arch5" ++ "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" + "blx%?\\t%0" + [(set_attr "type" "call")] + ) +@@ -8265,7 +8946,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && !arm_arch5" ++ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" + "* + return output_call (operands); + " +@@ -8284,7 +8965,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && !arm_arch5" ++ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" + "* + return output_call_mem (operands); + " +@@ -8297,7 +8978,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_THUMB1 && arm_arch5" ++ "TARGET_THUMB1 && arm_arch5 && !SIBLING_CALL_P (insn)" + "blx\\t%0" + [(set_attr "length" "2") + (set_attr "type" "call")] +@@ -8308,7 +8989,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_THUMB1 && !arm_arch5" ++ "TARGET_THUMB1 && !arm_arch5 && !SIBLING_CALL_P (insn)" + "* + { + if (!TARGET_CALLER_INTERWORKING) +@@ -8367,7 +9048,7 @@ + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && arm_arch5" ++ "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" + "blx%?\\t%1" + [(set_attr "type" "call")] + ) +@@ -8378,7 +9059,7 @@ + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && !arm_arch5" ++ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" + "* + return output_call (&operands[1]); + " +@@ -8394,7 +9075,8 @@ + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))" ++ "TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ++ && !SIBLING_CALL_P (insn)" + "* + return output_call_mem (&operands[1]); + " +@@ -8444,6 +9126,7 @@ + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] + "TARGET_32BIT ++ && !SIBLING_CALL_P (insn) + && (GET_CODE (operands[0]) == SYMBOL_REF) + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" + "* +@@ -8460,6 +9143,7 @@ + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] + "TARGET_32BIT ++ && !SIBLING_CALL_P (insn) + && (GET_CODE (operands[1]) == SYMBOL_REF) + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" + "* +@@ -8505,6 +9189,10 @@ + "TARGET_32BIT" + " + { ++ if (!REG_P (XEXP (operands[0], 0)) ++ && (GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)) ++ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); ++ + if (operands[2] == NULL_RTX) + operands[2] = const0_rtx; + }" +@@ -8519,47 +9207,67 @@ + "TARGET_32BIT" + " + { ++ if (!REG_P (XEXP (operands[1], 0)) && ++ (GET_CODE (XEXP (operands[1],0)) != SYMBOL_REF)) ++ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); ++ + if (operands[3] == NULL_RTX) + operands[3] = const0_rtx; + }" + ) + + (define_insn "*sibcall_insn" +- [(call (mem:SI (match_operand:SI 0 "" "X")) ++ [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "Cs,Ss")) + (match_operand 1 "" "")) + (return) + (use (match_operand 2 "" ""))] +- "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF" ++ "TARGET_32BIT && SIBLING_CALL_P (insn)" + "* +- return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; ++ if (which_alternative == 1) ++ return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; ++ else ++ { ++ if (arm_arch5 || arm_arch4t) ++ return \" bx\\t%0\\t%@ indirect register sibling call\"; ++ else ++ return \"mov%?\\t%|pc, %0\\t%@ indirect register sibling call\"; ++ } + " + [(set_attr "type" "call")] + ) + + (define_insn "*sibcall_value_insn" +- [(set (match_operand 0 "" "") +- (call (mem:SI (match_operand:SI 1 "" "X")) ++ [(set (match_operand 0 "s_register_operand" "") ++ (call (mem:SI (match_operand:SI 1 "call_insn_operand" "Cs,Ss")) + (match_operand 2 "" ""))) + (return) + (use (match_operand 3 "" ""))] +- "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF" ++ "TARGET_32BIT && SIBLING_CALL_P (insn)" + "* +- return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; ++ if (which_alternative == 1) ++ return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; ++ else ++ { ++ if (arm_arch5 || arm_arch4t) ++ return \"bx\\t%1\"; ++ else ++ return \"mov%?\\t%|pc, %1\\t@ indirect sibling call \"; ++ } + " + [(set_attr "type" "call")] + ) + +-(define_expand "return" +- [(return)] ++(define_expand "<return_str>return" ++ [(returns)] + "(TARGET_ARM || (TARGET_THUMB2 + && ARM_FUNC_TYPE (arm_current_func_type ()) == ARM_FT_NORMAL + && !IS_STACKALIGN (arm_current_func_type ()))) +- && USE_RETURN_INSN (FALSE)" ++ <return_cond_false>" + " + { + if (TARGET_THUMB2) + { +- thumb2_expand_return (); ++ thumb2_expand_return (<return_simple_p>); + DONE; + } + } +@@ -8584,13 +9292,13 @@ + (set_attr "predicable" "yes")] + ) + +-(define_insn "*cond_return" ++(define_insn "*cond_<return_str>return" + [(set (pc) + (if_then_else (match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") (const_int 0)]) +- (return) ++ (returns) + (pc)))] +- "TARGET_ARM && USE_RETURN_INSN (TRUE)" ++ "TARGET_ARM <return_cond_true>" + "* + { + if (arm_ccfsm_state == 2) +@@ -8598,20 +9306,21 @@ + arm_ccfsm_state += 2; + return \"\"; + } +- return output_return_instruction (operands[0], true, false, false); ++ return output_return_instruction (operands[0], true, false, ++ <return_simple_p>); + }" + [(set_attr "conds" "use") + (set_attr "length" "12") + (set_attr "type" "load1")] + ) + +-(define_insn "*cond_return_inverted" ++(define_insn "*cond_<return_str>return_inverted" + [(set (pc) + (if_then_else (match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") (const_int 0)]) + (pc) +- (return)))] +- "TARGET_ARM && USE_RETURN_INSN (TRUE)" ++ (returns)))] ++ "TARGET_ARM <return_cond_true>" + "* + { + if (arm_ccfsm_state == 2) +@@ -8619,7 +9328,8 @@ + arm_ccfsm_state += 2; + return \"\"; + } +- return output_return_instruction (operands[0], true, true, false); ++ return output_return_instruction (operands[0], true, true, ++ <return_simple_p>); + }" + [(set_attr "conds" "use") + (set_attr "length" "12") +@@ -9095,27 +9805,64 @@ (set_attr "type" "alu_shift,alu_shift_reg")]) @@ -17225,7 +22092,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set_attr "conds" "use") (set_attr "length" "4,8")] ) -@@ -9822,24 +10474,75 @@ +@@ -9822,24 +10569,75 @@ "") ;; ??? The conditional patterns above need checking for Thumb-2 usefulness @@ -17311,7 +22178,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ [(set_attr "conds" "clob") (set_attr "length" "12")] ) -@@ -11626,6 +12329,9 @@ +@@ -11626,6 +12424,9 @@ (set_attr "predicable" "yes")]) @@ -17380,49 +22247,81 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@198615 \ "__builtin_neon_poly16", "poly", 16, 4; --- a/src/libobjc/ChangeLog.linaro +++ b/src/libobjc/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libgfortran/ChangeLog.linaro +++ b/src/libgfortran/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libada/ChangeLog.linaro +++ b/src/libada/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libffi/ChangeLog.linaro +++ b/src/libffi/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libssp/ChangeLog.linaro +++ b/src/libssp/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libcpp/ChangeLog.linaro +++ b/src/libcpp/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/libcpp/po/ChangeLog.linaro +++ b/src/libcpp/po/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. --- a/src/fixincludes/ChangeLog.linaro +++ b/src/fixincludes/ChangeLog.linaro -@@ -0,0 +1,3 @@ +@@ -0,0 +1,7 @@ ++2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> ++ ++ GCC Linaro 4.8-2013.05 released. ++ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. |