diff options
| author | doko <doko@6ca36cf4-e1d1-0310-8c6f-e303bb2178ca> | 2013-07-08 16:11:49 +0000 |
|---|---|---|
| committer | doko <doko@6ca36cf4-e1d1-0310-8c6f-e303bb2178ca> | 2013-07-08 16:11:49 +0000 |
| commit | cbc8113ad79a16353041b3e8ce8febc25bcf001f (patch) | |
| tree | 7ff7ac7bdc57d135a193656b8c7cc4e32113e6b3 /debian/patches/gcc-linaro.diff | |
| parent | ad1a181da93a8ff5b944c3f44c4f929f829a542c (diff) | |
| download | gcc-48-cbc8113ad79a16353041b3e8ce8febc25bcf001f.tar.gz | |
* Update the Linaro support to the 4.8-2013.07 release.
git-svn-id: svn://svn.debian.org/svn/gcccvs/branches/sid/gcc-4.8@6905 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
Diffstat (limited to 'debian/patches/gcc-linaro.diff')
| -rw-r--r-- | debian/patches/gcc-linaro.diff | 3082 |
1 files changed, 2034 insertions, 1048 deletions
diff --git a/debian/patches/gcc-linaro.diff b/debian/patches/gcc-linaro.diff index c707e1d..432a613 100644 --- a/debian/patches/gcc-linaro.diff +++ b/debian/patches/gcc-linaro.diff @@ -1,12 +1,16 @@ -# DP: Changes for the Linaro 4.8-2013.06 release. +# DP: Changes for the Linaro 4.8-2013.07 release. -LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ - svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@r199923 \ +LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@200355 \ + svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@200692 \ | filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/ --- a/src/libitm/ChangeLog.linaro +++ b/src/libitm/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -16,7 +20,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgomp/ChangeLog.linaro +++ b/src/libgomp/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -26,7 +34,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libquadmath/ChangeLog.linaro +++ b/src/libquadmath/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -49,7 +61,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ current_++; --- a/src/libsanitizer/ChangeLog.linaro +++ b/src/libsanitizer/ChangeLog.linaro -@@ -0,0 +1,15 @@ +@@ -0,0 +1,26 @@ ++2013-06-20 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198683. ++ 2013-05-07 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ * configure.tgt: Add ARM pattern. ++ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-06-04 Christophe Lyon <christophe.lyon@linaro.org> + + Backport from trunk r199606. @@ -65,9 +88,24 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. +--- a/src/libsanitizer/configure.tgt ++++ b/src/libsanitizer/configure.tgt +@@ -29,6 +29,8 @@ + ;; + sparc*-*-linux*) + ;; ++ arm*-*-linux*) ++ ;; + x86_64-*-darwin[1]* | i?86-*-darwin[1]*) + TSAN_SUPPORTED=no + ;; --- a/src/zlib/ChangeLog.linaro +++ b/src/zlib/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -77,7 +115,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libstdc++-v3/ChangeLog.linaro +++ b/src/libstdc++-v3/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -87,7 +129,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/intl/ChangeLog.linaro +++ b/src/intl/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -97,7 +143,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/ChangeLog.linaro +++ b/src/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,16 @@ ++2013-06-18 Rob Savoye <rob.savoye@linaro.org> ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -107,7 +162,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libmudflap/ChangeLog.linaro +++ b/src/libmudflap/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -117,7 +176,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/boehm-gc/ChangeLog.linaro +++ b/src/boehm-gc/ChangeLog.linaro -@@ -0,0 +1,20 @@ +@@ -0,0 +1,24 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -208,7 +271,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ # define MACH_TYPE "ARM32" --- a/src/include/ChangeLog.linaro +++ b/src/include/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -218,7 +285,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libiberty/ChangeLog.linaro +++ b/src/libiberty/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -228,7 +299,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/lto-plugin/ChangeLog.linaro +++ b/src/lto-plugin/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -238,7 +313,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/regression/ChangeLog.linaro +++ b/src/contrib/regression/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -260,7 +339,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ arm-linux-androideabi arm-uclinux_eabi arm-eabi \ --- a/src/contrib/ChangeLog.linaro +++ b/src/contrib/ChangeLog.linaro -@@ -0,0 +1,14 @@ +@@ -0,0 +1,18 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -277,7 +360,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/reghunt/ChangeLog.linaro +++ b/src/contrib/reghunt/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -287,7 +374,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libatomic/ChangeLog.linaro +++ b/src/libatomic/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -297,7 +388,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/config/ChangeLog.linaro +++ b/src/config/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -307,7 +402,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libbacktrace/ChangeLog.linaro +++ b/src/libbacktrace/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -317,7 +416,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/libltdl/ChangeLog.linaro +++ b/src/libjava/libltdl/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -327,7 +430,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/ChangeLog.linaro +++ b/src/libjava/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -337,7 +444,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/classpath/ChangeLog.linaro +++ b/src/libjava/classpath/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -347,7 +458,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gnattools/ChangeLog.linaro +++ b/src/gnattools/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -357,7 +472,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/maintainer-scripts/ChangeLog.linaro +++ b/src/maintainer-scripts/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -367,7 +486,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgcc/ChangeLog.linaro +++ b/src/libgcc/ChangeLog.linaro -@@ -0,0 +1,17 @@ +@@ -0,0 +1,21 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -400,7 +523,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ typedef int TItype __attribute__ ((mode (TI))); --- a/src/libgcc/config/libbid/ChangeLog.linaro +++ b/src/libgcc/config/libbid/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -410,7 +537,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libdecnumber/ChangeLog.linaro +++ b/src/libdecnumber/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -421,7 +552,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ --- a/src/gcc/LINARO-VERSION +++ b/src/gcc/LINARO-VERSION @@ -0,0 +1 @@ -+4.8-2013.05-1~dev ++4.8-2013.06 --- a/src/gcc/hooks.c +++ b/src/gcc/hooks.c @@ -147,6 +147,14 @@ @@ -451,7 +582,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ HOST_WIDE_INT, --- a/src/gcc/c-family/ChangeLog.linaro +++ b/src/gcc/c-family/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -461,7 +596,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/java/ChangeLog.linaro +++ b/src/gcc/java/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -471,7 +610,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/c/ChangeLog.linaro +++ b/src/gcc/c/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -507,6 +650,19 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Target hook is used to compare the target attributes in two functions to determine which function's features get higher priority. This is used during function multi-versioning to figure out the order in which two +--- a/src/gcc/rtlanal.c ++++ b/src/gcc/rtlanal.c +@@ -1199,6 +1199,10 @@ + if (find_reg_note (insn, REG_EQUAL, NULL_RTX)) + return 0; + ++ /* Check the code to be executed for COND_EXEC. */ ++ if (GET_CODE (pat) == COND_EXEC) ++ pat = COND_EXEC_CODE (pat); ++ + if (GET_CODE (pat) == SET && set_noop_p (pat)) + return 1; + --- a/src/gcc/configure +++ b/src/gcc/configure @@ -1658,7 +1658,8 @@ @@ -528,9 +684,56 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ fi +--- a/src/gcc/gensupport.c ++++ b/src/gcc/gensupport.c +@@ -1717,6 +1717,21 @@ + XVECEXP (insn, 1, 0) = pattern; + } + ++ if (XVEC (ce_elem->data, 3) != NULL) ++ { ++ rtvec attributes = rtvec_alloc (XVECLEN (insn, 4) ++ + XVECLEN (ce_elem->data, 3)); ++ int i = 0; ++ int j = 0; ++ for (i = 0; i < XVECLEN (insn, 4); i++) ++ RTVEC_ELT (attributes, i) = XVECEXP (insn, 4, i); ++ ++ for (j = 0; j < XVECLEN (ce_elem->data, 3); j++, i++) ++ RTVEC_ELT (attributes, i) = XVECEXP (ce_elem->data, 3, j); ++ ++ XVEC (insn, 4) = attributes; ++ } ++ + XSTR (insn, 2) = alter_test_for_insn (ce_elem, insn_elem); + XTMPL (insn, 3) = alter_output_for_insn (ce_elem, insn_elem, + alternatives, max_operand); +--- a/src/gcc/fold-const.c ++++ b/src/gcc/fold-const.c +@@ -2457,9 +2457,13 @@ + } + + if (TREE_CODE (arg0) != TREE_CODE (arg1) +- /* This is needed for conversions and for COMPONENT_REF. +- Might as well play it safe and always test this. */ +- || TREE_CODE (TREE_TYPE (arg0)) == ERROR_MARK ++ /* NOP_EXPR and CONVERT_EXPR are considered equal. */ ++ && !(CONVERT_EXPR_P (arg0) && CONVERT_EXPR_P (arg1))) ++ return 0; ++ ++ /* This is needed for conversions and for COMPONENT_REF. ++ Might as well play it safe and always test this. */ ++ if (TREE_CODE (TREE_TYPE (arg0)) == ERROR_MARK + || TREE_CODE (TREE_TYPE (arg1)) == ERROR_MARK + || TYPE_MODE (TREE_TYPE (arg0)) != TYPE_MODE (TREE_TYPE (arg1))) + return 0; --- a/src/gcc/objc/ChangeLog.linaro +++ b/src/gcc/objc/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -540,7 +743,180 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/ChangeLog.linaro +++ b/src/gcc/ChangeLog.linaro -@@ -0,0 +1,1075 @@ +@@ -0,0 +1,1248 @@ ++2013-07-03 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Revert backport from trunk r198928,198973,199203. ++ 2013-05-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> ++ ++ PR target/19599 ++ PR target/57340 ++ * config/arm/arm.c (any_sibcall_uses_r3): Rename to .. ++ (any_sibcall_could_use_r3): this and handle indirect calls. ++ (arm_get_frame_offsets): Rename use of any_sibcall_uses_r3. ++ ++ 2013-05-16 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> ++ ++ PR target/19599 ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Add check ++ for NULL decl. ++ ++ 2013-05-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> ++ ++ PR target/19599 ++ * config/arm/predicates.md (call_insn_operand): New predicate. ++ * config/arm/constraints.md ("Cs", "Ss"): New constraints. ++ * config/arm/arm.md (*call_insn, *call_value_insn): Match only ++ if insn is not a tail call. ++ (*sibcall_insn, *sibcall_value_insn): Adjust for tailcalling through ++ registers. ++ * config/arm/arm.h (enum reg_class): New caller save register class. ++ (REG_CLASS_NAMES): Likewise. ++ (REG_CLASS_CONTENTS): Likewise. ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling ++ without decls. ++ ++2013-07-03 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Revert backport from mainline (r199438, r199439) ++ 2013-05-30 Zhenqiang Chen <zhenqiang.chen@linaro.org> ++ ++ * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added. ++ (arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes. ++ (arm_emit_vfp_multi_reg_pop): Likewise. ++ (thumb2_emit_ldrd_pop): Likewise. ++ (arm_expand_epilogue): Add misc REG_CFA notes. ++ (arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE. ++ ++ 2013-05-30 Bernd Schmidt <bernds@codesourcery.com> ++ Zhenqiang Chen <zhenqiang.chen@linaro.org> ++ ++ * config/arm/arm-protos.h: Add and update function protos. ++ * config/arm/arm.c (use_simple_return_p): New added. ++ (thumb2_expand_return): Check simple_return flag. ++ * config/arm/arm.md: Add simple_return and conditional simple_return. ++ * config/arm/iterators.md: Add iterator for return and simple_return. ++ * gcc.dg/shrink-wrap-alloca.c: New added. ++ * gcc.dg/shrink-wrap-pretend.c: New added. ++ * gcc.dg/shrink-wrap-sibcall.c: New added. ++ ++2013-07-03 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r199640, 199705, 199733, 199734, 199739. ++ 2013-06-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com> ++ ++ * rtl.def: Add extra fourth optional field to define_cond_exec. ++ * gensupport.c (process_one_cond_exec): Process attributes from ++ define_cond_exec. ++ * doc/md.texi: Document fourth field in define_cond_exec. ++ ++ 2013-06-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com> ++ ++ * config/arm/arm.md (enabled_for_depr_it): New attribute. ++ (predicable_short_it): Likewise. ++ (predicated): Likewise. ++ (enabled): Handle above. ++ (define_cond_exec): Set predicated attribute to yes. ++ ++ 2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> ++ ++ * config/arm/sync.md (atomic_loaddi_1): ++ Disable predication for arm_restrict_it. ++ (arm_load_exclusive<mode>): Likewise. ++ (arm_load_exclusivesi): Likewise. ++ (arm_load_exclusivedi): Likewise. ++ (arm_load_acquire_exclusive<mode>): Likewise. ++ (arm_load_acquire_exclusivesi): Likewise. ++ (arm_load_acquire_exclusivedi): Likewise. ++ (arm_store_exclusive<mode>): Likewise. ++ (arm_store_exclusive<mode>): Likewise. ++ (arm_store_release_exclusivedi): Likewise. ++ (arm_store_release_exclusive<mode>): Likewise. ++ ++ 2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> ++ ++ * config/arm/arm-ldmstm.ml: Set "predicable_short_it" to "no" ++ where appropriate. ++ * config/arm/ldmstm.md: Regenerate. ++ ++ 2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> ++ ++ * config/arm/arm-fixed.md (add<mode>3,usadd<mode>3,ssadd<mode>3, ++ sub<mode>3, ussub<mode>3, sssub<mode>3, arm_ssatsihi_shift, ++ arm_usatsihi): Adjust alternatives for arm_restrict_it. ++ ++2013-07-02 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 200096 ++ ++ 2013-06-14 Vidya Praveen <vidyapraveen@arm.com> ++ ++ * config/aarch64/aarch64-simd.md (aarch64_<su>mlal_lo<mode>): ++ New pattern. ++ (aarch64_<su>mlal_hi<mode>, aarch64_<su>mlsl_lo<mode>): Likewise. ++ (aarch64_<su>mlsl_hi<mode>, aarch64_<su>mlal<mode>): Likewise. ++ (aarch64_<su>mlsl<mode>): Likewise. ++ ++2013-07-02 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 200062 ++ ++ 2013-06-13 Bin Cheng <bin.cheng@arm.com> ++ * fold-const.c (operand_equal_p): Consider NOP_EXPR and ++ CONVERT_EXPR as equal nodes. ++ ++2013-07-02 Rob Savoye <rob.savoye@linaro.org> ++ Backport from trunk 199810 ++ ++ 2013-06-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com> ++ ++ * config/arm/arm.md (anddi3_insn): Remove duplicate alternatives. ++ Clean up alternatives. ++ ++2013-06-20 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 200152 ++ 2013-06-17 Sofiane Naci <sofiane.naci@arm.com> ++ ++ * config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>): Add r<-w ++ alternative and update. ++ (aarch64_dup_lanedi): Delete. ++ * config/aarch64/arm_neon.h (vdup<bhsd>_lane_*): Update. ++ * config/aarch64/aarch64-simd-builtins.def: Update. ++ ++2013-06-20 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 200061 ++ 2013-06-13 Bin Cheng <bin.cheng@arm.com> ++ ++ * rtlanal.c (noop_move_p): Check the code to be executed for ++ COND_EXEC. ++ ++2013-06-20 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 199694 ++ 2013-06-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com> ++ ++ * config/arm/arm.c (MAX_INSN_PER_IT_BLOCK): New macro. ++ (arm_option_override): Override arm_restrict_it where appropriate. ++ (thumb2_final_prescan_insn): Use MAX_INSN_PER_IT_BLOCK. ++ * config/arm/arm.opt (mrestrict-it): New command-line option. ++ * doc/invoke.texi: Document -mrestrict-it. ++ ++2013-06-20 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198683. ++ 2013-05-07 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ * config/arm/arm.c (arm_asan_shadow_offset): New function. ++ (TARGET_ASAN_SHADOW_OFFSET): Define. ++ * config/arm/linux-eabi.h (ASAN_CC1_SPEC): Define. ++ (LINUX_OR_ANDROID_CC): Add ASAN_CC1_SPEC. ++ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-06-06 Zhenqiang Chen <zhenqiang.chen@linaro.org> + + Backport from mainline (r199438, r199439) @@ -1801,19 +2177,6 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "stlex" 4 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/pr19599.c -+++ b/src/gcc/testsuite/gcc.target/arm/pr19599.c -@@ -0,0 +1,10 @@ -+/* { dg-skip-if "need at least armv5te" { *-*-* } { "-march=armv[234]*" } { "" } } */ -+/* { dg-options "-O2 -march=armv5te -marm" } */ -+/* { dg-final { scan-assembler "bx" } } */ -+ -+int (*indirect_func)(); -+ -+int indirect_call() -+{ -+ return indirect_func(); -+} --- a/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c +++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c @@ -0,0 +1,10 @@ @@ -2042,6 +2405,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ +/* { dg-final {scan-assembler-times "vshr" 0} } */ --- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c +++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c +@@ -4,7 +4,7 @@ + + #include <string.h> + +-char dest[16]; ++char dest[16] = { 0 }; + + void aligned_dest (char *src) + { @@ -14,7 +14,10 @@ /* Expect a multi-word store for the main part of the copy, but subword loads/stores for the remainder. */ @@ -2248,6 +2620,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ +/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */ --- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c +++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c +@@ -4,7 +4,7 @@ + + #include <string.h> + +-char src[16]; ++char src[16] = {0}; + + void aligned_src (char *dest) + { @@ -14,8 +14,11 @@ /* Expect a multi-word load for the main part of the copy, but subword loads/stores for the remainder. */ @@ -2312,6 +2693,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ +/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */ --- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c +++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c +@@ -4,8 +4,8 @@ + + #include <string.h> + +-char src[16]; +-char dest[16]; ++char src[16] = { 0 }; ++char dest[16] = { 0 }; + + void aligned_both (void) + { @@ -14,5 +14,9 @@ /* We know both src and dest to be aligned: expect multiword loads/stores. */ @@ -2395,20 +2787,6 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ +/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/pr40887.c -+++ b/src/gcc/testsuite/gcc.target/arm/pr40887.c -@@ -2,9 +2,9 @@ - /* { dg-options "-O2 -march=armv5te" } */ - /* { dg-final { scan-assembler "blx" } } */ - --int (*indirect_func)(); -+int (*indirect_func)(int x); - - int indirect_call() - { -- return indirect_func(); -+ return indirect_func(20) + indirect_func (40); - } --- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c +++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c @@ -0,0 +1,18 @@ @@ -2724,6 +3102,334 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ +{ + return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL); +} +--- a/src/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c +@@ -0,0 +1,325 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model" } */ ++ ++typedef signed char S8_t; ++typedef signed short S16_t; ++typedef signed int S32_t; ++typedef signed long S64_t; ++typedef signed char *__restrict__ pS8_t; ++typedef signed short *__restrict__ pS16_t; ++typedef signed int *__restrict__ pS32_t; ++typedef signed long *__restrict__ pS64_t; ++typedef unsigned char U8_t; ++typedef unsigned short U16_t; ++typedef unsigned int U32_t; ++typedef unsigned long U64_t; ++typedef unsigned char *__restrict__ pU8_t; ++typedef unsigned short *__restrict__ pU16_t; ++typedef unsigned int *__restrict__ pU32_t; ++typedef unsigned long *__restrict__ pU64_t; ++ ++extern void abort (); ++ ++void ++test_addS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c) ++{ ++ int i; ++ for (i = 0; i < 4; i++) ++ a[i] += (S64_t) b[i] * (S64_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.2d" } } */ ++ ++void ++test_addS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c) ++{ ++ int i; ++ for (i = 0; i < 8; i++) ++ a[i] += (S32_t) b[i] * (S32_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.4s" } } */ ++ ++void ++test_addS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (S16_t) b[i] * (S16_t) c[i]; ++} ++ ++void ++test_addS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (S16_t) -b[i] * (S16_t) -c[i]; ++} ++ ++void ++test_addS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (S16_t) b[i] * (S16_t) -c[i]; ++} ++ ++void ++test_addS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (S16_t) -b[i] * (S16_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler-times "smlal\tv\[0-9\]+\.8h" 4 } } */ ++/* { dg-final { scan-assembler-times "smlal2\tv\[0-9\]+\.8h" 4 } } */ ++ ++void ++test_subS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c) ++{ ++ int i; ++ for (i = 0; i < 4; i++) ++ a[i] -= (S64_t) b[i] * (S64_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.2d" } } */ ++ ++void ++test_subS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c) ++{ ++ int i; ++ for (i = 0; i < 8; i++) ++ a[i] -= (S32_t) b[i] * (S32_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.4s" } } */ ++ ++void ++test_subS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (S16_t) b[i] * (S16_t) c[i]; ++} ++ ++void ++test_subS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (S16_t) -b[i] * (S16_t) c[i]; ++} ++ ++void ++test_subS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (S16_t) b[i] * (S16_t) -c[i]; ++} ++ ++void ++test_subS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += -((S16_t) b[i] * (S16_t) c[i]); ++} ++ ++void ++test_subS16_tS8_t16_neg3 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (S16_t) -b[i] * (S16_t) -c[i]; ++} ++ ++/* { dg-final { scan-assembler-times "smlsl\tv\[0-9\]+\.8h" 5 } } */ ++/* { dg-final { scan-assembler-times "smlsl2\tv\[0-9\]+\.8h" 5 } } */ ++ ++void ++test_addU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c) ++{ ++ int i; ++ for (i = 0; i < 4; i++) ++ a[i] += (U64_t) b[i] * (U64_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.2d" } } */ ++ ++void ++test_addU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c) ++{ ++ int i; ++ for (i = 0; i < 8; i++) ++ a[i] += (U32_t) b[i] * (U32_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.4s" } } */ ++ ++void ++test_addU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (U16_t) b[i] * (U16_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.8h" } } */ ++/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.8h" } } */ ++ ++void ++test_subU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c) ++{ ++ int i; ++ for (i = 0; i < 4; i++) ++ a[i] -= (U64_t) b[i] * (U64_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.2d" } } */ ++ ++void ++test_subU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c) ++{ ++ int i; ++ for (i = 0; i < 8; i++) ++ a[i] -= (U32_t) b[i] * (U32_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.4s" } } */ ++ ++void ++test_subU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (U16_t) b[i] * (U16_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.8h" } } */ ++/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.8h" } } */ ++ ++ ++S64_t add_rS64[4] = { 6, 7, -4, -3 }; ++S32_t add_rS32[8] = { 6, 7, -4, -3, 10, 11, 0, 1 }; ++S16_t add_rS16[16] = ++ { 6, 7, -4, -3, 10, 11, 0, 1, 14, 15, 4, 5, 18, 19, 8, 9 }; ++ ++S64_t sub_rS64[4] = { 0, 1, 2, 3 }; ++S32_t sub_rS32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; ++S16_t sub_rS16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++ ++U64_t add_rU64[4] = { 0x6, 0x7, 0x2fffffffc, 0x2fffffffd }; ++ ++U32_t add_rU32[8] = ++{ ++ 0x6, 0x7, 0x2fffc, 0x2fffd, ++ 0xa, 0xb, 0x30000, 0x30001 ++}; ++ ++U16_t add_rU16[16] = ++{ ++ 0x6, 0x7, 0x2fc, 0x2fd, 0xa, 0xb, 0x300, 0x301, ++ 0xe, 0xf, 0x304, 0x305, 0x12, 0x13, 0x308, 0x309 ++}; ++ ++U64_t sub_rU64[4] = { 0, 1, 2, 3 }; ++U32_t sub_rU32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; ++U16_t sub_rU16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++ ++S8_t neg_r[16] = { -6, -5, 8, 9, -2, -1, 12, 13, 2, 3, 16, 17, 6, 7, 20, 21 }; ++ ++S64_t S64_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++S32_t S32_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 }; ++S32_t S32_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }; ++ ++S32_t S32_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++S16_t S16_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 }; ++S16_t S16_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }; ++ ++S16_t S16_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++S8_t S8_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 }; ++S8_t S8_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }; ++ ++ ++#define CHECK(T,N,AS,US) \ ++do \ ++ { \ ++ for (i = 0; i < N; i++) \ ++ if (S##T##_ta[i] != AS##_r##US##T[i]) \ ++ abort (); \ ++ } \ ++while (0) ++ ++#define SCHECK(T,N,AS) CHECK(T,N,AS,S) ++#define UCHECK(T,N,AS) CHECK(T,N,AS,U) ++ ++#define NCHECK(RES) \ ++do \ ++ { \ ++ for (i = 0; i < 16; i++) \ ++ if (S16_ta[i] != RES[i]) \ ++ abort (); \ ++ } \ ++while (0) ++ ++ ++int ++main () ++{ ++ int i; ++ ++ test_addS64_tS32_t4 (S64_ta, S32_tb, S32_tc); ++ SCHECK (64, 4, add); ++ test_addS32_tS16_t8 (S32_ta, S16_tb, S16_tc); ++ SCHECK (32, 8, add); ++ test_addS16_tS8_t16 (S16_ta, S8_tb, S8_tc); ++ SCHECK (16, 16, add); ++ test_subS64_tS32_t4 (S64_ta, S32_tb, S32_tc); ++ SCHECK (64, 4, sub); ++ test_subS32_tS16_t8 (S32_ta, S16_tb, S16_tc); ++ SCHECK (32, 8, sub); ++ test_subS16_tS8_t16 (S16_ta, S8_tb, S8_tc); ++ SCHECK (16, 16, sub); ++ ++ test_addU64_tU32_t4 (S64_ta, S32_tb, S32_tc); ++ UCHECK (64, 4, add); ++ test_addU32_tU16_t8 (S32_ta, S16_tb, S16_tc); ++ UCHECK (32, 8, add); ++ test_addU16_tU8_t16 (S16_ta, S8_tb, S8_tc); ++ UCHECK (16, 16, add); ++ test_subU64_tU32_t4 (S64_ta, S32_tb, S32_tc); ++ UCHECK (64, 4, sub); ++ test_subU32_tU16_t8 (S32_ta, S16_tb, S16_tc); ++ UCHECK (32, 8, sub); ++ test_subU16_tU8_t16 (S16_ta, S8_tb, S8_tc); ++ UCHECK (16, 16, sub); ++ ++ test_addS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc); ++ NCHECK (add_rS16); ++ test_subS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc); ++ NCHECK (sub_rS16); ++ test_addS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc); ++ NCHECK (add_rS16); ++ test_subS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc); ++ NCHECK (sub_rS16); ++ test_addS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc); ++ NCHECK (add_rS16); ++ test_subS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc); ++ NCHECK (sub_rS16); ++ test_subS16_tS8_t16_neg3 (S16_ta, S8_tb, S8_tc); ++ NCHECK (neg_r); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/extr.c +++ b/src/gcc/testsuite/gcc.target/aarch64/extr.c @@ -0,0 +1,34 @@ @@ -4036,7 +4742,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ +++ b/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c @@ -1,8 +1,14 @@ /* { dg-do compile } */ - /* { dg-options "-O2" } */ +-/* { dg-options "-O2" } */ ++/* { dg-options "-O2 -dp" } */ -#include "../../../config/aarch64/arm_neon.h" +#include <arm_neon.h> @@ -4185,7 +4892,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ } /* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -@@ -107,15 +161,24 @@ +@@ -107,18 +161,27 @@ uint64x1_t test_vclezd_s64 (int64x1_t a) { @@ -4212,13 +4919,35 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + return res; } - /* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */ +-/* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */ ++/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv16qi" 2 } } */ + + int8x1_t + test_vdupb_lane_s8 (int8x16_t a) +@@ -132,7 +195,7 @@ + return vdupb_lane_u8 (a, 2); + } + +-/* { dg-final { scan-assembler-times "\\tdup\\th\[0-9\]+, v\[0-9\]+\.h" 2 } } */ ++/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv8hi" 2 } } */ + + int16x1_t + test_vduph_lane_s16 (int16x8_t a) +@@ -146,7 +209,7 @@ + return vduph_lane_u16 (a, 2); + } + +-/* { dg-final { scan-assembler-times "\\tdup\\ts\[0-9\]+, v\[0-9\]+\.s" 2 } } */ ++/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv4si" 2 } } */ + + int32x1_t + test_vdups_lane_s32 (int32x4_t a) @@ -160,18 +223,18 @@ return vdups_lane_u32 (a, 2); } -/* { dg-final { scan-assembler-times "\\tdup\\td\[0-9\]+, v\[0-9\]+\.d" 2 } } */ -+/* { dg-final { scan-assembler-times "\\tumov\\tx\[0-9\]+, v\[0-9\]+\.d" 2 } } */ ++/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv2di" 2 } } */ int64x1_t test_vdupd_lane_s64 (int64x2_t a) @@ -6465,9 +7194,136 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ # Return 1 if this is a ARM target with NEON enabled. proc check_effective_target_arm_neon { } { +@@ -4591,6 +4668,33 @@ + return 0 + } + ++# Return 1 if programs are intended to be run on hardware rather than ++# on a simulator ++ ++proc check_effective_target_hw { } { ++ ++ # All "src/sim" simulators set this one. ++ if [board_info target exists is_simulator] { ++ if [board_info target is_simulator] { ++ return 0 ++ } else { ++ return 1 ++ } ++ } ++ ++ # The "sid" simulators don't set that one, but at least they set ++ # this one. ++ if [board_info target exists slow_simulator] { ++ if [board_info target slow_simulator] { ++ return 0 ++ } else { ++ return 1 ++ } ++ } ++ ++ return 1 ++} ++ + # Return 1 if the target is a VxWorks kernel. + + proc check_effective_target_vxworks_kernel { } { --- a/src/gcc/testsuite/ChangeLog.linaro +++ b/src/gcc/testsuite/ChangeLog.linaro -@@ -0,0 +1,374 @@ +@@ -0,0 +1,467 @@ ++2013-07-03 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Revert backport from trunk r198928. ++ 2013-05-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> ++ ++ PR target/19599 ++ * gcc.target/arm/pr40887.c: Adjust testcase. ++ * gcc.target/arm/pr19599.c: New test. ++ ++2013-07-03 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Revert backport from trunk 199439, 199533 ++ 2013-05-31 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> ++ ++ * gcc.dg/shrink-wrap-alloca.c: Use __builtin_alloca. ++ ++ 2013-05-30 Zhenqiang Chen <zhenqiang.chen@linaro.org> ++ ++ * gcc.dg/shrink-wrap-alloca.c: New added. ++ * gcc.dg/shrink-wrap-pretend.c: New added. ++ * gcc.dg/shrink-wrap-sibcall.c: New added. ++ ++2013-07-02 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 200096 ++ ++ 2013-06-14 Vidya Praveen <vidyapraveen@arm.com> ++ ++ * gcc.target/aarch64/vect_smlal_1.c: New file. ++ ++2013-07-02 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 200019 ++ 2013-06-12 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> ++ ++ * gcc.target/arm/unaligned-memcpy-4.c (src, dst): Initialize ++ to ensure alignment. ++ * gcc.target/arm/unaligned-memcpy-3.c (src): Likewise. ++ ++2013-06-20 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 200152 ++ 2013-06-17 Sofiane Naci <sofiane.naci@arm.com> ++ ++ * gcc.target/aarch64/scalar_intrinsics.c: Update. ++ ++2013-06-20 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 200148 ++ 2013-06-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com> ++ ++ * gcc.target/arm/unaligned-memcpy-2.c (dest): Initialize to ++ ensure alignment. ++ ++2013-06-20 Rob Savoye <rob.savoye@linaro.org> ++ ++ Backport from trunk 199533 ++ 2013-05-31 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> ++ ++ * gcc.dg/shrink-wrap-alloca.c: Use __builtin_alloca. ++ ++2013-06-20 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ Backport from trunk r198683. ++ 2013-05-07 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ * lib/target-supports.exp (check_effective_target_hw): New ++ function. ++ * c-c++-common/asan/clone-test-1.c: Call ++ check_effective_target_hw. ++ * c-c++-common/asan/rlimit-mmap-test-1.c: Likewise. ++ * c-c++-common/asan/heap-overflow-1.c: Update regexps to accept ++ possible decorations. ++ * c-c++-common/asan/null-deref-1.c: Likewise. ++ * c-c++-common/asan/stack-overflow-1.c: Likewise. ++ * c-c++-common/asan/strncpy-overflow-1.c: Likewise. ++ * c-c++-common/asan/use-after-free-1.c: Likewise. ++ * g++.dg/asan/deep-thread-stack-1.C: Likewise. ++ * g++.dg/asan/large-func-test-1.C: Likewise. ++ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ ++2013-06-06 Zhenqiang Chen <zhenqiang.chen@linaro.org> ++ ++ Backport from mainline r199439. ++ 2013-05-30 Zhenqiang Chen <zhenqiang.chen@linaro.org> ++ ++ * gcc.dg/shrink-wrap-alloca.c: New added. ++ * gcc.dg/shrink-wrap-pretend.c: New added. ++ * gcc.dg/shrink-wrap-sibcall.c: New added. ++ +2013-06-05 Christophe Lyon <christophe.lyon@linaro.org> + + Backport from trunk r199658. @@ -6842,61 +7698,6 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * gcc.target/aarch64/vect-fp-compile.c: Check for fabd + instruction in assembly. + * gcc.target/aarch64/vect-fp.x: Add fabd test function. ---- a/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c -+++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -g" } */ -+ -+extern int * alloca (int); -+ -+int *p; -+ -+void -+test (int a) -+{ -+ if (a > 0) -+ p = alloca (4); -+} ---- a/src/gcc/testsuite/gcc.dg/shrink-wrap-pretend.c -+++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-pretend.c -@@ -0,0 +1,36 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -g" } */ -+ -+#include <stdlib.h> -+#include <stdio.h> -+#include <stdarg.h> -+ -+#define DEBUG_BUFFER_SIZE 80 -+int unifi_debug = 5; -+ -+void -+unifi_trace (void* ospriv, int level, const char *fmt, ...) -+{ -+ static char s[DEBUG_BUFFER_SIZE]; -+ va_list args; -+ unsigned int len; -+ -+ if (!ospriv) -+ return; -+ -+ if (unifi_debug >= level) -+ { -+ va_start (args, fmt); -+ len = vsnprintf (&(s)[0], (DEBUG_BUFFER_SIZE), fmt, args); -+ va_end (args); -+ -+ if (len >= DEBUG_BUFFER_SIZE) -+ { -+ (s)[DEBUG_BUFFER_SIZE - 2] = '\n'; -+ (s)[DEBUG_BUFFER_SIZE - 1] = 0; -+ } -+ -+ printf ("%s", s); -+ } -+} -+ --- a/src/gcc/testsuite/gcc.dg/debug/pr57351.c +++ b/src/gcc/testsuite/gcc.dg/debug/pr57351.c @@ -0,0 +1,54 @@ @@ -6954,38 +7755,124 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + } + } +} ---- a/src/gcc/testsuite/gcc.dg/shrink-wrap-sibcall.c -+++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-sibcall.c -@@ -0,0 +1,26 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -g" } */ -+ -+unsigned char a, b, d, f, g; -+ -+int test (void); -+ -+int -+baz (int c) -+{ -+ if (c == 0) return test (); -+ if (b & 1) -+ { -+ g = 0; -+ int e = (a & 0x0f) - (g & 0x0f); -+ -+ if (!a) b |= 0x80; -+ a = e + test (); -+ f = g/5 + a*3879 + b *2985; -+ } -+ else -+ { -+ f = g + a*39879 + b *25; -+ } -+ return test (); -+} +--- a/src/gcc/testsuite/g++.dg/asan/large-func-test-1.C ++++ b/src/gcc/testsuite/g++.dg/asan/large-func-test-1.C +@@ -37,9 +37,9 @@ + + // { dg-output "ERROR: AddressSanitizer:? heap-buffer-overflow on address\[^\n\r]*" } + // { dg-output "0x\[0-9a-f\]+ at pc 0x\[0-9a-f\]+ bp 0x\[0-9a-f\]+ sp 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } +-// { dg-output "READ of size 4 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*READ of size 4 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } + // { dg-output " #0 0x\[0-9a-f\]+ (in \[^\n\r]*LargeFunction\[^\n\r]*(large-func-test-1.C:18|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } +-// { dg-output "0x\[0-9a-f\]+ is located 44 bytes to the right of 400-byte region.*(\n|\r\n|\r)" } +-// { dg-output "allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 44 bytes to the right of 400-byte region.*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } + // { dg-output " #0( 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } + // { dg-output " #1|) 0x\[0-9a-f\]+ (in (operator new|_*_Zn\[aw\]\[mj\])|\[(\])\[^\n\r]*(\n|\r\n|\r)" } +--- a/src/gcc/testsuite/g++.dg/asan/deep-thread-stack-1.C ++++ b/src/gcc/testsuite/g++.dg/asan/deep-thread-stack-1.C +@@ -45,9 +45,9 @@ + } + + // { dg-output "ERROR: AddressSanitizer: heap-use-after-free.*(\n|\r\n|\r)" } +-// { dg-output "WRITE of size 4 at 0x\[0-9a-f\]+ thread T(\[0-9\]+).*(\n|\r\n|\r)" } +-// { dg-output "freed by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } +-// { dg-output "previously allocated by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*WRITE of size 4 at 0x\[0-9a-f\]+ thread T(\[0-9\]+).*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*freed by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*previously allocated by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } + // { dg-output "Thread T\\2 created by T(\[0-9\]+) here:.*(\n|\r\n|\r)" } + // { dg-output "Thread T\\8 created by T0 here:.*(\n|\r\n|\r)" } + // { dg-output "Thread T\\4 created by T(\[0-9\]+) here:.*(\n|\r\n|\r)" } +--- a/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c +@@ -15,7 +15,7 @@ + /* { dg-output "WRITE of size \[0-9\]* at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)strncpy|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*strncpy-overflow-1.c:11|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "0x\[0-9a-f\]+ is located 0 bytes to the right of 9-byte region\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 0 bytes to the right of 9-byte region\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*strncpy-overflow-1.c:10|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ +--- a/src/gcc/testsuite/c-c++-common/asan/rlimit-mmap-test-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/rlimit-mmap-test-1.c +@@ -2,6 +2,7 @@ + + /* { dg-do run { target setrlimit } } */ + /* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */ ++/* { dg-require-effective-target hw } */ + /* { dg-shouldfail "asan" } */ + + #include <stdlib.h> +--- a/src/gcc/testsuite/c-c++-common/asan/stack-overflow-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/stack-overflow-1.c +@@ -19,4 +19,4 @@ + + /* { dg-output "READ of size 1 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*stack-overflow-1.c:16|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "Address 0x\[0-9a-f\]+ is\[^\n\r]*frame <main>" } */ ++/* { dg-output "\[^\n\r]*Address 0x\[0-9a-f\]+ is\[^\n\r]*frame <main>" } */ +--- a/src/gcc/testsuite/c-c++-common/asan/use-after-free-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/use-after-free-1.c +@@ -11,12 +11,12 @@ + + /* { dg-output "ERROR: AddressSanitizer:? heap-use-after-free on address\[^\n\r]*" } */ + /* { dg-output "0x\[0-9a-f\]+ at pc 0x\[0-9a-f\]+ bp 0x\[0-9a-f\]+ sp 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "READ of size 1 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*READ of size 1 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*use-after-free-1.c:9|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "0x\[0-9a-f\]+ is located 5 bytes inside of 10-byte region .0x\[0-9a-f\]+,0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "freed by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 5 bytes inside of 10-byte region .0x\[0-9a-f\]+,0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*freed by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)free|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*use-after-free-1.c:8|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "previously allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*previously allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*use-after-free-1.c:7|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ +--- a/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c +@@ -3,6 +3,7 @@ + + /* { dg-do run { target { *-*-linux* } } } */ + /* { dg-require-effective-target clone } */ ++/* { dg-require-effective-target hw } */ + /* { dg-options "-D_GNU_SOURCE" } */ + + #include <stdio.h> +--- a/src/gcc/testsuite/c-c++-common/asan/heap-overflow-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/heap-overflow-1.c +@@ -25,7 +25,7 @@ + + /* { dg-output "READ of size 1 at 0x\[0-9a-f\]+ thread T0.*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*heap-overflow-1.c:21|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "0x\[0-9a-f\]+ is located 0 bytes to the right of 10-byte region\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 0 bytes to the right of 10-byte region\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*heap-overflow-1.c:19|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ +--- a/src/gcc/testsuite/c-c++-common/asan/null-deref-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/null-deref-1.c +@@ -18,6 +18,6 @@ + + /* { dg-output "ERROR: AddressSanitizer:? SEGV on unknown address\[^\n\r]*" } */ + /* { dg-output "0x\[0-9a-f\]+ \[^\n\r]*pc 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "AddressSanitizer can not provide additional info.*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*AddressSanitizer can not provide additional info.*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in \[^\n\r]*NullDeref\[^\n\r]* (\[^\n\r]*null-deref-1.c:10|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*null-deref-1.c:15|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ --- a/src/gcc/objcp/ChangeLog.linaro +++ b/src/gcc/objcp/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -6995,7 +7882,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/cp/ChangeLog.linaro +++ b/src/gcc/cp/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -7003,9 +7894,27 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ +2013-04-09 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/rtl.def ++++ b/src/gcc/rtl.def +@@ -937,8 +937,9 @@ + relational operator. Operands should have only one alternative. + 1: A C expression giving an additional condition for recognizing + the generated pattern. +- 2: A template or C code to produce assembler output. */ +-DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) ++ 2: A template or C code to produce assembler output. ++ 3: A vector of attributes to append to the resulting cond_exec insn. */ ++DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA) + + /* Definition of an operand predicate. The difference between + DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will --- a/src/gcc/go/ChangeLog.linaro +++ b/src/gcc/go/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -7015,7 +7924,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/ada/ChangeLog.linaro +++ b/src/gcc/ada/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -7036,7 +7949,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ --- a/src/gcc/fortran/ChangeLog.linaro +++ b/src/gcc/fortran/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -7079,7 +7996,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ return changed; --- a/src/gcc/lto/ChangeLog.linaro +++ b/src/gcc/lto/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -7089,7 +8010,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/po/ChangeLog.linaro +++ b/src/gcc/po/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -7183,36 +8108,31 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (eq_attr "simd_type" "none") (const_string "none") ] (const_string "unknown"))) -@@ -356,7 +358,7 @@ +@@ -355,15 +357,17 @@ + (set_attr "simd_mode" "<MODE>")] ) - (define_insn "aarch64_dup_lane<mode>" +-(define_insn "aarch64_dup_lane<mode>" - [(set (match_operand:SDQ_I 0 "register_operand" "=w") -+ [(set (match_operand:ALLX 0 "register_operand" "=w") ++(define_insn "aarch64_dup_lane_scalar<mode>" ++ [(set (match_operand:<VEL> 0 "register_operand" "=w, r") (vec_select:<VEL> - (match_operand:<VCON> 1 "register_operand" "w") - (parallel [(match_operand:SI 2 "immediate_operand" "i")]) -@@ -367,6 +369,19 @@ +- (match_operand:<VCON> 1 "register_operand" "w") +- (parallel [(match_operand:SI 2 "immediate_operand" "i")]) ++ (match_operand:VDQ 1 "register_operand" "w, w") ++ (parallel [(match_operand:SI 2 "immediate_operand" "i, i")]) + ))] + "TARGET_SIMD" +- "dup\\t%<v>0<Vmtype>, %1.<Vetype>[%2]" +- [(set_attr "simd_type" "simd_dup") ++ "@ ++ dup\\t%<Vetype>0, %1.<Vetype>[%2] ++ umov\\t%<vw>0, %1.<Vetype>[%2]" ++ [(set_attr "simd_type" "simd_dup, simd_movgp") (set_attr "simd_mode" "<MODE>")] ) -+(define_insn "aarch64_dup_lanedi" -+ [(set (match_operand:DI 0 "register_operand" "=w,r") -+ (vec_select:DI -+ (match_operand:V2DI 1 "register_operand" "w,w") -+ (parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))] -+ "TARGET_SIMD" -+ "@ -+ dup\\t%<v>0<Vmtype>, %1.<Vetype>[%2] -+ umov\t%0, %1.d[%2]" -+ [(set_attr "simd_type" "simd_dup") -+ (set_attr "simd_mode" "DI")] -+) -+ - (define_insn "aarch64_simd_dup<mode>" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (vec_duplicate:VDQF (match_operand:<VEL> 1 "register_operand" "w")))] -@@ -394,7 +409,7 @@ +@@ -394,7 +398,7 @@ case 4: return "ins\t%0.d[0], %1"; case 5: return "mov\t%0, %1"; case 6: @@ -7221,7 +8141,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ <MODE>mode, 64); default: gcc_unreachable (); } -@@ -417,13 +432,13 @@ +@@ -417,13 +421,13 @@ case 0: return "ld1\t{%0.<Vtype>}, %1"; case 1: return "st1\t{%1.<Vtype>}, %0"; case 2: return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>"; @@ -7240,7 +8160,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ } } [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm") -@@ -452,6 +467,105 @@ +@@ -452,6 +456,105 @@ aarch64_simd_disambiguate_copy (operands, dest, src, 2); }) @@ -7346,7 +8266,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "orn<mode>3" [(set (match_operand:VDQ 0 "register_operand" "=w") (ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w")) -@@ -503,8 +617,8 @@ +@@ -503,8 +606,8 @@ ) (define_insn "neg<mode>2" @@ -7357,7 +8277,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ "TARGET_SIMD" "neg\t%0.<Vtype>, %1.<Vtype>" [(set_attr "simd_type" "simd_negabs") -@@ -520,6 +634,51 @@ +@@ -520,6 +623,51 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -7409,7 +8329,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "and<mode>3" [(set (match_operand:VDQ 0 "register_operand" "=w") (and:VDQ (match_operand:VDQ 1 "register_operand" "w") -@@ -904,12 +1063,12 @@ +@@ -904,12 +1052,12 @@ ) ;; Max/Min operations. @@ -7424,7 +8344,112 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "simd_type" "simd_minmax") (set_attr "simd_mode" "<MODE>")] ) -@@ -1196,7 +1355,9 @@ +@@ -1045,6 +1193,104 @@ + + ;; Widening arithmetic. + ++(define_insn "*aarch64_<su>mlal_lo<mode>" ++ [(set (match_operand:<VWIDE> 0 "register_operand" "=w") ++ (plus:<VWIDE> ++ (mult:<VWIDE> ++ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> ++ (match_operand:VQW 2 "register_operand" "w") ++ (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) ++ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> ++ (match_operand:VQW 4 "register_operand" "w") ++ (match_dup 3)))) ++ (match_operand:<VWIDE> 1 "register_operand" "0")))] ++ "TARGET_SIMD" ++ "<su>mlal\t%0.<Vwtype>, %2.<Vhalftype>, %4.<Vhalftype>" ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "<MODE>")] ++) ++ ++(define_insn "*aarch64_<su>mlal_hi<mode>" ++ [(set (match_operand:<VWIDE> 0 "register_operand" "=w") ++ (plus:<VWIDE> ++ (mult:<VWIDE> ++ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> ++ (match_operand:VQW 2 "register_operand" "w") ++ (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) ++ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> ++ (match_operand:VQW 4 "register_operand" "w") ++ (match_dup 3)))) ++ (match_operand:<VWIDE> 1 "register_operand" "0")))] ++ "TARGET_SIMD" ++ "<su>mlal2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vtype>" ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "<MODE>")] ++) ++ ++(define_insn "*aarch64_<su>mlsl_lo<mode>" ++ [(set (match_operand:<VWIDE> 0 "register_operand" "=w") ++ (minus:<VWIDE> ++ (match_operand:<VWIDE> 1 "register_operand" "0") ++ (mult:<VWIDE> ++ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> ++ (match_operand:VQW 2 "register_operand" "w") ++ (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) ++ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> ++ (match_operand:VQW 4 "register_operand" "w") ++ (match_dup 3))))))] ++ "TARGET_SIMD" ++ "<su>mlsl\t%0.<Vwtype>, %2.<Vhalftype>, %4.<Vhalftype>" ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "<MODE>")] ++) ++ ++(define_insn "*aarch64_<su>mlsl_hi<mode>" ++ [(set (match_operand:<VWIDE> 0 "register_operand" "=w") ++ (minus:<VWIDE> ++ (match_operand:<VWIDE> 1 "register_operand" "0") ++ (mult:<VWIDE> ++ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> ++ (match_operand:VQW 2 "register_operand" "w") ++ (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) ++ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> ++ (match_operand:VQW 4 "register_operand" "w") ++ (match_dup 3))))))] ++ "TARGET_SIMD" ++ "<su>mlsl2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vtype>" ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "<MODE>")] ++) ++ ++(define_insn "*aarch64_<su>mlal<mode>" ++ [(set (match_operand:<VWIDE> 0 "register_operand" "=w") ++ (plus:<VWIDE> ++ (mult:<VWIDE> ++ (ANY_EXTEND:<VWIDE> ++ (match_operand:VDW 1 "register_operand" "w")) ++ (ANY_EXTEND:<VWIDE> ++ (match_operand:VDW 2 "register_operand" "w"))) ++ (match_operand:<VWIDE> 3 "register_operand" "0")))] ++ "TARGET_SIMD" ++ "<su>mlal\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "<MODE>")] ++) ++ ++(define_insn "*aarch64_<su>mlsl<mode>" ++ [(set (match_operand:<VWIDE> 0 "register_operand" "=w") ++ (minus:<VWIDE> ++ (match_operand:<VWIDE> 1 "register_operand" "0") ++ (mult:<VWIDE> ++ (ANY_EXTEND:<VWIDE> ++ (match_operand:VDW 2 "register_operand" "w")) ++ (ANY_EXTEND:<VWIDE> ++ (match_operand:VDW 3 "register_operand" "w")))))] ++ "TARGET_SIMD" ++ "<su>mlsl\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>" ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "<MODE>")] ++) ++ + (define_insn "aarch64_simd_vec_<su>mult_lo_<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (mult:<VWIDE> (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> +@@ -1196,7 +1442,9 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -7435,7 +8460,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set (match_operand:VDQF 0 "register_operand" "=w") (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")] FRINT))] -@@ -1206,16 +1367,9 @@ +@@ -1206,16 +1454,9 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -7455,7 +8480,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set (match_operand:<FCVT_TARGET> 0 "register_operand" "=w") (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET> [(match_operand:VDQF 1 "register_operand" "w")] -@@ -1226,16 +1380,141 @@ +@@ -1226,16 +1467,141 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -7601,7 +8626,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "aarch64_vmls<mode>" [(set (match_operand:VDQF 0 "register_operand" "=w") (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") -@@ -1261,51 +1540,70 @@ +@@ -1261,51 +1627,70 @@ ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring ;; NaNs. @@ -7694,7 +8719,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set (match_operand:V4SF 0 "register_operand" "=w") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] UNSPEC_FADDV))] -@@ -1315,169 +1613,106 @@ +@@ -1315,169 +1700,106 @@ (set_attr "simd_mode" "V4SF")] ) @@ -7925,7 +8950,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ "TARGET_SIMD" "@ bsl\\t%0.<Vbtype>, %2.<Vbtype>, %3.<Vbtype> -@@ -1486,28 +1721,32 @@ +@@ -1486,28 +1808,32 @@ ) (define_expand "aarch64_simd_bsl<mode>" @@ -7967,7 +8992,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ rtx mask = gen_reg_rtx (<MODE>mode); switch (GET_CODE (operands[3])) -@@ -1548,12 +1787,12 @@ +@@ -1548,12 +1874,12 @@ case LTU: case GEU: @@ -7982,7 +9007,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ break; case NE: -@@ -1566,30 +1805,47 @@ +@@ -1566,30 +1892,47 @@ } if (inverse) @@ -8041,7 +9066,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ rtx (*base_comparison) (rtx, rtx, rtx); rtx (*complimentary_comparison) (rtx, rtx, rtx); -@@ -1609,7 +1865,7 @@ +@@ -1609,7 +1952,7 @@ /* Fall through. */ default: if (!REG_P (operands[5])) @@ -8050,7 +9075,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ } switch (GET_CODE (operands[3])) -@@ -1622,8 +1878,8 @@ +@@ -1622,8 +1965,8 @@ case UNGE: case ORDERED: case UNORDERED: @@ -8061,7 +9086,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ break; case LE: case UNLE: -@@ -1631,14 +1887,14 @@ +@@ -1631,14 +1974,14 @@ /* Fall through. */ case GT: case UNGT: @@ -8080,7 +9105,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ break; default: gcc_unreachable (); -@@ -1666,10 +1922,10 @@ +@@ -1666,10 +2009,10 @@ switch (GET_CODE (operands[3])) { case LT: @@ -8093,7 +9118,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ break; default: /* Do nothing, other zero form cases already have the correct -@@ -1712,9 +1968,9 @@ +@@ -1712,9 +2055,9 @@ true iff !(a != b && a ORDERED b), swapping the operands to BSL will then give us (a == b || a UNORDERED b) as intended. */ @@ -8106,7 +9131,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ swap_bsl_operands = 1; break; case UNORDERED: -@@ -1723,20 +1979,36 @@ +@@ -1723,20 +2066,36 @@ swap_bsl_operands = 1; /* Fall through. */ case ORDERED: @@ -8151,7 +9176,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ DONE; }) -@@ -1746,16 +2018,32 @@ +@@ -1746,16 +2105,32 @@ (match_operator 3 "comparison_operator" [(match_operand:VALL 4 "register_operand") (match_operand:VALL 5 "nonmemory_operand")]) @@ -8187,7 +9212,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_expand "vcondu<mode><mode>" [(set (match_operand:VDQ 0 "register_operand") -@@ -1763,11 +2051,11 @@ +@@ -1763,11 +2138,11 @@ (match_operator 3 "comparison_operator" [(match_operand:VDQ 4 "register_operand") (match_operand:VDQ 5 "nonmemory_operand")]) @@ -8202,7 +9227,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ operands[2], operands[3], operands[4], operands[5])); DONE; -@@ -2861,28 +3149,6 @@ +@@ -2861,28 +3236,6 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -8231,7 +9256,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ;; vshll_n (define_insn "aarch64_<sur>shll_n<mode>" -@@ -2927,28 +3193,6 @@ +@@ -2927,28 +3280,6 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -8260,7 +9285,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ;; vrshr_n (define_insn "aarch64_<sur>shr_n<mode>" -@@ -3034,52 +3278,180 @@ +@@ -3034,52 +3365,180 @@ ) @@ -8464,7 +9489,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ;; addp (define_insn "aarch64_addp<mode>" -@@ -3105,30 +3477,6 @@ +@@ -3105,30 +3564,6 @@ (set_attr "simd_mode" "DI")] ) @@ -8495,7 +9520,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ;; sqrt (define_insn "sqrt<mode>2" -@@ -3140,16 +3488,6 @@ +@@ -3140,16 +3575,6 @@ (set_attr "simd_mode" "<MODE>")] ) @@ -8512,7 +9537,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ;; Patterns for vector struct loads and stores. (define_insn "vec_load_lanesoi<mode>" -@@ -3714,3 +4052,25 @@ +@@ -3714,3 +4139,25 @@ "ld1r\\t{%0.<Vtype>}, %1" [(set_attr "simd_type" "simd_load1r") (set_attr "simd_mode" "<MODE>")]) @@ -12284,7 +13309,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ vcltq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__b, __a); -@@ -20450,43 +19619,616 @@ +@@ -20450,91 +19619,664 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcltq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -12907,6 +13932,62 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* vdup */ __extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) + vdupb_lane_s8 (int8x16_t a, int const b) + { +- return __builtin_aarch64_dup_laneqi (a, b); ++ return __builtin_aarch64_dup_lane_scalarv16qi (a, b); + } + + __extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) + vdupb_lane_u8 (uint8x16_t a, int const b) + { +- return (uint8x1_t) __builtin_aarch64_dup_laneqi ((int8x16_t) a, b); ++ return (uint8x1_t) __builtin_aarch64_dup_lane_scalarv16qi ((int8x16_t) a, b); + } + + __extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) + vduph_lane_s16 (int16x8_t a, int const b) + { +- return __builtin_aarch64_dup_lanehi (a, b); ++ return __builtin_aarch64_dup_lane_scalarv8hi (a, b); + } + + __extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) + vduph_lane_u16 (uint16x8_t a, int const b) + { +- return (uint16x1_t) __builtin_aarch64_dup_lanehi ((int16x8_t) a, b); ++ return (uint16x1_t) __builtin_aarch64_dup_lane_scalarv8hi ((int16x8_t) a, b); + } + + __extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) + vdups_lane_s32 (int32x4_t a, int const b) + { +- return __builtin_aarch64_dup_lanesi (a, b); ++ return __builtin_aarch64_dup_lane_scalarv4si (a, b); + } + + __extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) + vdups_lane_u32 (uint32x4_t a, int const b) + { +- return (uint32x1_t) __builtin_aarch64_dup_lanesi ((int32x4_t) a, b); ++ return (uint32x1_t) __builtin_aarch64_dup_lane_scalarv4si ((int32x4_t) a, b); + } + + __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) + vdupd_lane_s64 (int64x2_t a, int const b) + { +- return __builtin_aarch64_dup_lanedi (a, b); ++ return __builtin_aarch64_dup_lane_scalarv2di (a, b); + } + + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vdupd_lane_u64 (uint64x2_t a, int const b) + { +- return (uint64x1_t) __builtin_aarch64_dup_lanedi ((int64x2_t) a, b); ++ return (uint64x1_t) __builtin_aarch64_dup_lane_scalarv2di ((int64x2_t) a, b); + } + + /* vldn */ @@ -21408,7 +21150,7 @@ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vmax_f32 (float32x2_t __a, float32x2_t __b) @@ -13876,7 +14957,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ "(register_operand (operands[0], DImode) || aarch64_reg_or_zero (operands[1], DImode))" "@ -@@ -825,16 +856,18 @@ +@@ -825,17 +856,19 @@ mov\\t%x0, %1 mov\\t%x0, %1 ldr\\t%x0, %1 @@ -13892,12 +14973,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ - [(set_attr "v8type" "move,move,move,alu,load1,store1,adr,adr,fmov,fmov,fmov,fmov") + [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov") (set_attr "mode" "DI") -- (set_attr "fp" "*,*,*,*,*,*,*,*,yes,yes,yes,yes")] -+ (set_attr "fp" "*,*,*,*,*,*,*,*,*,*,yes,yes,yes,yes")] +- (set_attr "fp" "*,*,*,*,*,*,*,*,yes,yes,yes,*") +- (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,yes")] ++ (set_attr "fp" "*,*,*,*,*,*,*,*,*,*,yes,yes,yes,*") ++ (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")] ) (define_insn "insv_imm<mode>" -@@ -842,9 +875,8 @@ +@@ -843,9 +876,8 @@ (const_int 16) (match_operand:GPI 1 "const_int_operand" "n")) (match_operand:GPI 2 "const_int_operand" "n"))] @@ -13909,7 +14992,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ "movk\\t%<w>0, %X2, lsl %1" [(set_attr "v8type" "movk") (set_attr "mode" "<MODE>")] -@@ -1149,13 +1181,14 @@ +@@ -1150,13 +1182,14 @@ ) (define_insn "*zero_extend<SHORT:mode><GPI:mode>2_aarch64" @@ -13928,7 +15011,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (set_attr "mode" "<GPI:MODE>")] ) -@@ -1286,6 +1319,112 @@ +@@ -1287,6 +1320,112 @@ (set_attr "mode" "SI")] ) @@ -14041,7 +15124,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "*add<mode>3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ -@@ -1790,6 +1929,34 @@ +@@ -1791,6 +1930,34 @@ (set_attr "mode" "SI")] ) @@ -14076,7 +15159,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "*sub_uxt<mode>_multp2" [(set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_operand:GPI 4 "register_operand" "r") -@@ -1843,6 +2010,27 @@ +@@ -1844,6 +2011,27 @@ (set_attr "mode" "SI")] ) @@ -14104,7 +15187,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "*neg<mode>2_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ (neg:GPI (match_operand:GPI 1 "register_operand" "r")) -@@ -1868,6 +2056,21 @@ +@@ -1869,6 +2057,21 @@ (set_attr "mode" "SI")] ) @@ -14126,7 +15209,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "*neg_<shift>_<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (neg:GPI (ASHIFT:GPI -@@ -2157,6 +2360,18 @@ +@@ -2158,6 +2361,18 @@ (set_attr "mode" "<GPI:MODE>")] ) @@ -14145,7 +15228,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ;; ------------------------------------------------------------------- ;; Store-flag and conditional select insns -@@ -2210,7 +2425,7 @@ +@@ -2211,7 +2426,7 @@ (set_attr "mode" "SI")] ) @@ -14154,7 +15237,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set (match_operand:ALLI 0 "register_operand" "=r") (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)])))] -@@ -2433,6 +2648,69 @@ +@@ -2434,6 +2649,69 @@ [(set_attr "v8type" "logic,logic_imm") (set_attr "mode" "SI")]) @@ -14224,7 +15307,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI -@@ -2703,6 +2981,62 @@ +@@ -2704,6 +2982,62 @@ (set_attr "mode" "<MODE>")] ) @@ -14287,7 +15370,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>" [(set (match_operand:GPI 0 "register_operand" "=r") (ANY_EXTEND:GPI -@@ -2769,6 +3103,50 @@ +@@ -2770,6 +3104,50 @@ (set_attr "mode" "<MODE>")] ) @@ -14338,7 +15421,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "*<optab><ALLX:mode>_shft_<GPI:mode>" [(set (match_operand:GPI 0 "register_operand" "=r") (ashift:GPI (ANY_EXTEND:GPI -@@ -3089,6 +3467,27 @@ +@@ -3090,6 +3468,27 @@ (set_attr "mode" "<MODE>")] ) @@ -15090,7 +16173,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + BUILTIN_VQ (REINTERP, reinterpretv2df, 0) + + BUILTIN_VDQ_I (BINOP, dup_lane, 0) -+ BUILTIN_SDQ_I (BINOP, dup_lane, 0) ++ BUILTIN_VDQ_I (BINOP, dup_lane_scalar, 0) /* Implemented by aarch64_<sur>q<r>shl<mode>. */ - BUILTIN_VSDQ_I (BINOP, sqshl) - BUILTIN_VSDQ_I (BINOP, uqshl) @@ -16685,7 +17768,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ static int arm_arg_partial_bytes (cumulative_args_t, enum machine_mode, tree, bool); static rtx arm_function_arg (cumulative_args_t, enum machine_mode, -@@ -620,6 +621,13 @@ +@@ -280,6 +281,7 @@ + + static void arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1, + bool op0_preserve_value); ++static unsigned HOST_WIDE_INT arm_asan_shadow_offset (void); + + /* Table of machine attributes. */ + static const struct attribute_spec arm_attribute_table[] = +@@ -620,6 +622,13 @@ #undef TARGET_CLASS_LIKELY_SPILLED_P #define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p @@ -16699,7 +17790,21 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ #undef TARGET_VECTOR_ALIGNMENT #define TARGET_VECTOR_ALIGNMENT arm_vector_alignment -@@ -839,6 +847,10 @@ +@@ -649,6 +658,13 @@ + #define TARGET_CANONICALIZE_COMPARISON \ + arm_canonicalize_comparison + ++#undef TARGET_ASAN_SHADOW_OFFSET ++#define TARGET_ASAN_SHADOW_OFFSET arm_asan_shadow_offset ++ ++#undef MAX_INSN_PER_IT_BLOCK ++#define MAX_INSN_PER_IT_BLOCK (arm_restrict_it ? 1 : 4) ++ ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + /* Obstack for minipool constant handling. */ +@@ -839,6 +855,10 @@ int arm_arch_arm_hwdiv; int arm_arch_thumb_hwdiv; @@ -16710,7 +17815,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we must report the mode of the memory reference from TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */ -@@ -936,6 +948,7 @@ +@@ -936,6 +956,7 @@ false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16718,7 +17823,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; const struct tune_params arm_fastmul_tune = -@@ -950,6 +963,7 @@ +@@ -950,6 +971,7 @@ false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16726,7 +17831,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; /* StrongARM has early execution of branches, so a sequence that is worth -@@ -967,6 +981,7 @@ +@@ -967,6 +989,7 @@ false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16734,7 +17839,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; const struct tune_params arm_xscale_tune = -@@ -981,6 +996,7 @@ +@@ -981,6 +1004,7 @@ false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16742,7 +17847,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; const struct tune_params arm_9e_tune = -@@ -995,6 +1011,7 @@ +@@ -995,6 +1019,7 @@ false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16750,7 +17855,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; const struct tune_params arm_v6t2_tune = -@@ -1009,6 +1026,7 @@ +@@ -1009,6 +1034,7 @@ false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16758,7 +17863,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; /* Generic Cortex tuning. Use more specific tunings if appropriate. */ -@@ -1024,6 +1042,7 @@ +@@ -1024,6 +1050,7 @@ false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16766,7 +17871,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; const struct tune_params arm_cortex_a15_tune = -@@ -1038,6 +1057,7 @@ +@@ -1038,6 +1065,7 @@ true, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16774,7 +17879,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; /* Branches can be dual-issued on Cortex-A5, so conditional execution is -@@ -1055,6 +1075,7 @@ +@@ -1055,6 +1083,7 @@ false, /* Prefer LDRD/STRD. */ {false, false}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16782,7 +17887,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; const struct tune_params arm_cortex_a9_tune = -@@ -1069,6 +1090,7 @@ +@@ -1069,6 +1098,7 @@ false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16790,7 +17895,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than -@@ -1085,6 +1107,7 @@ +@@ -1085,6 +1115,7 @@ false, /* Prefer LDRD/STRD. */ {false, false}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16798,7 +17903,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; const struct tune_params arm_fa726te_tune = -@@ -1099,6 +1122,7 @@ +@@ -1099,6 +1130,7 @@ false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -16806,7 +17911,20 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; -@@ -2129,11 +2153,25 @@ +@@ -1842,7 +1874,12 @@ + arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0; + arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0; + arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; ++ if (arm_restrict_it == 2) ++ arm_restrict_it = arm_arch8 && TARGET_THUMB2; + ++ if (!TARGET_THUMB2) ++ arm_restrict_it = 0; ++ + /* If we are not using the default (ARM mode) section anchor offset + ranges, then set the correct ranges now. */ + if (TARGET_THUMB1) +@@ -2129,6 +2166,12 @@ global_options.x_param_values, global_options_set.x_param_values); @@ -16819,20 +17937,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Use the alternative scheduling-pressure algorithm by default. */ maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2, global_options.x_param_values, - global_options_set.x_param_values); - -+ /* Disable shrink-wrap when optimizing function for size, since it tends to -+ generate additional returns. */ -+ if (optimize_function_for_size_p (cfun) && TARGET_THUMB2) -+ flag_shrink_wrap = false; -+ /* TBD: Dwarf info for apcs frame is not handled yet. */ -+ if (TARGET_APCS_FRAME) -+ flag_shrink_wrap = false; -+ - /* Register global variables with the garbage collector. */ - arm_add_gc_roots (); - } -@@ -2382,6 +2420,10 @@ +@@ -2382,6 +2425,10 @@ if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB)) return 0; @@ -16843,26 +17948,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ offsets = arm_get_frame_offsets (); stack_adjust = offsets->outgoing_args - offsets->saved_regs; -@@ -2479,6 +2521,18 @@ - return 1; - } - -+/* Return TRUE if we should try to use a simple_return insn, i.e. perform -+ shrink-wrapping if possible. This is the case if we need to emit a -+ prologue, which we can test by looking at the offsets. */ -+bool -+use_simple_return_p (void) -+{ -+ arm_stack_offsets *offsets; -+ -+ offsets = arm_get_frame_offsets (); -+ return offsets->outgoing_args != 0; -+} -+ - /* Return TRUE if int I is a valid immediate ARM constant. */ - - int -@@ -2617,6 +2671,9 @@ +@@ -2617,6 +2664,9 @@ switch (code) { @@ -16872,44 +17958,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ case PLUS: return arm_not_operand (hi, SImode) && arm_add_operand (lo, SImode); -@@ -5335,9 +5392,8 @@ - if (cfun->machine->sibcall_blocked) - return false; - -- /* Never tailcall something for which we have no decl, or if we -- are generating code for Thumb-1. */ -- if (decl == NULL || TARGET_THUMB1) -+ /* Never tailcall something if we are generating code for Thumb-1. */ -+ if (TARGET_THUMB1) - return false; - - /* The PIC register is live on entry to VxWorks PLT entries, so we -@@ -5347,13 +5403,14 @@ - - /* Cannot tail-call to long calls, since these are out of range of - a branch instruction. */ -- if (arm_is_long_call_p (decl)) -+ if (decl && arm_is_long_call_p (decl)) - return false; - - /* If we are interworking and the function is not declared static - then we can't tail-call it unless we know that it exists in this - compilation unit (since it might be a Thumb routine). */ -- if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) -+ if (TARGET_INTERWORK && decl && TREE_PUBLIC (decl) -+ && !TREE_ASM_WRITTEN (decl)) - return false; - - func_type = arm_current_func_type (); -@@ -5385,6 +5442,7 @@ - sibling calls. */ - if (TARGET_AAPCS_BASED - && arm_abi == ARM_ABI_AAPCS -+ && decl - && DECL_WEAK (decl)) - return false; - -@@ -11803,6 +11861,134 @@ +@@ -11803,6 +11853,134 @@ return 1; } @@ -17044,7 +18093,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Select a dominance comparison mode if possible for a test of the general form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. COND_OR == DOM_CC_X_AND_Y => (X && Y) -@@ -12603,6 +12789,277 @@ +@@ -12603,6 +12781,277 @@ return true; } @@ -17322,7 +18371,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Print a symbolic form of X to the debug file, F. */ static void -@@ -14794,7 +15251,8 @@ +@@ -14794,7 +15243,8 @@ { /* Constraints should ensure this. */ gcc_assert (code0 == MEM && code1 == REG); @@ -17332,7 +18381,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ switch (GET_CODE (XEXP (operands[0], 0))) { -@@ -16387,6 +16845,148 @@ +@@ -16387,6 +16837,148 @@ return; } @@ -17481,27 +18530,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Generate and emit an insn that we will recognize as a push_multi. Unfortunately, since this insn does not reflect very well the actual semantics of the operation, we need to annotate the insn for the benefit -@@ -16529,6 +17129,19 @@ - return par; - } - -+/* Add a REG_CFA_ADJUST_CFA REG note to INSN. -+ SIZE is the offset to be adjusted. -+ DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx. */ -+static void -+arm_add_cfa_adjust_cfa_note (rtx insn, int size, rtx dest, rtx src) -+{ -+ rtx dwarf; -+ -+ RTX_FRAME_RELATED_P (insn) = 1; -+ dwarf = gen_rtx_SET (VOIDmode, dest, plus_constant (Pmode, src, size)); -+ add_reg_note (insn, REG_CFA_ADJUST_CFA, dwarf); -+} -+ - /* Generate and emit an insn pattern that we will recognize as a pop_multi. - SAVED_REGS_MASK shows which registers need to be restored. - -@@ -16586,6 +17199,17 @@ +@@ -16586,6 +17178,17 @@ if (saved_regs_mask & (1 << i)) { reg = gen_rtx_REG (SImode, i); @@ -17519,62 +18548,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ tmp = gen_rtx_SET (VOIDmode, reg, gen_frame_mem -@@ -16608,6 +17232,9 @@ - par = emit_insn (par); - - REG_NOTES (par) = dwarf; -+ if (!return_in_pc) -+ arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs, -+ stack_pointer_rtx, stack_pointer_rtx); - } - - /* Generate and emit an insn pattern that we will recognize as a pop_multi -@@ -16678,6 +17305,9 @@ - - par = emit_insn (par); - REG_NOTES (par) = dwarf; -+ -+ arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs, -+ base_reg, base_reg); - } - - /* Generate and emit a pattern that will be recognized as LDRD pattern. If even -@@ -16753,6 +17383,7 @@ - pattern can be emitted now. */ - par = emit_insn (par); - REG_NOTES (par) = dwarf; -+ RTX_FRAME_RELATED_P (par) = 1; - } - - i++; -@@ -16769,7 +17400,12 @@ - stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, 4 * i)); - RTX_FRAME_RELATED_P (tmp) = 1; -- emit_insn (tmp); -+ tmp = emit_insn (tmp); -+ if (!return_in_pc) -+ { -+ arm_add_cfa_adjust_cfa_note (tmp, UNITS_PER_WORD * i, -+ stack_pointer_rtx, stack_pointer_rtx); -+ } - - dwarf = NULL_RTX; - -@@ -16803,9 +17439,11 @@ - else - { - par = emit_insn (tmp); -+ REG_NOTES (par) = dwarf; -+ arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD, -+ stack_pointer_rtx, stack_pointer_rtx); - } - -- REG_NOTES (par) = dwarf; - } - else if ((num_regs % 2) == 1 && return_in_pc) - { -@@ -16817,6 +17455,129 @@ +@@ -16817,6 +17420,129 @@ return; } @@ -17704,51 +18678,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Calculate the size of the return value that is passed in registers. */ static unsigned arm_size_return_regs (void) -@@ -16841,11 +17602,27 @@ - || df_regs_ever_live_p (LR_REGNUM)); - } - -+/* We do not know if r3 will be available because -+ we do have an indirect tailcall happening in this -+ particular case. */ -+static bool -+is_indirect_tailcall_p (rtx call) -+{ -+ rtx pat = PATTERN (call); - -+ /* Indirect tail call. */ -+ pat = XVECEXP (pat, 0, 0); -+ if (GET_CODE (pat) == SET) -+ pat = SET_SRC (pat); -+ -+ pat = XEXP (XEXP (pat, 0), 0); -+ return REG_P (pat); -+} -+ - /* Return true if r3 is used by any of the tail call insns in the - current function. */ - static bool --any_sibcall_uses_r3 (void) -+any_sibcall_could_use_r3 (void) - { - edge_iterator ei; - edge e; -@@ -16859,7 +17636,8 @@ - if (!CALL_P (call)) - call = prev_nonnote_nondebug_insn (call); - gcc_assert (CALL_P (call) && SIBLING_CALL_P (call)); -- if (find_regno_fusage (call, USE, 3)) -+ if (find_regno_fusage (call, USE, 3) -+ || is_indirect_tailcall_p (call)) - return true; - } - return false; -@@ -17026,9 +17804,10 @@ +@@ -17026,9 +17752,10 @@ /* If it is safe to use r3, then do so. This sometimes generates better code on Thumb-2 by avoiding the need to use 32-bit push/pop instructions. */ - if (! any_sibcall_uses_r3 () -+ if (! any_sibcall_could_use_r3 () ++ if (! any_sibcall_uses_r3 () && arm_size_return_regs () <= 12 - && (offsets->saved_regs_mask & (1 << 3)) == 0) + && (offsets->saved_regs_mask & (1 << 3)) == 0 @@ -17756,7 +18691,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ { reg = 3; } -@@ -17460,6 +18239,12 @@ +@@ -17460,6 +18187,12 @@ { thumb2_emit_strd_push (live_regs_mask); } @@ -17769,7 +18704,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ else { insn = emit_multi_reg_push (live_regs_mask); -@@ -19339,6 +20124,7 @@ +@@ -18781,7 +19514,7 @@ + break; + /* Allow up to 4 conditionally executed instructions in a block. */ + n = get_attr_ce_count (insn); +- if (arm_condexec_masklen + n > 4) ++ if (arm_condexec_masklen + n > MAX_INSN_PER_IT_BLOCK) + break; + + predicate = COND_EXEC_TEST (body); +@@ -19339,6 +20072,7 @@ typedef enum { T_V8QI, T_V4HI, @@ -17777,7 +18721,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ T_V2SI, T_V2SF, T_DI, -@@ -19356,14 +20142,15 @@ +@@ -19356,14 +20090,15 @@ #define TYPE_MODE_BIT(X) (1 << (X)) #define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \ @@ -17795,7 +18739,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ #define v2si_UP T_V2SI #define v2sf_UP T_V2SF #define di_UP T_DI -@@ -19399,6 +20186,8 @@ +@@ -19399,6 +20134,8 @@ NEON_SCALARMULH, NEON_SCALARMAC, NEON_CONVERT, @@ -17804,7 +18748,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ NEON_FIXCONV, NEON_SELECT, NEON_RESULTPAIR, -@@ -19459,7 +20248,8 @@ +@@ -19459,7 +20196,8 @@ VAR9 (T, N, A, B, C, D, E, F, G, H, I), \ {#N, NEON_##T, UP (J), CF (N, J), 0} @@ -17814,7 +18758,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ instruction variant, i.e. equivalent to that which would be specified after the assembler mnemonic, which usually refers to the last vector operand. (Signed/unsigned/polynomial types are not differentiated between though, and -@@ -19469,196 +20259,7 @@ +@@ -19469,196 +20207,7 @@ static neon_builtin_datum neon_builtin_data[] = { @@ -18012,7 +18956,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ }; #undef CF -@@ -19673,9 +20274,36 @@ +@@ -19673,9 +20222,36 @@ #undef VAR9 #undef VAR10 @@ -18052,7 +18996,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ enum arm_builtins { ARM_BUILTIN_GETWCGR0, -@@ -19924,11 +20552,25 @@ +@@ -19924,11 +20500,25 @@ ARM_BUILTIN_WMERGE, @@ -18080,7 +19024,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX]; static void -@@ -19939,6 +20581,7 @@ +@@ -19939,6 +20529,7 @@ tree neon_intQI_type_node; tree neon_intHI_type_node; @@ -18088,7 +19032,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ tree neon_polyQI_type_node; tree neon_polyHI_type_node; tree neon_intSI_type_node; -@@ -19965,6 +20608,7 @@ +@@ -19965,6 +20556,7 @@ tree V8QI_type_node; tree V4HI_type_node; @@ -18096,7 +19040,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ tree V2SI_type_node; tree V2SF_type_node; tree V16QI_type_node; -@@ -20019,6 +20663,9 @@ +@@ -20019,6 +20611,9 @@ neon_float_type_node = make_node (REAL_TYPE); TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; layout_type (neon_float_type_node); @@ -18106,7 +19050,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Define typedefs which exactly correspond to the modes we are basing vector types on. If you change these names you'll need to change -@@ -20027,6 +20674,8 @@ +@@ -20027,6 +20622,8 @@ "__builtin_neon_qi"); (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, "__builtin_neon_hi"); @@ -18115,7 +19059,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, "__builtin_neon_si"); (*lang_hooks.types.register_builtin_type) (neon_float_type_node, -@@ -20068,6 +20717,8 @@ +@@ -20068,6 +20665,8 @@ build_vector_type_for_mode (neon_intQI_type_node, V8QImode); V4HI_type_node = build_vector_type_for_mode (neon_intHI_type_node, V4HImode); @@ -18124,7 +19068,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ V2SI_type_node = build_vector_type_for_mode (neon_intSI_type_node, V2SImode); V2SF_type_node = -@@ -20190,7 +20841,7 @@ +@@ -20190,7 +20789,7 @@ neon_builtin_datum *d = &neon_builtin_data[i]; const char* const modenames[] = { @@ -18133,7 +19077,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ "v16qi", "v8hi", "v4si", "v4sf", "v2di", "ti", "ei", "oi" }; -@@ -20393,8 +21044,9 @@ +@@ -20393,8 +20992,9 @@ case NEON_REINTERP: { /* We iterate over 5 doubleword types, then 5 quadword @@ -18145,7 +19089,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ switch (insn_data[d->code].operand[0].mode) { case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; -@@ -20411,7 +21063,38 @@ +@@ -20411,7 +21011,38 @@ } } break; @@ -18184,7 +19128,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ default: gcc_unreachable (); } -@@ -21408,6 +22091,8 @@ +@@ -21408,6 +22039,8 @@ case NEON_DUP: case NEON_RINT: case NEON_SPLIT: @@ -18193,7 +19137,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ case NEON_REINTERP: return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); -@@ -21605,7 +22290,7 @@ +@@ -21605,7 +22238,7 @@ rtx op1; rtx op2; rtx pat; @@ -18202,119 +19146,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ size_t i; enum machine_mode tmode; enum machine_mode mode0; -@@ -23322,7 +24007,7 @@ - all we really need to check here is if single register is to be - returned, or multiple register return. */ - void --thumb2_expand_return (void) -+thumb2_expand_return (bool simple_return) - { - int i, num_regs; - unsigned long saved_regs_mask; -@@ -23335,7 +24020,7 @@ - if (saved_regs_mask & (1 << i)) - num_regs++; - -- if (saved_regs_mask) -+ if (!simple_return && saved_regs_mask) - { - if (num_regs == 1) - { -@@ -23613,6 +24298,7 @@ - - if (frame_pointer_needed) - { -+ rtx insn; - /* Restore stack pointer if necessary. */ - if (TARGET_ARM) - { -@@ -23623,9 +24309,12 @@ - /* Force out any pending memory operations that reference stacked data - before stack de-allocation occurs. */ - emit_insn (gen_blockage ()); -- emit_insn (gen_addsi3 (stack_pointer_rtx, -- hard_frame_pointer_rtx, -- GEN_INT (amount))); -+ insn = emit_insn (gen_addsi3 (stack_pointer_rtx, -+ hard_frame_pointer_rtx, -+ GEN_INT (amount))); -+ arm_add_cfa_adjust_cfa_note (insn, amount, -+ stack_pointer_rtx, -+ hard_frame_pointer_rtx); - - /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not - deleted. */ -@@ -23635,16 +24324,25 @@ - { - /* In Thumb-2 mode, the frame pointer points to the last saved - register. */ -- amount = offsets->locals_base - offsets->saved_regs; -- if (amount) -- emit_insn (gen_addsi3 (hard_frame_pointer_rtx, -- hard_frame_pointer_rtx, -- GEN_INT (amount))); -+ amount = offsets->locals_base - offsets->saved_regs; -+ if (amount) -+ { -+ insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, -+ hard_frame_pointer_rtx, -+ GEN_INT (amount))); -+ arm_add_cfa_adjust_cfa_note (insn, amount, -+ hard_frame_pointer_rtx, -+ hard_frame_pointer_rtx); -+ } - - /* Force out any pending memory operations that reference stacked data - before stack de-allocation occurs. */ - emit_insn (gen_blockage ()); -- emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); -+ insn = emit_insn (gen_movsi (stack_pointer_rtx, -+ hard_frame_pointer_rtx)); -+ arm_add_cfa_adjust_cfa_note (insn, 0, -+ stack_pointer_rtx, -+ hard_frame_pointer_rtx); - /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not - deleted. */ - emit_insn (gen_force_register_use (stack_pointer_rtx)); -@@ -23657,12 +24355,15 @@ - amount = offsets->outgoing_args - offsets->saved_regs; - if (amount) - { -+ rtx tmp; - /* Force out any pending memory operations that reference stacked data - before stack de-allocation occurs. */ - emit_insn (gen_blockage ()); -- emit_insn (gen_addsi3 (stack_pointer_rtx, -- stack_pointer_rtx, -- GEN_INT (amount))); -+ tmp = emit_insn (gen_addsi3 (stack_pointer_rtx, -+ stack_pointer_rtx, -+ GEN_INT (amount))); -+ arm_add_cfa_adjust_cfa_note (tmp, amount, -+ stack_pointer_rtx, stack_pointer_rtx); - /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is - not deleted. */ - emit_insn (gen_force_register_use (stack_pointer_rtx)); -@@ -23715,6 +24416,8 @@ - REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, - gen_rtx_REG (V2SImode, i), - NULL_RTX); -+ arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, -+ stack_pointer_rtx, stack_pointer_rtx); - } - - if (saved_regs_mask) -@@ -23762,6 +24465,9 @@ - REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, - gen_rtx_REG (SImode, i), - NULL_RTX); -+ arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, -+ stack_pointer_rtx, -+ stack_pointer_rtx); - } - } - } -@@ -23772,6 +24478,8 @@ +@@ -23772,6 +24405,8 @@ { if (TARGET_THUMB2) thumb2_emit_ldrd_pop (saved_regs_mask); @@ -18323,45 +19155,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ else arm_emit_multi_reg_pop (saved_regs_mask); } -@@ -23784,10 +24492,34 @@ - } - - if (crtl->args.pretend_args_size) -- emit_insn (gen_addsi3 (stack_pointer_rtx, -- stack_pointer_rtx, -- GEN_INT (crtl->args.pretend_args_size))); -+ { -+ int i, j; -+ rtx dwarf = NULL_RTX; -+ rtx tmp = emit_insn (gen_addsi3 (stack_pointer_rtx, -+ stack_pointer_rtx, -+ GEN_INT (crtl->args.pretend_args_size))); - -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ -+ if (cfun->machine->uses_anonymous_args) -+ { -+ /* Restore pretend args. Refer arm_expand_prologue on how to save -+ pretend_args in stack. */ -+ int num_regs = crtl->args.pretend_args_size / 4; -+ saved_regs_mask = (0xf0 >> num_regs) & 0xf; -+ for (j = 0, i = 0; j < num_regs; i++) -+ if (saved_regs_mask & (1 << i)) -+ { -+ rtx reg = gen_rtx_REG (SImode, i); -+ dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); -+ j++; -+ } -+ REG_NOTES (tmp) = dwarf; -+ } -+ arm_add_cfa_adjust_cfa_note (tmp, crtl->args.pretend_args_size, -+ stack_pointer_rtx, stack_pointer_rtx); -+ } -+ - if (!really_return) - return; - -@@ -25040,7 +25772,7 @@ +@@ -25040,7 +25675,7 @@ { /* Neon also supports V2SImode, etc. listed in the clause below. */ if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode @@ -18370,7 +19164,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ return true; if ((TARGET_NEON || TARGET_IWMMXT) -@@ -25203,9 +25935,8 @@ +@@ -25203,9 +25838,8 @@ nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8; p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); @@ -18381,26 +19175,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ return p; } -@@ -25455,9 +26186,17 @@ - handled_one = true; - break; - -+ /* The INSN is generated in epilogue. It is set as RTX_FRAME_RELATED_P -+ to get correct dwarf information for shrink-wrap. We should not -+ emit unwind information for it because these are used either for -+ pretend arguments or notes to adjust sp and restore registers from -+ stack. */ -+ case REG_CFA_ADJUST_CFA: -+ case REG_CFA_RESTORE: -+ return; -+ - case REG_CFA_DEF_CFA: - case REG_CFA_EXPRESSION: -- case REG_CFA_ADJUST_CFA: - case REG_CFA_OFFSET: - /* ??? Only handling here what we actually emit. */ - gcc_unreachable (); -@@ -25855,6 +26594,7 @@ +@@ -25855,6 +26489,7 @@ case cortexa7: case cortexa8: case cortexa9: @@ -18408,7 +19183,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ case fa726te: case marvell_pj4: return 2; -@@ -25883,6 +26623,7 @@ +@@ -25883,6 +26518,7 @@ { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, @@ -18416,7 +19191,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, -@@ -25981,6 +26722,60 @@ +@@ -25981,6 +26617,60 @@ return !TARGET_THUMB1; } @@ -18477,7 +19252,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* The AAPCS sets the maximum alignment of a vector to 64 bits. */ static HOST_WIDE_INT arm_vector_alignment (const_tree type) -@@ -26211,40 +27006,72 @@ +@@ -26211,40 +26901,72 @@ emit_insn (gen_memory_barrier ()); } @@ -18567,7 +19342,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ emit_insn (gen (bval, rval, mem)); } -@@ -26279,6 +27106,15 @@ +@@ -26279,6 +27001,15 @@ mod_f = operands[7]; mode = GET_MODE (mem); @@ -18583,7 +19358,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ switch (mode) { case QImode: -@@ -26353,8 +27189,20 @@ +@@ -26353,8 +27084,20 @@ scratch = operands[7]; mode = GET_MODE (mem); @@ -18605,7 +19380,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ label1 = NULL_RTX; if (!is_weak) { -@@ -26363,7 +27211,7 @@ +@@ -26363,7 +27106,7 @@ } label2 = gen_label_rtx (); @@ -18614,7 +19389,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ cond = arm_gen_compare_reg (NE, rval, oldval, scratch); x = gen_rtx_NE (VOIDmode, cond, const0_rtx); -@@ -26371,7 +27219,7 @@ +@@ -26371,7 +27114,7 @@ gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x)); @@ -18623,7 +19398,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Weak or strong, we want EQ to be true for success, so that we match the flags that we got from the compare above. */ -@@ -26390,7 +27238,9 @@ +@@ -26390,7 +27133,9 @@ if (mod_f != MEMMODEL_RELAXED) emit_label (label2); @@ -18634,7 +19409,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ if (mod_f == MEMMODEL_RELAXED) emit_label (label2); -@@ -26405,8 +27255,20 @@ +@@ -26405,8 +27150,20 @@ enum machine_mode wmode = (mode == DImode ? DImode : SImode); rtx label, x; @@ -18656,7 +19431,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ label = gen_label_rtx (); emit_label (label); -@@ -26418,7 +27280,7 @@ +@@ -26418,7 +27175,7 @@ old_out = new_out; value = simplify_gen_subreg (wmode, value, mode, 0); @@ -18665,7 +19440,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ switch (code) { -@@ -26466,12 +27328,15 @@ +@@ -26466,12 +27223,15 @@ break; } @@ -18683,6 +19458,19 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ } #define MAX_VECT_LEN 16 +@@ -27411,4 +28171,12 @@ + + } + ++/* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */ ++ ++static unsigned HOST_WIDE_INT ++arm_asan_shadow_offset (void) ++{ ++ return (unsigned HOST_WIDE_INT) 1 << 29; ++} ++ + #include "gt-arm.h" --- a/src/gcc/config/arm/arm.h +++ b/src/gcc/config/arm/arm.h @@ -350,10 +350,16 @@ @@ -18722,31 +19510,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Modes valid for Neon Q registers. */ #define VALID_NEON_QREG_MODE(MODE) \ -@@ -1130,6 +1140,7 @@ - STACK_REG, - BASE_REGS, - HI_REGS, -+ CALLER_SAVE_REGS, - GENERAL_REGS, - CORE_REGS, - VFP_D0_D7_REGS, -@@ -1156,6 +1167,7 @@ - "STACK_REG", \ - "BASE_REGS", \ - "HI_REGS", \ -+ "CALLER_SAVE_REGS", \ - "GENERAL_REGS", \ - "CORE_REGS", \ - "VFP_D0_D7_REGS", \ -@@ -1181,6 +1193,7 @@ - { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ - { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ - { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ -+ { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ - { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ - { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ - { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ -@@ -1639,7 +1652,7 @@ +@@ -1639,7 +1649,7 @@ frame. */ #define EXIT_IGNORE_STACK 1 @@ -18755,6 +19519,113 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ /* Determine if the epilogue should be output as RTL. You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ +--- a/src/gcc/config/arm/arm-fixed.md ++++ b/src/gcc/config/arm/arm-fixed.md +@@ -19,12 +19,13 @@ + ;; This file contains ARM instructions that support fixed-point operations. + + (define_insn "add<mode>3" +- [(set (match_operand:FIXED 0 "s_register_operand" "=r") +- (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "r") +- (match_operand:FIXED 2 "s_register_operand" "r")))] ++ [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") ++ (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") ++ (match_operand:FIXED 2 "s_register_operand" "l,r")))] + "TARGET_32BIT" + "add%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no")]) + + (define_insn "add<mode>3" + [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") +@@ -32,7 +33,8 @@ + (match_operand:ADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "sadd<qaddsub_suf>%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "usadd<mode>3" + [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") +@@ -40,7 +42,8 @@ + (match_operand:UQADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "uqadd<qaddsub_suf>%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "ssadd<mode>3" + [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") +@@ -48,15 +51,17 @@ + (match_operand:QADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "qadd<qaddsub_suf>%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "sub<mode>3" +- [(set (match_operand:FIXED 0 "s_register_operand" "=r") +- (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "r") +- (match_operand:FIXED 2 "s_register_operand" "r")))] ++ [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") ++ (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") ++ (match_operand:FIXED 2 "s_register_operand" "l,r")))] + "TARGET_32BIT" + "sub%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no")]) + + (define_insn "sub<mode>3" + [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") +@@ -64,7 +69,8 @@ + (match_operand:ADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "ssub<qaddsub_suf>%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "ussub<mode>3" + [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") +@@ -73,7 +79,8 @@ + (match_operand:UQADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "uqsub<qaddsub_suf>%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "sssub<mode>3" + [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") +@@ -81,7 +88,8 @@ + (match_operand:QADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "qsub<qaddsub_suf>%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + ;; Fractional multiplies. + +@@ -374,6 +382,7 @@ + "TARGET_32BIT && arm_arch6" + "ssat%?\\t%0, #16, %2%S1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "insn" "sat") + (set_attr "shift" "1") + (set_attr "type" "alu_shift")]) +@@ -384,4 +393,5 @@ + "TARGET_INT_SIMD" + "usat%?\\t%0, #16, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "insn" "sat")]) --- a/src/gcc/config/arm/unspecs.md +++ b/src/gcc/config/arm/unspecs.md @@ -83,6 +83,8 @@ @@ -18777,6 +19648,25 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ]) ;; Enumerators for NEON unspecs. +--- a/src/gcc/config/arm/linux-eabi.h ++++ b/src/gcc/config/arm/linux-eabi.h +@@ -84,10 +84,14 @@ + LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ + LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) + ++#undef ASAN_CC1_SPEC ++#define ASAN_CC1_SPEC "%{fsanitize=*:-funwind-tables}" ++ + #undef CC1_SPEC + #define CC1_SPEC \ +- LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC, \ +- GNU_USER_TARGET_CC1_SPEC " " ANDROID_CC1_SPEC) ++ LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC " " ASAN_CC1_SPEC, \ ++ GNU_USER_TARGET_CC1_SPEC " " ASAN_CC1_SPEC " " \ ++ ANDROID_CC1_SPEC) + + #define CC1PLUS_SPEC \ + LINUX_OR_ANDROID_CC ("", ANDROID_CC1PLUS_SPEC) --- a/src/gcc/config/arm/arm-cores.def +++ b/src/gcc/config/arm/arm-cores.def @@ -129,9 +129,11 @@ @@ -18802,22 +19692,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (const (symbol_ref "((enum attr_tune) arm_tune)"))) --- a/src/gcc/config/arm/arm-protos.h +++ b/src/gcc/config/arm/arm-protos.h -@@ -24,12 +24,13 @@ - - extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *); - extern int use_return_insn (int, rtx); -+extern bool use_simple_return_p (void); - extern enum reg_class arm_regno_class (int); - extern void arm_load_pic_register (unsigned long); - extern int arm_volatile_func (void); - extern void arm_expand_prologue (void); - extern void arm_expand_epilogue (bool); --extern void thumb2_expand_return (void); -+extern void thumb2_expand_return (bool); - extern const char *arm_strip_name_encoding (const char *); - extern void arm_asm_output_labelref (FILE *, const char *); - extern void thumb2_asm_output_opcode (FILE *); -@@ -78,6 +79,7 @@ +@@ -78,6 +78,7 @@ extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode, rtx (*) (rtx, rtx, rtx)); extern rtx neon_make_constant (rtx); @@ -18825,7 +19700,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ extern void neon_expand_vector_init (rtx, rtx); extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); -@@ -117,7 +119,9 @@ +@@ -117,7 +118,9 @@ extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT); extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool); @@ -18835,7 +19710,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, HOST_WIDE_INT); -@@ -269,6 +273,8 @@ +@@ -269,6 +272,8 @@ bool logical_op_non_short_circuit[2]; /* Vectorizer costs. */ const struct cpu_vec_costs* vec_costs; @@ -18977,6 +19852,248 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ DONE; }) +--- a/src/gcc/config/arm/ldmstm.md ++++ b/src/gcc/config/arm/ldmstm.md +@@ -37,7 +37,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "ldm%(ia%)\t%5, {%1, %2, %3, %4}" + [(set_attr "type" "load4") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb_ldm4_ia" + [(match_parallel 0 "load_multiple_operation" +@@ -74,7 +75,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" + "ldm%(ia%)\t%5!, {%1, %2, %3, %4}" + [(set_attr "type" "load4") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb_ldm4_ia_update" + [(match_parallel 0 "load_multiple_operation" +@@ -108,7 +110,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "stm%(ia%)\t%5, {%1, %2, %3, %4}" + [(set_attr "type" "store4") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*stm4_ia_update" + [(match_parallel 0 "store_multiple_operation" +@@ -125,7 +128,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" + "stm%(ia%)\t%5!, {%1, %2, %3, %4}" + [(set_attr "type" "store4") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb_stm4_ia_update" + [(match_parallel 0 "store_multiple_operation" +@@ -302,7 +306,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "ldm%(db%)\t%5, {%1, %2, %3, %4}" + [(set_attr "type" "load4") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*ldm4_db_update" + [(match_parallel 0 "load_multiple_operation" +@@ -323,7 +328,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" + "ldm%(db%)\t%5!, {%1, %2, %3, %4}" + [(set_attr "type" "load4") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*stm4_db" + [(match_parallel 0 "store_multiple_operation" +@@ -338,7 +344,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "stm%(db%)\t%5, {%1, %2, %3, %4}" + [(set_attr "type" "store4") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*stm4_db_update" + [(match_parallel 0 "store_multiple_operation" +@@ -355,7 +362,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" + "stm%(db%)\t%5!, {%1, %2, %3, %4}" + [(set_attr "type" "store4") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_peephole2 + [(set (match_operand:SI 0 "s_register_operand" "") +@@ -477,7 +485,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "ldm%(ia%)\t%4, {%1, %2, %3}" + [(set_attr "type" "load3") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb_ldm3_ia" + [(match_parallel 0 "load_multiple_operation" +@@ -508,7 +517,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "ldm%(ia%)\t%4!, {%1, %2, %3}" + [(set_attr "type" "load3") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb_ldm3_ia_update" + [(match_parallel 0 "load_multiple_operation" +@@ -537,7 +547,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "stm%(ia%)\t%4, {%1, %2, %3}" + [(set_attr "type" "store3") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*stm3_ia_update" + [(match_parallel 0 "store_multiple_operation" +@@ -552,7 +563,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "stm%(ia%)\t%4!, {%1, %2, %3}" + [(set_attr "type" "store3") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb_stm3_ia_update" + [(match_parallel 0 "store_multiple_operation" +@@ -704,7 +716,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "ldm%(db%)\t%4, {%1, %2, %3}" + [(set_attr "type" "load3") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*ldm3_db_update" + [(match_parallel 0 "load_multiple_operation" +@@ -722,7 +735,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "ldm%(db%)\t%4!, {%1, %2, %3}" + [(set_attr "type" "load3") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*stm3_db" + [(match_parallel 0 "store_multiple_operation" +@@ -735,7 +749,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "stm%(db%)\t%4, {%1, %2, %3}" + [(set_attr "type" "store3") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*stm3_db_update" + [(match_parallel 0 "store_multiple_operation" +@@ -750,7 +765,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "stm%(db%)\t%4!, {%1, %2, %3}" + [(set_attr "type" "store3") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_peephole2 + [(set (match_operand:SI 0 "s_register_operand" "") +@@ -855,7 +871,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" + "ldm%(ia%)\t%3, {%1, %2}" + [(set_attr "type" "load2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb_ldm2_ia" + [(match_parallel 0 "load_multiple_operation" +@@ -880,7 +897,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "ldm%(ia%)\t%3!, {%1, %2}" + [(set_attr "type" "load2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb_ldm2_ia_update" + [(match_parallel 0 "load_multiple_operation" +@@ -904,7 +922,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" + "stm%(ia%)\t%3, {%1, %2}" + [(set_attr "type" "store2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*stm2_ia_update" + [(match_parallel 0 "store_multiple_operation" +@@ -917,7 +936,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "stm%(ia%)\t%3!, {%1, %2}" + [(set_attr "type" "store2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb_stm2_ia_update" + [(match_parallel 0 "store_multiple_operation" +@@ -1044,7 +1064,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" + "ldm%(db%)\t%3, {%1, %2}" + [(set_attr "type" "load2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*ldm2_db_update" + [(match_parallel 0 "load_multiple_operation" +@@ -1059,7 +1080,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "ldm%(db%)\t%3!, {%1, %2}" + [(set_attr "type" "load2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*stm2_db" + [(match_parallel 0 "store_multiple_operation" +@@ -1070,7 +1092,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" + "stm%(db%)\t%3, {%1, %2}" + [(set_attr "type" "store2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*stm2_db_update" + [(match_parallel 0 "store_multiple_operation" +@@ -1083,7 +1106,8 @@ + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "stm%(db%)\t%3!, {%1, %2}" + [(set_attr "type" "store2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_peephole2 + [(set (match_operand:SI 0 "s_register_operand" "") --- a/src/gcc/config/arm/arm_neon_builtins.def +++ b/src/gcc/config/arm/arm_neon_builtins.def @@ -0,0 +1,212 @@ @@ -19437,17 +20554,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS" "@internal Thumb only. The union of the low registers and the stack register.") -@@ -93,6 +96,9 @@ - (define_register_constraint "c" "CC_REG" - "@internal The condition code register.") - -+(define_register_constraint "Cs" "CALLER_SAVE_REGS" -+ "@internal The caller save registers. Useful for sibcalls.") -+ - (define_constraint "I" - "In ARM/Thumb-2 state a constant that can be used as an immediate value in a - Data Processing instruction. In Thumb-1 state a constant in the range -@@ -248,6 +254,12 @@ +@@ -248,6 +251,12 @@ (and (match_code "const_int") (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)"))) @@ -19460,16 +20567,6 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_constraint "Di" "@internal In ARM/Thumb-2 state a const_int or const_double where both the high -@@ -391,3 +403,9 @@ - ;; Additionally, we used to have a Q constraint in Thumb state, but - ;; this wasn't really a valid memory constraint. Again, all uses of - ;; this now seem to have been removed. -+ -+(define_constraint "Ss" -+ "@internal -+ Ss is a symbol reference." -+ (match_code "symbol_ref") -+) --- a/src/gcc/config/arm/arm-arches.def +++ b/src/gcc/config/arm/arm-arches.def @@ -53,6 +53,6 @@ @@ -19510,7 +20607,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H) --- a/src/gcc/config/arm/arm.opt +++ b/src/gcc/config/arm/arm.opt -@@ -247,3 +247,7 @@ +@@ -239,6 +239,10 @@ + Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) + Only generate absolute relocations on word sized values. + ++mrestrict-it ++Target Report Var(arm_restrict_it) Init(2) ++Generate IT blocks appropriate for ARMv8. ++ + mfix-cortex-m3-ldrd + Target Report Var(fix_cm3_ldrd) Init(2) + Avoid overlapping destination and address registers on LDRD instructions +@@ -247,3 +251,7 @@ munaligned-access Target Report Var(unaligned_access) Init(2) Enable unaligned word and halfword accesses to packed data. @@ -19855,14 +20963,6 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ;; Predicates for named expanders that overlap multiple ISAs. (define_predicate "cmpdi_operand" -@@ -617,3 +635,7 @@ - (define_predicate "mem_noofs_operand" - (and (match_code "mem") - (match_code "reg" "0"))) -+ -+(define_predicate "call_insn_operand" -+ (ior (match_code "symbol_ref") -+ (match_operand 0 "s_register_operand"))) --- a/src/gcc/config/arm/arm_neon.h +++ b/src/gcc/config/arm/arm_neon.h @@ -43,6 +43,7 @@ @@ -19896,6 +20996,36 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) vcvt_n_s32_f32 (float32x2_t __a, const int __b) { +--- a/src/gcc/config/arm/arm-ldmstm.ml ++++ b/src/gcc/config/arm/arm-ldmstm.ml +@@ -146,12 +146,15 @@ + | IA, true, true -> true + | _ -> false + ++exception InvalidAddrMode of string;; ++ + let target addrmode thumb = + match addrmode, thumb with + IA, true -> "TARGET_THUMB1" + | IA, false -> "TARGET_32BIT" + | DB, false -> "TARGET_32BIT" + | _, false -> "TARGET_ARM" ++ | _, _ -> raise (InvalidAddrMode "ERROR: Invalid Addressing mode for Thumb1.") + + let write_pattern_1 name ls addrmode nregs write_set_fn update thumb = + let astr = string_of_addrmode addrmode in +@@ -181,8 +184,10 @@ + done; + Printf.printf "}\"\n"; + Printf.printf " [(set_attr \"type\" \"%s%d\")" ls nregs; +- begin if not thumb then ++ if not thumb then begin + Printf.printf "\n (set_attr \"predicable\" \"yes\")"; ++ if addrmode == IA || addrmode == DB then ++ Printf.printf "\n (set_attr \"predicable_short_it\" \"no\")"; + end; + Printf.printf "])\n\n" + --- a/src/gcc/config/arm/cortex-a53.md +++ b/src/gcc/config/arm/cortex-a53.md @@ -0,0 +1,296 @@ @@ -20213,20 +21343,6 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ |mcpu=marvell-pj4 \ |mcpu=generic-armv7-a \ |march=armv7-m|mcpu=cortex-m3 \ ---- a/src/gcc/config/arm/iterators.md -+++ b/src/gcc/config/arm/iterators.md -@@ -496,3 +496,11 @@ - (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") - (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") - (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) -+;; Both kinds of return insn. -+(define_code_iterator returns [return simple_return]) -+(define_code_attr return_str [(return "") (simple_return "simple_")]) -+(define_code_attr return_simple_p [(return "false") (simple_return "true")]) -+(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") -+ (simple_return " && use_simple_return_p ()")]) -+(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") -+ (simple_return " && use_simple_return_p ()")]) --- a/src/gcc/config/arm/sync.md +++ b/src/gcc/config/arm/sync.md @@ -65,6 +65,42 @@ @@ -20272,9 +21388,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied ;; with a store. -@@ -327,6 +363,16 @@ +@@ -88,7 +124,8 @@ + UNSPEC_LL))] + "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN" + "ldrexd%?\t%0, %H0, %C1" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_expand "atomic_compare_and_swap<mode>" + [(match_operand:SI 0 "s_register_operand" "") ;; bool out +@@ -325,8 +362,20 @@ + VUNSPEC_LL)))] + "TARGET_HAVE_LDREXBH" "ldrex<sync_sfx>%?\t%0, %C1" - [(set_attr "predicable" "yes")]) +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) +(define_insn "arm_load_acquire_exclusive<mode>" + [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -20284,14 +21414,19 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + VUNSPEC_LAX)))] + "TARGET_HAVE_LDACQ" + "ldaex<sync_sfx>%?\\t%0, %C1" -+ [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + (define_insn "arm_load_exclusivesi" [(set (match_operand:SI 0 "s_register_operand" "=r") (unspec_volatile:SI -@@ -336,6 +382,15 @@ +@@ -334,8 +383,19 @@ + VUNSPEC_LL))] + "TARGET_HAVE_LDREX" "ldrex%?\t%0, %C1" - [(set_attr "predicable" "yes")]) +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) +(define_insn "arm_load_acquire_exclusivesi" + [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -20300,14 +21435,19 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + VUNSPEC_LAX))] + "TARGET_HAVE_LDACQ" + "ldaex%?\t%0, %C1" -+ [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + (define_insn "arm_load_exclusivedi" [(set (match_operand:DI 0 "s_register_operand" "=r") (unspec_volatile:DI -@@ -345,6 +400,15 @@ +@@ -343,8 +403,19 @@ + VUNSPEC_LL))] + "TARGET_HAVE_LDREXD" "ldrexd%?\t%0, %H0, %C1" - [(set_attr "predicable" "yes")]) +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) +(define_insn "arm_load_acquire_exclusivedi" + [(set (match_operand:DI 0 "s_register_operand" "=r") @@ -20316,15 +21456,19 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + VUNSPEC_LAX))] + "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" + "ldaexd%?\t%0, %H0, %C1" -+ [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + (define_insn "arm_store_exclusive<mode>" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(const_int 0)] VUNSPEC_SC)) -@@ -368,3 +432,31 @@ +@@ -367,4 +438,35 @@ + } return "strex<sync_sfx>%?\t%0, %2, %C1"; } - [(set_attr "predicable" "yes")]) +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + +(define_insn "arm_store_release_exclusivedi" + [(set (match_operand:SI 0 "s_register_operand" "=&r") @@ -20341,7 +21485,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); + return "stlexd%?\t%0, %2, %3, %C1"; + } -+ [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + +(define_insn "arm_store_release_exclusive<mode>" + [(set (match_operand:SI 0 "s_register_operand" "=&r") @@ -20352,7 +21497,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + VUNSPEC_SLX))] + "TARGET_HAVE_LDACQ" + "stlex<sync_sfx>%?\t%0, %2, %C1" -+ [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) --- a/src/gcc/config/arm/neon-testgen.ml +++ b/src/gcc/config/arm/neon-testgen.ml @@ -163,10 +163,12 @@ @@ -20370,7 +21516,32 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ --- a/src/gcc/config/arm/arm.md +++ b/src/gcc/config/arm/arm.md -@@ -94,7 +94,7 @@ +@@ -74,6 +74,15 @@ + ; IS_THUMB1 is set to 'yes' iff we are generating Thumb-1 code. + (define_attr "is_thumb1" "no,yes" (const (symbol_ref "thumb1_code"))) + ++; We use this attribute to disable alternatives that can produce 32-bit ++; instructions inside an IT-block in Thumb2 state. ARMv8 deprecates IT blocks ++; that contain 32-bit instructions. ++(define_attr "enabled_for_depr_it" "no,yes" (const_string "yes")) ++ ++; This attribute is used to disable a predicated alternative when we have ++; arm_restrict_it. ++(define_attr "predicable_short_it" "no,yes" (const_string "yes")) ++ + ;; Operand number of an input operand that is shifted. Zero if the + ;; given instruction does not shift one of its input operands. + (define_attr "shift" "" (const_int 0)) +@@ -84,6 +93,8 @@ + (define_attr "fpu" "none,vfp" + (const (symbol_ref "arm_fpu_attr"))) + ++(define_attr "predicated" "yes,no" (const_string "no")) ++ + ; LENGTH of an instruction (in bytes) + (define_attr "length" "" + (const_int 4)) +@@ -94,7 +105,7 @@ ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without ; arm_arch6. This attribute is used to compute attribute "enabled", ; use type "any" to enable an alternative in all cases. @@ -20379,7 +21550,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (const_string "any")) (define_attr "arch_enabled" "no,yes" -@@ -129,24 +129,16 @@ +@@ -129,24 +140,16 @@ (match_test "TARGET_32BIT && !arm_arch6")) (const_string "yes") @@ -20410,7 +21581,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (and (eq_attr "arch" "iwmmxt2") (match_test "TARGET_REALLY_IWMMXT2")) (const_string "yes")] -@@ -296,6 +288,8 @@ +@@ -179,6 +182,15 @@ + (cond [(eq_attr "insn_enabled" "no") + (const_string "no") + ++ (and (eq_attr "predicable_short_it" "no") ++ (and (eq_attr "predicated" "yes") ++ (match_test "arm_restrict_it"))) ++ (const_string "no") ++ ++ (and (eq_attr "enabled_for_depr_it" "no") ++ (match_test "arm_restrict_it")) ++ (const_string "no") ++ + (eq_attr "arch_enabled" "no") + (const_string "no") + +@@ -296,6 +308,8 @@ f_2_r,\ r_2_f,\ f_cvt,\ @@ -20419,7 +21606,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ branch,\ call,\ load_byte,\ -@@ -502,7 +496,7 @@ +@@ -502,7 +516,7 @@ (define_attr "generic_sched" "yes,no" (const (if_then_else @@ -20428,7 +21615,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (eq_attr "tune_cortexr4" "yes")) (const_string "no") (const_string "yes")))) -@@ -510,7 +504,7 @@ +@@ -510,7 +524,7 @@ (define_attr "generic_vfp" "yes,no" (const (if_then_else (and (eq_attr "fpu" "vfp") @@ -20437,7 +21624,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (eq_attr "tune_cortexr4" "no")) (const_string "yes") (const_string "no")))) -@@ -531,6 +525,7 @@ +@@ -531,6 +545,7 @@ (include "cortex-a8.md") (include "cortex-a9.md") (include "cortex-a15.md") @@ -20445,7 +21632,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (include "cortex-r4.md") (include "cortex-r4f.md") (include "cortex-m4.md") -@@ -844,7 +839,7 @@ +@@ -844,7 +859,7 @@ ;; This is the canonicalization of addsi3_compare0_for_combiner when the ;; addend is a constant. @@ -20454,7 +21641,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:SI 1 "s_register_operand" "r,r") -@@ -975,7 +970,8 @@ +@@ -975,7 +990,8 @@ "@ adc%?\\t%0, %1, %2 sbc%?\\t%0, %1, #%B2" @@ -20464,7 +21651,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ) (define_insn "*addsi3_carryin_alt2_<optab>" -@@ -987,7 +983,8 @@ +@@ -987,7 +1003,8 @@ "@ adc%?\\t%0, %1, %2 sbc%?\\t%0, %1, #%B2" @@ -20474,7 +21661,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ) (define_insn "*addsi3_carryin_shift_<optab>" -@@ -1001,6 +998,7 @@ +@@ -1001,6 +1018,7 @@ "TARGET_32BIT" "adc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") @@ -20482,7 +21669,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") (const_string "alu_shift") (const_string "alu_shift_reg")))] -@@ -1017,26 +1015,88 @@ +@@ -1017,26 +1035,88 @@ [(set_attr "conds" "set")] ) @@ -20585,7 +21772,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ) ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. -@@ -1087,13 +1147,27 @@ +@@ -1087,13 +1167,27 @@ " ) @@ -20615,7 +21802,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob") (set_attr "length" "8")] ) -@@ -1108,55 +1182,113 @@ +@@ -1108,55 +1202,113 @@ [(set_attr "length" "4")] ) @@ -20738,7 +21925,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set (match_operand:DI 0 "s_register_operand" "=r") (minus:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")) -@@ -1164,7 +1296,17 @@ +@@ -1164,7 +1316,17 @@ (match_operand:SI 2 "s_register_operand" "r")))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" @@ -20757,7 +21944,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob") (set_attr "length" "8")] ) -@@ -1254,7 +1396,7 @@ +@@ -1254,7 +1416,7 @@ (set_attr "type" "simple_alu_imm,*,*")] ) @@ -20766,7 +21953,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,r,I") (match_operand:SI 2 "arm_rhs_operand" "I,r,r"))) -@@ -1269,29 +1411,6 @@ +@@ -1269,29 +1431,6 @@ (set_attr "type" "simple_alu_imm,*,*")] ) @@ -20796,7 +21983,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_expand "subsf3" [(set (match_operand:SF 0 "s_register_operand" "") (minus:SF (match_operand:SF 1 "s_register_operand" "") -@@ -2024,13 +2143,58 @@ +@@ -2024,13 +2163,49 @@ "" ) @@ -20808,29 +21995,28 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ - "#" - [(set_attr "length" "8")] +(define_insn_and_split "*anddi3_insn" -+ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r,&r,w,w ,?&r,?&r,?w,?w") -+ (and:DI (match_operand:DI 1 "s_register_operand" "%0 ,r ,0,r ,w,0 ,0 ,r ,w ,0") -+ (match_operand:DI 2 "arm_anddi_operand_neon" "r ,r ,De,De,w,DL,r ,r ,w ,DL")))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,w ,&r,&r,&r,&r,?w,?w") ++ (and:DI (match_operand:DI 1 "s_register_operand" "%w,0 ,0 ,r ,0 ,r ,w ,0") ++ (match_operand:DI 2 "arm_anddi_operand_neon" "w ,DL,r ,r ,De,De,w ,DL")))] + "TARGET_32BIT && !TARGET_IWMMXT" +{ + switch (which_alternative) + { -+ case 0: -+ case 1: ++ case 0: /* fall through */ ++ case 6: return "vand\t%P0, %P1, %P2"; ++ case 1: /* fall through */ ++ case 7: return neon_output_logic_immediate ("vand", &operands[2], ++ DImode, 1, VALID_NEON_QREG_MODE (DImode)); + case 2: -+ case 3: /* fall through */ -+ return "#"; -+ case 4: /* fall through */ -+ case 8: return "vand\t%P0, %P1, %P2"; ++ case 3: ++ case 4: + case 5: /* fall through */ -+ case 9: return neon_output_logic_immediate ("vand", &operands[2], -+ DImode, 1, VALID_NEON_QREG_MODE (DImode)); -+ case 6: return "#"; -+ case 7: return "#"; ++ return "#"; + default: gcc_unreachable (); + } +} -+ "TARGET_32BIT && !TARGET_IWMMXT" ++ "TARGET_32BIT && !TARGET_IWMMXT && reload_completed ++ && !(IS_VFP_REGNUM (REGNO (operands[0])))" + [(set (match_dup 3) (match_dup 4)) + (set (match_dup 5) (match_dup 6))] + " @@ -20846,23 +22032,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + gen_highpart_mode (SImode, DImode, operands[2])); + + }" -+ [(set_attr "neon_type" "*,*,*,*,neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1") -+ (set_attr "arch" "*,*,*,*,neon_for_64bits,neon_for_64bits,*,*, ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1") ++ (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*, + avoid_neon_for_64bits,avoid_neon_for_64bits") -+ (set_attr "length" "8,8,8,8,*,*,8,8,*,*") -+ (set (attr "insn_enabled") (if_then_else -+ (lt (symbol_ref "which_alternative") -+ (const_int 4)) -+ (if_then_else (match_test "!TARGET_NEON") -+ (const_string "yes") -+ (const_string "no")) -+ (if_then_else (match_test "TARGET_NEON") -+ (const_string "yes") -+ (const_string "no"))))] ++ (set_attr "length" "*,*,8,8,8,8,*,*") ++ ] ) (define_insn_and_split "*anddi_zesidi_di" -@@ -3096,13 +3260,17 @@ +@@ -3096,13 +3271,17 @@ "" ) @@ -20882,7 +22060,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "length" "8") (set_attr "ce_count" "2") (set_attr "predicable" "yes")] -@@ -3253,15 +3421,23 @@ +@@ -3253,15 +3432,23 @@ [(set_attr "predicable" "yes")] ) @@ -20910,7 +22088,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob") (set_attr "length" "8,12")] ) -@@ -3293,15 +3469,23 @@ +@@ -3293,15 +3480,23 @@ [(set_attr "predicable" "yes")] ) @@ -20938,7 +22116,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob") (set_attr "length" "8,12")] ) -@@ -3316,16 +3500,24 @@ +@@ -3316,16 +3511,24 @@ "" ) @@ -20968,7 +22146,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob") (set_attr "length" "8,8,12")] ) -@@ -3340,16 +3532,24 @@ +@@ -3340,16 +3543,24 @@ "" ) @@ -20998,7 +22176,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob") (set_attr "length" "8,8,12")] ) -@@ -3360,7 +3560,7 @@ +@@ -3360,7 +3571,7 @@ [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "s_register_operand" "r")])) (clobber (reg:CC CC_REGNUM))] @@ -21007,7 +22185,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ "* operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode, operands[1], operands[2]); -@@ -3423,6 +3623,50 @@ +@@ -3423,6 +3634,50 @@ (const_int 12)))] ) @@ -21058,7 +22236,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_code_iterator SAT [smin smax]) (define_code_iterator SATrev [smin smax]) (define_code_attr SATlo [(smin "1") (smax "2")]) -@@ -3533,13 +3777,26 @@ +@@ -3533,13 +3788,26 @@ " ) @@ -21087,7 +22265,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob") (set_attr "length" "8")] ) -@@ -3615,18 +3872,43 @@ +@@ -3615,18 +3883,43 @@ " ) @@ -21134,7 +22312,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_expand "ashrsi3" [(set (match_operand:SI 0 "s_register_operand" "") (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") -@@ -3695,15 +3977,28 @@ +@@ -3695,15 +3988,28 @@ " ) @@ -21166,7 +22344,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (set_attr "length" "8")] ) -@@ -3791,6 +4086,23 @@ +@@ -3791,6 +4097,23 @@ (const_string "alu_shift_reg")))] ) @@ -21190,7 +22368,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "*shiftsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (match_operator:SI 3 "shift_operator" -@@ -4090,6 +4402,64 @@ +@@ -4090,6 +4413,64 @@ (set_attr "predicable" "yes") (set_attr "type" "store1")]) @@ -21255,7 +22433,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (define_insn "*extv_reg" [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") -@@ -4154,12 +4524,24 @@ +@@ -4154,12 +4535,24 @@ ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). ;; The first alternative allows the common case of a *full* overlap. @@ -21282,7 +22460,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob") (set_attr "length" "8")] ) -@@ -4209,6 +4591,73 @@ +@@ -4209,6 +4602,73 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "") @@ -21356,7 +22534,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ;; abssi2 doesn't really clobber the condition codes if a different register ;; is being set. To keep things simple, assume during rtl manipulations that ;; it does, but tell the final scan operator the truth. Similarly for -@@ -4227,14 +4676,67 @@ +@@ -4227,14 +4687,67 @@ operands[2] = gen_rtx_REG (CCmode, CC_REGNUM); ") @@ -21428,7 +22606,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob,*") (set_attr "shift" "1") (set_attr "predicable" "no, yes") -@@ -4255,14 +4757,56 @@ +@@ -4255,14 +4768,56 @@ [(set_attr "length" "6")] ) @@ -21489,7 +22667,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob,*") (set_attr "shift" "1") (set_attr "predicable" "no, yes") -@@ -4330,7 +4874,7 @@ +@@ -4330,7 +4885,7 @@ [(set_attr "length" "*,8,8,*") (set_attr "predicable" "no,yes,yes,no") (set_attr "neon_type" "neon_int_1,*,*,neon_int_1") @@ -21498,7 +22676,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ) (define_expand "one_cmplsi2" -@@ -4498,7 +5042,7 @@ +@@ -4498,7 +5053,7 @@ "TARGET_32BIT <qhs_zextenddi_cond>" "#" [(set_attr "length" "8,4,8,8") @@ -21507,7 +22685,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (set_attr "ce_count" "2") (set_attr "predicable" "yes")] ) -@@ -4513,7 +5057,7 @@ +@@ -4513,7 +5068,7 @@ (set_attr "ce_count" "2") (set_attr "shift" "1") (set_attr "predicable" "yes") @@ -21516,7 +22694,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ ) ;; Splits for all extensions to DImode -@@ -5313,8 +5857,8 @@ +@@ -5313,8 +5868,8 @@ ) (define_insn "*arm_movdi" @@ -21527,7 +22705,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_VFP) && !TARGET_IWMMXT -@@ -6738,8 +7282,8 @@ +@@ -6738,8 +7293,8 @@ ) (define_insn "*movdf_soft_insn" @@ -21538,7 +22716,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ "TARGET_32BIT && TARGET_SOFT_FLOAT && ( register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" -@@ -6869,10 +7413,18 @@ +@@ -6869,10 +7424,18 @@ (match_operand:BLK 1 "general_operand" "") (match_operand:SI 2 "const_int_operand" "") (match_operand:SI 3 "const_int_operand" "")] @@ -21558,7 +22736,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ if (arm_gen_movmemqi (operands)) DONE; FAIL; -@@ -7617,23 +8169,64 @@ +@@ -7617,23 +8180,64 @@ ;; if-conversion can not reduce to a conditional compare, so we do ;; that directly. @@ -21627,7 +22805,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "set") (set_attr "length" "8")] ) -@@ -7758,36 +8351,56 @@ +@@ -7758,36 +8362,56 @@ operands[3] = const0_rtx;" ) @@ -21693,7 +22871,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ (set_attr "length" "8")] ) -@@ -8110,7 +8723,40 @@ +@@ -8110,7 +8734,40 @@ }" ) @@ -21735,7 +22913,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r") (if_then_else:SI (match_operator 3 "arm_comparison_operator" -@@ -8123,10 +8769,45 @@ +@@ -8123,10 +8780,45 @@ mvn%D3\\t%0, #%B2 mov%d3\\t%0, %1 mvn%d3\\t%0, #%B1 @@ -21785,239 +22963,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "length" "4,4,4,4,8,8,8,8") (set_attr "conds" "use") (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn") -@@ -8255,7 +8936,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && arm_arch5" -+ "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" - "blx%?\\t%0" - [(set_attr "type" "call")] - ) -@@ -8265,7 +8946,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && !arm_arch5" -+ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" - "* - return output_call (operands); - " -@@ -8284,7 +8965,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && !arm_arch5" -+ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" - "* - return output_call_mem (operands); - " -@@ -8297,7 +8978,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_THUMB1 && arm_arch5" -+ "TARGET_THUMB1 && arm_arch5 && !SIBLING_CALL_P (insn)" - "blx\\t%0" - [(set_attr "length" "2") - (set_attr "type" "call")] -@@ -8308,7 +8989,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_THUMB1 && !arm_arch5" -+ "TARGET_THUMB1 && !arm_arch5 && !SIBLING_CALL_P (insn)" - "* - { - if (!TARGET_CALLER_INTERWORKING) -@@ -8367,7 +9048,7 @@ - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && arm_arch5" -+ "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" - "blx%?\\t%1" - [(set_attr "type" "call")] - ) -@@ -8378,7 +9059,7 @@ - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && !arm_arch5" -+ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" - "* - return output_call (&operands[1]); - " -@@ -8394,7 +9075,8 @@ - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))" -+ "TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) -+ && !SIBLING_CALL_P (insn)" - "* - return output_call_mem (&operands[1]); - " -@@ -8444,6 +9126,7 @@ - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] - "TARGET_32BIT -+ && !SIBLING_CALL_P (insn) - && (GET_CODE (operands[0]) == SYMBOL_REF) - && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" - "* -@@ -8460,6 +9143,7 @@ - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM))] - "TARGET_32BIT -+ && !SIBLING_CALL_P (insn) - && (GET_CODE (operands[1]) == SYMBOL_REF) - && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" - "* -@@ -8505,6 +9189,10 @@ - "TARGET_32BIT" - " - { -+ if (!REG_P (XEXP (operands[0], 0)) -+ && (GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)) -+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); -+ - if (operands[2] == NULL_RTX) - operands[2] = const0_rtx; - }" -@@ -8519,47 +9207,67 @@ - "TARGET_32BIT" - " - { -+ if (!REG_P (XEXP (operands[1], 0)) && -+ (GET_CODE (XEXP (operands[1],0)) != SYMBOL_REF)) -+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); -+ - if (operands[3] == NULL_RTX) - operands[3] = const0_rtx; - }" - ) - - (define_insn "*sibcall_insn" -- [(call (mem:SI (match_operand:SI 0 "" "X")) -+ [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "Cs,Ss")) - (match_operand 1 "" "")) - (return) - (use (match_operand 2 "" ""))] -- "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF" -+ "TARGET_32BIT && SIBLING_CALL_P (insn)" - "* -- return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; -+ if (which_alternative == 1) -+ return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; -+ else -+ { -+ if (arm_arch5 || arm_arch4t) -+ return \" bx\\t%0\\t%@ indirect register sibling call\"; -+ else -+ return \"mov%?\\t%|pc, %0\\t%@ indirect register sibling call\"; -+ } - " - [(set_attr "type" "call")] - ) - - (define_insn "*sibcall_value_insn" -- [(set (match_operand 0 "" "") -- (call (mem:SI (match_operand:SI 1 "" "X")) -+ [(set (match_operand 0 "s_register_operand" "") -+ (call (mem:SI (match_operand:SI 1 "call_insn_operand" "Cs,Ss")) - (match_operand 2 "" ""))) - (return) - (use (match_operand 3 "" ""))] -- "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF" -+ "TARGET_32BIT && SIBLING_CALL_P (insn)" - "* -- return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; -+ if (which_alternative == 1) -+ return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; -+ else -+ { -+ if (arm_arch5 || arm_arch4t) -+ return \"bx\\t%1\"; -+ else -+ return \"mov%?\\t%|pc, %1\\t@ indirect sibling call \"; -+ } - " - [(set_attr "type" "call")] - ) - --(define_expand "return" -- [(return)] -+(define_expand "<return_str>return" -+ [(returns)] - "(TARGET_ARM || (TARGET_THUMB2 - && ARM_FUNC_TYPE (arm_current_func_type ()) == ARM_FT_NORMAL - && !IS_STACKALIGN (arm_current_func_type ()))) -- && USE_RETURN_INSN (FALSE)" -+ <return_cond_false>" - " - { - if (TARGET_THUMB2) - { -- thumb2_expand_return (); -+ thumb2_expand_return (<return_simple_p>); - DONE; - } - } -@@ -8584,13 +9292,13 @@ - (set_attr "predicable" "yes")] - ) - --(define_insn "*cond_return" -+(define_insn "*cond_<return_str>return" - [(set (pc) - (if_then_else (match_operator 0 "arm_comparison_operator" - [(match_operand 1 "cc_register" "") (const_int 0)]) -- (return) -+ (returns) - (pc)))] -- "TARGET_ARM && USE_RETURN_INSN (TRUE)" -+ "TARGET_ARM <return_cond_true>" - "* - { - if (arm_ccfsm_state == 2) -@@ -8598,20 +9306,21 @@ - arm_ccfsm_state += 2; - return \"\"; - } -- return output_return_instruction (operands[0], true, false, false); -+ return output_return_instruction (operands[0], true, false, -+ <return_simple_p>); - }" - [(set_attr "conds" "use") - (set_attr "length" "12") - (set_attr "type" "load1")] - ) - --(define_insn "*cond_return_inverted" -+(define_insn "*cond_<return_str>return_inverted" - [(set (pc) - (if_then_else (match_operator 0 "arm_comparison_operator" - [(match_operand 1 "cc_register" "") (const_int 0)]) - (pc) -- (return)))] -- "TARGET_ARM && USE_RETURN_INSN (TRUE)" -+ (returns)))] -+ "TARGET_ARM <return_cond_true>" - "* - { - if (arm_ccfsm_state == 2) -@@ -8619,7 +9328,8 @@ - arm_ccfsm_state += 2; - return \"\"; - } -- return output_return_instruction (operands[0], true, true, false); -+ return output_return_instruction (operands[0], true, true, -+ <return_simple_p>); - }" - [(set_attr "conds" "use") - (set_attr "length" "12") -@@ -9095,27 +9805,64 @@ +@@ -9095,27 +9787,64 @@ (set_attr "type" "alu_shift,alu_shift_reg")]) @@ -22092,7 +23038,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "use") (set_attr "length" "4,8")] ) -@@ -9822,24 +10569,75 @@ +@@ -9822,24 +10551,75 @@ "") ;; ??? The conditional patterns above need checking for Thumb-2 usefulness @@ -22178,7 +23124,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ [(set_attr "conds" "clob") (set_attr "length" "12")] ) -@@ -11626,6 +12424,9 @@ +@@ -11280,6 +12060,7 @@ + (const_int 0)])] + "TARGET_32BIT" + "" ++[(set_attr "predicated" "yes")] + ) + + (define_insn "force_register_use" +@@ -11626,6 +12407,9 @@ (set_attr "predicable" "yes")]) @@ -22247,7 +23201,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ "__builtin_neon_poly16", "poly", 16, 4; --- a/src/libobjc/ChangeLog.linaro +++ b/src/libobjc/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -22257,7 +23215,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgfortran/ChangeLog.linaro +++ b/src/libgfortran/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -22267,7 +23229,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libada/ChangeLog.linaro +++ b/src/libada/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -22277,7 +23243,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libffi/ChangeLog.linaro +++ b/src/libffi/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -22287,7 +23257,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libssp/ChangeLog.linaro +++ b/src/libssp/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -22297,7 +23271,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libcpp/ChangeLog.linaro +++ b/src/libcpp/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -22307,7 +23285,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libcpp/po/ChangeLog.linaro +++ b/src/libcpp/po/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. @@ -22317,7 +23299,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@199609 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/fixincludes/ChangeLog.linaro +++ b/src/fixincludes/ChangeLog.linaro -@@ -0,0 +1,7 @@ +@@ -0,0 +1,11 @@ ++2013-06-11 Rob Savoye <rob.savoye@linaro.org> ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ +2013-05-14 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + GCC Linaro 4.8-2013.05 released. |