diff options
| -rw-r--r-- | debian/changelog | 2 | ||||
| -rw-r--r-- | debian/patches/gcc-base-version.diff | 2 | ||||
| -rw-r--r-- | debian/patches/gcc-linaro.diff | 445 | ||||
| -rw-r--r-- | debian/patches/gcc-ppc64el.diff | 3135 | ||||
| -rw-r--r-- | debian/patches/svn-updates.diff | 323 |
5 files changed, 2542 insertions, 1365 deletions
diff --git a/debian/changelog b/debian/changelog index 6ccbeab..0579c4b 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,6 +1,6 @@ gcc-4.8 (4.8.2-13) UNRELEASED; urgency=medium - * Update to SVN 20140110 (r206513) from the gcc-4_8-branch. + * Update to SVN 20140112 (r206564) from the gcc-4_8-branch. - Fix miscompilation due to wrong RTL-optimization (see PR rtl-optimization/59137). Closes: #716635. diff --git a/debian/patches/gcc-base-version.diff b/debian/patches/gcc-base-version.diff index f6f2fb1..97836b8 100644 --- a/debian/patches/gcc-base-version.diff +++ b/debian/patches/gcc-base-version.diff @@ -5,7 +5,7 @@ Index: b/src/gcc/BASE-VER --- a/src/gcc/BASE-VER +++ b/src/gcc/BASE-VER @@ -1 +1 @@ --4.8.3 +-4.8.2 +4.8 Index: b/src/gcc/FULL-VER =================================================================== diff --git a/debian/patches/gcc-linaro.diff b/debian/patches/gcc-linaro.diff index 23d3ae3..06e40bb 100644 --- a/debian/patches/gcc-linaro.diff +++ b/debian/patches/gcc-linaro.diff @@ -1,12 +1,16 @@ # DP: Changes for the Linaro 4.8-2013.12 release. LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ - svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@205893 \ + svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@206341 \ | filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/ --- a/src/libitm/ChangeLog.linaro +++ b/src/libitm/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -44,7 +48,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgomp/ChangeLog.linaro +++ b/src/libgomp/ChangeLog.linaro -@@ -0,0 +1,43 @@ +@@ -0,0 +1,47 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -98,7 +106,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ use omp_lib --- a/src/libquadmath/ChangeLog.linaro +++ b/src/libquadmath/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -149,7 +161,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ current_++; --- a/src/libsanitizer/ChangeLog.linaro +++ b/src/libsanitizer/ChangeLog.linaro -@@ -0,0 +1,50 @@ +@@ -0,0 +1,54 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -213,7 +229,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ ;; --- a/src/zlib/ChangeLog.linaro +++ b/src/zlib/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -251,7 +271,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libstdc++-v3/ChangeLog.linaro +++ b/src/libstdc++-v3/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -300,7 +324,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ arm*-*-*) --- a/src/intl/ChangeLog.linaro +++ b/src/intl/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -338,7 +366,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/ChangeLog.linaro +++ b/src/ChangeLog.linaro -@@ -0,0 +1,53 @@ +@@ -0,0 +1,57 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-12-06 Michael Collison <michael.collison@linaro.org> + + Backport from trunk r197997 @@ -394,7 +426,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libmudflap/ChangeLog.linaro +++ b/src/libmudflap/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -432,7 +468,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/boehm-gc/ChangeLog.linaro +++ b/src/boehm-gc/ChangeLog.linaro -@@ -0,0 +1,48 @@ +@@ -0,0 +1,52 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -551,7 +591,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ # define MACH_TYPE "ARM32" --- a/src/include/ChangeLog.linaro +++ b/src/include/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -589,7 +633,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libiberty/ChangeLog.linaro +++ b/src/libiberty/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -627,7 +675,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/lto-plugin/ChangeLog.linaro +++ b/src/lto-plugin/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -665,7 +717,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/regression/ChangeLog.linaro +++ b/src/contrib/regression/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -715,7 +771,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ arm-linux-androideabi arm-uclinux_eabi arm-eabi \ --- a/src/contrib/ChangeLog.linaro +++ b/src/contrib/ChangeLog.linaro -@@ -0,0 +1,42 @@ +@@ -0,0 +1,46 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -760,7 +820,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/reghunt/ChangeLog.linaro +++ b/src/contrib/reghunt/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -798,7 +862,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libatomic/ChangeLog.linaro +++ b/src/libatomic/ChangeLog.linaro -@@ -0,0 +1,43 @@ +@@ -0,0 +1,47 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-12-06 Michael Collison <michael.collison@linaro.org> + + Backport from trunk r203774 @@ -858,7 +926,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ config_path="${config_path} linux/arm posix" --- a/src/config/ChangeLog.linaro +++ b/src/config/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -896,7 +968,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libbacktrace/ChangeLog.linaro +++ b/src/libbacktrace/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -934,7 +1010,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/libltdl/ChangeLog.linaro +++ b/src/libjava/libltdl/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -997,69 +1077,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ arm*-linux* ) slow_pthread_self=no can_unwind_signal=no ---- a/src/libjava/sysdep/aarch64/locks.h -+++ b/src/libjava/sysdep/aarch64/locks.h -@@ -0,0 +1,57 @@ -+// locks.h - Thread synchronization primitives. AArch64 implementation. -+ -+#ifndef __SYSDEP_LOCKS_H__ -+#define __SYSDEP_LOCKS_H__ -+ -+typedef size_t obj_addr_t; /* Integer type big enough for object */ -+ /* address. */ -+ -+// Atomically replace *addr by new_val if it was initially equal to old. -+// Return true if the comparison succeeded. -+// Assumed to have acquire semantics, i.e. later memory operations -+// cannot execute before the compare_and_swap finishes. -+inline static bool -+compare_and_swap(volatile obj_addr_t *addr, -+ obj_addr_t old, -+ obj_addr_t new_val) -+{ -+ return __sync_bool_compare_and_swap(addr, old, new_val); -+} -+ -+// Set *addr to new_val with release semantics, i.e. making sure -+// that prior loads and stores complete before this -+// assignment. -+inline static void -+release_set(volatile obj_addr_t *addr, obj_addr_t new_val) -+{ -+ __sync_synchronize(); -+ *addr = new_val; -+} -+ -+// Compare_and_swap with release semantics instead of acquire semantics. -+// On many architecture, the operation makes both guarantees, so the -+// implementation can be the same. -+inline static bool -+compare_and_swap_release(volatile obj_addr_t *addr, -+ obj_addr_t old, -+ obj_addr_t new_val) -+{ -+ return __sync_bool_compare_and_swap(addr, old, new_val); -+} -+ -+// Ensure that subsequent instructions do not execute on stale -+// data that was loaded from memory before the barrier. -+inline static void -+read_barrier() -+{ -+ __sync_synchronize(); -+} -+ -+// Ensure that prior stores to memory are completed with respect to other -+// processors. -+inline static void -+write_barrier() -+{ -+ __sync_synchronize(); -+} -+#endif --- a/src/libjava/ChangeLog.linaro +++ b/src/libjava/ChangeLog.linaro -@@ -0,0 +1,43 @@ +@@ -0,0 +1,47 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-12-06 Michael Collison <michael.collison@linaro.org> + + Backport from trunk r197997 @@ -1105,7 +1129,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/classpath/ChangeLog.linaro +++ b/src/libjava/classpath/ChangeLog.linaro -@@ -0,0 +1,42 @@ +@@ -0,0 +1,46 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-12-06 Michael Collison <michael.collison@linaro.org> + + Backport from trunk r197997 @@ -1165,9 +1193,73 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ #ifdef __alpha__ #define __IEEE_LITTLE_ENDIAN #endif +--- a/src/libjava/sysdep/aarch64/locks.h ++++ b/src/libjava/sysdep/aarch64/locks.h +@@ -0,0 +1,57 @@ ++// locks.h - Thread synchronization primitives. AArch64 implementation. ++ ++#ifndef __SYSDEP_LOCKS_H__ ++#define __SYSDEP_LOCKS_H__ ++ ++typedef size_t obj_addr_t; /* Integer type big enough for object */ ++ /* address. */ ++ ++// Atomically replace *addr by new_val if it was initially equal to old. ++// Return true if the comparison succeeded. ++// Assumed to have acquire semantics, i.e. later memory operations ++// cannot execute before the compare_and_swap finishes. ++inline static bool ++compare_and_swap(volatile obj_addr_t *addr, ++ obj_addr_t old, ++ obj_addr_t new_val) ++{ ++ return __sync_bool_compare_and_swap(addr, old, new_val); ++} ++ ++// Set *addr to new_val with release semantics, i.e. making sure ++// that prior loads and stores complete before this ++// assignment. ++inline static void ++release_set(volatile obj_addr_t *addr, obj_addr_t new_val) ++{ ++ __sync_synchronize(); ++ *addr = new_val; ++} ++ ++// Compare_and_swap with release semantics instead of acquire semantics. ++// On many architecture, the operation makes both guarantees, so the ++// implementation can be the same. ++inline static bool ++compare_and_swap_release(volatile obj_addr_t *addr, ++ obj_addr_t old, ++ obj_addr_t new_val) ++{ ++ return __sync_bool_compare_and_swap(addr, old, new_val); ++} ++ ++// Ensure that subsequent instructions do not execute on stale ++// data that was loaded from memory before the barrier. ++inline static void ++read_barrier() ++{ ++ __sync_synchronize(); ++} ++ ++// Ensure that prior stores to memory are completed with respect to other ++// processors. ++inline static void ++write_barrier() ++{ ++ __sync_synchronize(); ++} ++#endif --- a/src/gnattools/ChangeLog.linaro +++ b/src/gnattools/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -1205,7 +1297,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/maintainer-scripts/ChangeLog.linaro +++ b/src/maintainer-scripts/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -1254,7 +1350,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ arm*-*-*) --- a/src/libgcc/ChangeLog.linaro +++ b/src/libgcc/ChangeLog.linaro -@@ -0,0 +1,45 @@ +@@ -0,0 +1,49 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -1315,7 +1415,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ typedef int TItype __attribute__ ((mode (TI))); --- a/src/libgcc/config/libbid/ChangeLog.linaro +++ b/src/libgcc/config/libbid/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -1353,7 +1457,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libdecnumber/ChangeLog.linaro +++ b/src/libdecnumber/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -1392,7 +1500,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ --- a/src/gcc/LINARO-VERSION +++ b/src/gcc/LINARO-VERSION @@ -0,0 +1 @@ -+4.8-2013.11-1~dev ++4.8-2013.12 --- a/src/gcc/hooks.c +++ b/src/gcc/hooks.c @@ -147,6 +147,14 @@ @@ -1422,7 +1530,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ HOST_WIDE_INT, --- a/src/gcc/c-family/ChangeLog.linaro +++ b/src/gcc/c-family/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -1460,7 +1572,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/java/ChangeLog.linaro +++ b/src/gcc/java/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -1498,7 +1614,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/c/ChangeLog.linaro +++ b/src/gcc/c/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -1575,6 +1695,39 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ if (GET_CODE (pat) == SET && set_noop_p (pat)) return 1; +--- a/src/gcc/configure ++++ b/src/gcc/configure +@@ -1658,7 +1658,8 @@ + use sysroot as the system root during the build + --with-sysroot[=DIR] search for usr/lib, usr/include, et al, within DIR + --with-specs=SPECS add SPECS to driver command-line processing +- --with-pkgversion=PKG Use PKG in the version string in place of "GCC" ++ --with-pkgversion=PKG Use PKG in the version string in place of "Linaro ++ GCC `cat $srcdir/LINARO-VERSION`" + --with-bugurl=URL Direct users to URL to report a bug + --with-multilib-list select multilibs (SH and x86-64 only) + --with-gnu-ld assume the C compiler uses GNU ld default=no +@@ -7327,7 +7328,7 @@ + *) PKGVERSION="($withval) " ;; + esac + else +- PKGVERSION="(GCC) " ++ PKGVERSION="(Linaro GCC `cat $srcdir/LINARO-VERSION`) " + + fi + +@@ -25950,8 +25951,9 @@ + # ??? Once 2.11 is released, probably need to add first known working + # version to the per-target configury. + case "$cpu_type" in +- alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze | mips \ +- | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 | xtensa) ++ aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \ ++ | mips | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 \ ++ | xtensa) + insn="nop" + ;; + ia64 | s390) --- a/src/gcc/gensupport.c +++ b/src/gcc/gensupport.c @@ -1717,6 +1717,21 @@ @@ -1620,7 +1773,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ return 0; --- a/src/gcc/objc/ChangeLog.linaro +++ b/src/gcc/objc/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -1658,7 +1815,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/ChangeLog.linaro +++ b/src/gcc/ChangeLog.linaro -@@ -0,0 +1,2708 @@ +@@ -0,0 +1,2712 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-12-06 Christophe Lyon <christophe.lyon@linaro.org> + + Backport from trunk r204737. @@ -11121,7 +11282,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ proc check_effective_target_vxworks_kernel { } { --- a/src/gcc/testsuite/ChangeLog.linaro +++ b/src/gcc/testsuite/ChangeLog.linaro -@@ -0,0 +1,746 @@ +@@ -0,0 +1,750 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-12-06 Michael Collison <michael.collison@linaro.org> + + Backport from trunk r202872. @@ -12196,7 +12361,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*null-deref-1.c:15|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ --- a/src/gcc/objcp/ChangeLog.linaro +++ b/src/gcc/objcp/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -12234,7 +12403,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/cp/ChangeLog.linaro +++ b/src/gcc/cp/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -12333,7 +12506,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will --- a/src/gcc/go/ChangeLog.linaro +++ b/src/gcc/go/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -12371,7 +12548,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/ada/ChangeLog.linaro +++ b/src/gcc/ada/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -12420,7 +12601,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ --- a/src/gcc/fortran/ChangeLog.linaro +++ b/src/gcc/fortran/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -12793,7 +12978,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ return changed; --- a/src/gcc/lto/ChangeLog.linaro +++ b/src/gcc/lto/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -12831,7 +13020,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/po/ChangeLog.linaro +++ b/src/gcc/po/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -39674,7 +39867,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ #define STARTFILE_SPEC \ --- a/src/libobjc/ChangeLog.linaro +++ b/src/libobjc/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -39712,7 +39909,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgfortran/ChangeLog.linaro +++ b/src/libgfortran/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -39750,7 +39951,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libada/ChangeLog.linaro +++ b/src/libada/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -39788,7 +39993,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libffi/ChangeLog.linaro +++ b/src/libffi/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -39826,7 +40035,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libssp/ChangeLog.linaro +++ b/src/libssp/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -39890,7 +40103,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ hppa*64*-*-* | \ --- a/src/libcpp/ChangeLog.linaro +++ b/src/libcpp/ChangeLog.linaro -@@ -0,0 +1,43 @@ +@@ -0,0 +1,47 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -39936,7 +40153,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/libcpp/po/ChangeLog.linaro +++ b/src/libcpp/po/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. @@ -39974,7 +40195,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205577 \ + * GCC Linaro 4.8-2013.04 released. --- a/src/fixincludes/ChangeLog.linaro +++ b/src/fixincludes/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-12-21 Christophe Lyon <christophe.lyon@linaro.org> ++ ++ GCC Linaro 4.8-2013.12 released. ++ +2013-11-14 Christophe Lyon <christophe.lyon@linaro.org> + + GCC Linaro 4.8-2013.11 released. diff --git a/debian/patches/gcc-ppc64el.diff b/debian/patches/gcc-ppc64el.diff index 43272c0..2a4b486 100644 --- a/debian/patches/gcc-ppc64el.diff +++ b/debian/patches/gcc-ppc64el.diff @@ -4,6 +4,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ svn://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_8-branch@205859 \ | filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/ +Index: b/src/libitm/configure +=================================================================== --- a/src/libitm/configure +++ b/src/libitm/configure @@ -7270,7 +7270,7 @@ @@ -57,7 +59,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H -@@ -17401,7 +17407,44 @@ +@@ -17401,6 +17407,43 @@ esac LIBITM_CHECK_AS_HTM @@ -68,7 +70,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +if test "${libitm_cv_as_htm+set}" = set; then : + $as_echo_n "(cached) " >&6 +else - ++ + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + @@ -98,11 +100,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + ;; +esac + -+ + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether weak refs work like ELF" >&5 $as_echo_n "checking whether weak refs work like ELF... " >&6; } - if test "${ac_cv_have_elf_style_weakref+set}" = set; then : ---- a/src/libitm/ChangeLog.ibm +Index: b/src/libitm/ChangeLog.ibm +=================================================================== +--- /dev/null +++ b/src/libitm/ChangeLog.ibm @@ -0,0 +1,31 @@ +2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> @@ -136,6 +139,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + _HTM_RETRIES) New macros. + (htm_abort, htm_abort_should_retry, htm_available, htm_begin, htm_init, + htm_begin_success, htm_commit, htm_transaction_active): New functions. +Index: b/src/libitm/configure.tgt +=================================================================== --- a/src/libitm/configure.tgt +++ b/src/libitm/configure.tgt @@ -47,7 +47,10 @@ @@ -150,15 +155,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ arm*) ARCH=arm ;; +Index: b/src/libitm/config/powerpc/sjlj.S +=================================================================== --- a/src/libitm/config/powerpc/sjlj.S +++ b/src/libitm/config/powerpc/sjlj.S -@@ -26,8 +26,27 @@ +@@ -26,7 +26,26 @@ #include "asmcfi.h" -#if defined(__powerpc64__) && defined(__ELF__) +#if defined(__powerpc64__) && _CALL_ELF == 2 - .macro FUNC name ++.macro FUNC name + .globl \name + .type \name, @function +\name: @@ -177,10 +184,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + nop +.endm +#elif defined(__powerpc64__) && defined(__ELF__) -+.macro FUNC name + .macro FUNC name .globl \name, .\name .section ".opd","aw" - .align 3 @@ -117,6 +136,9 @@ #if defined(_CALL_AIXDESC) # define BASE 6*WS @@ -191,6 +197,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #elif defined(_CALL_SYSV) # define BASE 2*WS # define LR_SAVE 1*WS +Index: b/src/libitm/config/powerpc/target.h +=================================================================== --- a/src/libitm/config/powerpc/target.h +++ b/src/libitm/config/powerpc/target.h @@ -22,6 +22,10 @@ @@ -287,6 +295,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#endif + } // namespace GTM +Index: b/src/libitm/acinclude.m4 +=================================================================== --- a/src/libitm/acinclude.m4 +++ b/src/libitm/acinclude.m4 @@ -134,6 +134,20 @@ @@ -310,6 +320,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ sinclude(../libtool.m4) dnl The lines below arrange for aclocal not to bring an installed dnl libtool.m4 into aclocal.m4, while still arranging for automake to +Index: b/src/libtool.m4 +=================================================================== --- a/src/libtool.m4 +++ b/src/libtool.m4 @@ -1220,7 +1220,7 @@ @@ -345,6 +357,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*|s390*-*tpf*) +Index: b/src/libgomp/configure +=================================================================== --- a/src/libgomp/configure +++ b/src/libgomp/configure @@ -6580,7 +6580,7 @@ @@ -398,6 +412,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/libquadmath/configure +=================================================================== --- a/src/libquadmath/configure +++ b/src/libquadmath/configure @@ -6248,7 +6248,7 @@ @@ -451,6 +467,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/libsanitizer/configure +=================================================================== --- a/src/libsanitizer/configure +++ b/src/libsanitizer/configure @@ -6604,7 +6604,7 @@ @@ -504,6 +522,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/zlib/configure +=================================================================== --- a/src/zlib/configure +++ b/src/zlib/configure @@ -5853,7 +5853,7 @@ @@ -557,6 +577,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/libstdc++-v3/configure +=================================================================== --- a/src/libstdc++-v3/configure +++ b/src/libstdc++-v3/configure @@ -7111,7 +7111,7 @@ @@ -682,6 +704,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ template<typename T1, typename T2> struct same { typedef T2 type; }; +Index: b/src/libstdc++-v3/scripts/extract_symvers.in +=================================================================== --- a/src/libstdc++-v3/scripts/extract_symvers.in +++ b/src/libstdc++-v3/scripts/extract_symvers.in @@ -53,6 +53,7 @@ @@ -692,7 +716,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ egrep -v ' (LOCAL|UND) ' |\ egrep -v ' (_DYNAMIC|_GLOBAL_OFFSET_TABLE_|_PROCEDURE_LINKAGE_TABLE_|_edata|_end|_etext)$' |\ sed -e 's/ <processor specific>: / <processor_specific>:_/g' |\ ---- a/src/libstdc++-v3/ChangeLog.ibm +Index: b/src/libstdc++-v3/ChangeLog.ibm +=================================================================== +--- /dev/null +++ b/src/libstdc++-v3/ChangeLog.ibm @@ -0,0 +1,19 @@ +2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> @@ -714,6 +740,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + duplicated comment about DR 550. Add a comment to explain the issue. + * testsuite/tr1/8_c_compatibility/cmath/pow_cmath.cc: New. + +Index: b/src/libstdc++-v3/include/tr1/cmath +=================================================================== --- a/src/libstdc++-v3/include/tr1/cmath +++ b/src/libstdc++-v3/include/tr1/cmath @@ -846,10 +846,6 @@ @@ -727,14 +755,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ inline float remainder(float __x, float __y) { return __builtin_remainderf(__x, __y); } -@@ -985,10 +981,19 @@ +@@ -985,9 +981,18 @@ // DR 550. What should the return type of pow(float,int) be? // NB: C++0x and TR1 != C++03. - inline double - pow(double __x, double __y) - { return std::pow(__x, __y); } - ++ + // The std::tr1::pow(double, double) overload cannot be provided + // here, because it would clash with ::pow(double,double) declared + // in <math.h>, if <tr1/math.h> is included at the same time (raised @@ -746,11 +774,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + // std::pow(double,double) via the templatized version below. See + // the discussion about this issue here: + // http://gcc.gnu.org/ml/gcc-patches/2012-09/msg01278.html -+ + inline float pow(float __x, float __y) - { return std::pow(__x, __y); } ---- a/src/libstdc++-v3/testsuite/tr1/8_c_compatibility/cmath/pow_cmath.cc +Index: b/src/libstdc++-v3/testsuite/tr1/8_c_compatibility/cmath/pow_cmath.cc +=================================================================== +--- /dev/null +++ b/src/libstdc++-v3/testsuite/tr1/8_c_compatibility/cmath/pow_cmath.cc @@ -0,0 +1,33 @@ +// { dg-do compile } @@ -786,6 +815,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + check_ret_type<float>(std::pow(x, 2)); + check_ret_type<double>(std::tr1::pow(x, 2)); +} +Index: b/src/libmudflap/configure +=================================================================== --- a/src/libmudflap/configure +++ b/src/libmudflap/configure @@ -6377,7 +6377,7 @@ @@ -839,6 +870,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/boehm-gc/configure +=================================================================== --- a/src/boehm-gc/configure +++ b/src/boehm-gc/configure @@ -6770,7 +6770,7 @@ @@ -892,6 +925,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/lto-plugin/configure +=================================================================== --- a/src/lto-plugin/configure +++ b/src/lto-plugin/configure @@ -6044,7 +6044,7 @@ @@ -945,6 +980,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/libatomic/configure +=================================================================== --- a/src/libatomic/configure +++ b/src/libatomic/configure @@ -6505,7 +6505,7 @@ @@ -998,6 +1035,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/libbacktrace/configure +=================================================================== --- a/src/libbacktrace/configure +++ b/src/libbacktrace/configure @@ -6842,7 +6842,7 @@ @@ -1051,6 +1090,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/libjava/libltdl/configure +=================================================================== --- a/src/libjava/libltdl/configure +++ b/src/libjava/libltdl/configure @@ -4806,7 +4806,7 @@ @@ -1164,6 +1205,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/libjava/libltdl/acinclude.m4 +=================================================================== --- a/src/libjava/libltdl/acinclude.m4 +++ b/src/libjava/libltdl/acinclude.m4 @@ -519,7 +519,7 @@ @@ -1199,6 +1242,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*) +Index: b/src/libjava/classpath/configure +=================================================================== --- a/src/libjava/classpath/configure +++ b/src/libjava/classpath/configure @@ -7577,7 +7577,7 @@ @@ -1288,6 +1333,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ public class Test { public static void main(String args) +Index: b/src/libjava/configure +=================================================================== --- a/src/libjava/configure +++ b/src/libjava/configure @@ -8842,7 +8842,7 @@ @@ -1350,6 +1397,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ struct S { ~S(); }; void bar(); void foo() +Index: b/src/libgcc/config/rs6000/tramp.S +=================================================================== --- a/src/libgcc/config/rs6000/tramp.S +++ b/src/libgcc/config/rs6000/tramp.S @@ -116,4 +116,70 @@ @@ -1423,6 +1472,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +FUNC_END(__trampoline_setup) + #endif +Index: b/src/libgcc/config/rs6000/linux-unwind.h +=================================================================== --- a/src/libgcc/config/rs6000/linux-unwind.h +++ b/src/libgcc/config/rs6000/linux-unwind.h @@ -24,9 +24,19 @@ @@ -1538,7 +1589,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } } #endif ---- a/src/libgcc/ChangeLog.ibm +Index: b/src/libgcc/ChangeLog.ibm +=================================================================== +--- /dev/null +++ b/src/libgcc/ChangeLog.ibm @@ -0,0 +1,38 @@ +2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> @@ -1579,6 +1632,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Correct + location of CR save area for 64-bit little-endian systems. + +Index: b/src/config.guess +=================================================================== --- a/src/config.guess +++ b/src/config.guess @@ -1,10 +1,8 @@ @@ -1667,10 +1722,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} + if test "$?" = 0 ; then LIBC="gnulibc1" ; fi + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; ++ exit ;; + arc:Linux:*:* | arceb:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; + exit ;; arm*:Linux:*:*) eval $set_cc_for_build if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ @@ -1776,13 +1831,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ ppc:Linux:*:*) - echo powerpc-unknown-linux-gnu + echo powerpc-unknown-linux-${LIBC} - exit ;; ++ exit ;; + ppc64le:Linux:*:*) + echo powerpc64le-unknown-linux-${LIBC} + exit ;; + ppcle:Linux:*:*) + echo powerpcle-unknown-linux-${LIBC} -+ exit ;; + exit ;; s390:Linux:*:* | s390x:Linux:*:*) - echo ${UNAME_MACHINE}-ibm-linux + echo ${UNAME_MACHINE}-ibm-linux-${LIBC} @@ -1852,9 +1907,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) +Index: b/src/gcc/configure +=================================================================== --- a/src/gcc/configure +++ b/src/gcc/configure -@@ -13589,7 +13589,7 @@ +@@ -13590,7 +13590,7 @@ rm -rf conftest* ;; @@ -1863,7 +1920,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext -@@ -13614,7 +13614,10 @@ +@@ -13615,7 +13615,10 @@ ;; esac ;; @@ -1875,7 +1932,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ LD="${LD-ld} -m elf32ppclinux" ;; s390x-*linux*) -@@ -13633,7 +13636,10 @@ +@@ -13634,7 +13637,10 @@ x86_64-*linux*) LD="${LD-ld} -m elf_x86_64" ;; @@ -1887,6 +1944,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*|s390*-*tpf*) +Index: b/src/gcc/builtins.c +=================================================================== --- a/src/gcc/builtins.c +++ b/src/gcc/builtins.c @@ -5850,6 +5850,9 @@ @@ -1909,6 +1968,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return fold_builtin_fabs (loc, arg0, type); case BUILT_IN_ABS: +Index: b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c +++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c @@ -5,8 +5,7 @@ @@ -1921,7 +1982,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* fabs/fnabs/fsel */ double normal1 (double a, double b) { return __builtin_copysign (a, b); } ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c @@ -0,0 +1,65 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -1989,7 +2052,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-times "vsld" 2 } } */ +/* { dg-final { scan-assembler-times "vsrad" 1 } } */ +/* { dg-final { scan-assembler-times "vsrd" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c @@ -0,0 +1,200 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -2192,7 +2257,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-times "\[\t \]vcmpequd\[\t \]" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vcmpgtsd\[\t \]" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vcmpgtud\[\t \]" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/pr57744.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/pr57744.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/pr57744.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { powerpc*-*-* && lp64 } } } */ @@ -2234,6 +2301,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + + return 0; +} +Index: b/src/gcc/testsuite/gcc.target/powerpc/recip-1.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/recip-1.c +++ b/src/gcc/testsuite/gcc.target/powerpc/recip-1.c @@ -3,8 +3,8 @@ @@ -2247,6 +2316,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ double rsqrt_d (double a) +Index: b/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c +++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c @@ -11,7 +11,11 @@ @@ -2261,7 +2332,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } int main() ---- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -2296,7 +2369,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#endif + +#include "bool2.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ @@ -2321,7 +2396,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +{ + return (long) return_double (); +} ---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ @@ -2338,7 +2415,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#define VSX_REG_ATTR "wa" + +#include "direct-move.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -2373,6 +2452,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#endif + +#include "bool2.h" +Index: b/src/gcc/testsuite/gcc.target/powerpc/pr43154.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/pr43154.c +++ b/src/gcc/testsuite/gcc.target/powerpc/pr43154.c @@ -1,5 +1,6 @@ @@ -2382,7 +2463,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O2 -mcpu=power7" } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/pr59054.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/pr59054.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/pr59054.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ @@ -2394,7 +2477,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + +/* { dg-final { scan-assembler-not "xxlor" } } */ +/* { dg-final { scan-assembler-not "stfd" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c @@ -0,0 +1,204 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -2601,7 +2686,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-times "vrld" 3 } } */ +/* { dg-final { scan-assembler-times "vsld" 5 } } */ +/* { dg-final { scan-assembler-times "vsrad" 3 } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -2634,7 +2721,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + +/* { dg-final { scan-assembler "vupkhsw" } } */ +/* { dg-final { scan-assembler "vupklsw" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ @@ -2660,7 +2749,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-not "vperm" } } */ +/* { dg-final { scan-assembler "vpkuhum" } } */ +/* { dg-final { scan-assembler "vpkuwum" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c @@ -0,0 +1,78 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ @@ -2741,6 +2832,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + deduce_conversion (arg0code, optab[i].arg0), 0)); + } +} +Index: b/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c +++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c @@ -1,5 +1,6 @@ @@ -2750,7 +2843,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* { dg-options "-O2 -mno-pointers-to-nested-functions" } */ int ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c @@ -0,0 +1,139 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -2892,7 +2987,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler "xssqrtsp" } } */ +/* { dg-final { scan-assembler "xssubdp" } } */ +/* { dg-final { scan-assembler "xssubsp" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c @@ -0,0 +1,13 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ @@ -2908,7 +3005,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#define VSX_REG_ATTR "wa" + +#include "direct-move.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ @@ -2948,7 +3047,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#endif + +#include "bool3.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c @@ -0,0 +1,104 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -3055,7 +3156,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */ +/* { dg-final { scan-assembler-times "vupklsw" 3 } } */ +/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -3087,7 +3190,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +} + +/* { dg-final { scan-assembler "vpkudum" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move.h +Index: b/src/gcc/testsuite/gcc.target/powerpc/direct-move.h +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move.h @@ -0,0 +1,187 @@ +/* Test functions for direct move support. */ @@ -3277,7 +3382,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + return 0; +} +#endif ---- a/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -3300,7 +3407,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +{ + a += (_Decimal32) 1.0; +} ---- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c @@ -0,0 +1,217 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ @@ -3520,7 +3629,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + } + } +} ---- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c @@ -0,0 +1,207 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ @@ -3730,6 +3841,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} +Index: b/src/gcc/testsuite/gcc.target/powerpc/recip-3.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/recip-3.c +++ b/src/gcc/testsuite/gcc.target/powerpc/recip-3.c @@ -1,14 +1,14 @@ @@ -3753,6 +3866,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ double rsqrt_d (double a) +Index: b/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c +++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c @@ -1,5 +1,6 @@ @@ -3762,7 +3877,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* { dg-options "-O2 -mpointers-to-nested-functions" } */ int ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -3807,7 +3924,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler "lxsdx" } } */ +/* { dg-final { scan-assembler "stxsspx" } } */ +/* { dg-final { scan-assembler "stxsdx" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ @@ -3846,7 +3965,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#endif + +#include "bool3.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c @@ -0,0 +1,32 @@ +/* This checks the availability of the XL compiler intrinsics for @@ -3881,7 +4002,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + *result++ = __TM_failure_code (TM_buff); +} + ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c @@ -0,0 +1,249 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -4133,7 +4256,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */ + +/* { dg-final { scan-assembler-times "vgbbd" 3 } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ @@ -4173,7 +4298,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#endif + +#include "bool3.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c @@ -0,0 +1,69 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -4245,7 +4372,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + +/* { dg-final { scan-assembler-times "vclzw" 2 } } */ +/* { dg-final { scan-assembler-times "vpopcntw" 2 } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ @@ -4268,7 +4397,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + +/* { dg-final { scan-assembler "li \.\*,144" } } */ +/* { dg-final { scan-assembler "ld \.\*,128\\(1\\)" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c @@ -0,0 +1,237 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ @@ -4508,7 +4639,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +{ + *q = __sync_val_compare_and_swap (p, i, j); +} ---- a/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -4530,6 +4663,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +{ + a += (_Decimal32) 1.0; +} +Index: b/src/gcc/testsuite/gcc.target/powerpc/recip-4.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/recip-4.c +++ b/src/gcc/testsuite/gcc.target/powerpc/recip-4.c @@ -7,8 +7,8 @@ @@ -4543,6 +4678,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define SIZE 1024 +Index: b/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c +++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c @@ -1,5 +1,6 @@ @@ -4552,7 +4689,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* { dg-options "-O2 -mno-pointers-to-nested-functions" } */ extern void ext_call (int (func) (void)); ---- a/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c @@ -0,0 +1,130 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -4685,6 +4824,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-times "vsbox " 1 } } */ +/* { dg-final { scan-assembler-times "vshasigmad " 2 } } */ +/* { dg-final { scan-assembler-times "vshasigmaw " 2 } } */ +Index: b/src/gcc/testsuite/gcc.target/powerpc/pr42747.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/pr42747.c +++ b/src/gcc/testsuite/gcc.target/powerpc/pr42747.c @@ -5,4 +5,4 @@ @@ -4693,7 +4834,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -/* { dg-final { scan-assembler "xssqrtdp" } } */ +/* { dg-final { scan-assembler "xssqrtdp\|fsqrt" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c @@ -0,0 +1,26 @@ +/* Test generation of DFP instructions for POWER6. */ @@ -4722,7 +4865,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +{ + return - __builtin_fabsd64 (b); +} ---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ @@ -4743,7 +4888,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#define VSX_REG_ATTR "ww" + +#include "direct-move.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c @@ -0,0 +1,29 @@ +/* Test generation of DFP instructions for POWER6. */ @@ -4775,7 +4922,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +{ + return - __builtin_fabsd128 (a); +} ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c @@ -0,0 +1,105 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -4883,7 +5032,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-times "xxleqv" 18 } } */ +/* { dg-final { scan-assembler-times "xxlnand" 26 } } */ +/* { dg-final { scan-assembler-times "xxlorc" 26 } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c @@ -0,0 +1,87 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -4973,7 +5124,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-times "xxleqv" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnand" 2 } } */ +/* { dg-final { scan-assembler-times "xxlorc" 2 } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ @@ -4996,6 +5149,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + +/* { dg-final { scan-assembler "ld .\*,136\\(1\\)" } } */ +/* { dg-final { scan-assembler "ld .\*,120\\(1\\)" } } */ +Index: b/src/gcc/testsuite/gcc.target/powerpc/recip-5.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/recip-5.c +++ b/src/gcc/testsuite/gcc.target/powerpc/recip-5.c @@ -4,8 +4,16 @@ @@ -5017,6 +5172,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include <altivec.h> +Index: b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c +++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c @@ -89,8 +89,10 @@ @@ -5030,7 +5187,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ parm_t slot[100]; } stack_frame_t; ---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ @@ -5048,7 +5207,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#define VSX_REG_ATTR "ww" + +#include "direct-move.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ @@ -5067,7 +5228,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#define VSX_REG_ATTR "ws" + +#include "direct-move.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c @@ -0,0 +1,29 @@ +/* Test generation of DFP instructions for POWER6. */ @@ -5099,7 +5262,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +{ + return - __builtin_fabsd128 (b); +} ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -5112,6 +5277,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + +/* { dg-final { scan-assembler "xscvdpspn" } } */ +/* { dg-final { scan-assembler "xscvspdpn" } } */ +Index: b/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c +++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c @@ -16,9 +16,9 @@ @@ -5127,7 +5294,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* { dg-final { scan-assembler "xsmaxdp" } } */ /* { dg-final { scan-assembler "xsmindp" } } */ /* { dg-final { scan-assembler "xxland" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c @@ -0,0 +1,51 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -5181,7 +5350,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + __builtin_set_tfhar (a[22]); + __builtin_set_tfiar (a[23]); +} ---- a/src/gcc/testsuite/gcc.target/powerpc/bool.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -5198,7 +5369,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +TYPE op2 (TYPE a, TYPE b) { return ~(a & b); } /* nand */ +TYPE op3 (TYPE a, TYPE b) { return ~(a | b); } /* nor */ + ---- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -5233,7 +5406,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#endif + +#include "bool2.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/fusion.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/fusion.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/fusion.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -5260,6 +5435,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* { dg-final { scan-assembler-times "lhz" 2 } } */ +/* { dg-final { scan-assembler-times "extsh" 1 } } */ +/* { dg-final { scan-assembler-times "lwz" 2 } } */ +Index: b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c +++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c @@ -107,8 +107,10 @@ @@ -5319,7 +5496,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ abort(); } ---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ @@ -5338,7 +5517,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#define VSX_REG_ATTR "d" + +#include "direct-move.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ @@ -5356,7 +5537,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#define VSX_REG_ATTR "ws" + +#include "direct-move.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -5391,7 +5574,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + +/* { dg-final { scan-assembler-times "vmrgew" 2 } } */ +/* { dg-final { scan-assembler-times "vmrgow" 2 } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/bool2.h +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool2.h +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool2.h @@ -0,0 +1,29 @@ +/* Test various logical operations. */ @@ -5423,6 +5608,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +void ptr11(TYPE *p) { p[0] = p[1] & (~p[2]); } /* ANDC */ +void ptr12(TYPE *p) { p[0] = p[1] | (~p[2]); } /* ORC */ +void ptr13(TYPE *p) { p[0] = p[1] ^ (~p[2]); } /* EQV */ +Index: b/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c +++ b/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c @@ -1,5 +1,6 @@ @@ -5432,6 +5619,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */ /* { dg-final { scan-assembler-times "xvaddsp" 3 } } */ +Index: b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c +++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c @@ -33,15 +33,27 @@ @@ -5481,7 +5670,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ unsigned long slot[100]; } stack_frame_t; ---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ @@ -5499,7 +5690,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#define VSX_REG_ATTR "d" + +#include "direct-move.h" ---- a/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -5518,6 +5711,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + + return sum; +} +Index: b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c +++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c @@ -5,8 +5,7 @@ @@ -5530,7 +5725,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ double normal1 (double, double); double power5 (double, double) __attribute__((__target__("cpu=power5"))); ---- a/src/gcc/testsuite/gcc.target/powerpc/bool3.h +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool3.h +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool3.h @@ -0,0 +1,186 @@ +/* Test forcing 128-bit logical types into GPR registers. */ @@ -5719,6 +5916,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + FORCE_REG1 (c); + p[0] = c; +} +Index: b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c +=================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c +++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c @@ -19,19 +19,6 @@ @@ -5747,7 +5946,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* { dg-final { scan-assembler "vspltw" } } */ -/* { dg-final { scan-assembler "vpkuhum" } } */ -/* { dg-final { scan-assembler "vpkuwum" } } */ ---- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c +Index: b/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ @@ -5781,7 +5982,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#endif + +#include "bool2.h" ---- a/src/gcc/testsuite/ChangeLog.ibm +Index: b/src/gcc/testsuite/ChangeLog.ibm +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/ChangeLog.ibm @@ -0,0 +1,404 @@ +2013-12-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> @@ -6188,9 +6391,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com> + + Clone branch from gcc-4_8-branch, subversion id 196835. +Index: b/src/gcc/testsuite/lib/target-supports.exp +=================================================================== --- a/src/gcc/testsuite/lib/target-supports.exp +++ b/src/gcc/testsuite/lib/target-supports.exp -@@ -1311,6 +1311,32 @@ +@@ -1304,6 +1304,32 @@ return 0 } @@ -6223,7 +6428,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ # Return 1 if the target supports executing VSX instructions, 0 # otherwise. Cache the result. -@@ -2672,6 +2698,33 @@ +@@ -2767,6 +2793,33 @@ } } @@ -6257,7 +6462,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ # Return 1 if this is a PowerPC target supporting -mvsx proc check_effective_target_powerpc_vsx_ok { } { -@@ -2699,6 +2752,27 @@ +@@ -2794,6 +2847,27 @@ } } @@ -6285,7 +6490,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ # Return 1 if this is a PowerPC target supporting -mcpu=cell. proc check_effective_target_powerpc_ppu_ok { } { -@@ -2794,6 +2868,22 @@ +@@ -2889,6 +2963,22 @@ } } @@ -6308,7 +6513,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ # Return 1 if this is a SPU target with a toolchain that # supports automatic overlay generation. -@@ -4499,6 +4589,7 @@ +@@ -4594,6 +4684,7 @@ switch $arg { "vmx_hw" { set selected [check_vmx_hw_available] } "vsx_hw" { set selected [check_vsx_hw_available] } @@ -6316,7 +6521,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] } "named_sections" { set selected [check_named_sections_available] } "gc_sections" { set selected [check_gc_sections_available] } -@@ -4520,6 +4611,7 @@ +@@ -4615,6 +4706,7 @@ switch $arg { "vmx_hw" { return 1 } "vsx_hw" { return 1 } @@ -6324,7 +6529,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ "ppc_recip_hw" { return 1 } "named_sections" { return 1 } "gc_sections" { return 1 } -@@ -5077,7 +5169,9 @@ +@@ -5199,7 +5291,9 @@ } lappend DEFAULT_VECTCFLAGS "-maltivec" @@ -6335,6 +6540,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign" } +Index: b/src/gcc/testsuite/gfortran.dg/nan_7.f90 +=================================================================== --- a/src/gcc/testsuite/gfortran.dg/nan_7.f90 +++ b/src/gcc/testsuite/gfortran.dg/nan_7.f90 @@ -2,6 +2,7 @@ @@ -6345,6 +6552,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ ! PR47293 NAN not correctly read character(len=200) :: str real(16) :: r +Index: b/src/gcc/testsuite/gcc.dg/vmx/3b-15.c +=================================================================== --- a/src/gcc/testsuite/gcc.dg/vmx/3b-15.c +++ b/src/gcc/testsuite/gcc.dg/vmx/3b-15.c @@ -3,7 +3,11 @@ @@ -6373,7 +6582,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ ((vector unsigned char){1,74,78,70,76,75,79,80,82,82,82,72,8,83,81,14})), "f"); } ---- a/src/gcc/testsuite/gcc.dg/vmx/vec-set.c +Index: b/src/gcc/testsuite/gcc.dg/vmx/vec-set.c +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/gcc.dg/vmx/vec-set.c @@ -0,0 +1,14 @@ +#include "harness.h" @@ -6390,6 +6601,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + ((vector short){7, 0, 0, 0, 0, 0, 0, 0})), + "vec_set"); +} +Index: b/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c +=================================================================== --- a/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c +++ b/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c @@ -13,12 +13,27 @@ @@ -6420,6 +6633,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ static DONT_INLINE int foo(vector signed short data) { +Index: b/src/gcc/testsuite/gcc.dg/vmx/eg-5.c +=================================================================== --- a/src/gcc/testsuite/gcc.dg/vmx/eg-5.c +++ b/src/gcc/testsuite/gcc.dg/vmx/eg-5.c @@ -7,10 +7,17 @@ @@ -6440,6 +6655,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return result; } +Index: b/src/gcc/testsuite/gcc.dg/stack-usage-1.c +=================================================================== --- a/src/gcc/testsuite/gcc.dg/stack-usage-1.c +++ b/src/gcc/testsuite/gcc.dg/stack-usage-1.c @@ -38,7 +38,11 @@ @@ -6455,6 +6672,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) \ || defined (__POWERPC__) || defined (PPC) || defined (_IBMR2) # if defined (__ALTIVEC__) +Index: b/src/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c +=================================================================== --- a/src/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c +++ b/src/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c @@ -1,4 +1,5 @@ @@ -6463,6 +6682,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include <stdarg.h> #include "../../tree-vect.h" +Index: b/src/gcc/testsuite/g++.dg/lookup/using9.C +=================================================================== --- a/src/gcc/testsuite/g++.dg/lookup/using9.C +++ b/src/gcc/testsuite/g++.dg/lookup/using9.C @@ -21,11 +21,11 @@ @@ -6479,7 +6700,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - using B::f; // { dg-error "already declared" } + using B::f; // { dg-error "previous declaration" } } ---- a/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C +Index: b/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C @@ -0,0 +1,54 @@ +// { dg-do run { target { powerpc64*-*-linux* } } } @@ -6536,7 +6759,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +} + + ---- a/src/gcc/testsuite/g++.dg/overload/using3.C +Index: b/src/gcc/testsuite/g++.dg/overload/using3.C +=================================================================== +--- /dev/null +++ b/src/gcc/testsuite/g++.dg/overload/using3.C @@ -0,0 +1,16 @@ +// { dg-do compile } @@ -6555,6 +6780,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + } + using a::f; // { dg-error "conflicts" } +} +Index: b/src/gcc/testsuite/g++.dg/overload/using2.C +=================================================================== --- a/src/gcc/testsuite/g++.dg/overload/using2.C +++ b/src/gcc/testsuite/g++.dg/overload/using2.C @@ -45,7 +45,7 @@ @@ -6584,7 +6811,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ using std::c3; using other::c3; using std::C3; using other::C3; ---- a/src/gcc/cp/ChangeLog.ibm +Index: b/src/gcc/cp/ChangeLog.ibm +=================================================================== +--- /dev/null +++ b/src/gcc/cp/ChangeLog.ibm @@ -0,0 +1,11 @@ +2013-08-04 Peter Bergner <bergner@vnet.ibm.com> @@ -6598,6 +6827,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + OVERLOAD before calling OVL_USED. Call diagnose_name_conflict + instead of issuing an error without mentioning the conflicting + declaration. +Index: b/src/gcc/cp/cp-tree.h +=================================================================== --- a/src/gcc/cp/cp-tree.h +++ b/src/gcc/cp/cp-tree.h @@ -331,7 +331,7 @@ @@ -6609,6 +6840,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* If set, this OVERLOAD was created for argument-dependent lookup and can be freed afterward. */ #define OVL_ARG_DEPENDENT(NODE) TREE_LANG_FLAG_0 (OVERLOAD_CHECK (NODE)) +Index: b/src/gcc/cp/name-lookup.c +=================================================================== --- a/src/gcc/cp/name-lookup.c +++ b/src/gcc/cp/name-lookup.c @@ -2268,8 +2268,7 @@ @@ -6639,6 +6872,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ break; } } +Index: b/src/gcc/builtins.def +=================================================================== --- a/src/gcc/builtins.def +++ b/src/gcc/builtins.def @@ -252,6 +252,9 @@ @@ -6651,6 +6886,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ DEF_C99_BUILTIN (BUILT_IN_FDIM, "fdim", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) DEF_C99_BUILTIN (BUILT_IN_FDIMF, "fdimf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) DEF_C99_BUILTIN (BUILT_IN_FDIML, "fdiml", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) +Index: b/src/gcc/expr.h +=================================================================== --- a/src/gcc/expr.h +++ b/src/gcc/expr.h @@ -521,8 +521,8 @@ @@ -6664,6 +6901,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ struct locate_and_pad_arg_data *); /* Return the CODE_LABEL rtx for a LABEL_DECL, creating it if necessary. */ +Index: b/src/gcc/function.c +=================================================================== --- a/src/gcc/function.c +++ b/src/gcc/function.c @@ -2507,6 +2507,7 @@ @@ -6761,7 +7000,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && targetm.calls.return_in_msb (TREE_TYPE (decl_result))) { emit_move_insn (gen_rtx_REG (GET_MODE (decl_rtl), ---- a/src/gcc/ChangeLog.ibm +Index: b/src/gcc/ChangeLog.ibm +=================================================================== +--- /dev/null +++ b/src/gcc/ChangeLog.ibm @@ -0,0 +1,2443 @@ +2013-12-10 Peter Bergner <bergner@vnet.ibm.com> @@ -9207,6 +9448,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + Clone branch from gcc-4_8-branch, subversion id 196835. + * REVISION: New file, track subversion id. + +Index: b/src/gcc/calls.c +=================================================================== --- a/src/gcc/calls.c +++ b/src/gcc/calls.c @@ -983,6 +983,7 @@ @@ -9254,13 +9497,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ NULL_TREE, &args_size, &argvec[count].locate); args_size.constant += argvec[count].locate.size.constant; gcc_assert (!argvec[count].locate.size.var); ---- a/src/gcc/REVISION +Index: b/src/gcc/REVISION +=================================================================== +--- /dev/null +++ b/src/gcc/REVISION @@ -0,0 +1 @@ +[ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] +Index: b/src/gcc/config.gcc +=================================================================== --- a/src/gcc/config.gcc +++ b/src/gcc/config.gcc -@@ -420,7 +420,7 @@ +@@ -421,7 +421,7 @@ ;; powerpc*-*-*) cpu_type=rs6000 @@ -9269,7 +9516,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ need_64bit_hwint=yes case x$with_cpu in xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[345678]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500) -@@ -3509,7 +3509,7 @@ +@@ -3535,7 +3535,7 @@ ;; powerpc*-*-* | rs6000-*-*) @@ -9278,7 +9525,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do eval "val=\$with_$which" -@@ -3546,6 +3546,16 @@ +@@ -3572,6 +3572,16 @@ ;; esac done @@ -9295,7 +9542,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ ;; s390*-*-*) ---- a/src/gcc/config/rs6000/power8.md +Index: b/src/gcc/config/rs6000/power8.md +=================================================================== +--- /dev/null +++ b/src/gcc/config/rs6000/power8.md @@ -0,0 +1,373 @@ +;; Scheduling description for IBM POWER8 processor. @@ -9671,6 +9920,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +Index: b/src/gcc/config/rs6000/vector.md +=================================================================== --- a/src/gcc/config/rs6000/vector.md +++ b/src/gcc/config/rs6000/vector.md @@ -24,13 +24,13 @@ @@ -9800,24 +10051,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - (match_operand:VEC_L 2 "vlogical_operand" "")))] - "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" - "") -+;; Vector count leading zeros -+(define_expand "clz<mode>2" -+ [(set (match_operand:VEC_I 0 "register_operand" "") -+ (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] -+ "TARGET_P8_VECTOR") - +- -(define_expand "ior<mode>3" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") - (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") - (match_operand:VEC_L 2 "vlogical_operand" "")))] - "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" - "") -+;; Vector population count -+(define_expand "popcount<mode>2" -+ [(set (match_operand:VEC_I 0 "register_operand" "") -+ (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] -+ "TARGET_P8_VECTOR") - +- -(define_expand "and<mode>3" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") - (and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") @@ -9844,7 +10085,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - (match_operand:VEC_L 1 "vlogical_operand" "")))] - "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" - "") -- ++;; Vector count leading zeros ++(define_expand "clz<mode>2" ++ [(set (match_operand:VEC_I 0 "register_operand" "") ++ (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] ++ "TARGET_P8_VECTOR") ++ ++;; Vector population count ++(define_expand "popcount<mode>2" ++ [(set (match_operand:VEC_I 0 "register_operand" "") ++ (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] ++ "TARGET_P8_VECTOR") + + ;; Same size conversions (define_expand "float<VEC_int><mode>2" @@ -9961,9 +10213,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ "") ;; Vector reduction expanders for VSX +Index: b/src/gcc/config/rs6000/constraints.md +=================================================================== --- a/src/gcc/config/rs6000/constraints.md +++ b/src/gcc/config/rs6000/constraints.md -@@ -52,22 +52,62 @@ +@@ -52,21 +52,61 @@ "@internal") ;; Use w as a prefix to add VSX modes @@ -9980,8 +10234,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" - "@internal") + "VSX vector register to hold vector float data or NO_REGS.") - --;; scalar double (DF) ++ +(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" + "If -mmfpgpr was used, a floating point register or NO_REGS.") + @@ -9998,7 +10251,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + +(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]" + "General purpose register if 64-bit instructions are enabled or NO_REGS.") -+ + +-;; scalar double (DF) (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" - "@internal") + "VSX vector register to hold scalar double values or NO_REGS.") @@ -10008,7 +10262,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - "@internal") +(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]" + "VSX vector register to hold 128 bit integer or NO_REGS.") - ++ +(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]" + "Altivec register to use for float/32-bit int loads/stores or NO_REGS.") + @@ -10031,10 +10285,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +(define_memory_constraint "wQ" + "Memory operand suitable for the load/store quad instructions" + (match_operand 0 "quad_memory_operand")) -+ + ;; Altivec style load/store that ignores the bottom bits of the address (define_memory_constraint "wZ" - "Indexed or indirect memory operand, ignoring the bottom 4 bits" +Index: b/src/gcc/config/rs6000/predicates.md +=================================================================== --- a/src/gcc/config/rs6000/predicates.md +++ b/src/gcc/config/rs6000/predicates.md @@ -124,6 +124,11 @@ @@ -10434,6 +10689,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + + return 0; +}) +Index: b/src/gcc/config/rs6000/ppc-asm.h +=================================================================== --- a/src/gcc/config/rs6000/ppc-asm.h +++ b/src/gcc/config/rs6000/ppc-asm.h @@ -256,7 +256,30 @@ @@ -10468,7 +10725,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define FUNC_NAME(name) GLUE(.,name) #define JUMP_TARGET(name) FUNC_NAME(name) #define FUNC_START(name) \ ---- a/src/gcc/config/rs6000/htm.md +Index: b/src/gcc/config/rs6000/htm.md +=================================================================== +--- /dev/null +++ b/src/gcc/config/rs6000/htm.md @@ -0,0 +1,366 @@ +;; Hardware Transactional Memory (HTM) patterns. @@ -10837,6 +11096,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "mtspr %1,%0"; + [(set_attr "type" "htm") + (set_attr "length" "4")]) +Index: b/src/gcc/config/rs6000/rs6000-modes.def +=================================================================== --- a/src/gcc/config/rs6000/rs6000-modes.def +++ b/src/gcc/config/rs6000/rs6000-modes.def @@ -41,3 +41,8 @@ @@ -10848,6 +11109,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + for quad memory atomic operations to force getting an even/odd register + combination. */ +PARTIAL_INT_MODE (TI); +Index: b/src/gcc/config/rs6000/rs6000-cpus.def +=================================================================== --- a/src/gcc/config/rs6000/rs6000-cpus.def +++ b/src/gcc/config/rs6000/rs6000-cpus.def @@ -28,7 +28,7 @@ @@ -10927,7 +11190,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) ---- a/src/gcc/config/rs6000/htmintrin.h +Index: b/src/gcc/config/rs6000/htmintrin.h +=================================================================== +--- /dev/null +++ b/src/gcc/config/rs6000/htmintrin.h @@ -0,0 +1,131 @@ +/* Hardware Transactional Memory (HTM) intrinsics. @@ -11061,6 +11326,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + _TEXASR_EXTRACT_BITS(TEXASR, 63, 12) + +#endif /* _HTMINTRIN_H */ +Index: b/src/gcc/config/rs6000/rs6000-protos.h +=================================================================== --- a/src/gcc/config/rs6000/rs6000-protos.h +++ b/src/gcc/config/rs6000/rs6000-protos.h @@ -50,11 +50,13 @@ @@ -11123,6 +11390,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ extern void rs6000_aix_asm_output_dwarf_table_ref (char *); extern void get_ppc476_thunk_name (char name[32]); extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); +Index: b/src/gcc/config/rs6000/t-rs6000 +=================================================================== --- a/src/gcc/config/rs6000/t-rs6000 +++ b/src/gcc/config/rs6000/t-rs6000 @@ -60,6 +60,7 @@ @@ -11142,7 +11411,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ $(srcdir)/config/rs6000/spe.md \ $(srcdir)/config/rs6000/dfp.md \ $(srcdir)/config/rs6000/paired.md ---- a/src/gcc/config/rs6000/htmxlintrin.h +Index: b/src/gcc/config/rs6000/htmxlintrin.h +=================================================================== +--- /dev/null +++ b/src/gcc/config/rs6000/htmxlintrin.h @@ -0,0 +1,208 @@ +/* XL compiler Hardware Transactional Memory (HTM) execution intrinsics. @@ -11353,6 +11624,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +#endif + +#endif /* _HTMXLINTRIN_H */ +Index: b/src/gcc/config/rs6000/rs6000-builtin.def +=================================================================== --- a/src/gcc/config/rs6000/rs6000-builtin.def +++ b/src/gcc/config/rs6000/rs6000-builtin.def @@ -30,7 +30,8 @@ @@ -11737,6 +12010,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Darwin CfString builtin. */ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, +Index: b/src/gcc/config/rs6000/rs6000-c.c +=================================================================== --- a/src/gcc/config/rs6000/rs6000-c.c +++ b/src/gcc/config/rs6000/rs6000-c.c @@ -315,6 +315,8 @@ @@ -11761,18 +12036,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* options from the builtin masks. */ if ((bu_mask & RS6000_BTM_SPE) != 0) -@@ -453,7 +461,11 @@ +@@ -453,6 +461,10 @@ case ABI_AIX: builtin_define ("_CALL_AIXDESC"); builtin_define ("_CALL_AIX"); + builtin_define ("_CALL_ELF=1"); - break; ++ break; + case ABI_ELFv2: + builtin_define ("_CALL_ELF=2"); -+ break; + break; case ABI_DARWIN: builtin_define ("_CALL_DARWIN"); - break; @@ -465,6 +477,13 @@ if (TARGET_SOFT_FLOAT || !TARGET_FPRS) builtin_define ("__NO_FPRS__"); @@ -12505,6 +12779,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return altivec_build_resolved_builtin (args, n, desc); bad: +Index: b/src/gcc/config/rs6000/rs6000.opt +=================================================================== --- a/src/gcc/config/rs6000/rs6000.opt +++ b/src/gcc/config/rs6000/rs6000.opt @@ -181,13 +181,16 @@ @@ -12591,6 +12867,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +mupper-regs-sf +Target Undocumented Mask(UPPER_REGS_SF) Var(rs6000_isa_flags) +Allow float variables in upper registers with -mcpu=power8 or -mp8-vector +Index: b/src/gcc/config/rs6000/linux64.h +=================================================================== --- a/src/gcc/config/rs6000/linux64.h +++ b/src/gcc/config/rs6000/linux64.h @@ -25,9 +25,6 @@ @@ -12641,7 +12919,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ -@@ -351,7 +364,11 @@ +@@ -362,7 +375,11 @@ #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)" #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" @@ -12654,6 +12932,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" #if DEFAULT_LIBC == LIBC_UCLIBC +Index: b/src/gcc/config/rs6000/darwin.h +=================================================================== --- a/src/gcc/config/rs6000/darwin.h +++ b/src/gcc/config/rs6000/darwin.h @@ -205,7 +205,8 @@ @@ -12666,6 +12946,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* This outputs NAME to FILE. */ +Index: b/src/gcc/config/rs6000/rs6000.c +=================================================================== --- a/src/gcc/config/rs6000/rs6000.c +++ b/src/gcc/config/rs6000/rs6000.c @@ -96,6 +96,7 @@ @@ -13113,12 +13395,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + CCmode, + CCUNSmode, + CCEQmode, - }; - -- fprintf (stderr, "Register information: (last virtual reg = %d)\n", -- LAST_VIRTUAL_REGISTER); -- rs6000_debug_reg_print (0, 31, "gr"); -- rs6000_debug_reg_print (32, 63, "fp"); ++ }; ++ + /* Virtual regs we are interested in. */ + const static struct { + int regno; /* register number. */ @@ -13140,8 +13418,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + { VIRTUAL_CFA_REGNUM, "cfa (frame): " }, + { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" }, + { LAST_VIRTUAL_REGISTER, "last virtual: " }, -+ }; -+ + }; + +- fprintf (stderr, "Register information: (last virtual reg = %d)\n", +- LAST_VIRTUAL_REGISTER); +- rs6000_debug_reg_print (0, 31, "gr"); +- rs6000_debug_reg_print (32, 63, "fp"); + fputs ("\nHard register information:\n", stderr); + rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr"); + rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp"); @@ -13159,7 +13441,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ fprintf (stderr, "\n" "d reg_class = %s\n" -@@ -1734,25 +2012,70 @@ +@@ -1734,24 +2012,69 @@ "wa reg_class = %s\n" "wd reg_class = %s\n" "wf reg_class = %s\n" @@ -13208,7 +13490,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]); - } + rs6000_debug_print_mode (m); - ++ + fputs ("\n", stderr); + + for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++) @@ -13236,10 +13518,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + if (!first_time) + fputs ("\n", stderr); + } -+ + if (nl) fputs (nl, stderr); - @@ -1913,6 +2236,7 @@ { case ABI_NONE: abi_str = "none"; break; @@ -13370,7 +13651,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ int align64; int align32; -@@ -1987,21 +2413,55 @@ +@@ -1987,20 +2413,54 @@ rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS; rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS; rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS; @@ -13403,18 +13684,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE; + + if (TARGET_VSX) ++ { ++ reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE; ++ reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE; ++ } ++ else { - rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE; - rs6000_vector_reload[m][0] = CODE_FOR_nothing; - rs6000_vector_reload[m][1] = CODE_FOR_nothing; -+ reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE; -+ reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE; - } -+ else -+ { + reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE; + reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE; -+ } + } - for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++) - rs6000_constraints[c] = NO_REGS; @@ -13424,16 +13705,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + gcc_assert ((int)VECTOR_NONE == 0); + memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit)); + memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit)); - ++ + gcc_assert ((int)CODE_FOR_nothing == 0); + memset ((void *) ®_addr[0], '\0', sizeof (reg_addr)); + + gcc_assert ((int)NO_REGS == 0); + memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints)); -+ + /* The VSX hardware allows native alignment for vectors, but control whether the compiler believes it can use native alignment or still uses 128-bit alignment. */ - if (TARGET_VSX && !TARGET_VSX_ALIGN_128) @@ -2062,12 +2522,13 @@ } } @@ -13502,7 +13782,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (TARGET_HARD_FLOAT && TARGET_FPRS) rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; -@@ -2092,64 +2587,158 @@ +@@ -2092,63 +2587,157 @@ if (TARGET_VSX) { @@ -13512,12 +13792,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - V4SF, wd = register class to use for V2DF, and ws = register classs to - use for DF scalars. */ rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; -+ rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; -- rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; +- rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY - ? VSX_REGS - : FLOAT_REGS); ++ rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; + + if (TARGET_VSX_TIMODE) + rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; @@ -13587,6 +13867,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store; - rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load; - if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY) +- { +- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store; +- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load; + reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store; + reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load; + reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store; @@ -13600,14 +13883,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store; + reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load; + if (TARGET_VSX && TARGET_UPPER_REGS_DF) - { -- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store; -- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load; ++ { + reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; + reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; + reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; + reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load; - } ++ } + if (TARGET_P8_VECTOR) + { + reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store; @@ -13648,7 +13929,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd; + reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf; + } -+ } + } } else { @@ -13678,14 +13959,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store; + reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load; + if (TARGET_VSX && TARGET_UPPER_REGS_DF) - { -- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store; -- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load; ++ { + reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; + reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; + reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; + reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load; - } ++ } + if (TARGET_P8_VECTOR) + { + reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store; @@ -13694,13 +13973,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load; + } + if (TARGET_VSX_TIMODE) -+ { + { +- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store; +- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load; + reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store; + reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load; -+ } + } } } - @@ -2267,6 +2856,11 @@ } } @@ -14205,7 +14485,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ default: break; } -@@ -5416,7 +6247,7 @@ +@@ -5406,6 +6237,7 @@ + case DFmode: + case DDmode: + case DImode: ++ case PTImode: + /* On e500v2, we may have: + + (subreg:DF (mem:DI (plus (reg) (const_int))) 0). +@@ -5416,7 +6248,7 @@ /* If we are using VSX scalar loads, restrict ourselves to reg+reg addressing. */ @@ -14214,15 +14502,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return false; if (!worst_case) -@@ -5430,6 +6261,7 @@ - case TFmode: - case TDmode: - case TImode: -+ case PTImode: - if (TARGET_E500_DOUBLE) - return (SPE_CONST_OFFSET_OK (offset) - && SPE_CONST_OFFSET_OK (offset + 8)); -@@ -5526,7 +6358,7 @@ +@@ -5527,7 +6359,7 @@ if (TARGET_ELF || TARGET_MACHO) { @@ -14231,7 +14511,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return false; if (TARGET_TOC) return false; -@@ -5582,8 +6414,11 @@ +@@ -5583,8 +6415,11 @@ if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx) return force_reg (Pmode, XEXP (x, 0)); @@ -14244,7 +14524,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), force_reg (Pmode, XEXP (x, 1))); -@@ -5603,11 +6438,12 @@ +@@ -5604,11 +6439,12 @@ case TFmode: case TDmode: case TImode: @@ -14258,7 +14538,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ extra = 8; break; default: -@@ -6099,10 +6935,13 @@ +@@ -6100,10 +6936,13 @@ 1, const0_rtx, Pmode); r3 = gen_rtx_REG (Pmode, 3); @@ -14276,7 +14556,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ else if (DEFAULT_ABI == ABI_V4) insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx); else -@@ -6121,10 +6960,13 @@ +@@ -6122,10 +6961,13 @@ 1, const0_rtx, Pmode); r3 = gen_rtx_REG (Pmode, 3); @@ -14294,7 +14574,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ else if (DEFAULT_ABI == ABI_V4) insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx); else -@@ -6338,7 +7180,7 @@ +@@ -6339,7 +7181,7 @@ && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode || mode == DImode)) @@ -14303,7 +14583,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; -@@ -6369,7 +7211,7 @@ +@@ -6370,7 +7212,7 @@ if (GET_CODE (x) == SYMBOL_REF && reg_offset_p @@ -14312,7 +14592,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && !SPE_VECTOR_MODE (mode) #if TARGET_MACHO && DEFAULT_ABI == ABI_DARWIN -@@ -6395,6 +7237,8 @@ +@@ -6396,6 +7238,8 @@ mem is sufficiently aligned. */ && mode != TFmode && mode != TDmode @@ -14321,7 +14601,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && (mode != DImode || TARGET_POWERPC64) && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT))) -@@ -6515,15 +7359,9 @@ +@@ -6516,15 +7360,9 @@ return 0; if (legitimate_indirect_address_p (x, reg_ok_strict)) return 1; @@ -14340,7 +14620,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) return 1; if (virtual_stack_registers_memory_p (x)) -@@ -6533,6 +7371,13 @@ +@@ -6534,6 +7372,13 @@ if (reg_offset_p && legitimate_constant_pool_address_p (x, mode, reg_ok_strict)) return 1; @@ -14354,7 +14634,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ if (! reg_ok_strict && reg_offset_p -@@ -6544,31 +7389,20 @@ +@@ -6545,31 +7390,20 @@ return 1; if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false)) return 1; @@ -14391,7 +14671,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict) && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict, false) -@@ -6589,10 +7423,13 @@ +@@ -6590,10 +7424,13 @@ bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict); fprintf (stderr, "\nrs6000_legitimate_address_p: return = %s, mode = %s, " @@ -14406,7 +14686,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ GET_RTX_NAME (GET_CODE (x))); debug_rtx (x); -@@ -6758,7 +7595,7 @@ +@@ -6759,7 +7596,7 @@ /* The TOC register is not killed across calls in a way that is visible to the compiler. */ @@ -14415,7 +14695,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ call_really_used_regs[2] = 0; if (DEFAULT_ABI == ABI_V4 -@@ -7006,7 +7843,7 @@ +@@ -7007,7 +7844,7 @@ } /* Helper for the following. Get rid of [r+r] memory refs @@ -14424,7 +14704,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ static void rs6000_eliminate_indexed_memrefs (rtx operands[2]) -@@ -7031,6 +7868,107 @@ +@@ -7032,6 +7869,107 @@ copy_addr_to_reg (XEXP (operands[1], 0))); } @@ -14532,7 +14812,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Emit a move from SOURCE to DEST in mode MODE. */ void rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) -@@ -7151,6 +8089,7 @@ +@@ -7152,6 +8090,7 @@ if (reload_in_progress && mode == SDmode @@ -14540,7 +14820,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && MEM_P (operands[0]) && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot) && REG_P (operands[1])) -@@ -7163,7 +8102,9 @@ +@@ -7164,7 +8103,9 @@ } else if (INT_REGNO_P (REGNO (operands[1]))) { @@ -14551,7 +14831,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ mem = eliminate_regs (mem, VOIDmode, NULL_RTX); emit_insn (gen_movsd_hardfloat (mem, operands[1])); } -@@ -7175,6 +8116,7 @@ +@@ -7176,6 +8117,7 @@ && mode == SDmode && REG_P (operands[0]) && MEM_P (operands[1]) @@ -14559,7 +14839,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot)) { if (FP_REGNO_P (REGNO (operands[0]))) -@@ -7185,7 +8127,9 @@ +@@ -7186,7 +8128,9 @@ } else if (INT_REGNO_P (REGNO (operands[0]))) { @@ -14570,7 +14850,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ mem = eliminate_regs (mem, VOIDmode, NULL_RTX); emit_insn (gen_movsd_hardfloat (operands[0], mem)); } -@@ -7388,6 +8332,11 @@ +@@ -7389,6 +8333,11 @@ break; case TImode: @@ -14582,7 +14862,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ rs6000_eliminate_indexed_memrefs (operands); break; -@@ -7426,18 +8375,231 @@ +@@ -7427,18 +8376,231 @@ } /* Nonzero if we can use a floating-point register to pass this arg. */ @@ -14816,7 +15096,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Return a nonzero value to say to return the function value in memory, just as large structures are always returned. TYPE will be the data type of the value, and FNTYPE will be the type of the -@@ -7490,6 +8652,16 @@ +@@ -7491,6 +8653,16 @@ /* Otherwise fall through to more conventional ABI rules. */ } @@ -14833,7 +15113,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (AGGREGATE_TYPE_P (type) && (aix_struct_return || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) -@@ -7521,6 +8693,19 @@ +@@ -7522,6 +8694,19 @@ return false; } @@ -14853,7 +15133,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #ifdef HAVE_AS_GNU_ATTRIBUTE /* Return TRUE if a call to function FNDECL may be one that potentially affects the function calling ABI of the object file. */ -@@ -7657,7 +8842,7 @@ +@@ -7658,7 +8843,7 @@ static bool rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type) { @@ -14862,7 +15142,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return must_pass_in_stack_var_size (mode, type); else return must_pass_in_stack_var_size_or_pad (mode, type); -@@ -7738,6 +8923,11 @@ +@@ -7739,6 +8924,11 @@ static unsigned int rs6000_function_arg_boundary (enum machine_mode mode, const_tree type) { @@ -14874,7 +15154,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (DEFAULT_ABI == ABI_V4 && (GET_MODE_SIZE (mode) == 8 || (TARGET_HARD_FLOAT -@@ -7749,12 +8939,13 @@ +@@ -7750,12 +8940,13 @@ && int_size_in_bytes (type) >= 8 && int_size_in_bytes (type) < 16)) return 64; @@ -14891,7 +15171,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && mode == BLKmode && type && TYPE_ALIGN (type) > 64) return 128; -@@ -7762,6 +8953,16 @@ +@@ -7763,6 +8954,16 @@ return PARM_BOUNDARY; } @@ -14908,7 +15188,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* For a function parm of MODE and TYPE, return the starting word in the parameter area. NWORDS of the parameter area are already used. */ -@@ -7770,11 +8971,9 @@ +@@ -7771,11 +8972,9 @@ unsigned int nwords) { unsigned int align; @@ -14921,7 +15201,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* Compute the size (in words) of a function argument. */ -@@ -7881,7 +9080,7 @@ +@@ -7882,7 +9081,7 @@ if (TREE_CODE (ftype) == RECORD_TYPE) rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos); @@ -14930,7 +15210,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3; rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0); -@@ -7922,7 +9121,7 @@ +@@ -7923,7 +9122,7 @@ else cum->words += n_fpregs; } @@ -14939,7 +15219,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0); cum->vregno++; -@@ -7959,6 +9158,11 @@ +@@ -7960,6 +9159,11 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode, const_tree type, bool named, int depth) { @@ -14951,7 +15231,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Only tick off an argument if we're not recursing. */ if (depth == 0) cum->nargs_prototype--; -@@ -7979,15 +9183,16 @@ +@@ -7980,15 +9184,16 @@ #endif if (TARGET_ALTIVEC_ABI @@ -14971,7 +15251,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (!TARGET_ALTIVEC) error ("cannot pass argument in vector register because" " altivec instructions are disabled, use -maltivec" -@@ -7996,7 +9201,8 @@ +@@ -7997,7 +9202,8 @@ /* PowerPC64 Linux and AIX allocate GPRs for a vector argument even if it is going to be passed in a vector register. Darwin does the same for variable-argument functions. */ @@ -14981,7 +15261,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ || (cum->stdarg && DEFAULT_ABI != ABI_V4)) stack = true; } -@@ -8007,15 +9213,13 @@ +@@ -8008,15 +9214,13 @@ { int align; @@ -15003,7 +15283,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ else align = cum->words & 1; cum->words += align + rs6000_arg_size (mode, type); -@@ -8140,15 +9344,15 @@ +@@ -8141,15 +9345,15 @@ cum->words = align_words + n_words; @@ -15022,7 +15302,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } if (TARGET_DEBUG_ARG) -@@ -8358,7 +9562,7 @@ +@@ -8359,7 +9563,7 @@ if (TREE_CODE (ftype) == RECORD_TYPE) rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k); @@ -15031,7 +15311,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; #if 0 -@@ -8386,7 +9590,7 @@ +@@ -8387,7 +9591,7 @@ if (mode == TFmode || mode == TDmode) cum->fregno++; } @@ -15040,7 +15320,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); rvec[(*k)++] -@@ -8503,6 +9707,84 @@ +@@ -8504,6 +9708,84 @@ return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); } @@ -15125,7 +15405,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Determine where to put an argument to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. -@@ -8537,6 +9819,8 @@ +@@ -8538,6 +9820,8 @@ { CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); enum rs6000_abi abi = DEFAULT_ABI; @@ -15134,7 +15414,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4 uses to say fp args were passed in registers. -@@ -8563,6 +9847,8 @@ +@@ -8564,6 +9848,8 @@ return GEN_INT (cum->call_cookie & ~CALL_LIBCALL); } @@ -15143,7 +15423,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type)) { rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false); -@@ -8571,33 +9857,30 @@ +@@ -8572,33 +9858,30 @@ /* Else fall through to usual handling. */ } @@ -15200,7 +15480,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ else if (TARGET_ALTIVEC_ABI && (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || (type && TREE_CODE (type) == VECTOR_TYPE -@@ -8612,13 +9895,13 @@ +@@ -8613,13 +9896,13 @@ int align, align_words, n_words; enum machine_mode part_mode; @@ -15220,7 +15500,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ else align = cum->words & 1; align_words = cum->words + align; -@@ -8696,101 +9979,50 @@ +@@ -8697,101 +9980,50 @@ /* _Decimal128 must be passed in an even/odd float register pair. This assumes that the register number is odd when fregno is odd. */ @@ -15237,25 +15517,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - bool needs_psave; - enum machine_mode fmode = mode; - unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; -+ rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1]; -+ rtx r, off; -+ int i, k = 0; -+ unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3; - +- - if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) - { - /* Currently, we only ever need one reg here because complex - doubles are split. */ - gcc_assert (cum->fregno == FP_ARG_MAX_REG - && (fmode == TFmode || fmode == TDmode)); -+ /* Do we also need to pass this argument in the parameter -+ save area? */ -+ if (type && (cum->nargs_prototype <= 0 -+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) -+ && TARGET_XL_COMPAT -+ && align_words >= GP_ARG_NUM_REG))) -+ k = rs6000_psave_function_arg (mode, type, align_words, rvec); - +- - /* Long double or _Decimal128 split over regs and memory. */ - fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode; - } @@ -15273,13 +15542,27 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - - k = 0; - if (needs_psave) -+ /* Describe where this argument goes in the fprs. */ -+ for (i = 0; i < n_elts -+ && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++) - { +- { - /* Describe the part that goes in gprs or the stack. - This piece must come first, before the fprs. */ - if (align_words < GP_ARG_NUM_REG) ++ rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1]; ++ rtx r, off; ++ int i, k = 0; ++ unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3; ++ ++ /* Do we also need to pass this argument in the parameter ++ save area? */ ++ if (type && (cum->nargs_prototype <= 0 ++ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) ++ && TARGET_XL_COMPAT ++ && align_words >= GP_ARG_NUM_REG))) ++ k = rs6000_psave_function_arg (mode, type, align_words, rvec); ++ ++ /* Describe where this argument goes in the fprs. */ ++ for (i = 0; i < n_elts ++ && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++) ++ { + /* Check if the argument is split over registers and memory. + This can only ever happen for long double or _Decimal128; + complex types are handled via split_complex_arg. */ @@ -15287,10 +15570,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1) { - unsigned long n_words = rs6000_arg_size (mode, type); -+ gcc_assert (fmode == TFmode || fmode == TDmode); -+ fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode; -+ } - +- - if (align_words + n_words > GP_ARG_NUM_REG - || (TARGET_32BIT && TARGET_POWERPC64)) - { @@ -15323,19 +15603,22 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); - rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); - } -- } ++ gcc_assert (fmode == TFmode || fmode == TDmode); ++ fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode; + } - else - /* It's entirely in memory. */ - rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); -+ r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg); -+ off = GEN_INT (i * GET_MODE_SIZE (elt_mode)); -+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); - } +- } - /* Describe where this piece goes in the fprs. */ - r = gen_rtx_REG (fmode, cum->fregno); - rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); -- ++ r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg); ++ off = GEN_INT (i * GET_MODE_SIZE (elt_mode)); ++ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); ++ } + - return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); + return rs6000_finish_function_arg (mode, rvec, k); } @@ -15350,7 +15633,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); } else -@@ -8809,42 +10041,62 @@ +@@ -8810,15 +10042,31 @@ tree type, bool named) { CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); @@ -15359,9 +15642,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ int align_words; + enum machine_mode elt_mode; + int n_elts; - -+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts); + ++ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts); + if (DEFAULT_ABI == ABI_V4) return 0; @@ -15376,16 +15659,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + PARALLEL including a memory element as necessary. */ + if (TARGET_64BIT && ! cum->prototype) + return 0; - ++ + /* Otherwise, we pass in VRs only. Check for partial copies. */ + passed_in_gprs = false; + if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1) + ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16; + } -+ + /* In this complicated case we just disable the partial_nregs code. */ if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type)) - return 0; +@@ -8826,26 +10074,30 @@ align_words = rs6000_parm_start (mode, type, cum->words); @@ -15427,29 +15710,49 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8); -@@ -8925,6 +10177,139 @@ +@@ -8926,41 +10178,174 @@ return 0; } +-static void +-rs6000_move_block_from_reg (int regno, rtx x, int nregs) +/* Process parameter of type TYPE after ARGS_SO_FAR parameters were + already processes. Return true if the parameter must be passed + (fully or partially) on the stack. */ + +static bool +rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type) -+{ + { +- int i; +- enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; + enum machine_mode mode; + int unsignedp; + rtx entry_parm; -+ + +- if (nregs == 0) +- return; + /* Catch errors. */ + if (type == NULL || type == error_mark_node) + return true; -+ + +- for (i = 0; i < nregs; i++) +- { +- rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode)); +- if (reload_completed) +- { +- if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) +- tem = NULL_RTX; +- else +- tem = simplify_gen_subreg (reg_mode, x, BLKmode, +- i * GET_MODE_SIZE (reg_mode)); +- } +- else +- tem = replace_equiv_address (tem, XEXP (tem, 0)); + /* Handle types with no storage requirement. */ + if (TYPE_MODE (type) == VOIDmode) + return false; -+ + +- gcc_assert (tem); + /* Handle complex types. */ + if (TREE_CODE (type) == COMPLEX_TYPE) + return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)) @@ -15468,16 +15771,24 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + /* Find mode as it is passed by the ABI. */ + unsignedp = TYPE_UNSIGNED (type); + mode = promote_mode (type, TYPE_MODE (type), &unsignedp); -+ + +- emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); +- } +-} +- +-/* Perform any needed actions needed for a function that is receiving a +- variable number of arguments. + /* If we must pass in stack, we need a stack. */ + if (rs6000_must_pass_in_stack (mode, type)) + return true; -+ + +- CUM is as above. + /* If there is no incoming register, we need a stack. */ + entry_parm = rs6000_function_arg (args_so_far, mode, type, true); + if (entry_parm == NULL) + return true; -+ + +- MODE and TYPE are the mode and type of the current parameter. + /* Likewise if we need to pass both in registers and on the stack. */ + if (GET_CODE (entry_parm) == PARALLEL + && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX) @@ -15564,10 +15875,45 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + return reg_parm_stack_space; +} + - static void - rs6000_move_block_from_reg (int regno, rtx x, int nregs) - { -@@ -9306,8 +10691,10 @@ ++static void ++rs6000_move_block_from_reg (int regno, rtx x, int nregs) ++{ ++ int i; ++ enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; ++ ++ if (nregs == 0) ++ return; ++ ++ for (i = 0; i < nregs; i++) ++ { ++ rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode)); ++ if (reload_completed) ++ { ++ if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) ++ tem = NULL_RTX; ++ else ++ tem = simplify_gen_subreg (reg_mode, x, BLKmode, ++ i * GET_MODE_SIZE (reg_mode)); ++ } ++ else ++ tem = replace_equiv_address (tem, XEXP (tem, 0)); ++ ++ gcc_assert (tem); ++ ++ emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); ++ } ++} ++ ++/* Perform any needed actions needed for a function that is receiving a ++ variable number of arguments. ++ ++ CUM is as above. ++ ++ MODE and TYPE are the mode and type of the current parameter. + + PRETEND_SIZE is a variable that should be set to the amount of stack + that must be pushed by the prolog to pretend that our caller pushed +@@ -9307,8 +10692,10 @@ We don't need to check for pass-by-reference because of the test above. We can return a simplifed answer, since we know there's no offset to add. */ @@ -15580,7 +15926,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && integer_zerop (TYPE_SIZE (type))) { unsigned HOST_WIDE_INT align, boundary; -@@ -9602,6 +10989,7 @@ +@@ -9603,6 +10990,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -15588,7 +15934,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9615,6 +11003,7 @@ +@@ -9616,6 +11004,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -15596,7 +15942,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9633,6 +11022,7 @@ +@@ -9634,6 +11023,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -15604,7 +15950,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9646,6 +11036,7 @@ +@@ -9647,6 +11037,7 @@ { MASK, ICODE, NAME, ENUM }, #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -15612,7 +15958,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9664,6 +11055,7 @@ +@@ -9665,6 +11056,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -15620,7 +15966,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9677,6 +11069,7 @@ +@@ -9678,6 +11070,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -15628,7 +15974,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9693,6 +11086,7 @@ +@@ -9694,6 +11087,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -15636,7 +15982,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9704,6 +11098,7 @@ +@@ -9705,6 +11099,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -15644,7 +15990,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, -@@ -9725,6 +11120,7 @@ +@@ -9726,6 +11121,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -15652,7 +15998,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9736,6 +11132,7 @@ +@@ -9737,6 +11133,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -15660,7 +16006,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \ -@@ -9755,6 +11152,7 @@ +@@ -9756,6 +11153,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -15668,7 +16014,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9768,6 +11166,7 @@ +@@ -9769,6 +11167,7 @@ #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, @@ -15676,7 +16022,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9785,6 +11184,7 @@ +@@ -9786,6 +11185,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -15684,7 +16030,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9796,6 +11196,7 @@ +@@ -9797,6 +11197,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -15692,7 +16038,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, -@@ -9816,6 +11217,7 @@ +@@ -9817,6 +11218,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -15700,7 +16046,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9829,6 +11231,7 @@ +@@ -9830,6 +11232,7 @@ #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -15708,18 +16054,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9846,8 +11249,9 @@ +@@ -9847,8 +11250,9 @@ #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A -+#undef RS6000_BUILTIN_D - #undef RS6000_BUILTIN_E --#undef RS6000_BUILTIN_D +-#undef RS6000_BUILTIN_E + #undef RS6000_BUILTIN_D ++#undef RS6000_BUILTIN_E +#undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9861,6 +11265,7 @@ +@@ -9862,6 +11266,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -15727,7 +16073,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9871,17 +11276,49 @@ +@@ -9872,17 +11277,49 @@ #include "rs6000-builtin.def" }; @@ -15777,7 +16123,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Return true if a builtin function is overloaded. */ bool rs6000_overloaded_builtin_p (enum rs6000_builtins fncode) -@@ -10351,7 +11788,198 @@ +@@ -10352,6 +11789,197 @@ return NULL_RTX; } @@ -15829,7 +16175,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + +/* Expand the HTM builtin in EXP and store the result in TARGET. + Store true in *EXPANDEDP if we found a builtin to expand. */ - static rtx ++static rtx +htm_expand_builtin (tree exp, rtx target, bool * expandedp) +{ + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); @@ -15972,11 +16318,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + return NULL_RTX; +} + -+static rtx + static rtx rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target) { - rtx pat; -@@ -10427,7 +12055,28 @@ +@@ -10428,6 +12056,27 @@ return const0_rtx; } } @@ -15992,7 +16337,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + error ("argument 2 must be 0 or 1"); + return const0_rtx; + } - ++ + STRIP_NOPS (arg2); + if (TREE_CODE (arg2) != INTEGER_CST + || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 15)) @@ -16001,11 +16346,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + return const0_rtx; + } + } -+ + if (target == 0 || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) -@@ -11411,6 +13060,8 @@ +@@ -11412,6 +13061,8 @@ error ("Builtin function %s is only valid for the cell processor", name); else if ((fnmask & RS6000_BTM_VSX) != 0) error ("Builtin function %s requires the -mvsx option", name); @@ -16014,7 +16358,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ else if ((fnmask & RS6000_BTM_ALTIVEC) != 0) error ("Builtin function %s requires the -maltivec option", name); else if ((fnmask & RS6000_BTM_PAIRED) != 0) -@@ -11515,7 +13166,8 @@ +@@ -11516,7 +13167,8 @@ case ALTIVEC_BUILTIN_MASK_FOR_LOAD: case ALTIVEC_BUILTIN_MASK_FOR_STORE: { @@ -16024,22 +16368,21 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode = insn_data[icode].operand[1].mode; tree arg; -@@ -11590,7 +13242,14 @@ +@@ -11591,6 +13243,13 @@ if (success) return ret; } + if (TARGET_HTM) + { + ret = htm_expand_builtin (exp, target, &success); - ++ + if (success) + return ret; + } -+ + gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT); - /* Handle simple unary operations. */ -@@ -11772,6 +13431,9 @@ +@@ -11773,6 +13432,9 @@ spe_init_builtins (); if (TARGET_EXTRA_BUILTINS) altivec_init_builtins (); @@ -16049,7 +16392,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT) rs6000_common_init_builtins (); -@@ -12117,6 +13779,10 @@ +@@ -12118,6 +13780,10 @@ = build_function_type_list (integer_type_node, integer_type_node, V4SI_type_node, V4SI_type_node, NULL_TREE); @@ -16060,7 +16403,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ tree void_ftype_v4si = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); tree v8hi_ftype_void -@@ -12199,6 +13865,8 @@ +@@ -12200,6 +13866,8 @@ = build_function_type_list (integer_type_node, integer_type_node, V2DF_type_node, V2DF_type_node, NULL_TREE); @@ -16069,7 +16412,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ tree v4si_ftype_v4si = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); tree v8hi_ftype_v8hi -@@ -12334,6 +14002,9 @@ +@@ -12335,6 +14003,9 @@ case VOIDmode: type = int_ftype_int_opaque_opaque; break; @@ -16079,7 +16422,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ case V4SImode: type = int_ftype_int_v4si_v4si; break; -@@ -12367,6 +14038,9 @@ +@@ -12368,6 +14039,9 @@ switch (mode0) { @@ -16089,7 +16432,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ case V4SImode: type = v4si_ftype_v4si; break; -@@ -12499,6 +14173,79 @@ +@@ -12500,6 +14174,79 @@ def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI); } @@ -16169,7 +16512,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Hash function for builtin functions with up to 3 arguments and a return type. */ static unsigned -@@ -12572,11 +14319,27 @@ +@@ -12573,11 +14320,27 @@ are type correct. */ switch (builtin) { @@ -16197,7 +16540,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ h.uns_p[0] = 1; h.uns_p[1] = 1; h.uns_p[2] = 1; -@@ -12599,6 +14362,14 @@ +@@ -12600,6 +14363,14 @@ case VSX_BUILTIN_XXSEL_8HI_UNS: case VSX_BUILTIN_XXSEL_4SI_UNS: case VSX_BUILTIN_XXSEL_2DI_UNS: @@ -16212,7 +16555,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ h.uns_p[0] = 1; h.uns_p[1] = 1; h.uns_p[2] = 1; -@@ -12740,9 +14511,24 @@ +@@ -12741,8 +14512,23 @@ else { enum insn_code icode = d->icode; @@ -16223,7 +16566,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n", + (long unsigned)i); - ++ + continue; + } + @@ -16235,11 +16578,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + + continue; + } -+ + type = builtin_function_type (insn_data[icode].operand[0].mode, insn_data[icode].operand[1].mode, - insn_data[icode].operand[2].mode, -@@ -12780,9 +14566,24 @@ +@@ -12781,8 +14567,23 @@ else { enum insn_code icode = d->icode; @@ -16250,7 +16592,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n", + (long unsigned)i); - ++ + continue; + } + @@ -16262,11 +16604,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + + continue; + } -+ + mode0 = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; - mode2 = insn_data[icode].operand[2].mode; -@@ -12842,9 +14643,24 @@ +@@ -12843,8 +14644,23 @@ else { enum insn_code icode = d->icode; @@ -16277,7 +16618,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n", + (long unsigned)i); - ++ + continue; + } + @@ -16289,11 +16630,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + + continue; + } -+ + mode0 = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; - -@@ -13631,7 +15447,7 @@ +@@ -13632,7 +15448,7 @@ static bool eliminated = false; rtx ret; @@ -16302,7 +16642,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); else { -@@ -13690,31 +15506,228 @@ +@@ -13691,29 +15507,226 @@ return NULL_TREE; } @@ -16450,7 +16790,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + icode = reg_addr[mode].reload_vsx_gpr; + } + } - } ++ } + + if (TARGET_POWERPC64 && size == 16) + { @@ -16500,8 +16840,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + } + + return ret; - } - ++} ++ +/* Return whether a move between two register classes can be done either + directly (simple move) or via a pattern that uses a single extra temporary + (using power8's direct move in this case. */ @@ -16538,17 +16878,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + sri->extra_cost = 0; + } + return true; -+ } + } + + /* Now check if we can do it in a few steps. */ + return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri, + altivec_p); -+} -+ + } + /* Inform reload about cases where moving X with a mode MODE to a register in - RCLASS requires an extra scratch or immediate register. Return the class - needed for the immediate register. -@@ -13738,12 +15751,36 @@ +@@ -13739,11 +15752,35 @@ bool default_p = false; sri->icode = CODE_FOR_nothing; @@ -16561,7 +16899,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - icode = rs6000_vector_reload[mode][in_p != false]; - if (icode != CODE_FOR_nothing) + if (REG_P (x) || register_operand (x, mode)) - { ++ { + enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass]; + bool altivec_p = (rclass == ALTIVEC_REGS); + enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p); @@ -16585,11 +16923,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + + /* Handle vector moves with reload helper functions. */ + if (ret == ALL_REGS && icode != CODE_FOR_nothing) -+ { + { ret = NO_REGS; sri->icode = CODE_FOR_nothing; - sri->extra_cost = 0; -@@ -13754,22 +15791,43 @@ +@@ -13755,12 +15792,21 @@ /* Loads to and stores from gprs can do reg+offset, and wouldn't need an extra register in that case, but it would need an extra @@ -16604,19 +16941,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + if (TARGET_POWERPC64 && TARGET_QUAD_MEMORY + && GET_MODE_SIZE (mode) == 16 + && quad_memory_operand (x, mode)) - { - sri->icode = icode; ++ { ++ sri->icode = icode; + sri->extra_cost = 2; + } + + else if (!legitimate_indirect_address_p (addr, false) + && !rs6000_legitimate_offset_address_p (PTImode, addr, + false, true)) -+ { -+ sri->icode = icode; + { + sri->icode = icode; /* account for splitting the loads, and converting the - address from reg+reg to reg. */ - sri->extra_cost = (((TARGET_64BIT) ? 3 : 5) +@@ -13769,8 +15815,20 @@ + ((GET_CODE (addr) == AND) ? 1 : 0)); } } @@ -16639,7 +16975,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS || rclass == FLOAT_REGS || rclass == NO_REGS) { -@@ -13813,12 +15871,12 @@ +@@ -13814,12 +15872,12 @@ else { enum reg_class xclass = REGNO_REG_CLASS (regno); @@ -16655,7 +16991,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ default_p = true; else ret = NO_REGS; -@@ -13828,7 +15886,7 @@ +@@ -13829,7 +15887,7 @@ default_p = true; } else if (TARGET_POWERPC64 @@ -16664,7 +17000,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && MEM_P (x) && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD) { -@@ -13867,7 +15925,7 @@ +@@ -13868,7 +15926,7 @@ default_p = true; } else if (!TARGET_POWERPC64 @@ -16673,7 +17009,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && MEM_P (x) && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) { -@@ -13945,6 +16003,36 @@ +@@ -13946,6 +16004,36 @@ return ret; } @@ -16710,7 +17046,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset to SP+reg addressing. */ -@@ -13963,19 +16051,14 @@ +@@ -13964,19 +16052,14 @@ rtx cc_clobber; if (TARGET_DEBUG_ADDR) @@ -16725,19 +17061,19 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - debug_rtx (scratch); - } + rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p); - -- gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER); -- gcc_assert (GET_CODE (mem) == MEM); ++ + if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER) + rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p); + + if (GET_CODE (mem) != MEM) + rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p); -+ + +- gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER); +- gcc_assert (GET_CODE (mem) == MEM); rclass = REGNO_REG_CLASS (regno); addr = XEXP (mem, 0); -@@ -13994,19 +16077,24 @@ +@@ -13995,19 +16078,24 @@ if (GET_CODE (addr) == PRE_MODIFY) { scratch_or_premodify = XEXP (addr, 0); @@ -16766,7 +17102,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (!REG_P (addr_op2) && (GET_CODE (addr_op2) != CONST_INT -@@ -14034,7 +16122,7 @@ +@@ -14035,7 +16123,7 @@ scratch_or_premodify = scratch; } else if (!legitimate_indirect_address_p (addr, false) @@ -16775,7 +17111,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ false, true)) { if (TARGET_DEBUG_ADDR) -@@ -14050,9 +16138,21 @@ +@@ -14051,9 +16139,21 @@ } break; @@ -16799,7 +17135,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ case VSX_REGS: case ALTIVEC_REGS: -@@ -14072,36 +16172,38 @@ +@@ -14073,36 +16173,38 @@ /* If we aren't using a VSX load, save the PRE_MODIFY register and use it as the address later. */ if (GET_CODE (addr) == PRE_MODIFY @@ -16850,7 +17186,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (TARGET_DEBUG_ADDR) { -@@ -14120,7 +16222,8 @@ +@@ -14121,7 +16223,8 @@ } else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST @@ -16860,7 +17196,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { if (TARGET_DEBUG_ADDR) { -@@ -14136,12 +16239,12 @@ +@@ -14137,12 +16240,12 @@ } else @@ -16875,7 +17211,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* If the original address involved a pre-modify that we couldn't use the VSX -@@ -14188,7 +16291,7 @@ +@@ -14189,7 +16292,7 @@ /* Adjust the address if it changed. */ if (addr != XEXP (mem, 0)) { @@ -16884,7 +17220,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (TARGET_DEBUG_ADDR) fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n"); } -@@ -14253,8 +16356,10 @@ +@@ -14254,8 +16357,10 @@ return; } @@ -16897,7 +17233,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ static void rs6000_alloc_sdmode_stack_slot (void) -@@ -14265,6 +16370,9 @@ +@@ -14266,6 +16371,9 @@ gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX); @@ -16907,7 +17243,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ FOR_EACH_BB (bb) for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) { -@@ -14325,8 +16433,7 @@ +@@ -14326,8 +16434,7 @@ { enum machine_mode mode = GET_MODE (x); @@ -16917,7 +17253,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return rclass; if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) -@@ -14381,60 +16488,45 @@ +@@ -14382,42 +16489,25 @@ set and vice versa. */ static bool @@ -16929,10 +17265,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { - if (class1 == class2) - return false; -+ enum rs6000_reg_type from_type, to_type; -+ bool altivec_p = ((from_class == ALTIVEC_REGS) -+ || (to_class == ALTIVEC_REGS)); - +- - /* Under VSX, there are 3 register classes that values could be in (VSX_REGS, - ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy - between these classes. But we need memory for other things that can go in @@ -16943,25 +17276,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - || class1 == FLOAT_REGS)) - return (class2 != VSX_REGS && class2 != ALTIVEC_REGS - && class2 != FLOAT_REGS); -+ /* If a simple/direct move is available, we don't need secondary memory */ -+ from_type = reg_class_to_reg_type[(int)from_class]; -+ to_type = reg_class_to_reg_type[(int)to_class]; - +- - if (class1 == VSX_REGS || class2 == VSX_REGS) - return true; -+ if (rs6000_secondary_reload_move (to_type, from_type, mode, -+ (secondary_reload_info *)0, altivec_p)) -+ return false; - +- - if (class1 == FLOAT_REGS - && (!TARGET_MFPGPR || !TARGET_POWERPC64 - || ((mode != DFmode) - && (mode != DDmode) - && (mode != DImode)))) -+ /* If we have a floating point or vector register class, we need to use -+ memory to transfer the data. */ -+ if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type)) - return true; +- return true; ++ enum rs6000_reg_type from_type, to_type; ++ bool altivec_p = ((from_class == ALTIVEC_REGS) ++ || (to_class == ALTIVEC_REGS)); ++ ++ /* If a simple/direct move is available, we don't need secondary memory */ ++ from_type = reg_class_to_reg_type[(int)from_class]; ++ to_type = reg_class_to_reg_type[(int)to_class]; - if (class2 == FLOAT_REGS - && (!TARGET_MFPGPR || !TARGET_POWERPC64 @@ -16969,12 +17300,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - && (mode != DDmode) - && (mode != DImode)))) - return true; -- ++ if (rs6000_secondary_reload_move (to_type, from_type, mode, ++ (secondary_reload_info *)0, altivec_p)) ++ return false; + - if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS) -- return true; -- ++ /* If we have a floating point or vector register class, we need to use ++ memory to transfer the data. */ ++ if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type)) + return true; + return false; - } +@@ -14425,17 +16515,19 @@ /* Debug version of rs6000_secondary_memory_needed. */ static bool @@ -17001,7 +17338,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return ret; } -@@ -14501,12 +16593,18 @@ +@@ -14502,11 +16594,17 @@ return (mode != SDmode) ? NO_REGS : GENERAL_REGS; /* Memory, and FP/altivec registers can go into fp/altivec registers under @@ -17015,14 +17352,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + { + if (GET_MODE_SIZE (mode) < 16) + return FLOAT_REGS; - ++ + return NO_REGS; + } -+ + /* Memory, and AltiVec registers can go into AltiVec registers. */ if ((regno == -1 || ALTIVEC_REGNO_P (regno)) - && rclass == ALTIVEC_REGS) -@@ -14550,8 +16648,42 @@ +@@ -14551,8 +16649,42 @@ if (from_size != to_size) { enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS; @@ -17067,7 +17403,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } if (TARGET_E500_DOUBLE -@@ -14565,10 +16697,19 @@ +@@ -14566,9 +16698,18 @@ /* Since the VSX register set includes traditional floating point registers and altivec registers, just check for the size being different instead of trying to check whether the modes are vector modes. Otherwise it won't @@ -17082,19 +17418,22 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + if (hard_regno_nregs[FIRST_FPR_REGNO][to] > num_regs + || hard_regno_nregs[FIRST_FPR_REGNO][from] > num_regs) + return true; - ++ + return (from_size != 8 && from_size != 16); + } -+ + if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1) - return true; -@@ -14598,6 +16739,161 @@ +@@ -14599,45 +16740,200 @@ return ret; } +-/* Given a comparison operation, return the bit number in CCR to test. We +- know this is a valid comparison. +/* Return a string to do a move operation of 128 bits of data. */ -+ + +- SCC_P is 1 if this is for an scc. That means that %D will have been +- used instead of %C, so the bits will be in different places. +const char * +rs6000_output_move_128bit (rtx operands[]) +{ @@ -17105,7 +17444,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + int src_regno; + bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p; + bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p; -+ + +- Return -1 if OP isn't a valid comparison for some reason. */ + if (REG_P (dest)) + { + dest_regno = REGNO (dest); @@ -17119,7 +17459,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + dest_regno = -1; + dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false; + } -+ + +-int +-ccr_bit (rtx op, int scc_p) +-{ +- enum rtx_code code = GET_CODE (op); +- enum machine_mode cc_mode; +- int cc_regnum; +- int base_bit; +- rtx reg; + if (REG_P (src)) + { + src_regno = REGNO (src); @@ -17133,7 +17481,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + src_regno = -1; + src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false; + } -+ + +- if (!COMPARISON_P (op)) +- return -1; + /* Register moves. */ + if (dest_regno >= 0 && src_regno >= 0) + { @@ -17141,30 +17491,43 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + { + if (src_gpr_p) + return "#"; -+ + +- reg = XEXP (op, 0); + else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p) + return "#"; + } -+ + +- gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg))); + else if (TARGET_VSX && dest_vsx_p) + { + if (src_vsx_p) + return "xxlor %x0,%x1,%x1"; -+ + +- cc_mode = GET_MODE (reg); +- cc_regnum = REGNO (reg); +- base_bit = 4 * (cc_regnum - CR0_REGNO); + else if (TARGET_DIRECT_MOVE && src_gpr_p) + return "#"; + } -+ + +- validate_condition_mode (code, cc_mode); + else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p) + return "vor %0,%1,%1"; -+ + +- /* When generating a sCOND operation, only positive conditions are +- allowed. */ +- gcc_assert (!scc_p +- || code == EQ || code == GT || code == LT || code == UNORDERED +- || code == GTU || code == LTU); + else if (dest_fp_p && src_fp_p) + return "#"; + } -+ + +- switch (code) + /* Loads. */ + else if (dest_regno >= 0 && MEM_P (src)) -+ { + { +- case NE: + if (dest_gpr_p) + { + if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src)) @@ -17248,10 +17611,49 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +} + + - /* Given a comparison operation, return the bit number in CCR to test. We - know this is a valid comparison. - -@@ -14823,6 +17119,7 @@ ++/* Given a comparison operation, return the bit number in CCR to test. We ++ know this is a valid comparison. ++ ++ SCC_P is 1 if this is for an scc. That means that %D will have been ++ used instead of %C, so the bits will be in different places. ++ ++ Return -1 if OP isn't a valid comparison for some reason. */ ++ ++int ++ccr_bit (rtx op, int scc_p) ++{ ++ enum rtx_code code = GET_CODE (op); ++ enum machine_mode cc_mode; ++ int cc_regnum; ++ int base_bit; ++ rtx reg; ++ ++ if (!COMPARISON_P (op)) ++ return -1; ++ ++ reg = XEXP (op, 0); ++ ++ gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg))); ++ ++ cc_mode = GET_MODE (reg); ++ cc_regnum = REGNO (reg); ++ base_bit = 4 * (cc_regnum - CR0_REGNO); ++ ++ validate_condition_mode (code, cc_mode); ++ ++ /* When generating a sCOND operation, only positive conditions are ++ allowed. */ ++ gcc_assert (!scc_p ++ || code == EQ || code == GT || code == LT || code == UNORDERED ++ || code == GTU || code == LTU); ++ ++ switch (code) ++ { ++ case NE: + return scc_p ? base_bit + 3 : base_bit + 2; + case EQ: + return base_bit + 2; +@@ -14824,6 +17120,7 @@ ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); break; @@ -17259,7 +17661,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ case ABI_V4: case ABI_DARWIN: break; -@@ -15302,7 +17599,7 @@ +@@ -15303,7 +17600,7 @@ return; case 'Y': @@ -17268,7 +17670,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (REG_P (x)) fputs (reg_names[REGNO (x) + 2], file); else if (MEM_P (x)) -@@ -15352,7 +17649,7 @@ +@@ -15353,7 +17650,7 @@ return; case 'Z': @@ -17277,7 +17679,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (REG_P (x)) fputs (reg_names[REGNO (x) + 3], file); else if (MEM_P (x)) -@@ -15383,7 +17680,8 @@ +@@ -15384,7 +17681,8 @@ if ((TARGET_SPE || TARGET_E500_DOUBLE) && (GET_MODE_SIZE (GET_MODE (x)) == 8 || GET_MODE (x) == TFmode @@ -17287,7 +17689,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { /* Handle [reg]. */ if (REG_P (tmp)) -@@ -16766,7 +19064,8 @@ +@@ -16767,7 +19065,8 @@ } /* A subroutine of the atomic operation splitters. Emit a load-locked @@ -17297,7 +17699,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ static void emit_load_locked (enum machine_mode mode, rtx reg, rtx mem) -@@ -16775,12 +19074,26 @@ +@@ -16776,12 +19075,26 @@ switch (mode) { @@ -17325,7 +17727,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ default: gcc_unreachable (); } -@@ -16797,12 +19110,21 @@ +@@ -16798,12 +19111,21 @@ switch (mode) { @@ -17347,7 +17749,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ default: gcc_unreachable (); } -@@ -16949,7 +19271,7 @@ +@@ -16950,7 +19272,7 @@ { rtx boolval, retval, mem, oldval, newval, cond; rtx label1, label2, x, mask, shift; @@ -17356,7 +17758,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ enum memmodel mod_s, mod_f; bool is_weak; -@@ -16961,23 +19283,30 @@ +@@ -16962,22 +19284,29 @@ is_weak = (INTVAL (operands[5]) != 0); mod_s = (enum memmodel) INTVAL (operands[6]); mod_f = (enum memmodel) INTVAL (operands[7]); @@ -17383,7 +17785,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + if (!TARGET_SYNC_HI_QI) + { + mem = rs6000_adjust_atomic_subword (mem, &shift, &mask); - ++ + /* Shift and mask OLDVAL into position with the word. */ + oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift, + NULL_RTX, 1, OPTAB_LIB_WIDEN); @@ -17393,11 +17795,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + newval = expand_simple_binop (SImode, ASHIFT, newval, shift, + NULL_RTX, 1, OPTAB_LIB_WIDEN); + } -+ + /* Prepare to adjust the return value. */ retval = gen_reg_rtx (SImode); - mode = SImode; -@@ -17005,7 +19334,25 @@ +@@ -17006,7 +19335,25 @@ } cond = gen_reg_rtx (CCmode); @@ -17424,7 +17825,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ emit_insn (gen_rtx_SET (VOIDmode, cond, x)); x = gen_rtx_NE (VOIDmode, cond, const0_rtx); -@@ -17015,7 +19362,7 @@ +@@ -17016,7 +19363,7 @@ if (mask) x = rs6000_mask_atomic_subword (retval, newval, mask); @@ -17433,7 +17834,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (!is_weak) { -@@ -17033,6 +19380,8 @@ +@@ -17034,6 +19381,8 @@ if (shift) rs6000_finish_atomic_subword (operands[1], retval, shift); @@ -17442,7 +17843,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* In all cases, CR0 contains EQ on success, and NE on failure. */ x = gen_rtx_EQ (SImode, cond, const0_rtx); -@@ -17056,7 +19405,7 @@ +@@ -17057,7 +19406,7 @@ mode = GET_MODE (mem); mask = shift = NULL_RTX; @@ -17451,7 +17852,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { mem = rs6000_adjust_atomic_subword (mem, &shift, &mask); -@@ -17105,53 +19454,70 @@ +@@ -17106,53 +19455,70 @@ { enum memmodel model = (enum memmodel) INTVAL (model_rtx); enum machine_mode mode = GET_MODE (mem); @@ -17466,15 +17867,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (mode == QImode || mode == HImode) { - mem = rs6000_adjust_atomic_subword (mem, &shift, &mask); -+ if (TARGET_SYNC_HI_QI) -+ { -+ val = convert_modes (SImode, mode, val, 1); - +- - /* Shift and mask VAL into position with the word. */ - val = convert_modes (SImode, mode, val, 1); - val = expand_simple_binop (SImode, ASHIFT, val, shift, - NULL_RTX, 1, OPTAB_LIB_WIDEN); -- ++ if (TARGET_SYNC_HI_QI) ++ { ++ val = convert_modes (SImode, mode, val, 1); + - switch (code) + /* Prepare to adjust the return value. */ + before = gen_reg_rtx (SImode); @@ -17522,6 +17923,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - default: - gcc_unreachable (); +- } + case AND: + /* If we make certain that all of the other bits in VAL are + set, that will be sufficient to not affect other bits. */ @@ -17530,7 +17932,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + emit_insn (gen_rtx_SET (VOIDmode, val, x)); + mask = NULL; + break; -+ + +- /* Prepare to adjust the return value. */ +- before = gen_reg_rtx (SImode); +- if (after) +- after = gen_reg_rtx (SImode); +- mode = SImode; + case NOT: + case PLUS: + case MINUS: @@ -17547,17 +17954,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + if (after) + after = gen_reg_rtx (SImode); + store_mode = mode = SImode; - } -- -- /* Prepare to adjust the return value. */ -- before = gen_reg_rtx (SImode); -- if (after) -- after = gen_reg_rtx (SImode); -- mode = SImode; ++ } } mem = rs6000_pre_atomic_barrier (mem, model); -@@ -17184,9 +19550,11 @@ +@@ -17185,9 +19551,11 @@ NULL_RTX, 1, OPTAB_LIB_WIDEN); x = rs6000_mask_atomic_subword (before, x, mask); } @@ -17570,7 +17971,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ x = gen_rtx_NE (VOIDmode, cond, const0_rtx); emit_unlikely_jump (x, label); -@@ -17195,11 +19563,22 @@ +@@ -17196,11 +19564,22 @@ if (shift) { @@ -17593,7 +17994,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ else if (orig_after && after != orig_after) emit_move_insn (orig_after, after); } -@@ -17239,6 +19618,39 @@ +@@ -17240,6 +19619,39 @@ gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode)); @@ -17633,7 +18034,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) { /* Move register range backwards, if we might have destructive -@@ -17693,7 +20105,7 @@ +@@ -17694,7 +20106,7 @@ } else { @@ -17642,7 +18043,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (info->first_fp_reg_save > 61) strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; -@@ -17704,7 +20116,8 @@ +@@ -17705,7 +20117,8 @@ by the static chain. It would require too much fiddling and the static chain is rarely used anyway. FPRs are saved w.r.t the stack pointer on Darwin, and AIX uses r1 or r12. */ @@ -17652,12 +18053,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS) | SAVE_INLINE_GPRS | SAVE_INLINE_VRS | REST_INLINE_VRS); -@@ -17837,7 +20250,35 @@ +@@ -17838,6 +20251,34 @@ The required alignment for AIX configurations is two words (i.e., 8 or 16 bytes). + The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like: - ++ + SP----> +---------------------------------------+ + | Back chain to caller | 0 + +---------------------------------------+ @@ -17684,11 +18085,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F + +---------------------------------------+ + -+ + V.4 stack frames look like: - SP----> +---------------------------------------+ -@@ -17897,6 +20338,7 @@ +@@ -17898,6 +20339,7 @@ rs6000_stack_t *info_ptr = &stack_info; int reg_size = TARGET_32BIT ? 4 : 8; int ehrd_size; @@ -17696,7 +18096,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ int save_align; int first_gp; HOST_WIDE_INT non_fixed_size; -@@ -17990,6 +20432,18 @@ +@@ -17991,6 +20433,18 @@ else ehrd_size = 0; @@ -17715,7 +18115,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Determine various sizes. */ info_ptr->reg_size = reg_size; info_ptr->fixed_size = RS6000_SAVE_AREA; -@@ -18029,6 +20483,7 @@ +@@ -18030,6 +20484,7 @@ gcc_unreachable (); case ABI_AIX: @@ -17723,7 +18123,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ case ABI_DARWIN: info_ptr->fp_save_offset = - info_ptr->fp_size; info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; -@@ -18058,6 +20513,8 @@ +@@ -18059,6 +20514,8 @@ } else info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; @@ -17732,7 +18132,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ info_ptr->lr_save_offset = 2*reg_size; break; -@@ -18120,6 +20577,7 @@ +@@ -18121,6 +20578,7 @@ + info_ptr->spe_gp_size + info_ptr->spe_padding_size + ehrd_size @@ -17740,7 +18140,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + info_ptr->cr_size + info_ptr->vrsave_size, save_align); -@@ -18133,7 +20591,7 @@ +@@ -18134,7 +20592,7 @@ /* Determine if we need to save the link register. */ if (info_ptr->calls_p @@ -17749,7 +18149,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && crtl->profile && !TARGET_PROFILE_KERNEL) || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca) -@@ -18279,6 +20737,7 @@ +@@ -18280,6 +20738,7 @@ default: abi_string = "Unknown"; break; case ABI_NONE: abi_string = "NONE"; break; case ABI_AIX: abi_string = "AIX"; break; @@ -17757,7 +18157,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ case ABI_DARWIN: abi_string = "Darwin"; break; case ABI_V4: abi_string = "V.4"; break; } -@@ -18400,7 +20859,8 @@ +@@ -18401,7 +20860,8 @@ /* Currently we don't optimize very well between prolog and body code and for PIC code the code can be actually quite bad, so don't try to be too clever here. */ @@ -17767,7 +18167,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { cfun->machine->ra_needs_full_frame = 1; -@@ -18459,13 +20919,13 @@ +@@ -18460,13 +20920,13 @@ return false; } @@ -17786,7 +18186,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && decl && !DECL_EXTERNAL (decl) && (*targetm.binds_local_p) (decl)) -@@ -18566,7 +21026,7 @@ +@@ -18567,7 +21027,7 @@ rtx dest; dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); @@ -17795,7 +18195,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { char buf[30]; rtx lab, tmp1, tmp2, got; -@@ -18594,7 +21054,7 @@ +@@ -18595,7 +21055,7 @@ emit_insn (gen_load_toc_v4_pic_si ()); emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO)); } @@ -17804,7 +18204,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { char buf[30]; rtx temp0 = (fromprolog -@@ -18642,7 +21102,7 @@ +@@ -18643,7 +21103,7 @@ } else { @@ -17813,7 +18213,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (TARGET_32BIT) emit_insn (gen_load_toc_aix_si (dest)); -@@ -19047,7 +21507,7 @@ +@@ -19048,7 +21508,7 @@ static rtx rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, @@ -17822,7 +18222,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { rtx real, temp; -@@ -19138,6 +21598,11 @@ +@@ -19139,6 +21599,11 @@ } } @@ -17834,7 +18234,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ RTX_FRAME_RELATED_P (insn) = 1; add_reg_note (insn, REG_FRAME_RELATED_EXPR, real); -@@ -19245,7 +21710,7 @@ +@@ -19246,7 +21711,7 @@ reg = gen_rtx_REG (mode, regno); insn = emit_insn (gen_frame_store (reg, frame_reg, offset)); return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp, @@ -17843,7 +18243,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* Emit an offset memory reference suitable for a frame store, while -@@ -19361,7 +21826,7 @@ +@@ -19362,7 +21827,7 @@ if ((sel & SAVRES_LR)) suffix = "_x"; } @@ -17852,7 +18252,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD) /* No out-of-line save/restore routines for GPRs on AIX. */ -@@ -19502,7 +21967,7 @@ +@@ -19503,7 +21968,7 @@ static inline unsigned ptr_regno_for_savres (int sel) { @@ -17861,7 +18261,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12; return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11; } -@@ -19587,6 +22052,43 @@ +@@ -19588,6 +22053,43 @@ return insn; } @@ -17905,7 +18305,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Determine whether the gp REG is really used. */ static bool -@@ -19652,6 +22154,17 @@ +@@ -19653,6 +22155,17 @@ #define NOT_INUSE(R) do {} while (0) #endif @@ -17923,7 +18323,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (flag_stack_usage_info) current_function_static_stack_size = info->total_size; -@@ -19766,7 +22279,7 @@ +@@ -19767,7 +22280,7 @@ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, @@ -17932,7 +18332,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ sp_off = frame_off = info->total_size; } -@@ -19851,14 +22364,14 @@ +@@ -19852,14 +22365,14 @@ insn = emit_move_insn (mem, reg); rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, @@ -17949,7 +18349,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && !(strategy & (SAVE_INLINE_GPRS | SAVE_NOINLINE_GPRS_SAVES_LR)) ? 11 : 12); -@@ -19867,21 +22380,9 @@ +@@ -19868,21 +22381,9 @@ && REGNO (frame_reg_rtx) != cr_save_regno && !(using_static_chain_p && cr_save_regno == 11)) { @@ -17972,7 +18372,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* Do any required saving of fpr's. If only one or two to save, do -@@ -19919,7 +22420,7 @@ +@@ -19920,7 +22421,7 @@ info->lr_save_offset, DFmode, sel); rs6000_frame_related (insn, ptr_reg, sp_off, @@ -17981,7 +18381,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (lr) END_USE (0); } -@@ -19998,7 +22499,7 @@ +@@ -19999,7 +22500,7 @@ SAVRES_SAVE | SAVRES_GPR); rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off, @@ -17990,7 +18390,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* Move the static chain pointer back. */ -@@ -20048,7 +22549,7 @@ +@@ -20049,7 +22550,7 @@ info->lr_save_offset + ptr_off, reg_mode, sel); rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off, @@ -17999,7 +18399,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (lr) END_USE (0); } -@@ -20064,7 +22565,7 @@ +@@ -20065,7 +22566,7 @@ info->gp_save_offset + frame_off + reg_size * i); insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, @@ -18008,7 +18408,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } else if (!WORLD_SAVE_P (info)) { -@@ -20133,7 +22634,8 @@ +@@ -20134,7 +22635,8 @@ be updated if we arrived at this function via a plt call or toc adjusting stub. */ emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg)); @@ -18018,7 +18418,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode); emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi)); compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO); -@@ -20152,7 +22654,7 @@ +@@ -20153,7 +22655,7 @@ LABEL_NUSES (toc_save_done) += 1; save_insn = emit_frame_save (frame_reg_rtx, reg_mode, @@ -18027,7 +18427,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ sp_off - frame_off); emit_label (toc_save_done); -@@ -20192,28 +22694,123 @@ +@@ -20193,26 +22695,121 @@ rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (info->cr_save_offset + frame_off)); rtx mem = gen_frame_mem (SImode, addr); @@ -18124,8 +18524,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + gen_rtx_REG (SImode, CR2_REGNO)); + add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); + } - } - ++ } ++ + /* In the ELFv2 ABI we need to save all call-saved CR fields into + *separate* slots if the routine calls __builtin_eh_return, so + that they can be independently restored by the unwinder. */ @@ -18157,12 +18557,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + + cr_off += reg_size; + } -+ } -+ + } + /* Update stack and set back pointer unless this is V.4, - for which it was done previously. */ - if (!WORLD_SAVE_P (info) && info->push_p -@@ -20291,7 +22888,7 @@ +@@ -20292,7 +22889,7 @@ info->altivec_save_offset + ptr_off, 0, V4SImode, SAVRES_SAVE | SAVRES_VR); rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off, @@ -18171,7 +18569,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (REGNO (frame_reg_rtx) == REGNO (scratch_reg)) { /* The oddity mentioned above clobbered our frame reg. */ -@@ -20307,7 +22904,7 @@ +@@ -20308,7 +22905,7 @@ for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) { @@ -18180,7 +18578,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ int offset; offset = (info->altivec_save_offset + frame_off -@@ -20325,8 +22922,18 @@ +@@ -20326,8 +22923,18 @@ insn = emit_move_insn (mem, savereg); @@ -18200,7 +18598,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } } -@@ -20350,7 +22957,8 @@ +@@ -20351,7 +22958,8 @@ be using r12 as frame_reg_rtx and r11 as the static chain pointer for nested functions. */ save_regno = 12; @@ -18210,7 +18608,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ save_regno = 11; else if (REGNO (frame_reg_rtx) == 12) { -@@ -20389,7 +22997,7 @@ +@@ -20390,7 +22998,7 @@ can use register 0. This allows us to use a plain 'blr' to return from the procedure more often. */ int save_LR_around_toc_setup = (TARGET_ELF @@ -18219,7 +18617,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && flag_pic && ! info->lr_save_p && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); -@@ -20451,7 +23059,7 @@ +@@ -20452,7 +23060,7 @@ if (rs6000_save_toc_in_prologue_p ()) { rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM); @@ -18228,7 +18626,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } } -@@ -20492,6 +23100,49 @@ +@@ -20493,6 +23101,49 @@ } } @@ -18278,7 +18676,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ rs6000_pic_labelno++; } -@@ -20544,6 +23195,7 @@ +@@ -20545,6 +23196,7 @@ if (using_mfcr_multiple && count > 1) { @@ -18286,7 +18684,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ rtvec p; int ndx; -@@ -20561,16 +23213,43 @@ +@@ -20562,19 +23214,46 @@ gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); ndx++; } @@ -18316,6 +18714,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (gen_rtx_REG (CCmode, CR0_REGNO + i), reg)); - if (!exit_func && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)) +- { +- rtx insn = get_last_insn (); +- rtx cr = gen_rtx_REG (SImode, CR2_REGNO); + /* For the ELFv2 ABI we generate a CFA_RESTORE for each + CR field separately, attached to the insn that in fact + restores this particular CR field. */ @@ -18331,10 +18732,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */ + if (!exit_func && DEFAULT_ABI != ABI_ELFv2 + && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)) - { - rtx insn = get_last_insn (); - rtx cr = gen_rtx_REG (SImode, CR2_REGNO); -@@ -20611,10 +23290,22 @@ ++ { ++ rtx insn = get_last_insn (); ++ rtx cr = gen_rtx_REG (SImode, CR2_REGNO); + + add_reg_note (insn, REG_CFA_RESTORE, cr); + RTX_FRAME_RELATED_P (insn) = 1; +@@ -20612,10 +23291,22 @@ static rtx add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores) { @@ -18358,7 +18762,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (info->lr_save_p) cfa_restores = alloc_reg_note (REG_CFA_RESTORE, gen_rtx_REG (Pmode, LR_REGNO), -@@ -21112,6 +23803,35 @@ +@@ -21113,6 +23804,35 @@ || (!restoring_GPRs_inline && info->first_fp_reg_save == 64)); @@ -18394,7 +18798,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Get the old lr if we saved it. If we are restoring registers out-of-line, then the out-of-line routines can do this for us. */ if (restore_lr && restoring_GPRs_inline) -@@ -21155,7 +23875,7 @@ +@@ -21156,7 +23876,7 @@ { rtx reg = gen_rtx_REG (reg_mode, 2); emit_insn (gen_frame_load (reg, frame_reg_rtx, @@ -18403,7 +18807,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } for (i = 0; ; ++i) -@@ -21441,6 +24161,7 @@ +@@ -21442,6 +24162,7 @@ if (! restoring_FPRs_inline) { int i; @@ -18411,7 +18815,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ rtx sym; if (flag_shrink_wrap) -@@ -21449,10 +24170,9 @@ +@@ -21450,10 +24171,9 @@ sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0)); RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym); @@ -18425,7 +18829,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ for (i = 0; i < 64 - info->first_fp_reg_save; i++) { rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); -@@ -21530,7 +24250,8 @@ +@@ -21531,7 +24251,8 @@ System V.4 Powerpc's (and the embedded ABI derived from it) use a different traceback table. */ @@ -18435,7 +18839,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && rs6000_traceback != traceback_none && !cfun->is_thunk) { const char *fname = NULL; -@@ -21858,6 +24579,12 @@ +@@ -21860,6 +24581,12 @@ SIBLING_CALL_P (insn) = 1; emit_barrier (); @@ -18448,7 +18852,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Run just enough of rest_of_compilation to get the insns emitted. There's not really enough bulk here to make other passes such as instruction scheduling worth while. Note that use_thunk calls -@@ -22554,7 +25281,7 @@ +@@ -22556,7 +25283,7 @@ if (TARGET_PROFILE_KERNEL) return; @@ -18457,7 +18861,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { #ifndef NO_PROFILE_COUNTERS # define NO_PROFILE_COUNTERS 0 -@@ -22698,29 +25425,9 @@ +@@ -22700,29 +25427,9 @@ break; case ABI_AIX: @@ -18489,7 +18893,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ break; } } -@@ -22846,6 +25553,7 @@ +@@ -22848,6 +25555,7 @@ || rs6000_cpu_attr == CPU_POWER4 || rs6000_cpu_attr == CPU_POWER5 || rs6000_cpu_attr == CPU_POWER7 @@ -18497,7 +18901,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ || rs6000_cpu_attr == CPU_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) -@@ -23128,7 +25836,8 @@ +@@ -23130,7 +25838,8 @@ if (rs6000_cpu_attr == CPU_CELL) return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS; @@ -18507,7 +18911,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { enum attr_type type = get_attr_type (insn); if (type == TYPE_LOAD_EXT_U -@@ -23153,7 +25862,8 @@ +@@ -23155,7 +25864,8 @@ || GET_CODE (PATTERN (insn)) == CLOBBER) return false; @@ -18517,7 +18921,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { enum attr_type type = get_attr_type (insn); if (type == TYPE_LOAD_U || type == TYPE_STORE_U -@@ -23432,6 +26142,8 @@ +@@ -23434,6 +26144,8 @@ case CPU_POWER6: case CPU_POWER7: return 5; @@ -18526,7 +18930,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ default: return 1; } -@@ -24059,6 +26771,39 @@ +@@ -24061,6 +26773,39 @@ break; } break; @@ -18566,7 +18970,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ default: break; } -@@ -24137,6 +26882,25 @@ +@@ -24139,6 +26884,25 @@ break; } break; @@ -18592,7 +18996,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ default: break; } -@@ -24226,8 +26990,9 @@ +@@ -24228,8 +26992,9 @@ if (can_issue_more && !is_branch_slot_insn (next_insn)) can_issue_more--; @@ -18604,7 +19008,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { nop = gen_group_ending_nop (); emit_insn_before (nop, next_insn); -@@ -24598,6 +27363,11 @@ +@@ -24600,6 +27365,11 @@ ret = (TARGET_32BIT) ? 12 : 24; break; @@ -18616,7 +19020,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ case ABI_DARWIN: case ABI_V4: ret = (TARGET_32BIT) ? 40 : 48; -@@ -24653,6 +27423,7 @@ +@@ -24655,6 +27425,7 @@ break; /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ @@ -18624,7 +19028,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ case ABI_DARWIN: case ABI_V4: emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"), -@@ -24947,7 +27718,7 @@ +@@ -24949,7 +27720,7 @@ static void rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED) { @@ -18633,7 +19037,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && TARGET_MINIMAL_TOC && !TARGET_RELOCATABLE) { -@@ -24968,7 +27739,8 @@ +@@ -24970,7 +27741,8 @@ else fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); } @@ -18643,7 +19047,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP); else { -@@ -25518,7 +28290,7 @@ +@@ -25520,7 +28292,7 @@ { if (flag_pic) return 3; @@ -18652,7 +19056,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return 2; else return 0; -@@ -25594,7 +28366,7 @@ +@@ -25596,7 +28368,7 @@ void rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) { @@ -18661,7 +19065,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); ASM_OUTPUT_LABEL (file, name); -@@ -25660,8 +28432,7 @@ +@@ -25662,8 +28434,7 @@ fprintf (file, "%s:\n", desc_name); fprintf (file, "\t.long %s\n", orig_name); fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); @@ -18671,7 +19075,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ fprintf (file, "\t.previous\n"); } ASM_OUTPUT_LABEL (file, name); -@@ -25690,7 +28461,7 @@ +@@ -25692,7 +28463,7 @@ } #endif #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD) @@ -18680,7 +19084,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ file_end_indicate_exec_stack (); #endif } -@@ -26430,7 +29201,8 @@ +@@ -26432,7 +29203,8 @@ /* For those processors that have slow LR/CTR moves, make them more expensive than memory in order to bias spills to memory .*/ else if ((rs6000_cpu == PROCESSOR_POWER6 @@ -18690,7 +19094,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS)) ret = 6 * hard_regno_nregs[0][mode]; -@@ -26440,7 +29212,7 @@ +@@ -26442,7 +29214,7 @@ } /* If we have VSX, we can easily move between FPR or Altivec registers. */ @@ -18699,7 +19103,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ && reg_classes_intersect_p (to, VSX_REGS) && reg_classes_intersect_p (from, VSX_REGS)) ret = 2 * hard_regno_nregs[32][mode]; -@@ -26481,7 +29253,8 @@ +@@ -26483,7 +29255,8 @@ if (reg_classes_intersect_p (rclass, GENERAL_REGS)) ret = 4 * hard_regno_nregs[0][mode]; @@ -18709,7 +19113,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ ret = 4 * hard_regno_nregs[32][mode]; else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS)) ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode]; -@@ -26643,54 +29416,26 @@ +@@ -26645,54 +29418,26 @@ emit_insn (gen_rtx_SET (VOIDmode, dst, r)); } @@ -18731,19 +19135,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - enum insn_code code = optab_handler (smul_optab, mode); - insn_gen_fn gen_mul = GEN_FCN (code); - rtx one = rs6000_load_constant_and_splat (mode, dconst1); -+ rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v; -+ int i; - +- - gcc_assert (code != CODE_FOR_nothing); -+ /* Low precision estimates guarantee 5 bits of accuracy. High -+ precision estimates guarantee 14 bits of accuracy. SFmode -+ requires 23 bits of accuracy. DFmode requires 52 bits of -+ accuracy. Each pass at least doubles the accuracy, leading -+ to the following. */ -+ int passes = (TARGET_RECIP_PRECISION) ? 1 : 3; -+ if (mode == DFmode || mode == V2DFmode) -+ passes++; - +- - /* x0 = 1./d estimate */ - x0 = gen_reg_rtx (mode); - emit_insn (gen_rtx_SET (VOIDmode, x0, @@ -18767,10 +19161,20 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - - rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */ -} -- ++ rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v; ++ int i; + -/* Newton-Raphson approximation of floating point divide that has a low - precision estimate. Assumes no trapping math and finite arguments. */ -- ++ /* Low precision estimates guarantee 5 bits of accuracy. High ++ precision estimates guarantee 14 bits of accuracy. SFmode ++ requires 23 bits of accuracy. DFmode requires 52 bits of ++ accuracy. Each pass at least doubles the accuracy, leading ++ to the following. */ ++ int passes = (TARGET_RECIP_PRECISION) ? 1 : 3; ++ if (mode == DFmode || mode == V2DFmode) ++ passes++; + -static void -rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d) -{ @@ -18779,7 +19183,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ enum insn_code code = optab_handler (smul_optab, mode); insn_gen_fn gen_mul = GEN_FCN (code); -@@ -26704,47 +29449,45 @@ +@@ -26706,46 +29451,44 @@ gen_rtx_UNSPEC (mode, gen_rtvec (1, d), UNSPEC_FRES))); @@ -18793,15 +19197,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + /* e0 = 1. - d * x0 */ + e0 = gen_reg_rtx (mode); + rs6000_emit_nmsub (e0, d, x0, one); - -- e1 = gen_reg_rtx (mode); -- emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */ ++ + /* x1 = x0 + e0 * x0 */ + x1 = gen_reg_rtx (mode); + rs6000_emit_madd (x1, e0, x0, x0); -- y2 = gen_reg_rtx (mode); -- rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */ +- e1 = gen_reg_rtx (mode); +- emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */ + for (i = 0, xprev = x1, eprev = e0; i < passes - 2; + ++i, xprev = xnext, eprev = enext) { + @@ -18809,40 +19211,41 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + enext = gen_reg_rtx (mode); + emit_insn (gen_mul (enext, eprev, eprev)); -- e2 = gen_reg_rtx (mode); -- emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */ +- y2 = gen_reg_rtx (mode); +- rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */ + /* xnext = xprev + enext * xprev */ + xnext = gen_reg_rtx (mode); + rs6000_emit_madd (xnext, enext, xprev, xprev); + } -- y3 = gen_reg_rtx (mode); -- rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */ +- e2 = gen_reg_rtx (mode); +- emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */ + } else + xprev = x0; -- u0 = gen_reg_rtx (mode); -- emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */ +- y3 = gen_reg_rtx (mode); +- rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */ + /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */ -- v0 = gen_reg_rtx (mode); -- rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */ +- u0 = gen_reg_rtx (mode); +- emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */ + /* u = n * xprev */ + u = gen_reg_rtx (mode); + emit_insn (gen_mul (u, n, xprev)); -- rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */ --} +- v0 = gen_reg_rtx (mode); +- rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */ + /* v = n - (d * u) */ + v = gen_reg_rtx (mode); + rs6000_emit_nmsub (v, d, u, n); +- rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */ +-} +- -/* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P, - add a reg_note saying that this was a division. Support both scalar and - vector divide. Assumes no trapping math and finite arguments. */ -+ /* dst = (v * xprev) + u */ -+ rs6000_emit_madd (dst, v, xprev, u); - +- -void -rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p) -{ @@ -18852,11 +19255,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - rs6000_emit_swdiv_high_precision (dst, n, d); - else - rs6000_emit_swdiv_low_precision (dst, n, d); -- ++ /* dst = (v * xprev) + u */ ++ rs6000_emit_madd (dst, v, xprev, u); + if (note_p) add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d)); - } -@@ -26758,7 +29501,16 @@ +@@ -26760,7 +29503,16 @@ enum machine_mode mode = GET_MODE (src); rtx x0 = gen_reg_rtx (mode); rtx y = gen_reg_rtx (mode); @@ -18874,7 +19278,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ REAL_VALUE_TYPE dconst3_2; int i; rtx halfthree; -@@ -26920,6 +29672,136 @@ +@@ -26922,6 +29674,136 @@ } } @@ -19011,7 +19415,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Expand an Altivec constant permutation. Return true if we match an efficient implementation; false to fall back to VPERM. */ -@@ -26927,26 +29809,37 @@ +@@ -26929,26 +29811,37 @@ altivec_expand_vec_perm_const (rtx operands[4]) { struct altivec_perm_insn { @@ -19058,7 +19462,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ }; unsigned int i, j, elt, which; -@@ -27003,6 +29896,8 @@ +@@ -27005,6 +29898,8 @@ break; if (i == 16) { @@ -19067,7 +19471,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt))); return true; } -@@ -27014,9 +29909,10 @@ +@@ -27016,9 +29911,10 @@ break; if (i == 16) { @@ -19079,7 +19483,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ emit_move_insn (target, gen_lowpart (V16QImode, x)); return true; } -@@ -27032,9 +29928,10 @@ +@@ -27034,9 +29930,10 @@ break; if (i == 16) { @@ -19091,7 +19495,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ emit_move_insn (target, gen_lowpart (V16QImode, x)); return true; } -@@ -27046,6 +29943,9 @@ +@@ -27048,6 +29945,9 @@ { bool swapped; @@ -19101,7 +19505,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ elt = patterns[j].perm[0]; if (perm[0] == elt) swapped = false; -@@ -27069,7 +29969,30 @@ +@@ -27071,7 +29971,30 @@ enum machine_mode omode = insn_data[icode].operand[0].mode; enum machine_mode imode = insn_data[icode].operand[1].mode; @@ -19133,7 +19537,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ x = op0, op0 = op1, op1 = x; if (imode != V16QImode) { -@@ -27087,6 +30010,12 @@ +@@ -27089,6 +30012,12 @@ } } @@ -19146,7 +19550,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return false; } -@@ -27136,6 +30065,21 @@ +@@ -27138,6 +30067,21 @@ gcc_assert (GET_MODE_NUNITS (vmode) == 2); dmode = mode_for_vector (GET_MODE_INNER (vmode), 4); @@ -19168,7 +19572,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ x = gen_rtx_VEC_CONCAT (dmode, op0, op1); v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1)); x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v)); -@@ -27231,7 +30175,7 @@ +@@ -27233,7 +30177,7 @@ unsigned i, high, nelt = GET_MODE_NUNITS (vmode); rtx perm[16]; @@ -19177,7 +19581,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ for (i = 0; i < nelt / 2; i++) { perm[i * 2] = GEN_INT (i + high); -@@ -27286,6 +30230,8 @@ +@@ -27288,6 +30232,8 @@ { enum machine_mode mode; unsigned int regno; @@ -19186,7 +19590,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Special handling for structs in darwin64. */ if (TARGET_MACHO -@@ -27305,6 +30251,36 @@ +@@ -27307,6 +30253,36 @@ /* Otherwise fall through to standard ABI rules. */ } @@ -19223,7 +19627,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) { /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ -@@ -27679,22 +30655,32 @@ +@@ -27681,22 +30657,32 @@ { { "altivec", OPTION_MASK_ALTIVEC, false, true }, { "cmpb", OPTION_MASK_CMPB, false, true }, @@ -19257,7 +19661,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS { "aix64", OPTION_MASK_64BIT, false, false }, -@@ -27734,6 +30720,9 @@ +@@ -27736,6 +30722,9 @@ { "frsqrtes", RS6000_BTM_FRSQRTES, false, false }, { "popcntd", RS6000_BTM_POPCNTD, false, false }, { "cell", RS6000_BTM_CELL, false, false }, @@ -19267,7 +19671,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ }; /* Option variables that we want to support inside attribute((target)) and -@@ -28250,7 +31239,6 @@ +@@ -28252,7 +31241,6 @@ size_t cur_column; size_t max_column = 76; const char *comma = ""; @@ -19275,7 +19679,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ if (indent) start_column += fprintf (file, "%*s", indent, ""); -@@ -28281,7 +31269,6 @@ +@@ -28283,7 +31271,6 @@ fprintf (stderr, ", \\\n%*s", (int)start_column, ""); cur_column = start_column + len; comma = ""; @@ -19283,7 +19687,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } fprintf (file, "%s%s%s%s", comma, prefix, no_str, -@@ -28291,7 +31278,7 @@ +@@ -28293,7 +31280,7 @@ } } @@ -19292,7 +19696,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* Helper function to print the current isa options on a line. */ -@@ -28467,118 +31454,149 @@ +@@ -28469,118 +31456,149 @@ } @@ -19301,9 +19705,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - pointer to its TOC, and whose third word contains a value to place in the - static chain register (r11). Note that if we load the static chain, our - "trampoline" need not have any executable code. */ - -+/* Expand code to perform a call under the AIX or ELFv2 ABI. */ + ++/* Expand code to perform a call under the AIX or ELFv2 ABI. */ + void -rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag) +rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie) @@ -19327,18 +19731,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ rtx insn; - rtx (*call_func) (rtx, rtx, rtx, rtx); - rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx); - +- - stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); - toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM); -+ /* Handle longcall attributes. */ -+ if (INTVAL (cookie) & CALL_LONG) -+ func_desc = rs6000_longcall_ref (func_desc); - /* Load up address of the actual function. */ - func_desc = force_reg (Pmode, func_desc); - func_addr = gen_reg_rtx (Pmode); - emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc)); -- ++ /* Handle longcall attributes. */ ++ if (INTVAL (cookie) & CALL_LONG) ++ func_desc = rs6000_longcall_ref (func_desc); + - if (TARGET_32BIT) + /* Handle indirect calls. */ + if (GET_CODE (func_desc) != SYMBOL_REF @@ -19415,6 +19819,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - gcc_assert (cfun); - gcc_assert (cfun->machine); +- +- /* Can we optimize saving the TOC in the prologue or do we need to do it at +- every call? */ +- if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca) +- cfun->machine->save_toc_in_prologue = true; + /* Prepare to load the TOC of the called function. Note that the + TOC load must happen immediately before the actual call so + that unwinding the TOC registers works correctly. See the @@ -19425,11 +19834,6 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + func_toc_offset)); + toc_load = gen_rtx_USE (VOIDmode, func_toc_mem); -- /* Can we optimize saving the TOC in the prologue or do we need to do it at -- every call? */ -- if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca) -- cfun->machine->save_toc_in_prologue = true; -- + /* If we have a static chain, load it up. */ + if (TARGET_POINTERS_TO_NESTED_FUNCTIONS) + { @@ -19483,9 +19887,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - } + call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO)); +- /* Create the call. */ +- if (value) +- insn = call_value_func (value, func_addr, flag, func_toc_mem, +- stack_toc_mem); +- else +- insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem); + insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call)); + insn = emit_call_insn (insn); -+ + +- emit_call_insn (insn); + /* Mention all registers defined by the ABI to hold information + as uses in CALL_INSN_FUNCTION_USAGE. */ + if (abi_reg) @@ -19502,17 +19913,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + + gcc_assert (INTVAL (cookie) == 0); + - /* Create the call. */ -- if (value) -- insn = call_value_func (value, func_addr, flag, func_toc_mem, -- stack_toc_mem); -- else -- insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem); ++ /* Create the call. */ + call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag); + if (value != NULL_RTX) + call[0] = gen_rtx_SET (VOIDmode, value, call[0]); - -- emit_call_insn (insn); ++ + call[1] = simple_return_rtx; + + insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call)); @@ -19526,7 +19931,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* Return whether we need to always update the saved TOC pointer when we update -@@ -28679,6 +31697,656 @@ +@@ -28681,6 +31699,656 @@ add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); } @@ -20183,6 +20588,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-rs6000.h" +Index: b/src/gcc/config/rs6000/vsx.md +=================================================================== --- a/src/gcc/config/rs6000/vsx.md +++ b/src/gcc/config/rs6000/vsx.md @@ -40,6 +40,14 @@ @@ -20939,7 +21346,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) -@@ -528,27 +851,11 @@ +@@ -528,26 +851,10 @@ [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) @@ -20947,11 +21354,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -;; fma, which allows the target to be a separate register from the 3 inputs. -;; Under VSX, the target must be either the addend or the first multiply. -;; Where we can, also do the same for the Altivec V4SF fmas. -+;; Fused vector multiply/add instructions. Support the classical Altivec -+;; versions of fma, which allows the target to be a separate register from the -+;; 3 inputs. Under VSX, the target must be either the addend or the first -+;; multiply. - +- -(define_insn "*vsx_fmadf4" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d") - (fma:DF @@ -20967,10 +21370,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - fmadd %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_d")]) -- ++;; Fused vector multiply/add instructions. Support the classical Altivec ++;; versions of fma, which allows the target to be a separate register from the ++;; 3 inputs. Under VSX, the target must be either the addend or the first ++;; multiply. + (define_insn "*vsx_fmav4sf4" [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,v") - (fma:V4SF @@ -578,23 +885,6 @@ xvmaddmdp %x0,%x1,%x3" [(set_attr "type" "vecdouble")]) @@ -21278,8 +21684,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + else + return "xxpermdi %x0,%x2,%x1,0"; +} - [(set_attr "type" "vecperm")]) - ++ [(set_attr "type" "vecperm")]) ++ +;; xxpermdi for little endian loads and stores. We need several of +;; these since the form of the PARALLEL differs by mode. +(define_insn "*vsx_xxpermdi2_le_<mode>" @@ -21289,8 +21695,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (parallel [(const_int 1) (const_int 0)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" + "xxpermdi %x0,%x1,%x1,2" -+ [(set_attr "type" "vecperm")]) -+ + [(set_attr "type" "vecperm")]) + +(define_insn "*vsx_xxpermdi4_le_<mode>" + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + (vec_select:VSX_W @@ -21457,7 +21863,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ return \"xxpermdi %x0,%x1,%x1,%3\"; } [(set_attr "type" "vecperm")]) -@@ -1149,9 +1533,28 @@ +@@ -1149,7 +1533,26 @@ (parallel [(const_int 0)])))] "VECTOR_MEM_VSX_P (<MODE>mode) && WORDS_BIG_ENDIAN" "lxsd%U1x %x0,%y1" @@ -21467,8 +21873,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (const_string "fpload"))) - (set_attr "length" "4")]) - ++ (set_attr "length" "4")]) ++ +;; Optimize extracting element 1 from memory for little endian +(define_insn "*vsx_extract_<mode>_one_le" + [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=ws,d,?wa") @@ -21482,11 +21888,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (const_string "fpload"))) -+ (set_attr "length" "4")]) -+ + (set_attr "length" "4")]) + ;; Extract a SF element from V4SF - (define_insn_and_split "vsx_extract_v4sf" - [(set (match_operand:SF 0 "vsx_register_operand" "=f,f") @@ -1172,7 +1575,7 @@ rtx op2 = operands[2]; rtx op3 = operands[3]; @@ -21535,6 +21939,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3" + [(set_attr "length" "8") + (set_attr "type" "vecload")]) +Index: b/src/gcc/config/rs6000/rs6000.h +=================================================================== --- a/src/gcc/config/rs6000/rs6000.h +++ b/src/gcc/config/rs6000/rs6000.h @@ -92,7 +92,7 @@ @@ -21722,18 +22128,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* The default CPU for TARGET_OPTION_OVERRIDE. */ #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT -@@ -842,15 +917,17 @@ +@@ -864,15 +939,17 @@ in inline functions. Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame - pointer, which is eventually eliminated in favor of SP or FP. */ + pointer, which is eventually eliminated in favor of SP or FP. - --#define FIRST_PSEUDO_REGISTER 114 ++ + The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ +-#define FIRST_PSEUDO_REGISTER 114 +#define FIRST_PSEUDO_REGISTER 117 -+ + /* This must be included for pre gcc 3.0 glibc compatibility. */ #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 @@ -21743,7 +22149,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* The SPE has an additional 32 synthetic registers, with DWARF debug info numbering for these registers starting at 1200. While eh_frame -@@ -866,7 +943,7 @@ +@@ -888,7 +965,7 @@ We must map them here to avoid huge unwinder tables mostly consisting of unused space. */ #define DWARF_REG_TO_UNWIND_COLUMN(r) \ @@ -21752,7 +22158,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Use standard DWARF numbering for DWARF debugging information. */ #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) -@@ -906,7 +983,7 @@ +@@ -928,7 +1005,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ @@ -21761,7 +22167,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* 1 for registers not available across function calls. -@@ -926,7 +1003,7 @@ +@@ -948,7 +1025,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ @@ -21770,7 +22176,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that -@@ -945,7 +1022,7 @@ +@@ -967,7 +1044,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 \ @@ -21779,7 +22185,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) -@@ -984,6 +1061,9 @@ +@@ -1006,6 +1083,9 @@ vrsave, vscr (fixed) spe_acc, spefscr (fixed) sfp (fixed) @@ -21789,7 +22195,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ */ #if FIXED_R2 == 1 -@@ -1004,7 +1084,9 @@ +@@ -1026,7 +1106,9 @@ #define REG_ALLOC_ORDER \ {32, \ @@ -21800,7 +22206,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ 33, \ 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 50, 49, 48, 47, 46, \ -@@ -1023,7 +1105,7 @@ +@@ -1045,7 +1127,7 @@ 96, 95, 94, 93, 92, 91, \ 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 109, 110, \ @@ -21809,7 +22215,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* True if register is floating-point. */ -@@ -1064,8 +1146,11 @@ +@@ -1086,8 +1168,11 @@ #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) /* Alternate name for any vector register supporting logical operations, no @@ -21823,7 +22229,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. */ -@@ -1125,28 +1210,32 @@ +@@ -1147,28 +1232,32 @@ /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, @@ -21867,7 +22273,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ : 1) /* Post-reload, we can't use any new AltiVec registers, as we already -@@ -1240,6 +1329,7 @@ +@@ -1262,6 +1351,7 @@ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, @@ -21875,7 +22281,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ NON_SPECIAL_REGS, LINK_REGS, CTR_REGS, -@@ -1270,6 +1360,7 @@ +@@ -1292,6 +1382,7 @@ "VSCR_REGS", \ "SPE_ACC_REGS", \ "SPEFSCR_REGS", \ @@ -21883,7 +22289,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ "NON_SPECIAL_REGS", \ "LINK_REGS", \ "CTR_REGS", \ -@@ -1299,6 +1390,7 @@ +@@ -1321,6 +1412,7 @@ { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ @@ -21891,7 +22297,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ -@@ -1309,7 +1401,7 @@ +@@ -1331,7 +1423,7 @@ { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ @@ -21900,7 +22306,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* The same information, inverted: -@@ -1337,7 +1429,18 @@ +@@ -1359,7 +1451,18 @@ RS6000_CONSTRAINT_wa, /* Any VSX register */ RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ @@ -21919,7 +22325,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ RS6000_CONSTRAINT_MAX }; -@@ -1425,21 +1528,14 @@ +@@ -1447,21 +1550,14 @@ arguments. */ #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 || flag_asan != 0) @@ -21945,7 +22351,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Align an address */ #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) -@@ -1489,7 +1585,7 @@ +@@ -1511,7 +1607,7 @@ /* Define this if stack space is still allocated for a parameter passed in a register. The value is the number of bytes allocated to this area. */ @@ -21954,7 +22360,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Define this if the above stack space is to be considered part of the space allocated by the caller. */ -@@ -1522,7 +1618,7 @@ +@@ -1544,7 +1640,7 @@ NONLOCAL needs twice Pmode to maintain both backchain and SP. */ #define STACK_SAVEAREA_MODE(LEVEL) \ (LEVEL == SAVE_FUNCTION ? VOIDmode \ @@ -21963,7 +22369,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Minimum and maximum general purpose registers used to hold arguments. */ #define GP_ARG_MIN_REG 3 -@@ -1533,9 +1629,8 @@ +@@ -1555,9 +1651,8 @@ #define FP_ARG_MIN_REG 33 #define FP_ARG_AIX_MAX_REG 45 #define FP_ARG_V4_MAX_REG 40 @@ -21975,7 +22381,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) /* Minimum and maximum AltiVec registers used to hold arguments. */ -@@ -1543,10 +1638,17 @@ +@@ -1565,10 +1660,17 @@ #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) @@ -21993,7 +22399,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Flags for the call/call_value rtl operations set up by function_arg */ #define CALL_NORMAL 0x00000000 /* no special processing */ -@@ -1566,8 +1668,10 @@ +@@ -1588,8 +1690,10 @@ On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ #define FUNCTION_VALUE_REGNO_P(N) \ ((N) == GP_ARG_RETURN \ @@ -22006,7 +22412,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* 1 if N is a possible register number for function argument passing. On RS/6000, these are r3-r10 and fp1-fp13. -@@ -1691,11 +1795,8 @@ +@@ -1713,11 +1817,8 @@ /* Number of bytes into the frame return addresses can be found. See rs6000_stack_info in rs6000.c for more information on how the different abi's store the return address. */ @@ -22020,7 +22426,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* The current return address is in link register (65). The return address of anything farther back is accessed normally at an offset of 8 from the -@@ -2215,6 +2316,9 @@ +@@ -2237,6 +2338,9 @@ &rs6000_reg_names[111][0], /* spe_acc */ \ &rs6000_reg_names[112][0], /* spefscr */ \ &rs6000_reg_names[113][0], /* sfp */ \ @@ -22030,7 +22436,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ } /* Table of additional register names to use in user input. */ -@@ -2268,7 +2372,9 @@ +@@ -2290,7 +2394,9 @@ {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ @@ -22041,7 +22447,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* This is how to output an element of a case-vector that is relative. */ -@@ -2357,7 +2463,12 @@ +@@ -2379,7 +2485,12 @@ #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ /* Miscellaneous information. */ @@ -22055,7 +22461,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Convenience macros to document the instruction type. */ #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ -@@ -2369,6 +2480,9 @@ +@@ -2391,6 +2502,9 @@ #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ @@ -22065,7 +22471,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BTM_SPE MASK_STRING /* E500 */ #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ -@@ -2380,10 +2494,13 @@ +@@ -2402,10 +2516,13 @@ #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | RS6000_BTM_VSX \ @@ -22079,7 +22485,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ | RS6000_BTM_POPCNTD \ | RS6000_BTM_CELL) -@@ -2395,6 +2512,7 @@ +@@ -2417,6 +2534,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -22087,7 +22493,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -2406,6 +2524,7 @@ +@@ -2428,6 +2546,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, @@ -22095,7 +22501,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -@@ -2424,6 +2543,7 @@ +@@ -2446,6 +2565,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -22103,6 +22509,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S +Index: b/src/gcc/config/rs6000/altivec.md +=================================================================== --- a/src/gcc/config/rs6000/altivec.md +++ b/src/gcc/config/rs6000/altivec.md @@ -41,15 +41,11 @@ @@ -22157,7 +22565,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ ;; Short vec in modes (define_mode_iterator VIshort [V8HI V16QI]) ;; Vec float modes -@@ -159,9 +156,19 @@ +@@ -159,8 +156,18 @@ ;; Like VM, except don't do TImode (define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI]) @@ -22169,16 +22577,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)") + (V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)") + (V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)")]) - ++ +;; Vector pack/unpack +(define_mode_iterator VP [V2DI V4SI V8HI]) +(define_mode_attr VP_small [(V2DI "V4SI") (V4SI "V8HI") (V8HI "V16QI")]) +(define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")]) +(define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")]) -+ + ;; Vector move instructions. (define_insn "*altivec_mov<mode>" - [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v") @@ -378,10 +385,10 @@ ;; add @@ -22327,12 +22734,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ high_product = gen_reg_rtx (V4SImode); emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero)); -@@ -669,11 +676,19 @@ +@@ -669,10 +676,18 @@ emit_insn (gen_vec_widen_smult_even_v8hi (even, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_odd_v8hi (odd, operands[1], operands[2])); - emit_insn (gen_altivec_vmrghw (high, even, odd)); - emit_insn (gen_altivec_vmrglw (low, even, odd)); +- +- emit_insn (gen_altivec_vpkuwum (operands[0], high, low)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmrghw (high, even, odd)); @@ -22346,11 +22755,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + emit_insn (gen_altivec_vpkuwum (operands[0], low, high)); + } -- emit_insn (gen_altivec_vpkuwum (operands[0], high, low)); -- DONE; }") - @@ -744,18 +759,18 @@ ;; max @@ -22553,12 +22959,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] - UNSPEC_VMULESB))] -+ UNSPEC_VMULOUB))] - "TARGET_ALTIVEC" +- "TARGET_ALTIVEC" - "vmulesb %0,%1,%2" -+ "vmuloub %0,%1,%2" - [(set_attr "type" "veccomplex")]) - +- [(set_attr "type" "veccomplex")]) +- -(define_insn "vec_widen_umult_even_v8hi" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") @@ -22573,10 +22977,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VMULESH))] -- "TARGET_ALTIVEC" ++ UNSPEC_VMULOUB))] + "TARGET_ALTIVEC" - "vmulesh %0,%1,%2" -- [(set_attr "type" "veccomplex")]) -- ++ "vmuloub %0,%1,%2" + [(set_attr "type" "veccomplex")]) + -(define_insn "vec_widen_umult_odd_v16qi" +(define_insn "altivec_vmulesb" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -22594,26 +23000,25 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] -@@ -989,167 +1115,124 @@ +@@ -989,7 +1115,16 @@ "vmulosb %0,%1,%2" [(set_attr "type" "veccomplex")]) -(define_insn "vec_widen_umult_odd_v8hi" +(define_insn "altivec_vmuleuh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] ++ [(set (match_operand:V4SI 0 "register_operand" "=v") ++ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") ++ (match_operand:V8HI 2 "register_operand" "v")] + UNSPEC_VMULEUH))] + "TARGET_ALTIVEC" + "vmuleuh %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulouh" -+ [(set (match_operand:V4SI 0 "register_operand" "=v") -+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") -+ (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VMULOUH))] - "TARGET_ALTIVEC" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] +@@ -998,158 +1133,106 @@ "vmulouh %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -22622,21 +23027,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")] +- UNSPEC_VMULOSH))] + UNSPEC_VMULESH))] -+ "TARGET_ALTIVEC" -+ "vmulesh %0,%1,%2" -+ [(set_attr "type" "veccomplex")]) -+ -+(define_insn "altivec_vmulosh" -+ [(set (match_operand:V4SI 0 "register_operand" "=v") -+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") -+ (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VMULOSH))] "TARGET_ALTIVEC" - "vmulosh %0,%1,%2" +- "vmulosh %0,%1,%2" ++ "vmulesh %0,%1,%2" [(set_attr "type" "veccomplex")]) - +- -;; logical ops. Have the logical ops follow the memory ops in -;; terms of whether to prefer VSX or Altivec - @@ -22692,10 +23090,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKUHUM))] -- "TARGET_ALTIVEC" ++(define_insn "altivec_vmulosh" ++ [(set (match_operand:V4SI 0 "register_operand" "=v") ++ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") ++ (match_operand:V8HI 2 "register_operand" "v")] ++ UNSPEC_VMULOSH))] + "TARGET_ALTIVEC" - "vpkuhum %0,%1,%2" - [(set_attr "type" "vecperm")]) -- ++ "vmulosh %0,%1,%2" ++ [(set_attr "type" "veccomplex")]) + -(define_insn "altivec_vpkuwum" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") @@ -22704,7 +23109,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - "TARGET_ALTIVEC" - "vpkuwum %0,%1,%2" - [(set_attr "type" "vecperm")]) -- + +;; Vector pack/unpack (define_insn "altivec_vpkpx" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -22713,15 +23118,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ UNSPEC_VPKPX))] "TARGET_ALTIVEC" - "vpkpx %0,%1,%2" -+ "* -+ { -+ if (BYTES_BIG_ENDIAN) -+ return \"vpkpx %0,%1,%2\"; -+ else -+ return \"vpkpx %0,%2,%1\"; -+ }" - [(set_attr "type" "vecperm")]) - +- [(set_attr "type" "vecperm")]) +- -(define_insn "altivec_vpkshss" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") @@ -22730,6 +23128,65 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkshss %0,%1,%2" +- [(set_attr "type" "vecperm")]) +- +-(define_insn "altivec_vpkswss" +- [(set (match_operand:V8HI 0 "register_operand" "=v") +- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") +- (match_operand:V4SI 2 "register_operand" "v")] +- UNSPEC_VPKSWSS)) +- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] +- "TARGET_ALTIVEC" +- "vpkswss %0,%1,%2" +- [(set_attr "type" "vecperm")]) +- +-(define_insn "altivec_vpkuhus" +- [(set (match_operand:V16QI 0 "register_operand" "=v") +- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") +- (match_operand:V8HI 2 "register_operand" "v")] +- UNSPEC_VPKUHUS)) +- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] +- "TARGET_ALTIVEC" +- "vpkuhus %0,%1,%2" +- [(set_attr "type" "vecperm")]) +- +-(define_insn "altivec_vpkshus" +- [(set (match_operand:V16QI 0 "register_operand" "=v") +- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") +- (match_operand:V8HI 2 "register_operand" "v")] +- UNSPEC_VPKSHUS)) +- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] +- "TARGET_ALTIVEC" +- "vpkshus %0,%1,%2" +- [(set_attr "type" "vecperm")]) +- +-(define_insn "altivec_vpkuwus" +- [(set (match_operand:V8HI 0 "register_operand" "=v") +- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") +- (match_operand:V4SI 2 "register_operand" "v")] +- UNSPEC_VPKUWUS)) +- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] +- "TARGET_ALTIVEC" +- "vpkuwus %0,%1,%2" +- [(set_attr "type" "vecperm")]) +- +-(define_insn "altivec_vpkswus" +- [(set (match_operand:V8HI 0 "register_operand" "=v") +- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") +- (match_operand:V4SI 2 "register_operand" "v")] +- UNSPEC_VPKSWUS)) +- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] +- "TARGET_ALTIVEC" +- "vpkswus %0,%1,%2" ++ "* ++ { ++ if (BYTES_BIG_ENDIAN) ++ return \"vpkpx %0,%1,%2\"; ++ else ++ return \"vpkpx %0,%2,%1\"; ++ }" ++ [(set_attr "type" "vecperm")]) ++ +(define_insn "altivec_vpks<VI_char>ss" + [(set (match_operand:<VP_small> 0 "register_operand" "=v") + (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v") @@ -22743,16 +23200,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + else + return \"vpks<VI_char>ss %0,%2,%1\"; + }" - [(set_attr "type" "vecperm")]) - --(define_insn "altivec_vpkswss" -- [(set (match_operand:V8HI 0 "register_operand" "=v") -- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") -- (match_operand:V4SI 2 "register_operand" "v")] -- UNSPEC_VPKSWSS)) -- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] -- "TARGET_ALTIVEC" -- "vpkswss %0,%1,%2" ++ [(set_attr "type" "vecperm")]) ++ +(define_insn "altivec_vpks<VI_char>us" + [(set (match_operand:<VP_small> 0 "register_operand" "=v") + (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v") @@ -22766,16 +23215,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + else + return \"vpks<VI_char>us %0,%2,%1\"; + }" - [(set_attr "type" "vecperm")]) - --(define_insn "altivec_vpkuhus" -- [(set (match_operand:V16QI 0 "register_operand" "=v") -- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") -- (match_operand:V8HI 2 "register_operand" "v")] -- UNSPEC_VPKUHUS)) -- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] -- "TARGET_ALTIVEC" -- "vpkuhus %0,%1,%2" ++ [(set_attr "type" "vecperm")]) ++ +(define_insn "altivec_vpku<VI_char>us" + [(set (match_operand:<VP_small> 0 "register_operand" "=v") + (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v") @@ -22789,16 +23230,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + else + return \"vpku<VI_char>us %0,%2,%1\"; + }" - [(set_attr "type" "vecperm")]) - --(define_insn "altivec_vpkshus" -- [(set (match_operand:V16QI 0 "register_operand" "=v") -- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") -- (match_operand:V8HI 2 "register_operand" "v")] -- UNSPEC_VPKSHUS)) -- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] -- "TARGET_ALTIVEC" -- "vpkshus %0,%1,%2" ++ [(set_attr "type" "vecperm")]) ++ +(define_insn "altivec_vpku<VI_char>um" + [(set (match_operand:<VP_small> 0 "register_operand" "=v") + (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v") @@ -22814,26 +23247,6 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + }" [(set_attr "type" "vecperm")]) --(define_insn "altivec_vpkuwus" -- [(set (match_operand:V8HI 0 "register_operand" "=v") -- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") -- (match_operand:V4SI 2 "register_operand" "v")] -- UNSPEC_VPKUWUS)) -- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] -- "TARGET_ALTIVEC" -- "vpkuwus %0,%1,%2" -- [(set_attr "type" "vecperm")]) -- --(define_insn "altivec_vpkswus" -- [(set (match_operand:V8HI 0 "register_operand" "=v") -- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") -- (match_operand:V4SI 2 "register_operand" "v")] -- UNSPEC_VPKSWUS)) -- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] -- "TARGET_ALTIVEC" -- "vpkswus %0,%1,%2" -- [(set_attr "type" "vecperm")]) -- (define_insn "*altivec_vrl<VI_char>" - [(set (match_operand:VI 0 "register_operand" "=v") - (rotate:VI (match_operand:VI 1 "register_operand" "v") @@ -22899,7 +23312,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ (define_expand "vec_perm_constv16qi" [(match_operand:V16QI 0 "register_operand" "") -@@ -1476,14 +1564,22 @@ +@@ -1476,12 +1564,20 @@ "vsldoi %0,%1,%2,%3" [(set_attr "type" "vecperm")]) @@ -22915,19 +23328,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + UNSPEC_VUNPACK_HI_SIGN))] + "<VI_unit>" + "vupkhs<VU_char> %0,%1" - [(set_attr "type" "vecperm")]) - ++ [(set_attr "type" "vecperm")]) ++ +(define_insn "altivec_vupkls<VU_char>" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")] + UNSPEC_VUNPACK_LO_SIGN))] + "<VI_unit>" + "vupkls<VU_char> %0,%1" -+ [(set_attr "type" "vecperm")]) -+ + [(set_attr "type" "vecperm")]) + (define_insn "altivec_vupkhpx" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] @@ -1492,22 +1588,6 @@ "vupkhpx %0,%1" [(set_attr "type" "vecperm")]) @@ -23035,6 +23446,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - (set (match_operand:VI 0 "register_operand" "=v") - (smax:VI (match_dup 1) (match_dup 3)))] - "TARGET_ALTIVEC" +-{ +- operands[2] = gen_reg_rtx (GET_MODE (operands[0])); +- operands[3] = gen_reg_rtx (GET_MODE (operands[0])); + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 4) + (minus:VI2 (match_dup 2) @@ -23042,9 +23456,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (set (match_operand:VI2 0 "register_operand" "=v") + (smax:VI2 (match_dup 1) (match_dup 4)))] + "<VI_unit>" - { -- operands[2] = gen_reg_rtx (GET_MODE (operands[0])); -- operands[3] = gen_reg_rtx (GET_MODE (operands[0])); ++{ + int i, n_elt = GET_MODE_NUNITS (<MODE>mode); + rtvec v = rtvec_alloc (n_elt); + @@ -23058,7 +23470,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ }) ;; Generate -@@ -1950,50 +2030,20 @@ +@@ -1950,49 +2030,19 @@ DONE; }") @@ -23072,13 +23484,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - emit_insn (gen_altivec_vupkhsb (operands[0], operands[1])); - DONE; -}") -+(define_expand "vec_unpacks_hi_<VP_small_lc>" -+ [(set (match_operand:VP 0 "register_operand" "=v") -+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")] -+ UNSPEC_VUNPACK_HI_SIGN))] -+ "<VI_unit>" -+ "") - +- -(define_expand "vec_unpacks_hi_v8hi" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] @@ -23089,13 +23495,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - emit_insn (gen_altivec_vupkhsh (operands[0], operands[1])); - DONE; -}") -+(define_expand "vec_unpacks_lo_<VP_small_lc>" -+ [(set (match_operand:VP 0 "register_operand" "=v") -+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")] -+ UNSPEC_VUNPACK_LO_SIGN))] -+ "<VI_unit>" -+ "") - +- -(define_expand "vec_unpacks_lo_v16qi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] @@ -23106,7 +23506,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - emit_insn (gen_altivec_vupklsb (operands[0], operands[1])); - DONE; -}") -- ++(define_expand "vec_unpacks_hi_<VP_small_lc>" ++ [(set (match_operand:VP 0 "register_operand" "=v") ++ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")] ++ UNSPEC_VUNPACK_HI_SIGN))] ++ "<VI_unit>" ++ "") + -(define_expand "vec_unpacks_lo_v8hi" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] @@ -23117,10 +23523,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - emit_insn (gen_altivec_vupklsh (operands[0], operands[1])); - DONE; -}") -- ++(define_expand "vec_unpacks_lo_<VP_small_lc>" ++ [(set (match_operand:VP 0 "register_operand" "=v") ++ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")] ++ UNSPEC_VUNPACK_LO_SIGN))] ++ "<VI_unit>" ++ "") + (define_insn "vperm_v8hiv4si" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") @@ -2025,25 +2075,26 @@ rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); @@ -23457,6 +23868,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "vgbbd %0,%1" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) +Index: b/src/gcc/config/rs6000/sysv4le.h +=================================================================== --- a/src/gcc/config/rs6000/sysv4le.h +++ b/src/gcc/config/rs6000/sysv4le.h @@ -34,3 +34,7 @@ @@ -23467,6 +23880,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +/* Little-endian PowerPC64 Linux uses the ELF v2 ABI by default. */ +#define LINUX64_DEFAULT_ABI_ELFv2 + +Index: b/src/gcc/config/rs6000/dfp.md +=================================================================== --- a/src/gcc/config/rs6000/dfp.md +++ b/src/gcc/config/rs6000/dfp.md @@ -29,77 +29,6 @@ @@ -23791,7 +24206,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ (define_expand "negtd2" [(set (match_operand:TD 0 "gpc_reg_operand" "") (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))] -@@ -410,40 +148,25 @@ +@@ -410,39 +148,24 @@ "") (define_insn "*abstd2_fpr" @@ -23811,21 +24226,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ (define_insn "*nabstd2_fpr" - [(set (match_operand:TD 0 "gpc_reg_operand" "=d") - (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))] -+ [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") -+ (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS" +- "TARGET_HARD_FLOAT && TARGET_FPRS" - "fnabs %0,%1" - [(set_attr "type" "fp")]) -+ "@ -+ fnabs %0,%1 -+ fnabs %0,%1\;fmr %L0,%L1" -+ [(set_attr "type" "fp") -+ (set_attr "length" "4,8")]) - +- -(define_expand "movtd" - [(set (match_operand:TD 0 "general_operand" "") - (match_operand:TD 1 "any_operand" ""))] -- "TARGET_HARD_FLOAT && TARGET_FPRS" ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") ++ (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))] + "TARGET_HARD_FLOAT && TARGET_FPRS" - "{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }") - -; It's important to list the Y->r and r->Y moves before r->r because @@ -23842,10 +24252,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - [(pc)] -{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,20,20,16")]) -- ++ "@ ++ fnabs %0,%1 ++ fnabs %0,%1\;fmr %L0,%L1" ++ [(set_attr "type" "fp") ++ (set_attr "length" "4,8")]) + ;; Hardware support for decimal floating point operations. - (define_insn "extendddtd2" +Index: b/src/gcc/config/rs6000/sync.md +=================================================================== --- a/src/gcc/config/rs6000/sync.md +++ b/src/gcc/config/rs6000/sync.md @@ -18,14 +18,23 @@ @@ -23859,13 +24275,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (SI "lwarx") + (DI "ldarx") + (TI "lqarx")]) - ++ +(define_mode_attr stcx [(QI "stbcx.") + (HI "sthcx.") + (SI "stwcx.") + (DI "stdcx.") + (TI "stqcx.")]) -+ + (define_code_iterator FETCHOP [plus minus ior xor and]) (define_code_attr fetchop_name [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")]) @@ -23900,6 +24316,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -;; ??? Power ISA 2.06B says that there *is* a load-{byte,half}-and-reserve -;; opcode that is "phased-in". Not implemented as of Power7, so not yet used, -;; but let's prepare the macros anyway. +- +-(define_mode_iterator ATOMIC [SI (DI "TARGET_POWERPC64")]) +;; Any supported integer mode that has atomic l<x>arx/st<x>cx. instrucitons +;; other than the quad memory operations, which have special restrictions. +;; Byte/halfword atomic instructions were added in ISA 2.06B, but were phased @@ -23909,16 +24327,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (HI "TARGET_SYNC_HI_QI") + SI + (DI "TARGET_POWERPC64")]) - --(define_mode_iterator ATOMIC [SI (DI "TARGET_POWERPC64")]) ++ +;; Types that we should provide atomic instructions for. - ++ +(define_mode_iterator AINT [QI + HI + SI + (DI "TARGET_POWERPC64") + (TI "TARGET_SYNC_TI")]) -+ + (define_insn "load_locked<mode>" - [(set (match_operand:ATOMIC 0 "gpc_reg_operand" "=r") + [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r") @@ -24107,7 +24524,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ (match_operand:SI 3 "const_int_operand" "")] ;; model "" { ---- a/src/gcc/config/rs6000/crypto.md +Index: b/src/gcc/config/rs6000/crypto.md +=================================================================== +--- /dev/null +++ b/src/gcc/config/rs6000/crypto.md @@ -0,0 +1,101 @@ +;; Cryptographic instructions added in ISA 2.07 @@ -24211,6 +24630,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "TARGET_CRYPTO" + "vshasigma<CR_char> %0,%1,%2,%3" + [(set_attr "type" "crypto")]) +Index: b/src/gcc/config/rs6000/rs6000.md +=================================================================== --- a/src/gcc/config/rs6000/rs6000.md +++ b/src/gcc/config/rs6000/rs6000.md @@ -25,10 +25,14 @@ @@ -24786,16 +25207,56 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - DONE; -} - [(set_attr "type" "fp,fp,fpload")]) -+ fabs %0,%1 -+ xsabsdp %x0,%x1" -+ [(set_attr "type" "fp") -+ (set_attr "fp_type" "fp_addsub_<Fs>")]) - +- -(define_expand "truncdfsf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" - "") +- +-(define_insn "*truncdfsf2_fpr" +- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") +- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))] +- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" +- "frsp %0,%1" +- [(set_attr "type" "fp")]) +- +-(define_expand "negsf2" +- [(set (match_operand:SF 0 "gpc_reg_operand" "") +- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] +- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +- "") +- +-(define_insn "*negsf2" +- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") +- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] +- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" +- "fneg %0,%1" +- [(set_attr "type" "fp")]) +- +-(define_expand "abssf2" +- [(set (match_operand:SF 0 "gpc_reg_operand" "") +- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] +- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +- "") +- +-(define_insn "*abssf2" +- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") +- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] +- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" +- "fabs %0,%1" +- [(set_attr "type" "fp")]) ++ fabs %0,%1 ++ xsabsdp %x0,%x1" ++ [(set_attr "type" "fp") ++ (set_attr "fp_type" "fp_addsub_<Fs>")]) + +-(define_insn "" +- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") +- (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] +- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" +- "fnabs %0,%1" +- [(set_attr "type" "fp")]) +(define_insn "*nabs<mode>2_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") + (neg:SFDF @@ -24808,16 +25269,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_<Fs>")]) --(define_insn "*truncdfsf2_fpr" -- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))] -- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" -- "frsp %0,%1" -- [(set_attr "type" "fp")]) -- --(define_expand "negsf2" +-(define_expand "addsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") -- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] +- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") +- (match_operand:SF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +(define_expand "neg<mode>2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") @@ -24825,12 +25280,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "TARGET_<MODE>_INSN" "") --(define_insn "*negsf2" +-(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] +- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") +- (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fneg %0,%1" -- [(set_attr "type" "fp")]) +- "fadds %0,%1,%2" +(define_insn "*neg<mode>2_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") + (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))] @@ -24838,12 +25293,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "@ + fneg %0,%1 + xsnegdp %x0,%x1" -+ [(set_attr "type" "fp") + [(set_attr "type" "fp") +- (set_attr "fp_type" "fp_addsub_s")]) + (set_attr "fp_type" "fp_addsub_<Fs>")]) --(define_expand "abssf2" +-(define_expand "subsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") -- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] +- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") +- (match_operand:SF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +(define_expand "add<mode>3" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") @@ -24852,12 +25309,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "TARGET_<MODE>_INSN" "") --(define_insn "*abssf2" +-(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] +- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") +- (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fabs %0,%1" -- [(set_attr "type" "fp")]) +- "fsubs %0,%1,%2" +(define_insn "*add<mode>3_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>") @@ -24866,19 +25323,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "@ + fadd<Ftrad> %0,%1,%2 + xsadd<Fvsx> %x0,%x1,%x2" -+ [(set_attr "type" "fp") + [(set_attr "type" "fp") +- (set_attr "fp_type" "fp_addsub_s")]) + (set_attr "fp_type" "fp_addsub_<Fs>")]) --(define_insn "" -- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] -- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fnabs %0,%1" -- [(set_attr "type" "fp")]) -- --(define_expand "addsf3" +-(define_expand "mulsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") -- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") +- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") - (match_operand:SF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +(define_expand "sub<mode>3" @@ -24890,10 +25341,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") +- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fadds %0,%1,%2" +- "fmuls %0,%1,%2" +(define_insn "*sub<mode>3_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>") @@ -24903,14 +25354,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + fsub<Ftrad> %0,%1,%2 + xssub<Fvsx> %x0,%x1,%x2" [(set_attr "type" "fp") -- (set_attr "fp_type" "fp_addsub_s")]) +- (set_attr "fp_type" "fp_mul_s")]) + (set_attr "fp_type" "fp_addsub_<Fs>")]) --(define_expand "subsf3" +-(define_expand "divsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") -- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") -- (match_operand:SF 2 "gpc_reg_operand" "")))] -- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +- (div:SF (match_operand:SF 1 "gpc_reg_operand" "") +- (match_operand:SF 2 "gpc_reg_operand" "")))] +- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" +(define_expand "mul<mode>3" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") @@ -24920,12 +25371,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") -- (match_operand:SF 2 "gpc_reg_operand" "f")))] -- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fsubs %0,%1,%2" -- [(set_attr "type" "fp") -- (set_attr "fp_type" "fp_addsub_s")]) +- (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") +- (match_operand:SF 2 "gpc_reg_operand" "f")))] +- "TARGET_HARD_FLOAT && TARGET_FPRS +- && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" +- "fdivs %0,%1,%2" +- [(set_attr "type" "sdiv")]) +(define_insn "*mul<mode>3_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>") @@ -24937,26 +25388,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + [(set_attr "type" "dmul") + (set_attr "fp_type" "fp_mul_<Fs>")]) --(define_expand "mulsf3" -- [(set (match_operand:SF 0 "gpc_reg_operand" "") -- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") -- (match_operand:SF 2 "gpc_reg_operand" "")))] -- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +-(define_insn "fres" +- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") +- (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] +- "TARGET_FRES" +- "fres %0,%1" +(define_expand "div<mode>3" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") + (match_operand:SFDF 2 "gpc_reg_operand" "")))] + "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU" - "") - --(define_insn "" -- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") -- (match_operand:SF 2 "gpc_reg_operand" "f")))] -- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fmuls %0,%1,%2" -- [(set_attr "type" "fp") -- (set_attr "fp_type" "fp_mul_s")]) ++ "") ++ +(define_insn "*div<mode>3_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>") @@ -24967,13 +25410,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + xsdiv<Fvsx> %x0,%x1,%x2" + [(set_attr "type" "<Fs>div") + (set_attr "fp_type" "fp_div_<Fs>")]) - --(define_expand "divsf3" -- [(set (match_operand:SF 0 "gpc_reg_operand" "") -- (div:SF (match_operand:SF 1 "gpc_reg_operand" "") -- (match_operand:SF 2 "gpc_reg_operand" "")))] -- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" -- "") ++ +(define_insn "sqrt<mode>2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") + (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))] @@ -24984,15 +25421,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + xssqrt<Fvsx> %x0,%x1" + [(set_attr "type" "<Fs>sqrt") + (set_attr "fp_type" "fp_sqrt_<Fs>")]) - --(define_insn "" -- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") -- (match_operand:SF 2 "gpc_reg_operand" "f")))] -- "TARGET_HARD_FLOAT && TARGET_FPRS -- && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" -- "fdivs %0,%1,%2" -- [(set_attr "type" "sdiv")]) ++ +;; Floating point reciprocal approximation +(define_insn "fre<Fs>" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") @@ -25002,13 +25431,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "@ + fre<Ftrad> %0,%1 + xsre<Fvsx> %x0,%x1" -+ [(set_attr "type" "fp")]) + [(set_attr "type" "fp")]) --(define_insn "fres" +-; builtin fmaf support +-(define_insn "*fmasf4_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] -- "TARGET_FRES" -- "fres %0,%1" +- (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") +- (match_operand:SF 2 "gpc_reg_operand" "f") +- (match_operand:SF 3 "gpc_reg_operand" "f")))] +- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" +- "fmadds %0,%1,%2,%3" +- [(set_attr "type" "fp") +- (set_attr "fp_type" "fp_maddsub_s")]) +(define_insn "*rsqrt<mode>2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] @@ -25017,16 +25451,15 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "@ + frsqrte<Ftrad> %0,%1 + xsrsqrte<Fvsx> %x0,%x1" - [(set_attr "type" "fp")]) ++ [(set_attr "type" "fp")]) --; builtin fmaf support --(define_insn "*fmasf4_fpr" +-(define_insn "*fmssf4_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f") -- (match_operand:SF 3 "gpc_reg_operand" "f")))] +- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fmadds %0,%1,%2,%3" +- "fmsubs %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_s")]) +;; Floating point comparisons @@ -25040,13 +25473,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + xscmpudp %0,%x1,%x2" + [(set_attr "type" "fpcompare")]) --(define_insn "*fmssf4_fpr" +-(define_insn "*nfmasf4_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") -- (match_operand:SF 2 "gpc_reg_operand" "f") -- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))] +- (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") +- (match_operand:SF 2 "gpc_reg_operand" "f") +- (match_operand:SF 3 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fmsubs %0,%1,%2,%3" +- "fnmadds %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_s")]) +;; Floating point conversions @@ -25056,13 +25489,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" + "") --(define_insn "*nfmasf4_fpr" +-(define_insn "*nfmssf4_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f") -- (match_operand:SF 3 "gpc_reg_operand" "f"))))] +- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fnmadds %0,%1,%2,%3" +- "fnmsubs %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_s")]) +(define_insn_and_split "*extendsfdf2_fpr" @@ -25102,16 +25535,6 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (const_string "fpload_u") + (const_string "fpload")))])]) --(define_insn "*nfmssf4_fpr" -- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") -- (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") -- (match_operand:SF 2 "gpc_reg_operand" "f") -- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))] -- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -- "fnmsubs %0,%1,%2,%3" -- [(set_attr "type" "fp") -- (set_attr "fp_type" "fp_maddsub_s")]) -- -(define_expand "sqrtsf2" +(define_expand "truncdfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "") @@ -25124,8 +25547,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ "") -(define_insn "" -+(define_insn "*truncdfsf2_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") +- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT - && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" @@ -25133,7 +25555,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - [(set_attr "type" "ssqrt")]) - -(define_insn "*rsqrtsf_internal1" -- [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ++(define_insn "*truncdfsf2_fpr" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] - UNSPEC_RSQRT))] - "TARGET_FRSQRTES" @@ -25144,7 +25567,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ [(set_attr "type" "fp")]) ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in -@@ -4742,39 +5012,84 @@ +@@ -4742,37 +5012,82 @@ ;; Use an unspec rather providing an if-then-else in RTL, to prevent the ;; compiler from optimizing -0.0 (define_insn "copysign<mode>3_fcpsgn" @@ -25205,7 +25628,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); + DONE; +}) - ++ +(define_insn "*smax<mode>3_vsx" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") + (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>") @@ -25234,7 +25657,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "xsmindp %x0,%x1,%x2" + [(set_attr "type" "fp")]) + - (define_split ++(define_split + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (match_operator:SFDF 3 "min_max_operator" + [(match_operand:SFDF 1 "gpc_reg_operand" "") @@ -25247,12 +25670,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + operands[2]); + DONE; +}) -+ -+(define_split + + (define_split [(set (match_operand:SF 0 "gpc_reg_operand" "") - (match_operator:SF 3 "min_max_operator" - [(match_operand:SF 1 "gpc_reg_operand" "") -@@ -4904,208 +5219,9 @@ +@@ -4904,267 +5219,71 @@ "fsel %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -25269,29 +25690,73 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - && !VECTOR_UNIT_VSX_P (DFmode)" - "fneg %0,%1" - [(set_attr "type" "fp")]) -- ++;; The conditional move instructions allow us to perform max and min ++;; operations even when + -(define_expand "absdf2" -- [(set (match_operand:DF 0 "gpc_reg_operand" "") ++(define_split + [(set (match_operand:DF 0 "gpc_reg_operand" "") - (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" - "") -- ++ (match_operator:DF 3 "min_max_operator" ++ [(match_operand:DF 1 "gpc_reg_operand" "") ++ (match_operand:DF 2 "gpc_reg_operand" "")]))] ++ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ++ && !flag_trapping_math" ++ [(const_int 0)] ++ " ++{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), ++ operands[1], operands[2]); ++ DONE; ++}") ++ ++(define_expand "movdfcc" ++ [(set (match_operand:DF 0 "gpc_reg_operand" "") ++ (if_then_else:DF (match_operand 1 "comparison_operator" "") ++ (match_operand:DF 2 "gpc_reg_operand" "") ++ (match_operand:DF 3 "gpc_reg_operand" "")))] ++ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" ++ " ++{ ++ if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) ++ DONE; ++ else ++ FAIL; ++}") + -(define_insn "*absdf2_fpr" -- [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++(define_insn "*fseldfdf4" + [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fabs %0,%1" -- [(set_attr "type" "fp")]) -- ++ (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d") ++ (match_operand:DF 4 "zero_fp_constant" "F")) ++ (match_operand:DF 2 "gpc_reg_operand" "d") ++ (match_operand:DF 3 "gpc_reg_operand" "d")))] ++ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" ++ "fsel %0,%1,%2,%3" + [(set_attr "type" "fp")]) + -(define_insn "*nabsdf2_fpr" -- [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++(define_insn "*fselsfdf4" + [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fnabs %0,%1" -- [(set_attr "type" "fp")]) -- ++ (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") ++ (match_operand:SF 4 "zero_fp_constant" "F")) ++ (match_operand:DF 2 "gpc_reg_operand" "d") ++ (match_operand:DF 3 "gpc_reg_operand" "d")))] ++ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT" ++ "fsel %0,%1,%2,%3" + [(set_attr "type" "fp")]) ++ ++;; Conversions to and from floating-point. + -(define_expand "adddf3" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (plus:DF (match_operand:DF 1 "gpc_reg_operand" "") @@ -25435,9 +25900,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - "fsqrt %0,%1" - [(set_attr "type" "dsqrt")]) - - ;; The conditional move instructions allow us to perform max and min - ;; operations even when - +-;; The conditional move instructions allow us to perform max and min +-;; operations even when +- -(define_expand "smaxdf3" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") @@ -25458,21 +25923,72 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - && !flag_trapping_math" - "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") - - (define_split - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (match_operator:DF 3 "min_max_operator" -@@ -5159,12 +5275,15 @@ - ; We don't define lfiwax/lfiwzx with the normal definition, because we - ; don't want to support putting SImode in FPR registers. - (define_insn "lfiwax" +-(define_split +- [(set (match_operand:DF 0 "gpc_reg_operand" "") +- (match_operator:DF 3 "min_max_operator" +- [(match_operand:DF 1 "gpc_reg_operand" "") +- (match_operand:DF 2 "gpc_reg_operand" "")]))] +- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT +- && !flag_trapping_math" +- [(const_int 0)] +- " +-{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), +- operands[1], operands[2]); +- DONE; +-}") +- +-(define_expand "movdfcc" +- [(set (match_operand:DF 0 "gpc_reg_operand" "") +- (if_then_else:DF (match_operand 1 "comparison_operator" "") +- (match_operand:DF 2 "gpc_reg_operand" "") +- (match_operand:DF 3 "gpc_reg_operand" "")))] +- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" +- " +-{ +- if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) +- DONE; +- else +- FAIL; +-}") +- +-(define_insn "*fseldfdf4" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=d") +- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d") +- (match_operand:DF 4 "zero_fp_constant" "F")) +- (match_operand:DF 2 "gpc_reg_operand" "d") +- (match_operand:DF 3 "gpc_reg_operand" "d")))] +- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" +- "fsel %0,%1,%2,%3" +- [(set_attr "type" "fp")]) +- +-(define_insn "*fselsfdf4" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=d") +- (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") +- (match_operand:SF 4 "zero_fp_constant" "F")) +- (match_operand:DF 2 "gpc_reg_operand" "d") +- (match_operand:DF 3 "gpc_reg_operand" "d")))] +- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT" +- "fsel %0,%1,%2,%3" +- [(set_attr "type" "fp")]) +- +-;; Conversions to and from floating-point. +- +-; We don't define lfiwax/lfiwzx with the normal definition, because we +-; don't want to support putting SImode in FPR registers. +-(define_insn "lfiwax" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d") - (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")] -+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm") -+ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] - UNSPEC_LFIWAX))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX" +- UNSPEC_LFIWAX))] +- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX" - "lfiwax %0,%y1" - [(set_attr "type" "fpload")]) ++; We don't define lfiwax/lfiwzx with the normal definition, because we ++; don't want to support putting SImode in FPR registers. ++(define_insn "lfiwax" ++ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm") ++ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] ++ UNSPEC_LFIWAX))] ++ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX" + "@ + lfiwax %0,%y1 + lxsiwax %x0,%y1 @@ -25551,23 +26067,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -(define_expand "btrunc<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] -+(define_insn "btrunc<mode>2" -+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") -+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] - UNSPEC_FRIZ))] +- UNSPEC_FRIZ))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>" - "") -+ "TARGET_<MODE>_FPR && TARGET_FPRND" -+ "@ -+ friz %0,%1 -+ xsrdpiz %x0,%x1" -+ [(set_attr "type" "fp") -+ (set_attr "fp_type" "fp_addsub_<Fs>")]) - +- -(define_insn "*btrunc<mode>2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")] -- UNSPEC_FRIZ))] ++(define_insn "btrunc<mode>2" ++ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") ++ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] + UNSPEC_FRIZ))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> - && !VECTOR_UNIT_VSX_P (<MODE>mode)" - "friz %0,%1" @@ -25576,23 +26086,23 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -(define_expand "ceil<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] -+(define_insn "ceil<mode>2" -+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") -+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] - UNSPEC_FRIP))] +- UNSPEC_FRIP))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>" - "") + "TARGET_<MODE>_FPR && TARGET_FPRND" + "@ -+ frip %0,%1 -+ xsrdpip %x0,%x1" ++ friz %0,%1 ++ xsrdpiz %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_<Fs>")]) -(define_insn "*ceil<mode>2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")] -- UNSPEC_FRIP))] ++(define_insn "ceil<mode>2" ++ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") ++ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] + UNSPEC_FRIP))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> - && !VECTOR_UNIT_VSX_P (<MODE>mode)" - "frip %0,%1" @@ -25601,28 +26111,34 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -(define_expand "floor<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] -+(define_insn "floor<mode>2" -+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") -+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] - UNSPEC_FRIM))] +- UNSPEC_FRIM))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>" - "") + "TARGET_<MODE>_FPR && TARGET_FPRND" + "@ -+ frim %0,%1 -+ xsrdpim %x0,%x1" ++ frip %0,%1 ++ xsrdpip %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_<Fs>")]) -(define_insn "*floor<mode>2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")] -- UNSPEC_FRIM))] ++(define_insn "floor<mode>2" ++ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") ++ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] + UNSPEC_FRIM))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> - && !VECTOR_UNIT_VSX_P (<MODE>mode)" - "frim %0,%1" - [(set_attr "type" "fp")]) -- ++ "TARGET_<MODE>_FPR && TARGET_FPRND" ++ "@ ++ frim %0,%1 ++ xsrdpim %x0,%x1" ++ [(set_attr "type" "fp") ++ (set_attr "fp_type" "fp_addsub_<Fs>")]) + ;; No VSX equivalent to frin (define_insn "round<mode>2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>") @@ -25660,7 +26176,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ (define_insn "anddi3_mc" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") -@@ -7379,12 +7498,18 @@ +@@ -7379,11 +7498,17 @@ (define_expand "iordi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -25672,17 +26188,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { - if (non_logical_cint_operand (operands[2], DImode)) + if (!TARGET_POWERPC64) - { ++ { + rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX); + DONE; + } + else if (!reg_or_logical_cint_operand (operands[2], DImode)) + operands[2] = force_reg (DImode, operands[2]); + else if (non_logical_cint_operand (operands[2], DImode)) -+ { + { HOST_WIDE_INT value; rtx tmp = ((!can_create_pseudo_p () - || rtx_equal_p (operands[0], operands[1])) @@ -7408,15 +7533,21 @@ emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; @@ -25718,11 +26233,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ (define_insn "*booldi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") -@@ -7678,7 +7809,385 @@ +@@ -7678,78 +7809,456 @@ (compare:CC (match_dup 0) (const_int 0)))] "") -+ +- +-;; Now define ways of moving data around. + +-;; Set up a register with a value from the GOT table +;; Eqv operation. +(define_insn "*eqv<mode>3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") @@ -25733,10 +26251,33 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + "eqv %0,%1,%2" + [(set_attr "type" "integer") + (set_attr "length" "4")]) -+ - + +-(define_expand "movsi_got" +- [(set (match_operand:SI 0 "gpc_reg_operand" "") +- (unspec:SI [(match_operand:SI 1 "got_operand" "") +- (match_dup 2)] UNSPEC_MOVSI_GOT))] +- "DEFAULT_ABI == ABI_V4 && flag_pic == 1" +- " +-{ +- if (GET_CODE (operands[1]) == CONST) +- { +- rtx offset = const0_rtx; +- HOST_WIDE_INT value; ++ +;; 128-bit logical operations expanders -+ + +- operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); +- value = INTVAL (offset); +- if (value != 0) +- { +- rtx tmp = (!can_create_pseudo_p () +- ? operands[0] +- : gen_reg_rtx (Pmode)); +- emit_insn (gen_movsi_got (tmp, operands[1])); +- emit_insn (gen_addsi3 (operands[0], tmp, offset)); +- DONE; +- } +- } +(define_expand "and<mode>3" + [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (and:BOOL_128 @@ -25745,27 +26286,62 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (clobber (match_scratch:CC 3 ""))])] + "" + "") -+ + +- operands[2] = rs6000_got_register (operands[1]); +-}") +(define_expand "ior<mode>3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") + (match_operand:BOOL_128 2 "vlogical_operand" "")))] + "" + "") -+ + +-(define_insn "*movsi_got_internal" +- [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") +- (match_operand:SI 2 "gpc_reg_operand" "b")] +- UNSPEC_MOVSI_GOT))] +- "DEFAULT_ABI == ABI_V4 && flag_pic == 1" +- "lwz %0,%a1@got(%2)" +- [(set_attr "type" "load")]) +(define_expand "xor<mode>3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") + (match_operand:BOOL_128 2 "vlogical_operand" "")))] + "" + "") -+ + +-;; Used by sched, shorten_branches and final when the GOT pseudo reg +-;; didn't get allocated to a hard register. +-(define_split +- [(set (match_operand:SI 0 "gpc_reg_operand" "") +- (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") +- (match_operand:SI 2 "memory_operand" "")] +- UNSPEC_MOVSI_GOT))] +- "DEFAULT_ABI == ABI_V4 +- && flag_pic == 1 +- && (reload_in_progress || reload_completed)" +- [(set (match_dup 0) (match_dup 2)) +- (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] +- UNSPEC_MOVSI_GOT))] +(define_expand "one_cmpl<mode>2" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))] + "" -+ "") -+ + "") + +-;; For SI, we special-case integers that can't be loaded in one insn. We +-;; do the load 16-bits at a time. We could do this by loading from memory, +-;; and this is even supposed to be faster, but it is simpler not to get +-;; integers in the TOC. +-(define_insn "movsi_low" +- [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") +- (match_operand 2 "" ""))))] +- "TARGET_MACHO && ! TARGET_64BIT" +- "lwz %0,lo16(%2)(%1)" +- [(set_attr "type" "load") +- (set_attr "length" "4")]) +(define_expand "nor<mode>3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (and:BOOL_128 @@ -25773,7 +26349,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + "" + "") -+ + +-(define_insn "*movsi_internal1" +- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h") +(define_expand "andc<mode>3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (and:BOOL_128 @@ -26101,9 +26679,80 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (const_string "16"))))]) + + - ;; Now define ways of moving data around. - - ;; Set up a register with a value from the GOT table ++;; Now define ways of moving data around. ++ ++;; Set up a register with a value from the GOT table ++ ++(define_expand "movsi_got" ++ [(set (match_operand:SI 0 "gpc_reg_operand" "") ++ (unspec:SI [(match_operand:SI 1 "got_operand" "") ++ (match_dup 2)] UNSPEC_MOVSI_GOT))] ++ "DEFAULT_ABI == ABI_V4 && flag_pic == 1" ++ " ++{ ++ if (GET_CODE (operands[1]) == CONST) ++ { ++ rtx offset = const0_rtx; ++ HOST_WIDE_INT value; ++ ++ operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); ++ value = INTVAL (offset); ++ if (value != 0) ++ { ++ rtx tmp = (!can_create_pseudo_p () ++ ? operands[0] ++ : gen_reg_rtx (Pmode)); ++ emit_insn (gen_movsi_got (tmp, operands[1])); ++ emit_insn (gen_addsi3 (operands[0], tmp, offset)); ++ DONE; ++ } ++ } ++ ++ operands[2] = rs6000_got_register (operands[1]); ++}") ++ ++(define_insn "*movsi_got_internal" ++ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") ++ (match_operand:SI 2 "gpc_reg_operand" "b")] ++ UNSPEC_MOVSI_GOT))] ++ "DEFAULT_ABI == ABI_V4 && flag_pic == 1" ++ "lwz %0,%a1@got(%2)" ++ [(set_attr "type" "load")]) ++ ++;; Used by sched, shorten_branches and final when the GOT pseudo reg ++;; didn't get allocated to a hard register. ++(define_split ++ [(set (match_operand:SI 0 "gpc_reg_operand" "") ++ (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") ++ (match_operand:SI 2 "memory_operand" "")] ++ UNSPEC_MOVSI_GOT))] ++ "DEFAULT_ABI == ABI_V4 ++ && flag_pic == 1 ++ && (reload_in_progress || reload_completed)" ++ [(set (match_dup 0) (match_dup 2)) ++ (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] ++ UNSPEC_MOVSI_GOT))] ++ "") ++ ++;; For SI, we special-case integers that can't be loaded in one insn. We ++;; do the load 16-bits at a time. We could do this by loading from memory, ++;; and this is even supposed to be faster, but it is simpler not to get ++;; integers in the TOC. ++(define_insn "movsi_low" ++ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") ++ (match_operand 2 "" ""))))] ++ "TARGET_MACHO && ! TARGET_64BIT" ++ "lwz %0,lo16(%2)(%1)" ++ [(set_attr "type" "load") ++ (set_attr "length" "4")]) ++ ++(define_insn "*movsi_internal1" ++ [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h") + (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))] + "!TARGET_SINGLE_FPU && + (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))" @@ -7765,7 +8274,31 @@ mt%0 %1 mt%0 %1 @@ -26292,14 +26941,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - (match_operand:SF 1 "any_operand" ""))] - "" - "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") - ++ +;; Move 32-bit binary/decimal floating point +(define_expand "mov<mode>" + [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "") + (match_operand:FMOVE32 1 "any_operand" ""))] + "<fmove_ok>" + "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") -+ + (define_split - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (match_operand:SF 1 "const_double_operand" ""))] @@ -26357,6 +27006,12 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #" - [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")]) +- +-(define_insn "*movsf_softfloat" +- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h") +- (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))] +- "(gpc_reg_operand (operands[0], SFmode) +- || gpc_reg_operand (operands[1], SFmode)) + [(set_attr_alternative "type" + [(const_string "*") + (if_then_else @@ -26400,12 +27055,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (const_string "*") + (const_string "*")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")]) - --(define_insn "*movsf_softfloat" -- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h") -- (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))] -- "(gpc_reg_operand (operands[0], SFmode) -- || gpc_reg_operand (operands[1], SFmode)) ++ +(define_insn "*mov<mode>_softfloat" + [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h") + (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))] @@ -26518,7 +27168,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ operands[2] = gen_lowpart (DImode, operands[0]); /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ -@@ -8099,22 +8793,19 @@ +@@ -8099,21 +8793,18 @@ ;; since the D-form version of the memory instructions does not need a GPR for ;; reloading. @@ -26541,17 +27191,20 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - lxsd%U1x %x0,%y1 stxsd%U0x %x1,%y0 - stxsd%U0x %x1,%y0 - xxlor %x0,%x1,%x1 - xxlor %x0,%x1,%x1 + xxlor %x0,%x1,%x1 xxlxor %x0,%x0,%x0 # - # @@ -8122,115 +8813,140 @@ # # #" - [(set_attr "type" "fpstore,fpload,fp,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,store,load,two,fp,fp,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")]) +- +-(define_insn "*movdf_softfloat32" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r") +- (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))] + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") @@ -26585,10 +27238,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (const_string "fp") + (const_string "*")]) + (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")]) - --(define_insn "*movdf_softfloat32" -- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r") -- (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))] ++ +(define_insn "*mov<mode>_softfloat32" + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r") + (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] @@ -26625,8 +27275,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - DONE; -}) - - ; ld/std require word-aligned displacements -> 'Y' constraint. - ; List Y->r and r->Y before r->r for reload. +-; ld/std require word-aligned displacements -> 'Y' constraint. +-; List Y->r and r->Y before r->r for reload. -(define_insn "*movdf_hardfloat64_mfpgpr" - [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d") - (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))] @@ -26634,13 +27284,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - && TARGET_DOUBLE_FLOAT - && (gpc_reg_operand (operands[0], DFmode) - || gpc_reg_operand (operands[1], DFmode))" -+(define_insn "*mov<mode>_hardfloat64" -+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm") -+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))] -+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT -+ && (gpc_reg_operand (operands[0], <MODE>mode) -+ || gpc_reg_operand (operands[1], <MODE>mode))" - "@ +- "@ - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 @@ -26650,13 +27294,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - lxsd%U1x %x0,%y1 - stxsd%U0x %x1,%y0 - stxsd%U0x %x1,%y0 - stfd%U0%X0 %1,%0 - lfd%U1%X1 %0,%1 - fmr %0,%1 -+ lxsd%U1x %x0,%y1 -+ stxsd%U0x %x1,%y0 -+ xxlor %x0,%x1,%x1 - xxlxor %x0,%x0,%x0 +- stfd%U0%X0 %1,%0 +- lfd%U1%X1 %0,%1 +- fmr %0,%1 +- xxlxor %x0,%x0,%x0 - mt%0 %1 - mf%1 %0 - nop @@ -26668,8 +27309,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")]) - --; ld/std require word-aligned displacements -> 'Y' constraint. --; List Y->r and r->Y before r->r for reload. + ; ld/std require word-aligned displacements -> 'Y' constraint. + ; List Y->r and r->Y before r->r for reload. -(define_insn "*movdf_hardfloat64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,Y,r,!r,ws,?wa,Z,?Z,ws,?wa,wa,*c*l,!r,*h,!r,!r,!r") - (match_operand:DF 1 "input_operand" "d,m,d,r,Y,r,Z,Z,ws,wa,ws,wa,j,r,h,0,G,H,F"))] @@ -26677,20 +27318,29 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - && TARGET_DOUBLE_FLOAT - && (gpc_reg_operand (operands[0], DFmode) - || gpc_reg_operand (operands[1], DFmode))" -- "@ -- stfd%U0%X0 %1,%0 -- lfd%U1%X1 %0,%1 -- fmr %0,%1 - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 -- lxsd%U1x %x0,%y1 ++(define_insn "*mov<mode>_hardfloat64" ++ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm") ++ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))] ++ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ++ && (gpc_reg_operand (operands[0], <MODE>mode) ++ || gpc_reg_operand (operands[1], <MODE>mode))" + "@ + stfd%U0%X0 %1,%0 + lfd%U1%X1 %0,%1 + fmr %0,%1 +- std%U0%X0 %1,%0 +- ld%U1%X1 %0,%1 +- mr %0,%1 - lxsd%U1x %x0,%y1 + lxsd%U1x %x0,%y1 + stxsd%U0x %x1,%y0 - stxsd%U0x %x1,%y0 -- stxsd%U0x %x1,%y0 -- xxlor %x0,%x1,%x1 - xxlor %x0,%x1,%x1 -- xxlxor %x0,%x0,%x0 + xxlor %x0,%x1,%x1 + xxlxor %x0,%x0,%x0 ++ std%U0%X0 %1,%0 ++ ld%U1%X1 %0,%1 ++ mr %0,%1 mt%0 %1 mf%1 %0 nop @@ -26699,6 +27349,10 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - #" - [(set_attr "type" "fpstore,fpload,fp,store,load,*,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,mtjmpr,mfjmpr,*,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")]) +- +-(define_insn "*movdf_softfloat64" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h") +- (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))] + # + mftgpr %0,%1 + mffgpr %0,%1 @@ -26756,10 +27410,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (const_string "mftgpr") + (const_string "mffgpr")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")]) - --(define_insn "*movdf_softfloat64" -- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h") -- (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))] ++ +(define_insn "*mov<mode>_softfloat64" + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h") + (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))] @@ -27143,7 +27794,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 1))] " -@@ -8607,14 +9598,15 @@ +@@ -8607,38 +9598,15 @@ [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "") (match_operand:DIFD 1 "input_operand" ""))] "reload_completed && !TARGET_POWERPC64 @@ -27157,20 +27808,44 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d") - (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))] - "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS -+(define_insn "*movdi_internal64" +- && (gpc_reg_operand (operands[0], DImode) +- || gpc_reg_operand (operands[1], DImode))" +- "@ +- std%U0%X0 %1,%0 +- ld%U1%X1 %0,%1 +- mr %0,%1 +- li %0,%1 +- lis %0,%v1 +- # +- stfd%U0%X0 %1,%0 +- lfd%U1%X1 %0,%1 +- fmr %0,%1 +- mf%1 %0 +- mt%0 %1 +- nop +- mftgpr %0,%1 +- mffgpr %0,%1" +- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr") +- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")]) +- + (define_insn "*movdi_internal64" +- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa") +- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))] +- "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS) + [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm") + (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))] + "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" "@ -@@ -8631,33 +9623,52 @@ +@@ -8654,9 +9622,52 @@ + mf%1 %0 mt%0 %1 nop - mftgpr %0,%1 -- mffgpr %0,%1" -- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr") -- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")]) +- xxlxor %x0,%x0,%x0" +- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple") +- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) ++ mftgpr %0,%1 + mffgpr %0,%1 + mfvsrd %0,%x1 + mtvsrd %x0,%1" @@ -27217,32 +27892,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + (const_string "mffgpr")]) + (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")]) --(define_insn "*movdi_internal64" -- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa") -- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))] -- "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS) -- && (gpc_reg_operand (operands[0], DImode) -- || gpc_reg_operand (operands[1], DImode))" -- "@ -- std%U0%X0 %1,%0 -- ld%U1%X1 %0,%1 -- mr %0,%1 -- li %0,%1 -- lis %0,%v1 -- # -- stfd%U0%X0 %1,%0 -- lfd%U1%X1 %0,%1 -- fmr %0,%1 -- mf%1 %0 -- mt%0 %1 -- nop -- xxlxor %x0,%x0,%x0" -- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple") -- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) -- ;; immediate value valid for a single instruction hiding in a const_double (define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -8719,14 +9730,16 @@ FAIL; }") @@ -27522,16 +28173,73 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ default: gcc_unreachable (); } -@@ -10698,136 +11718,7 @@ - [(set_attr "type" "branch") - (set_attr "length" "4,8")]) - +@@ -10641,192 +11661,63 @@ + (define_insn "*call_local64" + [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) + (match_operand 1 "" "g,g")) +- (use (match_operand:SI 2 "immediate_operand" "O,n")) +- (clobber (reg:SI LR_REGNO))] +- "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" +- "* +-{ +- if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) +- output_asm_insn (\"crxor 6,6,6\", operands); +- +- else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) +- output_asm_insn (\"creqv 6,6,6\", operands); +- +- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; +-}" +- [(set_attr "type" "branch") +- (set_attr "length" "4,8")]) +- +-(define_insn "*call_value_local32" +- [(set (match_operand 0 "" "") +- (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) +- (match_operand 2 "" "g,g"))) +- (use (match_operand:SI 3 "immediate_operand" "O,n")) +- (clobber (reg:SI LR_REGNO))] +- "(INTVAL (operands[3]) & CALL_LONG) == 0" +- "* +-{ +- if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) +- output_asm_insn (\"crxor 6,6,6\", operands); +- +- else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) +- output_asm_insn (\"creqv 6,6,6\", operands); +- +- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; +-}" +- [(set_attr "type" "branch") +- (set_attr "length" "4,8")]) +- +- +-(define_insn "*call_value_local64" +- [(set (match_operand 0 "" "") +- (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) +- (match_operand 2 "" "g,g"))) +- (use (match_operand:SI 3 "immediate_operand" "O,n")) +- (clobber (reg:SI LR_REGNO))] +- "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" +- "* +-{ +- if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) +- output_asm_insn (\"crxor 6,6,6\", operands); +- +- else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) +- output_asm_insn (\"creqv 6,6,6\", operands); +- +- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; +-}" +- [(set_attr "type" "branch") +- (set_attr "length" "4,8")]) +- -;; Call to indirect functions with the AIX abi using a 3 word descriptor. -;; Operand0 is the addresss of the function to call -;; Operand1 is the flag for System V.4 for unprototyped or FP registers -;; Operand2 is the location in the function descriptor to load r2 from -;; Operand3 is the stack location to hold the current TOC pointer - +- -(define_insn "call_indirect_aix<ptrsize>" - [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l")) - (match_operand 1 "" "g,g")) @@ -27622,43 +28330,89 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) - (match_operand 1 "" "g")) - (use (match_operand:SI 2 "immediate_operand" "O")) -- (clobber (reg:SI LR_REGNO))] ++ (use (match_operand:SI 2 "immediate_operand" "O,n")) + (clobber (reg:SI LR_REGNO))] - "TARGET_64BIT - && DEFAULT_ABI == ABI_AIX - && (INTVAL (operands[2]) & CALL_LONG) == 0" - "bl %z0\;nop" -- [(set_attr "type" "branch") ++ "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" ++ "* ++{ ++ if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) ++ output_asm_insn (\"crxor 6,6,6\", operands); ++ ++ else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) ++ output_asm_insn (\"creqv 6,6,6\", operands); ++ ++ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; ++}" + [(set_attr "type" "branch") - (set_attr "length" "8")]) -- ++ (set_attr "length" "4,8")]) + -(define_insn "*call_value_nonlocal_aix32" -- [(set (match_operand 0 "" "") ++(define_insn "*call_value_local32" + [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) - (match_operand 2 "" "g"))) - (use (match_operand:SI 3 "immediate_operand" "O")) -- (clobber (reg:SI LR_REGNO))] ++ (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) ++ (match_operand 2 "" "g,g"))) ++ (use (match_operand:SI 3 "immediate_operand" "O,n")) + (clobber (reg:SI LR_REGNO))] - "TARGET_32BIT - && DEFAULT_ABI == ABI_AIX - && (INTVAL (operands[3]) & CALL_LONG) == 0" - "bl %z1\;nop" -- [(set_attr "type" "branch") ++ "(INTVAL (operands[3]) & CALL_LONG) == 0" ++ "* ++{ ++ if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) ++ output_asm_insn (\"crxor 6,6,6\", operands); ++ ++ else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) ++ output_asm_insn (\"creqv 6,6,6\", operands); ++ ++ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; ++}" + [(set_attr "type" "branch") - (set_attr "length" "8")]) -- ++ (set_attr "length" "4,8")]) + -(define_insn "*call_value_nonlocal_aix64" -- [(set (match_operand 0 "" "") ++ ++(define_insn "*call_value_local64" + [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) - (match_operand 2 "" "g"))) - (use (match_operand:SI 3 "immediate_operand" "O")) -- (clobber (reg:SI LR_REGNO))] ++ (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) ++ (match_operand 2 "" "g,g"))) ++ (use (match_operand:SI 3 "immediate_operand" "O,n")) + (clobber (reg:SI LR_REGNO))] - "TARGET_64BIT - && DEFAULT_ABI == ABI_AIX - && (INTVAL (operands[3]) & CALL_LONG) == 0" - "bl %z1\;nop" -- [(set_attr "type" "branch") ++ "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" ++ "* ++{ ++ if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) ++ output_asm_insn (\"crxor 6,6,6\", operands); ++ ++ else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) ++ output_asm_insn (\"creqv 6,6,6\", operands); ++ ++ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; ++}" + [(set_attr "type" "branch") - (set_attr "length" "8")]) -- ++ (set_attr "length" "4,8")]) ++ + ;; A function pointer under System V is just a normal pointer ;; operands[0] is the function pointer - ;; operands[1] is the stack size to clean up @@ -11009,6 +11900,104 @@ [(set_attr "type" "branch,branch") (set_attr "length" "4,8")]) @@ -27764,7 +28518,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ ;; Call subroutine returning any type. (define_expand "untyped_call" [(parallel [(call (match_operand 0 "" "") -@@ -11056,8 +12045,41 @@ +@@ -11056,6 +12045,39 @@ gcc_assert (GET_CODE (operands[1]) == CONST_INT); operands[0] = XEXP (operands[0], 0); @@ -27774,8 +28528,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]); + DONE; + } - }") - ++}") ++ +(define_expand "sibcall_value" + [(parallel [(set (match_operand 0 "register_operand" "") + (call (mem:SI (match_operand 1 "address_operand" "")) @@ -27801,11 +28555,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]); + DONE; + } -+}") -+ + }") + ;; this and similar patterns must be marked as using LR, otherwise - ;; dataflow will try to delete the store into it. This is true - ;; even when the actual reg to jump to is in CTR, when LR was @@ -11123,7 +12145,6 @@ [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -28062,14 +28814,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ (define_expand "rs6000_get_timebase" [(use (match_operand:DI 0 "gpc_reg_operand" ""))] "" -@@ -14020,7 +15074,44 @@ +@@ -14020,6 +15074,43 @@ }) +;; Power8 fusion support for fusing an addis instruction with a D-form load of +;; a GPR. The addis instruction must be adjacent to the load, and use the same +;; register that is being loaded. The fused ops must be physically adjacent. - ++ +;; We use define_peephole for the actual addis/load, and the register used to +;; hold the addis value must be the same as the register being loaded. We use +;; define_peephole2 to change the register used for addis to be the register @@ -28103,16 +28855,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +}) + + -+ + (include "sync.md") (include "vector.md") - (include "vsx.md") @@ -14028,3 +15119,5 @@ (include "spe.md") (include "dfp.md") (include "paired.md") +(include "crypto.md") +(include "htm.md") +Index: b/src/gcc/config/rs6000/option-defaults.h +=================================================================== --- a/src/gcc/config/rs6000/option-defaults.h +++ b/src/gcc/config/rs6000/option-defaults.h @@ -54,6 +54,7 @@ @@ -28123,6 +28876,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ {"tune", "%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}" }, \ {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \ {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \ +Index: b/src/gcc/config/rs6000/rs6000-opts.h +=================================================================== --- a/src/gcc/config/rs6000/rs6000-opts.h +++ b/src/gcc/config/rs6000/rs6000-opts.h @@ -59,7 +59,8 @@ @@ -28161,9 +28916,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ VECTOR_PAIRED, /* Use paired floating point for vectors */ VECTOR_SPE, /* Use SPE for vector processing */ VECTOR_OTHER /* Some other vector unit */ +Index: b/src/gcc/config/rs6000/driver-rs6000.c +=================================================================== --- a/src/gcc/config/rs6000/driver-rs6000.c +++ b/src/gcc/config/rs6000/driver-rs6000.c -@@ -167,7 +167,7 @@ +@@ -171,7 +171,7 @@ if (fd != -1) { @@ -28172,6 +28929,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ ElfW(auxv_t) *av; ssize_t n; +Index: b/src/gcc/config/rs6000/altivec.h +=================================================================== --- a/src/gcc/config/rs6000/altivec.h +++ b/src/gcc/config/rs6000/altivec.h @@ -321,6 +321,42 @@ @@ -28217,6 +28976,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Predicates. For C++, we use templates in order to allow non-parenthesized arguments. For C, instead, we use macros since non-parenthesized arguments were +Index: b/src/gcc/config/rs6000/sysv4.h +=================================================================== --- a/src/gcc/config/rs6000/sysv4.h +++ b/src/gcc/config/rs6000/sysv4.h @@ -45,7 +45,7 @@ @@ -28286,6 +29047,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big)" +Index: b/src/libgo/configure +=================================================================== --- a/src/libgo/configure +++ b/src/libgo/configure @@ -6501,7 +6501,7 @@ @@ -28339,6 +29102,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/libgo/testsuite/gotest +=================================================================== --- a/src/libgo/testsuite/gotest +++ b/src/libgo/testsuite/gotest @@ -369,7 +369,7 @@ @@ -28350,6 +29115,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ esac symtogo='sed -e s/_test/XXXtest/ -e s/.*_\([^_]*\.\)/\1/ -e s/XXXtest/_test/' +Index: b/src/libgo/config/libtool.m4 +=================================================================== --- a/src/libgo/config/libtool.m4 +++ b/src/libgo/config/libtool.m4 @@ -1225,7 +1225,7 @@ @@ -28385,6 +29152,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*|s390*-*tpf*) +Index: b/src/config.sub +=================================================================== --- a/src/config.sub +++ b/src/config.sub @@ -1,10 +1,8 @@ @@ -28527,7 +29296,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ or32-*) os=-coff ;; ---- a/src/ChangeLog.ibm +Index: b/src/ChangeLog.ibm +=================================================================== +--- /dev/null +++ b/src/ChangeLog.ibm @@ -0,0 +1,106 @@ +2013-12-10 Alan Modra <amodra@gmail.com> @@ -28636,6 +29407,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + * libtool.m4 (_LT_ENABLE_LOCK <ld -m flags>): Remove non-canonical + ppc host match. Support little-endian powerpc linux hosts. + +Index: b/src/libobjc/configure +=================================================================== --- a/src/libobjc/configure +++ b/src/libobjc/configure @@ -6056,7 +6056,7 @@ @@ -28698,6 +29471,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ @interface Frob @end @implementation Frob +Index: b/src/libgfortran/configure +=================================================================== --- a/src/libgfortran/configure +++ b/src/libgfortran/configure @@ -8062,7 +8062,7 @@ @@ -28751,6 +29526,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H +Index: b/src/libffi/configure +=================================================================== --- a/src/libffi/configure +++ b/src/libffi/configure @@ -613,6 +613,7 @@ @@ -28864,6 +29641,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5 $as_echo_n "checking whether byte ordering is bigendian... " >&6; } if test "${ac_cv_c_bigendian+set}" = set; then : +Index: b/src/libffi/Makefile.in +=================================================================== --- a/src/libffi/Makefile.in +++ b/src/libffi/Makefile.in @@ -48,10 +48,10 @@ @@ -28954,6 +29733,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ @AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/linux64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/linux64_closure.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ppc_closure.Plo@am__quote@ +Index: b/src/libffi/include/ffi.h.in +=================================================================== --- a/src/libffi/include/ffi.h.in +++ b/src/libffi/include/ffi.h.in @@ -207,6 +207,11 @@ @@ -28968,6 +29749,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Used internally, but overridden by some architectures */ ffi_status ffi_prep_cif_core(ffi_cif *cif, ffi_abi abi, +Index: b/src/libffi/include/Makefile.in +=================================================================== --- a/src/libffi/include/Makefile.in +++ b/src/libffi/include/Makefile.in @@ -113,6 +113,7 @@ @@ -28978,6 +29761,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ +Index: b/src/libffi/fficonfig.h.in +=================================================================== --- a/src/libffi/fficonfig.h.in +++ b/src/libffi/fficonfig.h.in @@ -73,6 +73,9 @@ @@ -28990,6 +29775,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Define to 1 if you have the `memcpy' function. */ #undef HAVE_MEMCPY +Index: b/src/libffi/src/powerpc/ppc_closure.S +=================================================================== --- a/src/libffi/src/powerpc/ppc_closure.S +++ b/src/libffi/src/powerpc/ppc_closure.S @@ -31,7 +31,7 @@ @@ -29020,6 +29807,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ .section .note.GNU-stack,"",@progbits #endif +#endif +Index: b/src/libffi/src/powerpc/ffitarget.h +=================================================================== --- a/src/libffi/src/powerpc/ffitarget.h +++ b/src/libffi/src/powerpc/ffitarget.h @@ -60,45 +60,76 @@ @@ -29058,14 +29847,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ FFI_DEFAULT_ABI = FFI_DARWIN, -#endif + FFI_LAST_ABI - --#ifdef POWERPC_FREEBSD -- FFI_SYSV, -- FFI_GCC_SYSV, -- FFI_LINUX64, -- FFI_LINUX, -- FFI_LINUX_SOFT_FLOAT, -- FFI_DEFAULT_ABI = FFI_SYSV, ++ +#else + /* The FFI_COMPAT values are used by old code. Since libffi may be + a shared library we have to support old values for backwards @@ -29094,7 +29876,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +# endif + ), + FFI_LAST_ABI = 12 -+ + +-#ifdef POWERPC_FREEBSD +- FFI_SYSV, +- FFI_GCC_SYSV, +- FFI_LINUX64, +- FFI_LINUX, +- FFI_LINUX_SOFT_FLOAT, +- FFI_DEFAULT_ABI = FFI_SYSV, +# else + /* This bit, always set in new code, must not be set in any of the + old FFI_COMPAT values that might be used for 32-bit linux/sysv/bsd. */ @@ -29171,6 +29960,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #endif #ifndef LIBFFI_ASM +Index: b/src/libffi/src/powerpc/ffi.c +=================================================================== --- a/src/libffi/src/powerpc/ffi.c +++ b/src/libffi/src/powerpc/ffi.c @@ -1,5 +1,6 @@ @@ -29187,10 +29978,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -#include <ffi.h> -#include <ffi_common.h> -+#include "ffi.h" -+#include "ffi_common.h" -+#include "ffi_powerpc.h" - +- -#include <stdlib.h> -#include <stdio.h> - @@ -29252,11 +30040,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - -void -ffi_prep_args_SYSV (extended_cif *ecif, unsigned *const stack) -+#if HAVE_LONG_DOUBLE_VARIANT -+/* Adjust ffi_type_longdouble. */ -+void FFI_HIDDEN -+ffi_prep_types (ffi_abi abi) - { +-{ - const unsigned bytes = ecif->cif->bytes; - const unsigned flags = ecif->cif->flags; - @@ -29539,14 +30323,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - <= stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS); -#endif - FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS || intarg_count <= 4); -+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE -+# ifdef POWERPC64 -+ ffi_prep_types_linux64 (abi); -+# else -+ ffi_prep_types_sysv (abi); -+# endif -+# endif - } +-} - -/* About the LINUX64 ABI. */ -enum { @@ -29588,10 +30365,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - |--------------------------------------------| <<< ffi_call_LINUX64 - -*/ -- --void FFI_HIDDEN ++#include "ffi.h" ++#include "ffi_common.h" ++#include "ffi_powerpc.h" + ++#if HAVE_LONG_DOUBLE_VARIANT ++/* Adjust ffi_type_longdouble. */ + void FFI_HIDDEN -ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack) --{ ++ffi_prep_types (ffi_abi abi) + { - const unsigned long bytes = ecif->cif->bytes; - const unsigned long flags = ecif->cif->flags; - @@ -29701,8 +30484,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - FFI_ASSERT (__LDBL_MANT_DIG__ == 106); - FFI_ASSERT (flags & FLAG_FP_ARGUMENTS); - break; - #endif - +-#endif +- - case FFI_TYPE_STRUCT: - words = ((*ptr)->size + 7) / 8; - if (next_arg.ul >= gpr_base.ul && next_arg.ul + words > gpr_end.ul) @@ -29764,10 +30547,18 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS - || (next_arg.ul >= gpr_base.ul - && next_arg.ul <= gpr_base.ul + 4)); --} -- ++# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE ++# ifdef POWERPC64 ++ ffi_prep_types_linux64 (abi); ++# else ++ ffi_prep_types_sysv (abi); ++# endif ++# endif + } - - ++#endif + /* Perform machine dependent cif processing */ -ffi_status +ffi_status FFI_HIDDEN @@ -29834,14 +30625,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ -#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE - if (type == FFI_TYPE_LONGDOUBLE) - type = FFI_TYPE_STRUCT; -+#ifdef POWERPC64 -+ return ffi_prep_cif_linux64 (cif); -+#else -+ return ffi_prep_cif_sysv (cif); - #endif +-#endif - } -+} - +- - switch (type) - { -#ifndef __NO_FPRS__ @@ -29849,16 +30635,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - case FFI_TYPE_LONGDOUBLE: - flags |= FLAG_RETURNS_128BITS; - /* Fall through. */ -+ffi_status FFI_HIDDEN -+ffi_prep_cif_machdep_var (ffi_cif *cif, -+ unsigned int nfixedargs MAYBE_UNUSED, -+ unsigned int ntotalargs MAYBE_UNUSED) -+{ -+#ifdef POWERPC64 -+ return ffi_prep_cif_linux64_var (cif, nfixedargs, ntotalargs); -+#else -+ return ffi_prep_cif_sysv (cif); - #endif +-#endif - case FFI_TYPE_DOUBLE: - flags |= FLAG_RETURNS_64BITS; - /* Fall through. */ @@ -30060,8 +30837,13 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - /* Space for the FPR registers, if needed. */ - if (fparg_count != 0) - bytes += NUM_FPR_ARG_REGISTERS * sizeof (double); --#endif -- ++#ifdef POWERPC64 ++ return ffi_prep_cif_linux64 (cif); ++#else ++ return ffi_prep_cif_sysv (cif); + #endif ++} + - /* Stack space. */ - if (intarg_count > NUM_GPR_ARG_REGISTERS) - bytes += (intarg_count - NUM_GPR_ARG_REGISTERS) * sizeof (int); @@ -30076,7 +30858,16 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - /* Space for the FPR registers, if needed. */ - if (fparg_count != 0) - bytes += NUM_FPR_ARG_REGISTERS64 * sizeof (double); --#endif ++ffi_status FFI_HIDDEN ++ffi_prep_cif_machdep_var (ffi_cif *cif, ++ unsigned int nfixedargs MAYBE_UNUSED, ++ unsigned int ntotalargs MAYBE_UNUSED) ++{ ++#ifdef POWERPC64 ++ return ffi_prep_cif_linux64_var (cif, nfixedargs, ntotalargs); ++#else ++ return ffi_prep_cif_sysv (cif); + #endif - - /* Stack space. */ - if (intarg_count > NUM_GPR_ARG_REGISTERS64) @@ -30250,15 +31041,14 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - - /* Flush the icache. */ - flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE); -+ return ffi_prep_closure_loc_sysv (closure, cif, fun, user_data, codeloc); - #endif +-#endif - - closure->cif = cif; - closure->fun = fun; - closure->user_data = user_data; - - return FFI_OK; - } +-} - -typedef union -{ @@ -30451,7 +31241,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - pst++; - } - break; --#endif ++ return ffi_prep_closure_loc_sysv (closure, cif, fun, user_data, codeloc); + #endif - case FFI_TYPE_SINT16: - case FFI_TYPE_UINT16: -#ifndef __LITTLE_ENDIAN__ @@ -30704,7 +31495,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - - /* Tell ffi_closure_LINUX64 how to perform return type promotions. */ - return cif->rtype->type; --} + } +Index: b/src/libffi/src/powerpc/sysv.S +=================================================================== --- a/src/libffi/src/powerpc/sysv.S +++ b/src/libffi/src/powerpc/sysv.S @@ -30,7 +30,7 @@ @@ -30726,6 +31519,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ .section .note.GNU-stack,"",@progbits #endif +#endif +Index: b/src/libffi/src/powerpc/linux64_closure.S +=================================================================== --- a/src/libffi/src/powerpc/linux64_closure.S +++ b/src/libffi/src/powerpc/linux64_closure.S @@ -30,18 +30,25 @@ @@ -30787,7 +31582,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ - std %r6, 72(%r1) +# if _CALL_ELF == 2 + ld %r12, FFI_TRAMPOLINE_SIZE(%r11) # closure->cif - mflr %r0 ++ mflr %r0 + lwz %r12, 28(%r12) # cif->flags + mtcrf 0x40, %r12 + addi %r12, %r1, PARMSAVE @@ -30807,15 +31602,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + std %r8, 40(%r12) + std %r9, 48(%r12) + std %r10, 56(%r12) - -- std %r7, 80(%r1) -- std %r8, 88(%r1) -- std %r9, 96(%r1) -- std %r10, 104(%r1) ++ + # load up the pointer to the parm save area + mr %r5, %r12 +# else -+ mflr %r0 + mflr %r0 + # Save general regs into parm save area + # This is the parameter save area set up by our caller. + std %r3, PARMSAVE+0(%r1) @@ -30826,7 +31617,11 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + std %r8, PARMSAVE+40(%r1) + std %r9, PARMSAVE+48(%r1) + std %r10, PARMSAVE+56(%r1) -+ + +- std %r7, 80(%r1) +- std %r8, 88(%r1) +- std %r9, 96(%r1) +- std %r10, 104(%r1) std %r0, 16(%r1) - # mandatory 48 bytes special reg save area + 64 bytes parm save area @@ -31073,8 +31868,7 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ mtlr %r0 - addi %r1, %r1, 240 + addi %r1, %r1, STACKFRAME - blr --# esac ++ blr +# case FFI_V2_TYPE_FLOAT_HOMOG + lfs %f1, RETVAL+0(%r1) + lfs %f2, RETVAL+4(%r1) @@ -31127,7 +31921,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + sldi %r5, %r5, 3 + addi %r1, %r1, STACKFRAME + srd %r3, %r3, %r5 -+ blr + blr +-# esac +# endif + .LFE1: @@ -31166,7 +31961,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ .section .note.GNU-stack,"",@progbits +# endif #endif ---- a/src/libffi/src/powerpc/ffi_powerpc.h +Index: b/src/libffi/src/powerpc/ffi_powerpc.h +=================================================================== +--- /dev/null +++ b/src/libffi/src/powerpc/ffi_powerpc.h @@ -0,0 +1,77 @@ +/* ----------------------------------------------------------------------- @@ -31246,7 +32043,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ +void FFI_HIDDEN ffi_prep_args64 (extended_cif *, unsigned long *const); +int FFI_HIDDEN ffi_closure_helper_LINUX64 (ffi_closure *, void *, + unsigned long *, ffi_dblfl *); ---- a/src/libffi/src/powerpc/ffi_sysv.c +Index: b/src/libffi/src/powerpc/ffi_sysv.c +=================================================================== +--- /dev/null +++ b/src/libffi/src/powerpc/ffi_sysv.c @@ -0,0 +1,931 @@ +/* ----------------------------------------------------------------------- @@ -32180,6 +32979,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + return rtypenum; +} +#endif +Index: b/src/libffi/src/powerpc/linux64.S +=================================================================== --- a/src/libffi/src/powerpc/linux64.S +++ b/src/libffi/src/powerpc/linux64.S @@ -29,18 +29,25 @@ @@ -32355,7 +33156,9 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ .section .note.GNU-stack,"",@progbits +# endif #endif ---- a/src/libffi/src/powerpc/ffi_linux64.c +Index: b/src/libffi/src/powerpc/ffi_linux64.c +=================================================================== +--- /dev/null +++ b/src/libffi/src/powerpc/ffi_linux64.c @@ -0,0 +1,942 @@ +/* ----------------------------------------------------------------------- @@ -33300,6 +34103,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ + return cif->rtype->type; +} +#endif +Index: b/src/libffi/src/types.c +=================================================================== --- a/src/libffi/src/types.c +++ b/src/libffi/src/types.c @@ -44,6 +44,17 @@ @@ -33330,6 +34135,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ FFI_TYPEDEF(longdouble, long double, FFI_TYPE_LONGDOUBLE); +# endif #endif +Index: b/src/libffi/src/prep_cif.c +=================================================================== --- a/src/libffi/src/prep_cif.c +++ b/src/libffi/src/prep_cif.c @@ -126,6 +126,10 @@ @@ -33343,6 +34150,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* Initialize the return type if necessary */ if ((cif->rtype->size == 0) && (initialize_aggregate(cif->rtype) != FFI_OK)) return FFI_BAD_TYPEDEF; +Index: b/src/libffi/testsuite/Makefile.in +=================================================================== --- a/src/libffi/testsuite/Makefile.in +++ b/src/libffi/testsuite/Makefile.in @@ -88,6 +88,7 @@ @@ -33353,6 +34162,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ +Index: b/src/libffi/testsuite/libffi.call/cls_double_va.c +=================================================================== --- a/src/libffi/testsuite/libffi.call/cls_double_va.c +++ b/src/libffi/testsuite/libffi.call/cls_double_va.c @@ -38,26 +38,24 @@ @@ -33390,6 +34201,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ exit(0); } +Index: b/src/libffi/testsuite/libffi.call/cls_longdouble_va.c +=================================================================== --- a/src/libffi/testsuite/libffi.call/cls_longdouble_va.c +++ b/src/libffi/testsuite/libffi.call/cls_longdouble_va.c @@ -38,27 +38,24 @@ @@ -33428,6 +34241,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ exit(0); } +Index: b/src/libffi/configure.ac +=================================================================== --- a/src/libffi/configure.ac +++ b/src/libffi/configure.ac @@ -65,6 +65,7 @@ @@ -33478,6 +34293,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ AC_C_BIGENDIAN +Index: b/src/libffi/doc/libffi.texi +=================================================================== --- a/src/libffi/doc/libffi.texi +++ b/src/libffi/doc/libffi.texi @@ -184,11 +184,11 @@ @@ -33576,6 +34393,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ /* rc now holds the result of the call to fputs */ @} @} +Index: b/src/libffi/Makefile.am +=================================================================== --- a/src/libffi/Makefile.am +++ b/src/libffi/Makefile.am @@ -15,10 +15,12 @@ @@ -33613,6 +34432,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ endif if AARCH64 nodist_libffi_la_SOURCES += src/aarch64/sysv.S src/aarch64/ffi.c +Index: b/src/libffi/man/Makefile.in +=================================================================== --- a/src/libffi/man/Makefile.in +++ b/src/libffi/man/Makefile.in @@ -111,6 +111,7 @@ @@ -33623,6 +34444,8 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ +Index: b/src/libssp/configure +=================================================================== --- a/src/libssp/configure +++ b/src/libssp/configure @@ -6385,7 +6385,7 @@ @@ -33676,13 +34499,17 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@205847 \ #include "confdefs.h" #if HAVE_DLFCN_H ---- a/src/libcpp/ChangeLog.ibm +Index: b/src/libcpp/ChangeLog.ibm +=================================================================== +--- /dev/null +++ b/src/libcpp/ChangeLog.ibm @@ -0,0 +1,4 @@ +2013-11-18 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * lex.c (search_line_fast): Correct for little endian. + +Index: b/src/libcpp/lex.c +=================================================================== --- a/src/libcpp/lex.c +++ b/src/libcpp/lex.c @@ -559,8 +559,13 @@ diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff index 61473e2..c6863a9 100644 --- a/debian/patches/svn-updates.diff +++ b/debian/patches/svn-updates.diff @@ -1,10 +1,10 @@ -# DP: updates from the 4.8 branch upto 20140110 (r206513). +# DP: updates from the 4.8 branch upto 20140112 (r206564). last_updated() { cat > ${dir}LAST_UPDATED <<EOF -Mon Jan 10 09:52:42 CET 2014 -Mon Jan 10 08:52:42 UTC 2014 (revision 206513) +Sun Jan 12 12:14:23 CET 2014 +Sun Jan 12 11:14:23 UTC 2014 (revision 206564) EOF } @@ -4627,7 +4627,7 @@ Index: gcc/DATESTAMP +++ b/src/gcc/DATESTAMP (.../branches/gcc-4_8-branch) @@ -1 +1 @@ -20131016 -+20140110 ++20140112 Index: gcc/value-prof.c =================================================================== --- a/src/gcc/value-prof.c (.../tags/gcc_4_8_2_release) @@ -4907,12 +4907,6 @@ Index: gcc/reorg.c reorg_redirect_jump (delay_insn, target_label); next = insn; continue; -Index: gcc/DEV-PHASE -=================================================================== ---- a/src/gcc/DEV-PHASE (.../tags/gcc_4_8_2_release) -+++ b/src/gcc/DEV-PHASE (.../branches/gcc-4_8-branch) -@@ -0,0 +1 @@ -+prerelease Index: gcc/tree-ssa-sccvn.c =================================================================== --- a/src/gcc/tree-ssa-sccvn.c (.../tags/gcc_4_8_2_release) @@ -4948,6 +4942,11 @@ Index: gcc/ChangeLog --- a/src/gcc/ChangeLog (.../tags/gcc_4_8_2_release) +++ b/src/gcc/ChangeLog (.../branches/gcc-4_8-branch) @@ -1,3 +1,1030 @@ ++2014-01-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> ++ ++ * config/s390/s390.c (s390_expand_tbegin): Remove jump over CC ++ extraction in good case. ++ +2014-01-10 Huacai Chen <chenhc@lemote.com> + + * config/mips/driver-native.c (host_detect_local_cpu): Handle new @@ -5970,15 +5969,10 @@ Index: gcc/ChangeLog + * config/i386/i386.c (ix86_option_override_internal): Enable FMA4 + for AMD bdver3. + -+2013-10-16 Jakub Jelinek <jakub@redhat.com> -+ -+ * BASE-VER: Set to 4.8.3. -+ * DEV-PHASE: Set to prerelease. -+ 2013-10-16 Release Manager * GCC 4.8.2 released. -@@ -639,7 +1666,7 @@ +@@ -639,7 +1671,7 @@ 2013-07-31 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Backport from mainline @@ -10733,6 +10727,17 @@ Index: gcc/testsuite/gcc.dg/20050922-1.c #if __INT_MAX__ == 2147483647 typedef unsigned int uint32_t; +Index: gcc/testsuite/gcc.dg/pr46309.c +=================================================================== +--- a/src/gcc/testsuite/gcc.dg/pr46309.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.dg/pr46309.c (.../branches/gcc-4_8-branch) +@@ -1,5 +1,5 @@ + /* PR tree-optimization/46309 */ +-/* { dg-do compile } */ ++/* { dg-do compile { target { ! { cris*-*-* } } } } */ + /* { dg-options "-O2 -fdump-tree-reassoc-details" } */ + /* The transformation depends on BRANCH_COST being greater than 1 + (see the notes in the PR), so try to force that. */ Index: gcc/testsuite/gcc.dg/atomic-store-6.c =================================================================== --- a/src/gcc/testsuite/gcc.dg/atomic-store-6.c (.../tags/gcc_4_8_2_release) @@ -11584,7 +11589,18 @@ Index: gcc/testsuite/ChangeLog =================================================================== --- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_4_8_2_release) +++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,596 @@ +@@ -1,3 +1,607 @@ ++2014-01-10 Hans-Peter Nilsson <hp@axis.com> ++ ++ * gcc.dg/pr46309.c: Disable for cris*-*-*. ++ ++2014-01-10 Paolo Carlini <paolo.carlini@oracle.com> ++ ++ PR c++/56060 ++ PR c++/59730 ++ * g++.dg/cpp0x/variadic144.C: New. ++ * g++.dg/cpp0x/variadic145.C: Likewise. ++ +2014-01-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/59715 @@ -11615,7 +11631,7 @@ Index: gcc/testsuite/ChangeLog + * gcc.dg/strlenopt-4gf.c: Likewise. + + 2013-12-03 Jakub Jelinek <jakub@redhat.com> -+ ++ + PR tree-optimization/59362 + * gcc.c-torture/compile/pr59362.c: New test. + @@ -12181,7 +12197,7 @@ Index: gcc/testsuite/ChangeLog 2013-10-16 Release Manager * GCC 4.8.2 released. -@@ -39,9 +632,9 @@ +@@ -39,9 +643,9 @@ Backport from mainline 2013-06-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> @@ -12194,7 +12210,7 @@ Index: gcc/testsuite/ChangeLog 2013-10-04 Tobias Burnus <burnus@net-b.de> -@@ -307,8 +900,8 @@ +@@ -307,8 +911,8 @@ Backport from mainline 2013-08-12 Perez Read <netfirewall@gmail.com> @@ -12205,7 +12221,7 @@ Index: gcc/testsuite/ChangeLog 2013-08-11 Janus Weil <janus@gcc.gnu.org> -@@ -494,7 +1087,7 @@ +@@ -494,7 +1098,7 @@ 2013-06-19 Wei Mi <wmi@google.com> PR rtl-optimization/57518 @@ -12214,7 +12230,7 @@ Index: gcc/testsuite/ChangeLog 2013-06-11 Tobias Burnus <burnus@net-b.de> -@@ -623,8 +1216,8 @@ +@@ -623,8 +1227,8 @@ 2013-05-09 Martin Jambor <mjambor@suse.cz> @@ -12225,7 +12241,7 @@ Index: gcc/testsuite/ChangeLog 2013-05-08 Marc Glisse <marc.glisse@inria.fr> -@@ -701,7 +1294,7 @@ +@@ -701,7 +1305,7 @@ 2013-04-25 Marek Polacek <polacek@redhat.com> PR tree-optimization/57066 @@ -12234,7 +12250,7 @@ Index: gcc/testsuite/ChangeLog 2013-05-02 Jakub Jelinek <jakub@redhat.com> -@@ -727,32 +1320,32 @@ +@@ -727,32 +1331,32 @@ Backport from mainline 2013-04-24 Vladimir Makarov <vmakarov@redhat.com> @@ -12275,7 +12291,7 @@ Index: gcc/testsuite/ChangeLog 2013-05-02 Ian Bolton <ian.bolton@arm.com> -@@ -1102,7 +1695,7 @@ +@@ -1102,7 +1706,7 @@ 2013-03-29 Tobias Burnus <burnus@net-b.de> PR fortran/56737 @@ -12284,7 +12300,7 @@ Index: gcc/testsuite/ChangeLog 2013-04-02 Richard Biener <rguenther@suse.de> -@@ -1636,7 +2229,7 @@ +@@ -1636,7 +2240,7 @@ 2013-02-20 Jan Hubicka <jh@suse.cz> PR tree-optimization/56265 @@ -12293,7 +12309,7 @@ Index: gcc/testsuite/ChangeLog 2013-02-20 Richard Biener <rguenther@suse.de> -@@ -1823,11 +2416,9 @@ +@@ -1823,11 +2427,9 @@ Avoid instrumenting duplicated memory access in the same basic block * c-c++-common/asan/no-redundant-instrumentation-1.c: New test. @@ -12695,6 +12711,26 @@ Index: gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C +{ + int i = [] { return decltype(i)(); }(); +}; +Index: gcc/testsuite/g++.dg/cpp0x/variadic144.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic144.C (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic144.C (.../branches/gcc-4_8-branch) +@@ -0,0 +1,15 @@ ++// PR c++/56060 ++// { dg-do compile { target c++11 } } ++ ++template<typename T> struct baz { }; ++template<typename T> T bar(); ++ ++template<typename T, typename ... U> ++baz<decltype(bar<T>()(bar<U> ...))> // { dg-error "cannot be used" } ++foo(); ++ ++int main() ++{ ++ foo<int>(); // { dg-error "no matching" } ++ return 0; ++} Index: gcc/testsuite/g++.dg/cpp0x/enum18.C =================================================================== --- a/src/gcc/testsuite/g++.dg/cpp0x/enum18.C (.../tags/gcc_4_8_2_release) @@ -12793,6 +12829,24 @@ Index: gcc/testsuite/g++.dg/cpp0x/nsdmi9.C +}; + +B b; +Index: gcc/testsuite/g++.dg/cpp0x/variadic145.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic145.C (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic145.C (.../branches/gcc-4_8-branch) +@@ -0,0 +1,13 @@ ++// PR c++/59730 ++// { dg-do compile { target c++11 } } ++ ++template <typename> void declval(); ++template <typename> void forward(); ++template <typename> class D; ++template <typename _Functor, typename... _Bound_args> ++class D <_Functor(_Bound_args...)> { ++ template <typename... _Args, decltype(declval<_Functor>)> ++ void operator()(...) { ++ 0(forward<_Args>...); ++ } ++}; Index: gcc/testsuite/g++.dg/cpp0x/decltype57.C =================================================================== --- a/src/gcc/testsuite/g++.dg/cpp0x/decltype57.C (.../tags/gcc_4_8_2_release) @@ -13136,7 +13190,13 @@ Index: gcc/cp/ChangeLog =================================================================== --- a/src/gcc/cp/ChangeLog (.../tags/gcc_4_8_2_release) +++ b/src/gcc/cp/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,83 @@ +@@ -1,3 +1,89 @@ ++2014-01-10 Paolo Carlini <paolo.carlini@oracle.com> ++ ++ PR c++/56060 ++ PR c++/59730 ++ * pt.c (type_dependent_expression_p): Handle EXPR_PACK_EXPANSION. ++ +2013-12-12 Jason Merrill <jason@redhat.com> + + PR c++/58954 @@ -13394,6 +13454,17 @@ Index: gcc/cp/pt.c tmpl, tf_none, /*require_all_args=*/true, /*use_default_args=*/true); +@@ -19955,6 +19958,10 @@ + if (TREE_CODE (expression) == SCOPE_REF) + return false; + ++ /* Always dependent, on the number of arguments if nothing else. */ ++ if (TREE_CODE (expression) == EXPR_PACK_EXPANSION) ++ return true; ++ + if (BASELINK_P (expression)) + expression = BASELINK_FUNCTIONS (expression); + Index: gcc/cp/semantics.c =================================================================== --- a/src/gcc/cp/semantics.c (.../tags/gcc_4_8_2_release) @@ -14794,7 +14865,13 @@ Index: gcc/go/gofrontend/gogo-tree.cc - go_assert(FUNCTION_POINTER_TYPE_P(functype)); - functype = TREE_TYPE(functype); - } -- ++ Btype* functype = this->fntype_->get_backend_fntype(gogo); ++ this->fndecl_ = ++ gogo->backend()->function(functype, no->get_id(gogo), asm_name, ++ true, true, true, false, false, ++ this->location()); ++ } + - tree decl; - if (functype == error_mark_node) - decl = error_mark_node; @@ -14824,13 +14901,7 @@ Index: gcc/go/gofrontend/gogo-tree.cc - } - this->fndecl_ = decl; - go_preserve_from_gc(decl); -+ Btype* functype = this->fntype_->get_backend_fntype(gogo); -+ this->fndecl_ = -+ gogo->backend()->function(functype, no->get_id(gogo), asm_name, -+ true, true, true, false, false, -+ this->location()); - } -+ +- } return this->fndecl_; } @@ -16211,11 +16282,36 @@ Index: gcc/fortran/decl.c if (extended->attr.flavor != FL_DERIVED) { gfc_error ("'%s' in EXTENDS expression at %C is not a " +Index: gcc/fortran/dump-parse-tree.c +=================================================================== +--- a/src/gcc/fortran/dump-parse-tree.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/fortran/dump-parse-tree.c (.../branches/gcc-4_8-branch) +@@ -110,7 +110,8 @@ + break; + + case BT_CHARACTER: +- show_expr (ts->u.cl->length); ++ if (ts->u.cl) ++ show_expr (ts->u.cl->length); + fprintf(dumpfile, " %d", ts->kind); + break; + Index: gcc/fortran/ChangeLog =================================================================== --- a/src/gcc/fortran/ChangeLog (.../tags/gcc_4_8_2_release) +++ b/src/gcc/fortran/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,78 @@ +@@ -1,3 +1,89 @@ ++2014-01-11 Janus Weil <janus@gcc.gnu.org> ++ ++ Backport from mainline ++ 2013-12-29 Janus Weil <janus@gcc.gnu.org> ++ ++ PR fortran/59612 ++ PR fortran/57042 ++ * dump-parse-tree.c (show_typespec): Check for charlen. ++ * invoke.texi: Fix documentation of -fdump-fortran-optimized and ++ -fdump-parse-tree. ++ +2014-01-04 Janus Weil <janus@gcc.gnu.org> + + Backport from mainline @@ -16540,13 +16636,6 @@ Index: gcc/configure.ac plugin_rdynamic=yes pluginlibs="-rdynamic" else -Index: gcc/BASE-VER -=================================================================== ---- a/src/gcc/BASE-VER (.../tags/gcc_4_8_2_release) -+++ b/src/gcc/BASE-VER (.../branches/gcc-4_8-branch) -@@ -1 +1 @@ --4.8.2 -+4.8.3 Index: gcc/print-rtl.c =================================================================== --- a/src/gcc/print-rtl.c (.../tags/gcc_4_8_2_release) @@ -17027,8 +17116,7 @@ Index: gcc/tree-dfa.c exp = TREE_OPERAND (exp, 0); } -- done: - ++ + /* We need to deal with variable arrays ending structures. */ + if (seen_variable_array_ref + && maxsize != -1 @@ -17039,7 +17127,8 @@ Index: gcc/tree-dfa.c + TREE_INT_CST_LOW (TYPE_SIZE (TREE_TYPE (exp)))))) + maxsize = -1; + -+ done: + done: +- if (!bit_offset.fits_shwi ()) { *poffset = 0; @@ -17275,11 +17364,38 @@ Index: gcc/tree-predcom.c - bool ok; - - if (handled_component_p (ref)) -- { ++ tree off = DR_OFFSET (dr); ++ tree coff = DR_INIT (dr); ++ if (iter == 0) ++ ; ++ else if (TREE_CODE (DR_STEP (dr)) == INTEGER_CST) ++ coff = size_binop (PLUS_EXPR, coff, ++ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter))); ++ else ++ off = size_binop (PLUS_EXPR, off, ++ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter))); ++ tree addr = fold_build_pointer_plus (DR_BASE_ADDRESS (dr), off); ++ addr = force_gimple_operand_1 (addr, stmts, is_gimple_mem_ref_addr, ++ NULL_TREE); ++ tree alias_ptr = fold_convert (reference_alias_ptr_type (DR_REF (dr)), coff); ++ /* While data-ref analysis punts on bit offsets it still handles ++ bitfield accesses at byte boundaries. Cope with that. Note that ++ we cannot simply re-apply the outer COMPONENT_REF because the ++ byte-granular portion of it is already applied via DR_INIT and ++ DR_OFFSET, so simply build a BIT_FIELD_REF knowing that the bits ++ start at offset zero. */ ++ if (TREE_CODE (DR_REF (dr)) == COMPONENT_REF ++ && DECL_BIT_FIELD (TREE_OPERAND (DR_REF (dr), 1))) + { - op0 = ref_at_iteration (loop, TREE_OPERAND (ref, 0), iter); - if (!op0) - return NULL_TREE; -- } ++ tree field = TREE_OPERAND (DR_REF (dr), 1); ++ return build3 (BIT_FIELD_REF, TREE_TYPE (DR_REF (dr)), ++ build2 (MEM_REF, DECL_BIT_FIELD_TYPE (field), ++ addr, alias_ptr), ++ DECL_SIZE (field), bitsize_zero_node); + } - else if (!INDIRECT_REF_P (ref) - && TREE_CODE (ref) != MEM_REF) - return unshare_expr (ref); @@ -17317,13 +17433,6 @@ Index: gcc/tree-predcom.c - idx = TREE_OPERAND (ref, 1); - idx_p = &TREE_OPERAND (ret, 1); - } -+ tree off = DR_OFFSET (dr); -+ tree coff = DR_INIT (dr); -+ if (iter == 0) -+ ; -+ else if (TREE_CODE (DR_STEP (dr)) == INTEGER_CST) -+ coff = size_binop (PLUS_EXPR, coff, -+ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter))); else - return NULL_TREE; - @@ -17334,21 +17443,7 @@ Index: gcc/tree-predcom.c - if (integer_zerop (iv.step)) - *idx_p = unshare_expr (iv.base); - else -+ off = size_binop (PLUS_EXPR, off, -+ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter))); -+ tree addr = fold_build_pointer_plus (DR_BASE_ADDRESS (dr), off); -+ addr = force_gimple_operand_1 (addr, stmts, is_gimple_mem_ref_addr, -+ NULL_TREE); -+ tree alias_ptr = fold_convert (reference_alias_ptr_type (DR_REF (dr)), coff); -+ /* While data-ref analysis punts on bit offsets it still handles -+ bitfield accesses at byte boundaries. Cope with that. Note that -+ we cannot simply re-apply the outer COMPONENT_REF because the -+ byte-granular portion of it is already applied via DR_INIT and -+ DR_OFFSET, so simply build a BIT_FIELD_REF knowing that the bits -+ start at offset zero. */ -+ if (TREE_CODE (DR_REF (dr)) == COMPONENT_REF -+ && DECL_BIT_FIELD (TREE_OPERAND (DR_REF (dr), 1))) - { +- { - type = TREE_TYPE (iv.base); - if (POINTER_TYPE_P (type)) - { @@ -17363,15 +17458,9 @@ Index: gcc/tree-predcom.c - val = fold_build2 (PLUS_EXPR, type, iv.base, val); - } - *idx_p = unshare_expr (val); -+ tree field = TREE_OPERAND (DR_REF (dr), 1); -+ return build3 (BIT_FIELD_REF, TREE_TYPE (DR_REF (dr)), -+ build2 (MEM_REF, DECL_BIT_FIELD_TYPE (field), -+ addr, alias_ptr), -+ DECL_SIZE (field), bitsize_zero_node); - } +- } - - return ret; -+ else + return fold_build2 (MEM_REF, TREE_TYPE (DR_REF (dr)), addr, alias_ptr); } @@ -18708,15 +18797,21 @@ Index: gcc/config/s390/s390.c INSN_CODE (tbegin_insn) = -1; df_insn_rescan (tbegin_insn); -@@ -9573,6 +9775,7 @@ - const int CC3 = 1 << 0; - rtx abort_label = gen_label_rtx (); - rtx leave_label = gen_label_rtx (); +@@ -9568,61 +9770,47 @@ + void + s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) + { +- const int CC0 = 1 << 3; +- const int CC1 = 1 << 2; +- const int CC3 = 1 << 0; +- rtx abort_label = gen_label_rtx (); +- rtx leave_label = gen_label_rtx (); + rtx retry_plus_two = gen_reg_rtx (SImode); rtx retry_reg = gen_reg_rtx (SImode); rtx retry_label = NULL_RTX; - rtx jump; -@@ -9581,16 +9784,17 @@ +- rtx jump; +- rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1); + if (retry != NULL_RTX) { emit_move_insn (retry_reg, retry); @@ -18736,21 +18831,47 @@ Index: gcc/config/s390/s390.c + emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), + tdb)); - jump = s390_emit_jump (abort_label, - gen_rtx_NE (VOIDmode, -@@ -9611,6 +9815,10 @@ - /* Abort handler code. */ - - emit_label (abort_label); +- jump = s390_emit_jump (abort_label, +- gen_rtx_NE (VOIDmode, +- gen_rtx_REG (CCRAWmode, CC_REGNUM), +- gen_rtx_CONST_INT (VOIDmode, CC0))); +- +- JUMP_LABEL (jump) = abort_label; +- LABEL_NUSES (abort_label) = 1; +- add_reg_note (jump, REG_BR_PROB, very_unlikely); +- +- /* Initialize CC return value. */ +- emit_move_insn (dest, const0_rtx); +- +- s390_emit_jump (leave_label, NULL_RTX); +- LABEL_NUSES (leave_label) = 1; +- emit_barrier (); +- +- /* Abort handler code. */ +- +- emit_label (abort_label); + emit_move_insn (dest, gen_rtx_UNSPEC (SImode, + gen_rtvec (1, gen_rtx_REG (CCRAWmode, + CC_REGNUM)), + UNSPEC_CC_TO_INT)); if (retry != NULL_RTX) { ++ const int CC0 = 1 << 3; ++ const int CC1 = 1 << 2; ++ const int CC3 = 1 << 0; ++ rtx jump; rtx count = gen_reg_rtx (SImode); -@@ -9622,7 +9830,7 @@ - add_reg_note (jump, REG_BR_PROB, very_unlikely); ++ rtx leave_label = gen_label_rtx (); ++ ++ /* Exit for success and permanent failures. */ + jump = s390_emit_jump (leave_label, + gen_rtx_EQ (VOIDmode, + gen_rtx_REG (CCRAWmode, CC_REGNUM), +- gen_rtx_CONST_INT (VOIDmode, CC1 | CC3))); +- LABEL_NUSES (leave_label) = 2; +- add_reg_note (jump, REG_BR_PROB, very_unlikely); ++ gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3))); ++ LABEL_NUSES (leave_label) = 1; /* CC2 - transient failure. Perform retry with ppa. */ - emit_move_insn (count, retry); @@ -18758,18 +18879,22 @@ Index: gcc/config/s390/s390.c emit_insn (gen_subsi3 (count, count, retry_reg)); emit_insn (gen_tx_assist (count)); jump = emit_jump_insn (gen_doloop_si64 (retry_label, -@@ -9632,10 +9840,6 @@ +@@ -9630,13 +9818,8 @@ + retry_reg)); + JUMP_LABEL (jump) = retry_label; LABEL_NUSES (retry_label) = 1; ++ emit_label (leave_label); } - +- - emit_move_insn (dest, gen_rtx_UNSPEC (SImode, - gen_rtvec (1, gen_rtx_REG (CCRAWmode, - CC_REGNUM)), - UNSPEC_CC_TO_INT)); - emit_label (leave_label); +- emit_label (leave_label); } -@@ -9674,6 +9878,9 @@ + /* Builtins. */ +@@ -9674,6 +9857,9 @@ s390_init_builtins (void) { tree ftype, uint64_type; @@ -18779,7 +18904,7 @@ Index: gcc/config/s390/s390.c /* void foo (void) */ ftype = build_function_type_list (void_type_node, NULL_TREE); -@@ -9684,17 +9891,17 @@ +@@ -9684,17 +9870,17 @@ ftype = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); add_builtin_function ("__builtin_tabort", ftype, @@ -18800,7 +18925,7 @@ Index: gcc/config/s390/s390.c /* int foo (void *, int) */ ftype = build_function_type_list (integer_type_node, ptr_type_node, -@@ -9702,11 +9909,11 @@ +@@ -9702,11 +9888,11 @@ add_builtin_function ("__builtin_tbegin_retry", ftype, S390_BUILTIN_TBEGIN_RETRY, BUILT_IN_MD, @@ -18814,7 +18939,7 @@ Index: gcc/config/s390/s390.c /* int foo (void) */ ftype = build_function_type_list (integer_type_node, NULL_TREE); -@@ -11622,6 +11829,12 @@ +@@ -11622,6 +11808,12 @@ #undef TARGET_CANONICALIZE_COMPARISON #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison |