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-rw-r--r--debian/patches/svn-updates.diff90092
1 files changed, 1 insertions, 90091 deletions
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index c427f45..be9c8b4 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -8,90097 +8,7 @@ Fri May 16 11:28:00 UTC 2014 (revision 210514)
EOF
}
-LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_4_8_2_release svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch \
+LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_4_8_3_release svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch \
| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
| awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0'
-Index: libitm/configure
-===================================================================
---- a/src/libitm/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/configure (.../branches/gcc-4_8-branch)
-@@ -7270,7 +7270,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -7295,7 +7295,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -7314,7 +7317,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -11779,7 +11785,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11782 "configure"
-+#line 11788 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11885,7 +11891,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11888 "configure"
-+#line 11894 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -17362,6 +17368,43 @@
-
- fi
- ;;
-+esac
-+
-+case "${target_cpu}" in
-+powerpc*)
-+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the assembler supports HTM" >&5
-+$as_echo_n "checking if the assembler supports HTM... " >&6; }
-+if test "${libitm_cv_as_htm+set}" = set; then :
-+ $as_echo_n "(cached) " >&6
-+else
-+
-+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-+/* end confdefs.h. */
-+
-+int
-+main ()
-+{
-+asm("tbegin. 0; tend. 0");
-+ ;
-+ return 0;
-+}
-+_ACEOF
-+if ac_fn_c_try_compile "$LINENO"; then :
-+ libitm_cv_as_htm=yes
-+else
-+ libitm_cv_as_htm=no
-+fi
-+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
-+
-+fi
-+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libitm_cv_as_htm" >&5
-+$as_echo "$libitm_cv_as_htm" >&6; }
-+ if test x$libitm_cv_as_htm = xyes; then
-+
-+$as_echo "#define HAVE_AS_HTM 1" >>confdefs.h
-+
-+ fi
-+ ;;
- s390*)
- { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the assembler supports HTM" >&5
- $as_echo_n "checking if the assembler supports HTM... " >&6; }
-@@ -17399,7 +17442,6 @@
- fi
- ;;
- esac
--LIBITM_CHECK_AS_HTM
-
-
- { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether weak refs work like ELF" >&5
-Index: libitm/configure.tgt
-===================================================================
---- a/src/libitm/configure.tgt (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/configure.tgt (.../branches/gcc-4_8-branch)
-@@ -47,7 +47,10 @@
- # work out any special compilation flags as necessary.
- case "${target_cpu}" in
- alpha*) ARCH=alpha ;;
-- rs6000 | powerpc*) ARCH=powerpc ;;
-+ rs6000 | powerpc*)
-+ XCFLAGS="${XCFLAGS} -mhtm"
-+ ARCH=powerpc
-+ ;;
-
- arm*) ARCH=arm ;;
-
-Index: libitm/ChangeLog
-===================================================================
---- a/src/libitm/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,62 @@
-+2014-04-14 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ * acinclude.m4: Move s390* case from RTM to HTM check.
-+ * configure: Regenerate.
-+
-+2014-04-09 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
-+
-+ * config/generic/asmcfi.h: Also check for
-+ __GCC_HAVE_DWARF2_CFI_ASM.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r204808:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/powerpc/sjlj.S [__powerpc64__ && _CALL_ELF == 2]:
-+ (FUNC): Define ELFv2 variant.
-+ (END): Likewise.
-+ (HIDDEN): Likewise.
-+ (CALL): Likewise.
-+ (BASE): Likewise.
-+ (LR_SAVE): Likewise.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Power8 HTM Support
-+ Backport from mainline
-+ * acinclude.m4 (LIBITM_CHECK_AS_HTM): New.
-+ * configure: Rebuild.
-+ * configure.tgt (target_cpu): Add -mhtm to XCFLAGS.
-+ * config/powerpc/target.h: Include sys/auxv.h and htmintrin.h.
-+ (USE_HTM_FASTPATH): Define.
-+ (_TBEGIN_STARTED, _TBEGIN_INDETERMINATE, _TBEGIN_PERSISTENT)
-+ (_HTM_RETRIES) New macros.
-+ (htm_abort, htm_abort_should_retry, htm_available, htm_begin, htm_init)
-+ (htm_begin_success, htm_commit, htm_transaction_active): New functions.
-+
-+2014-03-26 Jakub Jelinek <jakub@redhat.com>
-+
-+ * config/linux/futex_bits.h: Include errno.h.
-+ (sys_futex0): If syscall returns -1, return -errno rather than
-+ -1.
-+
-+2014-03-03 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-06-20 Torvald Riegel <triegel@redhat.com>
-+
-+ * query.cc (_ITM_inTransaction): Abort when using the HTM fastpath.
-+ (_ITM_getTransactionId): Same.
-+ * config/x86/target.h (htm_transaction_active): New.
-+
-+ 2013-06-20 Torvald Riegel <triegel@redhat.com>
-+
-+ PR libitm/57643
-+ * beginend.cc (gtm_thread::begin_transaction): Handle reentrancy in
-+ the HTM fastpath.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-@@ -8,13 +67,12 @@
- 2013-08-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * configure.tgt: Add -msoft-float to XCFLAGS.
--
-
- 2013-08-14 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * config/s390/sjlj.S: Add file missing from last commit.
- * config/s390/target.h: Likewise.
--
-+
- 2013-08-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- Backports from mainline:
-Index: libitm/query.cc
-===================================================================
---- a/src/libitm/query.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/query.cc (.../branches/gcc-4_8-branch)
-@@ -43,6 +43,15 @@
- _ITM_howExecuting ITM_REGPARM
- _ITM_inTransaction (void)
- {
-+#if defined(USE_HTM_FASTPATH)
-+ // If we use the HTM fastpath, we cannot reliably detect whether we are
-+ // in a transaction because this function can be called outside of
-+ // a transaction and thus we can't deduce this by looking at just the serial
-+ // lock. This function isn't used in practice currently, so the easiest
-+ // way to handle it is to just abort.
-+ if (htm_fastpath && htm_transaction_active())
-+ htm_abort();
-+#endif
- struct gtm_thread *tx = gtm_thr();
- if (tx && (tx->nesting > 0))
- {
-@@ -58,6 +67,11 @@
- _ITM_transactionId_t ITM_REGPARM
- _ITM_getTransactionId (void)
- {
-+#if defined(USE_HTM_FASTPATH)
-+ // See ITM_inTransaction.
-+ if (htm_fastpath && htm_transaction_active())
-+ htm_abort();
-+#endif
- struct gtm_thread *tx = gtm_thr();
- return (tx && (tx->nesting > 0)) ? tx->id : _ITM_noTransactionId;
- }
-Index: libitm/beginend.cc
-===================================================================
---- a/src/libitm/beginend.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/beginend.cc (.../branches/gcc-4_8-branch)
-@@ -197,6 +197,8 @@
- // We are executing a transaction now.
- // Monitor the writer flag in the serial-mode lock, and abort
- // if there is an active or waiting serial-mode transaction.
-+ // Note that this can also happen due to an enclosing
-+ // serial-mode transaction; we handle this case below.
- if (unlikely(serial_lock.is_write_locked()))
- htm_abort();
- else
-@@ -219,6 +221,14 @@
- tx = new gtm_thread();
- set_gtm_thr(tx);
- }
-+ // Check whether there is an enclosing serial-mode transaction;
-+ // if so, we just continue as a nested transaction and don't
-+ // try to use the HTM fastpath. This case can happen when an
-+ // outermost relaxed transaction calls unsafe code that starts
-+ // a transaction.
-+ if (tx->nesting > 0)
-+ break;
-+ // Another thread is running a serial-mode transaction. Wait.
- serial_lock.read_lock(tx);
- serial_lock.read_unlock(tx);
- // TODO We should probably reset the retry count t here, unless
-Index: libitm/config/linux/futex_bits.h
-===================================================================
---- a/src/libitm/config/linux/futex_bits.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/config/linux/futex_bits.h (.../branches/gcc-4_8-branch)
-@@ -31,9 +31,13 @@
-
- #include <unistd.h>
- #include <sys/syscall.h>
-+#include <errno.h>
-
- static inline long
- sys_futex0 (std::atomic<int> *addr, long op, long val)
- {
-- return syscall (SYS_futex, (int*) addr, op, val, 0);
-+ long res = syscall (SYS_futex, (int*) addr, op, val, 0);
-+ if (__builtin_expect (res == -1, 0))
-+ return -errno;
-+ return res;
- }
-Index: libitm/config/powerpc/sjlj.S
-===================================================================
---- a/src/libitm/config/powerpc/sjlj.S (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/config/powerpc/sjlj.S (.../branches/gcc-4_8-branch)
-@@ -26,8 +26,27 @@
-
- #include "asmcfi.h"
-
--#if defined(__powerpc64__) && defined(__ELF__)
-+#if defined(__powerpc64__) && _CALL_ELF == 2
- .macro FUNC name
-+ .globl \name
-+ .type \name, @function
-+\name:
-+0: addis 2,12,(.TOC.-0b)@ha
-+ addi 2,2,(.TOC.-0b)@l
-+ .localentry \name, . - \name
-+.endm
-+.macro END name
-+ .size \name, . - \name
-+.endm
-+.macro HIDDEN name
-+ .hidden \name
-+.endm
-+.macro CALL name
-+ bl \name
-+ nop
-+.endm
-+#elif defined(__powerpc64__) && defined(__ELF__)
-+.macro FUNC name
- .globl \name, .\name
- .section ".opd","aw"
- .align 3
-@@ -117,6 +136,9 @@
- #if defined(_CALL_AIXDESC)
- # define BASE 6*WS
- # define LR_SAVE 2*WS
-+#elif _CALL_ELF == 2
-+# define BASE 6*WS
-+# define LR_SAVE 2*WS
- #elif defined(_CALL_SYSV)
- # define BASE 2*WS
- # define LR_SAVE 1*WS
-Index: libitm/config/powerpc/target.h
-===================================================================
---- a/src/libitm/config/powerpc/target.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/config/powerpc/target.h (.../branches/gcc-4_8-branch)
-@@ -22,6 +22,10 @@
- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
- <http://www.gnu.org/licenses/>. */
-
-+#ifdef HAVE_SYS_AUXV_H
-+#include <sys/auxv.h>
-+#endif
-+
- namespace GTM HIDDEN {
-
- typedef int v128 __attribute__((vector_size(16), may_alias, aligned(16)));
-@@ -55,4 +59,82 @@
- __asm volatile ("" : : : "memory");
- }
-
-+// Use HTM if it is supported by the system.
-+// See gtm_thread::begin_transaction for how these functions are used.
-+#if defined (__linux__) \
-+ && defined (HAVE_AS_HTM) \
-+ && defined (HAVE_GETAUXVAL) \
-+ && defined (AT_HWCAP2) \
-+ && defined (PPC_FEATURE2_HAS_HTM)
-+
-+#include <htmintrin.h>
-+
-+#define USE_HTM_FASTPATH
-+
-+#define _TBEGIN_STARTED 0
-+#define _TBEGIN_INDETERMINATE 1
-+#define _TBEGIN_PERSISTENT 2
-+
-+/* Number of retries for transient failures. */
-+#define _HTM_RETRIES 10
-+
-+static inline bool
-+htm_available (void)
-+{
-+ return (getauxval (AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) ? true : false;
-+}
-+
-+static inline uint32_t
-+htm_init (void)
-+{
-+ // Maximum number of times we try to execute a transaction
-+ // as a HW transaction.
-+ return htm_available () ? _HTM_RETRIES : 0;
-+}
-+
-+static inline uint32_t
-+htm_begin (void)
-+{
-+ if (__builtin_expect (__builtin_tbegin (0), 1))
-+ return _TBEGIN_STARTED;
-+
-+ if (_TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ()))
-+ return _TBEGIN_PERSISTENT;
-+
-+ return _TBEGIN_INDETERMINATE;
-+}
-+
-+static inline bool
-+htm_begin_success (uint32_t begin_ret)
-+{
-+ return begin_ret == _TBEGIN_STARTED;
-+}
-+
-+static inline void
-+htm_commit (void)
-+{
-+ __builtin_tend (0);
-+}
-+
-+static inline void
-+htm_abort (void)
-+{
-+ __builtin_tabort (0);
-+}
-+
-+static inline bool
-+htm_abort_should_retry (uint32_t begin_ret)
-+{
-+ return begin_ret != _TBEGIN_PERSISTENT;
-+}
-+
-+/* Returns true iff a hardware transaction is currently being executed. */
-+static inline bool
-+htm_transaction_active (void)
-+{
-+ return (_HTM_STATE (__builtin_ttest ()) == _HTM_TRANSACTIONAL);
-+}
-+
-+#endif
-+
- } // namespace GTM
-Index: libitm/config/x86/target.h
-===================================================================
---- a/src/libitm/config/x86/target.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/config/x86/target.h (.../branches/gcc-4_8-branch)
-@@ -125,6 +125,13 @@
- {
- return begin_ret & _XABORT_RETRY;
- }
-+
-+/* Returns true iff a hardware transaction is currently being executed. */
-+static inline bool
-+htm_transaction_active ()
-+{
-+ return _xtest() != 0;
-+}
- #endif
-
-
-Index: libitm/config/generic/asmcfi.h
-===================================================================
---- a/src/libitm/config/generic/asmcfi.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/config/generic/asmcfi.h (.../branches/gcc-4_8-branch)
-@@ -24,7 +24,7 @@
-
- #include "config.h"
-
--#ifdef HAVE_AS_CFI_PSEUDO_OP
-+#if defined(HAVE_AS_CFI_PSEUDO_OP) && defined(__GCC_HAVE_DWARF2_CFI_ASM)
-
- #define cfi_startproc .cfi_startproc
- #define cfi_endproc .cfi_endproc
-@@ -50,4 +50,4 @@
- #define cfi_restore(r)
- #define cfi_undefined(r)
-
--#endif /* HAVE_AS_CFI_PSEUDO_OP */
-+#endif /* HAVE_AS_CFI_PSEUDO_OP && __GCC_HAVE_DWARF2_CFI_ASM */
-Index: libitm/acinclude.m4
-===================================================================
---- a/src/libitm/acinclude.m4 (.../tags/gcc_4_8_2_release)
-+++ b/src/libitm/acinclude.m4 (.../branches/gcc-4_8-branch)
-@@ -121,12 +121,26 @@
- AC_DEFINE(HAVE_AS_RTM, 1, [Define to 1 if the assembler supports RTM.])
- fi
- ;;
-+esac])
-+
-+dnl Check if as supports HTM instructions.
-+AC_DEFUN([LIBITM_CHECK_AS_HTM], [
-+case "${target_cpu}" in
-+powerpc*)
-+ AC_CACHE_CHECK([if the assembler supports HTM], libitm_cv_as_htm, [
-+ AC_TRY_COMPILE([], [asm("tbegin. 0; tend. 0");],
-+ [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no])
-+ ])
-+ if test x$libitm_cv_as_htm = xyes; then
-+ AC_DEFINE(HAVE_AS_HTM, 1, [Define to 1 if the assembler supports HTM.])
-+ fi
-+ ;;
- s390*)
- AC_CACHE_CHECK([if the assembler supports HTM], libitm_cv_as_htm, [
- save_CFLAGS="$CFLAGS"
- CFLAGS="$CFLAGS -march=zEC12"
- AC_TRY_COMPILE([], [asm("tbegin 0,0; tend");],
-- [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no])
-+ [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no])
- CFLAGS="$save_CFLAGS"])
- if test x$libitm_cv_as_htm = xyes; then
- AC_DEFINE(HAVE_AS_HTM, 1, [Define to 1 if the assembler supports HTM.])
-Index: libtool.m4
-===================================================================
---- a/src/libtool.m4 (.../tags/gcc_4_8_2_release)
-+++ b/src/libtool.m4 (.../branches/gcc-4_8-branch)
-@@ -1220,7 +1220,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -1241,7 +1241,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -1260,7 +1263,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-Index: libgomp/configure
-===================================================================
---- a/src/libgomp/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libgomp/configure (.../branches/gcc-4_8-branch)
-@@ -6580,7 +6580,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6605,7 +6605,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6624,7 +6627,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -11088,7 +11094,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11091 "configure"
-+#line 11097 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11194,7 +11200,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11197 "configure"
-+#line 11203 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: libgomp/ChangeLog
-===================================================================
---- a/src/libgomp/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libgomp/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,21 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
-+2014-04-02 Richard Henderson <rth@redhat.com>
-+
-+ * config/linux/futex.h (futex_wait): Get error value from errno.
-+ (futex_wake): Likewise.
-+
-+2013-12-12 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR libgomp/59467
-+ * testsuite/libgomp.fortran/crayptr2.f90: Add private (d) clause to
-+ !$omp parallel.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libgomp/testsuite/libgomp.fortran/crayptr2.f90
-===================================================================
---- a/src/libgomp/testsuite/libgomp.fortran/crayptr2.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/libgomp/testsuite/libgomp.fortran/crayptr2.f90 (.../branches/gcc-4_8-branch)
-@@ -12,7 +12,7 @@
- b = 2
- c = 3
- l = .false.
--!$omp parallel num_threads (3) reduction (.or.:l)
-+!$omp parallel num_threads (3) reduction (.or.:l) private (d)
- if (omp_get_thread_num () .eq. 0) then
- ip = loc (a)
- elseif (omp_get_thread_num () .eq. 1) then
-Index: libgomp/config/linux/futex.h
-===================================================================
---- a/src/libgomp/config/linux/futex.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libgomp/config/linux/futex.h (.../branches/gcc-4_8-branch)
-@@ -41,8 +41,8 @@
- static inline void
- futex_wait (int *addr, int val)
- {
-- long err = syscall (SYS_futex, addr, gomp_futex_wait, val, NULL);
-- if (__builtin_expect (err == -ENOSYS, 0))
-+ int err = syscall (SYS_futex, addr, gomp_futex_wait, val, NULL);
-+ if (__builtin_expect (err < 0 && errno == ENOSYS, 0))
- {
- gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
- gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
-@@ -53,8 +53,8 @@
- static inline void
- futex_wake (int *addr, int count)
- {
-- long err = syscall (SYS_futex, addr, gomp_futex_wake, count);
-- if (__builtin_expect (err == -ENOSYS, 0))
-+ int err = syscall (SYS_futex, addr, gomp_futex_wake, count);
-+ if (__builtin_expect (err < 0 && errno == ENOSYS, 0))
- {
- gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
- gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
-Index: libquadmath/configure
-===================================================================
---- a/src/libquadmath/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libquadmath/configure (.../branches/gcc-4_8-branch)
-@@ -6248,7 +6248,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6273,7 +6273,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6292,7 +6295,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -10521,7 +10527,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10524 "configure"
-+#line 10530 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -10627,7 +10633,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10630 "configure"
-+#line 10636 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: libquadmath/ChangeLog
-===================================================================
---- a/src/libquadmath/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libquadmath/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,10 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libsanitizer/configure
-===================================================================
---- a/src/libsanitizer/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libsanitizer/configure (.../branches/gcc-4_8-branch)
-@@ -6604,7 +6604,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6629,7 +6629,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6648,7 +6651,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -11111,7 +11117,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11114 "configure"
-+#line 11120 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11217,7 +11223,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11220 "configure"
-+#line 11226 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: libsanitizer/ChangeLog
-===================================================================
---- a/src/libsanitizer/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libsanitizer/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,17 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r208290
-+ 2014-03-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * configure.tgt: Unsupported for little endian PowerPC for now.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libsanitizer/configure.tgt
-===================================================================
---- a/src/libsanitizer/configure.tgt (.../tags/gcc_4_8_2_release)
-+++ b/src/libsanitizer/configure.tgt (.../branches/gcc-4_8-branch)
-@@ -25,6 +25,9 @@
- TSAN_SUPPORTED=yes
- fi
- ;;
-+ powerpc*le-*-linux*)
-+ UNSUPPORTED=1
-+ ;;
- powerpc*-*-linux*)
- ;;
- sparc*-*-linux*)
-Index: zlib/configure
-===================================================================
---- a/src/zlib/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/zlib/configure (.../branches/gcc-4_8-branch)
-@@ -5853,7 +5853,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -5878,7 +5878,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -5897,7 +5900,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -10394,7 +10400,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10397 "configure"
-+#line 10403 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -10500,7 +10506,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10503 "configure"
-+#line 10509 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: zlib/ChangeLog
-===================================================================
---- a/src/zlib/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/zlib/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,10 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libstdc++-v3/configure
-===================================================================
---- a/src/libstdc++-v3/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/configure (.../branches/gcc-4_8-branch)
-@@ -7111,7 +7111,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -7136,7 +7136,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -7155,7 +7158,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -11513,7 +11519,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11516 "configure"
-+#line 11522 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11619,7 +11625,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11622 "configure"
-+#line 11628 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -15033,7 +15039,7 @@
- #
- # Fake what AC_TRY_COMPILE does. XXX Look at redoing this new-style.
- cat > conftest.$ac_ext << EOF
--#line 15036 "configure"
-+#line 15042 "configure"
- struct S { ~S(); };
- void bar();
- void foo()
-@@ -15383,7 +15389,7 @@
- # Fake what AC_TRY_COMPILE does.
-
- cat > conftest.$ac_ext << EOF
--#line 15386 "configure"
-+#line 15392 "configure"
- int main()
- {
- typedef bool atomic_type;
-@@ -15418,7 +15424,7 @@
- rm -f conftest*
-
- cat > conftest.$ac_ext << EOF
--#line 15421 "configure"
-+#line 15427 "configure"
- int main()
- {
- typedef short atomic_type;
-@@ -15453,7 +15459,7 @@
- rm -f conftest*
-
- cat > conftest.$ac_ext << EOF
--#line 15456 "configure"
-+#line 15462 "configure"
- int main()
- {
- // NB: _Atomic_word not necessarily int.
-@@ -15489,7 +15495,7 @@
- rm -f conftest*
-
- cat > conftest.$ac_ext << EOF
--#line 15492 "configure"
-+#line 15498 "configure"
- int main()
- {
- typedef long long atomic_type;
-@@ -15568,7 +15574,7 @@
- # unnecessary for this test.
-
- cat > conftest.$ac_ext << EOF
--#line 15571 "configure"
-+#line 15577 "configure"
- int main()
- {
- _Decimal32 d1;
-@@ -15610,7 +15616,7 @@
- # unnecessary for this test.
-
- cat > conftest.$ac_ext << EOF
--#line 15613 "configure"
-+#line 15619 "configure"
- template<typename T1, typename T2>
- struct same
- { typedef T2 type; };
-@@ -15644,7 +15650,7 @@
- rm -f conftest*
-
- cat > conftest.$ac_ext << EOF
--#line 15647 "configure"
-+#line 15653 "configure"
- template<typename T1, typename T2>
- struct same
- { typedef T2 type; };
-@@ -71573,7 +71579,7 @@
- fi
-
- # For libtool versioning info, format is CURRENT:REVISION:AGE
--libtool_VERSION=6:18:0
-+libtool_VERSION=6:19:0
-
- # Everything parsed; figure out what files and settings to use.
- case $enable_symvers in
-Index: libstdc++-v3/scripts/extract_symvers.in
-===================================================================
---- a/src/libstdc++-v3/scripts/extract_symvers.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/scripts/extract_symvers.in (.../branches/gcc-4_8-branch)
-@@ -53,6 +53,7 @@
- # present on Solaris.
- ${readelf} ${lib} |\
- sed -e 's/ \[<other>: [A-Fa-f0-9]*\] //' -e '/\.dynsym/,/^$/p;d' |\
-+ sed -e 's/ \[<localentry>: [0-9]*\] //' |\
- egrep -v ' (LOCAL|UND) ' |\
- egrep -v ' (_DYNAMIC|_GLOBAL_OFFSET_TABLE_|_PROCEDURE_LINKAGE_TABLE_|_edata|_end|_etext)$' |\
- sed -e 's/ <processor specific>: / <processor_specific>:_/g' |\
-Index: libstdc++-v3/src/c++98/ios_init.cc
-===================================================================
---- a/src/libstdc++-v3/src/c++98/ios_init.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/src/c++98/ios_init.cc (.../branches/gcc-4_8-branch)
-@@ -37,7 +37,7 @@
- {
- using namespace __gnu_cxx;
-
-- // Extern declarations for global objects in src/globals.cc.
-+ // Extern declarations for global objects in src/c++98/globals.cc.
- extern stdio_sync_filebuf<char> buf_cout_sync;
- extern stdio_sync_filebuf<char> buf_cin_sync;
- extern stdio_sync_filebuf<char> buf_cerr_sync;
-Index: libstdc++-v3/src/c++11/thread.cc
-===================================================================
---- a/src/libstdc++-v3/src/c++11/thread.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/src/c++11/thread.cc (.../branches/gcc-4_8-branch)
-@@ -183,7 +183,7 @@
- ::usleep(__us);
- }
- # else
-- ::sleep(__s.count() + (__ns >= 1000000));
-+ ::sleep(__s.count() + (__ns.count() >= 1000000));
- # endif
- #elif defined(_GLIBCXX_HAVE_WIN32_SLEEP)
- unsigned long ms = __ns.count() / 1000000;
-Index: libstdc++-v3/doc/xml/faq.xml
-===================================================================
---- a/src/libstdc++-v3/doc/xml/faq.xml (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/xml/faq.xml (.../branches/gcc-4_8-branch)
-@@ -241,7 +241,7 @@
- </question>
- <answer xml:id="a-license.what_restrictions">
- <para>
-- None. We encourage such programs to be released as open source,
-+ None. We encourage such programs to be released as free software,
- but we won't punish you or sue you if you choose otherwise.
- </para>
- </answer>
-Index: libstdc++-v3/doc/xml/manual/abi.xml
-===================================================================
---- a/src/libstdc++-v3/doc/xml/manual/abi.xml (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/xml/manual/abi.xml (.../branches/gcc-4_8-branch)
-@@ -203,6 +203,7 @@
- <listitem><para>GCC 4.5.0: GCC_4.5.0</para></listitem>
- <listitem><para>GCC 4.6.0: GCC_4.6.0</para></listitem>
- <listitem><para>GCC 4.7.0: GCC_4.7.0</para></listitem>
-+ <listitem><para>GCC 4.8.0: GCC_4.8.0</para></listitem>
- </itemizedlist>
- </listitem>
-
-@@ -261,6 +262,7 @@
- <listitem><para>GCC 4.6.1: libstdc++.so.6.0.16</para></listitem>
- <listitem><para>GCC 4.7.0: libstdc++.so.6.0.17</para></listitem>
- <listitem><para>GCC 4.8.0: libstdc++.so.6.0.18</para></listitem>
-+ <listitem><para>GCC 4.8.3: libstdc++.so.6.0.19</para></listitem>
- </itemizedlist>
- <para>
- Note 1: Error should be libstdc++.so.3.0.3.
-@@ -324,6 +326,7 @@
- <listitem><para>GCC 4.6.1: GLIBCXX_3.4.16, CXXABI_1.3.5</para></listitem>
- <listitem><para>GCC 4.7.0: GLIBCXX_3.4.17, CXXABI_1.3.6</para></listitem>
- <listitem><para>GCC 4.8.0: GLIBCXX_3.4.18, CXXABI_1.3.7</para></listitem>
-+ <listitem><para>GCC 4.8.3: GLIBCXX_3.4.19, CXXABI_1.3.7</para></listitem>
- </itemizedlist>
- </listitem>
-
-Index: libstdc++-v3/doc/xml/manual/status_cxx2011.xml
-===================================================================
---- a/src/libstdc++-v3/doc/xml/manual/status_cxx2011.xml (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/xml/manual/status_cxx2011.xml (.../branches/gcc-4_8-branch)
-@@ -877,10 +877,11 @@
- <entry/>
- </row>
- <row>
-+ <?dbhtml bgcolor="#B0B0B0" ?>
- <entry>20.9.7.6</entry>
- <entry>Other transformations</entry>
-- <entry>Y</entry>
-- <entry/>
-+ <entry>Partial</entry>
-+ <entry>Missing <code>aligned_union</code>.</entry>
- </row>
- <row>
- <entry>20.10</entry>
-Index: libstdc++-v3/doc/xml/manual/spine.xml
-===================================================================
---- a/src/libstdc++-v3/doc/xml/manual/spine.xml (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/xml/manual/spine.xml (.../branches/gcc-4_8-branch)
-@@ -20,6 +20,7 @@
- <year>2010</year>
- <year>2011</year>
- <year>2012</year>
-+ <year>2013</year>
- <holder>
- <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://www.fsf.org">FSF</link>
- </holder>
-Index: libstdc++-v3/doc/html/bk02.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/bk02.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/bk02.html (.../branches/gcc-4_8-branch)
-@@ -1,2 +1,2 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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-+++ b/src/libstdc++-v3/doc/html/bk03.html (.../branches/gcc-4_8-branch)
-@@ -1,2 +1,2 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="api.html" title="The GNU C++ Library API Reference" /><link rel="next" href="faq.html" title="Frequently Asked Questions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library API Reference </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Frequently Asked Questions</td></tr></table></div></body></html>
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="api.html" title="The GNU C++ Library API Reference" /><link rel="next" href="faq.html" title="Frequently Asked Questions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library API Reference </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Frequently Asked Questions</td></tr></table></div></body></html>
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-+++ b/src/libstdc++-v3/doc/html/faq.html (.../branches/gcc-4_8-branch)
-@@ -1,9 +1,9 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Frequently Asked Questions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk03.html" title="" /><link rel="prev" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Frequently Asked Questions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk03.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> </td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="faq"></a>Frequently Asked Questions</h1></div><div><p class="copyright">Copyright ©
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Frequently Asked Questions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk03.html" title="" /><link rel="prev" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Frequently Asked Questions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk03.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> </td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="faq"></a>Frequently Asked Questions</h1></div><div><p class="copyright">Copyright ©
- 2008, 2010
-
- <a class="link" href="http://www.fsf.org" target="_top">FSF</a>
-- </p></div></div><hr /></div><div class="qandaset"><a id="idp1581728"></a><dl><dt></dt><dd><dl><dt>1.1. <a href="faq.html#faq.what">
-+ </p></div></div><hr /></div><div class="qandaset"><a id="idm270011560848"></a><dl><dt></dt><dd><dl><dt>1.1. <a href="faq.html#faq.what">
- What is libstdc++?
- </a></dt><dt>1.2. <a href="faq.html#faq.why">
- Why should I use libstdc++?
-@@ -223,7 +223,7 @@
- </p></td></tr><tr class="question"><td align="left" valign="top"><a id="faq.license.what_restrictions"></a><a id="q-license.what_restrictions"></a><p><strong>2.4.</strong></p></td><td align="left" valign="top"><p>
- I see. So, what restrictions are there on programs that use the library?
- </p></td></tr><tr class="answer"><td align="left" valign="top"><a id="a-license.what_restrictions"></a></td><td align="left" valign="top"><p>
-- None. We encourage such programs to be released as open source,
-+ None. We encourage such programs to be released as free software,
- but we won't punish you or sue you if you choose otherwise.
- </p></td></tr><tr class="toc"><td align="left" valign="top" colspan="2"><dl><dt>3.1. <a href="faq.html#faq.how_to_install">How do I install libstdc++?
- </a></dt><dt>3.2. <a href="faq.html#faq.how_to_get_sources">How does one get current libstdc++ sources?
-Index: libstdc++-v3/doc/html/index.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/index.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/index.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="description" content="Short Contents Copyright (C) 2008-2013 FSF Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. This is the top level of the libstdc++ documentation set. The documentation is divided into the following three sections. Manual Frequently Asked Questions API and Source Documentation" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="next" href="manual/index.html" title="The GNU C++ Library Manual" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library</th></tr><tr><td width="20%" align="left"> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr></table><hr /></div><div class="set" lang="en" xml:lang="en"><div class="titlepage"><div><div><h1 class="title"><a id="set-index"></a>The GNU C++ Library</h1></div><div><div class="abstract"><a id="contents"></a><p class="title"><strong>Short Contents</strong></p><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="description" content="Short Contents Copyright (C) 2008-2013 FSF Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. This is the top level of the libstdc++ documentation set. The documentation is divided into the following three sections. Manual Frequently Asked Questions API and Source Documentation" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="next" href="manual/index.html" title="The GNU C++ Library Manual" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library</th></tr><tr><td width="20%" align="left"> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr></table><hr /></div><div class="set" lang="en" xml:lang="en"><div class="titlepage"><div><div><h1 class="title"><a id="set-index"></a>The GNU C++ Library</h1></div><div><div class="abstract"><a id="contents"></a><p class="title"><strong>Short Contents</strong></p><p>
- Copyright (C) 2008-2013
- <a class="link" href="http://www.fsf.org/" target="_top">FSF
- </a>
-@@ -20,7 +20,7 @@
- </p></li><li class="listitem"><p>
- <a class="link" href="api.html" title="The GNU C++ Library API Reference">API and Source Documentation</a>
- </p></li></ul></div><p>
-- </p></div></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="book"><a href="manual/index.html">The GNU C++ Library Manual</a></span></dt><dd><dl><dt><span class="part"><a href="manual/intro.html">I.
-+ </p></div></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="book"><a href="manual/index.html">The GNU C++ Library Manual</a></span></dt><dd><dl><dt><span class="part"><a href="manual/intro.html">I.
- Introduction
-
- </a></span></dt><dd><dl><dt><span class="chapter"><a href="manual/status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="manual/status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="manual/status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="manual/status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="manual/status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="manual/status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="manual/license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="manual/license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="manual/license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="manual/bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="manual/bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="manual/bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="manual/setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="manual/configure.html">Configure</a></span></dt><dt><span class="section"><a href="manual/make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="manual/using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="manual/using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="manual/using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="manual/using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="manual/using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="manual/using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="manual/using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="manual/using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="manual/using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="manual/using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="manual/using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="manual/debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="manual/debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="manual/debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="manual/debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="manual/debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="manual/debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="manual/debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="manual/debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="manual/debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="part"><a href="manual/std_contents.html">II.
-@@ -34,13 +34,13 @@
- </a></span></dt><dd><dl><dt><span class="section"><a href="manual/diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="manual/diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="manual/diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="manual/concept_checking.html">Concept Checking</a></span></dt></dl></dd><dt><span class="chapter"><a href="manual/utilities.html">6.
- Utilities
-
--</a></span></dt><dd><dl><dt><span class="section"><a href="manual/utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="manual/pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="manual/memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="manual/memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#idp13920976">Interface Design</a></span></dt><dt><span class="section"><a href="manual/memory.html#idp13924528">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="manual/memory.html#idp13937824">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="manual/memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="manual/memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="manual/memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="manual/memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#idp15512272">Class Hierarchy</a></span></dt><dt><span class="section"><a href="manual/memory.html#idp15534784">Thread Safety</a></span></dt><dt><span class="section"><a href="manual/memory.html#idp15542080">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="manual/memory.html#idp15556704">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#idp15573056">Examples</a></span></dt><dt><span class="section"><a href="manual/memory.html#idp15576640">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="manual/strings.html">7.
-+</a></span></dt><dd><dl><dt><span class="section"><a href="manual/utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="manual/pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="manual/memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="manual/memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="manual/memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="manual/memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="manual/memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="manual/memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="manual/memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="manual/memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="manual/memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="manual/memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="manual/memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="manual/memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="manual/memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="manual/memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="manual/strings.html">7.
- Strings
-
- </a></span></dt><dd><dl><dt><span class="section"><a href="manual/strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="manual/strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="manual/strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="manual/strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="manual/strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="manual/strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="manual/strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/localization.html">8.
- Localization
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--</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="manual/localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="manual/localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="manual/facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="manual/facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="manual/facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/containers.html">9.
-+</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="manual/localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="manual/localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="manual/facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="manual/facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="manual/facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/containers.html">9.
- Containers
-
- </a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="manual/containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="manual/associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="manual/associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/iterators.html">10.
-Index: libstdc++-v3/doc/html/api.html
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--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library API Reference</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk02.html" title="" /><link rel="prev" href="bk02.html" title="" /><link rel="next" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library API Reference</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk02.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> <a accesskey="n" href="bk03.html">Next</a></td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="api"></a>The GNU C++ Library API Reference</h1></div><div><p class="copyright">Copyright ©
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- 2008
- ,
- 2010
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-
- <a class="link" href="http://www.fsf.org/" target="_top">FSF
- </a>
-- </p></div><div><div class="legalnotice"><a id="idp3706336"></a><p>
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--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Dynamic Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4.  Support" /><link rel="prev" href="support.html" title="Chapter 4.  Support" /><link rel="next" href="termination.html" title="Termination" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Dynamic Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="support.html">Prev</a> </td><th width="60%" align="center">Chapter 4. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Dynamic Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4.  Support" /><link rel="prev" href="support.html" title="Chapter 4.  Support" /><link rel="next" href="termination.html" title="Termination" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Dynamic Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="support.html">Prev</a> </td><th width="60%" align="center">Chapter 4. 
- Support
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 10.  Iterators</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="containers_and_c.html" title="Interacting with C" /><link rel="next" href="algorithms.html" title="Chapter 11.  Algorithms" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 10. 
- Iterators
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- Iterators
-- <a id="idp16156992" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.iterators.predefined"></a>Predefined</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="iterators.predefined.vs_pointers"></a>Iterators vs. Pointers</h3></div></div></div><p>
-+ <a id="idm269999374096" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.iterators.predefined"></a>Predefined</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="iterators.predefined.vs_pointers"></a>Iterators vs. Pointers</h3></div></div></div><p>
- The following
- FAQ <a class="link" href="../faq.html#faq.iterator_as_pod" title="7.1.">entry</a> points out that
- iterators are not implemented as pointers. They are a generalization
-Index: libstdc++-v3/doc/html/manual/mt_allocator_ex_single.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/mt_allocator_ex_single.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/mt_allocator_ex_single.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Single Thread Example</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_impl.html" title="Implementation" /><link rel="next" href="mt_allocator_ex_multi.html" title="Multiple Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Single Thread Example</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_multi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.example_single"></a>Single Thread Example</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Single Thread Example</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_impl.html" title="Implementation" /><link rel="next" href="mt_allocator_ex_multi.html" title="Multiple Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Single Thread Example</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_multi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.example_single"></a>Single Thread Example</h2></div></div></div><p>
- Let's start by describing how the data on a freelist is laid out in memory.
- This is the first two blocks in freelist for thread id 3 in bin 3 (8 bytes):
- </p><pre class="programlisting">
-Index: libstdc++-v3/doc/html/manual/generalized_numeric_operations.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/generalized_numeric_operations.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/generalized_numeric_operations.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Generalized Operations</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="prev" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="next" href="numerics_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Generalized Operations</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="numerics.html">Prev</a> </td><th width="60%" align="center">Chapter 12. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Generalized Operations</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="prev" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="next" href="numerics_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Generalized Operations</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="numerics.html">Prev</a> </td><th width="60%" align="center">Chapter 12. 
- Numerics
-
- </th><td width="20%" align="right"> <a accesskey="n" href="numerics_and_c.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.generalized_ops"></a>Generalized Operations</h2></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/mt_allocator.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/mt_allocator.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/mt_allocator.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 20. The mt_allocator</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="profile_mode_diagnostics.html" title="Diagnostics" /><link rel="next" href="mt_allocator_design.html" title="Design Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 20. The mt_allocator</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_diagnostics.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 20. The mt_allocator</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="profile_mode_diagnostics.html" title="Diagnostics" /><link rel="next" href="mt_allocator_design.html" title="Design Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 20. The mt_allocator</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_diagnostics.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.allocator.mt"></a>Chapter 20. The mt_allocator</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="mt_allocator.html#allocator.mt.intro">Intro</a></span></dt><dt><span class="section"><a href="mt_allocator_design.html">Design Issues</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_design.html#allocator.mt.overview">Overview</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.tune">Tunable Parameters</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.init">Initialization</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.deallocation">Deallocation Notes</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_ex_single.html">Single Thread Example</a></span></dt><dt><span class="section"><a href="mt_allocator_ex_multi.html">Multiple Thread Example</a></span></dt></dl></div><p>
-+</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.allocator.mt"></a>Chapter 20. The mt_allocator</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="mt_allocator.html#allocator.mt.intro">Intro</a></span></dt><dt><span class="section"><a href="mt_allocator_design.html">Design Issues</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_design.html#allocator.mt.overview">Overview</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.tune">Tunable Parameters</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.init">Initialization</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.deallocation">Deallocation Notes</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_ex_single.html">Single Thread Example</a></span></dt><dt><span class="section"><a href="mt_allocator_ex_multi.html">Multiple Thread Example</a></span></dt></dl></div><p>
- </p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.intro"></a>Intro</h2></div></div></div><p>
- The mt allocator [hereinafter referred to simply as "the allocator"]
- is a fixed size (power of two) allocator that was initially
-Index: libstdc++-v3/doc/html/manual/unordered_associative.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/unordered_associative.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/unordered_associative.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Unordered Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="associative.html" title="Associative" /><link rel="next" href="containers_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Unordered Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Unordered Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="associative.html" title="Associative" /><link rel="next" href="containers_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Unordered Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
- Containers
-
- </th><td width="20%" align="right"> <a accesskey="n" href="containers_and_c.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.unordered"></a>Unordered Associative</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.unordered.hash"></a>Hash Code</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="containers.unordered.cache"></a>Hash Code Caching Policy</h4></div></div></div><p>
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Configure</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, configure, options" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="setup.html" title="Chapter 2. Setup" /><link rel="next" href="make.html" title="Make" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Configure</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="setup.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="make.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.configure"></a>Configure</h2></div></div></div><p>
- When configuring libstdc++, you'll have to configure the entire
- <span class="emphasis"><em>gccsrcdir</em></span> directory. Consider using the
- toplevel gcc configuration option
-Index: libstdc++-v3/doc/html/manual/status.html
-===================================================================
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- Introduction
-
--</th><td width="20%" align="right"> <a accesskey="n" href="license.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.status"></a>Chapter 1. Status</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.iso"></a>Implementation Status</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="status.iso.1998"></a>C++ 1998/2003</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="iso.1998.status"></a>Implementation Status</h4></div></div></div><p>
-+</th><td width="20%" align="right"> <a accesskey="n" href="license.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.status"></a>Chapter 1. Status</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.iso"></a>Implementation Status</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="status.iso.1998"></a>C++ 1998/2003</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="iso.1998.status"></a>Implementation Status</h4></div></div></div><p>
- This status table is based on the table of contents of ISO/IEC 14882:2003.
- </p><p>
- This page describes the C++ support in mainline GCC SVN, not in any
- particular release.
--</p><div class="table"><a id="idp452240"></a><p class="title"><strong>Table 1.1. C++ 1998/2003 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 1998/2003 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
-+</p><div class="table"><a id="idm270008034928"></a><p class="title"><strong>Table 1.1. C++ 1998/2003 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 1998/2003 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
- <span class="emphasis"><em>18</em></span>
- </td><td colspan="3" align="left">
- <span class="emphasis"><em>Language support</em></span>
-@@ -157,7 +157,7 @@
- </p><p>
- This page describes the C++11 support in mainline GCC SVN, not in any
- particular release.
--</p><div class="table"><a id="idp8670848"></a><p class="title"><strong>Table 1.2. C++ 2011 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 2011 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
-+</p><div class="table"><a id="idm270007982624"></a><p class="title"><strong>Table 1.2. C++ 2011 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 2011 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
- <span class="emphasis"><em>18</em></span>
- </td><td colspan="3" align="left">
- <span class="emphasis"><em>Language support</em></span>
-@@ -183,7 +183,7 @@
- is_trivially_copy_constructible, is_trivially_move_constructible,
- is_trivially_assignable, is_trivially_default_assignable,
- is_trivially_copy_assignable, is_trivially_move_assignable
-- </td></tr><tr><td align="left">20.9.5</td><td align="left">Type property queries</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.6</td><td align="left">Relationships between types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7</td><td align="left">Transformations between types</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.9.7.1</td><td align="left">Const-volatile modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.2</td><td align="left">Reference modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.3</td><td align="left">Sign modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.4</td><td align="left">Array modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.5</td><td align="left">Pointer modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.6</td><td align="left">Other transformations</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10</td><td align="left">Compile-time rational arithmetic</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.2</td><td align="left">Header <code class="code">&lt;ratio&gt;</code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.3</td><td align="left">Class template <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.4</td><td align="left">Arithmetic on <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.5</td><td align="left">Comparison of <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.6</td><td align="left">SI types for <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11</td><td align="left">Time utilities</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.3</td><td align="left">Clock requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4</td><td align="left">Time-related traits</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.4.1</td><td align="left"><code class="code">treat_as_floating_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.2</td><td align="left"><code class="code">duration_values</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.3</td><td align="left">Specializations of <code class="code">common_type</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.11.5</td><td align="left">Class template <code class="code">duration</code></td><td align="left">Partial</td><td align="left">Missing constexpr for non-member arithmetic operations</td></tr><tr><td align="left">20.11.6</td><td align="left">Class template <code class="code">time_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7</td><td align="left">Clocks</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.7.1</td><td align="left">Class <code class="code">system_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.2</td><td align="left">Class <code class="code">steady_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.3</td><td align="left">Class <code class="code">high_resolution_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.8</td><td align="left">Date and time functions</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12</td><td align="left">Scoped allocator adaptor</td><td align="left">Partial</td><td align="left"> </td></tr><tr><td align="left">20.12.1</td><td align="left">Header <code class="code">&lt;scoped_allocator&gt;</code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.12.2</td><td align="left">Scoped allocator adaptor member types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.12.3</td><td align="left">Scoped allocator adaptor constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12.4</td><td align="left">Scoped allocator adaptor members</td><td align="left">Partial</td><td align="left">OUTERMOST is not recursive.</td></tr><tr><td align="left">20.12.5</td><td align="left">Scoped allocator operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.13</td><td align="left">Class <code class="code">type_index</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">
-+ </td></tr><tr><td align="left">20.9.5</td><td align="left">Type property queries</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.6</td><td align="left">Relationships between types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7</td><td align="left">Transformations between types</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.9.7.1</td><td align="left">Const-volatile modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.2</td><td align="left">Reference modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.3</td><td align="left">Sign modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.4</td><td align="left">Array modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.9.7.5</td><td align="left">Pointer modifications</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.9.7.6</td><td align="left">Other transformations</td><td align="left">Partial</td><td align="left">Missing <code class="code">aligned_union</code>.</td></tr><tr><td align="left">20.10</td><td align="left">Compile-time rational arithmetic</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.2</td><td align="left">Header <code class="code">&lt;ratio&gt;</code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.10.3</td><td align="left">Class template <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.4</td><td align="left">Arithmetic on <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.5</td><td align="left">Comparison of <code class="code">ratio</code>s</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.10.6</td><td align="left">SI types for <code class="code">ratio</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11</td><td align="left">Time utilities</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.3</td><td align="left">Clock requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4</td><td align="left">Time-related traits</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.4.1</td><td align="left"><code class="code">treat_as_floating_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.2</td><td align="left"><code class="code">duration_values</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.4.3</td><td align="left">Specializations of <code class="code">common_type</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.11.5</td><td align="left">Class template <code class="code">duration</code></td><td align="left">Partial</td><td align="left">Missing constexpr for non-member arithmetic operations</td></tr><tr><td align="left">20.11.6</td><td align="left">Class template <code class="code">time_point</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7</td><td align="left">Clocks</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.11.7.1</td><td align="left">Class <code class="code">system_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.2</td><td align="left">Class <code class="code">steady_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.7.3</td><td align="left">Class <code class="code">high_resolution_clock</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.11.8</td><td align="left">Date and time functions</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12</td><td align="left">Scoped allocator adaptor</td><td align="left">Partial</td><td align="left"> </td></tr><tr><td align="left">20.12.1</td><td align="left">Header <code class="code">&lt;scoped_allocator&gt;</code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.12.2</td><td align="left">Scoped allocator adaptor member types</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.12.3</td><td align="left">Scoped allocator adaptor constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.12.4</td><td align="left">Scoped allocator adaptor members</td><td align="left">Partial</td><td align="left">OUTERMOST is not recursive.</td></tr><tr><td align="left">20.12.5</td><td align="left">Scoped allocator operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.13</td><td align="left">Class <code class="code">type_index</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">
- <span class="emphasis"><em>21</em></span>
- </td><td colspan="3" align="left">
- <span class="emphasis"><em>Strings</em></span>
-@@ -302,7 +302,7 @@
- </p><p>
- This page describes the TR1 support in mainline GCC SVN, not in any particular
- release.
--</p><div class="table"><a id="idp7483200"></a><p class="title"><strong>Table 1.3. C++ TR1 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR1 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left"><span class="emphasis"><em>2</em></span></td><td colspan="3" align="left"><span class="emphasis"><em>General Utilities</em></span></td></tr><tr><td align="left">2.1</td><td align="left">Reference wrappers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.1</td><td align="left">Additions to header <code class="code">&lt;functional&gt;</code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2</td><td align="left">Class template <code class="code">reference_wrapper</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.2.1</td><td align="left"><code class="code">reference_wrapper</code> construct/copy/destroy</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.2</td><td align="left"><code class="code">reference_wrapper</code> assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.3</td><td align="left"><code class="code">reference_wrapper</code> access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.4</td><td align="left"><code class="code">reference_wrapper</code> invocation</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.5</td><td align="left"><code class="code">reference_wrapper</code> helper functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.2.1</td><td align="left">Additions to header <code class="code">&lt;memory&gt;</code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.2</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.3</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left"> </td><td align="left">
-+</p><div class="table"><a id="idm270006687472"></a><p class="title"><strong>Table 1.3. C++ TR1 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR1 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left"><span class="emphasis"><em>2</em></span></td><td colspan="3" align="left"><span class="emphasis"><em>General Utilities</em></span></td></tr><tr><td align="left">2.1</td><td align="left">Reference wrappers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.1</td><td align="left">Additions to header <code class="code">&lt;functional&gt;</code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2</td><td align="left">Class template <code class="code">reference_wrapper</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.2.1</td><td align="left"><code class="code">reference_wrapper</code> construct/copy/destroy</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.2</td><td align="left"><code class="code">reference_wrapper</code> assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.3</td><td align="left"><code class="code">reference_wrapper</code> access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.4</td><td align="left"><code class="code">reference_wrapper</code> invocation</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.5</td><td align="left"><code class="code">reference_wrapper</code> helper functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.2.1</td><td align="left">Additions to header <code class="code">&lt;memory&gt;</code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.2</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.3</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left"> </td><td align="left">
- <p>
- Uses code from
- <a class="link" href="http://www.boost.org/libs/smart_ptr/shared_ptr.htm" target="_top">boost::shared_ptr</a>.
-@@ -323,7 +323,7 @@
- </p><p>
- This page describes the TR 24733 support in mainline GCC SVN, not in any
- particular release.
--</p><div class="table"><a id="idp12559072"></a><p class="title"><strong>Table 1.4. C++ TR 24733 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR 24733 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
-+</p><div class="table"><a id="idm270002960368"></a><p class="title"><strong>Table 1.4. C++ TR 24733 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR 24733 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
- <span class="emphasis"><em>0</em></span>
- </td><td colspan="3" align="left">
- <span class="emphasis"><em>Introduction</em></span>
-Index: libstdc++-v3/doc/html/manual/profile_mode_devel.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/profile_mode_devel.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/profile_mode_devel.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Developer Information</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_impl.html" title="Implementation Issues" /><link rel="next" href="profile_mode_diagnostics.html" title="Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Developer Information</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.developer"></a>Developer Information</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.developer.bigpic"></a>Big Picture</h3></div></div></div><p>The profile mode headers are included with
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Developer Information</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_impl.html" title="Implementation Issues" /><link rel="next" href="profile_mode_diagnostics.html" title="Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Developer Information</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.developer"></a>Developer Information</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.developer.bigpic"></a>Big Picture</h3></div></div></div><p>The profile mode headers are included with
- <code class="code">-D_GLIBCXX_PROFILE</code> through preprocessor directives in
- <code class="code">include/std/*</code>.
- </p><p>Instrumented implementations are provided in
-Index: libstdc++-v3/doc/html/manual/debug_mode_design.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/debug_mode_design.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/debug_mode_design.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_using.html" title="Using" /><link rel="next" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.design"></a>Design</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_using.html" title="Using" /><link rel="next" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.design"></a>Design</h2></div></div></div><p>
- </p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="debug_mode.design.goals"></a>Goals</h3></div></div></div><p>
- </p><p> The libstdc++ debug mode replaces unsafe (but efficient) standard
- containers and iterators with semantically equivalent safe standard
-@@ -391,7 +391,7 @@
- </p><p> There are several existing implementations of debug modes for C++
- standard library implementations, although none of them directly
- supports debugging for programs using libstdc++. The existing
-- implementations include:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><a class="link" href="http://www.mathcs.sjsu.edu/faculty/horstman/safestl.html" target="_top">SafeSTL</a>:
-+ implementations include:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><a class="link" href="http://www.cs.sjsu.edu/faculty/horstman/safestl.html" target="_top">SafeSTL</a>:
- SafeSTL was the original debugging version of the Standard Template
- Library (STL), implemented by Cay S. Horstmann on top of the
- Hewlett-Packard STL. Though it inspired much work in this area, it
-Index: libstdc++-v3/doc/html/manual/policy_data_structures_design.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/policy_data_structures_design.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures_design.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_using.html" title="Using" /><link rel="next" href="policy_based_data_structures_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_using.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_based_data_structures_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.design"></a>Design</h2></div></div></div><p></p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.design.concepts"></a>Concepts</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.design.concepts.null_type"></a>Null Policy Classes</h4></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_using.html" title="Using" /><link rel="next" href="policy_based_data_structures_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_using.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_based_data_structures_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.design"></a>Design</h2></div></div></div><p></p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.design.concepts"></a>Concepts</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.design.concepts.null_type"></a>Null Policy Classes</h4></div></div></div><p>
- Associative containers are typically parametrized by various
- policies. For example, a hash-based associative container is
- parametrized by a hash-functor, transforming each key into an
-@@ -170,7 +170,7 @@
- naturally; collision-chaining hash tables (label B) store
- equivalent-key values in the same bucket, the bucket can be
- arranged so that equivalent-key values are consecutive.
-- </p><div class="figure"><a id="idp18000448"></a><p class="title"><strong>Figure 22.8. Non-unique Mapping Standard Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_1.png" align="middle" alt="Non-unique Mapping Standard Containers" /></div></div></div><br class="figure-break" /><p>
-+ </p><div class="figure"><a id="idm269997530416"></a><p class="title"><strong>Figure 22.8. Non-unique Mapping Standard Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_1.png" align="middle" alt="Non-unique Mapping Standard Containers" /></div></div></div><br class="figure-break" /><p>
- Put differently, the standards' non-unique mapping
- associative-containers are associative containers that map
- primary keys to linked lists that are embedded into the
-@@ -252,7 +252,7 @@
- first graphic above. Labels A and B, respectively. Each shaded
- box represents some size-type or secondary
- associative-container.
-- </p><div class="figure"><a id="idp18023952"></a><p class="title"><strong>Figure 22.10. Non-unique Mapping Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_3.png" align="middle" alt="Non-unique Mapping Containers" /></div></div></div><br class="figure-break" /><p>
-+ </p><div class="figure"><a id="idm269997506912"></a><p class="title"><strong>Figure 22.10. Non-unique Mapping Containers</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_embedded_lists_3.png" align="middle" alt="Non-unique Mapping Containers" /></div></div></div><br class="figure-break" /><p>
- In the first example above, then, one would use an associative
- container mapping each user to an associative container which
- maps each application id to a start time (see
-@@ -305,7 +305,7 @@
- shows invariants for order-preserving containers: point-type
- iterators are synonymous with range-type iterators.
- Orthogonally, <span class="emphasis"><em>C</em></span>shows invariants for "set"
-- containers: iterators are synonymous with const iterators.</p><div class="figure"><a id="idp18043824"></a><p class="title"><strong>Figure 22.11. Point Iterator Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterator_hierarchy.png" align="middle" alt="Point Iterator Hierarchy" /></div></div></div><br class="figure-break" /><p>Note that point-type iterators in self-organizing containers
-+ containers: iterators are synonymous with const iterators.</p><div class="figure"><a id="idm269997487104"></a><p class="title"><strong>Figure 22.11. Point Iterator Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterator_hierarchy.png" align="middle" alt="Point Iterator Hierarchy" /></div></div></div><br class="figure-break" /><p>Note that point-type iterators in self-organizing containers
- (hash-based associative containers) lack movement
- operators, such as <code class="literal">operator++</code> - in fact, this
- is the reason why this library differentiates from the standard C++ librarys
-@@ -344,7 +344,7 @@
- to the question of whether point-type iterators and range-type
- iterators are valid. The graphic below shows tags corresponding to
- different types of invalidation guarantees.
-- </p><div class="figure"><a id="idp18057168"></a><p class="title"><strong>Figure 22.12. Invalidation Guarantee Tags Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_tag_hierarchy.png" align="middle" alt="Invalidation Guarantee Tags Hierarchy" /></div></div></div><br class="figure-break" /><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>
-+ </p><div class="figure"><a id="idm269997473760"></a><p class="title"><strong>Figure 22.12. Invalidation Guarantee Tags Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_tag_hierarchy.png" align="middle" alt="Invalidation Guarantee Tags Hierarchy" /></div></div></div><br class="figure-break" /><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>
- <code class="classname">basic_invalidation_guarantee</code>
- corresponds to a basic guarantee that a point-type iterator,
- a found pointer, or a found reference, remains valid as long
-@@ -428,7 +428,7 @@
- </p><p>
- This library contains a container tag hierarchy corresponding to the
- diagram below.
-- </p><div class="figure"><a id="idp18087392"></a><p class="title"><strong>Figure 22.13. Container Tag Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_container_tag_hierarchy.png" align="middle" alt="Container Tag Hierarchy" /></div></div></div><br class="figure-break" /><p>
-+ </p><div class="figure"><a id="idm269997443664"></a><p class="title"><strong>Figure 22.13. Container Tag Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_container_tag_hierarchy.png" align="middle" alt="Container Tag Hierarchy" /></div></div></div><br class="figure-break" /><p>
- Given any container <span class="type">Cntnr</span>, the tag of
- the underlying data structure can be found via <code class="literal">typename
- Cntnr::container_category</code>.
-@@ -487,7 +487,7 @@
- collision-chaining container, except for the following.</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p><code class="classname">Comb_Probe_Fn</code> describes how to transform a probe
- sequence into a sequence of positions within the table.</p></li><li class="listitem"><p><code class="classname">Probe_Fn</code> describes a probe sequence policy.</p></li></ol></div><p>Some of the default template values depend on the values of
- other parameters, and are explained below.</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="container.hash.details"></a>Details</h5></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.hash.details.hash_policies"></a>Hash Policies</h6></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="details.hash_policies.general"></a>General</h6></div></div></div><p>Following is an explanation of some functions which hashing
-- involves. The graphic below illustrates the discussion.</p><div class="figure"><a id="idp18127536"></a><p class="title"><strong>Figure 22.14. Hash functions, ranged-hash functions, and
-+ involves. The graphic below illustrates the discussion.</p><div class="figure"><a id="idm269997403584"></a><p class="title"><strong>Figure 22.14. Hash functions, ranged-hash functions, and
- range-hashing functions</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_ranged_hash_range_hashing_fns.png" align="middle" alt="Hash functions, ranged-hash functions, and range-hashing functions" /></div></div></div><br class="figure-break" /><p>Let U be a domain (e.g., the integers, or the
- strings of 3 characters). A hash-table algorithm needs to map
- elements of U "uniformly" into the range [0,..., m -
-@@ -504,7 +504,7 @@
- Z<sub>+</sub>,</p><p>which maps a non-negative hash value, and a non-negative
- range upper-bound into a non-negative integral in the range
- between 0 (inclusive) and the range upper bound (exclusive),
-- i.e., for any r in Z<sub>+</sub>,</p><p>0 ≤ g(r, m) ≤ m - 1</p><p>The resulting ranged-hash function, is</p><div class="equation"><a id="idp18141344"></a><p class="title"><strong>Equation 22.1. Ranged Hash Function</strong></p><div class="equation-contents"><span class="mathphrase">
-+ i.e., for any r in Z<sub>+</sub>,</p><p>0 ≤ g(r, m) ≤ m - 1</p><p>The resulting ranged-hash function, is</p><div class="equation"><a id="idm269997389776"></a><p class="title"><strong>Equation 22.1. Ranged Hash Function</strong></p><div class="equation-contents"><span class="mathphrase">
- f(u , m) = g(h(u), m)
- </span></div></div><br class="equation-break" /><p>From the above, it is obvious that given g and
- h, f can always be composed (however the converse
-@@ -524,7 +524,7 @@
- transforming the sequence of hash values into a sequence of
- positions.</p></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="details.hash_policies.range"></a>Range Hashing</h6></div></div></div><p>Some common choices for range-hashing functions are the
- division, multiplication, and middle-square methods (<a class="xref" href="policy_data_structures.html#biblio.knuth98sorting" title="The Art of Computer Programming - Sorting and Searching">[biblio.knuth98sorting]</a>), defined
-- as</p><div class="equation"><a id="idp18147232"></a><p class="title"><strong>Equation 22.2. Range-Hashing, Division Method</strong></p><div class="equation-contents"><span class="mathphrase">
-+ as</p><div class="equation"><a id="idm269997383888"></a><p class="title"><strong>Equation 22.2. Range-Hashing, Division Method</strong></p><div class="equation-contents"><span class="mathphrase">
- g(r, m) = r mod m
- </span></div></div><br class="equation-break" /><p>g(r, m) = ⌈ u/v ( a r mod v ) ⌉</p><p>and</p><p>g(r, m) = ⌈ u/v ( r<sup>2</sup> mod v ) ⌉</p><p>respectively, for some positive integrals u and
- v (typically powers of 2), and some a. Each of
-@@ -535,9 +535,9 @@
- implement using the low
- level % (modulo) operation (for any m), or the
- low level &amp; (bit-mask) operation (for the case where
-- m is a power of 2), i.e.,</p><div class="equation"><a id="idp18151744"></a><p class="title"><strong>Equation 22.3. Division via Prime Modulo</strong></p><div class="equation-contents"><span class="mathphrase">
-+ m is a power of 2), i.e.,</p><div class="equation"><a id="idm269997379376"></a><p class="title"><strong>Equation 22.3. Division via Prime Modulo</strong></p><div class="equation-contents"><span class="mathphrase">
- g(r, m) = r % m
-- </span></div></div><br class="equation-break" /><p>and</p><div class="equation"><a id="idp18153568"></a><p class="title"><strong>Equation 22.4. Division via Bit Mask</strong></p><div class="equation-contents"><span class="mathphrase">
-+ </span></div></div><br class="equation-break" /><p>and</p><div class="equation"><a id="idm269997377552"></a><p class="title"><strong>Equation 22.4. Division via Bit Mask</strong></p><div class="equation-contents"><span class="mathphrase">
- g(r, m) = r &amp; m - 1, (with m =
- 2<sup>k</sup> for some k)
- </span></div></div><br class="equation-break" /><p>respectively.</p><p>The % (modulo) implementation has the advantage that for
-@@ -563,7 +563,7 @@
- s = [ s<sub>0</sub>,..., s<sub>t - 1</sub>]
- </p><p>be a string of t characters, each of which is from
- domain S. Consider the following ranged-hash
-- function:</p><div class="equation"><a id="idp18163200"></a><p class="title"><strong>Equation 22.5. 
-+ function:</p><div class="equation"><a id="idm269997367984"></a><p class="title"><strong>Equation 22.5. 
- A Standard String Hash Function
- </strong></p><div class="equation-contents"><span class="mathphrase">
- f<sub>1</sub>(s, m) = ∑ <sub>i =
-@@ -575,7 +575,7 @@
- of a long DNA sequence (and so S = {'A', 'C', 'G',
- 'T'}). In this case, scanning the entire string might be
- prohibitively expensive. A possible alternative might be to use
-- only the first k characters of the string, where</p><p>|S|<sup>k</sup> ≥ m ,</p><p>i.e., using the hash function</p><div class="equation"><a id="idp18169344"></a><p class="title"><strong>Equation 22.6. 
-+ only the first k characters of the string, where</p><p>|S|<sup>k</sup> ≥ m ,</p><p>i.e., using the hash function</p><div class="equation"><a id="idm269997361840"></a><p class="title"><strong>Equation 22.6. 
- Only k String DNA Hash
- </strong></p><div class="equation-contents"><span class="mathphrase">
- f<sub>2</sub>(s, m) = ∑ <sub>i
-@@ -606,12 +606,12 @@
- the container transforms the key into a non-negative integral
- using the hash functor (points B and C), and transforms the
- result into a position using the combining functor (points D
-- and E).</p><div class="figure"><a id="idp18191968"></a><p class="title"><strong>Figure 22.15. Insert hash sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram.png" align="middle" alt="Insert hash sequence diagram" /></div></div></div><br class="figure-break" /><p>If <code class="classname">cc_hash_table</code>'s
-+ and E).</p><div class="figure"><a id="idm269997339216"></a><p class="title"><strong>Figure 22.15. Insert hash sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram.png" align="middle" alt="Insert hash sequence diagram" /></div></div></div><br class="figure-break" /><p>If <code class="classname">cc_hash_table</code>'s
- hash-functor, <code class="classname">Hash_Fn</code> is instantiated by <code class="classname">null_type</code> , then <code class="classname">Comb_Hash_Fn</code> is taken to be
- a ranged-hash function. The graphic below shows an <code class="function">insert</code> sequence
- diagram. The user inserts an element (point A), the container
- transforms the key into a position using the combining functor
-- (points B and C).</p><div class="figure"><a id="idp18199024"></a><p class="title"><strong>Figure 22.16. Insert hash sequence diagram with a null policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram2.png" align="middle" alt="Insert hash sequence diagram with a null policy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="hash_policies.implementation.probe"></a>
-+ (points B and C).</p><div class="figure"><a id="idm269997332160"></a><p class="title"><strong>Figure 22.16. Insert hash sequence diagram with a null policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_range_hashing_seq_diagram2.png" align="middle" alt="Insert hash sequence diagram with a null policy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="hash_policies.implementation.probe"></a>
- Probing tables
- </h6></div></div></div><p><code class="classname">gp_hash_table</code> is parametrized by
- <code class="classname">Hash_Fn</code>, <code class="classname">Probe_Fn</code>,
-@@ -634,7 +634,7 @@
- a linear probe and a quadratic probe function,
- respectively.</p></li></ol></div><p>
- The graphic below shows the relationships.
-- </p><div class="figure"><a id="idp18215840"></a><p class="title"><strong>Figure 22.17. Hash policy class diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_policy_cd.png" align="middle" alt="Hash policy class diagram" /></div></div></div><br class="figure-break" /></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.hash.details.resize_policies"></a>Resize Policies</h6></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="resize_policies.general"></a>General</h6></div></div></div><p>Hash-tables, as opposed to trees, do not naturally grow or
-+ </p><div class="figure"><a id="idm269997315408"></a><p class="title"><strong>Figure 22.17. Hash policy class diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_hash_policy_cd.png" align="middle" alt="Hash policy class diagram" /></div></div></div><br class="figure-break" /></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.hash.details.resize_policies"></a>Resize Policies</h6></div></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="resize_policies.general"></a>General</h6></div></div></div><p>Hash-tables, as opposed to trees, do not naturally grow or
- shrink. It is necessary to specify policies to determine how
- and when a hash table should change its size. Usually, resize
- policies can be decomposed into orthogonal policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>A size policy indicating how a hash table
-@@ -667,10 +667,10 @@
- and some load factor be denoted by Α. We would like to
- calculate the minimal length of k, such that if there were Α
- m elements in the hash table, a probe sequence of length k would
-- be found with probability at most 1/m.</p><div class="figure"><a id="idp18234944"></a><p class="title"><strong>Figure 22.18. Balls and bins</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_balls_and_bins.png" align="middle" alt="Balls and bins" /></div></div></div><br class="figure-break" /><p>Denote the probability that a probe sequence of length
-+ be found with probability at most 1/m.</p><div class="figure"><a id="idm269997296368"></a><p class="title"><strong>Figure 22.18. Balls and bins</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_balls_and_bins.png" align="middle" alt="Balls and bins" /></div></div></div><br class="figure-break" /><p>Denote the probability that a probe sequence of length
- k appears in bin i by p<sub>i</sub>, the
- length of the probe sequence of bin i by
-- l<sub>i</sub>, and assume uniform distribution. Then</p><div class="equation"><a id="idp18240448"></a><p class="title"><strong>Equation 22.7. 
-+ l<sub>i</sub>, and assume uniform distribution. Then</p><div class="equation"><a id="idm269997290864"></a><p class="title"><strong>Equation 22.7. 
- Probability of Probe Sequence of Length k
- </strong></p><div class="equation-contents"><span class="mathphrase">
- p<sub>1</sub> =
-@@ -684,7 +684,7 @@
- l<sub>i</sub> are negatively-dependent
- (<a class="xref" href="policy_data_structures.html#biblio.dubhashi98neg" title="Balls and bins: A study in negative dependence">[biblio.dubhashi98neg]</a>)
- . Let
-- I(.) denote the indicator function. Then</p><div class="equation"><a id="idp18247216"></a><p class="title"><strong>Equation 22.8. 
-+ I(.) denote the indicator function. Then</p><div class="equation"><a id="idm269997284096"></a><p class="title"><strong>Equation 22.8. 
- Probability Probe Sequence in Some Bin
- </strong></p><div class="equation-contents"><span class="mathphrase">
- P( exists<sub>i</sub> l<sub>i</sub> ≥ k ) =
-@@ -723,7 +723,7 @@
- a resize is needed, and if so, what is the new size (points D
- to G); following the resize, it notifies the policy that a
- resize has completed (point H); finally, the element is
-- inserted, and the policy notified (point I).</p><div class="figure"><a id="idp18265728"></a><p class="title"><strong>Figure 22.19. Insert resize sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram1.png" align="middle" alt="Insert resize sequence diagram" /></div></div></div><br class="figure-break" /><p>In practice, a resize policy can be usually orthogonally
-+ inserted, and the policy notified (point I).</p><div class="figure"><a id="idm269997265648"></a><p class="title"><strong>Figure 22.19. Insert resize sequence diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram1.png" align="middle" alt="Insert resize sequence diagram" /></div></div></div><br class="figure-break" /><p>In practice, a resize policy can be usually orthogonally
- decomposed to a size policy and a trigger policy. Consequently,
- the library contains a single class for instantiating a resize
- policy: <code class="classname">hash_standard_resize_policy</code>
-@@ -732,8 +732,8 @@
- both, and acts as a standard delegate (<a class="xref" href="policy_data_structures.html#biblio.gof" title="Design Patterns - Elements of Reusable Object-Oriented Software">[biblio.gof]</a>)
- to these policies.</p><p>The two graphics immediately below show sequence diagrams
- illustrating the interaction between the standard resize policy
-- and its trigger and size policies, respectively.</p><div class="figure"><a id="idp18273504"></a><p class="title"><strong>Figure 22.20. Standard resize policy trigger sequence
-- diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram2.png" align="middle" alt="Standard resize policy trigger sequence diagram" /></div></div></div><br class="figure-break" /><div class="figure"><a id="idp18277664"></a><p class="title"><strong>Figure 22.21. Standard resize policy size sequence
-+ and its trigger and size policies, respectively.</p><div class="figure"><a id="idm269997257872"></a><p class="title"><strong>Figure 22.20. Standard resize policy trigger sequence
-+ diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram2.png" align="middle" alt="Standard resize policy trigger sequence diagram" /></div></div></div><br class="figure-break" /><div class="figure"><a id="idm269997253712"></a><p class="title"><strong>Figure 22.21. Standard resize policy size sequence
- diagram</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_insert_resize_sequence_diagram3.png" align="middle" alt="Standard resize policy size sequence diagram" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="resize_policies.impl.predefined"></a>Predefined Policies</h6></div></div></div><p>The library includes the following
- instantiations of size and trigger policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p><code class="classname">hash_load_check_resize_trigger</code>
- implements a load check trigger policy.</p></li><li class="listitem"><p><code class="classname">cc_hash_max_collision_check_resize_trigger</code>
-@@ -876,7 +876,7 @@
- each node, and maintains node invariants (see <a class="xref" href="policy_data_structures.html#biblio.clrs2001" title="Introduction to Algorithms, 2nd edition">[biblio.clrs2001]</a>.) The first stores in
- each node the size of the sub-tree rooted at the node; the
- second stores at each node the maximal endpoint of the
-- intervals at the sub-tree rooted at the node.</p><div class="figure"><a id="idp18355696"></a><p class="title"><strong>Figure 22.22. Tree node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invariants.png" align="middle" alt="Tree node invariants" /></div></div></div><br class="figure-break" /><p>Supporting such trees is difficult for a number of
-+ intervals at the sub-tree rooted at the node.</p><div class="figure"><a id="idm269997175616"></a><p class="title"><strong>Figure 22.22. Tree node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invariants.png" align="middle" alt="Tree node invariants" /></div></div></div><br class="figure-break" /><p>Supporting such trees is difficult for a number of
- reasons:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>There must be a way to specify what a node's metadata
- should be (if any).</p></li><li class="listitem"><p>Various operations can invalidate node
- invariants. The graphic below shows how a right rotation,
-@@ -890,7 +890,7 @@
- metadata.</p></li><li class="listitem"><p>It is not feasible to know in advance which methods trees
- can support. Besides the usual <code class="classname">find</code> method, the
- first tree can support a <code class="classname">find_by_order</code> method, while
-- the second can support an <code class="classname">overlaps</code> method.</p></li></ol></div><div class="figure"><a id="idp18365136"></a><p class="title"><strong>Figure 22.23. Tree node invalidation</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invalidations.png" align="middle" alt="Tree node invalidation" /></div></div></div><br class="figure-break" /><p>These problems are solved by a combination of two means:
-+ the second can support an <code class="classname">overlaps</code> method.</p></li></ol></div><div class="figure"><a id="idm269997166176"></a><p class="title"><strong>Figure 22.23. Tree node invalidation</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_invalidations.png" align="middle" alt="Tree node invalidation" /></div></div></div><br class="figure-break" /><p>These problems are solved by a combination of two means:
- node iterators, and template-template node updater
- parameters.</p><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.tree.node.iterators"></a>Node Iterators</h6></div></div></div><p>Each tree-based container defines two additional iterator
- types, <code class="classname">const_node_iterator</code>
-@@ -919,7 +919,7 @@
- <code class="classname">node_update</code> class, and publicly subclasses
- <code class="classname">node_update</code>. The graphic below shows this
- scheme, as well as some predefined policies (which are explained
-- below).</p><div class="figure"><a id="idp18378304"></a><p class="title"><strong>Figure 22.24. A tree and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_updator_policy_cd.png" align="middle" alt="A tree and its update policy" /></div></div></div><br class="figure-break" /><p><code class="classname">node_update</code> (an instantiation of
-+ below).</p><div class="figure"><a id="idm269997153072"></a><p class="title"><strong>Figure 22.24. A tree and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_tree_node_updator_policy_cd.png" align="middle" alt="A tree and its update policy" /></div></div></div><br class="figure-break" /><p><code class="classname">node_update</code> (an instantiation of
- <code class="classname">Node_Update</code>) must define <code class="classname">metadata_type</code> as
- the type of metadata it requires. For order statistics,
- e.g., <code class="classname">metadata_type</code> might be <code class="classname">size_t</code>.
-@@ -938,7 +938,7 @@
- <code class="classname">nd_it</code>. For example, say node x in the
- graphic below label A has an invalid invariant, but its' children,
- y and z have valid invariants. After the invocation, all three
-- nodes should have valid invariants, as in label B.</p><div class="figure"><a id="idp18389968"></a><p class="title"><strong>Figure 22.25. Restoring node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_restoring_node_invariants.png" align="middle" alt="Restoring node invariants" /></div></div></div><br class="figure-break" /><p>When a tree operation might invalidate some node invariant,
-+ nodes should have valid invariants, as in label B.</p><div class="figure"><a id="idm269997141408"></a><p class="title"><strong>Figure 22.25. Restoring node invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_restoring_node_invariants.png" align="middle" alt="Restoring node invariants" /></div></div></div><br class="figure-break" /><p>When a tree operation might invalidate some node invariant,
- it invokes this method in its <code class="classname">node_update</code> base to
- restore the invariant. For example, the graphic below shows
- an <code class="function">insert</code> operation (point A); the tree performs some
-@@ -946,7 +946,7 @@
- C, and D). (It is well known that any <code class="function">insert</code>,
- <code class="function">erase</code>, <code class="function">split</code> or <code class="function">join</code>, can restore
- all node invariants by a small number of node invariant updates (<a class="xref" href="policy_data_structures.html#biblio.clrs2001" title="Introduction to Algorithms, 2nd edition">[biblio.clrs2001]</a>)
-- .</p><div class="figure"><a id="idp18398144"></a><p class="title"><strong>Figure 22.26. Insert update sequence</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_update_seq_diagram.png" align="middle" alt="Insert update sequence" /></div></div></div><br class="figure-break" /><p>To complete the description of the scheme, three questions
-+ .</p><div class="figure"><a id="idm269997133232"></a><p class="title"><strong>Figure 22.26. Insert update sequence</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_update_seq_diagram.png" align="middle" alt="Insert update sequence" /></div></div></div><br class="figure-break" /><p>To complete the description of the scheme, three questions
- need to be answered:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>How can a tree which supports order statistics define a
- method such as <code class="classname">find_by_order</code>?</p></li><li class="listitem"><p>How can the node updater base access methods of the
- tree?</p></li><li class="listitem"><p>How can the following cyclic dependency be resolved?
-@@ -988,7 +988,7 @@
- node's metadata (this is halting reducible). In the graphic
- below, assume the shaded node is inserted. The tree would have
- to traverse the useless path shown to the root, applying
-- redundant updates all the way.</p></li></ol></div><div class="figure"><a id="idp18420400"></a><p class="title"><strong>Figure 22.27. Useless update path</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_rationale_null_node_updator.png" align="middle" alt="Useless update path" /></div></div></div><br class="figure-break" /><p>A null policy class, <code class="classname">null_node_update</code>
-+ redundant updates all the way.</p></li></ol></div><div class="figure"><a id="idm269997110976"></a><p class="title"><strong>Figure 22.27. Useless update path</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_rationale_null_node_updator.png" align="middle" alt="Useless update path" /></div></div></div><br class="figure-break" /><p>A null policy class, <code class="classname">null_node_update</code>
- solves both these problems. The tree detects that node
- invariants are irrelevant, and defines all accordingly.</p></div></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.tree.details.split"></a>Split and Join</h6></div></div></div><p>Tree-based containers support split and join methods.
- It is possible to split a tree so that it passes
-@@ -1071,7 +1071,7 @@
- sub-tree with leafs "a" and "as". The maximal common prefix is
- "a". The internal node contains, consequently, to const
- iterators, one pointing to <code class="varname">'a'</code>, and the other to
-- <code class="varname">'s'</code>.</p><div class="figure"><a id="idp18465088"></a><p class="title"><strong>Figure 22.28. A PATRICIA trie</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_pat_trie.png" align="middle" alt="A PATRICIA trie" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.trie.details.node"></a>Node Invariants</h6></div></div></div><p>Trie-based containers support node invariants, as do
-+ <code class="varname">'s'</code>.</p><div class="figure"><a id="idm269997066288"></a><p class="title"><strong>Figure 22.28. A PATRICIA trie</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_pat_trie.png" align="middle" alt="A PATRICIA trie" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.trie.details.node"></a>Node Invariants</h6></div></div></div><p>Trie-based containers support node invariants, as do
- tree-based containers. There are two minor
- differences, though, which, unfortunately, thwart sharing them
- sharing the same node-updating policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>A trie's <code class="classname">Node_Update</code> template-template
-@@ -1080,7 +1080,7 @@
- parametrized by <code class="classname">Cmp_Fn</code>.</p></li><li class="listitem"><p>Tree-based containers store values in all nodes, while
- trie-based containers (at least in this implementation) store
- values in leafs.</p></li></ol></div><p>The graphic below shows the scheme, as well as some predefined
-- policies (which are explained below).</p><div class="figure"><a id="idp18475584"></a><p class="title"><strong>Figure 22.29. A trie and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_trie_node_updator_policy_cd.png" align="middle" alt="A trie and its update policy" /></div></div></div><br class="figure-break" /><p>This library offers the following pre-defined trie node
-+ policies (which are explained below).</p><div class="figure"><a id="idm269997055856"></a><p class="title"><strong>Figure 22.29. A trie and its update policy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_trie_node_updator_policy_cd.png" align="middle" alt="A trie and its update policy" /></div></div></div><br class="figure-break" /><p>This library offers the following pre-defined trie node
- updating policies:</p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>
- <code class="classname">trie_order_statistics_node_update</code>
- supports order statistics.
-@@ -1128,7 +1128,7 @@
- simple list of integer keys. If we search for the integer 6, we
- are paying an overhead: the link with key 6 is only the fifth
- link; if it were the first link, it could be accessed
-- faster.</p><div class="figure"><a id="idp18506160"></a><p class="title"><strong>Figure 22.30. A simple list</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_simple_list.png" align="middle" alt="A simple list" /></div></div></div><br class="figure-break" /><p>List-update algorithms reorder lists as elements are
-+ faster.</p><div class="figure"><a id="idm269997025344"></a><p class="title"><strong>Figure 22.30. A simple list</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_simple_list.png" align="middle" alt="A simple list" /></div></div></div><br class="figure-break" /><p>List-update algorithms reorder lists as elements are
- accessed. They try to determine, by the access history, which
- keys to move to the front of the list. Some of these algorithms
- require adding some metadata alongside each entry.</p><p>For example, in the graphic below label A shows the counter
-@@ -1138,7 +1138,7 @@
- predetermined value, say 10, as shown in label C, the count is set
- to 0 and the node is moved to the front of the list, as in label
- D.
-- </p><div class="figure"><a id="idp18511744"></a><p class="title"><strong>Figure 22.31. The counter algorithm</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_list_update.png" align="middle" alt="The counter algorithm" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.list.details.policies"></a>Policies</h6></div></div></div><p>this library allows instantiating lists with policies
-+ </p><div class="figure"><a id="idm269997019760"></a><p class="title"><strong>Figure 22.31. The counter algorithm</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_list_update.png" align="middle" alt="The counter algorithm" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h6 class="title"><a id="container.list.details.policies"></a>Policies</h6></div></div></div><p>this library allows instantiating lists with policies
- implementing any algorithm moving nodes to the front of the
- list (policies implementing algorithms interchanging nodes are
- unsupported).</p><p>Associative containers based on lists are parametrized by a
-@@ -1310,7 +1310,7 @@
- sequence; the second uses a tree (or forest of trees), which is
- typically less structured than an associative container's tree;
- the third simply uses an associative container. These are
-- shown in the graphic below, in labels A1 and A2, label B, and label C.</p><div class="figure"><a id="idp18575568"></a><p class="title"><strong>Figure 22.32. Underlying Priority-Queue Data-Structures.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_different_underlying_dss.png" align="middle" alt="Underlying Priority-Queue Data-Structures." /></div></div></div><br class="figure-break" /><p>Roughly speaking, any value that is both pushed and popped
-+ shown in the graphic below, in labels A1 and A2, label B, and label C.</p><div class="figure"><a id="idm269996955920"></a><p class="title"><strong>Figure 22.32. Underlying Priority-Queue Data-Structures.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_different_underlying_dss.png" align="middle" alt="Underlying Priority-Queue Data-Structures." /></div></div></div><br class="figure-break" /><p>Roughly speaking, any value that is both pushed and popped
- from a priority queue must incur a logarithmic expense (in the
- amortized sense). Any priority queue implementation that would
- avoid this, would violate known bounds on comparison-based
-@@ -1390,7 +1390,7 @@
- container <code class="classname">Cntnr</code>, the tag of the underlying
- data structure can be found via <code class="classname">typename
- Cntnr::container_category</code>; this is one of the possible tags shown in the graphic below.
-- </p><div class="figure"><a id="idp18610544"></a><p class="title"><strong>Figure 22.33. Priority-Queue Data-Structure Tags.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_tag_hierarchy.png" align="middle" alt="Priority-Queue Data-Structure Tags." /></div></div></div><br class="figure-break" /><p>Additionally, a traits mechanism can be used to query a
-+ </p><div class="figure"><a id="idm269996920880"></a><p class="title"><strong>Figure 22.33. Priority-Queue Data-Structure Tags.</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_tag_hierarchy.png" align="middle" alt="Priority-Queue Data-Structure Tags." /></div></div></div><br class="figure-break" /><p>Additionally, a traits mechanism can be used to query a
- container type for its attributes. Given any container
- <code class="classname">Cntnr</code>, then </p><pre class="programlisting">__gnu_pbds::container_traits&lt;Cntnr&gt;</pre><p>
- is a traits class identifying the properties of the
-Index: libstdc++-v3/doc/html/manual/using.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/using.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/using.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 3. Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="make.html" title="Make" /><link rel="next" href="using_headers.html" title="Headers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 3. Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><th width="60%" align="center">Part I. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 3. Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="make.html" title="Make" /><link rel="next" href="using_headers.html" title="Headers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 3. Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><th width="60%" align="center">Part I. 
- Introduction
-
--</th><td width="20%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.using"></a>Chapter 3. Using</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a 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-+</th><td width="20%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.using"></a>Chapter 3. Using</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a 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class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.flags"></a>Command Options</h2></div></div></div><p>
- The set of features available in the GNU C++ library is shaped
- by
- several <a class="link" href="http://gcc.gnu.org/onlinedocs/gcc-4.3.2/gcc/Invoking-GCC.html" target="_top">GCC
-@@ -10,5 +10,5 @@
- enumerated and detailed in the table below.
- </p><p>
- By default, <span class="command"><strong>g++</strong></span> is equivalent to <span class="command"><strong>g++ -std=gnu++98</strong></span>. The standard library also defaults to this dialect.
-- </p><div class="table"><a id="idp13051936"></a><p class="title"><strong>Table 3.1. C++ Command Options</strong></p><div class="table-contents"><table summary="C++ Command Options" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Option Flags</th><th align="left">Description</th></tr></thead><tbody><tr><td align="left"><code class="literal">-std=c++98</code></td><td align="left">Use the 1998 ISO C++ standard plus amendments.</td></tr><tr><td align="left"><code class="literal">-std=gnu++98</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-std=c++11</code></td><td align="left">Use the 2011 ISO C++ standard.</td></tr><tr><td align="left"><code class="literal">-std=gnu++11</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-fexceptions</code></td><td align="left">See <a class="link" href="using_exceptions.html#intro.using.exception.no" title="Doing without">exception-free dialect</a></td></tr><tr><td align="left"><code class="literal">-frtti</code></td><td align="left">As above, but RTTI-free dialect.</td></tr><tr><td align="left"><code class="literal">-pthread</code> or <code class="literal">-pthreads</code></td><td align="left">For ISO C++11 &lt;thread&gt;, &lt;future&gt;,
-+ </p><div class="table"><a id="idm270002481088"></a><p class="title"><strong>Table 3.1. C++ Command Options</strong></p><div class="table-contents"><table summary="C++ Command Options" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Option Flags</th><th align="left">Description</th></tr></thead><tbody><tr><td align="left"><code class="literal">-std=c++98</code></td><td align="left">Use the 1998 ISO C++ standard plus amendments.</td></tr><tr><td align="left"><code class="literal">-std=gnu++98</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-std=c++11</code></td><td align="left">Use the 2011 ISO C++ standard.</td></tr><tr><td align="left"><code class="literal">-std=gnu++11</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-fexceptions</code></td><td align="left">See <a class="link" href="using_exceptions.html#intro.using.exception.no" title="Doing without">exception-free dialect</a></td></tr><tr><td align="left"><code class="literal">-frtti</code></td><td align="left">As above, but RTTI-free dialect.</td></tr><tr><td align="left"><code class="literal">-pthread</code> or <code class="literal">-pthreads</code></td><td align="left">For ISO C++11 &lt;thread&gt;, &lt;future&gt;,
- &lt;mutex&gt;, or &lt;condition_variable&gt;.</td></tr><tr><td align="left"><code class="literal">-fopenmp</code></td><td align="left">For <a class="link" href="parallel_mode.html" title="Chapter 18. Parallel Mode">parallel</a> mode.</td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="intro.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Make </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Headers</td></tr></table></div></body></html>
-\ No newline at end of file
-Index: libstdc++-v3/doc/html/manual/profile_mode_impl.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/profile_mode_impl.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/profile_mode_impl.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_cost_model.html" title="Empirical Cost Model" /><link rel="next" href="profile_mode_devel.html" title="Developer Information" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_cost_model.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_devel.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.implementation"></a>Implementation Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.implementation.stack"></a>Stack Traces</h3></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_cost_model.html" title="Empirical Cost Model" /><link rel="next" href="profile_mode_devel.html" title="Developer Information" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_cost_model.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_devel.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.implementation"></a>Implementation Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.implementation.stack"></a>Stack Traces</h3></div></div></div><p>
- Accurate stack traces are needed during profiling since we group events by
- call context and dynamic instance. Without accurate traces, diagnostics
- may be hard to interpret. For instance, when giving advice to the user
-Index: libstdc++-v3/doc/html/manual/ext_containers.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/ext_containers.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/ext_containers.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 23. HP/SGI Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="policy_data_structures_ack.html" title="Acknowledgments" /><link rel="next" href="ext_sgi.html" title="Deprecated" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 23. HP/SGI Extensions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_ack.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 23. HP/SGI Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="policy_data_structures_ack.html" title="Acknowledgments" /><link rel="next" href="ext_sgi.html" title="Deprecated" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 23. HP/SGI Extensions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_ack.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="ext_sgi.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers"></a>Chapter 23. HP/SGI Extensions</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="ext_containers.html#manual.ext.containers.sgi">Backwards Compatibility</a></span></dt><dt><span class="section"><a href="ext_sgi.html">Deprecated</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.sgi"></a>Backwards Compatibility</h2></div></div></div><p>A few extensions and nods to backwards-compatibility have
-+</th><td width="20%" align="right"> <a accesskey="n" href="ext_sgi.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers"></a>Chapter 23. HP/SGI Extensions</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_containers.html#manual.ext.containers.sgi">Backwards Compatibility</a></span></dt><dt><span class="section"><a href="ext_sgi.html">Deprecated</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.sgi"></a>Backwards Compatibility</h2></div></div></div><p>A few extensions and nods to backwards-compatibility have
- been made with containers. Those dealing with older SGI-style
- allocators are dealt with elsewhere. The remaining ones all deal
- with bits:
-Index: libstdc++-v3/doc/html/manual/ext_concurrency_use.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/ext_concurrency_use.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/ext_concurrency_use.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency_impl.html" title="Implementation" /><link rel="next" href="appendix.html" title="Part IV.  Appendices" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="appendix.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.use"></a>Use</h2></div></div></div><p>Typical usage of the last two constructs is demonstrated as follows:
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency_impl.html" title="Implementation" /><link rel="next" href="appendix.html" title="Part IV.  Appendices" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="appendix.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.use"></a>Use</h2></div></div></div><p>Typical usage of the last two constructs is demonstrated as follows:
- </p><pre class="programlisting">
- #include &lt;ext/concurrence.h&gt;
-
-Index: libstdc++-v3/doc/html/manual/ext_io.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/ext_io.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/ext_io.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 28. Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_iterators.html" title="Chapter 27. Iterators" /><link rel="next" href="ext_demangling.html" title="Chapter 29. Demangling" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 28. Input and Output</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_iterators.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 28. Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_iterators.html" title="Chapter 27. Iterators" /><link rel="next" href="ext_demangling.html" title="Chapter 29. Demangling" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 28. Input and Output</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_iterators.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="ext_demangling.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.io"></a>Chapter 28. Input and Output</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="ext_io.html#manual.ext.io.filebuf_derived">Derived filebufs</a></span></dt></dl></div><p>
-+</th><td width="20%" align="right"> <a accesskey="n" href="ext_demangling.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.io"></a>Chapter 28. Input and Output</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_io.html#manual.ext.io.filebuf_derived">Derived filebufs</a></span></dt></dl></div><p>
- Extensions allowing <code class="code">filebuf</code>s to be constructed from
- "C" types like FILE*s and file descriptors.
- </p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.io.filebuf_derived"></a>Derived filebufs</h2></div></div></div><p>The v2 library included non-standard extensions to construct
-Index: libstdc++-v3/doc/html/manual/termination.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/termination.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/termination.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Termination</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4.  Support" /><link rel="prev" href="dynamic_memory.html" title="Dynamic Memory" /><link rel="next" href="diagnostics.html" title="Chapter 5.  Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Termination</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="dynamic_memory.html">Prev</a> </td><th width="60%" align="center">Chapter 4. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Termination</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4.  Support" /><link rel="prev" href="dynamic_memory.html" title="Dynamic Memory" /><link rel="next" href="diagnostics.html" title="Chapter 5.  Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Termination</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="dynamic_memory.html">Prev</a> </td><th width="60%" align="center">Chapter 4. 
- Support
-
- </th><td width="20%" align="right"> <a accesskey="n" href="diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.support.termination"></a>Termination</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="support.termination.handlers"></a>Termination Handlers</h3></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/using_macros.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/using_macros.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/using_macros.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Macros</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_headers.html" title="Headers" /><link rel="next" href="using_namespaces.html" title="Namespaces" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Macros</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_headers.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_namespaces.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.macros"></a>Macros</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Macros</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_headers.html" title="Headers" /><link rel="next" href="using_namespaces.html" title="Namespaces" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Macros</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_headers.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_namespaces.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.macros"></a>Macros</h2></div></div></div><p>
- All library macros begin with <code class="code">_GLIBCXX_</code>.
- </p><p>
- Furthermore, all pre-processor macros, switches, and
-Index: libstdc++-v3/doc/html/manual/concurrency.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/concurrency.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/concurrency.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 15.  Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library, mutex, thread, future, condition_variable" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="atomics.html" title="Chapter 14.  Atomics" /><link rel="next" href="extensions.html" title="Part III.  Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 15. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 15.  Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library, mutex, thread, future, condition_variable" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="atomics.html" title="Chapter 14.  Atomics" /><link rel="next" href="extensions.html" title="Part III.  Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 15. 
- Concurrency
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="atomics.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="extensions.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.concurrency"></a>Chapter 15. 
- Concurrency
-- <a id="idp16404464" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="concurrency.html#std.concurrency.api">API Reference</a></span></dt></dl></div><p>
-+ <a id="idm269999126816" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="concurrency.html#std.concurrency.api">API Reference</a></span></dt></dl></div><p>
- Facilities for concurrent operation, and control thereof.
- </p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.concurrency.api"></a>API Reference</h2></div></div></div><p>
- All items are declared in one of four standard header files.
-Index: libstdc++-v3/doc/html/manual/ext_utilities.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/ext_utilities.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/ext_utilities.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 24. Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_sgi.html" title="Deprecated" /><link rel="next" href="ext_algorithms.html" title="Chapter 25. Algorithms" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 24. Utilities</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_sgi.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 24. Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_sgi.html" title="Deprecated" /><link rel="next" href="ext_algorithms.html" title="Chapter 25. Algorithms" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 24. Utilities</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_sgi.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
- </th><td width="20%" align="right"> <a accesskey="n" href="ext_algorithms.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.util"></a>Chapter 24. Utilities</h2></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/policy_data_structures.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/policy_data_structures.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 22. Policy-Based Data Structures</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="bitmap_allocator_impl.html" title="Implementation" /><link rel="next" href="policy_data_structures_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 22. Policy-Based Data Structures</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bitmap_allocator_impl.html">Prev</a> </td><th width="60%" align="center">Part III. 
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- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_using.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers.pbds"></a>Chapter 22. Policy-Based Data Structures</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">
-+</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_using.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers.pbds"></a>Chapter 22. Policy-Based Data Structures</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">
- Configuring via Template Parameters
- </a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.traits">
- Querying Container Attributes
-@@ -248,7 +248,7 @@
- these invariants, one must supply some policy that is aware
- of these changes. Without this, it would be better to use a
- linked list (in itself very efficient for these purposes).
-- </p></li></ol></div><div class="figure"><a id="idp17613296"></a><p class="title"><strong>Figure 22.1. Node Invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_node_invariants.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="motivation.associative.underlying"></a>Underlying Data Structures</h5></div></div></div><p>
-+ </p></li></ol></div><div class="figure"><a id="idm269997917584"></a><p class="title"><strong>Figure 22.1. Node Invariants</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_node_invariants.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="motivation.associative.underlying"></a>Underlying Data Structures</h5></div></div></div><p>
- The standard C++ library contains associative containers based on
- red-black trees and collision-chaining hash tables. These are
- very useful, but they are not ideal for all types of
-@@ -256,7 +256,7 @@
- </p><p>
- The figure below shows the different underlying data structures
- currently supported in this library.
-- </p><div class="figure"><a id="idp17619952"></a><p class="title"><strong>Figure 22.2. Underlying Associative Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_1.png" align="middle" alt="Underlying Associative Data Structures" /></div></div></div><br class="figure-break" /><p>
-+ </p><div class="figure"><a id="idm269997910864"></a><p class="title"><strong>Figure 22.2. Underlying Associative Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_1.png" align="middle" alt="Underlying Associative Data Structures" /></div></div></div><br class="figure-break" /><p>
- A shows a collision-chaining hash-table, B shows a probing
- hash-table, C shows a red-black tree, D shows a splay tree, E shows
- a tree based on an ordered vector(implicit in the order of the
-@@ -375,7 +375,7 @@
- no guarantee that the elements traversed will coincide with the
- <span class="emphasis"><em>logical</em></span> elements between 1 and 5, as in
- label B.
-- </p><div class="figure"><a id="idp17651648"></a><p class="title"><strong>Figure 22.3. Range Iteration in Different Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_1.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /><p>
-+ </p><div class="figure"><a id="idm269997879168"></a><p class="title"><strong>Figure 22.3. Range Iteration in Different Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_1.png" align="middle" alt="Node Invariants" /></div></div></div><br class="figure-break" /><p>
- In our opinion, this problem is not caused just because
- red-black trees are order preserving while
- collision-chaining hash tables are (generally) not - it
-@@ -426,7 +426,7 @@
- list, as in the graphic below, label B. Here the iterators are as
- light as can be, but the hash-table's operations are more
- complicated.
-- </p><div class="figure"><a id="idp17666528"></a><p class="title"><strong>Figure 22.4. Point Iteration in Hash Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_2.png" align="middle" alt="Point Iteration in Hash Data Structures" /></div></div></div><br class="figure-break" /><p>
-+ </p><div class="figure"><a id="idm269997864256"></a><p class="title"><strong>Figure 22.4. Point Iteration in Hash Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_point_iterators_range_ops_2.png" align="middle" alt="Point Iteration in Hash Data Structures" /></div></div></div><br class="figure-break" /><p>
- It should be noted that containers based on collision-chaining
- hash-tables are not the only ones with this type of behavior;
- many other self-organizing data structures display it as well.
-@@ -442,7 +442,7 @@
- container. The graphic below shows three cases: A1 and A2 show
- a red-black tree; B1 and B2 show a probing hash-table; C1 and C2
- show a collision-chaining hash table.
-- </p><div class="figure"><a id="idp17675840"></a><p class="title"><strong>Figure 22.5. Effect of erase in different underlying data structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_guarantee_erase.png" align="middle" alt="Effect of erase in different underlying data structures" /></div></div></div><br class="figure-break" /><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>
-+ </p><div class="figure"><a id="idm269997855056"></a><p class="title"><strong>Figure 22.5. Effect of erase in different underlying data structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_invalidation_guarantee_erase.png" align="middle" alt="Effect of erase in different underlying data structures" /></div></div></div><br class="figure-break" /><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>
- Erasing 5 from A1 yields A2. Clearly, an iterator to 3 can
- be de-referenced and incremented. The sequence of iterators
- changed, but in a way that is well-defined by the interface.
-@@ -678,7 +678,7 @@
- typically less structured than an associative container's tree;
- the third simply uses an associative container. These are
- shown in the figure below with labels A1 and A2, B, and C.
-- </p><div class="figure"><a id="idp17743424"></a><p class="title"><strong>Figure 22.6. Underlying Priority Queue Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_2.png" align="middle" alt="Underlying Priority Queue Data Structures" /></div></div></div><br class="figure-break" /><p>
-+ </p><div class="figure"><a id="idm269997787392"></a><p class="title"><strong>Figure 22.6. Underlying Priority Queue Data Structures</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_different_underlying_dss_2.png" align="middle" alt="Underlying Priority Queue Data Structures" /></div></div></div><br class="figure-break" /><p>
- No single implementation can completely replace any of the
- others. Some have better <code class="function">push</code>
- and <code class="function">pop</code> amortized performance, some have
-@@ -1098,7 +1098,7 @@
- </span>. </span><span class="publisher"><span class="publishername">
- Proceedings of International Conference on Very Large Data Bases
- . </span></span></p></div><div class="biblioentry"><a id="biblio.maverik_lowerbounds"></a><p>[biblio.maverik_lowerbounds] <span class="title"><em>
-- <a class="link" href="http://magic.aladdin.cs.cmu.edu/2005/08/01/deamortization-part-2-binomial-heaps" target="_top">
-+ <a class="link" href="http://magic.aladdin.cs.cmu.edu/2005/08/01/deamortization-part-2-binomial-heaps/" target="_top">
- Deamortization - Part 2: Binomial Heaps
- </a>
- </em>. </span><span class="date">
-@@ -1190,7 +1190,7 @@
- </span>. </span><span class="publisher"><span class="publishername">
- Addison-Wesley Publishing Company
- . </span></span></p></div><div class="biblioentry"><a id="biblio.nelson96stlpq"></a><p>[biblio.nelson96stlpq] <span class="title"><em>
-- <a class="link" href="http://www.dogma.net/markn/articles/pq_stl/priority.htm" target="_top">Priority Queues and the STL
-+ <a class="link" href="http://marknelson.us/1996/01/01/priority-queues/" target="_top">Priority Queues and the STL
- </a>
- </em>. </span><span class="date">
- January 1996
-Index: libstdc++-v3/doc/html/manual/ext_iterators.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/ext_iterators.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/ext_iterators.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 27. Iterators</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_numerics.html" title="Chapter 26. Numerics" /><link rel="next" href="ext_io.html" title="Chapter 28. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 27. Iterators</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_numerics.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 27. Iterators</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_numerics.html" title="Chapter 26. Numerics" /><link rel="next" href="ext_io.html" title="Chapter 28. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 27. Iterators</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_numerics.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
- </th><td width="20%" align="right"> <a accesskey="n" href="ext_io.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.iterators"></a>Chapter 27. Iterators</h2></div></div></div><p>24.3.2 describes <code class="code">struct iterator</code>, which didn't exist in the
-Index: libstdc++-v3/doc/html/manual/bitmap_allocator_impl.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/bitmap_allocator_impl.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/bitmap_allocator_impl.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="prev" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="next" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bitmap_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 21. The bitmap_allocator</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.bitmap.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="bitmap.impl.free_list_store"></a>Free List Store</h3></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="prev" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="next" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bitmap_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 21. The bitmap_allocator</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.bitmap.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="bitmap.impl.free_list_store"></a>Free List Store</h3></div></div></div><p>
- The Free List Store (referred to as FLS for the remaining part of this
- document) is the Global memory pool that is shared by all instances of
- the bitmapped allocator instantiated for any type. This maintains a
-@@ -75,7 +75,7 @@
- </p><p>
- Consider a block of size 64 ints. In memory, it would look like this:
- (assume a 32-bit system where, size_t is a 32-bit entity).
-- </p><div class="table"><a id="idp17500848"></a><p class="title"><strong>Table 21.1. Bitmap Allocator Memory Map</strong></p><div class="table-contents"><table summary="Bitmap Allocator Memory Map" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left">268</td><td align="left">0</td><td align="left">4294967295</td><td align="left">4294967295</td><td align="left">Data -&gt; Space for 64 ints</td></tr></tbody></table></div></div><br class="table-break" /><p>
-+ </p><div class="table"><a id="idm269998030352"></a><p class="title"><strong>Table 21.1. Bitmap Allocator Memory Map</strong></p><div class="table-contents"><table summary="Bitmap Allocator Memory Map" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left">268</td><td align="left">0</td><td align="left">4294967295</td><td align="left">4294967295</td><td align="left">Data -&gt; Space for 64 ints</td></tr></tbody></table></div></div><br class="table-break" /><p>
- The first Column(268) represents the size of the Block in bytes as
- seen by the Bitmap Allocator. Internally, a global free list is
- used to keep track of the free blocks used and given back by the
-Index: libstdc++-v3/doc/html/manual/appendix_contributing.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/appendix_contributing.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/appendix_contributing.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix A.  Contributing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix.html" title="Part IV.  Appendices" /><link rel="next" href="source_organization.html" title="Directory Layout and Source Conventions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix A. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix A.  Contributing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix.html" title="Part IV.  Appendices" /><link rel="next" href="source_organization.html" title="Directory Layout and Source Conventions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix A. 
- Contributing
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix.html">Prev</a> </td><th width="60%" align="center">Part IV. 
-@@ -6,8 +6,8 @@
- Appendices
- </th><td width="20%" align="right"> <a accesskey="n" href="source_organization.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.contrib"></a>
- Contributing
-- <a id="idp21875168" class="indexterm"></a>
--</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="appendix_contributing.html#contrib.list">Contributor Checklist</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#list.reading">Reading</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.copyright">Assignment</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.getting">Getting Sources</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.patches">Submitting Patches</a></span></dt></dl></dd><dt><span class="section"><a href="source_organization.html">Directory Layout and Source Conventions</a></span></dt><dt><span class="section"><a href="source_code_style.html">Coding Style</a></span></dt><dd><dl><dt><span class="section"><a href="source_code_style.html#coding_style.bad_identifiers">Bad Identifiers</a></span></dt><dt><span class="section"><a href="source_code_style.html#coding_style.example">By Example</a></span></dt></dl></dd><dt><span class="section"><a href="source_design_notes.html">Design Notes</a></span></dt></dl></div><p>
-+ <a id="idm269993657472" class="indexterm"></a>
-+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="appendix_contributing.html#contrib.list">Contributor Checklist</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#list.reading">Reading</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.copyright">Assignment</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.getting">Getting Sources</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.patches">Submitting Patches</a></span></dt></dl></dd><dt><span class="section"><a href="source_organization.html">Directory Layout and Source Conventions</a></span></dt><dt><span class="section"><a href="source_code_style.html">Coding Style</a></span></dt><dd><dl><dt><span class="section"><a href="source_code_style.html#coding_style.bad_identifiers">Bad Identifiers</a></span></dt><dt><span class="section"><a href="source_code_style.html#coding_style.example">By Example</a></span></dt></dl></dd><dt><span class="section"><a href="source_design_notes.html">Design Notes</a></span></dt></dl></div><p>
- The GNU C++ Library follows an open development model. Active
- contributors are assigned maintainer-ship responsibility, and given
- write access to the source repository. First time contributors
-@@ -36,7 +36,7 @@
- for this group is quite useful.
- </p></li><li class="listitem"><p>
- Peruse
-- the <a class="link" href="http://www.gnu.org/prep/standards" target="_top">GNU
-+ the <a class="link" href="http://www.gnu.org/prep/standards/" target="_top">GNU
- Coding Standards</a>, and chuckle when you hit the part
- about <span class="quote">“<span class="quote">Using Languages Other Than C</span>”</span>.
- </p></li><li class="listitem"><p>
-Index: libstdc++-v3/doc/html/manual/parallel_mode_test.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/parallel_mode_test.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/parallel_mode_test.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_design.html" title="Design" /><link rel="next" href="profile_mode.html" title="Chapter 19. Profile Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.test"></a>Testing</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_design.html" title="Design" /><link rel="next" href="profile_mode.html" title="Chapter 19. Profile Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.test"></a>Testing</h2></div></div></div><p>
- Both the normal conformance and regression tests and the
- supplemental performance tests work.
- </p><p>
-Index: libstdc++-v3/doc/html/manual/profile_mode.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/profile_mode.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/profile_mode.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 19. Profile Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="parallel_mode_test.html" title="Testing" /><link rel="next" href="profile_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 19. Profile Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_test.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 19. Profile Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="parallel_mode_test.html" title="Testing" /><link rel="next" href="profile_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 19. Profile Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_test.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.profile_mode"></a>Chapter 19. Profile Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.intro"></a>Intro</h2></div></div></div><p>
-+</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.profile_mode"></a>Chapter 19. Profile Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.intro"></a>Intro</h2></div></div></div><p>
- <span class="emphasis"><em>Goal: </em></span>Give performance improvement advice based on
- recognition of suboptimal usage patterns of the standard library.
- </p><p>
-@@ -137,7 +137,7 @@
- call context.
- (Environment variable not supported.)
- </p></li></ul></div><p>
-- </p></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="profile_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idp17395456"></a><p><span class="citetitle"><em class="citetitle">
-+ </p></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="profile_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idm269998135936"></a><p><span class="citetitle"><em class="citetitle">
- Perflint: A Context Sensitive Performance Advisor for C++ Programs
- </em>. </span><span class="author"><span class="firstname">Lixia</span> <span class="surname">Liu</span>. </span><span class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span>. </span><span class="copyright">Copyright © 2009 . </span><span class="publisher"><span class="publishername">
- Proceedings of the 2009 International Symposium on Code Generation
-Index: libstdc++-v3/doc/html/manual/stringstreams.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/stringstreams.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/stringstreams.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="streambufs.html" title="Stream Buffers" /><link rel="next" href="fstreams.html" title="File Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="streambufs.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="streambufs.html" title="Stream Buffers" /><link rel="next" href="fstreams.html" title="File Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="streambufs.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
- Input and Output
-
- </th><td width="20%" align="right"> <a accesskey="n" href="fstreams.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.memstreams"></a>Memory Based Streams</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.memstreams.compat"></a>Compatibility With strstream</h3></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/traits.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/traits.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/traits.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Traits</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="memory.html" title="Memory" /><link rel="next" href="strings.html" title="Chapter 7.  Strings" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Traits</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="memory.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Traits</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="memory.html" title="Memory" /><link rel="next" href="strings.html" title="Chapter 7.  Strings" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Traits</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="memory.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
- Utilities
-
- </th><td width="20%" align="right"> <a accesskey="n" href="strings.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.traits"></a>Traits</h2></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/policy_data_structures_ack.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/policy_data_structures_ack.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures_ack.html (.../branches/gcc-4_8-branch)
-@@ -1,10 +1,9 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Acknowledgments</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_based_data_structures_test.html" title="Testing" /><link rel="next" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Acknowledgments</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_based_data_structures_test.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="ext_containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.ack"></a>Acknowledgments</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Acknowledgments</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_based_data_structures_test.html" title="Testing" /><link rel="next" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Acknowledgments</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_based_data_structures_test.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="ext_containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.ack"></a>Acknowledgments</h2></div></div></div><p>
- Written by Ami Tavory and Vladimir Dreizin (IBM Haifa Research
- Laboratories), and Benjamin Kosnik (Red Hat).
- </p><p>
-- This library was partially written at
-- <a class="link" href="http://www.haifa.il.ibm.com/" target="_top">IBM's Haifa Research Labs</a>.
-+ This library was partially written at IBM's Haifa Research Labs.
- It is based heavily on policy-based design and uses many useful
- techniques from Modern C++ Design: Generic Programming and Design
- Patterns Applied by Andrei Alexandrescu.
-Index: libstdc++-v3/doc/html/manual/associative.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/associative.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/associative.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="containers.html" title="Chapter 9.  Containers" /><link rel="next" href="unordered_associative.html" title="Unordered Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="containers.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="containers.html" title="Chapter 9.  Containers" /><link rel="next" href="unordered_associative.html" title="Unordered Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="containers.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
- Containers
-
- </th><td width="20%" align="right"> <a accesskey="n" href="unordered_associative.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.associative"></a>Associative</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.associative.insert_hints"></a>Insertion Hints</h3></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/ext_concurrency.html
-===================================================================
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-+++ b/src/libstdc++-v3/doc/html/manual/ext_concurrency.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 30. Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_demangling.html" title="Chapter 29. Demangling" /><link rel="next" href="ext_concurrency_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 30. Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_demangling.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 30. Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_demangling.html" title="Chapter 29. Demangling" /><link rel="next" href="ext_concurrency_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 30. Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_demangling.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_impl.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.concurrency"></a>Chapter 30. Concurrency</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="ext_concurrency.html#manual.ext.concurrency.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="ext_concurrency.html#manual.ext.concurrency.design.threads">Interface to Locks and Mutexes</a></span></dt><dt><span class="section"><a href="ext_concurrency.html#manual.ext.concurrency.design.atomics">Interface to Atomic Functions</a></span></dt></dl></dd><dt><span class="section"><a href="ext_concurrency_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="ext_concurrency_impl.html#manual.ext.concurrency.impl.atomic_fallbacks">Using Builtin Atomic Functions</a></span></dt><dt><span class="section"><a href="ext_concurrency_impl.html#manual.ext.concurrency.impl.thread">Thread Abstraction</a></span></dt></dl></dd><dt><span class="section"><a href="ext_concurrency_use.html">Use</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.design"></a>Design</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.design.threads"></a>Interface to Locks and Mutexes</h3></div></div></div><p>The file <code class="filename">&lt;ext/concurrence.h&gt;</code>
-+</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_impl.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.concurrency"></a>Chapter 30. Concurrency</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_concurrency.html#manual.ext.concurrency.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="ext_concurrency.html#manual.ext.concurrency.design.threads">Interface to Locks and Mutexes</a></span></dt><dt><span class="section"><a href="ext_concurrency.html#manual.ext.concurrency.design.atomics">Interface to Atomic Functions</a></span></dt></dl></dd><dt><span class="section"><a href="ext_concurrency_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="ext_concurrency_impl.html#manual.ext.concurrency.impl.atomic_fallbacks">Using Builtin Atomic Functions</a></span></dt><dt><span class="section"><a href="ext_concurrency_impl.html#manual.ext.concurrency.impl.thread">Thread Abstraction</a></span></dt></dl></dd><dt><span class="section"><a href="ext_concurrency_use.html">Use</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.design"></a>Design</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.design.threads"></a>Interface to Locks and Mutexes</h3></div></div></div><p>The file <code class="filename">&lt;ext/concurrence.h&gt;</code>
- contains all the higher-level
- constructs for playing with threads. In contrast to the atomics layer,
- the concurrence layer consists largely of types. All types are defined within <code class="code">namespace __gnu_cxx</code>.
-Index: libstdc++-v3/doc/html/manual/support.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/support.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/support.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 4.  Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="next" href="dynamic_memory.html" title="Dynamic Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 4. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 4.  Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="next" href="dynamic_memory.html" title="Dynamic Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 4. 
- Support
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="std_contents.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="dynamic_memory.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.support"></a>Chapter 4. 
- Support
-- <a id="idp13745936" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="support.html#std.support.types">Types</a></span></dt><dd><dl><dt><span class="section"><a href="support.html#std.support.types.fundamental">Fundamental Types</a></span></dt><dt><span class="section"><a href="support.html#std.support.types.numeric_limits">Numeric Properties</a></span></dt><dt><span class="section"><a href="support.html#std.support.types.null">NULL</a></span></dt></dl></dd><dt><span class="section"><a href="dynamic_memory.html">Dynamic Memory</a></span></dt><dt><span class="section"><a href="termination.html">Termination</a></span></dt><dd><dl><dt><span class="section"><a href="termination.html#support.termination.handlers">Termination Handlers</a></span></dt><dt><span class="section"><a href="termination.html#support.termination.verbose">Verbose Terminate Handler</a></span></dt></dl></dd></dl></div><p>
-+ <a id="idm270001786944" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="support.html#std.support.types">Types</a></span></dt><dd><dl><dt><span class="section"><a href="support.html#std.support.types.fundamental">Fundamental Types</a></span></dt><dt><span class="section"><a href="support.html#std.support.types.numeric_limits">Numeric Properties</a></span></dt><dt><span class="section"><a href="support.html#std.support.types.null">NULL</a></span></dt></dl></dd><dt><span class="section"><a href="dynamic_memory.html">Dynamic Memory</a></span></dt><dt><span class="section"><a href="termination.html">Termination</a></span></dt><dd><dl><dt><span class="section"><a href="termination.html#support.termination.handlers">Termination Handlers</a></span></dt><dt><span class="section"><a href="termination.html#support.termination.verbose">Verbose Terminate Handler</a></span></dt></dl></dd></dl></div><p>
- This part deals with the functions called and objects created
- automatically during the course of a program's existence.
- </p><p>
-Index: libstdc++-v3/doc/html/manual/bitmap_allocator.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/bitmap_allocator.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/bitmap_allocator.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 21. The bitmap_allocator</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="mt_allocator_ex_multi.html" title="Multiple Thread Example" /><link rel="next" href="bitmap_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 21. The bitmap_allocator</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_ex_multi.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 21. The bitmap_allocator</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="mt_allocator_ex_multi.html" title="Multiple Thread Example" /><link rel="next" href="bitmap_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 21. The bitmap_allocator</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_ex_multi.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.allocator.bitmap"></a>Chapter 21. The bitmap_allocator</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="bitmap_allocator.html#allocator.bitmap.design">Design</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.free_list_store">Free List Store</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block">Super Block</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block_data">Super Block Data Layout</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.max_wasted">Maximum Wasted Percentage</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.allocate"><code class="function">allocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.deallocate"><code class="function">deallocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.questions">Questions</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.1">1</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.2">2</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.3">3</a></span></dt></dl></dd><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.locality">Locality</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.grow_policy">Overhead and Grow Policy</a></span></dt></dl></dd></dl></div><p>
-+</th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.allocator.bitmap"></a>Chapter 21. The bitmap_allocator</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="bitmap_allocator.html#allocator.bitmap.design">Design</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.free_list_store">Free List Store</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block">Super Block</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block_data">Super Block Data Layout</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.max_wasted">Maximum Wasted Percentage</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.allocate"><code class="function">allocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.deallocate"><code class="function">deallocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.questions">Questions</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.1">1</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.2">2</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.3">3</a></span></dt></dl></dd><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.locality">Locality</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.grow_policy">Overhead and Grow Policy</a></span></dt></dl></dd></dl></div><p>
- </p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.bitmap.design"></a>Design</h2></div></div></div><p>
- As this name suggests, this allocator uses a bit-map to keep track
- of the used and unused memory locations for its book-keeping
-Index: libstdc++-v3/doc/html/manual/license.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/license.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/license.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="status.html" title="Chapter 1. Status" /><link rel="next" href="bugs.html" title="Bugs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="status.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="bugs.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.license"></a>License</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="status.html" title="Chapter 1. Status" /><link rel="next" href="bugs.html" title="Bugs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="status.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="bugs.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.license"></a>License</h2></div></div></div><p>
- There are two licenses affecting GNU libstdc++: one for the code,
- and one for the documentation.
- </p><p>
-Index: libstdc++-v3/doc/html/manual/numerics.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/numerics.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/numerics.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 12.  Numerics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="algorithms.html" title="Chapter 11.  Algorithms" /><link rel="next" href="generalized_numeric_operations.html" title="Generalized Operations" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 12. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 12.  Numerics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="algorithms.html" title="Chapter 11.  Algorithms" /><link rel="next" href="generalized_numeric_operations.html" title="Generalized Operations" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 12. 
- Numerics
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="algorithms.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="generalized_numeric_operations.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.numerics"></a>Chapter 12. 
- Numerics
-- <a id="idp16214640" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="numerics.html#std.numerics.complex">Complex</a></span></dt><dd><dl><dt><span class="section"><a href="numerics.html#numerics.complex.processing">complex Processing</a></span></dt></dl></dd><dt><span class="section"><a href="generalized_numeric_operations.html">Generalized Operations</a></span></dt><dt><span class="section"><a href="numerics_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="numerics_and_c.html#numerics.c.array">Numerics vs. Arrays</a></span></dt><dt><span class="section"><a href="numerics_and_c.html#numerics.c.c99">C99</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.complex"></a>Complex</h2></div></div></div><p>
-+ <a id="idm269999316576" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="numerics.html#std.numerics.complex">Complex</a></span></dt><dd><dl><dt><span class="section"><a href="numerics.html#numerics.complex.processing">complex Processing</a></span></dt></dl></dd><dt><span class="section"><a href="generalized_numeric_operations.html">Generalized Operations</a></span></dt><dt><span class="section"><a href="numerics_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="numerics_and_c.html#numerics.c.array">Numerics vs. Arrays</a></span></dt><dt><span class="section"><a href="numerics_and_c.html#numerics.c.c99">C99</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.complex"></a>Complex</h2></div></div></div><p>
- </p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="numerics.complex.processing"></a>complex Processing</h3></div></div></div><p>
- </p><p>Using <code class="code">complex&lt;&gt;</code> becomes even more comple- er, sorry,
- <span class="emphasis"><em>complicated</em></span>, with the not-quite-gratuitously-incompatible
-Index: libstdc++-v3/doc/html/manual/using_exceptions.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/using_exceptions.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/using_exceptions.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Exceptions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, exception, error, exception neutrality, exception safety, exception propagation, -fno-exceptions" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_concurrency.html" title="Concurrency" /><link rel="next" href="debug.html" title="Debugging Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Exceptions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="debug.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.exceptions"></a>Exceptions</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Exceptions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, exception, error, exception neutrality, exception safety, exception propagation, -fno-exceptions" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_concurrency.html" title="Concurrency" /><link rel="next" href="debug.html" title="Debugging Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Exceptions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="debug.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.exceptions"></a>Exceptions</h2></div></div></div><p>
- The C++ language provides language support for stack unwinding
- with <code class="literal">try</code> and <code class="literal">catch</code> blocks and
- the <code class="literal">throw</code> keyword.
-@@ -265,7 +265,7 @@
- }
- catch(...)
- { this-&gt;_M_setstate(ios_base::badbit); }
--</pre></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="using.exceptions.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idp13644000"></a><p><span class="title"><em>
-+</pre></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="using.exceptions.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idm270001889024"></a><p><span class="title"><em>
- <a class="link" href="http://www.opengroup.org/austin/" target="_top">
- System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
- </a>
-@@ -274,39 +274,39 @@
- . </span><span class="copyright">Copyright © 2008
- The Open Group/The Institute of Electrical and Electronics
- Engineers, Inc.
-- . </span></p></div><div class="biblioentry"><a id="idp13647696"></a><p><span class="title"><em>
-+ . </span></p></div><div class="biblioentry"><a id="idm270001885328"></a><p><span class="title"><em>
- <a class="link" href="http://www.boost.org/community/error_handling.html" target="_top">
- Error and Exception Handling
- </a>
- </em>. </span><span class="author"><span class="firstname">David</span> <span class="surname">Abrahams </span>. </span><span class="publisher"><span class="publishername">
- Boost
-- . </span></span></p></div><div class="biblioentry"><a id="idp13651392"></a><p><span class="title"><em>
-+ . </span></span></p></div><div class="biblioentry"><a id="idm270001881632"></a><p><span class="title"><em>
- <a class="link" href="http://www.boost.org/community/exception_safety.html" target="_top">
- Exception-Safety in Generic Components
- </a>
- </em>. </span><span class="author"><span class="firstname">David</span> <span class="surname">Abrahams</span>. </span><span class="publisher"><span class="publishername">
- Boost
-- . </span></span></p></div><div class="biblioentry"><a id="idp13655104"></a><p><span class="title"><em>
-+ . </span></span></p></div><div class="biblioentry"><a id="idm270001877920"></a><p><span class="title"><em>
- <a class="link" href="www.open-std.org/jtc1/sc22/wg21/docs/papers/1997/N1077.pdf" target="_top">
- Standard Library Exception Policy
- </a>
- </em>. </span><span class="author"><span class="firstname">Matt</span> <span class="surname">Austern</span>. </span><span class="publisher"><span class="publishername">
- WG21 N1077
-- . </span></span></p></div><div class="biblioentry"><a id="idp13658816"></a><p><span class="title"><em>
-+ . </span></span></p></div><div class="biblioentry"><a id="idm270001874208"></a><p><span class="title"><em>
- <a class="link" href="http://gcc.gnu.org/ml/gcc-patches/2001-03/msg00661.html" target="_top">
- ia64 c++ abi exception handling
- </a>
- </em>. </span><span class="author"><span class="firstname">Richard</span> <span class="surname">Henderson</span>. </span><span class="publisher"><span class="publishername">
- GNU
-- . </span></span></p></div><div class="biblioentry"><a id="idp13662512"></a><p><span class="title"><em>
-+ . </span></span></p></div><div class="biblioentry"><a id="idm270001870512"></a><p><span class="title"><em>
- <a class="link" href="http://www.research.att.com/~bs/3rd_safe.pdf" target="_top">
- Appendix E: Standard-Library Exception Safety
- </a>
-- </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span></p></div><div class="biblioentry"><a id="idp13665328"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span></p></div><div class="biblioentry"><a id="idm270001867696"></a><p><span class="citetitle"><em class="citetitle">
- Exceptional C++
- </em>. </span><span class="pagenums">
- Exception-Safety Issues and Techniques
-- . </span><span class="author"><span class="firstname">Herb</span> <span class="surname">Sutter</span>. </span></p></div><div class="biblioentry"><a id="idp13667712"></a><p><span class="title"><em>
-+ . </span><span class="author"><span class="firstname">Herb</span> <span class="surname">Sutter</span>. </span></p></div><div class="biblioentry"><a id="idm270001865312"></a><p><span class="title"><em>
- <a class="link" href="http://gcc.gnu.org/PR25191" target="_top">
- GCC Bug 25191: exception_defines.h #defines try/catch
- </a>
-Index: libstdc++-v3/doc/html/manual/policy_based_data_structures_test.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/policy_based_data_structures_test.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/policy_based_data_structures_test.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_design.html" title="Design" /><link rel="next" href="policy_data_structures_ack.html" title="Acknowledgments" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_design.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_ack.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.test"></a>Testing</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.test.regression"></a>Regression</h3></div></div></div><p>The library contains a single comprehensive regression test.
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_design.html" title="Design" /><link rel="next" href="policy_data_structures_ack.html" title="Acknowledgments" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_design.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_ack.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.test"></a>Testing</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.test.regression"></a>Regression</h3></div></div></div><p>The library contains a single comprehensive regression test.
- For a given container type in this library, the test creates
- an object of the container type and an object of the
- corresponding standard type (e.g., <code class="classname">std::set</code>). It
-Index: libstdc++-v3/doc/html/manual/parallel_mode_design.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/parallel_mode_design.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/parallel_mode_design.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_using.html" title="Using" /><link rel="next" href="parallel_mode_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.design"></a>Design</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_using.html" title="Using" /><link rel="next" href="parallel_mode_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.design"></a>Design</h2></div></div></div><p>
- </p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.design.intro"></a>Interface Basics</h3></div></div></div><p>
- All parallel algorithms are intended to have signatures that are
- equivalent to the ISO C++ algorithms replaced. For instance, the
-Index: libstdc++-v3/doc/html/manual/abi.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/abi.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/abi.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>ABI Policy and Guidelines</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, ABI, version, dynamic, shared, compatibility" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="test.html" title="Test" /><link rel="next" href="api.html" title="API Evolution and Deprecation History" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">ABI Policy and Guidelines</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="test.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>ABI Policy and Guidelines</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, ABI, version, dynamic, shared, compatibility" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="test.html" title="Test" /><link rel="next" href="api.html" title="API Evolution and Deprecation History" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">ABI Policy and Guidelines</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="test.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
- Porting and Maintenance
-
- </th><td width="20%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.abi"></a>ABI Policy and Guidelines</h2></div></div></div><p>
-@@ -493,39 +493,39 @@
- <a class="link" href="http://www.codesourcery.com/cxx-abi/" target="_top">
- C++ ABI Summary
- </a>
-- </em>. </span></p></div><div class="biblioentry"><a id="idp22945936"></a><p><span class="title"><em>
-+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992586624"></a><p><span class="title"><em>
- <a class="link" href="http://www.intel.com/cd/software/products/asmo-na/eng/284736.htm" target="_top">
- Intel Compilers for Linux Compatibility with the GNU Compilers
- </a>
-- </em>. </span></p></div><div class="biblioentry"><a id="idp22947792"></a><p><span class="title"><em>
-+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992584768"></a><p><span class="title"><em>
- <a class="link" href="http://download.oracle.com/docs/cd/E19963-01/html/819-0690/index.html" target="_top">
- Linker and Libraries Guide (document 819-0690)
- </a>
-- </em>. </span></p></div><div class="biblioentry"><a id="idp22949632"></a><p><span class="title"><em>
-+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992582928"></a><p><span class="title"><em>
- <a class="link" href="http://download.oracle.com/docs/cd/E19422-01/819-3689/index.html" target="_top">
- Sun Studio 11: C++ Migration Guide (document 819-3689)
- </a>
-- </em>. </span></p></div><div class="biblioentry"><a id="idp22951488"></a><p><span class="title"><em>
-+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992581072"></a><p><span class="title"><em>
- <a class="link" href="http://www.akkadia.org/drepper/dsohowto.pdf" target="_top">
- How to Write Shared Libraries
- </a>
-- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span></p></div><div class="biblioentry"><a id="idp22954928"></a><p><span class="title"><em>
-+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span></p></div><div class="biblioentry"><a id="idm269992577632"></a><p><span class="title"><em>
- <a class="link" href="http://www.arm.com/miscPDFs/8033.pdf" target="_top">
- C++ ABI for the ARM Architecture
- </a>
-- </em>. </span></p></div><div class="biblioentry"><a id="idp22956736"></a><p><span class="title"><em>
-+ </em>. </span></p></div><div class="biblioentry"><a id="idm269992575824"></a><p><span class="title"><em>
- <a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2006/n1976.html" target="_top">
- Dynamic Shared Objects: Survey and Issues
- </a>
- </em>. </span><span class="subtitle">
- ISO C++ J16/06-0046
-- . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idp22960032"></a><p><span class="title"><em>
-+ . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idm269992572528"></a><p><span class="title"><em>
- <a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2006/n2013.html" target="_top">
- Versioning With Namespaces
- </a>
- </em>. </span><span class="subtitle">
- ISO C++ J16/06-0083
-- . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idp22963312"></a><p><span class="title"><em>
-+ . </span><span class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span>. </span></p></div><div class="biblioentry"><a id="idm269992569248"></a><p><span class="title"><em>
- <a class="link" href="http://syrcose.ispras.ru/2009/files/SYRCoSE2009-CfP.pdf" target="_top">
- Binary Compatibility of Shared Libraries Implemented in C++
- on GNU/Linux Systems
-Index: libstdc++-v3/doc/html/manual/intro.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/intro.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/intro.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part I.  Introduction</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="index.html" title="The GNU C++ Library Manual" /><link rel="next" href="status.html" title="Chapter 1. Status" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part I. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part I.  Introduction</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="index.html" title="The GNU C++ Library Manual" /><link rel="next" href="status.html" title="Chapter 1. Status" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part I. 
- Introduction
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="index.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="status.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="manual.intro"></a>Part I. 
- Introduction
-- <a id="idp9040416" class="indexterm"></a>
--</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="chapter"><a href="status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="index.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="index.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="status.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library Manual </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 1. Status</td></tr></table></div></body></html>
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-+ <a id="idm270013458800" class="indexterm"></a>
-+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="chapter"><a href="status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="index.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="index.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="status.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library Manual </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 1. Status</td></tr></table></div></body></html>
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--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Extensions for Custom Containers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_design.html" title="Design" /><link rel="next" href="profile_mode_cost_model.html" title="Empirical Cost Model" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Extensions for Custom Containers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_cost_model.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.api"></a>Extensions for Custom Containers</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Extensions for Custom Containers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_design.html" title="Design" /><link rel="next" href="profile_mode_cost_model.html" title="Empirical Cost Model" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Extensions for Custom Containers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_cost_model.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.api"></a>Extensions for Custom Containers</h2></div></div></div><p>
- Many large projects use their own data structures instead of the ones in the
- standard library. If these data structures are similar in functionality
- to the standard library, they can be instrumented with the same hooks
-Index: libstdc++-v3/doc/html/manual/atomics.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/atomics.html (.../tags/gcc_4_8_2_release)
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--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 14.  Atomics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library, atomic" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="concurrency.html" title="Chapter 15.  Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 14. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 14.  Atomics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library, atomic" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="concurrency.html" title="Chapter 15.  Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 14. 
- Atomics
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io_and_c.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="concurrency.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.atomics"></a>Chapter 14. 
- Atomics
-- <a id="idp16390640" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="atomics.html#std.atomics.api">API Reference</a></span></dt></dl></div><p>
-+ <a id="idm269999140704" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="atomics.html#std.atomics.api">API Reference</a></span></dt></dl></div><p>
- Facilities for atomic operations.
- </p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.atomics.api"></a>API Reference</h2></div></div></div><p>
- All items are declared in the standard header
-Index: libstdc++-v3/doc/html/manual/internals.html
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---- a/src/libstdc++-v3/doc/html/manual/internals.html (.../tags/gcc_4_8_2_release)
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-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Porting to New Hardware or Operating Systems</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, internals" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="documentation_hacking.html" title="Writing and Generating Documentation" /><link rel="next" href="test.html" title="Test" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Porting to New Hardware or Operating Systems</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="documentation_hacking.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Porting to New Hardware or Operating Systems</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, internals" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="documentation_hacking.html" title="Writing and Generating Documentation" /><link rel="next" href="test.html" title="Test" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Porting to New Hardware or Operating Systems</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="documentation_hacking.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
- Porting and Maintenance
-
- </th><td width="20%" align="right"> <a accesskey="n" href="test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.internals"></a>Porting to New Hardware or Operating Systems</h2></div></div></div><p>
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-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/policy_data_structures_using.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures_using.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="next" href="policy_data_structures_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.prereq"></a>Prerequisites</h3></div></div></div><p>The library contains only header files, and does not require any
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="next" href="policy_data_structures_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.prereq"></a>Prerequisites</h3></div></div></div><p>The library contains only header files, and does not require any
- other libraries except the standard C++ library . All classes are
- defined in namespace <code class="code">__gnu_pbds</code>. The library internally
- uses macros beginning with <code class="code">PB_DS</code>, but
-@@ -61,7 +61,7 @@
- In addition, there are the following diagnostics classes,
- used to report errors specific to this library's data
- structures.
-- </p><div class="figure"><a id="idp17806128"></a><p class="title"><strong>Figure 22.7. Exception Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_exception_hierarchy.png" align="middle" alt="Exception Hierarchy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.tutorial"></a>Tutorial</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.using.tutorial.basic"></a>Basic Use</h4></div></div></div><p>
-+ </p><div class="figure"><a id="idm269997724688"></a><p class="title"><strong>Figure 22.7. Exception Hierarchy</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/pbds_exception_hierarchy.png" align="middle" alt="Exception Hierarchy" /></div></div></div><br class="figure-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.tutorial"></a>Tutorial</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.using.tutorial.basic"></a>Basic Use</h4></div></div></div><p>
- For the most part, the policy-based containers containers in
- namespace <code class="literal">__gnu_pbds</code> have the same interface as
- the equivalent containers in the standard C++ library, except for
-Index: libstdc++-v3/doc/html/manual/bugs.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/bugs.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/bugs.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Bugs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="license.html" title="License" /><link rel="next" href="setup.html" title="Chapter 2. Setup" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Bugs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="license.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="setup.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.bugs"></a>Bugs</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.status.bugs.impl"></a>Implementation Bugs</h3></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Bugs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="license.html" title="License" /><link rel="next" href="setup.html" title="Chapter 2. Setup" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Bugs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="license.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="setup.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.bugs"></a>Bugs</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.status.bugs.impl"></a>Implementation Bugs</h3></div></div></div><p>
- Information on known bugs, details on efforts to fix them, and
- fixed bugs are all available as part of the <a class="link" href="http://gcc.gnu.org/bugs/" target="_top">GCC bug tracking system</a>,
- with the category set to <code class="literal">libstdc++</code>.
-Index: libstdc++-v3/doc/html/manual/parallel_mode_using.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/parallel_mode_using.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/parallel_mode_using.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_semantics.html" title="Semantics" /><link rel="next" href="parallel_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.using.prereq_flags"></a>Prerequisite Compiler Flags</h3></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_semantics.html" title="Semantics" /><link rel="next" href="parallel_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.using.prereq_flags"></a>Prerequisite Compiler Flags</h3></div></div></div><p>
- Any use of parallel functionality requires additional compiler
- and runtime support, in particular support for OpenMP. Adding this support is
- not difficult: just compile your application with the compiler
-@@ -62,4 +62,4 @@
- flags for atomic operations.)
- </p><p> The following table provides the names and headers of all the
- parallel algorithms that can be used in a similar manner:
--</p><div class="table"><a id="idp16725920"></a><p class="title"><strong>Table 18.1. Parallel Algorithms</strong></p><div class="table-contents"><table summary="Parallel Algorithms" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Algorithm</th><th align="left">Header</th><th align="left">Parallel algorithm</th><th align="left">Parallel header</th></tr></thead><tbody><tr><td align="left"><code class="function">std::accumulate</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::accumulate</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_difference</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_difference</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::inner_product</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::inner_product</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::partial_sum</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::partial_sum</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::equal</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::equal</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_first_of</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_first_of</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::for_each</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::for_each</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::lexicographical_compare</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::lexicographical_compare</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::mismatch</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::mismatch</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::transform</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::transform</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::max_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::max_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::merge</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::merge</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::min_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::min_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::nth_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::nth_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partial_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partial_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partition</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partition</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::random_shuffle</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::random_shuffle</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_union</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_union</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_intersection</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_intersection</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_symmetric_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_symmetric_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::stable_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::stable_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::unique_copy</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::unique_copy</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="parallel_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>
-\ No newline at end of file
-+</p><div class="table"><a id="idm269998805216"></a><p class="title"><strong>Table 18.1. Parallel Algorithms</strong></p><div class="table-contents"><table summary="Parallel Algorithms" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Algorithm</th><th align="left">Header</th><th align="left">Parallel algorithm</th><th align="left">Parallel header</th></tr></thead><tbody><tr><td align="left"><code class="function">std::accumulate</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::accumulate</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_difference</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_difference</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::inner_product</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::inner_product</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::partial_sum</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::partial_sum</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::equal</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::equal</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find</code></td><td align="left"><code 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align="left"><code class="function">std::merge</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::merge</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::min_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::min_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::nth_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::nth_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partial_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partial_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partition</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partition</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::random_shuffle</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::random_shuffle</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_union</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_union</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_intersection</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_intersection</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_symmetric_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_symmetric_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::stable_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::stable_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::unique_copy</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::unique_copy</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" 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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 26. Numerics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_algorithms.html" title="Chapter 25. Algorithms" /><link rel="next" href="ext_iterators.html" title="Chapter 27. Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 26. Numerics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_algorithms.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="next" href="parallel_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.semantics"></a>Semantics</h2></div></div></div><p> The parallel mode STL algorithms are currently not exception-safe,
- i.e. user-defined functors must not throw exceptions.
- Also, the order of execution is not guaranteed for some functions, of course.
- Therefore, user-defined functors should not have any concurrent side effects.
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part II.  Standard Contents</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="debug.html" title="Debugging Support" /><link rel="next" href="support.html" title="Chapter 4.  Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part II. 
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- Utilities
-
--</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp13920976">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idp13924528">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp13937824">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15512272">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idp15534784">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idp15542080">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp15556704">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15573056">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idp15576640">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.
-+</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.
- Strings
-
- </a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="localization.html">8.
- Localization
-
--</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.
-+</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.
- Containers
-
- </a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.
-Index: libstdc++-v3/doc/html/manual/appendix.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/appendix.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/appendix.html (.../branches/gcc-4_8-branch)
-@@ -1,9 +1,9 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part IV.  Appendices</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="ext_concurrency_use.html" title="Use" /><link rel="next" href="appendix_contributing.html" title="Appendix A.  Contributing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part IV. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part IV.  Appendices</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="ext_concurrency_use.html" title="Use" /><link rel="next" href="appendix_contributing.html" title="Appendix A.  Contributing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part IV. 
- Appendices
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_use.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="appendix_contributing.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="appendix"></a>Part IV. 
- Appendices
--</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="appendix"><a href="appendix_contributing.html">A.
-+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="appendix"><a href="appendix_contributing.html">A.
- Contributing
-
- </a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#contrib.list">Contributor Checklist</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_contributing.html#list.reading">Reading</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.copyright">Assignment</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.getting">Getting Sources</a></span></dt><dt><span class="section"><a href="appendix_contributing.html#list.patches">Submitting Patches</a></span></dt></dl></dd><dt><span class="section"><a href="source_organization.html">Directory Layout and Source Conventions</a></span></dt><dt><span class="section"><a href="source_code_style.html">Coding Style</a></span></dt><dd><dl><dt><span class="section"><a href="source_code_style.html#coding_style.bad_identifiers">Bad Identifiers</a></span></dt><dt><span class="section"><a href="source_code_style.html#coding_style.example">By Example</a></span></dt></dl></dd><dt><span class="section"><a href="source_design_notes.html">Design Notes</a></span></dt></dl></dd><dt><span class="appendix"><a href="appendix_porting.html">B.
-Index: libstdc++-v3/doc/html/manual/memory.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/memory.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/memory.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="pairs.html" title="Pairs" /><link rel="next" href="traits.html" title="Traits" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="pairs.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="pairs.html" title="Pairs" /><link rel="next" href="traits.html" title="Traits" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="pairs.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
- Utilities
-
- </th><td width="20%" align="right"> <a accesskey="n" href="traits.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.memory"></a>Memory</h2></div></div></div><p>
-@@ -92,7 +92,7 @@
- or loading and unloading shared objects in memory. As such, using
- caching allocators on systems that do not support
- <code class="function">abi::__cxa_atexit</code> is not recommended.
-- </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp13920976"></a>Interface Design</h5></div></div></div><p>
-+ </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270001611968"></a>Interface Design</h5></div></div></div><p>
- The only allocator interface that
- is supported is the standard C++ interface. As such, all STL
- containers have been adjusted, and all external allocators have
-@@ -105,7 +105,7 @@
- </p><p>
- The base class that <code class="classname">allocator</code> is derived from
- may not be user-configurable.
--</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp13924528"></a>Selecting Default Allocation Policy</h5></div></div></div><p>
-+</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270001608416"></a>Selecting Default Allocation Policy</h5></div></div></div><p>
- It's difficult to pick an allocation strategy that will provide
- maximum utility, without excessively penalizing some behavior. In
- fact, it's difficult just deciding which typical actions to measure
-@@ -142,7 +142,7 @@
- The current default choice for
- <code class="classname">allocator</code> is
- <code class="classname">__gnu_cxx::new_allocator</code>.
-- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp13937824"></a>Disabling Memory Caching</h5></div></div></div><p>
-+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270001595120"></a>Disabling Memory Caching</h5></div></div></div><p>
- In use, <code class="classname">allocator</code> may allocate and
- deallocate using implementation-specific strategies and
- heuristics. Because of this, a given call to an allocator object's
-@@ -309,33 +309,33 @@
- of the used and unused memory locations. It has its own
- <a class="link" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator">chapter</a>
- in the documentation.
-- </p></li></ol></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp13992848"></a><p><span class="citetitle"><em class="citetitle">
-+ </p></li></ol></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="allocator.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm270000084224"></a><p><span class="citetitle"><em class="citetitle">
- ISO/IEC 14882:1998 Programming languages - C++
- </em>. </span>
- isoc++_1998
-- <span class="pagenums">20.4 Memory. </span></p></div><div class="biblioentry"><a id="idp13994688"></a><p><span class="title"><em>
-- <a class="link" href="http://www.drdobbs.com/cpp/184403759" target="_top">
-+ <span class="pagenums">20.4 Memory. </span></p></div><div class="biblioentry"><a id="idm270000082384"></a><p><span class="title"><em>
-+ <a class="link" href="http://www.drdobbs.com/the-standard-librarian-what-are-allocato/184403759" target="_top">
- The Standard Librarian: What Are Allocators Good For?
- </a>
- </em>. </span><span class="author"><span class="firstname">Matt</span> <span class="surname">Austern</span>. </span><span class="publisher"><span class="publishername">
- C/C++ Users Journal
-- . </span></span></p></div><div class="biblioentry"><a id="idp13998416"></a><p><span class="title"><em>
-+ . </span></span></p></div><div class="biblioentry"><a id="idm270000078608"></a><p><span class="title"><em>
- <a class="link" href="http://www.hoard.org/" target="_top">
- The Hoard Memory Allocator
- </a>
-- </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span></p></div><div class="biblioentry"><a id="idp14001184"></a><p><span class="title"><em>
-+ </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span></p></div><div class="biblioentry"><a id="idm270000075840"></a><p><span class="title"><em>
- <a class="link" href="http://people.cs.umass.edu/~emery/pubs/berger-oopsla2002.pdf" target="_top">
- Reconsidering Custom Memory Allocation
- </a>
-- </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span><span class="author"><span class="firstname">Ben</span> <span class="surname">Zorn</span>. </span><span class="author"><span class="firstname">Kathryn</span> <span class="surname">McKinley</span>. </span><span class="copyright">Copyright © 2002 OOPSLA. </span></p></div><div class="biblioentry"><a id="idp14007344"></a><p><span class="title"><em>
-+ </em>. </span><span class="author"><span class="firstname">Emery</span> <span class="surname">Berger</span>. </span><span class="author"><span class="firstname">Ben</span> <span class="surname">Zorn</span>. </span><span class="author"><span class="firstname">Kathryn</span> <span class="surname">McKinley</span>. </span><span class="copyright">Copyright © 2002 OOPSLA. </span></p></div><div class="biblioentry"><a id="idm270000069680"></a><p><span class="title"><em>
- <a class="link" href="http://www.angelikalanger.com/Articles/C++Report/Allocators/Allocators.html" target="_top">
- Allocator Types
- </a>
- </em>. </span><span class="author"><span class="firstname">Klaus</span> <span class="surname">Kreft</span>. </span><span class="author"><span class="firstname">Angelika</span> <span class="surname">Langer</span>. </span><span class="publisher"><span class="publishername">
- C/C++ Users Journal
-- . </span></span></p></div><div class="biblioentry"><a id="idp14012080"></a><p><span class="citetitle"><em class="citetitle">The C++ Programming Language</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 . </span><span class="pagenums">19.4 Allocators. </span><span class="publisher"><span class="publishername">
-+ . </span></span></p></div><div class="biblioentry"><a id="idm270000064944"></a><p><span class="citetitle"><em class="citetitle">The C++ Programming Language</em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 . </span><span class="pagenums">19.4 Allocators. </span><span class="publisher"><span class="publishername">
- Addison Wesley
-- . </span></span></p></div><div class="biblioentry"><a id="idp14016512"></a><p><span class="citetitle"><em class="citetitle">Yalloc: A Recycling C++ Allocator</em>. </span><span class="author"><span class="firstname">Felix</span> <span class="surname">Yen</span>. </span></p></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.util.memory.auto_ptr"></a>auto_ptr</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="auto_ptr.limitations"></a>Limitations</h4></div></div></div><p>Explaining all of the fun and delicious things that can
-+ . </span></span></p></div><div class="biblioentry"><a id="idm270000060512"></a><p><span class="citetitle"><em class="citetitle">Yalloc: A Recycling C++ Allocator</em>. </span><span class="author"><span class="firstname">Felix</span> <span class="surname">Yen</span>. </span></p></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.util.memory.auto_ptr"></a>auto_ptr</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="auto_ptr.limitations"></a>Limitations</h4></div></div></div><p>Explaining all of the fun and delicious things that can
- happen with misuse of the <code class="classname">auto_ptr</code> class
- template (called <acronym class="acronym">AP</acronym> here) would take some
- time. Suffice it to say that the use of <acronym class="acronym">AP</acronym>
-@@ -445,7 +445,7 @@
- Derived classes override those functions to destroy resources in a context
- where the correct dynamic type is known. This is an application of the
- technique known as type erasure.
-- </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15512272"></a>Class Hierarchy</h5></div></div></div><p>
-+ </p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm270000019344"></a>Class Hierarchy</h5></div></div></div><p>
- A <code class="classname">shared_ptr&lt;T&gt;</code> contains a pointer of
- type <span class="type">T*</span> and an object of type
- <code class="classname">__shared_count</code>. The shared_count contains a
-@@ -492,9 +492,9 @@
- aliasing constructor, make_shared &amp; allocate_shared. Additionally,
- the constructors taking <code class="classname">auto_ptr</code> parameters are
- deprecated in C++11 mode.
-- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15534784"></a>Thread Safety</h5></div></div></div><p>
-+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999996832"></a>Thread Safety</h5></div></div></div><p>
- The
--<a class="link" href="http://boost.org/libs/smart_ptr/shared_ptr.htm#ThreadSafety" target="_top">Thread
-+<a class="link" href="http://www.boost.org/libs/smart_ptr/shared_ptr.htm#ThreadSafety" target="_top">Thread
- Safety</a> section of the Boost shared_ptr documentation says "shared_ptr
- objects offer the same level of thread safety as built-in types."
- The implementation must ensure that concurrent updates to separate shared_ptr
-@@ -537,7 +537,7 @@
- shared_ptr in libstdc++ the compiler and library are fixed, which
- makes things much simpler: we have an atomic CAS or we don't, see Lock
- Policy below for details.
--</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15542080"></a>Selecting Lock Policy</h5></div></div></div><p>
-+</p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999989536"></a>Selecting Lock Policy</h5></div></div></div><p>
- </p><p>
- There is a single <code class="classname">_Sp_counted_base</code> class,
- which is a template parameterized on the enum
-@@ -578,7 +578,7 @@
- <code class="filename">ext/atomicity.h</code>, which detect if the program
- is multi-threaded. If only one thread of execution exists in
- the program then less expensive non-atomic operations are used.
-- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15556704"></a>Related functions and classes</h5></div></div></div><div class="variablelist"><dl class="variablelist"><dt><span class="term"><code class="code">dynamic_pointer_cast</code>, <code class="code">static_pointer_cast</code>,
-+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999974912"></a>Related functions and classes</h5></div></div></div><div class="variablelist"><dl class="variablelist"><dt><span class="term"><code class="code">dynamic_pointer_cast</code>, <code class="code">static_pointer_cast</code>,
- <code class="code">const_pointer_cast</code></span></dt><dd><p>
- As noted in N2351, these functions can be implemented non-intrusively using
- the alias constructor. However the aliasing constructor is only available
-@@ -611,13 +611,13 @@
- As well as the extra constructors, this implementation also needs some
- members of _Sp_counted_deleter to be protected where they could otherwise
- be private.
-- </p></dd></dl></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.using"></a>Use</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15573056"></a>Examples</h5></div></div></div><p>
-+ </p></dd></dl></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.using"></a>Use</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999958496"></a>Examples</h5></div></div></div><p>
- Examples of use can be found in the testsuite, under
- <code class="filename">testsuite/tr1/2_general_utilities/shared_ptr</code>,
- <code class="filename">testsuite/20_util/shared_ptr</code>
- and
- <code class="filename">testsuite/20_util/weak_ptr</code>.
-- </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15576640"></a>Unresolved Issues</h5></div></div></div><p>
-+ </p></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999954912"></a>Unresolved Issues</h5></div></div></div><p>
- The <span class="emphasis"><em><code class="classname">shared_ptr</code> atomic access</em></span>
- clause in the C++11 standard is not implemented in GCC.
- </p><p>
-@@ -658,25 +658,25 @@
- code to work with, Peter Dimov in particular for his help and
- invaluable advice on thread safety. Phillip Jordan and Paolo
- Carlini for the lock policy implementation.
-- </p></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15587936"></a><p><span class="title"><em>
-+ </p></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="shared_ptr.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999943680"></a><p><span class="title"><em>
- <a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2351.htm" target="_top">
- Improving shared_ptr for C++0x, Revision 2
- </a>
- </em>. </span><span class="subtitle">
- N2351
-- . </span></p></div><div class="biblioentry"><a id="idp15590224"></a><p><span class="title"><em>
-+ . </span></p></div><div class="biblioentry"><a id="idm269999941392"></a><p><span class="title"><em>
- <a class="link" href="http://open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2456.html" target="_top">
- C++ Standard Library Active Issues List
- </a>
- </em>. </span><span class="subtitle">
- N2456
-- . </span></p></div><div class="biblioentry"><a id="idp15592512"></a><p><span class="title"><em>
-+ . </span></p></div><div class="biblioentry"><a id="idm269999939104"></a><p><span class="title"><em>
- <a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2461.pdf" target="_top">
- Working Draft, Standard for Programming Language C++
- </a>
- </em>. </span><span class="subtitle">
- N2461
-- . </span></p></div><div class="biblioentry"><a id="idp15594816"></a><p><span class="title"><em>
-+ . </span></p></div><div class="biblioentry"><a id="idm269999936800"></a><p><span class="title"><em>
- <a class="link" href="http://boost.org/libs/smart_ptr/shared_ptr.htm" target="_top">
- Boost C++ Libraries documentation, shared_ptr
- </a>
-Index: libstdc++-v3/doc/html/manual/api.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/api.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/api.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>API Evolution and Deprecation History</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, api, evolution, deprecation, history" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="abi.html" title="ABI Policy and Guidelines" /><link rel="next" href="backwards.html" title="Backwards Compatibility" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">API Evolution and Deprecation History</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="abi.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>API Evolution and Deprecation History</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, api, evolution, deprecation, history" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="abi.html" title="ABI Policy and Guidelines" /><link rel="next" href="backwards.html" title="Backwards Compatibility" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">API Evolution and Deprecation History</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="abi.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
- Porting and Maintenance
-
- </th><td width="20%" align="right"> <a accesskey="n" href="backwards.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.api"></a>API Evolution and Deprecation History</h2></div></div></div><p>
-@@ -77,11 +77,11 @@
- <span class="type">__alloc</span> to select an underlying allocator that
- satisfied memory allocation requests. The selection of this
- underlying allocator was not user-configurable.
-- </p><div class="table"><a id="idp23030528"></a><p class="title"><strong>Table B.6. Extension Allocators</strong></p><div class="table-contents"><table summary="Extension Allocators" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Allocator (3.4)</th><th align="left">Header (3.4)</th><th align="left">Allocator (3.[0-3])</th><th align="left">Header (3.[0-3])</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::new_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="classname">std::__new_alloc</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::malloc_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="classname">std::__malloc_alloc_template&lt;int&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::debug_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="classname">std::debug_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__pool_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="classname">std::__default_alloc_template&lt;bool,int&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__mt_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left"><code class="classname">__gnu_cxx::bitmap_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><p> Releases after gcc-3.4 have continued to add to the collection
-+ </p><div class="table"><a id="idm269992502096"></a><p class="title"><strong>Table B.6. Extension Allocators</strong></p><div class="table-contents"><table summary="Extension Allocators" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Allocator (3.4)</th><th align="left">Header (3.4)</th><th align="left">Allocator (3.[0-3])</th><th align="left">Header (3.[0-3])</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::new_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="classname">std::__new_alloc</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::malloc_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="classname">std::__malloc_alloc_template&lt;int&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::debug_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="classname">std::debug_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__pool_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="classname">std::__default_alloc_template&lt;bool,int&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__mt_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left"><code class="classname">__gnu_cxx::bitmap_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><p> Releases after gcc-3.4 have continued to add to the collection
- of available allocators. All of these new allocators are
- standard-style. The following table includes details, along with
- the first released version of GCC that included the extension allocator.
-- </p><div class="table"><a id="idp23058160"></a><p class="title"><strong>Table B.7. Extension Allocators Continued</strong></p><div class="table-contents"><table summary="Extension Allocators Continued" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left">Allocator</th><th align="left">Include</th><th align="left">Version</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::array_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left">4.0.0</td></tr><tr><td align="left"><code class="classname">__gnu_cxx::throw_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left">4.2.0</td></tr></tbody></table></div></div><br class="table-break" /><p>
-+ </p><div class="table"><a id="idm269992474464"></a><p class="title"><strong>Table B.7. Extension Allocators Continued</strong></p><div class="table-contents"><table summary="Extension Allocators Continued" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left">Allocator</th><th align="left">Include</th><th align="left">Version</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::array_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left">4.0.0</td></tr><tr><td align="left"><code class="classname">__gnu_cxx::throw_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left">4.2.0</td></tr></tbody></table></div></div><br class="table-break" /><p>
- Debug mode first appears.
- </p><p>
- Precompiled header support <acronym class="acronym">PCH</acronym> support.
-Index: libstdc++-v3/doc/html/manual/source_organization.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/source_organization.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/source_organization.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Directory Layout and Source Conventions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="next" href="source_code_style.html" title="Coding Style" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Directory Layout and Source Conventions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_contributing.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Directory Layout and Source Conventions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="next" href="source_code_style.html" title="Coding Style" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Directory Layout and Source Conventions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_contributing.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
- Contributing
-
- </th><td width="20%" align="right"> <a accesskey="n" href="source_code_style.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.organization"></a>Directory Layout and Source Conventions</h2></div></div></div><p>
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>File Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="stringstreams.html" title="Memory Based Streams" /><link rel="next" href="io_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">File Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="stringstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
- Input and Output
-
- </th><td width="20%" align="right"> <a accesskey="n" href="io_and_c.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.filestreams"></a>File Based Streams</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.filestreams.copying_a_file"></a>Copying a File</h3></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/ext_demangling.html
-===================================================================
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 29. Demangling</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_io.html" title="Chapter 28. Input and Output" /><link rel="next" href="ext_concurrency.html" title="Chapter 30. Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 29. Demangling</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_io.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
- </th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.demangle"></a>Chapter 29. Demangling</h2></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/ext_preface.html
-===================================================================
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--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="extensions.html" title="Part III.  Extensions" /><link rel="next" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="extensions.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="extensions.html" title="Part III.  Extensions" /><link rel="next" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="extensions.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="ext_compile_checks.html">Next</a></td></tr></table><hr /></div><div class="preface"><div class="titlepage"><div><div><h1 class="title"><a id="idp16425920"></a></h1></div></div></div><p>
-+</th><td width="20%" align="right"> <a accesskey="n" href="ext_compile_checks.html">Next</a></td></tr></table><hr /></div><div class="preface"><div class="titlepage"><div><div><h1 class="title"><a id="idm269999105296"></a></h1></div></div></div><p>
- Here we will make an attempt at describing the non-Standard
- extensions to the library. Some of these are from older versions of
- standard library components, namely SGI's STL, and some of these are
-Index: libstdc++-v3/doc/html/manual/concept_checking.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/concept_checking.html (.../tags/gcc_4_8_2_release)
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concept Checking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="diagnostics.html" title="Chapter 5.  Diagnostics" /><link rel="prev" href="diagnostics.html" title="Chapter 5.  Diagnostics" /><link rel="next" href="utilities.html" title="Chapter 6.  Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concept Checking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="diagnostics.html">Prev</a> </td><th width="60%" align="center">Chapter 5. 
- Diagnostics
-
- </th><td width="20%" align="right"> <a accesskey="n" href="utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.concept_checking"></a>Concept Checking</h2></div></div></div><p>
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Multiple Thread Example</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_ex_single.html" title="Single Thread Example" /><link rel="next" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Multiple Thread Example</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_ex_single.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.example_multi"></a>Multiple Thread Example</h2></div></div></div><p>
- In the ST example we never used the thread_id variable present in each block.
- Let's start by explaining the purpose of this in a MT application.
- </p><p>
-Index: libstdc++-v3/doc/html/manual/ext_compile_checks.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/ext_compile_checks.html (.../tags/gcc_4_8_2_release)
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-@@ -1,5 +1,5 @@
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 16. Compile Time Checks</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_preface.html" title="" /><link rel="next" href="debug_mode.html" title="Chapter 17. Debug Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 16. Compile Time Checks</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_preface.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
- </th><td width="20%" align="right"> <a accesskey="n" href="debug_mode.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.compile_checks"></a>Chapter 16. Compile Time Checks</h2></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/strings.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/strings.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/strings.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
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-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 7.  Strings</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="traits.html" title="Traits" /><link rel="next" href="localization.html" title="Chapter 8.  Localization" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 7. 
- Strings
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="traits.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="localization.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.strings"></a>Chapter 7. 
- Strings
-- <a id="idp15603440" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.strings.string"></a>String Classes</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="strings.string.simple"></a>Simple Transformations</h3></div></div></div><p>
-+ <a id="idm269999928112" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.strings.string"></a>String Classes</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="strings.string.simple"></a>Simple Transformations</h3></div></div></div><p>
- Here are Standard, simple, and portable ways to perform common
- transformations on a <code class="code">string</code> instance, such as
- "convert to all upper case." The word transformations
-Index: libstdc++-v3/doc/html/manual/containers_and_c.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/containers_and_c.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/containers_and_c.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="unordered_associative.html" title="Unordered Associative" /><link rel="next" href="iterators.html" title="Chapter 10.  Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="unordered_associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="unordered_associative.html" title="Unordered Associative" /><link rel="next" href="iterators.html" title="Chapter 10.  Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="unordered_associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
- Containers
-
- </th><td width="20%" align="right"> <a accesskey="n" href="iterators.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.c.vs_array"></a>Containers vs. Arrays</h3></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_devel.html" title="Developer Information" /><link rel="next" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Diagnostics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_devel.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.diagnostics"></a>Diagnostics</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_devel.html" title="Developer Information" /><link rel="next" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Diagnostics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_devel.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.diagnostics"></a>Diagnostics</h2></div></div></div><p>
- The table below presents all the diagnostics we intend to implement.
- Each diagnostic has a corresponding compile time switch
- <code class="code">-D_GLIBCXX_PROFILE_&lt;diagnostic&gt;</code>.
-@@ -17,7 +17,7 @@
- A high accuracy means that the diagnostic is unlikely to be wrong.
- These grades are not perfect. They are just meant to guide users with
- specific needs or time budgets.
-- </p><div class="table"><a id="idp17088912"></a><p class="title"><strong>Table 19.2. Profile Diagnostics</strong></p><div class="table-contents"><table summary="Profile Diagnostics" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left">Group</th><th align="left">Flag</th><th align="left">Benefit</th><th align="left">Cost</th><th align="left">Freq.</th><th align="left">Implemented</th><td class="auto-generated"> </td></tr></thead><tbody><tr><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers" title="Containers">
-+ </p><div class="table"><a id="idm269998442544"></a><p class="title"><strong>Table 19.2. Profile Diagnostics</strong></p><div class="table-contents"><table summary="Profile Diagnostics" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left">Group</th><th align="left">Flag</th><th align="left">Benefit</th><th align="left">Cost</th><th align="left">Freq.</th><th align="left">Implemented</th><td class="auto-generated"> </td></tr></thead><tbody><tr><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers" title="Containers">
- CONTAINERS</a></td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small" title="Hashtable Too Small">
- HASHTABLE_TOO_SMALL</a></td><td align="left">10</td><td align="left">1</td><td align="left"> </td><td align="left">10</td><td align="left">yes</td></tr><tr><td align="left"> </td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large" title="Hashtable Too Large">
- HASHTABLE_TOO_LARGE</a></td><td align="left">5</td><td align="left">1</td><td align="left"> </td><td align="left">10</td><td align="left">yes</td></tr><tr><td align="left"> </td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash" title="Inefficient Hash">
-@@ -374,7 +374,7 @@
- Quick Sort for a particular call context.
- </p></li><li class="listitem"><p><span class="emphasis"><em>Fundamentals:</em></span>
- See papers:
-- <a class="link" href="http://portal.acm.org/citation.cfm?doid=1065944.1065981" target="_top">
-+ <a class="link" href="https://dl.acm.org/citation.cfm?doid=1065944.1065981" target="_top">
- A framework for adaptive algorithm selection in STAPL</a> and
- <a class="link" href="http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4228227" target="_top">
- Optimizing Sorting with Machine Learning Algorithms</a>.
-@@ -500,7 +500,7 @@
- Keep a shadow for each container. Record iterator dereferences and
- container member accesses. Issue advice for elements referenced by
- multiple threads.
-- See paper: <a class="link" href="http://portal.acm.org/citation.cfm?id=207110.207148" target="_top">
-+ See paper: <a class="link" href="https://dl.acm.org/citation.cfm?id=207110.207148" target="_top">
- The LRPD test: speculative run-time parallelization of loops with
- privatization and reduction parallelization</a>.
- </p></li><li class="listitem"><p><span class="emphasis"><em>Cost model:</em></span>
-Index: libstdc++-v3/doc/html/manual/ext_concurrency_impl.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="next" href="ext_concurrency_use.html" title="Use" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_use.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.impl.atomic_fallbacks"></a>Using Builtin Atomic Functions</h3></div></div></div><p>The functions for atomic operations described above are either
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="next" href="ext_concurrency_use.html" title="Use" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_use.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.impl.atomic_fallbacks"></a>Using Builtin Atomic Functions</h3></div></div></div><p>The functions for atomic operations described above are either
- implemented via compiler intrinsics (if the underlying host is
- capable) or by library fallbacks.</p><p>Compiler intrinsics (builtins) are always preferred. However, as
- the compiler builtins for atomics are not universally implemented,
-Index: libstdc++-v3/doc/html/manual/io_and_c.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/io_and_c.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/io_and_c.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="fstreams.html" title="File Based Streams" /><link rel="next" href="atomics.html" title="Chapter 14.  Atomics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="fstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="fstreams.html" title="File Based Streams" /><link rel="next" href="atomics.html" title="Chapter 14.  Atomics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="fstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
- Input and Output
-
- </th><td width="20%" align="right"> <a accesskey="n" href="atomics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.c.FILE"></a>Using FILE* and file descriptors</h3></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/documentation_hacking.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/documentation_hacking.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/documentation_hacking.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Writing and Generating Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, documentation, style, docbook, doxygen" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="next" href="internals.html" title="Porting to New Hardware or Operating Systems" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Writing and Generating Documentation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_porting.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Writing and Generating Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, documentation, style, docbook, doxygen" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="next" href="internals.html" title="Porting to New Hardware or Operating Systems" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Writing and Generating Documentation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_porting.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
- Porting and Maintenance
-
- </th><td width="20%" align="right"> <a accesskey="n" href="internals.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.doc"></a>Writing and Generating Documentation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.intro"></a>Introduction</h3></div></div></div><p>
-@@ -112,7 +112,7 @@
- supported, and are always aliased to dummy rules. These
- unsupported formats are: <span class="emphasis"><em>info</em></span>,
- <span class="emphasis"><em>ps</em></span>, and <span class="emphasis"><em>dvi</em></span>.
-- </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.doxygen"></a>Doxygen</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="doxygen.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idp22162432"></a><p class="title"><strong>Table B.1. Doxygen Prerequisites</strong></p><div class="table-contents"><table summary="Doxygen Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">coreutils</td><td align="center">8.5</td><td align="center">all</td></tr><tr><td align="center">bash</td><td align="center">4.1</td><td align="center">all</td></tr><tr><td align="center">doxygen</td><td align="center">1.7.6.1</td><td align="center">all</td></tr><tr><td align="center">graphviz</td><td align="center">2.26</td><td align="center">graphical hierarchies</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr></tbody></table></div></div><br class="table-break" /><p>
-+ </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.doxygen"></a>Doxygen</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="doxygen.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idm269993370272"></a><p class="title"><strong>Table B.1. Doxygen Prerequisites</strong></p><div class="table-contents"><table summary="Doxygen Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">coreutils</td><td align="center">8.5</td><td align="center">all</td></tr><tr><td align="center">bash</td><td align="center">4.1</td><td align="center">all</td></tr><tr><td align="center">doxygen</td><td align="center">1.7.6.1</td><td align="center">all</td></tr><tr><td align="center">graphviz</td><td align="center">2.26</td><td align="center">graphical hierarchies</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr></tbody></table></div></div><br class="table-break" /><p>
- Prerequisite tools are Bash 2.0 or later,
- <a class="link" href="http://www.doxygen.org/" target="_top">Doxygen</a>, and
- the <a class="link" href="http://www.gnu.org/software/coreutils/" target="_top">GNU
-@@ -232,9 +232,8 @@
- member functions.
- </p><p>
- Some commentary to accompany
-- the first list in the <a class="link" href="http://www.stack.nl/~dimitri/doxygen/docblocks.html" target="_top">Special
-- Documentation Blocks</a> section of
-- the Doxygen manual:
-+ the first list in the <a class="link" href="http://www.stack.nl/~dimitri/doxygen/manual/docblocks.html" target="_top">Special
-+ Documentation Blocks</a> section of the Doxygen manual:
- </p><div class="orderedlist"><ol class="orderedlist" type="1"><li class="listitem"><p>For longer comments, use the Javadoc style...</p></li><li class="listitem"><p>
- ...not the Qt style. The intermediate *'s are preferred.
- </p></li><li class="listitem"><p>
-@@ -310,7 +309,7 @@
- writing Doxygen comments. Single and double quotes, and
- separators in filenames are two common trouble spots. When in
- doubt, consult the following table.
-- </p><div class="table"><a id="idp22238096"></a><p class="title"><strong>Table B.2. HTML to Doxygen Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Doxygen Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Doxygen</th></tr></thead><tbody><tr><td align="left">\</td><td align="left">\\</td></tr><tr><td align="left">"</td><td align="left">\"</td></tr><tr><td align="left">'</td><td align="left">\'</td></tr><tr><td align="left">&lt;i&gt;</td><td align="left">@a word</td></tr><tr><td align="left">&lt;b&gt;</td><td align="left">@b word</td></tr><tr><td align="left">&lt;code&gt;</td><td align="left">@c word</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">@a word</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">&lt;em&gt;two words or more&lt;/em&gt;</td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.docbook"></a>Docbook</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="docbook.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idp22257536"></a><p class="title"><strong>Table B.3. Docbook Prerequisites</strong></p><div class="table-contents"><table summary="Docbook Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">docbook5-style-xsl</td><td align="center">1.76.1</td><td align="center">all</td></tr><tr><td align="center">xsltproc</td><td align="center">1.1.26</td><td align="center">all</td></tr><tr><td align="center">xmllint</td><td align="center">2.7.7</td><td align="center">validation</td></tr><tr><td align="center">dblatex</td><td align="center">0.3</td><td align="center">pdf output</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr><tr><td align="center">docbook2X</td><td align="center">0.8.8</td><td align="center">info output</td></tr><tr><td align="center">epub3 stylesheets</td><td align="center">b3</td><td align="center">epub output</td></tr></tbody></table></div></div><br class="table-break" /><p>
-+ </p><div class="table"><a id="idm269993294592"></a><p class="title"><strong>Table B.2. HTML to Doxygen Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Doxygen Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Doxygen</th></tr></thead><tbody><tr><td align="left">\</td><td align="left">\\</td></tr><tr><td align="left">"</td><td align="left">\"</td></tr><tr><td align="left">'</td><td align="left">\'</td></tr><tr><td align="left">&lt;i&gt;</td><td align="left">@a word</td></tr><tr><td align="left">&lt;b&gt;</td><td align="left">@b word</td></tr><tr><td align="left">&lt;code&gt;</td><td align="left">@c word</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">@a word</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">&lt;em&gt;two words or more&lt;/em&gt;</td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.docbook"></a>Docbook</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="docbook.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="idm269993275152"></a><p class="title"><strong>Table B.3. Docbook Prerequisites</strong></p><div class="table-contents"><table summary="Docbook Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">docbook5-style-xsl</td><td align="center">1.76.1</td><td align="center">all</td></tr><tr><td align="center">xsltproc</td><td align="center">1.1.26</td><td align="center">all</td></tr><tr><td align="center">xmllint</td><td align="center">2.7.7</td><td align="center">validation</td></tr><tr><td align="center">dblatex</td><td align="center">0.3</td><td align="center">pdf output</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr><tr><td align="center">docbook2X</td><td align="center">0.8.8</td><td align="center">info output</td></tr><tr><td align="center">epub3 stylesheets</td><td align="center">b3</td><td align="center">epub output</td></tr></tbody></table></div></div><br class="table-break" /><p>
- Editing the DocBook sources requires an XML editor. Many
- exist: some notable options
- include <span class="command"><strong>emacs</strong></span>, <span class="application">Kate</span>,
-@@ -520,11 +519,11 @@
- <a class="link" href="http://www.docbook.org/tdg/en/html/part2.html" target="_top">online</a>.
- An incomplete reference for HTML to Docbook conversion is
- detailed in the table below.
-- </p><div class="table"><a id="idp22335040"></a><p class="title"><strong>Table B.4. HTML to Docbook XML Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Docbook XML Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Docbook</th></tr></thead><tbody><tr><td align="left">&lt;p&gt;</td><td align="left">&lt;para&gt;</td></tr><tr><td align="left">&lt;pre&gt;</td><td align="left">&lt;computeroutput&gt;, &lt;programlisting&gt;,
-+ </p><div class="table"><a id="idm269993197520"></a><p class="title"><strong>Table B.4. HTML to Docbook XML Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Docbook XML Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Docbook</th></tr></thead><tbody><tr><td align="left">&lt;p&gt;</td><td align="left">&lt;para&gt;</td></tr><tr><td align="left">&lt;pre&gt;</td><td align="left">&lt;computeroutput&gt;, &lt;programlisting&gt;,
- &lt;literallayout&gt;</td></tr><tr><td align="left">&lt;ul&gt;</td><td align="left">&lt;itemizedlist&gt;</td></tr><tr><td align="left">&lt;ol&gt;</td><td align="left">&lt;orderedlist&gt;</td></tr><tr><td align="left">&lt;il&gt;</td><td align="left">&lt;listitem&gt;</td></tr><tr><td align="left">&lt;dl&gt;</td><td align="left">&lt;variablelist&gt;</td></tr><tr><td align="left">&lt;dt&gt;</td><td align="left">&lt;term&gt;</td></tr><tr><td align="left">&lt;dd&gt;</td><td align="left">&lt;listitem&gt;</td></tr><tr><td align="left">&lt;a href=""&gt;</td><td align="left">&lt;ulink url=""&gt;</td></tr><tr><td align="left">&lt;code&gt;</td><td align="left">&lt;literal&gt;, &lt;programlisting&gt;</td></tr><tr><td align="left">&lt;strong&gt;</td><td align="left">&lt;emphasis&gt;</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">&lt;emphasis&gt;</td></tr><tr><td align="left">"</td><td align="left">&lt;quote&gt;</td></tr></tbody></table></div></div><br class="table-break" /><p>
- And examples of detailed markup for which there are no real HTML
- equivalents are listed in the table below.
--</p><div class="table"><a id="idp22359184"></a><p class="title"><strong>Table B.5. Docbook XML Element Use</strong></p><div class="table-contents"><table summary="Docbook XML Element Use" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Element</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left">&lt;structname&gt;</td><td align="left">&lt;structname&gt;char_traits&lt;/structname&gt;</td></tr><tr><td align="left">&lt;classname&gt;</td><td align="left">&lt;classname&gt;string&lt;/classname&gt;</td></tr><tr><td align="left">&lt;function&gt;</td><td align="left">
-+</p><div class="table"><a id="idm269993173376"></a><p class="title"><strong>Table B.5. Docbook XML Element Use</strong></p><div class="table-contents"><table summary="Docbook XML Element Use" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Element</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left">&lt;structname&gt;</td><td align="left">&lt;structname&gt;char_traits&lt;/structname&gt;</td></tr><tr><td align="left">&lt;classname&gt;</td><td align="left">&lt;classname&gt;string&lt;/classname&gt;</td></tr><tr><td align="left">&lt;function&gt;</td><td align="left">
- <p>&lt;function&gt;clear()&lt;/function&gt;</p>
- <p>&lt;function&gt;fs.clear()&lt;/function&gt;</p>
- </td></tr><tr><td align="left">&lt;type&gt;</td><td align="left">&lt;type&gt;long long&lt;/type&gt;</td></tr><tr><td align="left">&lt;varname&gt;</td><td align="left">&lt;varname&gt;fs&lt;/varname&gt;</td></tr><tr><td align="left">&lt;literal&gt;</td><td align="left">
-Index: libstdc++-v3/doc/html/manual/extensions.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/extensions.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/extensions.html (.../branches/gcc-4_8-branch)
-@@ -1,11 +1,11 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part III.  Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="ext_preface.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part III.  Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="ext_preface.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part III. 
- Extensions
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io_and_c.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="ext_preface.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="manual.ext"></a>Part III. 
- Extensions
-- <a id="idp16423680" class="indexterm"></a>
--</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="preface"><a href="ext_preface.html"></a></span></dt><dt><span class="chapter"><a href="ext_compile_checks.html">16. Compile Time Checks</a></span></dt><dt><span class="chapter"><a href="debug_mode.html">17. Debug Mode</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and
-+ <a id="idm269999107536" class="indexterm"></a>
-+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="preface"><a href="ext_preface.html"></a></span></dt><dt><span class="chapter"><a href="ext_compile_checks.html">16. Compile Time Checks</a></span></dt><dt><span class="chapter"><a href="debug_mode.html">17. Debug Mode</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and
- debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.alt">Alternatives for Coexistence</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.other">Other Implementations</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="parallel_mode.html">18. Parallel Mode</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></dd><dt><span class="chapter"><a href="profile_mode.html">19. Profile Mode</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></dd><dt><span class="chapter"><a href="mt_allocator.html">20. The mt_allocator</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator.html#allocator.mt.intro">Intro</a></span></dt><dt><span class="section"><a href="mt_allocator_design.html">Design Issues</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_design.html#allocator.mt.overview">Overview</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.tune">Tunable Parameters</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.init">Initialization</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.deallocation">Deallocation Notes</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_ex_single.html">Single Thread Example</a></span></dt><dt><span class="section"><a href="mt_allocator_ex_multi.html">Multiple Thread Example</a></span></dt></dl></dd><dt><span class="chapter"><a href="bitmap_allocator.html">21. The bitmap_allocator</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator.html#allocator.bitmap.design">Design</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.free_list_store">Free List Store</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block">Super Block</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block_data">Super Block Data Layout</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.max_wasted">Maximum Wasted Percentage</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.allocate"><code class="function">allocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.deallocate"><code class="function">deallocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.questions">Questions</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.1">1</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.2">2</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.3">3</a></span></dt></dl></dd><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.locality">Locality</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.grow_policy">Overhead and Grow Policy</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="policy_data_structures.html">22. Policy-Based Data Structures</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">
- Configuring via Template Parameters
- </a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.traits">
-Index: libstdc++-v3/doc/html/manual/debug_mode_using.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/debug_mode_using.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/debug_mode_using.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_semantics.html" title="Semantics" /><link rel="next" href="debug_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.using"></a>Using</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_semantics.html" title="Semantics" /><link rel="next" href="debug_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.using"></a>Using</h2></div></div></div><p>
- </p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="debug_mode.using.mode"></a>Using the Debug Mode</h3></div></div></div><p>To use the libstdc++ debug mode, compile your application with the
- compiler flag <code class="code">-D_GLIBCXX_DEBUG</code>. Note that this flag
- changes the sizes and behavior of standard class templates such
-@@ -18,6 +18,6 @@
- mode or with debug mode. The
- following table provides the names and headers of the debugging
- containers:
--</p><div class="table"><a id="idp16490400"></a><p class="title"><strong>Table 17.1. Debugging Containers</strong></p><div class="table-contents"><table summary="Debugging Containers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::bitset</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="classname">__gnu_debug::bitset</code></td><td align="left"><code class="filename">&lt;debug/bitset&gt;</code></td></tr><tr><td align="left"><code class="classname">std::deque</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="classname">__gnu_debug::deque</code></td><td align="left"><code class="filename">&lt;debug/deque&gt;</code></td></tr><tr><td align="left"><code class="classname">std::list</code></td><td align="left"><code class="filename">list</code></td><td align="left"><code class="classname">__gnu_debug::list</code></td><td align="left"><code class="filename">&lt;debug/list&gt;</code></td></tr><tr><td align="left"><code class="classname">std::map</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::map</code></td><td align="left"><code class="filename">&lt;debug/map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::multimap</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::multimap</code></td><td align="left"><code class="filename">&lt;debug/map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::multiset</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::multiset</code></td><td align="left"><code class="filename">&lt;debug/set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::set</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::set</code></td><td align="left"><code class="filename">&lt;debug/set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::string</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::wstring</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::wstring</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::basic_string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::basic_string</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::vector</code></td><td align="left"><code class="filename">vector</code></td><td align="left"><code class="classname">__gnu_debug::vector</code></td><td align="left"><code class="filename">&lt;debug/vector&gt;</code></td></tr></tbody></table></div></div><br class="table-break" /><p>In addition, when compiling in C++11 mode, these additional
-+</p><div class="table"><a id="idm269999040896"></a><p class="title"><strong>Table 17.1. Debugging Containers</strong></p><div class="table-contents"><table summary="Debugging Containers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::bitset</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="classname">__gnu_debug::bitset</code></td><td align="left"><code class="filename">&lt;debug/bitset&gt;</code></td></tr><tr><td align="left"><code class="classname">std::deque</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="classname">__gnu_debug::deque</code></td><td align="left"><code class="filename">&lt;debug/deque&gt;</code></td></tr><tr><td align="left"><code class="classname">std::list</code></td><td align="left"><code class="filename">list</code></td><td align="left"><code class="classname">__gnu_debug::list</code></td><td align="left"><code class="filename">&lt;debug/list&gt;</code></td></tr><tr><td align="left"><code class="classname">std::map</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::map</code></td><td align="left"><code class="filename">&lt;debug/map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::multimap</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::multimap</code></td><td align="left"><code class="filename">&lt;debug/map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::multiset</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::multiset</code></td><td align="left"><code class="filename">&lt;debug/set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::set</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::set</code></td><td align="left"><code class="filename">&lt;debug/set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::string</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::wstring</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::wstring</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::basic_string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::basic_string</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::vector</code></td><td align="left"><code class="filename">vector</code></td><td align="left"><code class="classname">__gnu_debug::vector</code></td><td align="left"><code class="filename">&lt;debug/vector&gt;</code></td></tr></tbody></table></div></div><br class="table-break" /><p>In addition, when compiling in C++11 mode, these additional
- containers have additional debug capability.
--</p><div class="table"><a id="idp16535296"></a><p class="title"><strong>Table 17.2. Debugging Containers C++11</strong></p><div class="table-contents"><table summary="Debugging Containers C++11" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::unordered_map</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_map</code></td><td align="left"><code class="filename">&lt;debug/unordered_map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_multimap</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multimap</code></td><td align="left"><code class="filename">&lt;debug/unordered_map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_set</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_set</code></td><td align="left"><code class="filename">&lt;debug/unordered_set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_multiset</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multiset</code></td><td align="left"><code class="filename">&lt;debug/unordered_set&gt;</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="debug_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>
-\ No newline at end of file
-+</p><div class="table"><a id="idm269998996000"></a><p class="title"><strong>Table 17.2. Debugging Containers C++11</strong></p><div class="table-contents"><table summary="Debugging Containers C++11" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::unordered_map</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_map</code></td><td align="left"><code class="filename">&lt;debug/unordered_map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_multimap</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multimap</code></td><td align="left"><code class="filename">&lt;debug/unordered_map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_set</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_set</code></td><td align="left"><code class="filename">&lt;debug/unordered_set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_multiset</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multiset</code></td><td align="left"><code class="filename">&lt;debug/unordered_set&gt;</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="debug_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>
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-Index: libstdc++-v3/doc/html/manual/parallel_mode.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/parallel_mode.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/parallel_mode.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 18. Parallel Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="debug_mode_design.html" title="Design" /><link rel="next" href="parallel_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 18. Parallel Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_design.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 18. Parallel Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="debug_mode_design.html" title="Design" /><link rel="next" href="parallel_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 18. Parallel Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_design.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.parallel_mode"></a>Chapter 18. Parallel Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></div><p> The libstdc++ parallel mode is an experimental parallel
-+</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.parallel_mode"></a>Chapter 18. Parallel Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></div><p> The libstdc++ parallel mode is an experimental parallel
- implementation of many algorithms the C++ Standard Library.
- </p><p>
- Several of the standard algorithms, for instance
-@@ -12,11 +12,11 @@
- specific compiler flag.
- </p><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.intro"></a>Intro</h2></div></div></div><p>The following library components in the include
- <code class="filename">numeric</code> are included in the parallel mode:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><code class="function">std::accumulate</code></p></li><li class="listitem"><p><code class="function">std::adjacent_difference</code></p></li><li class="listitem"><p><code class="function">std::inner_product</code></p></li><li class="listitem"><p><code class="function">std::partial_sum</code></p></li></ul></div><p>The following library components in the include
--<code class="filename">algorithm</code> are included in the parallel mode:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><code class="function">std::adjacent_find</code></p></li><li class="listitem"><p><code class="function">std::count</code></p></li><li class="listitem"><p><code class="function">std::count_if</code></p></li><li class="listitem"><p><code class="function">std::equal</code></p></li><li class="listitem"><p><code class="function">std::find</code></p></li><li class="listitem"><p><code class="function">std::find_if</code></p></li><li class="listitem"><p><code class="function">std::find_first_of</code></p></li><li class="listitem"><p><code class="function">std::for_each</code></p></li><li class="listitem"><p><code class="function">std::generate</code></p></li><li class="listitem"><p><code class="function">std::generate_n</code></p></li><li class="listitem"><p><code class="function">std::lexicographical_compare</code></p></li><li class="listitem"><p><code class="function">std::mismatch</code></p></li><li class="listitem"><p><code class="function">std::search</code></p></li><li class="listitem"><p><code class="function">std::search_n</code></p></li><li class="listitem"><p><code class="function">std::transform</code></p></li><li class="listitem"><p><code class="function">std::replace</code></p></li><li class="listitem"><p><code class="function">std::replace_if</code></p></li><li class="listitem"><p><code class="function">std::max_element</code></p></li><li class="listitem"><p><code class="function">std::merge</code></p></li><li class="listitem"><p><code class="function">std::min_element</code></p></li><li class="listitem"><p><code class="function">std::nth_element</code></p></li><li class="listitem"><p><code class="function">std::partial_sort</code></p></li><li class="listitem"><p><code class="function">std::partition</code></p></li><li class="listitem"><p><code class="function">std::random_shuffle</code></p></li><li class="listitem"><p><code class="function">std::set_union</code></p></li><li class="listitem"><p><code class="function">std::set_intersection</code></p></li><li class="listitem"><p><code class="function">std::set_symmetric_difference</code></p></li><li class="listitem"><p><code class="function">std::set_difference</code></p></li><li class="listitem"><p><code class="function">std::sort</code></p></li><li class="listitem"><p><code class="function">std::stable_sort</code></p></li><li class="listitem"><p><code class="function">std::unique_copy</code></p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="parallel_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idp16926864"></a><p><span class="citetitle"><em class="citetitle">
-+<code class="filename">algorithm</code> are included in the parallel mode:</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p><code class="function">std::adjacent_find</code></p></li><li class="listitem"><p><code class="function">std::count</code></p></li><li class="listitem"><p><code class="function">std::count_if</code></p></li><li class="listitem"><p><code class="function">std::equal</code></p></li><li class="listitem"><p><code class="function">std::find</code></p></li><li class="listitem"><p><code class="function">std::find_if</code></p></li><li class="listitem"><p><code class="function">std::find_first_of</code></p></li><li class="listitem"><p><code class="function">std::for_each</code></p></li><li class="listitem"><p><code class="function">std::generate</code></p></li><li class="listitem"><p><code class="function">std::generate_n</code></p></li><li class="listitem"><p><code class="function">std::lexicographical_compare</code></p></li><li class="listitem"><p><code class="function">std::mismatch</code></p></li><li class="listitem"><p><code class="function">std::search</code></p></li><li class="listitem"><p><code class="function">std::search_n</code></p></li><li class="listitem"><p><code class="function">std::transform</code></p></li><li class="listitem"><p><code class="function">std::replace</code></p></li><li class="listitem"><p><code class="function">std::replace_if</code></p></li><li class="listitem"><p><code class="function">std::max_element</code></p></li><li class="listitem"><p><code class="function">std::merge</code></p></li><li class="listitem"><p><code class="function">std::min_element</code></p></li><li class="listitem"><p><code class="function">std::nth_element</code></p></li><li class="listitem"><p><code class="function">std::partial_sort</code></p></li><li class="listitem"><p><code class="function">std::partition</code></p></li><li class="listitem"><p><code class="function">std::random_shuffle</code></p></li><li class="listitem"><p><code class="function">std::set_union</code></p></li><li class="listitem"><p><code class="function">std::set_intersection</code></p></li><li class="listitem"><p><code class="function">std::set_symmetric_difference</code></p></li><li class="listitem"><p><code class="function">std::set_difference</code></p></li><li class="listitem"><p><code class="function">std::sort</code></p></li><li class="listitem"><p><code class="function">std::stable_sort</code></p></li><li class="listitem"><p><code class="function">std::unique_copy</code></p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h2 class="title"><a id="parallel_mode.biblio"></a>Bibliography</h2></div></div></div><div class="biblioentry"><a id="idm269998604464"></a><p><span class="citetitle"><em class="citetitle">
- Parallelization of Bulk Operations for STL Dictionaries
- </em>. </span><span class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span>. </span><span class="author"><span class="firstname">Leonor</span> <span class="surname">Frias</span>. </span><span class="copyright">Copyright © 2007 . </span><span class="publisher"><span class="publishername">
- Workshop on Highly Parallel Processing on a Chip (HPPC) 2007. (LNCS)
-- . </span></span></p></div><div class="biblioentry"><a id="idp16931936"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></span></p></div><div class="biblioentry"><a id="idm269998599392"></a><p><span class="citetitle"><em class="citetitle">
- The Multi-Core Standard Template Library
- </em>. </span><span class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span>. </span><span class="author"><span class="firstname">Peter</span> <span class="surname">Sanders</span>. </span><span class="author"><span class="firstname">Felix</span> <span class="surname">Putze</span>. </span><span class="copyright">Copyright © 2007 . </span><span class="publisher"><span class="publishername">
- Euro-Par 2007: Parallel Processing. (LNCS 4641)
-Index: libstdc++-v3/doc/html/manual/debug_mode_semantics.html
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---- a/src/libstdc++-v3/doc/html/manual/debug_mode_semantics.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/debug_mode_semantics.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="next" href="debug_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.semantics"></a>Semantics</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="next" href="debug_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.semantics"></a>Semantics</h2></div></div></div><p>
- </p><p>A program that uses the C++ standard library correctly
- will maintain the same semantics under debug mode as it had with
- the normal (release) library. All functional and exception-handling
-Index: libstdc++-v3/doc/html/manual/setup.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/setup.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/setup.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 2. Setup</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="bugs.html" title="Bugs" /><link rel="next" href="configure.html" title="Configure" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 2. Setup</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bugs.html">Prev</a> </td><th width="60%" align="center">Part I. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 2. Setup</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="bugs.html" title="Bugs" /><link rel="next" href="configure.html" title="Configure" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 2. Setup</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bugs.html">Prev</a> </td><th width="60%" align="center">Part I. 
- Introduction
-
--</th><td width="20%" align="right"> <a accesskey="n" href="configure.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.setup"></a>Chapter 2. Setup</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></div><p>To transform libstdc++ sources into installed include files
-+</th><td width="20%" align="right"> <a accesskey="n" href="configure.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.setup"></a>Chapter 2. Setup</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></div><p>To transform libstdc++ sources into installed include files
- and properly built binaries useful for linking to other software is
- a multi-step process. Steps include getting the sources,
- configuring and building the sources, testing, and installation.
-Index: libstdc++-v3/doc/html/manual/backwards.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/backwards.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/backwards.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Backwards Compatibility</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, backwards" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="api.html" title="API Evolution and Deprecation History" /><link rel="next" href="appendix_free.html" title="Appendix C.  Free Software Needs Free Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Backwards Compatibility</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Backwards Compatibility</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, backwards" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="api.html" title="API Evolution and Deprecation History" /><link rel="next" href="appendix_free.html" title="Appendix C.  Free Software Needs Free Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Backwards Compatibility</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
- Porting and Maintenance
-
- </th><td width="20%" align="right"> <a accesskey="n" href="appendix_free.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.appendix.porting.backwards"></a>Backwards Compatibility</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.first"></a>First</h3></div></div></div><p>The first generation GNU C++ library was called libg++. It was a
-@@ -940,15 +940,15 @@
- This is a change in behavior from older versions. Now, most
- <span class="type">iterator_type</span> typedefs in container classes are POD
- objects, not <span class="type">value_type</span> pointers.
--</p></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idp23415104"></a><p><span class="title"><em>
-+</p></div></div><div class="bibliography"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.biblio"></a>Bibliography</h3></div></div></div><div class="biblioentry"><a id="idm269992117648"></a><p><span class="title"><em>
- <a class="link" href="http://www.kegel.com/gcc/gcc4.html" target="_top">
- Migrating to GCC 4.1
- </a>
-- </em>. </span><span class="author"><span class="firstname">Dan</span> <span class="surname">Kegel</span>. </span></p></div><div class="biblioentry"><a id="idp23417888"></a><p><span class="title"><em>
-+ </em>. </span><span class="author"><span class="firstname">Dan</span> <span class="surname">Kegel</span>. </span></p></div><div class="biblioentry"><a id="idm269992114864"></a><p><span class="title"><em>
- <a class="link" href="http://lists.debian.org/debian-gcc/2006/03/msg00405.html" target="_top">
- Building the Whole Debian Archive with GCC 4.1: A Summary
- </a>
-- </em>. </span><span class="author"><span class="firstname">Martin</span> <span class="surname">Michlmayr</span>. </span></p></div><div class="biblioentry"><a id="idp23420736"></a><p><span class="title"><em>
-+ </em>. </span><span class="author"><span class="firstname">Martin</span> <span class="surname">Michlmayr</span>. </span></p></div><div class="biblioentry"><a id="idm269992112016"></a><p><span class="title"><em>
- <a class="link" href="http://annwm.lbl.gov/~leggett/Atlas/gcc-3.2.html" target="_top">
- Migration guide for GCC-3.2
- </a>
-Index: libstdc++-v3/doc/html/manual/source_design_notes.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/source_design_notes.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/source_design_notes.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Notes</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="source_code_style.html" title="Coding Style" /><link rel="next" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Notes</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_code_style.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Notes</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="source_code_style.html" title="Coding Style" /><link rel="next" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Notes</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_code_style.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
- Contributing
-
- </th><td width="20%" align="right"> <a accesskey="n" href="appendix_porting.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.design_notes"></a>Design Notes</h2></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/ext_sgi.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/ext_sgi.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/ext_sgi.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Deprecated</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="prev" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="next" href="ext_utilities.html" title="Chapter 24. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Deprecated</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_containers.html">Prev</a> </td><th width="60%" align="center">Chapter 23. HP/SGI Extensions</th><td width="20%" align="right"> <a accesskey="n" href="ext_utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.deprecated_sgi"></a>Deprecated</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Deprecated</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="prev" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="next" href="ext_utilities.html" title="Chapter 24. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Deprecated</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_containers.html">Prev</a> </td><th width="60%" align="center">Chapter 23. HP/SGI Extensions</th><td width="20%" align="right"> <a accesskey="n" href="ext_utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.deprecated_sgi"></a>Deprecated</h2></div></div></div><p>
- The SGI hashing classes <code class="classname">hash_set</code> and
- <code class="classname">hash_set</code> have been deprecated by the
- unordered_set, unordered_multiset, unordered_map,
-Index: libstdc++-v3/doc/html/manual/facets.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/facets.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/facets.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Facets</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="localization.html" title="Chapter 8.  Localization" /><link rel="prev" href="localization.html" title="Chapter 8.  Localization" /><link rel="next" href="containers.html" title="Chapter 9.  Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Facets</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="localization.html">Prev</a> </td><th width="60%" align="center">Chapter 8. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Facets</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="localization.html" title="Chapter 8.  Localization" /><link rel="prev" href="localization.html" title="Chapter 8.  Localization" /><link rel="next" href="containers.html" title="Chapter 9.  Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Facets</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="localization.html">Prev</a> </td><th width="60%" align="center">Chapter 8. 
- Localization
-
--</th><td width="20%" align="right"> <a accesskey="n" href="containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.facet"></a>Facets</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.facet.ctype"></a>ctype</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idp15778336"></a>Specializations</h5></div></div></div><p>
-+</th><td width="20%" align="right"> <a accesskey="n" href="containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.facet"></a>Facets</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.facet.ctype"></a>ctype</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="idm269999753024"></a>Specializations</h5></div></div></div><p>
- For the required specialization codecvt&lt;wchar_t, char, mbstate_t&gt; ,
- conversions are made between the internal character set (always UCS4
- on GNU/Linux) and whatever the currently selected locale for the
-@@ -49,24 +49,24 @@
- </p></li><li class="listitem"><p>
- Rename abstract base class. See if just smash-overriding is a
- better approach. Clarify, add sanity to naming.
-- </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15793392"></a><p><span class="citetitle"><em class="citetitle">
-+ </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999738032"></a><p><span class="citetitle"><em class="citetitle">
- The GNU C Library
-- </em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">Chapters 6 Character Set Handling and 7 Locales and Internationalization. </span></p></div><div class="biblioentry"><a id="idp15798144"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">Chapters 6 Character Set Handling and 7 Locales and Internationalization. </span></p></div><div class="biblioentry"><a id="idm269999733280"></a><p><span class="citetitle"><em class="citetitle">
- Correspondence
-- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp15801232"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999730192"></a><p><span class="citetitle"><em class="citetitle">
- ISO/IEC 14882:1998 Programming languages - C++
-- </em>. </span><span class="copyright">Copyright © 1998 ISO. </span></p></div><div class="biblioentry"><a id="idp15803520"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="copyright">Copyright © 1998 ISO. </span></p></div><div class="biblioentry"><a id="idm269999727904"></a><p><span class="citetitle"><em class="citetitle">
- ISO/IEC 9899:1999 Programming languages - C
-- </em>. </span><span class="copyright">Copyright © 1999 ISO. </span></p></div><div class="biblioentry"><a id="idp15805792"></a><p><span class="title"><em>
-+ </em>. </span><span class="copyright">Copyright © 1999 ISO. </span></p></div><div class="biblioentry"><a id="idm269999725632"></a><p><span class="title"><em>
- <a class="link" href="http://www.unix.org/version3/ieee_std.html" target="_top">
- The Open Group Base Specifications, Issue 6 (IEEE Std. 1003.1-2004)
- </a>
- </em>. </span><span class="copyright">Copyright © 1999
-- The Open Group/The Institute of Electrical and Electronics Engineers, Inc.. </span></p></div><div class="biblioentry"><a id="idp15809040"></a><p><span class="citetitle"><em class="citetitle">
-+ The Open Group/The Institute of Electrical and Electronics Engineers, Inc.. </span></p></div><div class="biblioentry"><a id="idm269999722384"></a><p><span class="citetitle"><em class="citetitle">
- The C++ Programming Language, Special Edition
- </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">
- Addison Wesley
-- . </span></span></p></div><div class="biblioentry"><a id="idp15813664"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></span></p></div><div class="biblioentry"><a id="idm269999717760"></a><p><span class="citetitle"><em class="citetitle">
- Standard C++ IOStreams and Locales
- </em>. </span><span class="subtitle">
- Advanced Programmer's Guide and Reference
-@@ -409,17 +409,17 @@
- </p></li><li class="listitem"><p>
- wchar_t/char internal buffers and conversions between
- internal/external buffers?
-- </p></li></ul></div></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.codecvt.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15891136"></a><p><span class="citetitle"><em class="citetitle">
-+ </p></li></ul></div></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.codecvt.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999640080"></a><p><span class="citetitle"><em class="citetitle">
- The GNU C Library
- </em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">
- Chapters 6 Character Set Handling and 7 Locales and Internationalization
-- . </span></p></div><div class="biblioentry"><a id="idp15895888"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></p></div><div class="biblioentry"><a id="idm269999635328"></a><p><span class="citetitle"><em class="citetitle">
- Correspondence
-- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp15898976"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999632240"></a><p><span class="citetitle"><em class="citetitle">
- ISO/IEC 14882:1998 Programming languages - C++
-- </em>. </span><span class="copyright">Copyright © 1998 ISO. </span></p></div><div class="biblioentry"><a id="idp15901264"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="copyright">Copyright © 1998 ISO. </span></p></div><div class="biblioentry"><a id="idm269999629952"></a><p><span class="citetitle"><em class="citetitle">
- ISO/IEC 9899:1999 Programming languages - C
-- </em>. </span><span class="copyright">Copyright © 1999 ISO. </span></p></div><div class="biblioentry"><a id="idp15903536"></a><p><span class="title"><em>
-+ </em>. </span><span class="copyright">Copyright © 1999 ISO. </span></p></div><div class="biblioentry"><a id="idm269999627680"></a><p><span class="title"><em>
- <a class="link" href="http://www.opengroup.org/austin/" target="_top">
- System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
- </a>
-@@ -426,25 +426,25 @@
- </em>. </span><span class="copyright">Copyright © 2008
- The Open Group/The Institute of Electrical and Electronics
- Engineers, Inc.
-- . </span></p></div><div class="biblioentry"><a id="idp15906768"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></p></div><div class="biblioentry"><a id="idm269999624448"></a><p><span class="citetitle"><em class="citetitle">
- The C++ Programming Language, Special Edition
- </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">
- Addison Wesley
-- . </span></span></p></div><div class="biblioentry"><a id="idp15911392"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></span></p></div><div class="biblioentry"><a id="idm269999619824"></a><p><span class="citetitle"><em class="citetitle">
- Standard C++ IOStreams and Locales
- </em>. </span><span class="subtitle">
- Advanced Programmer's Guide and Reference
- . </span><span class="author"><span class="firstname">Angelika</span> <span class="surname">Langer</span>. </span><span class="author"><span class="firstname">Klaus</span> <span class="surname">Kreft</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley Longman, Inc.. </span><span class="publisher"><span class="publishername">
- Addison Wesley Longman
-- . </span></span></p></div><div class="biblioentry"><a id="idp15917056"></a><p><span class="title"><em>
-+ . </span></span></p></div><div class="biblioentry"><a id="idm269999614160"></a><p><span class="title"><em>
- <a class="link" href="http://www.lysator.liu.se/c/na1.html" target="_top">
- A brief description of Normative Addendum 1
- </a>
-- </em>. </span><span class="author"><span class="firstname">Clive</span> <span class="surname">Feather</span>. </span><span class="pagenums">Extended Character Sets. </span></p></div><div class="biblioentry"><a id="idp15920304"></a><p><span class="title"><em>
-+ </em>. </span><span class="author"><span class="firstname">Clive</span> <span class="surname">Feather</span>. </span><span class="pagenums">Extended Character Sets. </span></p></div><div class="biblioentry"><a id="idm269999610912"></a><p><span class="title"><em>
- <a class="link" href="http://tldp.org/HOWTO/Unicode-HOWTO.html" target="_top">
- The Unicode HOWTO
- </a>
-- </em>. </span><span class="author"><span class="firstname">Bruno</span> <span class="surname">Haible</span>. </span></p></div><div class="biblioentry"><a id="idp15923088"></a><p><span class="title"><em>
-+ </em>. </span><span class="author"><span class="firstname">Bruno</span> <span class="surname">Haible</span>. </span></p></div><div class="biblioentry"><a id="idm269999608128"></a><p><span class="title"><em>
- <a class="link" href="http://www.cl.cam.ac.uk/~mgk25/unicode.html" target="_top">
- UTF-8 and Unicode FAQ for Unix/Linux
- </a>
-@@ -690,16 +690,16 @@
- model. As of this writing, it is unknown how to query to see
- if a specified message catalog exists using the gettext
- package.
-- </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.messages.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp16003632"></a><p><span class="citetitle"><em class="citetitle">
-+ </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="facet.messages.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999527584"></a><p><span class="citetitle"><em class="citetitle">
- The GNU C Library
- </em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">Chapters 6 Character Set Handling, and 7 Locales and Internationalization
-- . </span></p></div><div class="biblioentry"><a id="idp16008384"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></p></div><div class="biblioentry"><a id="idm269999522832"></a><p><span class="citetitle"><em class="citetitle">
- Correspondence
-- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp16011472"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999519744"></a><p><span class="citetitle"><em class="citetitle">
- ISO/IEC 14882:1998 Programming languages - C++
-- </em>. </span><span class="copyright">Copyright © 1998 ISO. </span></p></div><div class="biblioentry"><a id="idp16013760"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="copyright">Copyright © 1998 ISO. </span></p></div><div class="biblioentry"><a id="idm269999517456"></a><p><span class="citetitle"><em class="citetitle">
- ISO/IEC 9899:1999 Programming languages - C
-- </em>. </span><span class="copyright">Copyright © 1999 ISO. </span></p></div><div class="biblioentry"><a id="idp16016032"></a><p><span class="title"><em>
-+ </em>. </span><span class="copyright">Copyright © 1999 ISO. </span></p></div><div class="biblioentry"><a id="idm269999515184"></a><p><span class="title"><em>
- <a class="link" href="http://www.opengroup.org/austin/" target="_top">
- System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
- </a>
-@@ -706,23 +706,23 @@
- </em>. </span><span class="copyright">Copyright © 2008
- The Open Group/The Institute of Electrical and Electronics
- Engineers, Inc.
-- . </span></p></div><div class="biblioentry"><a id="idp16019264"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></p></div><div class="biblioentry"><a id="idm269999511952"></a><p><span class="citetitle"><em class="citetitle">
- The C++ Programming Language, Special Edition
- </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">
- Addison Wesley
-- . </span></span></p></div><div class="biblioentry"><a id="idp16023888"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></span></p></div><div class="biblioentry"><a id="idm269999507328"></a><p><span class="citetitle"><em class="citetitle">
- Standard C++ IOStreams and Locales
- </em>. </span><span class="subtitle">
- Advanced Programmer's Guide and Reference
- . </span><span class="author"><span class="firstname">Angelika</span> <span class="surname">Langer</span>. </span><span class="author"><span class="firstname">Klaus</span> <span class="surname">Kreft</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley Longman, Inc.. </span><span class="publisher"><span class="publishername">
- Addison Wesley Longman
-- . </span></span></p></div><div class="biblioentry"><a id="idp16029552"></a><p><span class="title"><em>
-- <a class="link" href="http://java.sun.com/reference/api/index.html" target="_top">
-+ . </span></span></p></div><div class="biblioentry"><a id="idm269999501664"></a><p><span class="title"><em>
-+ <a class="link" href="http://www.oracle.com/technetwork/java/api/index.html" target="_top">
- API Specifications, Java Platform
- </a>
- </em>. </span><span class="pagenums">java.util.Properties, java.text.MessageFormat,
- java.util.Locale, java.util.ResourceBundle
-- . </span></p></div><div class="biblioentry"><a id="idp16031888"></a><p><span class="title"><em>
-+ . </span></p></div><div class="biblioentry"><a id="idm269999499328"></a><p><span class="title"><em>
- <a class="link" href="https://www.gnu.org/software/gettext/" target="_top">
- GNU gettext tools, version 0.10.38, Native Language Support
- Library and Tools.
-Index: libstdc++-v3/doc/html/manual/diagnostics.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/diagnostics.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/diagnostics.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 5.  Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="termination.html" title="Termination" /><link rel="next" href="concept_checking.html" title="Concept Checking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 5. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 5.  Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="termination.html" title="Termination" /><link rel="next" href="concept_checking.html" title="Concept Checking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 5. 
- Diagnostics
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="termination.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="concept_checking.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.diagnostics"></a>Chapter 5. 
- Diagnostics
-- <a id="idp13835248" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="concept_checking.html">Concept Checking</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.exceptions"></a>Exceptions</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.diagnostics.exceptions.api"></a>API Reference</h3></div></div></div><p>
-+ <a id="idm270001697504" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="concept_checking.html">Concept Checking</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.exceptions"></a>Exceptions</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.diagnostics.exceptions.api"></a>API Reference</h3></div></div></div><p>
- All exception objects are defined in one of the standard header
- files: <code class="filename">exception</code>,
- <code class="filename">stdexcept</code>, <code class="filename">new</code>, and
-Index: libstdc++-v3/doc/html/manual/mt_allocator_design.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/mt_allocator_design.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/mt_allocator_design.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="next" href="mt_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.design_issues"></a>Design Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.overview"></a>Overview</h3></div></div></div><p> There are three general components to the allocator: a datum
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="next" href="mt_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.design_issues"></a>Design Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.overview"></a>Overview</h3></div></div></div><p> There are three general components to the allocator: a datum
- describing the characteristics of the memory pool, a policy class
- containing this pool that links instantiation types to common or
- individual pools, and a class inheriting from the policy class that is
-Index: libstdc++-v3/doc/html/manual/appendix_free.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/appendix_free.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/appendix_free.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix C.  Free Software Needs Free Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="backwards.html" title="Backwards Compatibility" /><link rel="next" href="appendix_gpl.html" title="Appendix D.  GNU General Public License version 3" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix C. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix C.  Free Software Needs Free Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="backwards.html" title="Backwards Compatibility" /><link rel="next" href="appendix_gpl.html" title="Appendix D.  GNU General Public License version 3" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix C. 
- Free Software Needs Free Documentation
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="backwards.html">Prev</a> </td><th width="60%" align="center">Part IV. 
-@@ -6,7 +6,7 @@
- Appendices
- </th><td width="20%" align="right"> <a accesskey="n" href="appendix_gpl.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.free"></a>
- Free Software Needs Free Documentation
-- <a id="idp23426192" class="indexterm"></a>
-+ <a id="idm269992106560" class="indexterm"></a>
- </h1></div></div></div><p>
- The biggest deficiency in free operating systems is not in the
- software--it is the lack of good free manuals that we can include in
-Index: libstdc++-v3/doc/html/manual/algorithms.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/algorithms.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/algorithms.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 11.  Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library, algorithm" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="iterators.html" title="Chapter 10.  Iterators" /><link rel="next" href="numerics.html" title="Chapter 12.  Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 11. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 11.  Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library, algorithm" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="iterators.html" title="Chapter 10.  Iterators" /><link rel="next" href="numerics.html" title="Chapter 12.  Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 11. 
- Algorithms
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="iterators.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="numerics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.algorithms"></a>Chapter 11. 
- Algorithms
-- <a id="idp16191968" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="algorithms.html#std.algorithms.mutating">Mutating</a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.mutating.swap"><code class="function">swap</code></a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.swap.specializations">Specializations</a></span></dt></dl></dd></dl></dd></dl></div><p>
-+ <a id="idm269999339120" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="algorithms.html#std.algorithms.mutating">Mutating</a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.mutating.swap"><code class="function">swap</code></a></span></dt><dd><dl><dt><span class="section"><a href="algorithms.html#algorithms.swap.specializations">Specializations</a></span></dt></dl></dd></dl></dd></dl></div><p>
- The neatest accomplishment of the algorithms section is that all the
- work is done via iterators, not containers directly. This means two
- important things:
-Index: libstdc++-v3/doc/html/manual/appendix_porting.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/appendix_porting.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/appendix_porting.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix B.  Porting and Maintenance</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="source_design_notes.html" title="Design Notes" /><link rel="next" href="documentation_hacking.html" title="Writing and Generating Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix B. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix B.  Porting and Maintenance</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="source_design_notes.html" title="Design Notes" /><link rel="next" href="documentation_hacking.html" title="Writing and Generating Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix B. 
- Porting and Maintenance
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_design_notes.html">Prev</a> </td><th width="60%" align="center">Part IV. 
-@@ -6,8 +6,8 @@
- Appendices
- </th><td width="20%" align="right"> <a accesskey="n" href="documentation_hacking.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.porting"></a>
- Porting and Maintenance
-- <a id="idp22008864" class="indexterm"></a>
--</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="appendix_porting.html#appendix.porting.build_hacking">Configure and Build Hacking</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview">Overview</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.basic">General Process</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.map">What Comes from Where</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure">Configure</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.scripts">Storing Information in non-AC files (like configure.host)</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.conventions">Coding and Commenting Conventions</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.acinclude">The acinclude.m4 layout</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.enable"><code class="constant">GLIBCXX_ENABLE</code>, the <code class="literal">--enable</code> maker</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.make">Make</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html">Writing and Generating Documentation</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doc.intro">Introduction</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.generation">Generating Documentation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.doxygen">Doxygen</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doxygen.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.rules">Generating the Doxygen Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.markup">Markup</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html#doc.docbook">Docbook</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#docbook.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.rules">Generating the DocBook Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.validation">Editing and Validation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.examples">File Organization and Basics</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.markup">Markup By Example</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="internals.html">Porting to New Hardware or Operating Systems</a></span></dt><dd><dl><dt><span class="section"><a href="internals.html#internals.os">Operating System</a></span></dt><dt><span class="section"><a href="internals.html#internals.cpu">CPU</a></span></dt><dt><span class="section"><a href="internals.html#internals.char_types">Character Types</a></span></dt><dt><span class="section"><a href="internals.html#internals.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="internals.html#internals.numeric_limits">Numeric Limits</a></span></dt><dt><span class="section"><a href="internals.html#internals.libtool">Libtool</a></span></dt></dl></dd><dt><span class="section"><a href="test.html">Test</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization">Organization</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization.layout">Directory Layout</a></span></dt><dt><span class="section"><a href="test.html#test.organization.naming">Naming Conventions</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.run">Running the Testsuite</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.run.basic">Basic</a></span></dt><dt><span class="section"><a href="test.html#test.run.variations">Variations</a></span></dt><dt><span class="section"><a href="test.html#test.run.permutations">Permutations</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.new_tests">Writing a new test case</a></span></dt><dt><span class="section"><a href="test.html#test.harness">Test Harness and Utilities</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.harness.dejagnu">Dejagnu Harness Details</a></span></dt><dt><span class="section"><a href="test.html#test.harness.utils">Utilities</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.special">Special Topics</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.exception.safety">
-+ <a id="idm269993523968" class="indexterm"></a>
-+</h1></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="appendix_porting.html#appendix.porting.build_hacking">Configure and Build Hacking</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview">Overview</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.basic">General Process</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.overview.map">What Comes from Where</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure">Configure</a></span></dt><dd><dl><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.scripts">Storing Information in non-AC files (like configure.host)</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.conventions">Coding and Commenting Conventions</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.acinclude">The acinclude.m4 layout</a></span></dt><dt><span class="section"><a href="appendix_porting.html#build_hacking.configure.enable"><code class="constant">GLIBCXX_ENABLE</code>, the <code class="literal">--enable</code> maker</a></span></dt></dl></dd><dt><span class="section"><a href="appendix_porting.html#build_hacking.make">Make</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html">Writing and Generating Documentation</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doc.intro">Introduction</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.generation">Generating Documentation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doc.doxygen">Doxygen</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#doxygen.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.rules">Generating the Doxygen Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#doxygen.markup">Markup</a></span></dt></dl></dd><dt><span class="section"><a href="documentation_hacking.html#doc.docbook">Docbook</a></span></dt><dd><dl><dt><span class="section"><a href="documentation_hacking.html#docbook.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.rules">Generating the DocBook Files</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.debug">Debugging Generation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.validation">Editing and Validation</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.examples">File Organization and Basics</a></span></dt><dt><span class="section"><a href="documentation_hacking.html#docbook.markup">Markup By Example</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="internals.html">Porting to New Hardware or Operating Systems</a></span></dt><dd><dl><dt><span class="section"><a href="internals.html#internals.os">Operating System</a></span></dt><dt><span class="section"><a href="internals.html#internals.cpu">CPU</a></span></dt><dt><span class="section"><a href="internals.html#internals.char_types">Character Types</a></span></dt><dt><span class="section"><a href="internals.html#internals.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="internals.html#internals.numeric_limits">Numeric Limits</a></span></dt><dt><span class="section"><a href="internals.html#internals.libtool">Libtool</a></span></dt></dl></dd><dt><span class="section"><a href="test.html">Test</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization">Organization</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.organization.layout">Directory Layout</a></span></dt><dt><span class="section"><a href="test.html#test.organization.naming">Naming Conventions</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.run">Running the Testsuite</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.run.basic">Basic</a></span></dt><dt><span class="section"><a href="test.html#test.run.variations">Variations</a></span></dt><dt><span class="section"><a href="test.html#test.run.permutations">Permutations</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.new_tests">Writing a new test case</a></span></dt><dt><span class="section"><a href="test.html#test.harness">Test Harness and Utilities</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.harness.dejagnu">Dejagnu Harness Details</a></span></dt><dt><span class="section"><a href="test.html#test.harness.utils">Utilities</a></span></dt></dl></dd><dt><span class="section"><a href="test.html#test.special">Special Topics</a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.exception.safety">
- Qualifying Exception Safety Guarantees
-
- </a></span></dt><dd><dl><dt><span class="section"><a href="test.html#test.exception.safety.overview">Overview</a></span></dt><dt><span class="section"><a href="test.html#test.exception.safety.status">
-@@ -61,7 +61,7 @@
- in the build directory starts the build process. The <code class="literal">all</code> target comes from the <code class="filename">Makefile</code> file, which is generated via <span class="command"><strong>configure</strong></span> from the <code class="filename">Makefile.in</code> file, which is in turn generated (via
- <span class="command"><strong>automake</strong></span>) from the file
- <code class="filename">Makefile.am</code>.
--</p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="build_hacking.overview.map"></a>What Comes from Where</h4></div></div></div><div class="figure"><a id="idp22035648"></a><p class="title"><strong>Figure B.1. Configure and Build File Dependencies</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/confdeps.png" align="middle" alt="Dependency Graph for Configure and Build Files" /></div></div></div><br class="figure-break" /><p>
-+</p></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="build_hacking.overview.map"></a>What Comes from Where</h4></div></div></div><div class="figure"><a id="idm269993497120"></a><p class="title"><strong>Figure B.1. Configure and Build File Dependencies</strong></p><div class="figure-contents"><div class="mediaobject" align="center"><img src="../images/confdeps.png" align="middle" alt="Dependency Graph for Configure and Build Files" /></div></div></div><br class="figure-break" /><p>
- Regenerate all generated files by using the command
- <code class="code">autoreconf</code> at the top level of the libstdc++ source
- directory.
-Index: libstdc++-v3/doc/html/manual/profile_mode_cost_model.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/profile_mode_cost_model.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/profile_mode_cost_model.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Empirical Cost Model</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_api.html" title="Extensions for Custom Containers" /><link rel="next" href="profile_mode_impl.html" title="Implementation Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Empirical Cost Model</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_api.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.cost_model"></a>Empirical Cost Model</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Empirical Cost Model</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_api.html" title="Extensions for Custom Containers" /><link rel="next" href="profile_mode_impl.html" title="Implementation Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Empirical Cost Model</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_api.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.cost_model"></a>Empirical Cost Model</h2></div></div></div><p>
- Currently, the cost model uses formulas with predefined relative weights
- for alternative containers or container implementations. For instance,
- iterating through a vector is X times faster than iterating through a list.
-Index: libstdc++-v3/doc/html/manual/make.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/make.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/make.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Make</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="configure.html" title="Configure" /><link rel="next" href="using.html" title="Chapter 3. Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Make</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="configure.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.make"></a>Make</h2></div></div></div><p>If you have never done this before, you should read the basic
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Make</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="configure.html" title="Configure" /><link rel="next" href="using.html" title="Chapter 3. Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Make</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="configure.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.make"></a>Make</h2></div></div></div><p>If you have never done this before, you should read the basic
- <a class="link" href="http://gcc.gnu.org/install/" target="_top">GCC Installation
- Instructions</a> first. Read <span class="emphasis"><em>all of them</em></span>.
- <span class="emphasis"><em>Twice.</em></span>
-Index: libstdc++-v3/doc/html/manual/pairs.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/pairs.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/pairs.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Pairs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="next" href="memory.html" title="Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Pairs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="utilities.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Pairs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="next" href="memory.html" title="Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Pairs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="utilities.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
- Utilities
-
- </th><td width="20%" align="right"> <a accesskey="n" href="memory.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.pairs"></a>Pairs</h2></div></div></div><p>The <code class="code">pair&lt;T1,T2&gt;</code> is a simple and handy way to
-Index: libstdc++-v3/doc/html/manual/test.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/test.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/test.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Test</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, test, testsuite, performance, conformance, ABI, exception safety" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="internals.html" title="Porting to New Hardware or Operating Systems" /><link rel="next" href="abi.html" title="ABI Policy and Guidelines" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Test</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="internals.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Test</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, test, testsuite, performance, conformance, ABI, exception safety" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="internals.html" title="Porting to New Hardware or Operating Systems" /><link rel="next" href="abi.html" title="ABI Policy and Guidelines" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Test</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="internals.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
- Porting and Maintenance
-
- </th><td width="20%" align="right"> <a accesskey="n" href="abi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.test"></a>Test</h2></div></div></div><p>
-@@ -492,7 +492,7 @@
- reporting functions including:
- </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: circle; "><li class="listitem"><p>time_counter</p></li><li class="listitem"><p>resource_counter</p></li><li class="listitem"><p>report_performance</p></li></ul></div></li></ul></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="test.special"></a>Special Topics</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="test.exception.safety"></a>
- Qualifying Exception Safety Guarantees
-- <a id="idp22628992" class="indexterm"></a>
-+ <a id="idm269992903504" class="indexterm"></a>
- </h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="test.exception.safety.overview"></a>Overview</h5></div></div></div><p>
- Testing is composed of running a particular test sequence,
- and looking at what happens to the surrounding code when
-Index: libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Linking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_namespaces.html" title="Namespaces" /><link rel="next" href="using_concurrency.html" title="Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Linking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_namespaces.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_concurrency.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.linkage"></a>Linking</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.linkage.freestanding"></a>Almost Nothing</h3></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Linking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_namespaces.html" title="Namespaces" /><link rel="next" href="using_concurrency.html" title="Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Linking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_namespaces.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_concurrency.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.linkage"></a>Linking</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.linkage.freestanding"></a>Almost Nothing</h3></div></div></div><p>
- Or as close as it gets: freestanding. This is a minimal
- configuration, with only partial support for the standard
- library. Assume only the following header files can be used:
-Index: libstdc++-v3/doc/html/manual/using_headers.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/using_headers.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/using_headers.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Headers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using.html" title="Chapter 3. Using" /><link rel="next" href="using_macros.html" title="Macros" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Headers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_macros.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.headers"></a>Headers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.all"></a>Header Files</h3></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Headers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using.html" title="Chapter 3. Using" /><link rel="next" href="using_macros.html" title="Macros" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Headers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_macros.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.headers"></a>Headers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.all"></a>Header Files</h3></div></div></div><p>
- The C++ standard specifies the entire set of header files that
- must be available to all hosted implementations. Actually, the
- word "files" is a misnomer, since the contents of the
-@@ -18,19 +18,19 @@
- the 1998 standard as updated for 2003, and the current 2011 standard.
- </p><p>
- C++98/03 include files. These are available in the default compilation mode, i.e. <code class="code">-std=c++98</code> or <code class="code">-std=gnu++98</code>.
-- </p><div class="table"><a id="idp13079360"></a><p class="title"><strong>Table 3.2. C++ 1998 Library Headers</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">complex</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td></tr><tr><td align="left"><code class="filename">fstream</code></td><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td><td align="left"><code class="filename">iosfwd</code></td></tr><tr><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td><td align="left"><code class="filename">list</code></td></tr><tr><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td></tr><tr><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">typeinfo</code></td></tr><tr><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13115840"></a><p class="title"><strong>Table 3.3. C++ 1998 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">ciso646</code></td></tr><tr><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td></tr><tr><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p>
-+ </p><div class="table"><a id="idm270002453792"></a><p class="title"><strong>Table 3.2. C++ 1998 Library Headers</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">complex</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td></tr><tr><td align="left"><code class="filename">fstream</code></td><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td><td align="left"><code class="filename">iosfwd</code></td></tr><tr><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td><td align="left"><code class="filename">list</code></td></tr><tr><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td></tr><tr><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">typeinfo</code></td></tr><tr><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002417312"></a><p class="title"><strong>Table 3.3. C++ 1998 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">ciso646</code></td></tr><tr><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td></tr><tr><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p>
- C++11 include files. These are only available in C++11 compilation
- mode, i.e. <code class="literal">-std=c++11</code> or <code class="literal">-std=gnu++11</code>.
--</p><p></p><div class="table"><a id="idp13140576"></a><p class="title"><strong>Table 3.4. C++ 2011 Library Headers</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">array</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">chrono</code></td><td align="left"><code class="filename">complex</code></td></tr><tr><td align="left"><code class="filename">condition_variable</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td><td align="left"><code class="filename">forward_list</code></td><td align="left"><code class="filename">fstream</code></td></tr><tr><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">future</code></td><td align="left"><code class="filename">initalizer_list</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td></tr><tr><td align="left"><code class="filename">iosfwd</code></td><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td></tr><tr><td align="left"><code class="filename">list</code></td><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">mutex</code></td></tr><tr><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">random</code></td></tr><tr><td align="left"><code class="filename">ratio</code></td><td align="left"><code class="filename">regex</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">system_error</code></td><td align="left"><code class="filename">thread</code></td></tr><tr><td align="left"><code class="filename">tuple</code></td><td align="left"><code class="filename">type_traits</code></td><td align="left"><code class="filename">typeinfo</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="filename">unordered_set</code></td></tr><tr><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13192016"></a><p class="title"><strong>Table 3.5. C++ 2011 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">ccomplex</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cfenv</code></td></tr><tr><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">cinttypes</code></td><td align="left"><code class="filename">ciso646</code></td><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td></tr><tr><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstdbool</code></td></tr><tr><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdint</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctgmath</code></td><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cuchar</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
-+</p><p></p><div class="table"><a id="idm270002392576"></a><p class="title"><strong>Table 3.4. C++ 2011 Library Headers</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">array</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">chrono</code></td><td align="left"><code class="filename">complex</code></td></tr><tr><td align="left"><code class="filename">condition_variable</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td><td align="left"><code class="filename">forward_list</code></td><td align="left"><code class="filename">fstream</code></td></tr><tr><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">future</code></td><td align="left"><code class="filename">initalizer_list</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td></tr><tr><td align="left"><code class="filename">iosfwd</code></td><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td></tr><tr><td align="left"><code class="filename">list</code></td><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">mutex</code></td></tr><tr><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">random</code></td></tr><tr><td align="left"><code class="filename">ratio</code></td><td align="left"><code class="filename">regex</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">system_error</code></td><td align="left"><code class="filename">thread</code></td></tr><tr><td align="left"><code class="filename">tuple</code></td><td align="left"><code class="filename">type_traits</code></td><td align="left"><code class="filename">typeinfo</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="filename">unordered_set</code></td></tr><tr><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002341136"></a><p class="title"><strong>Table 3.5. C++ 2011 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">ccomplex</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cfenv</code></td></tr><tr><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">cinttypes</code></td><td align="left"><code class="filename">ciso646</code></td><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td></tr><tr><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstdbool</code></td></tr><tr><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdint</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctgmath</code></td><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cuchar</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
- In addition, TR1 includes as:
--</p><div class="table"><a id="idp13221904"></a><p class="title"><strong>Table 3.6. C++ TR 1 Library Headers</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/array</code></td><td align="left"><code class="filename">tr1/complex</code></td><td align="left"><code class="filename">tr1/memory</code></td><td align="left"><code class="filename">tr1/functional</code></td><td align="left"><code class="filename">tr1/random</code></td></tr><tr><td align="left"><code class="filename">tr1/regex</code></td><td align="left"><code class="filename">tr1/tuple</code></td><td align="left"><code class="filename">tr1/type_traits</code></td><td align="left"><code class="filename">tr1/unordered_map</code></td><td align="left"><code class="filename">tr1/unordered_set</code></td></tr><tr><td align="left"><code class="filename">tr1/utility</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13238832"></a><p class="title"><strong>Table 3.7. C++ TR 1 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/ccomplex</code></td><td align="left"><code class="filename">tr1/cfenv</code></td><td align="left"><code class="filename">tr1/cfloat</code></td><td align="left"><code class="filename">tr1/cmath</code></td><td align="left"><code class="filename">tr1/cinttypes</code></td></tr><tr><td align="left"><code class="filename">tr1/climits</code></td><td align="left"><code class="filename">tr1/cstdarg</code></td><td align="left"><code class="filename">tr1/cstdbool</code></td><td align="left"><code class="filename">tr1/cstdint</code></td><td align="left"><code class="filename">tr1/cstdio</code></td></tr><tr><td align="left"><code class="filename">tr1/cstdlib</code></td><td align="left"><code class="filename">tr1/ctgmath</code></td><td align="left"><code class="filename">tr1/ctime</code></td><td align="left"><code class="filename">tr1/cwchar</code></td><td align="left"><code class="filename">tr1/cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>Decimal floating-point arithmetic is available if the C++
-+</p><div class="table"><a id="idm270002311248"></a><p class="title"><strong>Table 3.6. C++ TR 1 Library Headers</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/array</code></td><td align="left"><code class="filename">tr1/complex</code></td><td align="left"><code class="filename">tr1/memory</code></td><td align="left"><code class="filename">tr1/functional</code></td><td align="left"><code class="filename">tr1/random</code></td></tr><tr><td align="left"><code class="filename">tr1/regex</code></td><td align="left"><code class="filename">tr1/tuple</code></td><td align="left"><code class="filename">tr1/type_traits</code></td><td align="left"><code class="filename">tr1/unordered_map</code></td><td align="left"><code class="filename">tr1/unordered_set</code></td></tr><tr><td align="left"><code class="filename">tr1/utility</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002294320"></a><p class="title"><strong>Table 3.7. C++ TR 1 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/ccomplex</code></td><td align="left"><code class="filename">tr1/cfenv</code></td><td align="left"><code class="filename">tr1/cfloat</code></td><td align="left"><code class="filename">tr1/cmath</code></td><td align="left"><code class="filename">tr1/cinttypes</code></td></tr><tr><td align="left"><code class="filename">tr1/climits</code></td><td align="left"><code class="filename">tr1/cstdarg</code></td><td align="left"><code class="filename">tr1/cstdbool</code></td><td align="left"><code class="filename">tr1/cstdint</code></td><td align="left"><code class="filename">tr1/cstdio</code></td></tr><tr><td align="left"><code class="filename">tr1/cstdlib</code></td><td align="left"><code class="filename">tr1/ctgmath</code></td><td align="left"><code class="filename">tr1/ctime</code></td><td align="left"><code class="filename">tr1/cwchar</code></td><td align="left"><code class="filename">tr1/cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>Decimal floating-point arithmetic is available if the C++
- compiler supports scalar decimal floating-point types defined via
- <code class="code">__attribute__((mode(SD|DD|LD)))</code>.
--</p><div class="table"><a id="idp13259904"></a><p class="title"><strong>Table 3.8. C++ TR 24733 Decimal Floating-Point Header</strong></p><div class="table-contents"><table summary="C++ TR 24733 Decimal Floating-Point Header" border="1"><colgroup><col align="left" class="c1" /></colgroup><tbody><tr><td align="left"><code class="filename">decimal/decimal</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
-+</p><div class="table"><a id="idm270002273248"></a><p class="title"><strong>Table 3.8. C++ TR 24733 Decimal Floating-Point Header</strong></p><div class="table-contents"><table summary="C++ TR 24733 Decimal Floating-Point Header" border="1"><colgroup><col align="left" class="c1" /></colgroup><tbody><tr><td align="left"><code class="filename">decimal/decimal</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
- Also included are files for the C++ ABI interface:
--</p><div class="table"><a id="idp13265424"></a><p class="title"><strong>Table 3.9. C++ ABI Headers</strong></p><div class="table-contents"><table summary="C++ ABI Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">cxxabi.h</code></td><td align="left"><code class="filename">cxxabi_forced.h</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
-+</p><div class="table"><a id="idm270002267728"></a><p class="title"><strong>Table 3.9. C++ ABI Headers</strong></p><div class="table-contents"><table summary="C++ ABI Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">cxxabi.h</code></td><td align="left"><code class="filename">cxxabi_forced.h</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
- And a large variety of extensions.
--</p><div class="table"><a id="idp13271824"></a><p class="title"><strong>Table 3.10. Extension Headers</strong></p><div class="table-contents"><table summary="Extension Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">ext/algorithm</code></td><td align="left"><code class="filename">ext/atomicity.h</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"><code class="filename">ext/cast.h</code></td></tr><tr><td align="left"><code class="filename">ext/codecvt_specializations.h</code></td><td align="left"><code class="filename">ext/concurrence.h</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="filename">ext/enc_filebuf.h</code></td><td align="left"><code class="filename">ext/extptr_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/functional</code></td><td align="left"><code class="filename">ext/iterator</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="filename">ext/memory</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="filename">ext/numeric</code></td><td align="left"><code class="filename">ext/numeric_traits.h</code></td><td align="left"><code class="filename">ext/pb_ds/assoc_container.h</code></td><td align="left"><code class="filename">ext/pb_ds/priority_queue.h</code></td></tr><tr><td align="left"><code class="filename">ext/pod_char_traits.h</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="filename">ext/rb_tree</code></td><td align="left"><code class="filename">ext/rope</code></td><td align="left"><code class="filename">ext/slist</code></td></tr><tr><td align="left"><code class="filename">ext/stdio_filebuf.h</code></td><td align="left"><code class="filename">ext/stdio_sync_filebuf.h</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left"><code class="filename">ext/typelist.h</code></td><td align="left"><code class="filename">ext/type_traits.h</code></td></tr><tr><td align="left"><code class="filename">ext/vstring.h</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13307552"></a><p class="title"><strong>Table 3.11. Extension Debug Headers</strong></p><div class="table-contents"><table summary="Extension Debug Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">debug/bitset</code></td><td align="left"><code class="filename">debug/deque</code></td><td align="left"><code class="filename">debug/list</code></td><td align="left"><code class="filename">debug/map</code></td><td align="left"><code class="filename">debug/set</code></td></tr><tr><td align="left"><code class="filename">debug/string</code></td><td align="left"><code class="filename">debug/unordered_map</code></td><td align="left"><code class="filename">debug/unordered_set</code></td><td align="left"><code class="filename">debug/vector</code></td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13322320"></a><p class="title"><strong>Table 3.12. Extension Profile Headers</strong></p><div class="table-contents"><table summary="Extension Profile Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><tbody><tr><td align="left"><code class="filename">profile/bitset</code></td><td align="left"><code class="filename">profile/deque</code></td><td align="left"><code class="filename">profile/list</code></td><td align="left"><code class="filename">profile/map</code></td></tr><tr><td align="left"><code class="filename">profile/set</code></td><td align="left"><code class="filename">profile/unordered_map</code></td><td align="left"><code class="filename">profile/unordered_set</code></td><td align="left"><code class="filename">profile/vector</code></td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idp13335696"></a><p class="title"><strong>Table 3.13. Extension Parallel Headers</strong></p><div class="table-contents"><table summary="Extension Parallel Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">parallel/algorithm</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr></tbody></table></div></div><br class="table-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.mixing"></a>Mixing Headers</h3></div></div></div><p> A few simple rules.
-+</p><div class="table"><a id="idm270002261328"></a><p class="title"><strong>Table 3.10. Extension Headers</strong></p><div class="table-contents"><table summary="Extension Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">ext/algorithm</code></td><td align="left"><code class="filename">ext/atomicity.h</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"><code class="filename">ext/cast.h</code></td></tr><tr><td align="left"><code class="filename">ext/codecvt_specializations.h</code></td><td align="left"><code class="filename">ext/concurrence.h</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="filename">ext/enc_filebuf.h</code></td><td align="left"><code class="filename">ext/extptr_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/functional</code></td><td align="left"><code class="filename">ext/iterator</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="filename">ext/memory</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="filename">ext/numeric</code></td><td align="left"><code class="filename">ext/numeric_traits.h</code></td><td align="left"><code class="filename">ext/pb_ds/assoc_container.h</code></td><td align="left"><code class="filename">ext/pb_ds/priority_queue.h</code></td></tr><tr><td align="left"><code class="filename">ext/pod_char_traits.h</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="filename">ext/rb_tree</code></td><td align="left"><code class="filename">ext/rope</code></td><td align="left"><code class="filename">ext/slist</code></td></tr><tr><td align="left"><code class="filename">ext/stdio_filebuf.h</code></td><td align="left"><code class="filename">ext/stdio_sync_filebuf.h</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left"><code class="filename">ext/typelist.h</code></td><td align="left"><code class="filename">ext/type_traits.h</code></td></tr><tr><td align="left"><code class="filename">ext/vstring.h</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002225600"></a><p class="title"><strong>Table 3.11. Extension Debug Headers</strong></p><div class="table-contents"><table summary="Extension Debug Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">debug/bitset</code></td><td align="left"><code class="filename">debug/deque</code></td><td align="left"><code class="filename">debug/list</code></td><td align="left"><code class="filename">debug/map</code></td><td align="left"><code class="filename">debug/set</code></td></tr><tr><td align="left"><code class="filename">debug/string</code></td><td align="left"><code class="filename">debug/unordered_map</code></td><td align="left"><code class="filename">debug/unordered_set</code></td><td align="left"><code class="filename">debug/vector</code></td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002210832"></a><p class="title"><strong>Table 3.12. Extension Profile Headers</strong></p><div class="table-contents"><table summary="Extension Profile Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><tbody><tr><td align="left"><code class="filename">profile/bitset</code></td><td align="left"><code class="filename">profile/deque</code></td><td align="left"><code class="filename">profile/list</code></td><td align="left"><code class="filename">profile/map</code></td></tr><tr><td align="left"><code class="filename">profile/set</code></td><td align="left"><code class="filename">profile/unordered_map</code></td><td align="left"><code class="filename">profile/unordered_set</code></td><td align="left"><code class="filename">profile/vector</code></td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="idm270002197456"></a><p class="title"><strong>Table 3.13. Extension Parallel Headers</strong></p><div class="table-contents"><table summary="Extension Parallel Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">parallel/algorithm</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr></tbody></table></div></div><br class="table-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.mixing"></a>Mixing Headers</h3></div></div></div><p> A few simple rules.
- </p><p>First, mixing different dialects of the standard headers is not
- possible. It's an all-or-nothing affair. Thus, code like
- </p><pre class="programlisting">
-Index: libstdc++-v3/doc/html/manual/using_namespaces.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/using_namespaces.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/using_namespaces.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Namespaces</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_macros.html" title="Macros" /><link rel="next" href="using_dynamic_or_shared.html" title="Linking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Namespaces</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_macros.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dynamic_or_shared.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.namespaces"></a>Namespaces</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.namespaces.all"></a>Available Namespaces</h3></div></div></div><p> There are three main namespaces.
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Namespaces</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_macros.html" title="Macros" /><link rel="next" href="using_dynamic_or_shared.html" title="Linking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Namespaces</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_macros.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dynamic_or_shared.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.namespaces"></a>Namespaces</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.namespaces.all"></a>Available Namespaces</h3></div></div></div><p> There are three main namespaces.
- </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>std</p><p>The ISO C++ standards specify that "all library entities are defined
- within namespace std." This includes namespaces nested
- within <code class="code">namespace std</code>, such as <code class="code">namespace
-Index: libstdc++-v3/doc/html/manual/debug.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/debug.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/debug.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Debugging Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_exceptions.html" title="Exceptions" /><link rel="next" href="std_contents.html" title="Part II.  Standard Contents" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Debugging Support</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_exceptions.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="std_contents.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.debug"></a>Debugging Support</h2></div></div></div><p>
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Debugging Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_exceptions.html" title="Exceptions" /><link rel="next" href="std_contents.html" title="Part II.  Standard Contents" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Debugging Support</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_exceptions.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="std_contents.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.debug"></a>Debugging Support</h2></div></div></div><p>
- There are numerous things that can be done to improve the ease with
- which C++ binaries are debugged when using the GNU tool chain. Here
- are some of them.
-@@ -161,7 +161,7 @@
- DRD</a>,
- <a class="link" href="http://valgrind.org/docs/manual/hg-manual.html" target="_top">
- Helgrind</a>, and
-- <a class="link" href="http://code.google.com/p/data-race-test" target="_top">
-+ <a class="link" href="http://code.google.com/p/data-race-test/" target="_top">
- ThreadSanitizer</a>.
- </p><p>
- With DRD, Helgrind and ThreadSanitizer you will need to define
-Index: libstdc++-v3/doc/html/manual/localization.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/localization.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/localization.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 8.  Localization</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="strings.html" title="Chapter 7.  Strings" /><link rel="next" href="facets.html" title="Facets" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 8. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 8.  Localization</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="strings.html" title="Chapter 7.  Strings" /><link rel="next" href="facets.html" title="Facets" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 8. 
- Localization
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="strings.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="facets.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.localization"></a>Chapter 8. 
- Localization
-- <a id="idp15701088" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.locales"></a>Locales</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.locales.locale"></a>locale</h3></div></div></div><p>
-+ <a id="idm269999830208" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.locales"></a>Locales</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.locales.locale"></a>locale</h3></div></div></div><p>
- Describes the basic locale object, including nested
- classes id, facet, and the reference-counted implementation object,
- class _Impl.
-@@ -402,18 +402,18 @@
- What should non-required facet instantiations do? If the
- generic implementation is provided, then how to end-users
- provide specializations?
-- </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="locales.locale.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idp15744064"></a><p><span class="citetitle"><em class="citetitle">
-+ </p></li></ul></div></div><div class="bibliography"><div class="titlepage"><div><div><h4 class="title"><a id="locales.locale.biblio"></a>Bibliography</h4></div></div></div><div class="biblioentry"><a id="idm269999787232"></a><p><span class="citetitle"><em class="citetitle">
- The GNU C Library
- </em>. </span><span class="author"><span class="firstname">Roland</span> <span class="surname">McGrath</span>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2007 FSF. </span><span class="pagenums">
- Chapters 6 Character Set Handling and 7 Locales and
- Internationalization
-- . </span></p></div><div class="biblioentry"><a id="idp15748832"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></p></div><div class="biblioentry"><a id="idm269999782464"></a><p><span class="citetitle"><em class="citetitle">
- Correspondence
-- </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idp15751920"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="author"><span class="firstname">Ulrich</span> <span class="surname">Drepper</span>. </span><span class="copyright">Copyright © 2002 . </span></p></div><div class="biblioentry"><a id="idm269999779376"></a><p><span class="citetitle"><em class="citetitle">
- ISO/IEC 14882:1998 Programming languages - C++
-- </em>. </span><span class="copyright">Copyright © 1998 ISO. </span></p></div><div class="biblioentry"><a id="idp15754208"></a><p><span class="citetitle"><em class="citetitle">
-+ </em>. </span><span class="copyright">Copyright © 1998 ISO. </span></p></div><div class="biblioentry"><a id="idm269999777088"></a><p><span class="citetitle"><em class="citetitle">
- ISO/IEC 9899:1999 Programming languages - C
-- </em>. </span><span class="copyright">Copyright © 1999 ISO. </span></p></div><div class="biblioentry"><a id="idp15756480"></a><p><span class="title"><em>
-+ </em>. </span><span class="copyright">Copyright © 1999 ISO. </span></p></div><div class="biblioentry"><a id="idm269999774816"></a><p><span class="title"><em>
- <a class="link" href="http://www.opengroup.org/austin/" target="_top">
- System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
- </a>
-@@ -420,11 +420,11 @@
- </em>. </span><span class="copyright">Copyright © 2008
- The Open Group/The Institute of Electrical and Electronics
- Engineers, Inc.
-- . </span></p></div><div class="biblioentry"><a id="idp15759712"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></p></div><div class="biblioentry"><a id="idm269999771584"></a><p><span class="citetitle"><em class="citetitle">
- The C++ Programming Language, Special Edition
- </em>. </span><span class="author"><span class="firstname">Bjarne</span> <span class="surname">Stroustrup</span>. </span><span class="copyright">Copyright © 2000 Addison Wesley, Inc.. </span><span class="pagenums">Appendix D. </span><span class="publisher"><span class="publishername">
- Addison Wesley
-- . </span></span></p></div><div class="biblioentry"><a id="idp15764336"></a><p><span class="citetitle"><em class="citetitle">
-+ . </span></span></p></div><div class="biblioentry"><a id="idm269999766960"></a><p><span class="citetitle"><em class="citetitle">
- Standard C++ IOStreams and Locales
- </em>. </span><span class="subtitle">
- Advanced Programmer's Guide and Reference
-Index: libstdc++-v3/doc/html/manual/ext_algorithms.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/ext_algorithms.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/ext_algorithms.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 25. Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_utilities.html" title="Chapter 24. Utilities" /><link rel="next" href="ext_numerics.html" title="Chapter 26. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 25. Algorithms</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_utilities.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 25. Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_utilities.html" title="Chapter 24. Utilities" /><link rel="next" href="ext_numerics.html" title="Chapter 26. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 25. Algorithms</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_utilities.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
- </th><td width="20%" align="right"> <a accesskey="n" href="ext_numerics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.algorithms"></a>Chapter 25. Algorithms</h2></div></div></div><p>25.1.6 (count, count_if) is extended with two more versions of count
-Index: libstdc++-v3/doc/html/manual/debug_mode.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/debug_mode.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/debug_mode.html (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 17. Debug Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /><link rel="next" href="debug_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 17. Debug Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_compile_checks.html">Prev</a> </td><th width="60%" align="center">Part III. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 17. Debug Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /><link rel="next" href="debug_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 17. Debug Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_compile_checks.html">Prev</a> </td><th width="60%" align="center">Part III. 
- Extensions
-
--</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.debug_mode"></a>Chapter 17. Debug Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and
-+</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.debug_mode"></a>Chapter 17. Debug Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and
- debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.alt">Alternatives for Coexistence</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.other">Other Implementations</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.intro"></a>Intro</h2></div></div></div><p>
- By default, libstdc++ is built with efficiency in mind, and
- therefore performs little or no error checking that is not
-Index: libstdc++-v3/doc/html/manual/profile_mode_design.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/profile_mode_design.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/profile_mode_design.html (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,6 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="next" href="profile_mode_api.html" title="Extensions for Custom Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.design"></a>Design</h2></div></div></div><p>
--</p><div class="table"><a id="idp16981200"></a><p class="title"><strong>Table 19.1. Profile Code Location</strong></p><div class="table-contents"><table summary="Profile Code Location" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Code Location</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><code class="code">libstdc++-v3/include/std/*</code></td><td align="left">Preprocessor code to redirect to profile extension headers.</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/*</code></td><td align="left">Profile extension public headers (map, vector, ...).</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/impl/*</code></td><td align="left">Profile extension internals. Implementation files are
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="next" href="profile_mode_api.html" title="Extensions for Custom Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.design"></a>Design</h2></div></div></div><p>
-+</p><div class="table"><a id="idm269998550064"></a><p class="title"><strong>Table 19.1. Profile Code Location</strong></p><div class="table-contents"><table summary="Profile Code Location" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Code Location</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><code class="code">libstdc++-v3/include/std/*</code></td><td align="left">Preprocessor code to redirect to profile extension headers.</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/*</code></td><td align="left">Profile extension public headers (map, vector, ...).</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/impl/*</code></td><td align="left">Profile extension internals. Implementation files are
- only included from <code class="code">impl/profiler.h</code>, which is the only
- file included from the public headers.</td></tr></tbody></table></div></div><br class="table-break" /><p>
- </p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.design.wrapper"></a>Wrapper Model</h3></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/using_concurrency.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/using_concurrency.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/using_concurrency.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dynamic_or_shared.html" title="Linking" /><link rel="next" href="using_exceptions.html" title="Exceptions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dynamic_or_shared.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_exceptions.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.concurrency"></a>Concurrency</h2></div></div></div><p>This section discusses issues surrounding the proper compilation
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dynamic_or_shared.html" title="Linking" /><link rel="next" href="using_exceptions.html" title="Exceptions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dynamic_or_shared.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_exceptions.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.concurrency"></a>Concurrency</h2></div></div></div><p>This section discusses issues surrounding the proper compilation
- of multithreaded applications which use the Standard C++
- library. This information is GCC-specific since the C++
- standard does not address matters of multithreaded applications.
-Index: libstdc++-v3/doc/html/manual/mt_allocator_impl.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/mt_allocator_impl.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/mt_allocator_impl.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_design.html" title="Design Issues" /><link rel="next" href="mt_allocator_ex_single.html" title="Single Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_design.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_single.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.tune"></a>Tunable Parameters</h3></div></div></div><p>Certain allocation parameters can be modified, or tuned. There
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_design.html" title="Design Issues" /><link rel="next" href="mt_allocator_ex_single.html" title="Single Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_design.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_single.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.tune"></a>Tunable Parameters</h3></div></div></div><p>Certain allocation parameters can be modified, or tuned. There
- exists a nested <code class="code">struct __pool_base::_Tune</code> that contains all
- these parameters, which include settings for
- </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>Alignment</p></li><li class="listitem"><p>Maximum bytes before calling <code class="code">::operator new</code> directly</p></li><li class="listitem"><p>Minimum bytes</p></li><li class="listitem"><p>Size of underlying global allocations</p></li><li class="listitem"><p>Maximum number of supported threads</p></li><li class="listitem"><p>Migration of deallocations to the global free list</p></li><li class="listitem"><p>Shunt for global <code class="code">new</code> and <code class="code">delete</code></p></li></ul></div><p>Adjusting parameters for a given instance of an allocator can only
-Index: libstdc++-v3/doc/html/manual/appendix_gfdl.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/appendix_gfdl.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/appendix_gfdl.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix E. GNU Free Documentation License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix_gpl.html" title="Appendix D.  GNU General Public License version 3" /><link rel="next" href="../bk02.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix E. GNU Free Documentation License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_gpl.html">Prev</a> </td><th width="60%" align="center">Part IV. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix E. GNU Free Documentation License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix_gpl.html" title="Appendix D.  GNU General Public License version 3" /><link rel="next" href="../bk02.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix E. GNU Free Documentation License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_gpl.html">Prev</a> </td><th width="60%" align="center">Part IV. 
- Appendices
- </th><td width="20%" align="right"> <a accesskey="n" href="../bk02.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.gfdl-1.3"></a>GNU Free Documentation License</h1></div></div></div><p>Version 1.3, 3 November 2008</p><p>
- Copyright © 2000, 2001, 2002, 2007, 2008
-Index: libstdc++-v3/doc/html/manual/containers.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/containers.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/containers.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 9.  Containers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="facets.html" title="Facets" /><link rel="next" href="associative.html" title="Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 9. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 9.  Containers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="facets.html" title="Facets" /><link rel="next" href="associative.html" title="Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 9. 
- Containers
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="facets.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="associative.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.containers"></a>Chapter 9. 
- Containers
-- <a id="idp16037808" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p>
-+ <a id="idm269999493408" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p>
- Yes it is, and that's okay. This is a decision that we preserved
- when we imported SGI's STL implementation. The following is
- quoted from <a class="link" href="http://www.sgi.com/tech/stl/FAQ.html" target="_top">their FAQ</a>:
-Index: libstdc++-v3/doc/html/manual/io.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/io.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/io.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 13.  Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="numerics_and_c.html" title="Interacting with C" /><link rel="next" href="streambufs.html" title="Stream Buffers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 13. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 13.  Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="numerics_and_c.html" title="Interacting with C" /><link rel="next" href="streambufs.html" title="Stream Buffers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 13. 
- Input and Output
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="numerics_and_c.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="streambufs.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.io"></a>Chapter 13. 
- Input and Output
-- <a id="idp16257600" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="io.html#std.io.objects">Iostream Objects</a></span></dt><dt><span class="section"><a href="streambufs.html">Stream Buffers</a></span></dt><dd><dl><dt><span class="section"><a href="streambufs.html#io.streambuf.derived">Derived streambuf Classes</a></span></dt><dt><span class="section"><a href="streambufs.html#io.streambuf.buffering">Buffering</a></span></dt></dl></dd><dt><span class="section"><a href="stringstreams.html">Memory Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="stringstreams.html#std.io.memstreams.compat">Compatibility With strstream</a></span></dt></dl></dd><dt><span class="section"><a href="fstreams.html">File Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="fstreams.html#std.io.filestreams.copying_a_file">Copying a File</a></span></dt><dt><span class="section"><a href="fstreams.html#std.io.filestreams.binary">Binary Input and Output</a></span></dt></dl></dd><dt><span class="section"><a href="io_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="io_and_c.html#std.io.c.FILE">Using FILE* and file descriptors</a></span></dt><dt><span class="section"><a href="io_and_c.html#std.io.c.sync">Performance</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.objects"></a>Iostream Objects</h2></div></div></div><p>To minimize the time you have to wait on the compiler, it's good to
-+ <a id="idm269999273616" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="io.html#std.io.objects">Iostream Objects</a></span></dt><dt><span class="section"><a href="streambufs.html">Stream Buffers</a></span></dt><dd><dl><dt><span class="section"><a href="streambufs.html#io.streambuf.derived">Derived streambuf Classes</a></span></dt><dt><span class="section"><a href="streambufs.html#io.streambuf.buffering">Buffering</a></span></dt></dl></dd><dt><span class="section"><a href="stringstreams.html">Memory Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="stringstreams.html#std.io.memstreams.compat">Compatibility With strstream</a></span></dt></dl></dd><dt><span class="section"><a href="fstreams.html">File Based Streams</a></span></dt><dd><dl><dt><span class="section"><a href="fstreams.html#std.io.filestreams.copying_a_file">Copying a File</a></span></dt><dt><span class="section"><a href="fstreams.html#std.io.filestreams.binary">Binary Input and Output</a></span></dt></dl></dd><dt><span class="section"><a href="io_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="io_and_c.html#std.io.c.FILE">Using FILE* and file descriptors</a></span></dt><dt><span class="section"><a href="io_and_c.html#std.io.c.sync">Performance</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.objects"></a>Iostream Objects</h2></div></div></div><p>To minimize the time you have to wait on the compiler, it's good to
- only include the headers you really need. Many people simply include
- &lt;iostream&gt; when they don't need to -- and that can <span class="emphasis"><em>penalize
- your runtime as well.</em></span> Here are some tips on which header to use
-Index: libstdc++-v3/doc/html/manual/index.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/index.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/index.html (.../branches/gcc-4_8-branch)
-@@ -1,7 +1,7 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library Manual</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="../index.html" title="The GNU C++ Library" /><link rel="prev" href="../index.html" title="The GNU C++ Library" /><link rel="next" href="intro.html" title="Part I.  Introduction" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library Manual</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><div><div><h1 class="title"><a id="manual"></a>The GNU C++ Library Manual</h1></div><div><div class="authorgroup"><div class="author"><h3 class="author"><span class="firstname"></span> <span class="surname"></span></h3></div><div class="author"><h3 class="author"><span class="firstname">Paolo</span> <span class="surname">Carlini</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Phil</span> <span class="surname">Edwards</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Doug</span> <span class="surname">Gregor</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Dhruv</span> <span class="surname">Matani</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jason</span> <span class="surname">Merrill</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Mark</span> <span class="surname">Mitchell</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Nathan</span> <span class="surname">Myers</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Felix</span> <span class="surname">Natter</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Stefan</span> <span class="surname">Olsson</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Ami</span> <span class="surname">Tavory</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jonathan</span> <span class="surname">Wakely</span></h3></div></div></div><div><p class="copyright">Copyright © 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library Manual</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="../index.html" title="The GNU C++ Library" /><link rel="prev" href="../index.html" title="The GNU C++ Library" /><link rel="next" href="intro.html" title="Part I.  Introduction" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library Manual</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><div><div><h1 class="title"><a id="manual"></a>The GNU C++ Library Manual</h1></div><div><div class="authorgroup"><div class="author"><h3 class="author"><span class="firstname"></span> <span class="surname"></span></h3></div><div class="author"><h3 class="author"><span class="firstname">Paolo</span> <span class="surname">Carlini</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Phil</span> <span class="surname">Edwards</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Doug</span> <span class="surname">Gregor</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Dhruv</span> <span class="surname">Matani</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jason</span> <span class="surname">Merrill</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Mark</span> <span class="surname">Mitchell</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Nathan</span> <span class="surname">Myers</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Felix</span> <span class="surname">Natter</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Stefan</span> <span class="surname">Olsson</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Ami</span> <span class="surname">Tavory</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jonathan</span> <span class="surname">Wakely</span></h3></div></div></div><div><p class="copyright">Copyright © 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
- <a class="link" href="http://www.fsf.org" target="_top">FSF</a>
-- </p></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="part"><a href="intro.html">I.
-+ </p></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="part"><a href="intro.html">I.
- Introduction
-
- </a></span></dt><dd><dl><dt><span class="chapter"><a href="status.html">1. Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="setup.html">2. Setup</a></span></dt><dd><dl><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></dd><dt><span class="chapter"><a href="using.html">3. Using</a></span></dt><dd><dl><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="part"><a href="std_contents.html">II.
-@@ -15,13 +15,13 @@
- </a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.api">API Reference</a></span></dt><dt><span class="section"><a href="diagnostics.html#std.diagnostics.exceptions.data">Adding Data to <code class="classname">exception</code></a></span></dt></dl></dd><dt><span class="section"><a href="concept_checking.html">Concept Checking</a></span></dt></dl></dd><dt><span class="chapter"><a href="utilities.html">6.
- Utilities
-
--</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp13920976">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idp13924528">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp13937824">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15512272">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idp15534784">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idp15542080">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp15556704">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15573056">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idp15576640">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.
-+</a></span></dt><dd><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></dd><dt><span class="chapter"><a href="strings.html">7.
- Strings
-
- </a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#std.strings.string">String Classes</a></span></dt><dd><dl><dt><span class="section"><a href="strings.html#strings.string.simple">Simple Transformations</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.case">Case Sensitivity</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.character_types">Arbitrary Character Types</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.token">Tokenizing</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.shrink">Shrink to Fit</a></span></dt><dt><span class="section"><a href="strings.html#strings.string.Cstring">CString (MFC)</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="localization.html">8.
- Localization
-
--</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idp15778336">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.
-+</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.
- Containers
-
- </a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.
-@@ -143,19 +143,19 @@
-
- </a></span></dt><dt><span class="appendix"><a href="appendix_gpl.html">D.
- <acronym class="acronym">GNU</acronym> General Public License version 3
-- </a></span></dt><dt><span class="appendix"><a href="appendix_gfdl.html">E. GNU Free Documentation License</a></span></dt></dl></dd></dl></div><div class="list-of-figures"><p><strong>List of Figures</strong></p><dl><dt>22.1. <a href="policy_data_structures.html#idp17613296">Node Invariants</a></dt><dt>22.2. <a href="policy_data_structures.html#idp17619952">Underlying Associative Data Structures</a></dt><dt>22.3. <a href="policy_data_structures.html#idp17651648">Range Iteration in Different Data Structures</a></dt><dt>22.4. <a href="policy_data_structures.html#idp17666528">Point Iteration in Hash Data Structures</a></dt><dt>22.5. <a href="policy_data_structures.html#idp17675840">Effect of erase in different underlying data structures</a></dt><dt>22.6. <a href="policy_data_structures.html#idp17743424">Underlying Priority Queue Data Structures</a></dt><dt>22.7. <a href="policy_data_structures_using.html#idp17806128">Exception Hierarchy</a></dt><dt>22.8. <a href="policy_data_structures_design.html#idp18000448">Non-unique Mapping Standard Containers</a></dt><dt>22.9. <a href="policy_data_structures_design.html#fig.pbds_embedded_lists_2">
-+ </a></span></dt><dt><span class="appendix"><a href="appendix_gfdl.html">E. GNU Free Documentation License</a></span></dt></dl></dd></dl></div><div class="list-of-figures"><p><strong>List of Figures</strong></p><dl><dt>22.1. <a href="policy_data_structures.html#idm269997917584">Node Invariants</a></dt><dt>22.2. <a href="policy_data_structures.html#idm269997910864">Underlying Associative Data Structures</a></dt><dt>22.3. <a href="policy_data_structures.html#idm269997879168">Range Iteration in Different Data Structures</a></dt><dt>22.4. <a href="policy_data_structures.html#idm269997864256">Point Iteration in Hash Data Structures</a></dt><dt>22.5. <a href="policy_data_structures.html#idm269997855056">Effect of erase in different underlying data structures</a></dt><dt>22.6. <a href="policy_data_structures.html#idm269997787392">Underlying Priority Queue Data Structures</a></dt><dt>22.7. <a href="policy_data_structures_using.html#idm269997724688">Exception Hierarchy</a></dt><dt>22.8. <a href="policy_data_structures_design.html#idm269997530416">Non-unique Mapping Standard Containers</a></dt><dt>22.9. <a href="policy_data_structures_design.html#fig.pbds_embedded_lists_2">
- Effect of embedded lists in
- <code class="classname">std::multimap</code>
-- </a></dt><dt>22.10. <a href="policy_data_structures_design.html#idp18023952">Non-unique Mapping Containers</a></dt><dt>22.11. <a href="policy_data_structures_design.html#idp18043824">Point Iterator Hierarchy</a></dt><dt>22.12. <a href="policy_data_structures_design.html#idp18057168">Invalidation Guarantee Tags Hierarchy</a></dt><dt>22.13. <a href="policy_data_structures_design.html#idp18087392">Container Tag Hierarchy</a></dt><dt>22.14. <a href="policy_data_structures_design.html#idp18127536">Hash functions, ranged-hash functions, and
-- range-hashing functions</a></dt><dt>22.15. <a href="policy_data_structures_design.html#idp18191968">Insert hash sequence diagram</a></dt><dt>22.16. <a href="policy_data_structures_design.html#idp18199024">Insert hash sequence diagram with a null policy</a></dt><dt>22.17. <a href="policy_data_structures_design.html#idp18215840">Hash policy class diagram</a></dt><dt>22.18. <a href="policy_data_structures_design.html#idp18234944">Balls and bins</a></dt><dt>22.19. <a href="policy_data_structures_design.html#idp18265728">Insert resize sequence diagram</a></dt><dt>22.20. <a href="policy_data_structures_design.html#idp18273504">Standard resize policy trigger sequence
-- diagram</a></dt><dt>22.21. <a href="policy_data_structures_design.html#idp18277664">Standard resize policy size sequence
-- diagram</a></dt><dt>22.22. <a href="policy_data_structures_design.html#idp18355696">Tree node invariants</a></dt><dt>22.23. <a href="policy_data_structures_design.html#idp18365136">Tree node invalidation</a></dt><dt>22.24. <a href="policy_data_structures_design.html#idp18378304">A tree and its update policy</a></dt><dt>22.25. <a href="policy_data_structures_design.html#idp18389968">Restoring node invariants</a></dt><dt>22.26. <a href="policy_data_structures_design.html#idp18398144">Insert update sequence</a></dt><dt>22.27. <a href="policy_data_structures_design.html#idp18420400">Useless update path</a></dt><dt>22.28. <a href="policy_data_structures_design.html#idp18465088">A PATRICIA trie</a></dt><dt>22.29. <a href="policy_data_structures_design.html#idp18475584">A trie and its update policy</a></dt><dt>22.30. <a href="policy_data_structures_design.html#idp18506160">A simple list</a></dt><dt>22.31. <a href="policy_data_structures_design.html#idp18511744">The counter algorithm</a></dt><dt>22.32. <a href="policy_data_structures_design.html#idp18575568">Underlying Priority-Queue Data-Structures.</a></dt><dt>22.33. <a href="policy_data_structures_design.html#idp18610544">Priority-Queue Data-Structure Tags.</a></dt><dt>B.1. <a href="appendix_porting.html#idp22035648">Configure and Build File Dependencies</a></dt></dl></div><div class="list-of-tables"><p><strong>List of Tables</strong></p><dl><dt>1.1. <a href="status.html#idp452240">C++ 1998/2003 Implementation Status</a></dt><dt>1.2. <a href="status.html#idp8670848">C++ 2011 Implementation Status</a></dt><dt>1.3. <a href="status.html#idp7483200">C++ TR1 Implementation Status</a></dt><dt>1.4. <a href="status.html#idp12559072">C++ TR 24733 Implementation Status</a></dt><dt>3.1. <a href="using.html#idp13051936">C++ Command Options</a></dt><dt>3.2. <a href="using_headers.html#idp13079360">C++ 1998 Library Headers</a></dt><dt>3.3. <a href="using_headers.html#idp13115840">C++ 1998 Library Headers for C Library Facilities</a></dt><dt>3.4. <a href="using_headers.html#idp13140576">C++ 2011 Library Headers</a></dt><dt>3.5. <a href="using_headers.html#idp13192016">C++ 2011 Library Headers for C Library Facilities</a></dt><dt>3.6. <a href="using_headers.html#idp13221904">C++ TR 1 Library Headers</a></dt><dt>3.7. <a href="using_headers.html#idp13238832">C++ TR 1 Library Headers for C Library Facilities</a></dt><dt>3.8. <a href="using_headers.html#idp13259904">C++ TR 24733 Decimal Floating-Point Header</a></dt><dt>3.9. <a href="using_headers.html#idp13265424">C++ ABI Headers</a></dt><dt>3.10. <a href="using_headers.html#idp13271824">Extension Headers</a></dt><dt>3.11. <a href="using_headers.html#idp13307552">Extension Debug Headers</a></dt><dt>3.12. <a href="using_headers.html#idp13322320">Extension Profile Headers</a></dt><dt>3.13. <a href="using_headers.html#idp13335696">Extension Parallel Headers</a></dt><dt>17.1. <a href="debug_mode_using.html#idp16490400">Debugging Containers</a></dt><dt>17.2. <a href="debug_mode_using.html#idp16535296">Debugging Containers C++11</a></dt><dt>18.1. <a href="parallel_mode_using.html#idp16725920">Parallel Algorithms</a></dt><dt>19.1. <a href="profile_mode_design.html#idp16981200">Profile Code Location</a></dt><dt>19.2. <a href="profile_mode_diagnostics.html#idp17088912">Profile Diagnostics</a></dt><dt>21.1. <a href="bitmap_allocator_impl.html#idp17500848">Bitmap Allocator Memory Map</a></dt><dt>B.1. <a href="documentation_hacking.html#idp22162432">Doxygen Prerequisites</a></dt><dt>B.2. <a href="documentation_hacking.html#idp22238096">HTML to Doxygen Markup Comparison</a></dt><dt>B.3. <a href="documentation_hacking.html#idp22257536">Docbook Prerequisites</a></dt><dt>B.4. <a href="documentation_hacking.html#idp22335040">HTML to Docbook XML Markup Comparison</a></dt><dt>B.5. <a href="documentation_hacking.html#idp22359184">Docbook XML Element Use</a></dt><dt>B.6. <a href="api.html#idp23030528">Extension Allocators</a></dt><dt>B.7. <a href="api.html#idp23058160">Extension Allocators Continued</a></dt></dl></div><div class="list-of-equations"><p><strong>List of Equations</strong></p><dl><dt>22.1. <a href="policy_data_structures_design.html#idp18141344">Ranged Hash Function</a></dt><dt>22.2. <a href="policy_data_structures_design.html#idp18147232">Range-Hashing, Division Method</a></dt><dt>22.3. <a href="policy_data_structures_design.html#idp18151744">Division via Prime Modulo</a></dt><dt>22.4. <a href="policy_data_structures_design.html#idp18153568">Division via Bit Mask</a></dt><dt>22.5. <a href="policy_data_structures_design.html#idp18163200">
-+ </a></dt><dt>22.10. <a href="policy_data_structures_design.html#idm269997506912">Non-unique Mapping Containers</a></dt><dt>22.11. <a href="policy_data_structures_design.html#idm269997487104">Point Iterator Hierarchy</a></dt><dt>22.12. <a href="policy_data_structures_design.html#idm269997473760">Invalidation Guarantee Tags Hierarchy</a></dt><dt>22.13. <a href="policy_data_structures_design.html#idm269997443664">Container Tag Hierarchy</a></dt><dt>22.14. <a href="policy_data_structures_design.html#idm269997403584">Hash functions, ranged-hash functions, and
-+ range-hashing functions</a></dt><dt>22.15. <a href="policy_data_structures_design.html#idm269997339216">Insert hash sequence diagram</a></dt><dt>22.16. <a href="policy_data_structures_design.html#idm269997332160">Insert hash sequence diagram with a null policy</a></dt><dt>22.17. <a href="policy_data_structures_design.html#idm269997315408">Hash policy class diagram</a></dt><dt>22.18. <a href="policy_data_structures_design.html#idm269997296368">Balls and bins</a></dt><dt>22.19. <a href="policy_data_structures_design.html#idm269997265648">Insert resize sequence diagram</a></dt><dt>22.20. <a href="policy_data_structures_design.html#idm269997257872">Standard resize policy trigger sequence
-+ diagram</a></dt><dt>22.21. <a href="policy_data_structures_design.html#idm269997253712">Standard resize policy size sequence
-+ diagram</a></dt><dt>22.22. <a href="policy_data_structures_design.html#idm269997175616">Tree node invariants</a></dt><dt>22.23. <a href="policy_data_structures_design.html#idm269997166176">Tree node invalidation</a></dt><dt>22.24. <a href="policy_data_structures_design.html#idm269997153072">A tree and its update policy</a></dt><dt>22.25. <a href="policy_data_structures_design.html#idm269997141408">Restoring node invariants</a></dt><dt>22.26. <a href="policy_data_structures_design.html#idm269997133232">Insert update sequence</a></dt><dt>22.27. <a href="policy_data_structures_design.html#idm269997110976">Useless update path</a></dt><dt>22.28. <a href="policy_data_structures_design.html#idm269997066288">A PATRICIA trie</a></dt><dt>22.29. <a href="policy_data_structures_design.html#idm269997055856">A trie and its update policy</a></dt><dt>22.30. <a href="policy_data_structures_design.html#idm269997025344">A simple list</a></dt><dt>22.31. <a href="policy_data_structures_design.html#idm269997019760">The counter algorithm</a></dt><dt>22.32. <a href="policy_data_structures_design.html#idm269996955920">Underlying Priority-Queue Data-Structures.</a></dt><dt>22.33. <a href="policy_data_structures_design.html#idm269996920880">Priority-Queue Data-Structure Tags.</a></dt><dt>B.1. <a href="appendix_porting.html#idm269993497120">Configure and Build File Dependencies</a></dt></dl></div><div class="list-of-tables"><p><strong>List of Tables</strong></p><dl><dt>1.1. <a href="status.html#idm270008034928">C++ 1998/2003 Implementation Status</a></dt><dt>1.2. <a href="status.html#idm270007982624">C++ 2011 Implementation Status</a></dt><dt>1.3. <a href="status.html#idm270006687472">C++ TR1 Implementation Status</a></dt><dt>1.4. <a href="status.html#idm270002960368">C++ TR 24733 Implementation Status</a></dt><dt>3.1. <a href="using.html#idm270002481088">C++ Command Options</a></dt><dt>3.2. <a href="using_headers.html#idm270002453792">C++ 1998 Library Headers</a></dt><dt>3.3. <a href="using_headers.html#idm270002417312">C++ 1998 Library Headers for C Library Facilities</a></dt><dt>3.4. <a href="using_headers.html#idm270002392576">C++ 2011 Library Headers</a></dt><dt>3.5. <a href="using_headers.html#idm270002341136">C++ 2011 Library Headers for C Library Facilities</a></dt><dt>3.6. <a href="using_headers.html#idm270002311248">C++ TR 1 Library Headers</a></dt><dt>3.7. <a href="using_headers.html#idm270002294320">C++ TR 1 Library Headers for C Library Facilities</a></dt><dt>3.8. <a href="using_headers.html#idm270002273248">C++ TR 24733 Decimal Floating-Point Header</a></dt><dt>3.9. <a href="using_headers.html#idm270002267728">C++ ABI Headers</a></dt><dt>3.10. <a href="using_headers.html#idm270002261328">Extension Headers</a></dt><dt>3.11. <a href="using_headers.html#idm270002225600">Extension Debug Headers</a></dt><dt>3.12. <a href="using_headers.html#idm270002210832">Extension Profile Headers</a></dt><dt>3.13. <a href="using_headers.html#idm270002197456">Extension Parallel Headers</a></dt><dt>17.1. <a href="debug_mode_using.html#idm269999040896">Debugging Containers</a></dt><dt>17.2. <a href="debug_mode_using.html#idm269998996000">Debugging Containers C++11</a></dt><dt>18.1. <a href="parallel_mode_using.html#idm269998805216">Parallel Algorithms</a></dt><dt>19.1. <a href="profile_mode_design.html#idm269998550064">Profile Code Location</a></dt><dt>19.2. <a href="profile_mode_diagnostics.html#idm269998442544">Profile Diagnostics</a></dt><dt>21.1. <a href="bitmap_allocator_impl.html#idm269998030352">Bitmap Allocator Memory Map</a></dt><dt>B.1. <a href="documentation_hacking.html#idm269993370272">Doxygen Prerequisites</a></dt><dt>B.2. <a href="documentation_hacking.html#idm269993294592">HTML to Doxygen Markup Comparison</a></dt><dt>B.3. <a href="documentation_hacking.html#idm269993275152">Docbook Prerequisites</a></dt><dt>B.4. <a href="documentation_hacking.html#idm269993197520">HTML to Docbook XML Markup Comparison</a></dt><dt>B.5. <a href="documentation_hacking.html#idm269993173376">Docbook XML Element Use</a></dt><dt>B.6. <a href="api.html#idm269992502096">Extension Allocators</a></dt><dt>B.7. <a href="api.html#idm269992474464">Extension Allocators Continued</a></dt></dl></div><div class="list-of-equations"><p><strong>List of Equations</strong></p><dl><dt>22.1. <a href="policy_data_structures_design.html#idm269997389776">Ranged Hash Function</a></dt><dt>22.2. <a href="policy_data_structures_design.html#idm269997383888">Range-Hashing, Division Method</a></dt><dt>22.3. <a href="policy_data_structures_design.html#idm269997379376">Division via Prime Modulo</a></dt><dt>22.4. <a href="policy_data_structures_design.html#idm269997377552">Division via Bit Mask</a></dt><dt>22.5. <a href="policy_data_structures_design.html#idm269997367984">
- A Standard String Hash Function
-- </a></dt><dt>22.6. <a href="policy_data_structures_design.html#idp18169344">
-+ </a></dt><dt>22.6. <a href="policy_data_structures_design.html#idm269997361840">
- Only k String DNA Hash
-- </a></dt><dt>22.7. <a href="policy_data_structures_design.html#idp18240448">
-+ </a></dt><dt>22.7. <a href="policy_data_structures_design.html#idm269997290864">
- Probability of Probe Sequence of Length k
-- </a></dt><dt>22.8. <a href="policy_data_structures_design.html#idp18247216">
-+ </a></dt><dt>22.8. <a href="policy_data_structures_design.html#idm269997284096">
- Probability Probe Sequence in Some Bin
- </a></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Part I. 
- Introduction
-Index: libstdc++-v3/doc/html/manual/numerics_and_c.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/numerics_and_c.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/numerics_and_c.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="prev" href="generalized_numeric_operations.html" title="Generalized Operations" /><link rel="next" href="io.html" title="Chapter 13.  Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="generalized_numeric_operations.html">Prev</a> </td><th width="60%" align="center">Chapter 12. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="prev" href="generalized_numeric_operations.html" title="Generalized Operations" /><link rel="next" href="io.html" title="Chapter 13.  Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="generalized_numeric_operations.html">Prev</a> </td><th width="60%" align="center">Chapter 12. 
- Numerics
-
- </th><td width="20%" align="right"> <a accesskey="n" href="io.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="numerics.c.array"></a>Numerics vs. Arrays</h3></div></div></div><p>One of the major reasons why FORTRAN can chew through numbers so well
-Index: libstdc++-v3/doc/html/manual/appendix_gpl.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/appendix_gpl.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/appendix_gpl.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix D.  GNU General Public License version 3</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix_free.html" title="Appendix C.  Free Software Needs Free Documentation" /><link rel="next" href="appendix_gfdl.html" title="Appendix E. GNU Free Documentation License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix D. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix D.  GNU General Public License version 3</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix_free.html" title="Appendix C.  Free Software Needs Free Documentation" /><link rel="next" href="appendix_gfdl.html" title="Appendix E. GNU Free Documentation License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix D. 
- <acronym class="acronym">GNU</acronym> General Public License version 3
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_free.html">Prev</a> </td><th width="60%" align="center">Part IV. 
- Appendices
-@@ -77,7 +77,7 @@
- </p><p>
- The precise terms and conditions for copying, distribution and modification
- follow.
-- </p><h2><a id="idp23466384"></a>
-+ </p><h2><a id="idm269992066368"></a>
- TERMS AND CONDITIONS
- </h2><h2><a id="gpl-3-definitions"></a>
- 0. Definitions.
-@@ -618,7 +618,7 @@
- waiver of all civil liability in connection with the Program, unless a
- warranty or assumption of liability accompanies a copy of the Program in
- return for a fee.
-- </p><h2><a id="idp23565184"></a>
-+ </p><h2><a id="idm269991967568"></a>
- END OF TERMS AND CONDITIONS
- </h2><h2><a id="HowToApply"></a>
- How to Apply These Terms to Your New Programs
-Index: libstdc++-v3/doc/html/manual/source_code_style.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/source_code_style.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/source_code_style.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Coding Style</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="source_organization.html" title="Directory Layout and Source Conventions" /><link rel="next" href="source_design_notes.html" title="Design Notes" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Coding Style</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_organization.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Coding Style</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="source_organization.html" title="Directory Layout and Source Conventions" /><link rel="next" href="source_design_notes.html" title="Design Notes" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Coding Style</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_organization.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
- Contributing
-
- </th><td width="20%" align="right"> <a accesskey="n" href="source_design_notes.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.coding_style"></a>Coding Style</h2></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/streambufs.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/streambufs.html (.../tags/gcc_4_8_2_release)
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-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Stream Buffers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="io.html" title="Chapter 13.  Input and Output" /><link rel="next" href="stringstreams.html" title="Memory Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Stream Buffers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Stream Buffers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="io.html" title="Chapter 13.  Input and Output" /><link rel="next" href="stringstreams.html" title="Memory Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Stream Buffers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
- Input and Output
-
- </th><td width="20%" align="right"> <a accesskey="n" href="stringstreams.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.streambufs"></a>Stream Buffers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="io.streambuf.derived"></a>Derived streambuf Classes</h3></div></div></div><p>
-Index: libstdc++-v3/doc/html/manual/utilities.html
-===================================================================
---- a/src/libstdc++-v3/doc/html/manual/utilities.html (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/doc/html/manual/utilities.html (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
--<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 6.  Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.77.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="concept_checking.html" title="Concept Checking" /><link rel="next" href="pairs.html" title="Pairs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 6. 
-+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 6.  Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="concept_checking.html" title="Concept Checking" /><link rel="next" href="pairs.html" title="Pairs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 6. 
- Utilities
-
- </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="concept_checking.html">Prev</a> </td><th width="60%" align="center">Part II. 
-@@ -6,8 +6,8 @@
- Standard Contents
- </th><td width="20%" align="right"> <a accesskey="n" href="pairs.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.util"></a>Chapter 6. 
- Utilities
-- <a id="idp13862416" class="indexterm"></a>
--</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp13920976">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idp13924528">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp13937824">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15512272">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idp15534784">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idp15542080">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idp15556704">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idp15573056">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idp15576640">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.functors"></a>Functors</h2></div></div></div><p>If you don't know what functors are, you're not alone. Many people
-+ <a id="idm270001670464" class="indexterm"></a>
-+</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="utilities.html#std.util.functors">Functors</a></span></dt><dt><span class="section"><a href="pairs.html">Pairs</a></span></dt><dt><span class="section"><a href="memory.html">Memory</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#std.util.memory.allocator">Allocators</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#allocator.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#allocator.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#allocator.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270001611968">Interface Design</a></span></dt><dt><span class="section"><a href="memory.html#idm270001608416">Selecting Default Allocation Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm270001595120">Disabling Memory Caching</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#allocator.using">Using a Specific Allocator</a></span></dt><dt><span class="section"><a href="memory.html#allocator.custom">Custom Allocators</a></span></dt><dt><span class="section"><a href="memory.html#allocator.ext">Extension Allocators</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.auto_ptr">auto_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#auto_ptr.limitations">Limitations</a></span></dt><dt><span class="section"><a href="memory.html#auto_ptr.using">Use in Containers</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#std.util.memory.shared_ptr">shared_ptr</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#shared_ptr.req">Requirements</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.design_issues">Design Issues</a></span></dt><dt><span class="section"><a href="memory.html#shared_ptr.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm270000019344">Class Hierarchy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999996832">Thread Safety</a></span></dt><dt><span class="section"><a href="memory.html#idm269999989536">Selecting Lock Policy</a></span></dt><dt><span class="section"><a href="memory.html#idm269999974912">Related functions and classes</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.using">Use</a></span></dt><dd><dl><dt><span class="section"><a href="memory.html#idm269999958496">Examples</a></span></dt><dt><span class="section"><a href="memory.html#idm269999954912">Unresolved Issues</a></span></dt></dl></dd><dt><span class="section"><a href="memory.html#shared_ptr.ack">Acknowledgments</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="traits.html">Traits</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.functors"></a>Functors</h2></div></div></div><p>If you don't know what functors are, you're not alone. Many people
- get slightly the wrong idea. In the interest of not reinventing
- the wheel, we will refer you to the introduction to the functor
- concept written by SGI as part of their STL, in
-Index: libstdc++-v3/include/debug/functions.h
-===================================================================
---- a/src/libstdc++-v3/include/debug/functions.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/debug/functions.h (.../branches/gcc-4_8-branch)
-@@ -345,11 +345,13 @@
- return __check_sorted_set_aux(__first, __last, __pred, _SameType());
- }
-
-+ // _GLIBCXX_RESOLVE_LIB_DEFECTS
-+ // 270. Binary search requirements overly strict
-+ // Determine if a sequence is partitioned w.r.t. this element.
- template<typename _ForwardIterator, typename _Tp>
- inline bool
-- __check_partitioned_lower_aux(_ForwardIterator __first,
-- _ForwardIterator __last, const _Tp& __value,
-- std::forward_iterator_tag)
-+ __check_partitioned_lower(_ForwardIterator __first,
-+ _ForwardIterator __last, const _Tp& __value)
- {
- while (__first != __last && *__first < __value)
- ++__first;
-@@ -362,38 +364,11 @@
- return __first == __last;
- }
-
-- // For performance reason, as the iterator range has been validated, check on
-- // random access safe iterators is done using the base iterator.
-- template<typename _Iterator, typename _Sequence, typename _Tp>
-- inline bool
-- __check_partitioned_lower_aux(
-- const _Safe_iterator<_Iterator, _Sequence>& __first,
-- const _Safe_iterator<_Iterator, _Sequence>& __last,
-- const _Tp& __value,
-- std::random_access_iterator_tag __tag)
-- {
-- return __check_partitioned_lower_aux(__first.base(), __last.base(),
-- __value, __tag);
-- }
--
-- // _GLIBCXX_RESOLVE_LIB_DEFECTS
-- // 270. Binary search requirements overly strict
-- // Determine if a sequence is partitioned w.r.t. this element.
- template<typename _ForwardIterator, typename _Tp>
- inline bool
-- __check_partitioned_lower(_ForwardIterator __first,
-+ __check_partitioned_upper(_ForwardIterator __first,
- _ForwardIterator __last, const _Tp& __value)
- {
-- return __check_partitioned_lower_aux(__first, __last, __value,
-- std::__iterator_category(__first));
-- }
--
-- template<typename _ForwardIterator, typename _Tp>
-- inline bool
-- __check_partitioned_upper_aux(_ForwardIterator __first,
-- _ForwardIterator __last, const _Tp& __value,
-- std::forward_iterator_tag)
-- {
- while (__first != __last && !(__value < *__first))
- ++__first;
- if (__first != __last)
-@@ -405,35 +380,12 @@
- return __first == __last;
- }
-
-- // For performance reason, as the iterator range has been validated, check on
-- // random access safe iterators is done using the base iterator.
-- template<typename _Iterator, typename _Sequence, typename _Tp>
-- inline bool
-- __check_partitioned_upper_aux(
-- const _Safe_iterator<_Iterator, _Sequence>& __first,
-- const _Safe_iterator<_Iterator, _Sequence>& __last,
-- const _Tp& __value,
-- std::random_access_iterator_tag __tag)
-- {
-- return __check_partitioned_upper_aux(__first.base(), __last.base(),
-- __value, __tag);
-- }
--
-- template<typename _ForwardIterator, typename _Tp>
-- inline bool
-- __check_partitioned_upper(_ForwardIterator __first,
-- _ForwardIterator __last, const _Tp& __value)
-- {
-- return __check_partitioned_upper_aux(__first, __last, __value,
-- std::__iterator_category(__first));
-- }
--
-+ // Determine if a sequence is partitioned w.r.t. this element.
- template<typename _ForwardIterator, typename _Tp, typename _Pred>
- inline bool
-- __check_partitioned_lower_aux(_ForwardIterator __first,
-- _ForwardIterator __last, const _Tp& __value,
-- _Pred __pred,
-- std::forward_iterator_tag)
-+ __check_partitioned_lower(_ForwardIterator __first,
-+ _ForwardIterator __last, const _Tp& __value,
-+ _Pred __pred)
- {
- while (__first != __last && bool(__pred(*__first, __value)))
- ++__first;
-@@ -446,39 +398,12 @@
- return __first == __last;
- }
-
-- // For performance reason, as the iterator range has been validated, check on
-- // random access safe iterators is done using the base iterator.
-- template<typename _Iterator, typename _Sequence,
-- typename _Tp, typename _Pred>
-- inline bool
-- __check_partitioned_lower_aux(
-- const _Safe_iterator<_Iterator, _Sequence>& __first,
-- const _Safe_iterator<_Iterator, _Sequence>& __last,
-- const _Tp& __value, _Pred __pred,
-- std::random_access_iterator_tag __tag)
-- {
-- return __check_partitioned_lower_aux(__first.base(), __last.base(),
-- __value, __pred, __tag);
-- }
--
-- // Determine if a sequence is partitioned w.r.t. this element.
- template<typename _ForwardIterator, typename _Tp, typename _Pred>
- inline bool
-- __check_partitioned_lower(_ForwardIterator __first,
-+ __check_partitioned_upper(_ForwardIterator __first,
- _ForwardIterator __last, const _Tp& __value,
- _Pred __pred)
- {
-- return __check_partitioned_lower_aux(__first, __last, __value, __pred,
-- std::__iterator_category(__first));
-- }
--
-- template<typename _ForwardIterator, typename _Tp, typename _Pred>
-- inline bool
-- __check_partitioned_upper_aux(_ForwardIterator __first,
-- _ForwardIterator __last, const _Tp& __value,
-- _Pred __pred,
-- std::forward_iterator_tag)
-- {
- while (__first != __last && !bool(__pred(__value, *__first)))
- ++__first;
- if (__first != __last)
-@@ -490,31 +415,6 @@
- return __first == __last;
- }
-
-- // For performance reason, as the iterator range has been validated, check on
-- // random access safe iterators is done using the base iterator.
-- template<typename _Iterator, typename _Sequence,
-- typename _Tp, typename _Pred>
-- inline bool
-- __check_partitioned_upper_aux(
-- const _Safe_iterator<_Iterator, _Sequence>& __first,
-- const _Safe_iterator<_Iterator, _Sequence>& __last,
-- const _Tp& __value, _Pred __pred,
-- std::random_access_iterator_tag __tag)
-- {
-- return __check_partitioned_upper_aux(__first.base(), __last.base(),
-- __value, __pred, __tag);
-- }
--
-- template<typename _ForwardIterator, typename _Tp, typename _Pred>
-- inline bool
-- __check_partitioned_upper(_ForwardIterator __first,
-- _ForwardIterator __last, const _Tp& __value,
-- _Pred __pred)
-- {
-- return __check_partitioned_upper_aux(__first, __last, __value, __pred,
-- std::__iterator_category(__first));
-- }
--
- // Helper struct to detect random access safe iterators.
- template<typename _Iterator>
- struct __is_safe_random_iterator
-Index: libstdc++-v3/include/debug/safe_unordered_base.h
-===================================================================
---- a/src/libstdc++-v3/include/debug/safe_unordered_base.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/debug/safe_unordered_base.h (.../branches/gcc-4_8-branch)
-@@ -133,9 +133,19 @@
- protected:
- // Initialize with a version number of 1 and no iterators
- _Safe_unordered_container_base()
-- : _M_local_iterators(0), _M_const_local_iterators(0)
-+ : _M_local_iterators(nullptr), _M_const_local_iterators(nullptr)
- { }
-
-+ // Initialize with a version number of 1 and no iterators
-+ _Safe_unordered_container_base(const _Safe_unordered_container_base&)
-+ noexcept
-+ : _Safe_unordered_container_base() { }
-+
-+ _Safe_unordered_container_base(_Safe_unordered_container_base&& __x)
-+ noexcept
-+ : _Safe_unordered_container_base()
-+ { this->_M_swap(__x); }
-+
- /** Notify all iterators that reference this container that the
- container is being destroyed. */
- ~_Safe_unordered_container_base()
-Index: libstdc++-v3/include/debug/macros.h
-===================================================================
---- a/src/libstdc++-v3/include/debug/macros.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/debug/macros.h (.../branches/gcc-4_8-branch)
-@@ -261,8 +261,9 @@
- w.r.t. the value _Value. */
- #define __glibcxx_check_partitioned_lower(_First,_Last,_Value) \
- __glibcxx_check_valid_range(_First,_Last); \
--_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower(_First, _Last, \
-- _Value), \
-+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower( \
-+ __gnu_debug::__base(_First), \
-+ __gnu_debug::__base(_Last), _Value), \
- _M_message(__gnu_debug::__msg_unpartitioned) \
- ._M_iterator(_First, #_First) \
- ._M_iterator(_Last, #_Last) \
-@@ -270,8 +271,9 @@
-
- #define __glibcxx_check_partitioned_upper(_First,_Last,_Value) \
- __glibcxx_check_valid_range(_First,_Last); \
--_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper(_First, _Last, \
-- _Value), \
-+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper( \
-+ __gnu_debug::__base(_First), \
-+ __gnu_debug::__base(_Last), _Value), \
- _M_message(__gnu_debug::__msg_unpartitioned) \
- ._M_iterator(_First, #_First) \
- ._M_iterator(_Last, #_Last) \
-@@ -281,8 +283,9 @@
- w.r.t. the value _Value and predicate _Pred. */
- #define __glibcxx_check_partitioned_lower_pred(_First,_Last,_Value,_Pred) \
- __glibcxx_check_valid_range(_First,_Last); \
--_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower(_First, _Last, \
-- _Value, _Pred), \
-+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower( \
-+ __gnu_debug::__base(_First), \
-+ __gnu_debug::__base(_Last), _Value, _Pred), \
- _M_message(__gnu_debug::__msg_unpartitioned_pred) \
- ._M_iterator(_First, #_First) \
- ._M_iterator(_Last, #_Last) \
-@@ -293,8 +296,9 @@
- w.r.t. the value _Value and predicate _Pred. */
- #define __glibcxx_check_partitioned_upper_pred(_First,_Last,_Value,_Pred) \
- __glibcxx_check_valid_range(_First,_Last); \
--_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper(_First, _Last, \
-- _Value, _Pred), \
-+_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper( \
-+ __gnu_debug::__base(_First), \
-+ __gnu_debug::__base(_Last), _Value, _Pred), \
- _M_message(__gnu_debug::__msg_unpartitioned_pred) \
- ._M_iterator(_First, #_First) \
- ._M_iterator(_Last, #_Last) \
-Index: libstdc++-v3/include/std/iostream
-===================================================================
---- a/src/libstdc++-v3/include/std/iostream (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/std/iostream (.../branches/gcc-4_8-branch)
-@@ -48,13 +48,13 @@
- *
- * The &lt;iostream&gt; header declares the eight <em>standard stream
- * objects</em>. For other declarations, see
-- * http://gcc.gnu.org/onlinedocs/libstdc++/manual/bk01pt11ch24.html
-+ * http://gcc.gnu.org/onlinedocs/libstdc++/manual/io.html
- * and the @link iosfwd I/O forward declarations @endlink
- *
- * They are required by default to cooperate with the global C
- * library's @c FILE streams, and to be available during program
-- * startup and termination. For more information, see the HOWTO
-- * linked to above.
-+ * startup and termination. For more information, see the section of the
-+ * manual linked to above.
- */
- //@{
- extern istream cin; /// Linked to standard input
-Index: libstdc++-v3/include/std/tuple
-===================================================================
---- a/src/libstdc++-v3/include/std/tuple (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/std/tuple (.../branches/gcc-4_8-branch)
-@@ -755,7 +755,7 @@
- typename tuple_element<__i, tuple<_Elements...>>::type
- >::type
- get(tuple<_Elements...>& __t) noexcept
-- { return __get_helper<__i>(__t); }
-+ { return std::__get_helper<__i>(__t); }
-
- template<std::size_t __i, typename... _Elements>
- constexpr typename __add_c_ref<
-@@ -762,7 +762,7 @@
- typename tuple_element<__i, tuple<_Elements...>>::type
- >::type
- get(const tuple<_Elements...>& __t) noexcept
-- { return __get_helper<__i>(__t); }
-+ { return std::__get_helper<__i>(__t); }
-
- template<std::size_t __i, typename... _Elements>
- constexpr typename __add_r_ref<
-Index: libstdc++-v3/include/std/future
-===================================================================
---- a/src/libstdc++-v3/include/std/future (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/std/future (.../branches/gcc-4_8-branch)
-@@ -1261,9 +1261,11 @@
- struct __future_base::_Task_state<_Fn, _Alloc, _Res(_Args...)> final
- : __future_base::_Task_state_base<_Res(_Args...)>
- {
-- _Task_state(_Fn&& __fn, const _Alloc& __a)
-- : _Task_state_base<_Res(_Args...)>(__a), _M_impl(std::move(__fn), __a)
-- { }
-+ template<typename _Fn2>
-+ _Task_state(_Fn2&& __fn, const _Alloc& __a)
-+ : _Task_state_base<_Res(_Args...)>(__a),
-+ _M_impl(std::forward<_Fn2>(__fn), __a)
-+ { }
-
- private:
- virtual void
-@@ -1292,19 +1294,21 @@
-
- struct _Impl : _Alloc
- {
-- _Impl(_Fn&& __fn, const _Alloc& __a)
-- : _Alloc(__a), _M_fn(std::move(__fn)) { }
-+ template<typename _Fn2>
-+ _Impl(_Fn2&& __fn, const _Alloc& __a)
-+ : _Alloc(__a), _M_fn(std::forward<_Fn2>(__fn)) { }
- _Fn _M_fn;
- } _M_impl;
- };
-
-- template<typename _Signature, typename _Fn, typename _Alloc>
-- static shared_ptr<__future_base::_Task_state_base<_Signature>>
-- __create_task_state(_Fn&& __fn, const _Alloc& __a)
-- {
-- typedef __future_base::_Task_state<_Fn, _Alloc, _Signature> _State;
-- return std::allocate_shared<_State>(__a, std::move(__fn), __a);
-- }
-+ template<typename _Signature, typename _Fn, typename _Alloc>
-+ static shared_ptr<__future_base::_Task_state_base<_Signature>>
-+ __create_task_state(_Fn&& __fn, const _Alloc& __a)
-+ {
-+ typedef typename decay<_Fn>::type _Fn2;
-+ typedef __future_base::_Task_state<_Fn2, _Alloc, _Signature> _State;
-+ return std::allocate_shared<_State>(__a, std::forward<_Fn>(__fn), __a);
-+ }
-
- template<typename _Fn, typename _Alloc, typename _Res, typename... _Args>
- shared_ptr<__future_base::_Task_state_base<_Res(_Args...)>>
-@@ -1344,7 +1348,8 @@
- __constrain_pkgdtask<packaged_task, _Fn>::__type>
- explicit
- packaged_task(_Fn&& __fn)
-- : packaged_task(allocator_arg, std::allocator<int>(), std::move(__fn))
-+ : packaged_task(allocator_arg, std::allocator<int>(),
-+ std::forward<_Fn>(__fn))
- { }
-
- // _GLIBCXX_RESOLVE_LIB_DEFECTS
-Index: libstdc++-v3/include/std/functional
-===================================================================
---- a/src/libstdc++-v3/include/std/functional (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/std/functional (.../branches/gcc-4_8-branch)
-@@ -2181,8 +2181,15 @@
- using _Invoke = decltype(__callable_functor(std::declval<_Functor&>())
- (std::declval<_ArgTypes>()...) );
-
-+ // Used so the return type convertibility checks aren't done when
-+ // performing overload resolution for copy construction/assignment.
-+ template<typename _Tp>
-+ using _NotSelf = __not_<is_same<_Tp, function>>;
-+
- template<typename _Functor>
-- using _Callable = __check_func_return_type<_Invoke<_Functor>, _Res>;
-+ using _Callable
-+ = __and_<_NotSelf<_Functor>,
-+ __check_func_return_type<_Invoke<_Functor>, _Res>>;
-
- template<typename _Cond, typename _Tp>
- using _Requires = typename enable_if<_Cond::value, _Tp>::type;
-@@ -2323,7 +2330,7 @@
- * reference_wrapper<F>, this function will not throw.
- */
- template<typename _Functor>
-- _Requires<_Callable<_Functor>, function&>
-+ _Requires<_Callable<typename decay<_Functor>::type>, function&>
- operator=(_Functor&& __f)
- {
- function(std::forward<_Functor>(__f)).swap(*this);
-Index: libstdc++-v3/include/bits/atomic_base.h
-===================================================================
---- a/src/libstdc++-v3/include/bits/atomic_base.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/bits/atomic_base.h (.../branches/gcc-4_8-branch)
-@@ -764,11 +764,11 @@
-
- bool
- is_lock_free() const noexcept
-- { return __atomic_is_lock_free(_M_type_size(1), nullptr); }
-+ { return __atomic_is_lock_free(sizeof(__pointer_type), nullptr); }
-
- bool
- is_lock_free() const volatile noexcept
-- { return __atomic_is_lock_free(_M_type_size(1), nullptr); }
-+ { return __atomic_is_lock_free(sizeof(__pointer_type), nullptr); }
-
- void
- store(__pointer_type __p,
-Index: libstdc++-v3/include/bits/stl_vector.h
-===================================================================
---- a/src/libstdc++-v3/include/bits/stl_vector.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/bits/stl_vector.h (.../branches/gcc-4_8-branch)
-@@ -1361,7 +1361,8 @@
- void
- _M_move_assign(vector&& __x, std::true_type) noexcept
- {
-- const vector __tmp(std::move(*this));
-+ vector __tmp(get_allocator());
-+ this->_M_impl._M_swap_data(__tmp._M_impl);
- this->_M_impl._M_swap_data(__x._M_impl);
- if (_Alloc_traits::_S_propagate_on_move_assign())
- std::__alloc_on_move(_M_get_Tp_allocator(),
-Index: libstdc++-v3/include/bits/stl_algo.h
-===================================================================
---- a/src/libstdc++-v3/include/bits/stl_algo.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/bits/stl_algo.h (.../branches/gcc-4_8-branch)
-@@ -2279,7 +2279,7 @@
- _RandomAccessIterator __last)
- {
- _RandomAccessIterator __mid = __first + (__last - __first) / 2;
-- std::__move_median_to_first(__first, __first + 1, __mid, (__last - 2));
-+ std::__move_median_to_first(__first, __first + 1, __mid, __last - 1);
- return std::__unguarded_partition(__first + 1, __last, *__first);
- }
-
-@@ -2291,7 +2291,7 @@
- _RandomAccessIterator __last, _Compare __comp)
- {
- _RandomAccessIterator __mid = __first + (__last - __first) / 2;
-- std::__move_median_to_first(__first, __first + 1, __mid, (__last - 2),
-+ std::__move_median_to_first(__first, __first + 1, __mid, __last - 1,
- __comp);
- return std::__unguarded_partition(__first + 1, __last, *__first, __comp);
- }
-Index: libstdc++-v3/include/bits/shared_ptr_base.h
-===================================================================
---- a/src/libstdc++-v3/include/bits/shared_ptr_base.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/bits/shared_ptr_base.h (.../branches/gcc-4_8-branch)
-@@ -233,7 +233,7 @@
- _M_add_ref_lock()
- {
- // Perform lock-free add-if-not-zero operation.
-- _Atomic_word __count = _M_use_count;
-+ _Atomic_word __count = _M_get_use_count();
- do
- {
- if (__count == 0)
-@@ -391,7 +391,7 @@
- public:
- template<typename... _Args>
- _Sp_counted_ptr_inplace(_Alloc __a, _Args&&... __args)
-- : _M_impl(__a), _M_storage()
-+ : _M_impl(__a)
- {
- _M_impl._M_ptr = static_cast<_Tp*>(static_cast<void*>(&_M_storage));
- // _GLIBCXX_RESOLVE_LIB_DEFECTS
-@@ -819,7 +819,7 @@
- : _M_ptr(__r.get()), _M_refcount()
- {
- __glibcxx_function_requires(_ConvertibleConcept<_Tp1*, _Tp*>)
-- auto __tmp = std::__addressof(*__r.get());
-+ auto __tmp = __r.get();
- _M_refcount = __shared_count<_Lp>(std::move(__r));
- __enable_shared_from_this_helper(_M_refcount, __tmp, __tmp);
- }
-Index: libstdc++-v3/include/c_global/cstdio
-===================================================================
---- a/src/libstdc++-v3/include/c_global/cstdio (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/include/c_global/cstdio (.../branches/gcc-4_8-branch)
-@@ -69,6 +69,7 @@
- #undef ftell
- #undef fwrite
- #undef getc
-+#undef getchar
- #undef gets
- #undef perror
- #undef printf
-Index: libstdc++-v3/ChangeLog
-===================================================================
---- a/src/libstdc++-v3/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,200 @@
-+2014-05-08 Joshua Gay <jgay@gnu.org>
-+
-+ PR libstdc++/61117
-+ * doc/xml/faq.xml (faq.license.what_restrictions): Replace "open
-+ source" with "free software".
-+ * doc/html/faq.html: Likewise.
-+
-+2014-05-08 Jonathan Wakely <jwakely@redhat.com>
-+
-+ * include/std/iostream: Fix URL in comment.
-+ * src/c++98/ios_init.cc: Fix path in comment.
-+
-+2014-05-06 Jonathan Wakely <jwakely@redhat.com>
-+
-+ Backport from mainline
-+ 2014-04-15 Jonathan Wakely <jwakely@redhat.com>
-+
-+ PR libstdc++/60594
-+ * include/std/functional (function::_Callable): Exclude own type
-+ from the callable checks.
-+ * testsuite/20_util/function/60594.cc: New.
-+
-+2014-04-27 Jonathan Wakely <jwakely@redhat.com>
-+
-+ PR libstdc++/60497
-+ * include/std/tuple (get): Qualify calls to prevent ADL.
-+ * testsuite/20_util/tuple/60497.cc: New.
-+
-+2012-04-05 Dominique d'Humieres <dominiq@lps.ens.fr>
-+ Jack Howarth <howarth@bromo.med.uc.edu>
-+
-+ PR target/54407
-+ * 30_threads/condition_variable/54185.cc: Skip for darwin < 11.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r204808:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * scripts/extract_symvers.in: Ignore <localentry: > fields
-+ in readelf --symbols output.
-+
-+2014-03-26 Jonathan Wakely <jwakely@redhat.com>
-+
-+ PR libstdc++/59548
-+ * include/debug/safe_unordered_base.h (_Safe_unordered_container_base):
-+ Define copy and move constructors that handle iterators correctly.
-+ * testsuite/23_containers/unordered_map/59548.cc: New.
-+
-+2014-03-25 Jonathan Wakely <jwakely@redhat.com>
-+
-+ PR libstdc++/60658
-+ * include/bits/atomic_base.h (__atomic_base<_PTp*>::is_lock_free()):
-+ Use sizeof pointer type not the element type.
-+ * testsuite/29_atomics/atomic/60658.cc: New.
-+
-+2014-03-18 Jonathan Wakely <jwakely@redhat.com>
-+
-+ PR libstdc++/60564
-+ * include/std/future (__future_base::_Task_state<>): Change
-+ constructors to template functions using perfect forwarding.
-+ (__create_task_state): Use decayed type as stored task.
-+ (packaged_task::packaged_task(_Fn&&)): Forward instead of moving.
-+ * testsuite/30_threads/packaged_task/60564.cc: New.
-+
-+2014-03-12 Roland McGrath <mcgrathr@google.com>
-+ Mark Seaborn <mseaborn@google.com>
-+
-+ PR libstdc++/59392
-+ * libsupc++/eh_call.cc (__cxa_call_unexpected): Call __do_catch with
-+ the address of a null pointer, not with a null pointer to pointer.
-+ Copy comment for this case from eh_personality.cc:__cxa_call_unexpected.
-+ * testsuite/18_support/bad_exception/59392.cc: New file.
-+
-+2014-03-11 Jonathan Wakely <jwakely@redhat.com>
-+
-+ Backport from mainline.
-+ 2014-01-09 Jonathan Wakely <jwakely@redhat.com>
-+
-+ PR libstdc++/59680
-+ * src/c++11/thread.cc (__sleep_for): Fix call to ::sleep.
-+
-+2014-03-11 Jonathan Wakely <jwakely@redhat.com>
-+
-+ Backport from mainline.
-+ 2014-01-27 Jonathan Wakely <jwakely@redhat.com>
-+
-+ PR libstdc++/59215
-+ * include/bits/shared_ptr_base.h
-+ (_Sp_counted_base<_S_atomic>::_M_add_ref_lock()): Use relaxed atomic
-+ load.
-+
-+2014-03-11 Jonathan Wakely <jwakely@redhat.com>
-+
-+ Backport from mainline.
-+
-+ 2014-01-09 Jonathan Wakely <jwakely@redhat.com>
-+
-+ PR libstdc++/59738
-+ * include/bits/stl_vector.h (vector<>::_M_move_assign): Restore
-+ support for non-Movable types.
-+
-+ 2014-01-08 François Dumont <fdumont@gcc.gnu.org>
-+
-+ * include/bits/stl_vector.h (std::vector<>::_M_move_assign): Pass
-+ *this allocator instance when building temporary vector instance
-+ so that *this allocator does not get moved.
-+ * testsuite/23_containers/vector/allocator/move.cc (test01): Add
-+ check on a vector iterator.
-+ * testsuite/23_containers/vector/allocator/move_assign.cc
-+ (test02): Likewise.
-+ (test03): New, test with a non-propagating allocator.
-+
-+ 2013-11-15 Jonathan Wakely <jwakely.gcc@gmail.com>
-+
-+ * testsuite/23_containers/vector/allocator/move.cc: New
-+
-+2014-01-27 Jason Merrill <jason@redhat.com>
-+
-+ Core DR 475
-+ PR c++/41174
-+ PR c++/59224
-+ * libsupc++/eh_throw.cc (__cxa_throw): Set uncaughtExceptions.
-+ * libsupc++/eh_alloc.cc (__cxa_allocate_dependent_exception)
-+ (__cxa_allocate_exception): Don't set it here.
-+
-+2013-12-15 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ * config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt: Update.
-+
-+2013-11-22 Jonathan Wakely <jwakely.gcc@gmail.com>
-+
-+ * acinclude.m4 (libtool_VERSION): Bump.
-+ * configure: Regenerate.
-+ * doc/xml/manual/abi.xml: Update version information.
-+
-+2013-11-05 Jonathan Wakely <jwakely.gcc@gmail.com>
-+
-+ * doc/xml/manual/status_cxx2011.xml: Document aligned_union as
-+ missing.
-+
-+ * doc/xml/manual/spine.xml: Update copyright years.
-+ * doc/html/*: Regenerate.
-+
-+2013-11-01 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR libstdc++/58952
-+ * include/c_global/cstdio: Undef getchar.
-+
-+2013-10-31 Jonathan Wakely <jwakely.gcc@gmail.com>
-+
-+ * testsuite/20_util/shared_ptr/cons/58839.cc: Do not use
-+ default_delete<void>.
-+
-+2013-10-30 Chris Studholme <cvs@cs.utoronto.ca>
-+
-+ PR libstdc++/58912
-+ * include/bits/shared_ptr_base.h (_Sp_counted_ptr_inplace): Remove
-+ unnecessary initialization of storage buffer.
-+
-+2013-10-29 Jonathan Wakely <jwakely.gcc@gmail.com>
-+
-+ PR libstdc++/58839
-+ * include/bits/shared_ptr_base.h
-+ (__shared_ptr<T>::__shared_ptr(unique_ptr<U,D>&&)): Do not dereference
-+ pointer.
-+ * testsuite/20_util/shared_ptr/cons/58839.cc: New.
-+
-+2013-10-20 Chris Jefferson <chris@bubblescope.net>
-+ Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR libstdc++/58800
-+ * include/bits/stl_algo.h (__unguarded_partition_pivot): Change
-+ __last - 2 to __last - 1.
-+ * testsuite/25_algorithms/nth_element/58800.cc: New
-+
-+2013-10-16 François Dumont <fdumont@gcc.gnu.org>
-+
-+ PR libstdc++/58191
-+ * include/debug/macros.h (__glibcxx_check_partitioned_lower): Add
-+ __gnu_debug::__base calls on iterators passed to internal debug
-+ check.
-+ (__glibcxx_check_partitioned_lower_pred): Likewise.
-+ (__glibcxx_check_partitioned_upper): Likewise.
-+ (__glibcxx_check_partitioned_upper_pred): Likewise.
-+ * include/debug/functions.h (__check_partitioned_lower):
-+ Remove code to detect safe iterators.
-+ (__check_partitioned_upper): Likewise.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libstdc++-v3/libsupc++/eh_call.cc
-===================================================================
---- a/src/libstdc++-v3/libsupc++/eh_call.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/libsupc++/eh_call.cc (.../branches/gcc-4_8-branch)
-@@ -104,14 +104,14 @@
- } end_catch_protect_obj;
-
-
-- __try
-- {
-+ __try
-+ {
- if (foreign_exception)
- std::unexpected();
- else
- __unexpected(unexpectedHandler);
- }
-- __catch(...)
-+ __catch(...)
- {
- /* See if the new exception matches the rtti list. */
- if (foreign_exception)
-@@ -140,15 +140,19 @@
- &new_ptr) != ctm_failed)
- __throw_exception_again;
-
-- if (catch_type->__do_catch(&bad_exc, 0, 1))
-+ // If the exception spec allows std::bad_exception, throw that.
-+ // We don't have a thrown object to compare against, but since
-+ // bad_exception doesn't have virtual bases, that's OK; just pass NULL.
-+ void* obj = NULL;
-+ if (catch_type->__do_catch(&bad_exc, &obj, 1))
- bad_exception_allowed = true;
- }
-
- // If the exception spec allows std::bad_exception, throw that.
--#ifdef __EXCEPTIONS
-+#ifdef __EXCEPTIONS
- if (bad_exception_allowed)
- throw std::bad_exception();
--#endif
-+#endif
-
- // Otherwise, die.
- __terminate(terminateHandler);
-Index: libstdc++-v3/libsupc++/eh_alloc.cc
-===================================================================
---- a/src/libstdc++-v3/libsupc++/eh_alloc.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/libsupc++/eh_alloc.cc (.../branches/gcc-4_8-branch)
-@@ -129,12 +129,6 @@
- std::terminate ();
- }
-
-- // We have an uncaught exception as soon as we allocate memory. This
-- // yields uncaught_exception() true during the copy-constructor that
-- // initializes the exception object. See Issue 475.
-- __cxa_eh_globals *globals = __cxa_get_globals ();
-- globals->uncaughtExceptions += 1;
--
- memset (ret, 0, sizeof (__cxa_refcounted_exception));
-
- return (void *)((char *)ret + sizeof (__cxa_refcounted_exception));
-@@ -191,12 +185,6 @@
- std::terminate ();
- }
-
-- // We have an uncaught exception as soon as we allocate memory. This
-- // yields uncaught_exception() true during the copy-constructor that
-- // initializes the exception object. See Issue 475.
-- __cxa_eh_globals *globals = __cxa_get_globals ();
-- globals->uncaughtExceptions += 1;
--
- memset (ret, 0, sizeof (__cxa_dependent_exception));
-
- return ret;
-Index: libstdc++-v3/libsupc++/eh_throw.cc
-===================================================================
---- a/src/libstdc++-v3/libsupc++/eh_throw.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/libsupc++/eh_throw.cc (.../branches/gcc-4_8-branch)
-@@ -62,6 +62,9 @@
- {
- PROBE2 (throw, obj, tinfo);
-
-+ __cxa_eh_globals *globals = __cxa_get_globals ();
-+ globals->uncaughtExceptions += 1;
-+
- // Definitely a primary.
- __cxa_refcounted_exception *header
- = __get_refcounted_exception_header_from_obj (obj);
-Index: libstdc++-v3/testsuite/25_algorithms/nth_element/58800.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/25_algorithms/nth_element/58800.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/25_algorithms/nth_element/58800.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,52 @@
-+// Copyright (C) 2013 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// 25.3.2 [lib.alg.nth.element]
-+
-+// { dg-options "-std=gnu++11" }
-+
-+#include <algorithm>
-+#include <testsuite_hooks.h>
-+#include <testsuite_iterators.h>
-+
-+using __gnu_test::test_container;
-+using __gnu_test::random_access_iterator_wrapper;
-+
-+typedef test_container<int, random_access_iterator_wrapper> Container;
-+
-+void test01()
-+{
-+ std::vector<int> v = {
-+ 207089,
-+ 202585,
-+ 180067,
-+ 157549,
-+ 211592,
-+ 216096,
-+ 207089
-+ };
-+
-+ Container con(v.data(), v.data() + 7);
-+
-+ std::nth_element(con.begin(), con.begin() + 3, con.end());
-+}
-+
-+int main()
-+{
-+ test01();
-+ return 0;
-+}
-Index: libstdc++-v3/testsuite/18_support/bad_exception/59392.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/18_support/bad_exception/59392.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/18_support/bad_exception/59392.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,51 @@
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+#include <exception>
-+#include <cstdlib>
-+
-+class expected {};
-+class unexpected {};
-+class from_handler {};
-+
-+static void func_with_exception_spec() throw(expected)
-+{
-+ throw unexpected();
-+}
-+
-+static void unexpected_handler()
-+{
-+ throw from_handler();
-+}
-+
-+static void terminate_handler()
-+{
-+ exit(0);
-+}
-+
-+// libstdc++/59392
-+int main()
-+{
-+ std::set_unexpected(unexpected_handler);
-+ std::set_terminate(terminate_handler);
-+ try {
-+ func_with_exception_spec();
-+ } catch (expected&) {
-+ abort();
-+ }
-+ abort();
-+}
-
-Property changes on: libstdc++-v3/testsuite/18_support/bad_exception/59392.cc
-___________________________________________________________________
-Added: svn:eol-style
-## -0,0 +1 ##
-+LF
-\ No newline at end of property
-Index: libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,51 @@
-+// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } }
-+// { dg-options " -std=gnu++11 -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* powerpc-ibm-aix* } }
-+// { dg-options " -std=gnu++11 -pthreads" { target *-*-solaris* } }
-+// { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-darwin* } }
-+// { dg-require-cstdint "" }
-+// { dg-require-gthreads "" }
-+// { dg-require-atomic-builtins "" }
-+
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+
-+#include <future>
-+#include <testsuite_hooks.h>
-+
-+struct X
-+{
-+ X() = default;
-+ X(const X&) = default;
-+ X(X&& x) { x.moved = true; }
-+
-+ void operator()() const { }
-+
-+ bool moved = false;
-+};
-+
-+void test01()
-+{
-+ X x;
-+ std::packaged_task<void()> p(x);
-+ VERIFY( !x.moved );
-+}
-+
-+int main()
-+{
-+ test01();
-+}
-Index: libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc (.../branches/gcc-4_8-branch)
-@@ -1,11 +1,11 @@
--// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } }
--// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } }
-+// { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* *-*-cygwin *-*-darwin1[1-9]* powerpc-ibm-aix* } }
-+// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-gnu* powerpc-ibm-aix* } }
- // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } }
- // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } }
- // { dg-require-cstdint "" }
- // { dg-require-gthreads "" }
-
--// Copyright (C) 2012-2013 Free Software Foundation, Inc.
-+// Copyright (C) 2012-2014 Free Software Foundation, Inc.
- //
- // This file is part of the GNU ISO C++ Library. This library is free
- // software; you can redistribute it and/or modify it under the
-Index: libstdc++-v3/testsuite/29_atomics/atomic/60658.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/29_atomics/atomic/60658.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/29_atomics/atomic/60658.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,43 @@
-+// { dg-require-atomic-builtins "" }
-+// { dg-options "-std=gnu++11" }
-+
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+#include <atomic>
-+#include <testsuite_hooks.h>
-+
-+// libstdc++/60658
-+
-+struct Foo {
-+ char buf[1];
-+};
-+
-+struct Bar {
-+ char buf[100];
-+};
-+
-+int
-+main ()
-+{
-+ bool test __attribute__((unused)) = true;
-+
-+ std::atomic<Foo*> a;
-+ std::atomic<Bar*> b;
-+
-+ VERIFY (a.is_lock_free() == b.is_lock_free());
-+}
-Index: libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,34 @@
-+// { dg-options "-std=gnu++11" }
-+// { dg-do compile }
-+// { dg-require-debug-mode "" }
-+
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// libstdc++/59548
-+
-+#include <unordered_map>
-+
-+int main()
-+{
-+ std::unordered_map<int,int> foo{ {0,1} };
-+ auto i = foo.begin();
-+ {
-+ auto bar = foo;
-+ }
-+ return i->first;
-+}
-Index: libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,59 @@
-+// Copyright (C) 2013 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// { dg-options "-std=gnu++11" }
-+
-+#include <vector>
-+#include <testsuite_hooks.h>
-+#include <testsuite_allocator.h>
-+
-+struct T { int i; };
-+
-+using __gnu_test::uneq_allocator;
-+
-+void test01()
-+{
-+ bool test __attribute__((unused)) = true;
-+ typedef uneq_allocator<T> alloc_type;
-+ typedef std::vector<T, alloc_type> test_type;
-+ test_type v1(alloc_type(1));
-+ v1 = { T() };
-+ auto it = v1.begin();
-+ test_type v2(std::move(v1));
-+ VERIFY(1 == v1.get_allocator().get_personality());
-+ VERIFY(1 == v2.get_allocator().get_personality());
-+ VERIFY( it == v2.begin() );
-+}
-+
-+void test02()
-+{
-+ bool test __attribute__((unused)) = true;
-+ typedef uneq_allocator<T> alloc_type;
-+ typedef std::vector<T, alloc_type> test_type;
-+ test_type v1(alloc_type(1));
-+ v1 = { T() };
-+ test_type v2(std::move(v1), alloc_type(2));
-+ VERIFY(1 == v1.get_allocator().get_personality());
-+ VERIFY(2 == v2.get_allocator().get_personality());
-+}
-+
-+int main()
-+{
-+ test01();
-+ test02();
-+ return 0;
-+}
-Index: libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc (.../branches/gcc-4_8-branch)
-@@ -46,16 +46,35 @@
- typedef std::vector<T, alloc_type> test_type;
- test_type v1(alloc_type(1));
- v1.push_back(T());
-+ auto it = v1.begin();
- test_type v2(alloc_type(2));
-+ v2.push_back(T());
- v2 = std::move(v1);
-- v2.push_back(T());
-+ VERIFY( it == v2.begin() );
- VERIFY(0 == v1.get_allocator().get_personality());
- VERIFY(1 == v2.get_allocator().get_personality());
- }
-
-+void test03()
-+{
-+ bool test __attribute__((unused)) = true;
-+ typedef propagating_allocator<T, false> alloc_type;
-+ typedef std::vector<T, alloc_type> test_type;
-+ test_type v1(alloc_type(1));
-+ v1.push_back(T());
-+ auto it = v1.begin();
-+ test_type v2(alloc_type(1));
-+ v2.push_back(T());
-+ v2 = std::move(v1);
-+ VERIFY( it == v2.begin() );
-+ VERIFY(1 == v1.get_allocator().get_personality());
-+ VERIFY(1 == v2.get_allocator().get_personality());
-+}
-+
- int main()
- {
- test01();
- test02();
-+ test03();
- return 0;
- }
-Index: libstdc++-v3/testsuite/20_util/tuple/60497.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,35 @@
-+// { dg-options "-std=gnu++11" }
-+// { dg-do compile }
-+
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// libstdc++/60497
-+
-+#include <tuple>
-+
-+struct A;
-+template<typename T> struct B { T t; };
-+
-+using element_type = B<A>*;
-+using tuple_type = std::tuple<element_type>;
-+
-+tuple_type t;
-+const tuple_type ct;
-+
-+auto a = std::get<0>(t);
-+auto b = std::get<0>(ct);
-Index: libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,33 @@
-+// { dg-options "-std=gnu++11" }
-+// { dg-do compile }
-+
-+// Copyright (C) 2013 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+#include <memory>
-+
-+// libstdc++/58839
-+
-+struct D {
-+ void operator()(void*) const noexcept { }
-+};
-+
-+void test01()
-+{
-+ std::unique_ptr<void, D> y;
-+ std::shared_ptr<void> x = std::move(y);
-+}
-Index: libstdc++-v3/testsuite/20_util/function/60594.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/function/60594.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/function/60594.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,36 @@
-+// { dg-options "-std=gnu++11" }
-+// { dg-do compile }
-+
-+// Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+//
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+//
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// libstdc++/60594
-+
-+#include <functional>
-+#include <type_traits>
-+struct bar;
-+using F = std::function<bar()>;
-+// check for copy constructible and assignable while 'bar' is incomplete
-+constexpr int c = std::is_copy_constructible<F>::value;
-+constexpr int a = std::is_copy_assignable<F>::value;
-+struct bar { };
-+bar func();
-+void test()
-+{
-+ F g{ &func };
-+ g = func;
-+}
-Index: libstdc++-v3/testsuite/20_util/bind/57899.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/bind/57899.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/bind/57899.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,48 @@
-+// Copyright (C) 2010-2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library. This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3. If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// 20.7.11 Function template bind
-+
-+// PR c++/57899
-+// { dg-do compile }
-+// { dg-options -std=c++11 }
-+
-+#include <functional>
-+using std::bind;
-+using std::placeholders::_1;
-+
-+struct S { int i; };
-+
-+struct P { S s; };
-+
-+struct get_s
-+{
-+ const S& operator()(const P& p) const { return p.s; }
-+} gs;
-+
-+int gi(const S& s) { return s.i; }
-+
-+bool cmp(int, int) { return true; }
-+
-+int main()
-+{
-+ P p{};
-+ auto f1 = bind(gs, _1);
-+ auto f2 = bind(gi, f1);
-+ auto f3 = bind(cmp, f2, 5);
-+ f3(p);
-+}
-Index: libstdc++-v3/config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt
-===================================================================
---- a/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt (.../branches/gcc-4_8-branch)
-@@ -403,6 +403,7 @@
- FUNC:_ZNKSt15basic_streambufIwSt11char_traitsIwEE6getlocEv@@GLIBCXX_3.4
- FUNC:_ZNKSt15basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4
- FUNC:_ZNKSt15basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4
-+FUNC:_ZNKSt17bad_function_call4whatEv@@GLIBCXX_3.4.18
- FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4
- FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@@GLIBCXX_3.4
- FUNC:_ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4
-@@ -590,6 +591,8 @@
- FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewm@@GLIBCXX_3.4
- FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewx@@GLIBCXX_3.4
- FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewy@@GLIBCXX_3.4
-+FUNC:_ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEj@@GLIBCXX_3.4.18
-+FUNC:_ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEjjj@@GLIBCXX_3.4.18
- FUNC:_ZNKSt8bad_cast4whatEv@@GLIBCXX_3.4.9
- FUNC:_ZNKSt8ios_base7failure4whatEv@@GLIBCXX_3.4
- FUNC:_ZNKSt8messagesIcE18_M_convert_to_charERKSs@@GLIBCXX_3.4
-@@ -1207,6 +1210,7 @@
- FUNC:_ZNSt11regex_errorD0Ev@@GLIBCXX_3.4.15
- FUNC:_ZNSt11regex_errorD1Ev@@GLIBCXX_3.4.15
- FUNC:_ZNSt11regex_errorD2Ev@@GLIBCXX_3.4.15
-+FUNC:_ZNSt11this_thread11__sleep_forENSt6chrono8durationIxSt5ratioILx1ELx1EEEENS1_IxS2_ILx1ELx1000000000EEEE@@GLIBCXX_3.4.18
- FUNC:_ZNSt12__basic_fileIcE2fdEv@@GLIBCXX_3.4
- FUNC:_ZNSt12__basic_fileIcE4fileEv@@GLIBCXX_3.4.1
- FUNC:_ZNSt12__basic_fileIcE4openEPKcSt13_Ios_Openmodei@@GLIBCXX_3.4
-@@ -1485,6 +1489,11 @@
- FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEt@@GLIBCXX_3.4
- FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEx@@GLIBCXX_3.4
- FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEy@@GLIBCXX_3.4
-+FUNC:_ZNSt13random_device14_M_init_pretr1ERKSs@@GLIBCXX_3.4.18
-+FUNC:_ZNSt13random_device16_M_getval_pretr1Ev@@GLIBCXX_3.4.18
-+FUNC:_ZNSt13random_device7_M_finiEv@@GLIBCXX_3.4.18
-+FUNC:_ZNSt13random_device7_M_initERKSs@@GLIBCXX_3.4.18
-+FUNC:_ZNSt13random_device9_M_getvalEv@@GLIBCXX_3.4.18
- FUNC:_ZNSt13runtime_errorC1ERKSs@@GLIBCXX_3.4
- FUNC:_ZNSt13runtime_errorC2ERKSs@@GLIBCXX_3.4
- FUNC:_ZNSt13runtime_errorD0Ev@@GLIBCXX_3.4
-@@ -1929,6 +1938,8 @@
- FUNC:_ZNSt6__norm15_List_node_base8transferEPS0_S1_@@GLIBCXX_3.4.9
- FUNC:_ZNSt6__norm15_List_node_base9_M_unhookEv@@GLIBCXX_3.4.14
- FUNC:_ZNSt6chrono12system_clock3nowEv@@GLIBCXX_3.4.11
-+FUNC:_ZNSt6chrono3_V212steady_clock3nowEv@@GLIBCXX_3.4.19
-+FUNC:_ZNSt6chrono3_V212system_clock3nowEv@@GLIBCXX_3.4.19
- FUNC:_ZNSt6gslice8_IndexerC1EjRKSt8valarrayIjES4_@@GLIBCXX_3.4
- FUNC:_ZNSt6gslice8_IndexerC2EjRKSt8valarrayIjES4_@@GLIBCXX_3.4
- FUNC:_ZNSt6locale11_M_coalesceERKS_S1_i@@GLIBCXX_3.4
-@@ -2467,6 +2478,7 @@
- FUNC:__cxa_guard_release@@CXXABI_1.3
- FUNC:__cxa_pure_virtual@@CXXABI_1.3
- FUNC:__cxa_rethrow@@CXXABI_1.3
-+FUNC:__cxa_thread_atexit@@CXXABI_1.3.7
- FUNC:__cxa_throw@@CXXABI_1.3
- FUNC:__cxa_tm_cleanup@@CXXABI_TM_1
- FUNC:__cxa_vec_cctor@@CXXABI_1.3
-@@ -2491,6 +2503,7 @@
- OBJECT:0:CXXABI_1.3.4
- OBJECT:0:CXXABI_1.3.5
- OBJECT:0:CXXABI_1.3.6
-+OBJECT:0:CXXABI_1.3.7
- OBJECT:0:CXXABI_TM_1
- OBJECT:0:GLIBCXX_3.4
- OBJECT:0:GLIBCXX_3.4.1
-@@ -2502,6 +2515,8 @@
- OBJECT:0:GLIBCXX_3.4.15
- OBJECT:0:GLIBCXX_3.4.16
- OBJECT:0:GLIBCXX_3.4.17
-+OBJECT:0:GLIBCXX_3.4.18
-+OBJECT:0:GLIBCXX_3.4.19
- OBJECT:0:GLIBCXX_3.4.2
- OBJECT:0:GLIBCXX_3.4.3
- OBJECT:0:GLIBCXX_3.4.4
-@@ -3033,6 +3048,8 @@
- OBJECT:1:_ZNSt21__numeric_limits_base9is_moduloE@@GLIBCXX_3.4
- OBJECT:1:_ZNSt21__numeric_limits_base9is_signedE@@GLIBCXX_3.4
- OBJECT:1:_ZNSt6chrono12system_clock12is_monotonicE@@GLIBCXX_3.4.11
-+OBJECT:1:_ZNSt6chrono3_V212steady_clock9is_steadyE@@GLIBCXX_3.4.19
-+OBJECT:1:_ZNSt6chrono3_V212system_clock9is_steadyE@@GLIBCXX_3.4.19
- OBJECT:1:_ZSt10adopt_lock@@GLIBCXX_3.4.11
- OBJECT:1:_ZSt10defer_lock@@GLIBCXX_3.4.11
- OBJECT:1:_ZSt11try_to_lock@@GLIBCXX_3.4.11
-Index: libstdc++-v3/acinclude.m4
-===================================================================
---- a/src/libstdc++-v3/acinclude.m4 (.../tags/gcc_4_8_2_release)
-+++ b/src/libstdc++-v3/acinclude.m4 (.../branches/gcc-4_8-branch)
-@@ -3266,7 +3266,7 @@
- fi
-
- # For libtool versioning info, format is CURRENT:REVISION:AGE
--libtool_VERSION=6:18:0
-+libtool_VERSION=6:19:0
-
- # Everything parsed; figure out what files and settings to use.
- case $enable_symvers in
-Index: libmudflap/configure
-===================================================================
---- a/src/libmudflap/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libmudflap/configure (.../branches/gcc-4_8-branch)
-@@ -6377,7 +6377,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6402,7 +6402,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6421,7 +6424,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -10615,7 +10621,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10618 "configure"
-+#line 10624 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -10721,7 +10727,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10724 "configure"
-+#line 10730 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: libmudflap/ChangeLog
-===================================================================
---- a/src/libmudflap/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libmudflap/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,10 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: boehm-gc/include/private/gcconfig.h
-===================================================================
---- a/src/boehm-gc/include/private/gcconfig.h (.../tags/gcc_4_8_2_release)
-+++ b/src/boehm-gc/include/private/gcconfig.h (.../branches/gcc-4_8-branch)
-@@ -837,7 +837,15 @@
- # define NO_PTHREAD_TRYLOCK
- # endif
- # ifdef FREEBSD
-+# if defined(__powerpc64__)
-+# define ALIGNMENT 8
-+# define CPP_WORDSZ 64
-+# ifndef HBLKSIZE
-+# define HBLKSIZE 4096
-+# endif
-+# else
- # define ALIGNMENT 4
-+# endif
- # define OS_TYPE "FREEBSD"
- # ifndef GC_FREEBSD_THREADS
- # define MPROTECT_VDB
-Index: boehm-gc/ChangeLog
-===================================================================
---- a/src/boehm-gc/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/boehm-gc/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,15 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
-+2013-12-29 Andreas Tobler <andreast@gcc.gnu.org>
-+
-+ Merge from trunk:
-+ * include/private/gcconfig.h: Add FreeBSD powerpc64 defines.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: boehm-gc/configure
-===================================================================
---- a/src/boehm-gc/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/boehm-gc/configure (.../branches/gcc-4_8-branch)
-@@ -6770,7 +6770,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6795,7 +6795,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6814,7 +6817,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -11312,7 +11318,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11315 "configure"
-+#line 11321 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11418,7 +11424,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11421 "configure"
-+#line 11427 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: ChangeLog
-===================================================================
---- a/src/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,21 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * libtool.m4: Update to mainline version.
-+ * configure: Regenerate.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r203071:
-+
-+ 2013-10-01 Joern Rennecke <joern.rennecke@embecosm.com>
-+
-+ Import from savannah.gnu.org:
-+ * config.guess: Update to 2013-06-10 version.
-+ * config.sub: Update to 2013-10-01 version.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: lto-plugin/configure
-===================================================================
---- a/src/lto-plugin/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/lto-plugin/configure (.../branches/gcc-4_8-branch)
-@@ -6044,7 +6044,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6069,7 +6069,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6088,7 +6091,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -10552,7 +10558,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10555 "configure"
-+#line 10561 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -10658,7 +10664,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10661 "configure"
-+#line 10667 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: lto-plugin/ChangeLog
-===================================================================
---- a/src/lto-plugin/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/lto-plugin/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,10 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: contrib/ChangeLog
-===================================================================
---- a/src/contrib/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/contrib/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,7 @@
-+2013-10-21 Mike Stump <mikestump@comcast.net>
-+
-+ * gcc_update (configure): Update to handle svn 1.8.1.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: contrib/gcc_update
-===================================================================
---- a/src/contrib/gcc_update (.../tags/gcc_4_8_2_release)
-+++ b/src/contrib/gcc_update (.../branches/gcc-4_8-branch)
-@@ -382,7 +382,7 @@
- fi
-
- revision=`$GCC_SVN info | awk '/Revision:/ { print $2 }'`
-- branch=`$GCC_SVN info | sed -ne "/URL:/ {
-+ branch=`$GCC_SVN info | sed -ne "/^URL:/ {
- s,.*/trunk,trunk,
- s,.*/branches/,,
- s,.*/tags/,,
-Index: libatomic/configure
-===================================================================
---- a/src/libatomic/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libatomic/configure (.../branches/gcc-4_8-branch)
-@@ -6505,7 +6505,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6530,7 +6530,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6549,7 +6552,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -11013,7 +11019,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11016 "configure"
-+#line 11022 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11119,7 +11125,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11122 "configure"
-+#line 11128 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: libatomic/cas_n.c
-===================================================================
---- a/src/libatomic/cas_n.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libatomic/cas_n.c (.../branches/gcc-4_8-branch)
-@@ -51,10 +51,9 @@
- #if !DONE && N <= WORDSIZE && defined(atomic_compare_exchange_w)
- bool
- SIZE(libat_compare_exchange) (UTYPE *mptr, UTYPE *eptr, UTYPE newval,
-- int smodel, int fmodel UNUSED)
-+ int smodel, int fmodel)
- {
- UWORD mask, shift, weval, woldval, wnewval, t, *wptr;
-- bool ret = false;
-
- pre_barrier (smodel);
-
-@@ -82,12 +81,13 @@
- }
- while (!atomic_compare_exchange_w (wptr, &woldval, t, true,
- __ATOMIC_RELAXED, __ATOMIC_RELAXED));
-- ret = true;
-+ post_barrier (smodel);
-+ return true;
-+
- failure:
- *eptr = woldval >> shift;
--
-- post_barrier (smodel);
-- return ret;
-+ post_barrier (fmodel);
-+ return false;
- }
-
- #define DONE 1
-@@ -102,18 +102,17 @@
- {
- UTYPE oldval;
- UWORD magic;
-- bool ret = false;
-+ bool ret;
-
- pre_seq_barrier (smodel);
- magic = protect_start (mptr);
-
- oldval = *mptr;
-- if (oldval == *eptr)
-- {
-- *mptr = newval;
-- ret = true;
-- }
-- *eptr = oldval;
-+ ret = (oldval == *eptr);
-+ if (ret)
-+ *mptr = newval;
-+ else
-+ *eptr = oldval;
-
- protect_end (mptr, magic);
- post_seq_barrier (smodel);
-Index: libatomic/ChangeLog
-===================================================================
---- a/src/libatomic/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libatomic/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,16 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
-+2014-02-20 Richard Henderson <rth@redhat.com>
-+
-+ PR c++/60272
-+ * cas_n.c (libat_compare_exchange): Conditionalize on failure
-+ the store back to EPTR.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libbacktrace/configure
-===================================================================
---- a/src/libbacktrace/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libbacktrace/configure (.../branches/gcc-4_8-branch)
-@@ -6842,7 +6842,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6867,7 +6867,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6886,7 +6889,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -11081,7 +11087,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11084 "configure"
-+#line 11090 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11187,7 +11193,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11190 "configure"
-+#line 11196 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11667,12 +11673,13 @@
- return 0;
- }
- _ACEOF
--if ac_fn_c_try_compile "$LINENO"; then :
-+if ac_fn_c_try_link "$LINENO"; then :
- have_unwind_getipinfo=yes
- else
- have_unwind_getipinfo=no
- fi
--rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
-+rm -f core conftest.err conftest.$ac_objext \
-+ conftest$ac_exeext conftest.$ac_ext
- CFLAGS="$ac_save_CFLAGS"
- { $as_echo "$as_me:${as_lineno-$LINENO}: result: $have_unwind_getipinfo" >&5
- $as_echo "$have_unwind_getipinfo" >&6; }
-Index: libbacktrace/Makefile.in
-===================================================================
---- a/src/libbacktrace/Makefile.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libbacktrace/Makefile.in (.../branches/gcc-4_8-branch)
-@@ -16,7 +16,7 @@
- @SET_MAKE@
-
- # Makefile.am -- Backtrace Makefile.
--# Copyright (C) 2012 Free Software Foundation, Inc.
-+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
-
- # Redistribution and use in source and binary forms, with or without
- # modification, are permitted provided that the following conditions are
-Index: libbacktrace/dwarf.c
-===================================================================
---- a/src/libbacktrace/dwarf.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libbacktrace/dwarf.c (.../branches/gcc-4_8-branch)
-@@ -2507,7 +2507,6 @@
- if (pfvec->count == 0)
- return;
-
-- addrs = (struct function_addrs *) pfvec->vec.base;
- addrs_count = pfvec->count;
-
- if (fvec == NULL)
-@@ -2514,12 +2513,17 @@
- {
- if (!backtrace_vector_release (state, &lvec.vec, error_callback, data))
- return;
-+ addrs = (struct function_addrs *) pfvec->vec.base;
- }
- else
- {
- /* Finish this list of addresses, but leave the remaining space in
- the vector available for the next function unit. */
-- backtrace_vector_finish (state, &fvec->vec);
-+ addrs = ((struct function_addrs *)
-+ backtrace_vector_finish (state, &fvec->vec,
-+ error_callback, data));
-+ if (addrs == NULL)
-+ return;
- fvec->count = 0;
- }
-
-Index: libbacktrace/ChangeLog
-===================================================================
---- a/src/libbacktrace/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libbacktrace/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,35 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
-+2014-02-07 Misty De Meo <misty@brew.sh>
-+
-+ PR target/58710
-+ * configure.ac: Use AC_LINK_IFELSE in check for
-+ _Unwind_GetIPInfo.
-+ * configure: Regenerate.
-+
-+2013-12-05 Ian Lance Taylor <iant@google.com>
-+
-+ * alloc.c (backtrace_vector_finish): Add error_callback and data
-+ parameters. Call backtrace_vector_release. Return address base.
-+ * mmap.c (backtrace_vector_finish): Add error_callback and data
-+ parameters. Return address base.
-+ * dwarf.c (read_function_info): Get new address base from
-+ backtrace_vector_finish.
-+ * internal.h (backtrace_vector_finish): Update declaration.
-+
-+2013-11-30 Ian Lance Taylor <iant@google.com>
-+
-+ Backport from mainline:
-+ 2013-10-17 Ian Lance Taylor <iant@google.com>
-+
-+ * elf.c (elf_add): Don't get the wrong offsets if a debug section
-+ is missing.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libbacktrace/elf.c
-===================================================================
---- a/src/libbacktrace/elf.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libbacktrace/elf.c (.../branches/gcc-4_8-branch)
-@@ -725,6 +725,8 @@
- {
- off_t end;
-
-+ if (sections[i].size == 0)
-+ continue;
- if (min_offset == 0 || sections[i].offset < min_offset)
- min_offset = sections[i].offset;
- end = sections[i].offset + sections[i].size;
-@@ -751,8 +753,13 @@
- descriptor = -1;
-
- for (i = 0; i < (int) DEBUG_MAX; ++i)
-- sections[i].data = ((const unsigned char *) debug_view.data
-- + (sections[i].offset - min_offset));
-+ {
-+ if (sections[i].size == 0)
-+ sections[i].data = NULL;
-+ else
-+ sections[i].data = ((const unsigned char *) debug_view.data
-+ + (sections[i].offset - min_offset));
-+ }
-
- if (!backtrace_dwarf_add (state, base_address,
- sections[DEBUG_INFO].data,
-Index: libbacktrace/internal.h
-===================================================================
---- a/src/libbacktrace/internal.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libbacktrace/internal.h (.../branches/gcc-4_8-branch)
-@@ -192,13 +192,17 @@
- struct backtrace_vector *vec);
-
- /* Finish the current allocation on VEC. Prepare to start a new
-- allocation. The finished allocation will never be freed. */
-+ allocation. The finished allocation will never be freed. Returns
-+ a pointer to the base of the finished entries, or NULL on
-+ failure. */
-
--extern void backtrace_vector_finish (struct backtrace_state *state,
-- struct backtrace_vector *vec);
-+extern void* backtrace_vector_finish (struct backtrace_state *state,
-+ struct backtrace_vector *vec,
-+ backtrace_error_callback error_callback,
-+ void *data);
-
--/* Release any extra space allocated for VEC. Returns 1 on success, 0
-- on failure. */
-+/* Release any extra space allocated for VEC. This may change
-+ VEC->base. Returns 1 on success, 0 on failure. */
-
- extern int backtrace_vector_release (struct backtrace_state *state,
- struct backtrace_vector *vec,
-Index: libbacktrace/configure.ac
-===================================================================
---- a/src/libbacktrace/configure.ac (.../tags/gcc_4_8_2_release)
-+++ b/src/libbacktrace/configure.ac (.../branches/gcc-4_8-branch)
-@@ -144,7 +144,7 @@
- ac_save_CFFLAGS="$CFLAGS"
- CFLAGS="$CFLAGS -Werror-implicit-function-declaration"
- AC_MSG_CHECKING([for _Unwind_GetIPInfo])
-- AC_COMPILE_IFELSE(
-+ AC_LINK_IFELSE(
- [AC_LANG_PROGRAM(
- [#include "unwind.h"
- struct _Unwind_Context *context;
-Index: libbacktrace/alloc.c
-===================================================================
---- a/src/libbacktrace/alloc.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libbacktrace/alloc.c (.../branches/gcc-4_8-branch)
-@@ -113,12 +113,24 @@
-
- /* Finish the current allocation on VEC. */
-
--void
--backtrace_vector_finish (struct backtrace_state *state ATTRIBUTE_UNUSED,
-- struct backtrace_vector *vec)
-+void *
-+backtrace_vector_finish (struct backtrace_state *state,
-+ struct backtrace_vector *vec,
-+ backtrace_error_callback error_callback,
-+ void *data)
- {
-- vec->base = (char *) vec->base + vec->size;
-+ void *ret;
-+
-+ /* With this allocator we call realloc in backtrace_vector_grow,
-+ which means we can't easily reuse the memory here. So just
-+ release it. */
-+ if (!backtrace_vector_release (state, vec, error_callback, data))
-+ return NULL;
-+ ret = vec->base;
-+ vec->base = NULL;
- vec->size = 0;
-+ vec->alc = 0;
-+ return ret;
- }
-
- /* Release any extra space allocated for VEC. */
-Index: libbacktrace/mmap.c
-===================================================================
---- a/src/libbacktrace/mmap.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libbacktrace/mmap.c (.../branches/gcc-4_8-branch)
-@@ -230,12 +230,19 @@
-
- /* Finish the current allocation on VEC. */
-
--void
--backtrace_vector_finish (struct backtrace_state *state ATTRIBUTE_UNUSED,
-- struct backtrace_vector *vec)
-+void *
-+backtrace_vector_finish (
-+ struct backtrace_state *state ATTRIBUTE_UNUSED,
-+ struct backtrace_vector *vec,
-+ backtrace_error_callback error_callback ATTRIBUTE_UNUSED,
-+ void *data ATTRIBUTE_UNUSED)
- {
-+ void *ret;
-+
-+ ret = vec->base;
- vec->base = (char *) vec->base + vec->size;
- vec->size = 0;
-+ return ret;
- }
-
- /* Release any extra space allocated for VEC. */
-Index: libjava/libltdl/configure
-===================================================================
---- a/src/libjava/libltdl/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/libltdl/configure (.../branches/gcc-4_8-branch)
-@@ -4806,7 +4806,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)
-+x86_64-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
- if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
-@@ -4820,7 +4820,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_i386"
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -4836,7 +4839,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*)
-@@ -6456,11 +6462,11 @@
- -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
- -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
- -e 's:$: $lt_compiler_flag:'`
-- (eval echo "\"\$as_me:6459: $lt_compile\"" >&5)
-+ (eval echo "\"\$as_me:6465: $lt_compile\"" >&5)
- (eval "$lt_compile" 2>conftest.err)
- ac_status=$?
- cat conftest.err >&5
-- echo "$as_me:6463: \$? = $ac_status" >&5
-+ echo "$as_me:6469: \$? = $ac_status" >&5
- if (exit $ac_status) && test -s "$ac_outfile"; then
- # The compiler can only warn and ignore the option if not recognized
- # So say no if there are warnings other than the usual output.
-@@ -6718,11 +6724,11 @@
- -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
- -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
- -e 's:$: $lt_compiler_flag:'`
-- (eval echo "\"\$as_me:6721: $lt_compile\"" >&5)
-+ (eval echo "\"\$as_me:6727: $lt_compile\"" >&5)
- (eval "$lt_compile" 2>conftest.err)
- ac_status=$?
- cat conftest.err >&5
-- echo "$as_me:6725: \$? = $ac_status" >&5
-+ echo "$as_me:6731: \$? = $ac_status" >&5
- if (exit $ac_status) && test -s "$ac_outfile"; then
- # The compiler can only warn and ignore the option if not recognized
- # So say no if there are warnings other than the usual output.
-@@ -6780,11 +6786,11 @@
- -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
- -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
- -e 's:$: $lt_compiler_flag:'`
-- (eval echo "\"\$as_me:6783: $lt_compile\"" >&5)
-+ (eval echo "\"\$as_me:6789: $lt_compile\"" >&5)
- (eval "$lt_compile" 2>out/conftest.err)
- ac_status=$?
- cat out/conftest.err >&5
-- echo "$as_me:6787: \$? = $ac_status" >&5
-+ echo "$as_me:6793: \$? = $ac_status" >&5
- if (exit $ac_status) && test -s out/conftest2.$ac_objext
- then
- # The compiler can only warn and ignore the option if not recognized
-@@ -8099,7 +8105,7 @@
- libsuff=
- case "$host_cpu" in
- x86_64*|s390x*|powerpc64*)
-- echo '#line 8102 "configure"' > conftest.$ac_ext
-+ echo '#line 8108 "configure"' > conftest.$ac_ext
- if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
- (eval $ac_compile) 2>&5
- ac_status=$?
-@@ -8652,7 +8658,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<EOF
--#line 8655 "configure"
-+#line 8661 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -8750,7 +8756,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<EOF
--#line 8753 "configure"
-+#line 8759 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -10591,7 +10597,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<EOF
--#line 10594 "configure"
-+#line 10600 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: libjava/libltdl/ChangeLog
-===================================================================
---- a/src/libjava/libltdl/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/libltdl/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,11 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * acinclude.m4: Update to mainline version.
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libjava/libltdl/acinclude.m4
-===================================================================
---- a/src/libjava/libltdl/acinclude.m4 (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/libltdl/acinclude.m4 (.../branches/gcc-4_8-branch)
-@@ -519,7 +519,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)
-+x86_64-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
- if AC_TRY_EVAL(ac_compile); then
-@@ -529,7 +529,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_i386"
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -545,7 +548,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*)
-Index: libjava/classpath/ChangeLog
-===================================================================
---- a/src/libjava/classpath/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/classpath/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,10 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libjava/classpath/configure
-===================================================================
---- a/src/libjava/classpath/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/classpath/configure (.../branches/gcc-4_8-branch)
-@@ -7577,7 +7577,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -7602,7 +7602,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -7621,7 +7624,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -11820,7 +11826,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11823 "configure"
-+#line 11829 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11926,7 +11932,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11929 "configure"
-+#line 11935 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -25300,7 +25306,7 @@
- JAVA_TEST=Object.java
- CLASS_TEST=Object.class
- cat << \EOF > $JAVA_TEST
--/* #line 25303 "configure" */
-+/* #line 25309 "configure" */
- package java.lang;
-
- public class Object
-@@ -25393,7 +25399,7 @@
- if uudecode$EXEEXT Test.uue; then
- ac_cv_prog_uudecode_base64=yes
- else
-- echo "configure: 25396: uudecode had trouble decoding base 64 file 'Test.uue'" >&5
-+ echo "configure: 25402: uudecode had trouble decoding base 64 file 'Test.uue'" >&5
- echo "configure: failed file was:" >&5
- cat Test.uue >&5
- ac_cv_prog_uudecode_base64=no
-@@ -25421,7 +25427,7 @@
- CLASS_TEST=Test.class
- TEST=Test
- cat << \EOF > $JAVA_TEST
--/* [#]line 25424 "configure" */
-+/* [#]line 25430 "configure" */
- public class Test {
- public static void main (String args[]) {
- System.exit (0);
-@@ -25629,7 +25635,7 @@
- JAVA_TEST=Test.java
- CLASS_TEST=Test.class
- cat << \EOF > $JAVA_TEST
-- /* #line 25632 "configure" */
-+ /* #line 25638 "configure" */
- public class Test
- {
- public static void main(String args)
-Index: libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c
-===================================================================
---- a/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c (.../branches/gcc-4_8-branch)
-@@ -39,10 +39,11 @@
- #include <pango/pango.h>
- #include <pango/pangoft2.h>
- #include <pango/pangofc-font.h>
--#include <freetype/ftglyph.h>
--#include <freetype/ftoutln.h>
--#include <freetype/fttypes.h>
--#include <freetype/tttables.h>
-+#include <ft2build.h>
-+#include FT_GLYPH_H
-+#include FT_OUTLINE_H
-+#include FT_TYPES_H
-+#include FT_TRUETYPE_TABLES_H
- #include "gdkfont.h"
- #include "gtkpeer.h"
- #include "gnu_java_awt_peer_gtk_GdkFontPeer.h"
-Index: libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c
-===================================================================
---- a/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/classpath/native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c (.../branches/gcc-4_8-branch)
-@@ -42,8 +42,9 @@
- #include <pango/pango.h>
- #include <pango/pangoft2.h>
- #include <pango/pangofc-font.h>
--#include <freetype/ftglyph.h>
--#include <freetype/ftoutln.h>
-+#include <ft2build.h>
-+#include FT_GLYPH_H
-+#include FT_OUTLINE_H
- #include "jcl.h"
- #include "gdkfont.h"
- #include "gnu_java_awt_peer_gtk_FreetypeGlyphVector.h"
-Index: libjava/classpath/ChangeLog.gcj
-===================================================================
---- a/src/libjava/classpath/ChangeLog.gcj (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/classpath/ChangeLog.gcj (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,9 @@
-+2013-11-29 Matthias Klose <doko@ubuntu.com>
-+
-+ * native/jni/gtk-peer/gnu_java_awt_peer_gtk_FreetypeGlyphVector.c,
-+ native/jni/gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c:
-+ Fix freetype includes.
-+
- 2013-03-22 Jakub Jelinek <jakub@redhat.com>
-
- PR other/43620
-Index: libjava/classpath
-===================================================================
---- a/src/libjava/classpath (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/classpath (.../branches/gcc-4_8-branch)
-
-Property changes on: libjava/classpath
-___________________________________________________________________
-Modified: svn:mergeinfo
- Merged /trunk/libjava/classpath:r206395
-Index: libjava/ChangeLog
-===================================================================
---- a/src/libjava/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,23 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
-+2014-04-01 Dominique d'Humieres <dominiq@lps.ens.fr>
-+
-+ Backport from mainline
-+ 2014-02-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
-+
-+ PR libgcj/55637
-+ * testsuite/libjava.lang/sourcelocation.xfail: New file.
-+
-+2014-03-11 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * java/lang/natObject.cc (_Jv_MonitorEnter): Add missing parenthesis
-+ around comparison with (address | LOCKED) in JvAssert.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libjava/testsuite/libjava.lang/sourcelocation.xfail
-===================================================================
---- a/src/libjava/testsuite/libjava.lang/sourcelocation.xfail (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/testsuite/libjava.lang/sourcelocation.xfail (.../branches/gcc-4_8-branch)
-@@ -0,0 +1 @@
-+xfail-output
-Index: libjava/configure
-===================================================================
---- a/src/libjava/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/configure (.../branches/gcc-4_8-branch)
-@@ -8842,7 +8842,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -8867,7 +8867,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -8886,7 +8889,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -13382,7 +13388,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 13385 "configure"
-+#line 13391 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -13488,7 +13494,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 13491 "configure"
-+#line 13497 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -19483,7 +19489,7 @@
- enableval=$enable_sjlj_exceptions; :
- else
- cat > conftest.$ac_ext << EOF
--#line 19486 "configure"
-+#line 19492 "configure"
- struct S { ~S(); };
- void bar();
- void foo()
-Index: libjava/java/lang/natObject.cc
-===================================================================
---- a/src/libjava/java/lang/natObject.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/libjava/java/lang/natObject.cc (.../branches/gcc-4_8-branch)
-@@ -929,7 +929,7 @@
- // only be held by other threads waiting for conversion, and
- // they, like us, drop it quickly without blocking.
- _Jv_MutexLock(&(hl->si.mutex));
-- JvAssert(he -> address == address | LOCKED );
-+ JvAssert(he -> address == (address | LOCKED));
- release_set(&(he -> address), (address | REQUEST_CONVERSION | HEAVY));
- // release lock on he
- LOG(REQ_CONV, (address | REQUEST_CONVERSION | HEAVY), self);
-@@ -961,7 +961,7 @@
- }
- obj_addr_t was_heavy = (address & HEAVY);
- if ((address & LOCKED) ||
-- !compare_and_swap(&(he -> address), address, (address | LOCKED )))
-+ !compare_and_swap(&(he -> address), address, address | LOCKED ))
- {
- wait_unlocked(he);
- goto retry;
-Index: gnattools/configure
-===================================================================
---- a/src/gnattools/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/gnattools/configure (.../branches/gcc-4_8-branch)
-@@ -2029,66 +2029,59 @@
- # Per-target case statement
- # -------------------------
- case "${target}" in
-- alpha*-dec-vx*) # Unlike all other Vxworks
-+ *-*-aix*)
-+ TOOLS_TARGET_PAIRS="\
-+ mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \
-+ indepsw.adb<indepsw-aix.adb"
- ;;
-- m68k*-wrs-vx* \
-- | powerpc*-wrs-vxworks \
-- | sparc*-wrs-vx* \
-- | *86-wrs-vxworks \
-- | mips*-wrs-vx*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb"
-+ *-*-darwin*)
-+ TOOLS_TARGET_PAIRS="\
-+ mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb \
-+ indepsw.adb<indepsw-darwin.adb"
- ;;
-- sparc-sun-solaris*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
-+ *-*-freebsd*)
-+ TOOLS_TARGET_PAIRS="\
-+ mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
-+ indepsw.adb<indepsw-gnu.adb"
- ;;
-- *86-*-solaris2* | x86_64-*-solaris2.1[0-9]*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
-- ;;
-- *86-*-linux* \
-- | powerpc*-*-linux* \
-- | *ia64-*-linux* \
-- | alpha*-*-linux* \
-- | sparc*-*-linux* \
-- | hppa*-*-linux* \
-- | *x86_64-*-linux*)
-+ *-*-linux*)
- TOOLS_TARGET_PAIRS="\
- mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
- indepsw.adb<indepsw-gnu.adb"
- ;;
-- s390*-*-linux*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"
-+ *-*-lynxos*)
-+ TOOLS_TARGET_PAIRS="\
-+ mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \
-+ indepsw.adb<indepsw-gnu.adb"
- ;;
-- *86-*-freebsd*)
-+ *-*-solaris*)
-+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
-+ ;;
-+ *-*-vxworks*)
- TOOLS_TARGET_PAIRS="\
-- mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
-+ mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb \
- indepsw.adb<indepsw-gnu.adb"
- ;;
-- hppa*-hp-hpux10*) # Unlike hpux11
-+ hppa*-hp-hpux10*)
- ;;
- hppa*-hp-hpux11*)
- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-hpux.adb"
- ;;
-- *-ibm-aix*)
-- TOOLS_TARGET_PAIRS="\
-- mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \
-- indepsw.adb<indepsw-aix.adb"
-+ ia64-hp-hpux11*)
-+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-ia64-hpux.adb"
- ;;
-- alpha*-dec-vms* | alpha*-dec-openvms* | alpha*-dec-vms* \
-- | alpha*-hp-vms* | alpha*-hp-openvms* | alpha*-hp-vms*)
-+ alpha*-*-vms* | alpha*-*-openvms*)
- TOOLS_TARGET_PAIRS="\
- mlib-tgt-specific.adb<mlib-tgt-specific-vms-alpha.adb \
- symbols.adb<symbols-vms.adb \
- symbols-processing.adb<symbols-processing-vms-alpha.adb"
--
- EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'
- ;;
-- ia64*-dec-vms* | ia64*-dec-openvms* | ia64*-dec-vms* \
-- | ia64*-hp-vms* | ia64*-hp-openvms* | ia64*-hp-vms*)
-+ ia64-*-vms* | ia64-*-openvms*)
- TOOLS_TARGET_PAIRS="\
- mlib-tgt-specific.adb<mlib-tgt-specific-vms-ia64.adb \
- symbols.adb<symbols-vms.adb \
- symbols-processing.adb<symbols-processing-vms-ia64.adb"
--
- EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'
- ;;
- *-*-cygwin32* | *-*-mingw32* | *-*-pe)
-@@ -2097,14 +2090,6 @@
- indepsw.adb<indepsw-mingw.adb"
- EXTRA_GNATTOOLS='../../gnatdll$(exeext)'
- ;;
-- *-*-darwin*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb"
-- ;;
-- *-*-lynxos)
-- TOOLS_TARGET_PAIRS="\
-- mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \
-- indepsw.adb<indepsw-gnu.adb"
-- ;;
- esac
-
- # From user or toplevel makefile.
-Index: gnattools/Makefile.in
-===================================================================
---- a/src/gnattools/Makefile.in (.../tags/gcc_4_8_2_release)
-+++ b/src/gnattools/Makefile.in (.../branches/gcc-4_8-branch)
-@@ -24,6 +24,8 @@
- libdir = @libdir@
- build = @build@
- target = @target@
-+host = @host@
-+host_alias = @host_alias@
- prefix = @prefix@
- INSTALL = @INSTALL@
- INSTALL_DATA = @INSTALL_DATA@
-@@ -84,6 +86,7 @@
- TOOLS_FLAGS_TO_PASS_RE= \
- "CC=../../xgcc -B../../" \
- "CFLAGS=$(CFLAGS)" \
-+ "LDFLAGS=$(LDFLAGS)" \
- "ADAFLAGS=$(ADAFLAGS)" \
- "ADA_CFLAGS=$(ADA_CFLAGS)" \
- "INCLUDES=$(INCLUDES_FOR_SUBDIR)" \
-@@ -97,6 +100,22 @@
- "TOOLSCASE=cross"
-
- # Variables for gnattools, cross
-+ifeq ($(build), $(host))
-+ GNATMAKE_FOR_HOST=gnatmake
-+ GNATLINK_FOR_HOST=gnatlink
-+ GNATBIND_FOR_HOST=gnatbind
-+ GNATLS_FOR_HOST=gnatls
-+else
-+ GNATMAKE_FOR_HOST=$(host_alias)-gnatmake
-+ GNATLINK_FOR_HOST=$(host_alias)-gnatlink
-+ GNATBIND_FOR_HOST=$(host_alias)-gnatbind
-+ GNATLS_FOR_HOST=$(host_alias)-gnatls
-+endif
-+
-+# Put the host RTS dir first in the PATH to hide the default runtime
-+# files that are among the sources
-+RTS_DIR:=$(strip $(subst \,/,$(shell $(GNATLS_FOR_HOST) -v | grep adalib )))
-+
- TOOLS_FLAGS_TO_PASS_CROSS= \
- "CC=$(CC)" \
- "CFLAGS=$(CFLAGS) $(WARN_CFLAGS)" \
-@@ -108,9 +127,9 @@
- "exeext=$(exeext)" \
- "fsrcdir=$(fsrcdir)" \
- "srcdir=$(fsrcdir)" \
-- "GNATMAKE=gnatmake" \
-- "GNATLINK=gnatlink" \
-- "GNATBIND=gnatbind" \
-+ "GNATMAKE=$(GNATMAKE_FOR_HOST)" \
-+ "GNATLINK=$(GNATLINK_FOR_HOST)" \
-+ "GNATBIND=$(GNATBIND_FOR_HOST)" \
- "TOOLSCASE=cross" \
- "LIBGNAT="
-
-@@ -179,11 +198,6 @@
- $(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \
- $(TOOLS_FLAGS_TO_PASS_NATIVE) common-tools
-
--# For cross builds of gnattools,
--# put the host RTS dir first in the PATH to hide the default runtime
--# files that are among the sources
--# FIXME: This should be done in configure.
--RTS_DIR:=$(strip $(subst \,/,$(shell gnatls -v | grep adalib )))
- gnattools-cross: $(GCC_DIR)/stamp-tools
- # gnattools1-re
- $(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \
-Index: gnattools/configure.ac
-===================================================================
---- a/src/gnattools/configure.ac (.../tags/gcc_4_8_2_release)
-+++ b/src/gnattools/configure.ac (.../branches/gcc-4_8-branch)
-@@ -69,66 +69,59 @@
- # Per-target case statement
- # -------------------------
- case "${target}" in
-- alpha*-dec-vx*) # Unlike all other Vxworks
-+ *-*-aix*)
-+ TOOLS_TARGET_PAIRS="\
-+ mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \
-+ indepsw.adb<indepsw-aix.adb"
- ;;
-- m68k*-wrs-vx* \
-- | powerpc*-wrs-vxworks \
-- | sparc*-wrs-vx* \
-- | *86-wrs-vxworks \
-- | mips*-wrs-vx*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb"
-+ *-*-darwin*)
-+ TOOLS_TARGET_PAIRS="\
-+ mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb \
-+ indepsw.adb<indepsw-darwin.adb"
- ;;
-- sparc-sun-solaris*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
-+ *-*-freebsd*)
-+ TOOLS_TARGET_PAIRS="\
-+ mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
-+ indepsw.adb<indepsw-gnu.adb"
- ;;
-- *86-*-solaris2* | x86_64-*-solaris2.1[[0-9]]*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
-- ;;
-- *86-*-linux* \
-- | powerpc*-*-linux* \
-- | *ia64-*-linux* \
-- | alpha*-*-linux* \
-- | sparc*-*-linux* \
-- | hppa*-*-linux* \
-- | *x86_64-*-linux*)
-+ *-*-linux*)
- TOOLS_TARGET_PAIRS="\
- mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
- indepsw.adb<indepsw-gnu.adb"
- ;;
-- s390*-*-linux*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"
-+ *-*-lynxos*)
-+ TOOLS_TARGET_PAIRS="\
-+ mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \
-+ indepsw.adb<indepsw-gnu.adb"
- ;;
-- *86-*-freebsd*)
-+ *-*-solaris*)
-+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
-+ ;;
-+ *-*-vxworks*)
- TOOLS_TARGET_PAIRS="\
-- mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
-+ mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb \
- indepsw.adb<indepsw-gnu.adb"
- ;;
-- hppa*-hp-hpux10*) # Unlike hpux11
-+ hppa*-hp-hpux10*)
- ;;
- hppa*-hp-hpux11*)
- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-hpux.adb"
- ;;
-- *-ibm-aix*)
-- TOOLS_TARGET_PAIRS="\
-- mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb \
-- indepsw.adb<indepsw-aix.adb"
-+ ia64-hp-hpux11*)
-+ TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-ia64-hpux.adb"
- ;;
-- alpha*-dec-vms* | alpha*-dec-openvms* | alpha*-dec-vms* \
-- | alpha*-hp-vms* | alpha*-hp-openvms* | alpha*-hp-vms*)
-+ alpha*-*-vms* | alpha*-*-openvms*)
- TOOLS_TARGET_PAIRS="\
- mlib-tgt-specific.adb<mlib-tgt-specific-vms-alpha.adb \
- symbols.adb<symbols-vms.adb \
- symbols-processing.adb<symbols-processing-vms-alpha.adb"
--
- EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'
- ;;
-- ia64*-dec-vms* | ia64*-dec-openvms* | ia64*-dec-vms* \
-- | ia64*-hp-vms* | ia64*-hp-openvms* | ia64*-hp-vms*)
-+ ia64-*-vms* | ia64-*-openvms*)
- TOOLS_TARGET_PAIRS="\
- mlib-tgt-specific.adb<mlib-tgt-specific-vms-ia64.adb \
- symbols.adb<symbols-vms.adb \
- symbols-processing.adb<symbols-processing-vms-ia64.adb"
--
- EXTRA_GNATTOOLS='../../gnatlbr$(exeext) ../../gnatsym$(exeext)'
- ;;
- *-*-cygwin32* | *-*-mingw32* | *-*-pe)
-@@ -137,14 +130,6 @@
- indepsw.adb<indepsw-mingw.adb"
- EXTRA_GNATTOOLS='../../gnatdll$(exeext)'
- ;;
-- *-*-darwin*)
-- TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb"
-- ;;
-- *-*-lynxos)
-- TOOLS_TARGET_PAIRS="\
-- mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb \
-- indepsw.adb<indepsw-gnu.adb"
-- ;;
- esac
-
- # From user or toplevel makefile.
-Index: gnattools/ChangeLog
-===================================================================
---- a/src/gnattools/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gnattools/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,23 @@
-+2013-12-12 Eric Botcazou <ebotcazou@adacore.com>
-+ Iain Sandoe <iain@codesourcery.com>
-+
-+ PR ada/55946
-+ * Makefile.in (host): Define.
-+ (host_alias): Likewise.
-+ (TOOLS_FLAGS_TO_PASS_RE): Add LDFLAGS.
-+ (GNATMAKE_FOR_HOST): Define.
-+ (GNATLINK_FOR_HOST): Likewise.
-+ (GNATBIND_FOR_HOST): Likewise.
-+ (GNATLS_FOR_HOST): Likewise.
-+ (RTS_DIR): Move around and use GNATLS_FOR_HOST.
-+ (TOOLS_FLAGS_TO_PASS_CROSS): Use the other *_HOST variables.
-+
-+2013-12-04 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR ada/59382
-+ * configure.ac (target parameterization): Rewrite.
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: maintainer-scripts/ChangeLog
-===================================================================
---- a/src/maintainer-scripts/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/maintainer-scripts/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,9 @@
-+2014-02-01 Dmitry Gorbachev <d.g.gorbachev@gmail.com>
-+
-+ PR other/56653
-+ * gcc_release: Avoid printing empty line to generated MD5SUMS files.
-+ Bump copyright year.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: maintainer-scripts/gcc_release
-===================================================================
---- a/src/maintainer-scripts/gcc_release (.../tags/gcc_4_8_2_release)
-+++ b/src/maintainer-scripts/gcc_release (.../branches/gcc-4_8-branch)
-@@ -9,7 +9,7 @@
- # Contents:
- # Script to create a GCC release.
- #
--# Copyright (c) 2001, 2002, 2006, 2009, 2010, 2011 Free Software Foundation.
-+# Copyright (c) 2001-2014 Free Software Foundation.
- #
- # This file is part of GCC.
- #
-@@ -213,7 +213,7 @@
- #
- # Suggested usage:
- # md5sum -c MD5SUMS | grep -v \"OK$\"
--" > MD5SUMS
-+#" > MD5SUMS
-
- find . -type f |
- sed -e 's:^\./::' -e '/MD5SUMS/d' |
-Index: libgcc/config.host
-===================================================================
---- a/src/libgcc/config.host (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/config.host (.../branches/gcc-4_8-branch)
-@@ -331,10 +331,10 @@
- ;;
- arm*-*-uclinux*) # ARM ucLinux
- tmake_file="${tmake_file} t-fixedpoint-gnu-prefix"
-+ tmake_file="$tmake_file arm/t-arm arm/t-elf t-softfp-sfdf t-softfp-excl arm/t-softfp t-softfp"
- tmake_file="${tmake_file} arm/t-bpabi"
- tm_file="$tm_file arm/bpabi-lib.h"
- unwind_header=config/arm/unwind-arm.h
-- tmake_file="$tmake_file arm/t-arm arm/t-elf t-softfp-sfdf t-softfp-excl arm/t-softfp t-softfp"
- extra_parts="$extra_parts crti.o crtn.o"
- ;;
- arm*-*-eabi* | arm*-*-symbianelf* | arm*-*-rtems*)
-@@ -718,6 +718,10 @@
- tmake_file="${tmake_file} microblaze/t-microblaze t-fdpbit"
- extra_parts="$extra_parts crtbeginS.o crtendS.o crtbeginT.o crti.o crtn.o"
- ;;
-+microblaze*-*-rtems*)
-+ tmake_file="${tmake_file} microblaze/t-microblaze t-fdpbit"
-+ extra_parts="$extra_parts crtbeginS.o crtendS.o crtbeginT.o crti.o crtn.o"
-+ ;;
- mips*-*-netbsd*) # NetBSD/mips, either endian.
- ;;
- mips*-*-linux*) # Linux MIPS, either endian.
-@@ -1081,7 +1085,7 @@
- md_unwind_header=tilepro/linux-unwind.h
- ;;
- v850*-*-*)
-- tmake_file="v850/t-v850 t-fdpbit"
-+ tmake_file="${tmake_file} v850/t-v850 t-fdpbit"
- ;;
- vax-*-linux*)
- tmake_file="$tmake_file vax/t-linux"
-@@ -1098,7 +1102,7 @@
- extra_parts="$extra_parts crti.o crtn.o"
- ;;
- xtensa*-*-linux*)
-- tmake_file="$tmake_file xtensa/t-xtensa xtensa/t-linux"
-+ tmake_file="$tmake_file xtensa/t-xtensa xtensa/t-linux t-slibgcc-libgcc"
- md_unwind_header=xtensa/linux-unwind.h
- ;;
- am33_2.0-*-linux*)
-Index: libgcc/ChangeLog
-===================================================================
---- a/src/libgcc/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,206 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r204808:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Alan Modra <amodra@gmail.com>
-+
-+ * config/rs6000/linux-unwind.h (TOC_SAVE_SLOT): Define.
-+ (frob_update_context): Use it.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Alan Modra <amodra@gmail.com>
-+
-+ * config/rs6000/tramp.S [__powerpc64__ && _CALL_ELF == 2]:
-+ (trampoline_initial): Provide ELFv2 variant.
-+ (__trampoline_setup): Likewise.
-+
-+ * config/rs6000/linux-unwind.h (frob_update_context): Do not
-+ check for AIX indirect function call sequence if _CALL_ELF == 2.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Alan Modra <amodra@gmail.com>
-+
-+ * config/rs6000/linux-unwind.h (get_regs): Do not support
-+ old kernel versions if _CALL_ELF == 2.
-+ (frob_update_context): Do not support PLT stub variants only
-+ generated by old linkers if _CALL_ELF == 2.
-+
-+ Backport from mainline r204800:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Alan Modra <amodra@gmail.com>
-+
-+ * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Correct
-+ location of CR save area for 64-bit little-endian systems.
-+
-+2014-03-20 Joel Sherrill <joel.sherrill@oarcorp.com>
-+
-+ * config.host (v850*-*-*): Add to tmake_file instead of resetting it.
-+
-+2014-02-28 Joey Ye <joey.ye@arm.com>
-+
-+ Backport from mainline r208229
-+ 2014-02-28 Joey Ye <joey.ye@arm.com>
-+
-+ PR libgcc/60166
-+ * config/arm/sfp-machine.h (_FP_NANFRAC_H,
-+ _FP_NANFRAC_S, _FP_NANFRAC_D, _FP_NANFRAC_Q):
-+ Set to zero.
-+
-+2014-02-18 Kai Tietz <ktietz@redhat.com>
-+ Jonathan Schleifer <js@webkeks.org>
-+
-+ PR objc/56870
-+ * unwind-seh.c (_GCC_specific_handler): Pass proper
-+ value to unwind-handler.
-+
-+2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ Backport from mainline
-+ 2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ * config/tilepro/atomic.c (pre_atomic_barrier): Mark inline.
-+ (post_atomic_barrier): Ditto.
-+ (__fetch_and_do): New macro.
-+ (__atomic_fetch_and_do): Use __fetch_and_do.
-+ (__sync_fetch_and_do): New macro.
-+ (__sync_fetch_and_add_4): New function.
-+ (__sync_fetch_and_sub_4): New function.
-+ (__sync_fetch_and_or_4): New function.
-+ (__sync_fetch_and_and_4): New function.
-+ (__sync_fetch_and_xor_4): New function.
-+ (__sync_fetch_and_nand_4): New function.
-+ (__sync_fetch_and_add_8): New function.
-+ (__sync_fetch_and_sub_8): New function.
-+ (__sync_fetch_and_or_8): New function.
-+ (__sync_fetch_and_and_8): New function.
-+ (__sync_fetch_and_xor_8): New function.
-+ (__sync_fetch_and_nand_8): New function.
-+ (__do_and_fetch): New macro.
-+ (__atomic_do_and_fetch): Use __do_and_fetch.
-+ (__sync_do_and_fetch): New macro.
-+ (__sync_add_and_fetch_4): New function.
-+ (__sync_sub_and_fetch_4): New function.
-+ (__sync_or_and_fetch_4): New function.
-+ (__sync_and_and_fetch_4): New function.
-+ (__sync_xor_and_fetch_4): New function.
-+ (__sync_nand_and_fetch_4): New function.
-+ (__sync_add_and_fetch_8): New function.
-+ (__sync_sub_and_fetch_8): New function.
-+ (__sync_or_and_fetch_8): New function.
-+ (__sync_and_and_fetch_8): New function.
-+ (__sync_xor_and_fetch_8): New function.
-+ (__sync_nand_and_fetch_8): New function.
-+ (__sync_exchange_methods): New macro.
-+ (__sync_val_compare_and_swap_4): New function.
-+ (__sync_bool_compare_and_swap_4): New function.
-+ (__sync_lock_test_and_test_4): New function.
-+ (__sync_val_compare_and_swap_8): New function.
-+ (__sync_bool_compare_and_swap_8): New function.
-+ (__sync_lock_test_and_test_8): New function.
-+ (__subword_cmpxchg_body): New macro.
-+ (__atomic_compare_exchange_1): Use __subword_cmpxchg_body.
-+ (__atomic_compare_exchange_2): Ditto.
-+ (__sync_subword_cmpxchg): New macro.
-+ (__sync_val_compare_and_swap_1): New function.
-+ (__sync_bool_compare_and_swap_1): New function.
-+ (__sync_val_compare_and_swap_2): New function.
-+ (__sync_bool_compare_and_swap_2): New function.
-+ (__atomic_subword): Rename to ...
-+ (__subword): ... New name.
-+ (__atomic_subword_fetch): Use __subword.
-+ (__sync_subword_fetch): New macro.
-+ (__sync_fetch_and_add_1): New function.
-+ (__sync_fetch_and_sub_1): New function.
-+ (__sync_fetch_and_or_1): New function.
-+ (__sync_fetch_and_and_1): New function.
-+ (__sync_fetch_and_xor_1): New function.
-+ (__sync_fetch_and_nand_1): New function.
-+ (__sync_fetch_and_add_2): New function.
-+ (__sync_fetch_and_sub_2): New function.
-+ (__sync_fetch_and_or_2): New function.
-+ (__sync_fetch_and_and_2): New function.
-+ (__sync_fetch_and_xor_2): New function.
-+ (__sync_fetch_and_nand_2): New function.
-+ (__sync_add_and_fetch_1): New function.
-+ (__sync_sub_and_fetch_1): New function.
-+ (__sync_or_and_fetch_1): New function.
-+ (__sync_and_and_fetch_1): New function.
-+ (__sync_xor_and_fetch_1): New function.
-+ (__sync_nand_and_fetch_1): New function.
-+ (__sync_add_and_fetch_2): New function.
-+ (__sync_sub_and_fetch_2): New function.
-+ (__sync_or_and_fetch_2): New function.
-+ (__sync_and_and_fetch_2): New function.
-+ (__sync_xor_and_fetch_2): New function.
-+ (__sync_nand_and_fetch_2): New function.
-+ (__atomic_subword_lock): Use __subword.
-+ (__sync_subword_lock): New macro.
-+ (__sync_lock_test_and_set_1): New function.
-+ (__sync_lock_test_and_set_2): New function.
-+
-+2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ Backport from mainline
-+ 2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ * config/tilepro/atomic.c (BIT_OFFSET): Define.
-+ (__atomic_subword_cmpxchg): Use BIT_OFFSET.
-+ (__atomic_subword): Ditto.
-+
-+2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ Backport from mainline
-+ 2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ * config/tilepro/atomic.c (__atomic_do_and_fetch): Add
-+ a prefix op argument.
-+ (__atomic_nand_fetch_4): Add prefix op.
-+ (__atomic_nand_fetch_8): Ditto.
-+
-+2014-01-21 Baruch Siach <barch@tkos.co.il>
-+
-+ * config.host (tmake_file): add t-slibgcc-libgcc for xtensa*-*-linux*.
-+
-+2014-01-03 Joseph Myers <joseph@codesourcery.com>
-+
-+ * config/rs6000/ibm-ldouble.c (__gcc_qdiv): Scale up arguments in
-+ case of small numerator and finite nonzero result.
-+
-+2013-12-12 Zhenqiang Chen <zhenqiang.chen@arm.com>
-+
-+ Backport from trunk r205917.
-+ 2013-12-12 Zhenqiang Chen <zhenqiang.chen@arm.com>
-+ * config.host (arm*-*-uclinux*): Move t-arm before t-bpabi.
-+
-+2013-12-10 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/sfp-exceptions.c (__sfp_handle_exceptions): Emit SSE
-+ instructions when __SSE_MATH__ is defined.
-+
-+2013-12-06 Ralf Corsépius <ralf.corsepius@rtems.org>
-+
-+ * config.host (microblaze-*-rtems*): New.
-+
-+2013-11-10 Kai Tietz <ktietz@redhat.com>
-+
-+ Back-merged from trunk
-+ * config/i386/cygming-crtbegin.c (__gcc_register_frame):
-+ Increment load-count on use of LIBGCC_SONAME DLL.
-+ (hmod_libgcc): New static variable to hold handle of
-+ LIBGCC_SONAME DLL.
-+ (__gcc_deregister_frame): Decrement load-count of
-+ LIBGCC_SONAME DLL.
-+
-+2013-11-07 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/sfp-exceptions.c (__sfp_handle_exceptions): Handle
-+ FP_EX_DENORM. Store result to volatile location after SSE division
-+ to close interrupt window. Remove unneeded fwait after x87
-+ division since interrupt window will be closed by emitted fstp.
-+ Rewrite FP_EX_INEXACT handling.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-@@ -151,7 +354,7 @@
- * config/mips/crtn.S (fini, init): New labels.
-
- 2012-02-19 Edgar E. Iglesias <edgar.iglesias@gmail.com>
-- * config/microblaze/modsi3.S (modsi3): Fix case with 0x80000000
-+ * config/microblaze/modsi3.S (modsi3): Fix case with 0x80000000
- as dividend.
-
- 2013-02-16 Alan Modra <amodra@gmail.com>
-Index: libgcc/config/i386/sfp-exceptions.c
-===================================================================
---- a/src/libgcc/config/i386/sfp-exceptions.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/config/i386/sfp-exceptions.c (.../branches/gcc-4_8-branch)
-@@ -47,21 +47,33 @@
- if (_fex & FP_EX_INVALID)
- {
- float f = 0.0f;
--#ifdef __x86_64__
-+#ifdef __SSE_MATH__
-+ volatile float r __attribute__ ((unused));
- asm volatile ("%vdivss\t{%0, %d0|%d0, %0}" : "+x" (f));
-+ r = f; /* Needed to trigger exception. */
- #else
- asm volatile ("fdiv\t{%y0, %0|%0, %y0}" : "+t" (f));
-- asm volatile ("fwait");
-+ /* No need for fwait, exception is triggered by emitted fstp. */
- #endif
- }
-+ if (_fex & FP_EX_DENORM)
-+ {
-+ struct fenv temp;
-+ asm volatile ("fnstenv\t%0" : "=m" (temp));
-+ temp.__status_word |= FP_EX_DENORM;
-+ asm volatile ("fldenv\t%0" : : "m" (temp));
-+ asm volatile ("fwait");
-+ }
- if (_fex & FP_EX_DIVZERO)
- {
- float f = 1.0f, g = 0.0f;
--#ifdef __x86_64__
-+#ifdef __SSE_MATH__
-+ volatile float r __attribute__ ((unused));
- asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
-+ r = f; /* Needed to trigger exception. */
- #else
- asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));
-- asm volatile ("fwait");
-+ /* No need for fwait, exception is triggered by emitted fstp. */
- #endif
- }
- if (_fex & FP_EX_OVERFLOW)
-@@ -82,11 +94,15 @@
- }
- if (_fex & FP_EX_INEXACT)
- {
-- struct fenv temp;
-- asm volatile ("fnstenv\t%0" : "=m" (temp));
-- temp.__status_word |= FP_EX_INEXACT;
-- asm volatile ("fldenv\t%0" : : "m" (temp));
-- asm volatile ("fwait");
-+ float f = 1.0f, g = 3.0f;
-+#ifdef __SSE_MATH__
-+ volatile float r __attribute__ ((unused));
-+ asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
-+ r = f; /* Needed to trigger exception. */
-+#else
-+ asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));
-+ /* No need for fwait, exception is triggered by emitted fstp. */
-+#endif
- }
- };
- #endif
-Index: libgcc/config/i386/cygming-crtbegin.c
-===================================================================
---- a/src/libgcc/config/i386/cygming-crtbegin.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/config/i386/cygming-crtbegin.c (.../branches/gcc-4_8-branch)
-@@ -69,6 +69,9 @@
- = { };
-
- static struct object obj;
-+
-+/* Handle of libgcc's DLL reference. */
-+HANDLE hmod_libgcc;
- #endif
-
- #if TARGET_USE_JCR_SECTION
-@@ -93,9 +96,14 @@
-
- void (*register_frame_fn) (const void *, struct object *);
- HANDLE h = GetModuleHandle (LIBGCC_SONAME);
-+
- if (h)
-- register_frame_fn = (void (*) (const void *, struct object *))
-- GetProcAddress (h, "__register_frame_info");
-+ {
-+ /* Increasing the load-count of LIBGCC_SONAME DLL. */
-+ hmod_libgcc = LoadLibrary (LIBGCC_SONAME);
-+ register_frame_fn = (void (*) (const void *, struct object *))
-+ GetProcAddress (h, "__register_frame_info");
-+ }
- else
- register_frame_fn = __register_frame_info;
- if (register_frame_fn)
-@@ -132,5 +140,7 @@
- deregister_frame_fn = __deregister_frame_info;
- if (deregister_frame_fn)
- deregister_frame_fn (__EH_FRAME_BEGIN__);
-+ if (hmod_libgcc)
-+ FreeLibrary (hmod_libgcc);
- #endif
- }
-Index: libgcc/config/rs6000/tramp.S
-===================================================================
---- a/src/libgcc/config/rs6000/tramp.S (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/config/rs6000/tramp.S (.../branches/gcc-4_8-branch)
-@@ -116,4 +116,70 @@
-
- #endif
-
-+#elif _CALL_ELF == 2
-+ .type trampoline_initial,@object
-+ .align 3
-+trampoline_initial:
-+ ld r11,.Lchain(r12)
-+ ld r12,.Lfunc(r12)
-+ mtctr r12
-+ bctr
-+.Lfunc = .-trampoline_initial
-+ .quad 0 /* will be replaced with function address */
-+.Lchain = .-trampoline_initial
-+ .quad 0 /* will be replaced with static chain */
-+
-+trampoline_size = .-trampoline_initial
-+ .size trampoline_initial,trampoline_size
-+
-+
-+/* R3 = stack address to store trampoline */
-+/* R4 = length of trampoline area */
-+/* R5 = function address */
-+/* R6 = static chain */
-+
-+ .pushsection ".toc","aw"
-+.LC0:
-+ .quad trampoline_initial-8
-+ .popsection
-+
-+FUNC_START(__trampoline_setup)
-+ addis 7,2,.LC0@toc@ha
-+ ld 7,.LC0@toc@l(7) /* trampoline address -8 */
-+
-+ li r8,trampoline_size /* verify that the trampoline is big enough */
-+ cmpw cr1,r8,r4
-+ srwi r4,r4,3 /* # doublewords to move */
-+ addi r9,r3,-8 /* adjust pointer for stdu */
-+ mtctr r4
-+ blt cr1,.Labort
-+
-+ /* Copy the instructions to the stack */
-+.Lmove:
-+ ldu r10,8(r7)
-+ stdu r10,8(r9)
-+ bdnz .Lmove
-+
-+ /* Store correct function and static chain */
-+ std r5,.Lfunc(r3)
-+ std r6,.Lchain(r3)
-+
-+ /* Now flush both caches */
-+ mtctr r4
-+.Lcache:
-+ icbi 0,r3
-+ dcbf 0,r3
-+ addi r3,r3,8
-+ bdnz .Lcache
-+
-+ /* Finally synchronize things & return */
-+ sync
-+ isync
-+ blr
-+
-+.Labort:
-+ bl JUMP_TARGET(abort)
-+ nop
-+FUNC_END(__trampoline_setup)
-+
- #endif
-Index: libgcc/config/rs6000/linux-unwind.h
-===================================================================
---- a/src/libgcc/config/rs6000/linux-unwind.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/config/rs6000/linux-unwind.h (.../branches/gcc-4_8-branch)
-@@ -24,9 +24,19 @@
-
- #define R_LR 65
- #define R_CR2 70
-+#define R_CR3 71
-+#define R_CR4 72
- #define R_VR0 77
- #define R_VRSAVE 109
-
-+#ifdef __powerpc64__
-+#if _CALL_ELF == 2
-+#define TOC_SAVE_SLOT 24
-+#else
-+#define TOC_SAVE_SLOT 40
-+#endif
-+#endif
-+
- struct gcc_vregs
- {
- __attribute__ ((vector_size (16))) int vr[32];
-@@ -107,6 +117,8 @@
- }
- else if (pc[1] == 0x380000AC)
- {
-+#if _CALL_ELF != 2
-+ /* These old kernel versions never supported ELFv2. */
- /* This works for 2.4 kernels, but not for 2.6 kernels with vdso
- because pc isn't pointing into the stack. Can be removed when
- no one is running 2.4.19 or 2.4.20, the first two ppc64
-@@ -121,6 +133,7 @@
- if ((long) frame24->puc != -21 * 8)
- return frame24->puc->regs;
- else
-+#endif
- {
- /* This works for 2.4.21 and later kernels. */
- struct rt_sigframe {
-@@ -185,6 +198,7 @@
- {
- struct gcc_regs *regs = get_regs (context);
- struct gcc_vregs *vregs;
-+ long cr_offset;
- long new_cfa;
- int i;
-
-@@ -206,11 +220,21 @@
- fs->regs.reg[i].loc.offset = (long) &regs->gpr[i] - new_cfa;
- }
-
-+ /* The CR is saved in the low 32 bits of regs->ccr. */
-+ cr_offset = (long) &regs->ccr - new_cfa;
-+#ifndef __LITTLE_ENDIAN__
-+ cr_offset += sizeof (long) - 4;
-+#endif
-+ /* In the ELFv1 ABI, CR2 stands in for the whole CR. */
- fs->regs.reg[R_CR2].how = REG_SAVED_OFFSET;
-- /* CR? regs are always 32-bit and PPC is big-endian, so in 64-bit
-- libgcc loc.offset needs to point to the low 32 bits of regs->ccr. */
-- fs->regs.reg[R_CR2].loc.offset = (long) &regs->ccr - new_cfa
-- + sizeof (long) - 4;
-+ fs->regs.reg[R_CR2].loc.offset = cr_offset;
-+#if _CALL_ELF == 2
-+ /* In the ELFv2 ABI, every CR field has a separate CFI entry. */
-+ fs->regs.reg[R_CR3].how = REG_SAVED_OFFSET;
-+ fs->regs.reg[R_CR3].loc.offset = cr_offset;
-+ fs->regs.reg[R_CR4].how = REG_SAVED_OFFSET;
-+ fs->regs.reg[R_CR4].loc.offset = cr_offset;
-+#endif
-
- fs->regs.reg[R_LR].how = REG_SAVED_OFFSET;
- fs->regs.reg[R_LR].loc.offset = (long) &regs->link - new_cfa;
-@@ -294,9 +318,13 @@
- figure out if it was saved. The big problem here is that the
- code that does the save/restore is generated by the linker, so
- we have no good way to determine at compile time what to do. */
-- if (pc[0] == 0xF8410028
-+ if (pc[0] == 0xF8410000 + TOC_SAVE_SLOT
-+#if _CALL_ELF != 2
-+ /* The ELFv2 linker never generates the old PLT stub form. */
- || ((pc[0] & 0xFFFF0000) == 0x3D820000
-- && pc[1] == 0xF8410028))
-+ && pc[1] == 0xF8410000 + TOC_SAVE_SLOT)
-+#endif
-+ )
- {
- /* We are in a plt call stub or r2 adjusting long branch stub,
- before r2 has been saved. Keep REG_UNSAVED. */
-@@ -305,10 +333,12 @@
- {
- unsigned int *insn
- = (unsigned int *) _Unwind_GetGR (context, R_LR);
-- if (insn && *insn == 0xE8410028)
-- _Unwind_SetGRPtr (context, 2, context->cfa + 40);
-+ if (insn && *insn == 0xE8410000 + TOC_SAVE_SLOT)
-+ _Unwind_SetGRPtr (context, 2, context->cfa + TOC_SAVE_SLOT);
-+#if _CALL_ELF != 2
-+ /* ELFv2 does not use this function pointer call sequence. */
- else if (pc[0] == 0x4E800421
-- && pc[1] == 0xE8410028)
-+ && pc[1] == 0xE8410000 + TOC_SAVE_SLOT)
- {
- /* We are at the bctrl instruction in a call via function
- pointer. gcc always emits the load of the new R2 just
-@@ -315,8 +345,9 @@
- before the bctrl so this is the first and only place
- we need to use the stored R2. */
- _Unwind_Word sp = _Unwind_GetGR (context, 1);
-- _Unwind_SetGRPtr (context, 2, (void *)(sp + 40));
-+ _Unwind_SetGRPtr (context, 2, (void *)(sp + TOC_SAVE_SLOT));
- }
-+#endif
- }
- }
- #endif
-Index: libgcc/config/rs6000/ibm-ldouble.c
-===================================================================
---- a/src/libgcc/config/rs6000/ibm-ldouble.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/config/rs6000/ibm-ldouble.c (.../branches/gcc-4_8-branch)
-@@ -188,7 +188,16 @@
- || nonfinite (t))
- return t;
-
-- /* Finite nonzero result requires corrections to the highest order term. */
-+ /* Finite nonzero result requires corrections to the highest order
-+ term. These corrections require the low part of c * t to be
-+ exactly represented in double. */
-+ if (fabs (a) <= 0x1p-969)
-+ {
-+ a *= 0x1p106;
-+ b *= 0x1p106;
-+ c *= 0x1p106;
-+ d *= 0x1p106;
-+ }
-
- s = c * t; /* (s,sigma) = c*t exactly. */
- w = -(-b + d * t); /* Written to get fnmsub for speed, but not
-Index: libgcc/config/tilepro/atomic.c
-===================================================================
---- a/src/libgcc/config/tilepro/atomic.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/config/tilepro/atomic.c (.../branches/gcc-4_8-branch)
-@@ -28,7 +28,7 @@
- /* This code should be inlined by the compiler, but for now support
- it as out-of-line methods in libgcc. */
-
--static void
-+static inline void
- pre_atomic_barrier (int model)
- {
- switch ((enum memmodel) model)
-@@ -44,7 +44,7 @@
- return;
- }
-
--static void
-+static inline void
- post_atomic_barrier (int model)
- {
- switch ((enum memmodel) model)
-@@ -62,16 +62,21 @@
-
- #define __unused __attribute__((unused))
-
--#define __atomic_fetch_and_do(type, size, opname) \
--type \
--__atomic_fetch_##opname##_##size(type* p, type i, int model) \
-+#define __fetch_and_do(proto, type, size, opname, top, bottom) \
-+proto \
- { \
-- pre_atomic_barrier(model); \
-+ top; \
- type rv = arch_atomic_##opname(p, i); \
-- post_atomic_barrier(model); \
-+ bottom; \
- return rv; \
- }
-
-+#define __atomic_fetch_and_do(type, size, opname) \
-+ __fetch_and_do(type __atomic_fetch_##opname##_##size(type* p, type i, int model), \
-+ type, size, opname, \
-+ pre_atomic_barrier(model), \
-+ post_atomic_barrier(model)) \
-+
- __atomic_fetch_and_do (int, 4, add)
- __atomic_fetch_and_do (int, 4, sub)
- __atomic_fetch_and_do (int, 4, or)
-@@ -84,27 +89,73 @@
- __atomic_fetch_and_do (long long, 8, and)
- __atomic_fetch_and_do (long long, 8, xor)
- __atomic_fetch_and_do (long long, 8, nand)
--#define __atomic_do_and_fetch(type, size, opname, op) \
--type \
--__atomic_##opname##_fetch_##size(type* p, type i, int model) \
--{ \
-- pre_atomic_barrier(model); \
-- type rv = arch_atomic_##opname(p, i) op i; \
-- post_atomic_barrier(model); \
-- return rv; \
-+
-+#define __sync_fetch_and_do(type, size, opname) \
-+ __fetch_and_do(type __sync_fetch_and_##opname##_##size(type* p, type i), \
-+ type, size, opname, \
-+ arch_atomic_write_barrier(), \
-+ arch_atomic_read_barrier())
-+
-+__sync_fetch_and_do (int, 4, add)
-+__sync_fetch_and_do (int, 4, sub)
-+__sync_fetch_and_do (int, 4, or)
-+__sync_fetch_and_do (int, 4, and)
-+__sync_fetch_and_do (int, 4, xor)
-+__sync_fetch_and_do (int, 4, nand)
-+__sync_fetch_and_do (long long, 8, add)
-+__sync_fetch_and_do (long long, 8, sub)
-+__sync_fetch_and_do (long long, 8, or)
-+__sync_fetch_and_do (long long, 8, and)
-+__sync_fetch_and_do (long long, 8, xor)
-+__sync_fetch_and_do (long long, 8, nand)
-+
-+#define __do_and_fetch(proto, type, size, opname, op, op2, top, bottom) \
-+proto \
-+{ \
-+ top; \
-+ type rv = op2 (arch_atomic_##opname(p, i) op i); \
-+ bottom; \
-+ return rv; \
- }
--__atomic_do_and_fetch (int, 4, add, +)
--__atomic_do_and_fetch (int, 4, sub, -)
--__atomic_do_and_fetch (int, 4, or, |)
--__atomic_do_and_fetch (int, 4, and, &)
--__atomic_do_and_fetch (int, 4, xor, |)
--__atomic_do_and_fetch (int, 4, nand, &)
--__atomic_do_and_fetch (long long, 8, add, +)
--__atomic_do_and_fetch (long long, 8, sub, -)
--__atomic_do_and_fetch (long long, 8, or, |)
--__atomic_do_and_fetch (long long, 8, and, &)
--__atomic_do_and_fetch (long long, 8, xor, |)
--__atomic_do_and_fetch (long long, 8, nand, &)
-+
-+#define __atomic_do_and_fetch(type, size, opname, op, op2) \
-+ __do_and_fetch(type __atomic_##opname##_fetch_##size(type* p, type i, int model), \
-+ type, size, opname, op, op2, \
-+ pre_atomic_barrier(model), \
-+ post_atomic_barrier(model)) \
-+
-+__atomic_do_and_fetch (int, 4, add, +, )
-+__atomic_do_and_fetch (int, 4, sub, -, )
-+__atomic_do_and_fetch (int, 4, or, |, )
-+__atomic_do_and_fetch (int, 4, and, &, )
-+__atomic_do_and_fetch (int, 4, xor, |, )
-+__atomic_do_and_fetch (int, 4, nand, &, ~)
-+__atomic_do_and_fetch (long long, 8, add, +, )
-+__atomic_do_and_fetch (long long, 8, sub, -, )
-+__atomic_do_and_fetch (long long, 8, or, |, )
-+__atomic_do_and_fetch (long long, 8, and, &, )
-+__atomic_do_and_fetch (long long, 8, xor, |, )
-+__atomic_do_and_fetch (long long, 8, nand, &, ~)
-+
-+#define __sync_do_and_fetch(type, size, opname, op, op2) \
-+ __do_and_fetch(type __sync_##opname##_and_fetch_##size(type* p, type i), \
-+ type, size, opname, op, op2, \
-+ arch_atomic_write_barrier(), \
-+ arch_atomic_read_barrier()) \
-+
-+__sync_do_and_fetch (int, 4, add, +, )
-+__sync_do_and_fetch (int, 4, sub, -, )
-+__sync_do_and_fetch (int, 4, or, |, )
-+__sync_do_and_fetch (int, 4, and, &, )
-+__sync_do_and_fetch (int, 4, xor, |, )
-+__sync_do_and_fetch (int, 4, nand, &, ~)
-+__sync_do_and_fetch (long long, 8, add, +, )
-+__sync_do_and_fetch (long long, 8, sub, -, )
-+__sync_do_and_fetch (long long, 8, or, |, )
-+__sync_do_and_fetch (long long, 8, and, &, )
-+__sync_do_and_fetch (long long, 8, xor, |, )
-+__sync_do_and_fetch (long long, 8, nand, &, ~)
-+
- #define __atomic_exchange_methods(type, size) \
- bool \
- __atomic_compare_exchange_##size(volatile type* ptr, type* oldvalp, \
-@@ -128,49 +179,117 @@
- post_atomic_barrier(model); \
- return retval; \
- }
-+
- __atomic_exchange_methods (int, 4)
- __atomic_exchange_methods (long long, 8)
-
-+#define __sync_exchange_methods(type, size) \
-+type \
-+__sync_val_compare_and_swap_##size(type* ptr, type oldval, type newval) \
-+{ \
-+ arch_atomic_write_barrier(); \
-+ type retval = arch_atomic_val_compare_and_exchange(ptr, oldval, newval); \
-+ arch_atomic_read_barrier(); \
-+ return retval; \
-+} \
-+ \
-+bool \
-+__sync_bool_compare_and_swap_##size(type* ptr, type oldval, type newval) \
-+{ \
-+ arch_atomic_write_barrier(); \
-+ bool retval = arch_atomic_bool_compare_and_exchange(ptr, oldval, newval); \
-+ arch_atomic_read_barrier(); \
-+ return retval; \
-+} \
-+ \
-+type \
-+__sync_lock_test_and_set_##size(type* ptr, type val) \
-+{ \
-+ type retval = arch_atomic_exchange(ptr, val); \
-+ arch_atomic_acquire_barrier_value(retval); \
-+ return retval; \
-+}
-+
-+__sync_exchange_methods (int, 4)
-+__sync_exchange_methods (long long, 8)
-+
-+#ifdef __LITTLE_ENDIAN__
-+#define BIT_OFFSET(n, type) ((n) * 8)
-+#else
-+#define BIT_OFFSET(n, type) ((4 - sizeof(type) - (n)) * 8)
-+#endif
-+
- /* Subword methods require the same approach for both TILEPro and
- TILE-Gx. We load the background data for the word, insert the
- desired subword piece, then compare-and-exchange it into place. */
- #define u8 unsigned char
- #define u16 unsigned short
-+
-+#define __subword_cmpxchg_body(type, size, ptr, guess, val) \
-+ ({ \
-+ unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \
-+ const int shift = BIT_OFFSET((unsigned long)ptr & 3UL, type); \
-+ const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \
-+ const unsigned int bgmask = ~(valmask << shift); \
-+ unsigned int oldword = *p; \
-+ type oldval = (oldword >> shift) & valmask; \
-+ if (__builtin_expect((oldval == guess), 1)) { \
-+ unsigned int word = (oldword & bgmask) | ((val & valmask) << shift); \
-+ oldword = arch_atomic_val_compare_and_exchange(p, oldword, word); \
-+ oldval = (oldword >> shift) & valmask; \
-+ } \
-+ oldval; \
-+ }) \
-+
- #define __atomic_subword_cmpxchg(type, size) \
- \
- bool \
--__atomic_compare_exchange_##size(volatile type* ptr, type* guess, \
-+__atomic_compare_exchange_##size(volatile type* ptr, type* guess_ptr, \
- type val, bool weak __unused, int models, \
- int modelf __unused) \
- { \
- pre_atomic_barrier(models); \
-- unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \
-- const int shift = ((unsigned long)ptr & 3UL) * 8; \
-- const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \
-- const unsigned int bgmask = ~(valmask << shift); \
-- unsigned int oldword = *p; \
-- type oldval = (oldword >> shift) & valmask; \
-- if (__builtin_expect((oldval == *guess), 1)) { \
-- unsigned int word = (oldword & bgmask) | ((val & valmask) << shift); \
-- oldword = arch_atomic_val_compare_and_exchange(p, oldword, word); \
-- oldval = (oldword >> shift) & valmask; \
-- } \
-+ type guess = *guess_ptr; \
-+ type oldval = __subword_cmpxchg_body(type, size, ptr, guess, val); \
- post_atomic_barrier(models); \
-- bool success = (oldval == *guess); \
-- *guess = oldval; \
-+ bool success = (oldval == guess); \
-+ *guess_ptr = oldval; \
- return success; \
- }
-+
- __atomic_subword_cmpxchg (u8, 1)
- __atomic_subword_cmpxchg (u16, 2)
-+
-+#define __sync_subword_cmpxchg(type, size) \
-+ \
-+type \
-+__sync_val_compare_and_swap_##size(type* ptr, type guess, type val) \
-+{ \
-+ arch_atomic_write_barrier(); \
-+ type oldval = __subword_cmpxchg_body(type, size, ptr, guess, val); \
-+ arch_atomic_read_barrier(); \
-+ return oldval; \
-+} \
-+ \
-+bool \
-+__sync_bool_compare_and_swap_##size(type* ptr, type guess, type val) \
-+{ \
-+ type oldval = __sync_val_compare_and_swap_##size(ptr, guess, val); \
-+ return oldval == guess; \
-+}
-+
-+__sync_subword_cmpxchg (u8, 1)
-+__sync_subword_cmpxchg (u16, 2)
-+
- /* For the atomic-update subword methods, we use the same approach as
- above, but we retry until we succeed if the compare-and-exchange
- fails. */
--#define __atomic_subword(type, proto, top, expr, bottom) \
-+#define __subword(type, proto, top, expr, bottom) \
- proto \
- { \
- top \
- unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \
-- const int shift = ((unsigned long)ptr & 3UL) * 8; \
-+ const int shift = BIT_OFFSET((unsigned long)ptr & 3UL, type); \
- const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \
- const unsigned int bgmask = ~(valmask << shift); \
- unsigned int oldword, xword = *p; \
-@@ -184,12 +303,14 @@
- } while (__builtin_expect(xword != oldword, 0)); \
- bottom \
- }
-+
- #define __atomic_subword_fetch(type, funcname, expr, retval) \
-- __atomic_subword(type, \
-- type __atomic_ ## funcname(volatile type *ptr, type i, int model), \
-- pre_atomic_barrier(model);, \
-- expr, \
-- post_atomic_barrier(model); return retval;)
-+ __subword(type, \
-+ type __atomic_ ## funcname(volatile type *ptr, type i, int model), \
-+ pre_atomic_barrier(model);, \
-+ expr, \
-+ post_atomic_barrier(model); return retval;)
-+
- __atomic_subword_fetch (u8, fetch_add_1, oldval + i, oldval)
- __atomic_subword_fetch (u8, fetch_sub_1, oldval - i, oldval)
- __atomic_subword_fetch (u8, fetch_or_1, oldval | i, oldval)
-@@ -196,6 +317,7 @@
- __atomic_subword_fetch (u8, fetch_and_1, oldval & i, oldval)
- __atomic_subword_fetch (u8, fetch_xor_1, oldval ^ i, oldval)
- __atomic_subword_fetch (u8, fetch_nand_1, ~(oldval & i), oldval)
-+
- __atomic_subword_fetch (u16, fetch_add_2, oldval + i, oldval)
- __atomic_subword_fetch (u16, fetch_sub_2, oldval - i, oldval)
- __atomic_subword_fetch (u16, fetch_or_2, oldval | i, oldval)
-@@ -202,6 +324,7 @@
- __atomic_subword_fetch (u16, fetch_and_2, oldval & i, oldval)
- __atomic_subword_fetch (u16, fetch_xor_2, oldval ^ i, oldval)
- __atomic_subword_fetch (u16, fetch_nand_2, ~(oldval & i), oldval)
-+
- __atomic_subword_fetch (u8, add_fetch_1, oldval + i, val)
- __atomic_subword_fetch (u8, sub_fetch_1, oldval - i, val)
- __atomic_subword_fetch (u8, or_fetch_1, oldval | i, val)
-@@ -208,6 +331,7 @@
- __atomic_subword_fetch (u8, and_fetch_1, oldval & i, val)
- __atomic_subword_fetch (u8, xor_fetch_1, oldval ^ i, val)
- __atomic_subword_fetch (u8, nand_fetch_1, ~(oldval & i), val)
-+
- __atomic_subword_fetch (u16, add_fetch_2, oldval + i, val)
- __atomic_subword_fetch (u16, sub_fetch_2, oldval - i, val)
- __atomic_subword_fetch (u16, or_fetch_2, oldval | i, val)
-@@ -214,12 +338,58 @@
- __atomic_subword_fetch (u16, and_fetch_2, oldval & i, val)
- __atomic_subword_fetch (u16, xor_fetch_2, oldval ^ i, val)
- __atomic_subword_fetch (u16, nand_fetch_2, ~(oldval & i), val)
-+
-+#define __sync_subword_fetch(type, funcname, expr, retval) \
-+ __subword(type, \
-+ type __sync_ ## funcname(type *ptr, type i), \
-+ arch_atomic_read_barrier();, \
-+ expr, \
-+ arch_atomic_write_barrier(); return retval;)
-+
-+__sync_subword_fetch (u8, fetch_and_add_1, oldval + i, oldval)
-+__sync_subword_fetch (u8, fetch_and_sub_1, oldval - i, oldval)
-+__sync_subword_fetch (u8, fetch_and_or_1, oldval | i, oldval)
-+__sync_subword_fetch (u8, fetch_and_and_1, oldval & i, oldval)
-+__sync_subword_fetch (u8, fetch_and_xor_1, oldval ^ i, oldval)
-+__sync_subword_fetch (u8, fetch_and_nand_1, ~(oldval & i), oldval)
-+
-+__sync_subword_fetch (u16, fetch_and_add_2, oldval + i, oldval)
-+__sync_subword_fetch (u16, fetch_and_sub_2, oldval - i, oldval)
-+__sync_subword_fetch (u16, fetch_and_or_2, oldval | i, oldval)
-+__sync_subword_fetch (u16, fetch_and_and_2, oldval & i, oldval)
-+__sync_subword_fetch (u16, fetch_and_xor_2, oldval ^ i, oldval)
-+__sync_subword_fetch (u16, fetch_and_nand_2, ~(oldval & i), oldval)
-+
-+__sync_subword_fetch (u8, add_and_fetch_1, oldval + i, val)
-+__sync_subword_fetch (u8, sub_and_fetch_1, oldval - i, val)
-+__sync_subword_fetch (u8, or_and_fetch_1, oldval | i, val)
-+__sync_subword_fetch (u8, and_and_fetch_1, oldval & i, val)
-+__sync_subword_fetch (u8, xor_and_fetch_1, oldval ^ i, val)
-+__sync_subword_fetch (u8, nand_and_fetch_1, ~(oldval & i), val)
-+
-+__sync_subword_fetch (u16, add_and_fetch_2, oldval + i, val)
-+__sync_subword_fetch (u16, sub_and_fetch_2, oldval - i, val)
-+__sync_subword_fetch (u16, or_and_fetch_2, oldval | i, val)
-+__sync_subword_fetch (u16, and_and_fetch_2, oldval & i, val)
-+__sync_subword_fetch (u16, xor_and_fetch_2, oldval ^ i, val)
-+__sync_subword_fetch (u16, nand_and_fetch_2, ~(oldval & i), val)
-+
- #define __atomic_subword_lock(type, size) \
-- \
--__atomic_subword(type, \
-- type __atomic_exchange_##size(volatile type* ptr, type nval, int model), \
-- pre_atomic_barrier(model);, \
-- nval, \
-- post_atomic_barrier(model); return oldval;)
-+ __subword(type, \
-+ type __atomic_exchange_##size(volatile type* ptr, type nval, int model), \
-+ pre_atomic_barrier(model);, \
-+ nval, \
-+ post_atomic_barrier(model); return oldval;)
-+
- __atomic_subword_lock (u8, 1)
- __atomic_subword_lock (u16, 2)
-+
-+#define __sync_subword_lock(type, size) \
-+ __subword(type, \
-+ type __sync_lock_test_and_set_##size(type* ptr, type nval), \
-+ , \
-+ nval, \
-+ arch_atomic_acquire_barrier_value(oldval); return oldval;)
-+
-+__sync_subword_lock (u8, 1)
-+__sync_subword_lock (u16, 2)
-Index: libgcc/config/arm/sfp-machine.h
-===================================================================
---- a/src/libgcc/config/arm/sfp-machine.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/config/arm/sfp-machine.h (.../branches/gcc-4_8-branch)
-@@ -19,10 +19,12 @@
- #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
- #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
-
--#define _FP_NANFRAC_H ((_FP_QNANBIT_H << 1) - 1)
--#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
--#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
--#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
-+/* According to RTABI, QNAN is only with the most significant bit of the
-+ significand set, and all other significand bits zero. */
-+#define _FP_NANFRAC_H 0
-+#define _FP_NANFRAC_S 0
-+#define _FP_NANFRAC_D 0, 0
-+#define _FP_NANFRAC_Q 0, 0, 0, 0
- #define _FP_NANSIGN_H 0
- #define _FP_NANSIGN_S 0
- #define _FP_NANSIGN_D 0
-Index: libgcc/unwind-seh.c
-===================================================================
---- a/src/libgcc/unwind-seh.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgcc/unwind-seh.c (.../branches/gcc-4_8-branch)
-@@ -313,8 +313,9 @@
- ms_exc->ExceptionInformation[3] = gcc_context.reg[1];
-
- /* Begin phase 2. Perform the unwinding. */
-- RtlUnwindEx (this_frame, gcc_context.ra, ms_exc, gcc_exc,
-- ms_orig_context, ms_disp->HistoryTable);
-+ RtlUnwindEx (this_frame, gcc_context.ra, ms_exc,
-+ (PVOID)gcc_context.reg[0], ms_orig_context,
-+ ms_disp->HistoryTable);
- }
-
- /* In _Unwind_RaiseException we return _URC_FATAL_PHASE1_ERROR. */
-Index: config.guess
-===================================================================
---- a/src/config.guess (.../tags/gcc_4_8_2_release)
-+++ b/src/config.guess (.../branches/gcc-4_8-branch)
-@@ -1,10 +1,8 @@
- #! /bin/sh
- # Attempt to guess a canonical system name.
--# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
--# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
--# 2011, 2012, 2013 Free Software Foundation, Inc.
-+# Copyright 1992-2013 Free Software Foundation, Inc.
-
--timestamp='2012-12-30'
-+timestamp='2013-06-10'
-
- # This file is free software; you can redistribute it and/or modify it
- # under the terms of the GNU General Public License as published by
-@@ -52,9 +50,7 @@
- GNU config.guess ($timestamp)
-
- Originally written by Per Bothner.
--Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
--2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
--2012, 2013 Free Software Foundation, Inc.
-+Copyright 1992-2013 Free Software Foundation, Inc.
-
- This is free software; see the source for copying conditions. There is NO
- warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
-@@ -136,6 +132,27 @@
- UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown
- UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown
-
-+case "${UNAME_SYSTEM}" in
-+Linux|GNU|GNU/*)
-+ # If the system lacks a compiler, then just pick glibc.
-+ # We could probably try harder.
-+ LIBC=gnu
-+
-+ eval $set_cc_for_build
-+ cat <<-EOF > $dummy.c
-+ #include <features.h>
-+ #if defined(__UCLIBC__)
-+ LIBC=uclibc
-+ #elif defined(__dietlibc__)
-+ LIBC=dietlibc
-+ #else
-+ LIBC=gnu
-+ #endif
-+ EOF
-+ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'`
-+ ;;
-+esac
-+
- # Note: order is significant - the case branches are not exclusive.
-
- case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
-@@ -857,21 +874,21 @@
- exit ;;
- *:GNU:*:*)
- # the GNU system
-- echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`
-+ echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`
- exit ;;
- *:GNU/*:*:*)
- # other systems with GNU libc and userland
-- echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu
-+ echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC}
- exit ;;
- i*86:Minix:*:*)
- echo ${UNAME_MACHINE}-pc-minix
- exit ;;
- aarch64:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- aarch64_be:Linux:*:*)
- UNAME_MACHINE=aarch64_be
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- alpha:Linux:*:*)
- case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
-@@ -884,59 +901,54 @@
- EV68*) UNAME_MACHINE=alphaev68 ;;
- esac
- objdump --private-headers /bin/sh | grep -q ld.so.1
-- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi
-- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC}
-+ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
-+ arc:Linux:*:* | arceb:Linux:*:*)
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
-+ exit ;;
- arm*:Linux:*:*)
- eval $set_cc_for_build
- if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \
- | grep -q __ARM_EABI__
- then
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- else
- if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \
- | grep -q __ARM_PCS_VFP
- then
-- echo ${UNAME_MACHINE}-unknown-linux-gnueabi
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi
- else
-- echo ${UNAME_MACHINE}-unknown-linux-gnueabihf
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf
- fi
- fi
- exit ;;
- avr32*:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- cris:Linux:*:*)
-- echo ${UNAME_MACHINE}-axis-linux-gnu
-+ echo ${UNAME_MACHINE}-axis-linux-${LIBC}
- exit ;;
- crisv32:Linux:*:*)
-- echo ${UNAME_MACHINE}-axis-linux-gnu
-+ echo ${UNAME_MACHINE}-axis-linux-${LIBC}
- exit ;;
- frv:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- hexagon:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- i*86:Linux:*:*)
-- LIBC=gnu
-- eval $set_cc_for_build
-- sed 's/^ //' << EOF >$dummy.c
-- #ifdef __dietlibc__
-- LIBC=dietlibc
-- #endif
--EOF
-- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'`
-- echo "${UNAME_MACHINE}-pc-linux-${LIBC}"
-+ echo ${UNAME_MACHINE}-pc-linux-${LIBC}
- exit ;;
- ia64:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- m32r*:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- m68*:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- mips:Linux:*:* | mips64:Linux:*:*)
- eval $set_cc_for_build
-@@ -955,54 +967,63 @@
- #endif
- EOF
- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'`
-- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; }
-+ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; }
- ;;
-+ or1k:Linux:*:*)
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
-+ exit ;;
- or32:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- padre:Linux:*:*)
-- echo sparc-unknown-linux-gnu
-+ echo sparc-unknown-linux-${LIBC}
- exit ;;
- parisc64:Linux:*:* | hppa64:Linux:*:*)
-- echo hppa64-unknown-linux-gnu
-+ echo hppa64-unknown-linux-${LIBC}
- exit ;;
- parisc:Linux:*:* | hppa:Linux:*:*)
- # Look for CPU level
- case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in
-- PA7*) echo hppa1.1-unknown-linux-gnu ;;
-- PA8*) echo hppa2.0-unknown-linux-gnu ;;
-- *) echo hppa-unknown-linux-gnu ;;
-+ PA7*) echo hppa1.1-unknown-linux-${LIBC} ;;
-+ PA8*) echo hppa2.0-unknown-linux-${LIBC} ;;
-+ *) echo hppa-unknown-linux-${LIBC} ;;
- esac
- exit ;;
- ppc64:Linux:*:*)
-- echo powerpc64-unknown-linux-gnu
-+ echo powerpc64-unknown-linux-${LIBC}
- exit ;;
- ppc:Linux:*:*)
-- echo powerpc-unknown-linux-gnu
-+ echo powerpc-unknown-linux-${LIBC}
- exit ;;
-+ ppc64le:Linux:*:*)
-+ echo powerpc64le-unknown-linux-${LIBC}
-+ exit ;;
-+ ppcle:Linux:*:*)
-+ echo powerpcle-unknown-linux-${LIBC}
-+ exit ;;
- s390:Linux:*:* | s390x:Linux:*:*)
-- echo ${UNAME_MACHINE}-ibm-linux
-+ echo ${UNAME_MACHINE}-ibm-linux-${LIBC}
- exit ;;
- sh64*:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- sh*:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- sparc:Linux:*:* | sparc64:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- tile*:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- vax:Linux:*:*)
-- echo ${UNAME_MACHINE}-dec-linux-gnu
-+ echo ${UNAME_MACHINE}-dec-linux-${LIBC}
- exit ;;
- x86_64:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- xtensa*:Linux:*:*)
-- echo ${UNAME_MACHINE}-unknown-linux-gnu
-+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
- exit ;;
- i*86:DYNIX/ptx:4*:*)
- # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.
-@@ -1235,19 +1256,21 @@
- exit ;;
- *:Darwin:*:*)
- UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown
-- case $UNAME_PROCESSOR in
-- i386)
-- eval $set_cc_for_build
-- if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then
-- if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \
-- (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \
-- grep IS_64BIT_ARCH >/dev/null
-- then
-- UNAME_PROCESSOR="x86_64"
-- fi
-- fi ;;
-- unknown) UNAME_PROCESSOR=powerpc ;;
-- esac
-+ eval $set_cc_for_build
-+ if test "$UNAME_PROCESSOR" = unknown ; then
-+ UNAME_PROCESSOR=powerpc
-+ fi
-+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then
-+ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \
-+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \
-+ grep IS_64BIT_ARCH >/dev/null
-+ then
-+ case $UNAME_PROCESSOR in
-+ i386) UNAME_PROCESSOR=x86_64 ;;
-+ powerpc) UNAME_PROCESSOR=powerpc64 ;;
-+ esac
-+ fi
-+ fi
- echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE}
- exit ;;
- *:procnto*:*:* | *:QNX:[0123456789]*:*)
-Index: gcc/tree-vrp.c
-===================================================================
---- a/src/gcc/tree-vrp.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-vrp.c (.../branches/gcc-4_8-branch)
-@@ -5271,9 +5271,13 @@
- }
- else if (CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (op_def)))
- {
-- /* Recurse through the type conversion. */
-- retval |= register_edge_assert_for_1 (gimple_assign_rhs1 (op_def),
-- code, e, bsi);
-+ /* Recurse through the type conversion, unless it is a narrowing
-+ conversion or conversion from non-integral type. */
-+ tree rhs = gimple_assign_rhs1 (op_def);
-+ if (INTEGRAL_TYPE_P (TREE_TYPE (rhs))
-+ && (TYPE_PRECISION (TREE_TYPE (rhs))
-+ <= TYPE_PRECISION (TREE_TYPE (op))))
-+ retval |= register_edge_assert_for_1 (rhs, code, e, bsi);
- }
-
- return retval;
-@@ -7453,7 +7457,8 @@
- }
- else if ((operand_less_p (vr1min, *vr0max) == 1
- || operand_equal_p (vr1min, *vr0max, 0))
-- && operand_less_p (*vr0min, vr1min) == 1)
-+ && operand_less_p (*vr0min, vr1min) == 1
-+ && operand_less_p (*vr0max, vr1max) == 1)
- {
- /* [ ( ] ) or [ ]( ) */
- if (*vr0type == VR_RANGE
-@@ -7487,7 +7492,8 @@
- }
- else if ((operand_less_p (*vr0min, vr1max) == 1
- || operand_equal_p (*vr0min, vr1max, 0))
-- && operand_less_p (vr1min, *vr0min) == 1)
-+ && operand_less_p (vr1min, *vr0min) == 1
-+ && operand_less_p (vr1max, *vr0max) == 1)
- {
- /* ( [ ) ] or ( )[ ] */
- if (*vr0type == VR_RANGE
-Index: gcc/loop-unswitch.c
-===================================================================
---- a/src/gcc/loop-unswitch.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/loop-unswitch.c (.../branches/gcc-4_8-branch)
-@@ -191,6 +191,7 @@
- if (!test)
- return NULL_RTX;
-
-+ mode = VOIDmode;
- for (i = 0; i < 2; i++)
- {
- op[i] = XEXP (test, i);
-@@ -205,11 +206,15 @@
- return NULL_RTX;
-
- op[i] = get_iv_value (&iv, const0_rtx);
-+ if (iv.extend != IV_UNKNOWN_EXTEND
-+ && iv.mode != iv.extend_mode)
-+ op[i] = lowpart_subreg (iv.mode, op[i], iv.extend_mode);
-+ if (mode == VOIDmode)
-+ mode = iv.mode;
-+ else
-+ gcc_assert (mode == iv.mode);
- }
-
-- mode = GET_MODE (op[0]);
-- if (mode == VOIDmode)
-- mode = GET_MODE (op[1]);
- if (GET_MODE_CLASS (mode) == MODE_CC)
- {
- if (at != BB_END (bb))
-Index: gcc/tree-ssa-loop-im.c
-===================================================================
---- a/src/gcc/tree-ssa-loop-im.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-loop-im.c (.../branches/gcc-4_8-branch)
-@@ -1190,6 +1190,67 @@
- fini_walk_dominator_tree (&walk_data);
- }
-
-+/* Return true if CODE is an operation that when operating on signed
-+ integer types involves undefined behavior on overflow and the
-+ operation can be expressed with unsigned arithmetic. */
-+
-+static bool
-+arith_code_with_undefined_signed_overflow (tree_code code)
-+{
-+ switch (code)
-+ {
-+ case PLUS_EXPR:
-+ case MINUS_EXPR:
-+ case MULT_EXPR:
-+ case NEGATE_EXPR:
-+ case POINTER_PLUS_EXPR:
-+ return true;
-+ default:
-+ return false;
-+ }
-+}
-+
-+/* Rewrite STMT, an assignment with a signed integer or pointer arithmetic
-+ operation that can be transformed to unsigned arithmetic by converting
-+ its operand, carrying out the operation in the corresponding unsigned
-+ type and converting the result back to the original type.
-+
-+ Returns a sequence of statements that replace STMT and also contain
-+ a modified form of STMT itself. */
-+
-+static gimple_seq
-+rewrite_to_defined_overflow (gimple stmt)
-+{
-+ if (dump_file && (dump_flags & TDF_DETAILS))
-+ {
-+ fprintf (dump_file, "rewriting stmt with undefined signed "
-+ "overflow ");
-+ print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM);
-+ }
-+
-+ tree lhs = gimple_assign_lhs (stmt);
-+ tree type = unsigned_type_for (TREE_TYPE (lhs));
-+ gimple_seq stmts = NULL;
-+ for (unsigned i = 1; i < gimple_num_ops (stmt); ++i)
-+ {
-+ gimple_seq stmts2 = NULL;
-+ gimple_set_op (stmt, i,
-+ force_gimple_operand (fold_convert (type,
-+ gimple_op (stmt, i)),
-+ &stmts2, true, NULL_TREE));
-+ gimple_seq_add_seq (&stmts, stmts2);
-+ }
-+ gimple_assign_set_lhs (stmt, make_ssa_name (type, stmt));
-+ if (gimple_assign_rhs_code (stmt) == POINTER_PLUS_EXPR)
-+ gimple_assign_set_rhs_code (stmt, PLUS_EXPR);
-+ gimple_seq_add_stmt (&stmts, stmt);
-+ gimple cvt = gimple_build_assign_with_ops
-+ (NOP_EXPR, lhs, gimple_assign_lhs (stmt), NULL_TREE);
-+ gimple_seq_add_stmt (&stmts, cvt);
-+
-+ return stmts;
-+}
-+
- /* Hoist the statements in basic block BB out of the loops prescribed by
- data stored in LIM_DATA structures associated with each statement. Callback
- for walk_dominator_tree. */
-@@ -1321,7 +1382,21 @@
- }
- }
- gsi_remove (&bsi, false);
-- gsi_insert_on_edge (e, stmt);
-+ /* In case this is a stmt that is not unconditionally executed
-+ when the target loop header is executed and the stmt may
-+ invoke undefined integer or pointer overflow rewrite it to
-+ unsigned arithmetic. */
-+ if (is_gimple_assign (stmt)
-+ && INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_lhs (stmt)))
-+ && TYPE_OVERFLOW_UNDEFINED (TREE_TYPE (gimple_assign_lhs (stmt)))
-+ && arith_code_with_undefined_signed_overflow
-+ (gimple_assign_rhs_code (stmt))
-+ && (!ALWAYS_EXECUTED_IN (bb)
-+ || !(ALWAYS_EXECUTED_IN (bb) == level
-+ || flow_loop_nested_p (ALWAYS_EXECUTED_IN (bb), level))))
-+ gsi_insert_seq_on_edge (e, rewrite_to_defined_overflow (stmt));
-+ else
-+ gsi_insert_on_edge (e, stmt);
- }
- }
-
-@@ -1992,6 +2067,7 @@
- gimple_stmt_iterator gsi;
- gimple stmt;
- struct prev_flag_edges *prev_edges = (struct prev_flag_edges *) ex->aux;
-+ bool irr = ex->flags & EDGE_IRREDUCIBLE_LOOP;
-
- /* ?? Insert store after previous store if applicable. See note
- below. */
-@@ -2006,8 +2082,9 @@
- old_dest = ex->dest;
- new_bb = split_edge (ex);
- then_bb = create_empty_bb (new_bb);
-- if (current_loops && new_bb->loop_father)
-- add_bb_to_loop (then_bb, new_bb->loop_father);
-+ if (irr)
-+ then_bb->flags = BB_IRREDUCIBLE_LOOP;
-+ add_bb_to_loop (then_bb, new_bb->loop_father);
-
- gsi = gsi_start_bb (new_bb);
- stmt = gimple_build_cond (NE_EXPR, flag, boolean_false_node,
-@@ -2019,9 +2096,12 @@
- stmt = gimple_build_assign (unshare_expr (mem), tmp_var);
- gsi_insert_after (&gsi, stmt, GSI_CONTINUE_LINKING);
-
-- make_edge (new_bb, then_bb, EDGE_TRUE_VALUE);
-- make_edge (new_bb, old_dest, EDGE_FALSE_VALUE);
-- then_old_edge = make_edge (then_bb, old_dest, EDGE_FALLTHRU);
-+ make_edge (new_bb, then_bb,
-+ EDGE_TRUE_VALUE | (irr ? EDGE_IRREDUCIBLE_LOOP : 0));
-+ make_edge (new_bb, old_dest,
-+ EDGE_FALSE_VALUE | (irr ? EDGE_IRREDUCIBLE_LOOP : 0));
-+ then_old_edge = make_edge (then_bb, old_dest,
-+ EDGE_FALLTHRU | (irr ? EDGE_IRREDUCIBLE_LOOP : 0));
-
- set_immediate_dominator (CDI_DOMINATORS, then_bb, new_bb);
-
-Index: gcc/tree-ssa-tail-merge.c
-===================================================================
---- a/src/gcc/tree-ssa-tail-merge.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-tail-merge.c (.../branches/gcc-4_8-branch)
-@@ -297,7 +297,8 @@
- tree val;
- def_operand_p def_p;
-
-- if (gimple_has_side_effects (stmt))
-+ if (gimple_has_side_effects (stmt)
-+ || gimple_vdef (stmt) != NULL_TREE)
- return false;
-
- def_p = SINGLE_SSA_DEF_OPERAND (stmt, SSA_OP_DEF);
-Index: gcc/cgraphbuild.c
-===================================================================
---- a/src/gcc/cgraphbuild.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cgraphbuild.c (.../branches/gcc-4_8-branch)
-@@ -73,7 +73,7 @@
- decl = get_base_var (*tp);
- if (TREE_CODE (decl) == FUNCTION_DECL)
- {
-- struct cgraph_node *node = cgraph_get_create_node (decl);
-+ struct cgraph_node *node = cgraph_get_create_real_symbol_node (decl);
- if (!ctx->only_vars)
- cgraph_mark_address_taken_node (node);
- ipa_record_reference ((symtab_node)ctx->varpool_node,
-@@ -143,7 +143,7 @@
- {
- struct cgraph_node *per_node;
-
-- per_node = cgraph_get_create_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl));
-+ per_node = cgraph_get_create_real_symbol_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl));
- ipa_record_reference ((symtab_node)node, (symtab_node)per_node, IPA_REF_ADDR, NULL);
- cgraph_mark_address_taken_node (per_node);
- }
-@@ -218,12 +218,12 @@
- /* Mark address taken in STMT. */
-
- static bool
--mark_address (gimple stmt, tree addr, void *data)
-+mark_address (gimple stmt, tree addr, tree, void *data)
- {
- addr = get_base_address (addr);
- if (TREE_CODE (addr) == FUNCTION_DECL)
- {
-- struct cgraph_node *node = cgraph_get_create_node (addr);
-+ struct cgraph_node *node = cgraph_get_create_real_symbol_node (addr);
- cgraph_mark_address_taken_node (node);
- ipa_record_reference ((symtab_node)data,
- (symtab_node)node,
-@@ -245,7 +245,7 @@
- /* Mark load of T. */
-
- static bool
--mark_load (gimple stmt, tree t, void *data)
-+mark_load (gimple stmt, tree t, tree, void *data)
- {
- t = get_base_address (t);
- if (t && TREE_CODE (t) == FUNCTION_DECL)
-@@ -252,7 +252,7 @@
- {
- /* ??? This can happen on platforms with descriptors when these are
- directly manipulated in the code. Pretend that it's an address. */
-- struct cgraph_node *node = cgraph_get_create_node (t);
-+ struct cgraph_node *node = cgraph_get_create_real_symbol_node (t);
- cgraph_mark_address_taken_node (node);
- ipa_record_reference ((symtab_node)data,
- (symtab_node)node,
-@@ -273,7 +273,7 @@
- /* Mark store of T. */
-
- static bool
--mark_store (gimple stmt, tree t, void *data)
-+mark_store (gimple stmt, tree t, tree, void *data)
- {
- t = get_base_address (t);
- if (t && TREE_CODE (t) == VAR_DECL
-@@ -330,7 +330,7 @@
- {
- tree fn = gimple_omp_parallel_child_fn (stmt);
- ipa_record_reference ((symtab_node)node,
-- (symtab_node)cgraph_get_create_node (fn),
-+ (symtab_node)cgraph_get_create_real_symbol_node (fn),
- IPA_REF_ADDR, stmt);
- }
- if (gimple_code (stmt) == GIMPLE_OMP_TASK)
-@@ -338,12 +338,12 @@
- tree fn = gimple_omp_task_child_fn (stmt);
- if (fn)
- ipa_record_reference ((symtab_node)node,
-- (symtab_node) cgraph_get_create_node (fn),
-+ (symtab_node) cgraph_get_create_real_symbol_node (fn),
- IPA_REF_ADDR, stmt);
- fn = gimple_omp_task_copy_fn (stmt);
- if (fn)
- ipa_record_reference ((symtab_node)node,
-- (symtab_node)cgraph_get_create_node (fn),
-+ (symtab_node)cgraph_get_create_real_symbol_node (fn),
- IPA_REF_ADDR, stmt);
- }
- }
-Index: gcc/tree-ssa-uninit.c
-===================================================================
---- a/src/gcc/tree-ssa-uninit.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-uninit.c (.../branches/gcc-4_8-branch)
-@@ -36,6 +36,7 @@
- #include "hashtab.h"
- #include "tree-pass.h"
- #include "diagnostic-core.h"
-+#include "params.h"
-
- /* This implements the pass that does predicate aware warning on uses of
- possibly uninitialized variables. The pass first collects the set of
-@@ -246,8 +247,8 @@
-
- /* Computes the control dependence chains (paths of edges)
- for DEP_BB up to the dominating basic block BB (the head node of a
-- chain should be dominated by it). CD_CHAINS is pointer to a
-- dynamic array holding the result chains. CUR_CD_CHAIN is the current
-+ chain should be dominated by it). CD_CHAINS is pointer to an
-+ array holding the result chains. CUR_CD_CHAIN is the current
- chain being computed. *NUM_CHAINS is total number of chains. The
- function returns true if the information is successfully computed,
- return false if there is no control dependence or not computed. */
-@@ -256,7 +257,8 @@
- compute_control_dep_chain (basic_block bb, basic_block dep_bb,
- vec<edge> *cd_chains,
- size_t *num_chains,
-- vec<edge> *cur_cd_chain)
-+ vec<edge> *cur_cd_chain,
-+ int *num_calls)
- {
- edge_iterator ei;
- edge e;
-@@ -267,6 +269,10 @@
- if (EDGE_COUNT (bb->succs) < 2)
- return false;
-
-+ if (*num_calls > PARAM_VALUE (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS))
-+ return false;
-+ ++*num_calls;
-+
- /* Could use a set instead. */
- cur_chain_len = cur_cd_chain->length ();
- if (cur_chain_len > MAX_CHAIN_LEN)
-@@ -306,7 +312,7 @@
-
- /* Now check if DEP_BB is indirectly control dependent on BB. */
- if (compute_control_dep_chain (cd_bb, dep_bb, cd_chains,
-- num_chains, cur_cd_chain))
-+ num_chains, cur_cd_chain, num_calls))
- {
- found_cd_chain = true;
- break;
-@@ -438,14 +444,12 @@
- basic_block use_bb)
- {
- size_t num_chains = 0, i;
-- vec<edge> *dep_chains = 0;
-+ int num_calls = 0;
-+ vec<edge> dep_chains[MAX_NUM_CHAINS];
- vec<edge> cur_chain = vNULL;
- bool has_valid_pred = false;
- basic_block cd_root = 0;
-
-- typedef vec<edge> vec_edge_heap;
-- dep_chains = XCNEWVEC (vec_edge_heap, MAX_NUM_CHAINS);
--
- /* First find the closest bb that is control equivalent to PHI_BB
- that also dominates USE_BB. */
- cd_root = phi_bb;
-@@ -458,20 +462,16 @@
- break;
- }
-
-- compute_control_dep_chain (cd_root, use_bb,
-- dep_chains, &num_chains,
-- &cur_chain);
-+ compute_control_dep_chain (cd_root, use_bb, dep_chains, &num_chains,
-+ &cur_chain, &num_calls);
-
- has_valid_pred
-- = convert_control_dep_chain_into_preds (dep_chains,
-- num_chains,
-- preds,
-- num_preds);
-+ = convert_control_dep_chain_into_preds (dep_chains, num_chains, preds,
-+ num_preds);
- /* Free individual chain */
- cur_chain.release ();
- for (i = 0; i < num_chains; i++)
- dep_chains[i].release ();
-- free (dep_chains);
- return has_valid_pred;
- }
-
-@@ -539,7 +539,7 @@
- size_t *num_preds, gimple phi)
- {
- size_t num_chains = 0, i, n;
-- vec<edge> *dep_chains = 0;
-+ vec<edge> dep_chains[MAX_NUM_CHAINS];
- vec<edge> cur_chain = vNULL;
- vec<edge> def_edges = vNULL;
- bool has_valid_pred = false;
-@@ -546,9 +546,6 @@
- basic_block phi_bb, cd_root = 0;
- struct pointer_set_t *visited_phis;
-
-- typedef vec<edge> vec_edge_heap;
-- dep_chains = XCNEWVEC (vec_edge_heap, MAX_NUM_CHAINS);
--
- phi_bb = gimple_bb (phi);
- /* First find the closest dominating bb to be
- the control dependence root */
-@@ -567,38 +564,33 @@
- for (i = 0; i < n; i++)
- {
- size_t prev_nc, j;
-+ int num_calls = 0;
- edge opnd_edge;
-
- opnd_edge = def_edges[i];
- prev_nc = num_chains;
-- compute_control_dep_chain (cd_root, opnd_edge->src,
-- dep_chains, &num_chains,
-- &cur_chain);
-- /* Free individual chain */
-- cur_chain.release ();
-+ compute_control_dep_chain (cd_root, opnd_edge->src, dep_chains,
-+ &num_chains, &cur_chain, &num_calls);
-
- /* Now update the newly added chains with
- the phi operand edge: */
- if (EDGE_COUNT (opnd_edge->src->succs) > 1)
- {
-- if (prev_nc == num_chains
-- && num_chains < MAX_NUM_CHAINS)
-- num_chains++;
-+ if (prev_nc == num_chains && num_chains < MAX_NUM_CHAINS)
-+ dep_chains[num_chains++] = vNULL;
- for (j = prev_nc; j < num_chains; j++)
-- {
-- dep_chains[j].safe_push (opnd_edge);
-- }
-+ dep_chains[j].safe_push (opnd_edge);
- }
- }
-
-+ /* Free individual chain */
-+ cur_chain.release ();
-+
- has_valid_pred
-- = convert_control_dep_chain_into_preds (dep_chains,
-- num_chains,
-- preds,
-- num_preds);
-+ = convert_control_dep_chain_into_preds (dep_chains, num_chains, preds,
-+ num_preds);
- for (i = 0; i < num_chains; i++)
- dep_chains[i].release ();
-- free (dep_chains);
- return has_valid_pred;
- }
-
-Index: gcc/tree-ssa-loop-niter.c
-===================================================================
---- a/src/gcc/tree-ssa-loop-niter.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-loop-niter.c (.../branches/gcc-4_8-branch)
-@@ -2075,7 +2075,8 @@
- return NULL;
- }
-
-- if (gimple_code (stmt) != GIMPLE_ASSIGN)
-+ if (gimple_code (stmt) != GIMPLE_ASSIGN
-+ || gimple_assign_rhs_class (stmt) == GIMPLE_TERNARY_RHS)
- return NULL;
-
- code = gimple_assign_rhs_code (stmt);
-@@ -2143,7 +2144,7 @@
- {
- gimple stmt;
-
-- gcc_assert (is_gimple_min_invariant (base));
-+ gcc_checking_assert (is_gimple_min_invariant (base));
-
- if (!x)
- return base;
-@@ -2152,7 +2153,7 @@
- if (gimple_code (stmt) == GIMPLE_PHI)
- return base;
-
-- gcc_assert (is_gimple_assign (stmt));
-+ gcc_checking_assert (is_gimple_assign (stmt));
-
- /* STMT must be either an assignment of a single SSA name or an
- expression involving an SSA name and a constant. Try to fold that
-Index: gcc/c-family/c.opt
-===================================================================
---- a/src/gcc/c-family/c.opt (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c-family/c.opt (.../branches/gcc-4_8-branch)
-@@ -933,7 +933,7 @@
- Recognize GNU-defined keywords
-
- fgnu-runtime
--ObjC ObjC++ Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME)
-+ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME)
- Generate code for GNU runtime environment
-
- fgnu89-inline
-@@ -1007,7 +1007,7 @@
- C++ ObjC++ Ignore Warn(switch %qs is no longer supported)
-
- fnext-runtime
--ObjC ObjC++ Report RejectNegative Var(flag_next_runtime)
-+ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime)
- Generate code for NeXT (Apple Mac OS X) runtime environment
-
- fnil-receivers
-@@ -1025,7 +1025,7 @@
- Treat a throw() exception specification as noexcept to improve code size
-
- fobjc-abi-version=
--ObjC ObjC++ Joined Report RejectNegative UInteger Var(flag_objc_abi)
-+ObjC ObjC++ LTO Joined Report RejectNegative UInteger Var(flag_objc_abi)
- Specify which ABI to use for Objective-C family code and meta-data generation.
-
- ; Generate special '- .cxx_construct' and '- .cxx_destruct' methods
-@@ -1045,7 +1045,7 @@
- Enable Objective-C exception and synchronization syntax
-
- fobjc-gc
--ObjC ObjC++ Var(flag_objc_gc)
-+ObjC ObjC++ LTO Var(flag_objc_gc)
- Enable garbage collection (GC) in Objective-C/Objective-C++ programs
-
- fobjc-nilcheck
-@@ -1105,7 +1105,7 @@
- -fno-pretty-templates Do not pretty-print template specializations as the template signature followed by the arguments
-
- freplace-objc-classes
--ObjC ObjC++ Var(flag_replace_objc_classes)
-+ObjC ObjC++ LTO Var(flag_replace_objc_classes)
- Used in Fix-and-Continue mode to indicate that object files may be swapped in at runtime
-
- frepo
-Index: gcc/c-family/c-opts.c
-===================================================================
---- a/src/gcc/c-family/c-opts.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c-family/c-opts.c (.../branches/gcc-4_8-branch)
-@@ -840,6 +840,12 @@
- if (flag_objc_exceptions && !flag_objc_sjlj_exceptions)
- flag_exceptions = 1;
-
-+ /* If -ffreestanding, -fno-hosted or -fno-builtin then disable
-+ pattern recognition. */
-+ if (!global_options_set.x_flag_tree_loop_distribute_patterns
-+ && flag_no_builtin)
-+ flag_tree_loop_distribute_patterns = 0;
-+
- /* -Woverlength-strings is off by default, but is enabled by -Wpedantic.
- It is never enabled in C++, as the minimum limit is not normative
- in that standard. */
-@@ -1258,17 +1264,18 @@
- {
- size_t i;
-
-- {
-- /* Make sure all of the builtins about to be declared have
-- BUILTINS_LOCATION has their source_location. */
-- source_location builtins_loc = BUILTINS_LOCATION;
-- cpp_force_token_locations (parse_in, &builtins_loc);
-+ cb_file_change (parse_in,
-+ linemap_add (line_table, LC_RENAME, 0,
-+ _("<built-in>"), 0));
-+ /* Make sure all of the builtins about to be declared have
-+ BUILTINS_LOCATION has their source_location. */
-+ source_location builtins_loc = BUILTINS_LOCATION;
-+ cpp_force_token_locations (parse_in, &builtins_loc);
-
-- cpp_init_builtins (parse_in, flag_hosted);
-- c_cpp_builtins (parse_in);
-+ cpp_init_builtins (parse_in, flag_hosted);
-+ c_cpp_builtins (parse_in);
-
-- cpp_stop_forcing_token_locations (parse_in);
-- }
-+ cpp_stop_forcing_token_locations (parse_in);
-
- /* We're about to send user input to cpplib, so make it warn for
- things that we previously (when we sent it internal definitions)
-Index: gcc/c-family/ChangeLog
-===================================================================
---- a/src/gcc/c-family/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c-family/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,78 @@
-+2014-05-06 Richard Biener <rguenther@suse.de>
-+
-+ * c-opts.c (c_common_post_options): For -freestanding,
-+ -fno-hosted and -fno-builtin disable pattern recognition
-+ if not enabled explicitely.
-+
-+2014-04-10 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c++/60689
-+ * c-common.c (add_atomic_size_parameter): When creating new
-+ params vector, push the size argument first.
-+
-+ 2014-03-22 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR debug/60603
-+ * c-opts.c (c_finish_options): Restore cb_file_change call to
-+ <built-in>.
-+
-+ 2014-03-13 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/36282
-+ * c-pragma.c (apply_pragma_weak): Only look at
-+ TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) if
-+ DECL_ASSEMBLER_NAME_SET_P (decl).
-+ (maybe_apply_pending_pragma_weaks): Exit early if
-+ vec_safe_is_empty (pending_weaks) rather than only when
-+ !pending_weaks.
-+ (maybe_apply_pragma_weak): Likewise. If !DECL_ASSEMBLER_NAME_SET_P,
-+ set assembler name back to NULL afterwards.
-+
-+2014-04-07 Dominique d'Humieres <dominiq@lps.ens.fr>
-+
-+ Backport from mainline
-+ 2013-09-14 Iain Sandoe <iains@gcc.gnu.org>
-+
-+ PR target/48094
-+ * c.opt (fgnu-runtime, fnext-runtime, fobjc-abi-version,
-+ fobjc-gc, freplace-objc-classes): Accept for LTO.
-+
-+2014-03-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-02-19 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c/37743
-+ * c-common.c (c_common_nodes_and_builtins): When initializing
-+ c_uint{16,32,64}_type_node, also set corresponding
-+ uint{16,32,64}_type_node to the same value.
-+
-+ 2014-02-12 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c/60101
-+ * c-common.c (merge_tlist): If copy is true, call new_tlist,
-+ if false, add ADD itself, rather than vice versa.
-+ (verify_tree): For COND_EXPR, don't call merge_tlist with non-zero
-+ copy. For SAVE_EXPR, only call merge_tlist once.
-+
-+2013-11-29 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c/59280
-+ * c-common.c (get_priority): If TREE_VALUE (args) is IDENTIFIER_NODE,
-+ goto invalid. If it is error_mark_node, don't issue further
-+ diagnostics.
-+
-+2013-11-04 Marek Polacek <polacek@redhat.com>
-+
-+ Backport from mainline
-+ 2013-11-04 Marek Polacek <polacek@redhat.com>
-+
-+ PR c++/58979
-+ * c-common.c (invalid_indirection_error): Handle RO_ARROW_STAR case.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: gcc/c-family/c-common.c
-===================================================================
---- a/src/gcc/c-family/c-common.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c-family/c-common.c (.../branches/gcc-4_8-branch)
-@@ -2894,7 +2894,7 @@
- }
- if (!found)
- {
-- *end = copy ? add : new_tlist (NULL, add->expr, add->writer);
-+ *end = copy ? new_tlist (NULL, add->expr, add->writer) : add;
- end = &(*end)->next;
- *end = 0;
- }
-@@ -3052,7 +3052,7 @@
- verify_tree (TREE_OPERAND (x, 0), &tmp_before, &tmp_list2, NULL_TREE);
- warn_for_collisions (tmp_list2);
- merge_tlist (pbefore_sp, tmp_before, 0);
-- merge_tlist (pbefore_sp, tmp_list2, 1);
-+ merge_tlist (pbefore_sp, tmp_list2, 0);
-
- tmp_list3 = tmp_nosp = 0;
- verify_tree (TREE_OPERAND (x, 1), &tmp_list3, &tmp_nosp, NULL_TREE);
-@@ -3156,12 +3156,7 @@
- warn_for_collisions (tmp_nosp);
-
- tmp_list3 = 0;
-- while (tmp_nosp)
-- {
-- struct tlist *t = tmp_nosp;
-- tmp_nosp = t->next;
-- merge_tlist (&tmp_list3, t, 0);
-- }
-+ merge_tlist (&tmp_list3, tmp_nosp, 0);
- t->cache_before_sp = tmp_before;
- t->cache_after_sp = tmp_list3;
- }
-@@ -5511,13 +5506,13 @@
- uint8_type_node =
- TREE_TYPE (identifier_global_value (c_get_ident (UINT8_TYPE)));
- if (UINT16_TYPE)
-- c_uint16_type_node =
-+ c_uint16_type_node = uint16_type_node =
- TREE_TYPE (identifier_global_value (c_get_ident (UINT16_TYPE)));
- if (UINT32_TYPE)
-- c_uint32_type_node =
-+ c_uint32_type_node = uint32_type_node =
- TREE_TYPE (identifier_global_value (c_get_ident (UINT32_TYPE)));
- if (UINT64_TYPE)
-- c_uint64_type_node =
-+ c_uint64_type_node = uint64_type_node =
- TREE_TYPE (identifier_global_value (c_get_ident (UINT64_TYPE)));
- if (INT_LEAST8_TYPE)
- int_least8_type_node =
-@@ -6917,6 +6912,10 @@
- }
-
- arg = TREE_VALUE (args);
-+ if (TREE_CODE (arg) == IDENTIFIER_NODE)
-+ goto invalid;
-+ if (arg == error_mark_node)
-+ return DEFAULT_INIT_PRIORITY;
- arg = default_conversion (arg);
- if (!host_integerp (arg, /*pos=*/0)
- || !INTEGRAL_TYPE_P (TREE_TYPE (arg)))
-@@ -9763,6 +9762,11 @@
- "invalid type argument of %<->%> (have %qT)",
- type);
- break;
-+ case RO_ARROW_STAR:
-+ error_at (loc,
-+ "invalid type argument of %<->*%> (have %qT)",
-+ type);
-+ break;
- case RO_IMPLICIT_CONVERSION:
- error_at (loc,
- "invalid type argument of implicit conversion (have %qT)",
-@@ -10198,6 +10202,7 @@
-
- len = params->length ();
- vec_alloc (v, len + 1);
-+ v->quick_push (build_int_cst (size_type_node, n));
- for (z = 0; z < len; z++)
- v->quick_push ((*params)[z]);
- f = build_function_call_vec (loc, function, v, NULL);
-Index: gcc/c-family/c-pragma.c
-===================================================================
---- a/src/gcc/c-family/c-pragma.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c-family/c-pragma.c (.../branches/gcc-4_8-branch)
-@@ -259,6 +259,7 @@
-
- if (SUPPORTS_WEAK && DECL_EXTERNAL (decl) && TREE_USED (decl)
- && !DECL_WEAK (decl) /* Don't complain about a redundant #pragma. */
-+ && DECL_ASSEMBLER_NAME_SET_P (decl)
- && TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
- warning (OPT_Wpragmas, "applying #pragma weak %q+D after first use "
- "results in unspecified behavior", decl);
-@@ -276,7 +277,7 @@
- /* Avoid asking for DECL_ASSEMBLER_NAME when it's not needed. */
-
- /* No weak symbols pending, take the short-cut. */
-- if (!pending_weaks)
-+ if (vec_safe_is_empty (pending_weaks))
- return;
- /* If it's not visible outside this file, it doesn't matter whether
- it's weak. */
-@@ -288,7 +289,13 @@
- if (TREE_CODE (decl) != FUNCTION_DECL && TREE_CODE (decl) != VAR_DECL)
- return;
-
-- id = DECL_ASSEMBLER_NAME (decl);
-+ if (DECL_ASSEMBLER_NAME_SET_P (decl))
-+ id = DECL_ASSEMBLER_NAME (decl);
-+ else
-+ {
-+ id = DECL_ASSEMBLER_NAME (decl);
-+ SET_DECL_ASSEMBLER_NAME (decl, NULL_TREE);
-+ }
-
- FOR_EACH_VEC_ELT (*pending_weaks, i, pe)
- if (id == pe->name)
-@@ -309,7 +316,7 @@
- pending_weak *pe;
- symtab_node target;
-
-- if (!pending_weaks)
-+ if (vec_safe_is_empty (pending_weaks))
- return;
-
- FOR_EACH_VEC_ELT (*pending_weaks, i, pe)
-Index: gcc/c/c-typeck.c
-===================================================================
---- a/src/gcc/c/c-typeck.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c/c-typeck.c (.../branches/gcc-4_8-branch)
-@@ -2666,7 +2666,7 @@
- vec_alloc (v, list_length (params));
- for (; params; params = TREE_CHAIN (params))
- v->quick_push (TREE_VALUE (params));
-- ret = build_function_call_vec (loc, function, v, NULL);
-+ ret = c_build_function_call_vec (loc, function, v, NULL);
- vec_free (v);
- return ret;
- }
-@@ -2705,14 +2705,6 @@
- /* Convert anything with function type to a pointer-to-function. */
- if (TREE_CODE (function) == FUNCTION_DECL)
- {
-- /* Implement type-directed function overloading for builtins.
-- resolve_overloaded_builtin and targetm.resolve_overloaded_builtin
-- handle all the type checking. The result is a complete expression
-- that implements this function call. */
-- tem = resolve_overloaded_builtin (loc, function, params);
-- if (tem)
-- return tem;
--
- name = DECL_NAME (function);
-
- if (flag_tm)
-@@ -2863,6 +2855,30 @@
- }
- return require_complete_type (result);
- }
-+
-+/* Like build_function_call_vec, but call also resolve_overloaded_builtin. */
-+
-+tree
-+c_build_function_call_vec (location_t loc, tree function,
-+ vec<tree, va_gc> *params,
-+ vec<tree, va_gc> *origtypes)
-+{
-+ /* Strip NON_LVALUE_EXPRs, etc., since we aren't using as an lvalue. */
-+ STRIP_TYPE_NOPS (function);
-+
-+ /* Convert anything with function type to a pointer-to-function. */
-+ if (TREE_CODE (function) == FUNCTION_DECL)
-+ {
-+ /* Implement type-directed function overloading for builtins.
-+ resolve_overloaded_builtin and targetm.resolve_overloaded_builtin
-+ handle all the type checking. The result is a complete expression
-+ that implements this function call. */
-+ tree tem = resolve_overloaded_builtin (loc, function, params);
-+ if (tem)
-+ return tem;
-+ }
-+ return build_function_call_vec (loc, function, params, origtypes);
-+}
-
- /* Convert the argument expressions in the vector VALUES
- to the types in the list TYPELIST.
-@@ -3629,7 +3645,8 @@
- /* Report invalid types. */
-
- if (typecode != POINTER_TYPE && typecode != FIXED_POINT_TYPE
-- && typecode != INTEGER_TYPE && typecode != REAL_TYPE)
-+ && typecode != INTEGER_TYPE && typecode != REAL_TYPE
-+ && typecode != VECTOR_TYPE)
- {
- if (code == PREINCREMENT_EXPR || code == POSTINCREMENT_EXPR)
- error_at (location, "wrong type argument to increment");
-@@ -3694,7 +3711,9 @@
- }
- else
- {
-- inc = integer_one_node;
-+ inc = (TREE_CODE (argtype) == VECTOR_TYPE
-+ ? build_one_cst (argtype)
-+ : integer_one_node);
- inc = convert (argtype, inc);
- }
-
-@@ -4331,8 +4350,10 @@
- {
- if (int_operands)
- {
-- op1 = remove_c_maybe_const_expr (op1);
-- op2 = remove_c_maybe_const_expr (op2);
-+ /* Use c_fully_fold here, since C_MAYBE_CONST_EXPR might be
-+ nested inside of the expression. */
-+ op1 = c_fully_fold (op1, false, NULL);
-+ op2 = c_fully_fold (op2, false, NULL);
- }
- ret = build3 (COND_EXPR, result_type, ifexp, op1, op2);
- if (int_operands)
-@@ -10618,7 +10639,8 @@
- "%qE has invalid type for %<reduction%>", t);
- remove = true;
- }
-- else if (FLOAT_TYPE_P (TREE_TYPE (t)))
-+ else if (FLOAT_TYPE_P (TREE_TYPE (t))
-+ || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)
- {
- enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c);
- const char *r_name = NULL;
-@@ -10628,8 +10650,14 @@
- case PLUS_EXPR:
- case MULT_EXPR:
- case MINUS_EXPR:
-+ break;
- case MIN_EXPR:
-+ if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)
-+ r_name = "min";
-+ break;
- case MAX_EXPR:
-+ if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)
-+ r_name = "max";
- break;
- case BIT_AND_EXPR:
- r_name = "&";
-@@ -10641,10 +10669,12 @@
- r_name = "|";
- break;
- case TRUTH_ANDIF_EXPR:
-- r_name = "&&";
-+ if (FLOAT_TYPE_P (TREE_TYPE (t)))
-+ r_name = "&&";
- break;
- case TRUTH_ORIF_EXPR:
-- r_name = "||";
-+ if (FLOAT_TYPE_P (TREE_TYPE (t)))
-+ r_name = "||";
- break;
- default:
- gcc_unreachable ();
-Index: gcc/c/c-tree.h
-===================================================================
---- a/src/gcc/c/c-tree.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c/c-tree.h (.../branches/gcc-4_8-branch)
-@@ -640,6 +640,8 @@
- extern tree c_finish_omp_clauses (tree);
- extern tree c_build_va_arg (location_t, tree, tree);
- extern tree c_finish_transaction (location_t, tree, int);
-+extern tree c_build_function_call_vec (location_t, tree, vec<tree, va_gc> *,
-+ vec<tree, va_gc> *);
-
- /* Set to 0 at beginning of a function definition, set to 1 if
- a return statement that specifies a return value is seen. */
-Index: gcc/c/ChangeLog
-===================================================================
---- a/src/gcc/c/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,49 @@
-+2014-04-10 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c++/60689
-+ * c-tree.h (c_build_function_call_vec): New prototype.
-+ * c-typeck.c (build_function_call_vec): Don't call
-+ resolve_overloaded_builtin here.
-+ (c_build_function_call_vec): New wrapper function around
-+ build_function_call_vec. Call resolve_overloaded_builtin here.
-+ (convert_lvalue_to_rvalue, build_function_call, build_atomic_assign):
-+ Call c_build_function_call_vec instead of build_function_call_vec.
-+ * c-parser.c (c_parser_postfix_expression_after_primary): Likewise.
-+ * c-decl.c (finish_decl): Likewise.
-+
-+2014-01-23 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/58809
-+ * c-typeck.c (c_finish_omp_clause): Reject MIN_EXPR, MAX_EXPR,
-+ BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs.
-+
-+2014-01-22 Marek Polacek <polacek@redhat.com>
-+
-+ Backport from mainline
-+ 2014-01-22 Marek Polacek <polacek@redhat.com>
-+
-+ PR c/59891
-+ * c-typeck.c (build_conditional_expr): Call c_fully_fold instead
-+ of remove_c_maybe_const_expr on op1 and op2.
-+
-+2013-12-03 Marek Polacek <polacek@redhat.com>
-+
-+ Backport from mainline
-+ 2013-12-03 Marek Polacek <polacek@redhat.com>
-+
-+ PR c/59351
-+ * c-decl.c (build_compound_literal): Allow compound literals with
-+ empty initial value.
-+
-+2013-11-27 Tom de Vries <tom@codesourcery.com>
-+ Marc Glisse <marc.glisse@inria.fr>
-+
-+ PR c++/59032
-+ * c-typeck.c (build_unary_op): Allow vector increment and decrement.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: gcc/c/c-decl.c
-===================================================================
---- a/src/gcc/c/c-decl.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c/c-decl.c (.../branches/gcc-4_8-branch)
-@@ -4507,8 +4507,8 @@
- cleanup = build_unary_op (input_location, ADDR_EXPR, decl, 0);
- vec_alloc (v, 1);
- v->quick_push (cleanup);
-- cleanup = build_function_call_vec (DECL_SOURCE_LOCATION (decl),
-- cleanup_decl, v, NULL);
-+ cleanup = c_build_function_call_vec (DECL_SOURCE_LOCATION (decl),
-+ cleanup_decl, v, NULL);
- vec_free (v);
-
- /* Don't warn about decl unused; the cleanup uses it. */
-@@ -4632,7 +4632,9 @@
- {
- int failure = complete_array_type (&TREE_TYPE (decl),
- DECL_INITIAL (decl), true);
-- gcc_assert (!failure);
-+ /* If complete_array_type returns 3, it means that the
-+ initial value of the compound literal is empty. Allow it. */
-+ gcc_assert (failure == 0 || failure == 3);
-
- type = TREE_TYPE (decl);
- TREE_TYPE (DECL_INITIAL (decl)) = type;
-Index: gcc/c/c-parser.c
-===================================================================
---- a/src/gcc/c/c-parser.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/c/c-parser.c (.../branches/gcc-4_8-branch)
-@@ -6904,8 +6904,8 @@
- sizeof_ptr_memacc_comptypes);
- /* FIXME diagnostics: Ideally we want the FUNCNAME, not the
- "(" after the FUNCNAME, which is what we have now. */
-- expr.value = build_function_call_vec (op_loc, expr.value, exprlist,
-- origtypes);
-+ expr.value = c_build_function_call_vec (op_loc, expr.value, exprlist,
-+ origtypes);
- expr.original_code = ERROR_MARK;
- if (TREE_CODE (expr.value) == INTEGER_CST
- && TREE_CODE (orig_expr.value) == FUNCTION_DECL
-Index: gcc/cgraph.c
-===================================================================
---- a/src/gcc/cgraph.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cgraph.c (.../branches/gcc-4_8-branch)
-@@ -2596,4 +2596,47 @@
- FOR_EACH_FUNCTION (node)
- verify_cgraph_node (node);
- }
-+
-+/* Create external decl node for DECL.
-+ The difference i nbetween cgraph_get_create_node and
-+ cgraph_get_create_real_symbol_node is that cgraph_get_create_node
-+ may return inline clone, while cgraph_get_create_real_symbol_node
-+ will create a new node in this case.
-+ FIXME: This function should be removed once clones are put out of decl
-+ hash. */
-+
-+struct cgraph_node *
-+cgraph_get_create_real_symbol_node (tree decl)
-+{
-+ struct cgraph_node *first_clone = cgraph_get_node (decl);
-+ struct cgraph_node *node;
-+ /* create symbol table node. even if inline clone exists, we can not take
-+ it as a target of non-inlined call. */
-+ node = cgraph_get_node (decl);
-+ if (node && !node->global.inlined_to)
-+ return node;
-+
-+ node = cgraph_create_node (decl);
-+
-+ /* ok, we previously inlined the function, then removed the offline copy and
-+ now we want it back for external call. this can happen when devirtualizing
-+ while inlining function called once that happens after extern inlined and
-+ virtuals are already removed. in this case introduce the external node
-+ and make it available for call. */
-+ if (first_clone)
-+ {
-+ first_clone->clone_of = node;
-+ node->clones = first_clone;
-+ symtab_prevail_in_asm_name_hash ((symtab_node) node);
-+ symtab_insert_node_to_hashtable ((symtab_node) node);
-+ if (dump_file)
-+ fprintf (dump_file, "Introduced new external node "
-+ "(%s/%i) and turned into root of the clone tree.\n",
-+ xstrdup (cgraph_node_name (node)), node->uid);
-+ }
-+ else if (dump_file)
-+ fprintf (dump_file, "Introduced new external node "
-+ "(%s/%i).\n", xstrdup (cgraph_node_name (node)), node->uid);
-+ return node;
-+}
- #include "gt-cgraph.h"
-Index: gcc/cgraph.h
-===================================================================
---- a/src/gcc/cgraph.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cgraph.h (.../branches/gcc-4_8-branch)
-@@ -575,6 +575,7 @@
- struct cgraph_node * cgraph_create_node (tree);
- struct cgraph_node * cgraph_create_empty_node (void);
- struct cgraph_node * cgraph_get_create_node (tree);
-+struct cgraph_node * cgraph_get_create_real_symbol_node (tree);
- struct cgraph_node * cgraph_same_body_alias (struct cgraph_node *, tree, tree);
- struct cgraph_node * cgraph_add_thunk (struct cgraph_node *, tree, tree, bool, HOST_WIDE_INT,
- HOST_WIDE_INT, tree, tree);
-Index: gcc/optabs.c
-===================================================================
---- a/src/gcc/optabs.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/optabs.c (.../branches/gcc-4_8-branch)
-@@ -3376,7 +3376,8 @@
- {
- rtx temp;
-
-- if (! flag_trapv)
-+ if (GET_MODE_CLASS (mode) != MODE_INT
-+ || ! flag_trapv)
- result_unsignedp = 1;
-
- /* First try to do it with a special abs instruction. */
-@@ -3399,7 +3400,8 @@
- {
- rtx last = get_last_insn ();
-
-- temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0);
-+ temp = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab,
-+ op0, NULL_RTX, 0);
- if (temp != 0)
- temp = expand_binop (mode, smax_optab, op0, temp, target, 0,
- OPTAB_WIDEN);
-@@ -3441,7 +3443,8 @@
- {
- rtx temp, op1;
-
-- if (! flag_trapv)
-+ if (GET_MODE_CLASS (mode) != MODE_INT
-+ || ! flag_trapv)
- result_unsignedp = 1;
-
- temp = expand_abs_nojump (mode, op0, target, result_unsignedp);
-@@ -4558,8 +4561,11 @@
- if (!COMPARISON_P (comparison))
- return NULL_RTX;
-
-+ /* State variables we need to save and restore if cmove can't be used. */
-+ int save_pending_stack_adjust = pending_stack_adjust;
-+ int save_stack_pointer_delta = stack_pointer_delta;
-+ last = get_last_insn ();
- do_pending_stack_adjust ();
-- last = get_last_insn ();
- prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1),
- GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN,
- &comparison, &cmode);
-@@ -4579,6 +4585,8 @@
- }
- }
- delete_insns_since (last);
-+ pending_stack_adjust = save_pending_stack_adjust;
-+ stack_pointer_delta = save_stack_pointer_delta;
- return NULL_RTX;
- }
-
-@@ -6233,7 +6241,7 @@
-
- /* If the optabs changed, record it. */
- if (memcmp (tmp_optabs, this_target_optabs, sizeof (struct target_optabs)))
-- TREE_OPTIMIZATION_OPTABS (optnode) = (unsigned char *) tmp_optabs;
-+ TREE_OPTIMIZATION_OPTABS (optnode) = tmp_optabs;
- else
- {
- TREE_OPTIMIZATION_OPTABS (optnode) = NULL;
-@@ -7035,8 +7043,7 @@
-
- create_output_operand (&ops[0], target, mode);
- create_fixed_operand (&ops[1], mem);
-- /* VAL may have been promoted to a wider mode. Shrink it if so. */
-- create_convert_operand_to (&ops[2], val, mode, true);
-+ create_input_operand (&ops[2], val, mode);
- create_integer_operand (&ops[3], model);
- if (maybe_expand_insn (icode, 4, ops))
- return ops[0].value;
-@@ -7075,8 +7082,7 @@
- struct expand_operand ops[3];
- create_output_operand (&ops[0], target, mode);
- create_fixed_operand (&ops[1], mem);
-- /* VAL may have been promoted to a wider mode. Shrink it if so. */
-- create_convert_operand_to (&ops[2], val, mode, true);
-+ create_input_operand (&ops[2], val, mode);
- if (maybe_expand_insn (icode, 3, ops))
- return ops[0].value;
- }
-@@ -7118,8 +7124,6 @@
- {
- if (!target || !register_operand (target, mode))
- target = gen_reg_rtx (mode);
-- if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode)
-- val = convert_modes (mode, GET_MODE (val), val, 1);
- if (expand_compare_and_swap_loop (mem, target, val, NULL_RTX))
- return target;
- }
-@@ -7331,8 +7335,8 @@
- create_output_operand (&ops[0], target_bool, bool_mode);
- create_output_operand (&ops[1], target_oval, mode);
- create_fixed_operand (&ops[2], mem);
-- create_convert_operand_to (&ops[3], expected, mode, true);
-- create_convert_operand_to (&ops[4], desired, mode, true);
-+ create_input_operand (&ops[3], expected, mode);
-+ create_input_operand (&ops[4], desired, mode);
- create_integer_operand (&ops[5], is_weak);
- create_integer_operand (&ops[6], succ_model);
- create_integer_operand (&ops[7], fail_model);
-@@ -7353,8 +7357,8 @@
-
- create_output_operand (&ops[0], target_oval, mode);
- create_fixed_operand (&ops[1], mem);
-- create_convert_operand_to (&ops[2], expected, mode, true);
-- create_convert_operand_to (&ops[3], desired, mode, true);
-+ create_input_operand (&ops[2], expected, mode);
-+ create_input_operand (&ops[3], desired, mode);
- if (!maybe_expand_insn (icode, 4, ops))
- return false;
-
-Index: gcc/DATESTAMP
-===================================================================
---- a/src/gcc/DATESTAMP (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/DATESTAMP (.../branches/gcc-4_8-branch)
-@@ -1 +1 @@
--20131016
-+20140516
-Index: gcc/value-prof.c
-===================================================================
---- a/src/gcc/value-prof.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/value-prof.c (.../branches/gcc-4_8-branch)
-@@ -1270,8 +1270,7 @@
-
- /* Build an EH edge for the direct call if necessary. */
- lp_nr = lookup_stmt_eh_lp (icall_stmt);
-- if (lp_nr != 0
-- && stmt_could_throw_p (dcall_stmt))
-+ if (lp_nr > 0 && stmt_could_throw_p (dcall_stmt))
- {
- edge e_eh, e;
- edge_iterator ei;
-Index: gcc/tree.c
-===================================================================
---- a/src/gcc/tree.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree.c (.../branches/gcc-4_8-branch)
-@@ -1619,6 +1619,60 @@
- }
- }
-
-+/* Return an integer of type TYPE containing all 1's in as much precision as
-+ it contains, or a complex or vector whose subparts are such integers. */
-+
-+tree
-+build_all_ones_cst (tree type)
-+{
-+ if (TREE_CODE (type) == COMPLEX_TYPE)
-+ {
-+ tree scalar = build_all_ones_cst (TREE_TYPE (type));
-+ return build_complex (type, scalar, scalar);
-+ }
-+ else
-+ return build_minus_one_cst (type);
-+}
-+
-+/* Return a constant of arithmetic type TYPE which is the
-+ opposite of the multiplicative identity of the set TYPE. */
-+
-+tree
-+build_minus_one_cst (tree type)
-+{
-+ switch (TREE_CODE (type))
-+ {
-+ case INTEGER_TYPE: case ENUMERAL_TYPE: case BOOLEAN_TYPE:
-+ case POINTER_TYPE: case REFERENCE_TYPE:
-+ case OFFSET_TYPE:
-+ return build_int_cst (type, -1);
-+
-+ case REAL_TYPE:
-+ return build_real (type, dconstm1);
-+
-+ case FIXED_POINT_TYPE:
-+ /* We can only generate 1 for accum types. */
-+ gcc_assert (ALL_SCALAR_ACCUM_MODE_P (TYPE_MODE (type)));
-+ return build_fixed (type, fixed_from_double_int (double_int_minus_one,
-+ TYPE_MODE (type)));
-+
-+ case VECTOR_TYPE:
-+ {
-+ tree scalar = build_minus_one_cst (TREE_TYPE (type));
-+
-+ return build_vector_from_val (type, scalar);
-+ }
-+
-+ case COMPLEX_TYPE:
-+ return build_complex (type,
-+ build_minus_one_cst (TREE_TYPE (type)),
-+ build_zero_cst (TREE_TYPE (type)));
-+
-+ default:
-+ gcc_unreachable ();
-+ }
-+}
-+
- /* Build 0 constant of type TYPE. This is used by constructor folding
- and thus the constant should be represented in memory by
- zero(es). */
-Index: gcc/tree.h
-===================================================================
---- a/src/gcc/tree.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree.h (.../branches/gcc-4_8-branch)
-@@ -3589,7 +3589,7 @@
-
- /* Target optabs for this set of optimization options. This is of
- type `struct target_optabs *'. */
-- unsigned char *GTY ((atomic)) optabs;
-+ void *GTY ((atomic)) optabs;
-
- /* The value of this_target_optabs against which the optabs above were
- generated. */
-@@ -4760,6 +4760,8 @@
- extern tree build_real_from_int_cst (tree, const_tree);
- extern tree build_complex (tree, tree, tree);
- extern tree build_one_cst (tree);
-+extern tree build_minus_one_cst (tree);
-+extern tree build_all_ones_cst (tree);
- extern tree build_zero_cst (tree);
- extern tree build_string (int, const char *);
- extern tree build_tree_list_stat (tree, tree MEM_STAT_DECL);
-@@ -5854,6 +5856,7 @@
- extern tree fold_builtin_fputs (location_t, tree, tree, bool, bool, tree);
- extern tree fold_builtin_strcpy (location_t, tree, tree, tree, tree);
- extern tree fold_builtin_strncpy (location_t, tree, tree, tree, tree, tree);
-+extern tree fold_builtin_strcat (location_t, tree, tree, tree);
- extern tree fold_builtin_memory_chk (location_t, tree, tree, tree, tree, tree, tree, bool,
- enum built_in_function);
- extern tree fold_builtin_stxcpy_chk (location_t, tree, tree, tree, tree, tree, bool,
-@@ -6545,4 +6548,18 @@
- && builtin_info.implicit_p[uns_fncode]);
- }
-
-+/* Return pointer to optimization flags of FNDECL. */
-+static inline struct cl_optimization *
-+opts_for_fn (const_tree fndecl)
-+{
-+ tree fn_opts = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
-+ if (fn_opts == NULL_TREE)
-+ fn_opts = optimization_default_node;
-+ return TREE_OPTIMIZATION (fn_opts);
-+}
-+
-+/* opt flag for function FNDECL, e.g. opts_for_fn (fndecl, optimize) is
-+ the optimization level of function fndecl. */
-+#define opt_for_fn(fndecl, opt) (opts_for_fn (fndecl)->x_##opt)
-+
- #endif /* GCC_TREE_H */
-Index: gcc/ipa-cp.c
-===================================================================
---- a/src/gcc/ipa-cp.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ipa-cp.c (.../branches/gcc-4_8-branch)
-@@ -444,6 +444,9 @@
- reason = "not a tree_versionable_function";
- else if (cgraph_function_body_availability (node) <= AVAIL_OVERWRITABLE)
- reason = "insufficient body availability";
-+ else if (!opt_for_fn (node->symbol.decl, optimize)
-+ || !opt_for_fn (node->symbol.decl, flag_ipa_cp))
-+ reason = "non-optimized function";
-
- if (reason && dump_file && !node->alias && !node->thunk.thunk_p)
- fprintf (dump_file, "Function %s/%i is not versionable, reason: %s.\n",
-@@ -1455,22 +1458,21 @@
- args_count = ipa_get_cs_argument_count (args);
- parms_count = ipa_get_param_count (callee_info);
-
-- /* If this call goes through a thunk we must not propagate to the first (0th)
-- parameter. However, we might need to uncover a thunk from below a series
-- of aliases first. */
-+ /* If this call goes through a thunk we should not propagate because we
-+ cannot redirect edges to thunks. However, we might need to uncover a
-+ thunk from below a series of aliases first. */
- alias_or_thunk = cs->callee;
- while (alias_or_thunk->alias)
- alias_or_thunk = cgraph_alias_aliased_node (alias_or_thunk);
- if (alias_or_thunk->thunk.thunk_p)
- {
-- ret |= set_all_contains_variable (ipa_get_parm_lattices (callee_info,
-- 0));
-- i = 1;
-+ for (i = 0; i < parms_count; i++)
-+ ret |= set_all_contains_variable (ipa_get_parm_lattices (callee_info,
-+ i));
-+ return ret;
- }
-- else
-- i = 0;
-
-- for (; (i < args_count) && (i < parms_count); i++)
-+ for (i = 0; (i < args_count) && (i < parms_count); i++)
- {
- struct ipa_jump_func *jump_func = ipa_get_ith_jump_func (args, i);
- struct ipcp_param_lattices *dest_plats;
-@@ -3119,6 +3121,7 @@
- struct cgraph_node *node)
- {
- struct ipa_node_params *orig_caller_info = IPA_NODE_REF (cs->caller);
-+ struct ipa_node_params *orig_node_info;
- struct ipa_agg_replacement_value *aggval;
- int i, ec, count;
-
-@@ -3133,6 +3136,7 @@
- if (aggval->index >= ec)
- return false;
-
-+ orig_node_info = IPA_NODE_REF (IPA_NODE_REF (node)->ipcp_orig_node);
- if (orig_caller_info->ipcp_orig_node)
- orig_caller_info = IPA_NODE_REF (orig_caller_info->ipcp_orig_node);
-
-@@ -3150,7 +3154,7 @@
- if (!interesting)
- continue;
-
-- plats = ipa_get_parm_lattices (orig_caller_info, aggval->index);
-+ plats = ipa_get_parm_lattices (orig_node_info, aggval->index);
- if (plats->aggs_bottom)
- return false;
-
-Index: gcc/rtlanal.c
-===================================================================
---- a/src/gcc/rtlanal.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/rtlanal.c (.../branches/gcc-4_8-branch)
-@@ -224,10 +224,10 @@
- return 0;
- }
-
--/* Return nonzero if the use of X as an address in a MEM can cause a trap.
-- MODE is the mode of the MEM (not that of X) and UNALIGNED_MEMS controls
-- whether nonzero is returned for unaligned memory accesses on strict
-- alignment machines. */
-+/* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
-+ bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
-+ UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
-+ references on strict alignment machines. */
-
- static int
- rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size,
-@@ -235,11 +235,12 @@
- {
- enum rtx_code code = GET_CODE (x);
-
-- if (STRICT_ALIGNMENT
-- && unaligned_mems
-- && GET_MODE_SIZE (mode) != 0)
-+ /* The offset must be a multiple of the mode size if we are considering
-+ unaligned memory references on strict alignment machines. */
-+ if (STRICT_ALIGNMENT && unaligned_mems && GET_MODE_SIZE (mode) != 0)
- {
- HOST_WIDE_INT actual_offset = offset;
-+
- #ifdef SPARC_STACK_BOUNDARY_HACK
- /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
- the real alignment of %sp. However, when it does this, the
-@@ -298,8 +299,27 @@
- return 0;
-
- case REG:
-- /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
-- if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
-+ /* Stack references are assumed not to trap, but we need to deal with
-+ nonsensical offsets. */
-+ if (x == frame_pointer_rtx)
-+ {
-+ HOST_WIDE_INT adj_offset = offset - STARTING_FRAME_OFFSET;
-+ if (size == 0)
-+ size = GET_MODE_SIZE (mode);
-+ if (FRAME_GROWS_DOWNWARD)
-+ {
-+ if (adj_offset < frame_offset || adj_offset + size - 1 >= 0)
-+ return 1;
-+ }
-+ else
-+ {
-+ if (adj_offset < 0 || adj_offset + size - 1 >= frame_offset)
-+ return 1;
-+ }
-+ return 0;
-+ }
-+ /* ??? Need to add a similar guard for nonsensical offsets. */
-+ if (x == hard_frame_pointer_rtx
- || x == stack_pointer_rtx
- /* The arg pointer varies if it is not a fixed register. */
- || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
-@@ -320,9 +340,7 @@
- if (XEXP (x, 0) == pic_offset_table_rtx && CONSTANT_P (XEXP (x, 1)))
- return 0;
-
-- /* - or it is an address that can't trap plus a constant integer,
-- with the proper remainder modulo the mode size if we are
-- considering unaligned memory references. */
-+ /* - or it is an address that can't trap plus a constant integer. */
- if (CONST_INT_P (XEXP (x, 1))
- && !rtx_addr_can_trap_p_1 (XEXP (x, 0), offset + INTVAL (XEXP (x, 1)),
- size, mode, unaligned_mems))
-Index: gcc/configure
-===================================================================
---- a/src/gcc/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/configure (.../branches/gcc-4_8-branch)
-@@ -11202,13 +11202,16 @@
- /* | A-Za-z:\\/* ) realsrcdir=${srcdir};;
- *) realsrcdir=../${srcdir};;
- esac
-- saved_CFLAGS="${CFLAGS}"
-+ # Clearing GMPINC is necessary to prevent host headers being
-+ # used by the build compiler. Defining GENERATOR_FILE stops
-+ # system.h from including gmp.h.
- CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
-- LDFLAGS="${LDFLAGS_FOR_BUILD}" \
-+ CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \
-+ LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \
-+ GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \
- ${realsrcdir}/configure \
- --enable-languages=${enable_languages-all} \
- --target=$target_alias --host=$build_alias --build=$build_alias
-- CFLAGS="${saved_CFLAGS}"
-
- # We just finished tests for the build machine, so rename
- # the file auto-build.h in the gcc directory.
-@@ -11703,6 +11706,7 @@
- if test x$build != x$host || test "x$coverage_flags" != x
- then
- BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'
-+ BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)'
- BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'
- fi
-
-@@ -13590,7 +13594,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -13615,7 +13619,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -13634,7 +13641,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -17828,7 +17838,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 17831 "configure"
-+#line 17841 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -17934,7 +17944,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 17937 "configure"
-+#line 17947 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -24263,6 +24273,43 @@
- $as_echo "#define HAVE_AS_SPARC4 1" >>confdefs.h
-
- fi
-+
-+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for LEON instructions" >&5
-+$as_echo_n "checking assembler for LEON instructions... " >&6; }
-+if test "${gcc_cv_as_sparc_leon+set}" = set; then :
-+ $as_echo_n "(cached) " >&6
-+else
-+ gcc_cv_as_sparc_leon=no
-+ if test x$gcc_cv_as != x; then
-+ $as_echo '.text
-+ .register %g2, #scratch
-+ .register %g3, #scratch
-+ .align 4
-+ smac %g2, %g3, %g1
-+ umac %g2, %g3, %g1
-+ casa [%g2] 0xb, %g3, %g1' > conftest.s
-+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -Aleon -o conftest.o conftest.s >&5'
-+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
-+ (eval $ac_try) 2>&5
-+ ac_status=$?
-+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
-+ test $ac_status = 0; }; }
-+ then
-+ gcc_cv_as_sparc_leon=yes
-+ else
-+ echo "configure: failed program was" >&5
-+ cat conftest.s >&5
-+ fi
-+ rm -f conftest.o conftest.s
-+ fi
-+fi
-+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_leon" >&5
-+$as_echo "$gcc_cv_as_sparc_leon" >&6; }
-+if test $gcc_cv_as_sparc_leon = yes; then
-+
-+$as_echo "#define HAVE_AS_LEON 1" >>confdefs.h
-+
-+fi
- ;;
-
- i[34567]86-*-* | x86_64-*-*)
-@@ -24745,6 +24792,10 @@
-
- # These two are used unconditionally by i386.[ch]; it is to be defined
- # to 1 if the feature is present, 0 otherwise.
-+ as_ix86_gotoff_in_data_opt=
-+ if test x$gas = xyes; then
-+ as_ix86_gotoff_in_data_opt="--32"
-+ fi
- { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for GOTOFF in data" >&5
- $as_echo_n "checking assembler for GOTOFF in data... " >&6; }
- if test "${gcc_cv_as_ix86_gotoff_in_data+set}" = set; then :
-@@ -24761,7 +24812,7 @@
- nop
- .data
- .long .L0@GOTOFF' > conftest.s
-- if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5'
-+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags $as_ix86_gotoff_in_data_opt -o conftest.o conftest.s >&5'
- { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
- (eval $ac_try) 2>&5
- ac_status=$?
-@@ -24822,6 +24873,37 @@
-
- fi
-
-+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for ud2 mnemonic" >&5
-+$as_echo_n "checking assembler for ud2 mnemonic... " >&6; }
-+if test "${gcc_cv_as_ix86_ud2+set}" = set; then :
-+ $as_echo_n "(cached) " >&6
-+else
-+ gcc_cv_as_ix86_ud2=no
-+ if test x$gcc_cv_as != x; then
-+ $as_echo 'ud2' > conftest.s
-+ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5'
-+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
-+ (eval $ac_try) 2>&5
-+ ac_status=$?
-+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
-+ test $ac_status = 0; }; }
-+ then
-+ gcc_cv_as_ix86_ud2=yes
-+ else
-+ echo "configure: failed program was" >&5
-+ cat conftest.s >&5
-+ fi
-+ rm -f conftest.o conftest.s
-+ fi
-+fi
-+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_ix86_ud2" >&5
-+$as_echo "$gcc_cv_as_ix86_ud2" >&6; }
-+if test $gcc_cv_as_ix86_ud2 = yes; then
-+
-+$as_echo "#define HAVE_AS_IX86_UD2 1" >>confdefs.h
-+
-+fi
-+
- { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for R_386_TLS_GD_PLT reloc" >&5
- $as_echo_n "checking assembler for R_386_TLS_GD_PLT reloc... " >&6; }
- if test "${gcc_cv_as_ix86_tlsgdplt+set}" = set; then :
-@@ -27239,8 +27321,8 @@
- $as_echo_n "checking for exported symbols... " >&6; }
- if test "x$export_sym_check" != x; then
- echo "int main() {return 0;} int foobar() {return 0;}" > conftest.c
-- ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest > /dev/null 2>&1
-- if $export_sym_check conftest | grep foobar > /dev/null; then
-+ ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest$ac_exeext > /dev/null 2>&1
-+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then
- : # No need to use a flag
- { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
- $as_echo "yes" >&6; }
-@@ -27249,8 +27331,8 @@
- $as_echo "yes" >&6; }
- { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -rdynamic" >&5
- $as_echo_n "checking for -rdynamic... " >&6; }
-- ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest > /dev/null 2>&1
-- if $export_sym_check conftest | grep foobar > /dev/null; then
-+ ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest$ac_exeext > /dev/null 2>&1
-+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then
- plugin_rdynamic=yes
- pluginlibs="-rdynamic"
- else
-Index: gcc/builtins.c
-===================================================================
---- a/src/gcc/builtins.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/builtins.c (.../branches/gcc-4_8-branch)
-@@ -180,7 +180,6 @@
- static tree fold_builtin_strpbrk (location_t, tree, tree, tree);
- static tree fold_builtin_strstr (location_t, tree, tree, tree);
- static tree fold_builtin_strrchr (location_t, tree, tree, tree);
--static tree fold_builtin_strcat (location_t, tree, tree);
- static tree fold_builtin_strncat (location_t, tree, tree, tree);
- static tree fold_builtin_strspn (location_t, tree, tree);
- static tree fold_builtin_strcspn (location_t, tree, tree);
-@@ -906,9 +905,24 @@
- if (! HAVE_nonlocal_goto)
- #endif
- {
-+ /* First adjust our frame pointer to its actual value. It was
-+ previously set to the start of the virtual area corresponding to
-+ the stacked variables when we branched here and now needs to be
-+ adjusted to the actual hardware fp value.
-+
-+ Assignments to virtual registers are converted by
-+ instantiate_virtual_regs into the corresponding assignment
-+ to the underlying register (fp in this case) that makes
-+ the original assignment true.
-+ So the following insn will actually be decrementing fp by
-+ STARTING_FRAME_OFFSET. */
- emit_move_insn (virtual_stack_vars_rtx, hard_frame_pointer_rtx);
-- /* This might change the hard frame pointer in ways that aren't
-- apparent to early optimization passes, so force a clobber. */
-+
-+ /* Restoring the frame pointer also modifies the hard frame pointer.
-+ Mark it used (so that the previous assignment remains live once
-+ the frame pointer is eliminated) and clobbered (to represent the
-+ implicit update from the assignment). */
-+ emit_use (hard_frame_pointer_rtx);
- emit_clobber (hard_frame_pointer_rtx);
- }
-
-@@ -949,8 +963,7 @@
-
- /* We must not allow the code we just generated to be reordered by
- scheduling. Specifically, the update of the frame pointer must
-- happen immediately, not later. Similarly, we must block
-- (frame-related) register values to be used across this code. */
-+ happen immediately, not later. */
- emit_insn (gen_blockage ());
- }
-
-@@ -1958,6 +1971,7 @@
- tree fndecl = get_callee_fndecl (exp);
- enum machine_mode mode;
- bool errno_set = false;
-+ bool try_widening = false;
- tree arg;
-
- if (!validate_arglist (exp, REAL_TYPE, VOID_TYPE))
-@@ -1969,6 +1983,7 @@
- {
- CASE_FLT_FN (BUILT_IN_SQRT):
- errno_set = ! tree_expr_nonnegative_p (arg);
-+ try_widening = true;
- builtin_optab = sqrt_optab;
- break;
- CASE_FLT_FN (BUILT_IN_EXP):
-@@ -2025,8 +2040,10 @@
- if (! flag_errno_math || ! HONOR_NANS (mode))
- errno_set = false;
-
-- /* Before working hard, check whether the instruction is available. */
-- if (optab_handler (builtin_optab, mode) != CODE_FOR_nothing
-+ /* Before working hard, check whether the instruction is available, but try
-+ to widen the mode for specific operations. */
-+ if ((optab_handler (builtin_optab, mode) != CODE_FOR_nothing
-+ || (try_widening && !excess_precision_type (TREE_TYPE (exp))))
- && (!errno_set || !optimize_insn_for_size_p ()))
- {
- rtx result = gen_reg_rtx (mode);
-@@ -5347,7 +5364,7 @@
- expand_builtin_atomic_compare_exchange (enum machine_mode mode, tree exp,
- rtx target)
- {
-- rtx expect, desired, mem, oldval;
-+ rtx expect, desired, mem, oldval, label;
- enum memmodel success, failure;
- tree weak;
- bool is_weak;
-@@ -5385,14 +5402,26 @@
- if (host_integerp (weak, 0) && tree_low_cst (weak, 0) != 0)
- is_weak = true;
-
-- oldval = expect;
-- if (!expand_atomic_compare_and_swap ((target == const0_rtx ? NULL : &target),
-- &oldval, mem, oldval, desired,
-+ if (target == const0_rtx)
-+ target = NULL;
-+
-+ /* Lest the rtl backend create a race condition with an imporoper store
-+ to memory, always create a new pseudo for OLDVAL. */
-+ oldval = NULL;
-+
-+ if (!expand_atomic_compare_and_swap (&target, &oldval, mem, expect, desired,
- is_weak, success, failure))
- return NULL_RTX;
-
-- if (oldval != expect)
-- emit_move_insn (expect, oldval);
-+ /* Conditionally store back to EXPECT, lest we create a race condition
-+ with an improper store to memory. */
-+ /* ??? With a rearrangement of atomics at the gimple level, we can handle
-+ the normal case where EXPECT is totally private, i.e. a register. At
-+ which point the store can be unconditional. */
-+ label = gen_label_rtx ();
-+ emit_cmp_and_jump_insns (target, const0_rtx, NE, NULL, VOIDmode, 1, label);
-+ emit_move_insn (expect, oldval);
-+ emit_label (label);
-
- return target;
- }
-@@ -5846,6 +5875,9 @@
- switch (fcode)
- {
- CASE_FLT_FN (BUILT_IN_FABS):
-+ case BUILT_IN_FABSD32:
-+ case BUILT_IN_FABSD64:
-+ case BUILT_IN_FABSD128:
- target = expand_builtin_fabs (exp, target, subtarget);
- if (target)
- return target;
-@@ -10298,6 +10330,9 @@
- return fold_builtin_strlen (loc, type, arg0);
-
- CASE_FLT_FN (BUILT_IN_FABS):
-+ case BUILT_IN_FABSD32:
-+ case BUILT_IN_FABSD64:
-+ case BUILT_IN_FABSD128:
- return fold_builtin_fabs (loc, arg0, type);
-
- case BUILT_IN_ABS:
-@@ -10766,7 +10801,7 @@
- return fold_builtin_strstr (loc, arg0, arg1, type);
-
- case BUILT_IN_STRCAT:
-- return fold_builtin_strcat (loc, arg0, arg1);
-+ return fold_builtin_strcat (loc, arg0, arg1, NULL_TREE);
-
- case BUILT_IN_STRSPN:
- return fold_builtin_strspn (loc, arg0, arg1);
-@@ -11809,8 +11844,9 @@
- COMPOUND_EXPR in the chain will contain the tree for the simplified
- form of the builtin function call. */
-
--static tree
--fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src)
-+tree
-+fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src,
-+ tree len)
- {
- if (!validate_arg (dst, POINTER_TYPE)
- || !validate_arg (src, POINTER_TYPE))
-@@ -11828,22 +11864,17 @@
- /* See if we can store by pieces into (dst + strlen(dst)). */
- tree newdst, call;
- tree strlen_fn = builtin_decl_implicit (BUILT_IN_STRLEN);
-- tree strcpy_fn = builtin_decl_implicit (BUILT_IN_STRCPY);
-+ tree memcpy_fn = builtin_decl_implicit (BUILT_IN_MEMCPY);
-
-- if (!strlen_fn || !strcpy_fn)
-+ if (!strlen_fn || !memcpy_fn)
- return NULL_TREE;
-
-- /* If we don't have a movstr we don't want to emit an strcpy
-- call. We have to do that if the length of the source string
-- isn't computable (in that case we can use memcpy probably
-- later expanding to a sequence of mov instructions). If we
-- have movstr instructions we can emit strcpy calls. */
-- if (!HAVE_movstr)
-- {
-- tree len = c_strlen (src, 1);
-- if (! len || TREE_SIDE_EFFECTS (len))
-- return NULL_TREE;
-- }
-+ /* If the length of the source string isn't computable don't
-+ split strcat into strlen and memcpy. */
-+ if (! len)
-+ len = c_strlen (src, 1);
-+ if (! len || TREE_SIDE_EFFECTS (len))
-+ return NULL_TREE;
-
- /* Stabilize the argument list. */
- dst = builtin_save_expr (dst);
-@@ -11855,7 +11886,11 @@
- newdst = fold_build_pointer_plus_loc (loc, dst, newdst);
- newdst = builtin_save_expr (newdst);
-
-- call = build_call_expr_loc (loc, strcpy_fn, 2, newdst, src);
-+ len = fold_convert_loc (loc, size_type_node, len);
-+ len = size_binop_loc (loc, PLUS_EXPR, len,
-+ build_int_cst (size_type_node, 1));
-+
-+ call = build_call_expr_loc (loc, memcpy_fn, 3, newdst, src, len);
- return build2 (COMPOUND_EXPR, TREE_TYPE (dst), call, dst);
- }
- return NULL_TREE;
-Index: gcc/gcc.c
-===================================================================
---- a/src/gcc/gcc.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/gcc.c (.../branches/gcc-4_8-branch)
-@@ -5441,7 +5441,7 @@
- const char *save_suffix_subst;
-
- int save_growing_size;
-- void *save_growing_value;
-+ void *save_growing_value = NULL;
-
- sf = lookup_spec_function (func);
- if (sf == NULL)
-Index: gcc/fold-const.c
-===================================================================
---- a/src/gcc/fold-const.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fold-const.c (.../branches/gcc-4_8-branch)
-@@ -461,8 +461,6 @@
-
- case TRUNC_DIV_EXPR:
- case ROUND_DIV_EXPR:
-- case FLOOR_DIV_EXPR:
-- case CEIL_DIV_EXPR:
- case EXACT_DIV_EXPR:
- /* In general we can't negate A / B, because if A is INT_MIN and
- B is 1, we may turn this into INT_MIN / -1 which is undefined
-@@ -644,8 +642,6 @@
-
- case TRUNC_DIV_EXPR:
- case ROUND_DIV_EXPR:
-- case FLOOR_DIV_EXPR:
-- case CEIL_DIV_EXPR:
- case EXACT_DIV_EXPR:
- /* In general we can't negate A / B, because if A is INT_MIN and
- B is 1, we may turn this into INT_MIN / -1 which is undefined
-@@ -2664,10 +2660,11 @@
- case COMPONENT_REF:
- /* Handle operand 2 the same as for ARRAY_REF. Operand 0
- may be NULL when we're called to compare MEM_EXPRs. */
-- if (!OP_SAME_WITH_NULL (0))
-+ if (!OP_SAME_WITH_NULL (0)
-+ || !OP_SAME (1))
- return 0;
- flags &= ~OEP_CONSTANT_ADDRESS_OF;
-- return OP_SAME (1) && OP_SAME_WITH_NULL (2);
-+ return OP_SAME_WITH_NULL (2);
-
- case BIT_FIELD_REF:
- if (!OP_SAME (0))
-@@ -4920,12 +4917,16 @@
- int in0_p, in1_p, in_p;
- tree low0, low1, low, high0, high1, high;
- bool strict_overflow_p = false;
-- tree lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p);
-- tree rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p);
-- tree tem;
-+ tree tem, lhs, rhs;
- const char * const warnmsg = G_("assuming signed overflow does not occur "
- "when simplifying range test");
-
-+ if (!INTEGRAL_TYPE_P (type))
-+ return 0;
-+
-+ lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p);
-+ rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p);
-+
- /* If this is an OR operation, invert both sides; we will invert
- again at the end. */
- if (or_op)
-@@ -10927,6 +10928,13 @@
- fold_build2_loc (loc, MULT_EXPR, type,
- build_int_cst (type, 2) , arg1));
-
-+ /* ((T) (X /[ex] C)) * C cancels out if the conversion is
-+ sign-changing only. */
-+ if (TREE_CODE (arg1) == INTEGER_CST
-+ && TREE_CODE (arg0) == EXACT_DIV_EXPR
-+ && operand_equal_p (arg1, TREE_OPERAND (arg0, 1), 0))
-+ return fold_convert_loc (loc, type, TREE_OPERAND (arg0, 0));
-+
- strict_overflow_p = false;
- if (TREE_CODE (arg1) == INTEGER_CST
- && 0 != (tem = extract_muldiv (op0, arg1, code, NULL_TREE,
-@@ -16587,7 +16595,7 @@
- unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT;
- tree index = bitsize_int (indexi);
-
-- if (offset/part_widthi <= TYPE_VECTOR_SUBPARTS (op00type))
-+ if (offset / part_widthi < TYPE_VECTOR_SUBPARTS (op00type))
- return fold_build3_loc (loc,
- BIT_FIELD_REF, type, op00,
- part_width, index);
-Index: gcc/objc/ChangeLog
-===================================================================
---- a/src/gcc/objc/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/objc/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,14 @@
-+2014-04-07 Dominique d'Humieres <dominiq@lps.ens.fr>
-+
-+ Backport from mainline
-+ 2013-09-14 Iain Sandoe <iains@gcc.gnu.org>
-+
-+ PR target/48094
-+ * objc-next-runtime-abi-01.c (generate_objc_image_info): Remove.
-+ (objc_generate_v1_next_metadata): Remove generation of ImageInfo.
-+ * objc-next-runtime-abi-02.c (generate_v2_objc_image_info): Remove.
-+ (objc_generate_v2_next_metadata): Remove generation of ImageInfo.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: gcc/objc/objc-next-runtime-abi-01.c
-===================================================================
---- a/src/gcc/objc/objc-next-runtime-abi-01.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/objc/objc-next-runtime-abi-01.c (.../branches/gcc-4_8-branch)
-@@ -2332,37 +2332,7 @@
- return;
- }
-
--
--/* The Fix-and-Continue functionality available in Mac OS X 10.3 and
-- later requires that ObjC translation units participating in F&C be
-- specially marked. The following routine accomplishes this. */
--
--/* static int _OBJC_IMAGE_INFO[2] = { 0, 1 }; */
--
- static void
--generate_objc_image_info (void)
--{
-- tree decl;
-- int flags
-- = ((flag_replace_objc_classes && imp_count ? 1 : 0)
-- | (flag_objc_gc ? 2 : 0));
-- vec<constructor_elt, va_gc> *v = NULL;
-- tree array_type;
--
-- array_type = build_sized_array_type (integer_type_node, 2);
--
-- decl = start_var_decl (array_type, "_OBJC_ImageInfo");
--
-- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, integer_zero_node);
-- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, build_int_cst (integer_type_node, flags));
-- /* The runtime wants this and refers to it in a manner hidden from the compiler.
-- So we must force the output. */
-- DECL_PRESERVE_P (decl) = 1;
-- OBJCMETA (decl, objc_meta, meta_info);
-- finish_var_decl (decl, objc_build_constructor (TREE_TYPE (decl), v));
--}
--
--static void
- objc_generate_v1_next_metadata (void)
- {
- struct imp_entry *impent;
-@@ -2412,9 +2382,6 @@
- attr = build_tree_list (objc_meta, meta_modules);
- build_module_descriptor (vers, attr);
-
-- /* This conveys information on GC usage and zero-link. */
-- generate_objc_image_info ();
--
- /* Dump the class references. This forces the appropriate classes
- to be linked into the executable image, preserving unix archive
- semantics. */
-Index: gcc/objc/objc-next-runtime-abi-02.c
-===================================================================
---- a/src/gcc/objc/objc-next-runtime-abi-02.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/objc/objc-next-runtime-abi-02.c (.../branches/gcc-4_8-branch)
-@@ -3329,32 +3329,7 @@
- finish_var_decl (ref->decl, ref->offset);
- }
-
--/* static int _OBJC_IMAGE_INFO[2] = { 0, 16 | flags }; */
--
- static void
--generate_v2_objc_image_info (void)
--{
-- tree decl, array_type;
-- vec<constructor_elt, va_gc> *v = NULL;
-- int flags =
-- ((flag_replace_objc_classes && imp_count ? 1 : 0)
-- | (flag_objc_gc ? 2 : 0));
--
-- flags |= 16;
--
-- array_type = build_sized_array_type (integer_type_node, 2);
--
-- decl = start_var_decl (array_type, "_OBJC_ImageInfo");
--
-- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, integer_zero_node);
-- CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, build_int_cst (integer_type_node, flags));
-- /* The Runtime wants this. */
-- DECL_PRESERVE_P (decl) = 1;
-- OBJCMETA (decl, objc_meta, meta_info);
-- finish_var_decl (decl, objc_build_constructor (TREE_TYPE (decl), v));
--}
--
--static void
- objc_generate_v2_next_metadata (void)
- {
- struct imp_entry *impent;
-@@ -3405,9 +3380,6 @@
- build_v2_address_table (nonlazy_category_list, "_OBJC_NonLazyCategoryList$",
- meta_label_nonlazy_categorylist);
-
-- /* This conveys information on GC usage and zero-link. */
-- generate_v2_objc_image_info ();
--
- /* Generate catch objects for eh, if any are needed. */
- build_v2_eh_catch_objects ();
-
-Index: gcc/reorg.c
-===================================================================
---- a/src/gcc/reorg.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/reorg.c (.../branches/gcc-4_8-branch)
-@@ -1105,6 +1105,7 @@
- int used_annul = 0;
- int i;
- struct resources cc_set;
-+ bool *redundant;
-
- /* We can't do anything if there are more delay slots in SEQ than we
- can handle, or if we don't know that it will be a taken branch.
-@@ -1145,6 +1146,7 @@
- return delay_list;
- #endif
-
-+ redundant = XALLOCAVEC (bool, XVECLEN (seq, 0));
- for (i = 1; i < XVECLEN (seq, 0); i++)
- {
- rtx trial = XVECEXP (seq, 0, i);
-@@ -1166,7 +1168,8 @@
-
- /* If this insn was already done (usually in a previous delay slot),
- pretend we put it in our delay slot. */
-- if (redundant_insn (trial, insn, new_delay_list))
-+ redundant[i] = redundant_insn (trial, insn, new_delay_list);
-+ if (redundant[i])
- continue;
-
- /* We will end up re-vectoring this branch, so compute flags
-@@ -1199,6 +1202,12 @@
- return delay_list;
- }
-
-+ /* Record the effect of the instructions that were redundant and which
-+ we therefore decided not to copy. */
-+ for (i = 1; i < XVECLEN (seq, 0); i++)
-+ if (redundant[i])
-+ update_block (XVECEXP (seq, 0, i), insn);
-+
- /* Show the place to which we will be branching. */
- *pnew_thread = first_active_target_insn (JUMP_LABEL (XVECEXP (seq, 0, 0)));
-
-@@ -1262,6 +1271,7 @@
- /* If this insn was already done, we don't need it. */
- if (redundant_insn (trial, insn, delay_list))
- {
-+ update_block (trial, insn);
- delete_from_delay_slot (trial);
- continue;
- }
-@@ -3266,6 +3276,7 @@
- to reprocess this insn. */
- if (redundant_insn (XVECEXP (pat, 0, 1), delay_insn, 0))
- {
-+ update_block (XVECEXP (pat, 0, 1), insn);
- delete_from_delay_slot (XVECEXP (pat, 0, 1));
- next = prev_active_insn (next);
- continue;
-@@ -3385,6 +3396,7 @@
- && redirect_with_delay_slots_safe_p (delay_insn, target_label,
- insn))
- {
-+ update_block (XVECEXP (PATTERN (trial), 0, 1), insn);
- reorg_redirect_jump (delay_insn, target_label);
- next = insn;
- continue;
-Index: gcc/tree-ssa-sccvn.c
-===================================================================
---- a/src/gcc/tree-ssa-sccvn.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-sccvn.c (.../branches/gcc-4_8-branch)
-@@ -660,7 +660,7 @@
- }
-
- /* For non-calls, store the information that makes up the address. */
--
-+ tree orig = ref;
- while (ref)
- {
- vn_reference_op_s temp;
-@@ -711,7 +711,15 @@
- .arshift (BITS_PER_UNIT == 8
- ? 3 : exact_log2 (BITS_PER_UNIT),
- HOST_BITS_PER_DOUBLE_INT);
-- if (off.fits_shwi ())
-+ if (off.fits_shwi ()
-+ /* Probibit value-numbering zero offset components
-+ of addresses the same before the pass folding
-+ __builtin_object_size had a chance to run
-+ (checking cfun->after_inlining does the
-+ trick here). */
-+ && (TREE_CODE (orig) != ADDR_EXPR
-+ || !off.is_zero ()
-+ || cfun->after_inlining))
- temp.off = off.low;
- }
- }
-Index: gcc/ChangeLog
-===================================================================
---- a/src/gcc/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,5474 @@
-+2014-05-15 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2014-05-15 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ PR target/61193
-+ * config/rs6000/htmxlintrin.h (_HTM_TBEGIN_STARTED): New define.
-+ (__TM_simple_begin): Use it.
-+ (__TM_begin): Likewise.
-+
-+2014-05-14 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * config/sparc/sparc-protos.h (sparc_absnegfloat_split_legitimate):
-+ Delete.
-+ * config/sparc/sparc.c (sparc_absnegfloat_split_legitimate): Likewise.
-+ * config/sparc/sparc.md (fptype_ut699): New attribute.
-+ (in_branch_delay): Return false if -mfix-ut699 is specified and
-+ fptype_ut699 is set to single.
-+ (truncdfsf2): Add fptype_ut699 attribute.
-+ (fix_truncdfsi2): Likewise.
-+ (floatsisf2): Change fptype attribute.
-+ (fix_truncsfsi2): Likewise.
-+ (negtf2_notv9): Delete.
-+ (negtf2_v9): Likewise.
-+ (negtf2_hq): New instruction.
-+ (negtf2): New instruction and splitter.
-+ (negdf2_notv9): Rewrite.
-+ (abstf2_notv9): Delete.
-+ (abstf2_hq_v9): Likewise.
-+ (abstf2_v9): Likewise.
-+ (abstf2_hq): New instruction.
-+ (abstf2): New instruction and splitter.
-+ (absdf2_notv9): Rewrite.
-+
-+2014-05-14 Matthias Klose <doko@ubuntu.com>
-+
-+ Revert:
-+ 2014-05-08 Manuel López-Ibáñez <manu@gcc.gnu.org>
-+ Matthias Klose <doko@ubuntu.com>
-+
-+ PR driver/61106
-+ * optc-gen.awk: Fix option handling for -Wunused-parameter.
-+
-+2014-05-13 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * doc/sourcebuild.texi: (dfp_hw): Document.
-+ (p8vector_hw): Likewise.
-+ (powerpc_eabi_ok): Likewise.
-+ (powerpc_elfv2): Likewise.
-+ (powerpc_htm_ok): Likewise.
-+ (ppc_recip_hw): Likewise.
-+ (vsx_hw): Likewise.
-+
-+2014-05-12 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
-+
-+ Backport from mainline
-+ 2014-05-12 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
-+
-+ PR target/60991
-+ * config/avr/avr.c (avr_out_store_psi): Use correct constant
-+ to restore Y.
-+
-+2014-05-09 Georg-Johann Lay <avr@gjlay.de>
-+
-+ Backport from 2014-05-09 trunk r210267
-+
-+ PR target/61055
-+ * config/avr/avr.md (cc): Add new attribute set_vzn.
-+ (addqi3, addqq3, adduqq3, subqi3, subqq3, subuqq3, negqi2) [cc]:
-+ Set cc insn attribute to set_vzn instead of set_zn for alternatives
-+ with INC, DEC or NEG.
-+ * config/avr/avr.c (avr_notice_update_cc): Handle SET_VZN.
-+ (avr_out_plus_1): ADIW sets cc0 to CC_SET_CZN.
-+ INC, DEC and ADD+ADC set cc0 to CC_CLOBBER.
-+
-+2014-05-09 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ * builtins.c (expand_builtin_setjmp_receiver): Emit a use of
-+ the hard frame pointer. Synchronize commentary with mainline.
-+ * cse.c (cse_insn): Only check for volatile asms.
-+ * cselib.c (cselib_process_insn): Likewise.
-+ * dse.c (scan_insn): Likewise.
-+ * stmt.c (expand_nl_goto_receiver): Emit a use and a clobber of
-+ the hard frame pointer.
-+
-+2014-05-08 Manuel López-Ibáñez <manu@gcc.gnu.org>
-+ Matthias Klose <doko@ubuntu.com>
-+
-+ PR driver/61106
-+ * optc-gen.awk: Fix option handling for -Wunused-parameter.
-+
-+2014-05-08 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59952
-+ * config/i386/i386.c (ix86_option_override_internal): Remove PTA_RTM
-+ from core-avx2.
-+
-+2014-05-08 Charles Baylis <charles.baylis@linaro.org>
-+
-+ Backport from mainline
-+ 2014-04-07 Charles Baylis <charles.baylis@linaro.org>
-+
-+ PR target/60609
-+ * config/arm/arm.h (ASM_OUTPUT_CASE_END): Remove.
-+ (LABEL_ALIGN_AFTER_BARRIER): Align barriers which occur after
-+ ADDR_DIFF_VEC.
-+
-+2014-05-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-+
-+ * config.gcc (aarch64*-*-*): Use ISA flags from aarch64-arches.def.
-+ Do not define target_cpu_default2 to generic.
-+
-+2014-05-06 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-04-14 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/55022
-+ * fold-const.c (negate_expr_p): Don't negate directional rounding
-+ division.
-+ (fold_negate_expr): Likewise.
-+
-+2014-05-06 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-04-17 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60849
-+ * tree-ssa-propagate.c (valid_gimple_rhs_p): Only allow effective
-+ boolean results for comparisons.
-+
-+ 2014-04-07 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60766
-+ * tree-ssa-loop-ivopts.c (cand_value_at): Compute in an
-+ unsigned type.
-+ (may_eliminate_iv): Convert cand_value_at result to desired
-+ type.
-+
-+ 2014-04-23 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60903
-+ * tree-ssa-loop-im.c (execute_sm_if_changed): Properly apply
-+ IRREDUCIBLE_LOOP loop flags to newly created BBs and edges.
-+
-+2014-05-05 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-04-23 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60895
-+ * tree-inline.c (declare_return_variable): Use mark_addressable.
-+
-+ 2014-04-07 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60750
-+ * tree-ssa-operands.c (maybe_add_call_vops): Also add VDEFs
-+ for noreturn calls.
-+ * tree-cfgcleanup.c (fixup_noreturn_call): Do not remove VDEFs.
-+
-+ 2014-04-14 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59817
-+ PR tree-optimization/60453
-+ * graphite-scop-detection.c (graphite_can_represent_scev): Complete
-+ recursion to catch all CHRECs in the scalar evolution and restrict
-+ the predicate for the remains appropriately.
-+
-+ 2014-04-17 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60836
-+ * tree-vect-loop.c (vect_create_epilog_for_reduction): Force
-+ initial PHI args to be gimple values.
-+
-+2014-05-05 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backported from mainline
-+ 2014-04-25 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/60960
-+ * tree-vect-generic.c (expand_vector_operation): Only call
-+ expand_vector_divmod if type's mode satisfies VECTOR_MODE_P.
-+
-+2014-05-04 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.h (RS6000_BTM_HARD_FLOAT): New define.
-+ (RS6000_BTM_COMMON): Add RS6000_BTM_HARD_FLOAT.
-+ (TARGET_EXTRA_BUILTINS): Add TARGET_HARD_FLOAT.
-+ * config/rs6000/rs6000-builtin.def (BU_MISC_1):
-+ Use RS6000_BTM_HARD_FLOAT.
-+ (BU_MISC_2): Likewise.
-+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle
-+ RS6000_BTM_HARD_FLOAT.
-+ (rs6000_option_override_internal): Enforce -mhard-float if -mhard-dfp
-+ is explicitly used.
-+ (rs6000_invalid_builtin): Add hard floating builtin support.
-+ (rs6000_expand_builtin): Relax the gcc_assert to allow the new
-+ hard float builtins.
-+ (rs6000_builtin_mask_names): Add RS6000_BTM_HARD_FLOAT.
-+
-+2014-05-03 Joey Ye <joey.ye@arm.com>
-+
-+ Backport from mainline r209463
-+ 2014-04-17 Joey Ye <joey.ye@arm.com>
-+
-+ * opts.c (OPT_fif_conversion, OPT_fif_conversion2): Disable for Og.
-+
-+2014-05-03 Oleg Endo <olegendo@gcc.gnu.org>
-+
-+ Back port from mainline
-+ PR target/61026
-+ * config/sh/sh.c: Include stdlib headers before everything else.
-+
-+2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ PR tree-optimization/60930
-+ * gimple-ssa-strength-reduction.c (create_mul_imm_cand): Reject
-+ creating a multiply candidate by folding two constant
-+ multiplicands when the result overflows.
-+
-+2014-05-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-+
-+ * config/aarch64/aarch64.h (TARGET_SIMD): Take AARCH64_ISA_SIMD
-+ into account.
-+ (TARGET_FLOAT): Take AARCH64_ISA_FP into account.
-+
-+2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ Back port from mainline
-+ 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * doc/extend.texi (PowerPC Built-in Functions): Document new
-+ powerpc extended divide, bcd, pack/unpack 128-bit, builtin
-+ functions.
-+ (PowerPC AltiVec/VSX Built-in Functions): Likewise.
-+
-+ * config/rs6000/predicates.md (const_0_to_3_operand): New
-+ predicate to match 0..3 integer constants.
-+
-+ * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros
-+ to support adding miscellaneous builtin functions.
-+ (BU_DFP_MISC_2): Likewise.
-+ (BU_P7_MISC_1): Likewise.
-+ (BU_P7_MISC_2): Likewise.
-+ (BU_P8V_MISC_3): Likewise.
-+ (BU_MISC_1): Likewise.
-+ (BU_MISC_2): Likewise.
-+ (DIVWE): Add extended divide builtin functions.
-+ (DIVWEO): Likewise.
-+ (DIVWEU): Likewise.
-+ (DIVWEUO): Likewise.
-+ (DIVDE): Likewise.
-+ (DIVDEO): Likewise.
-+ (DIVDEU): Likewise.
-+ (DIVDEUO): Likewise.
-+ (DXEX): Add decimal floating-point builtin functions.
-+ (DXEXQ): Likewise.
-+ (DDEDPD): Likewise.
-+ (DDEDPDQ): Likewise.
-+ (DENBCD): Likewise.
-+ (DENBCDQ): Likewise.
-+ (DIEX): Likewise.
-+ (DIEXQ): Likewise.
-+ (DSCLI): Likewise.
-+ (DSCLIQ): Likewise.
-+ (DSCRI): Likewise.
-+ (DSCRIQ): Likewise.
-+ (CDTBCD): Add new BCD builtin functions.
-+ (CBCDTD): Likewise.
-+ (ADDG6S): Likewise.
-+ (BCDADD): Likewise.
-+ (BCDADD_LT): Likewise.
-+ (BCDADD_EQ): Likewise.
-+ (BCDADD_GT): Likewise.
-+ (BCDADD_OV): Likewise.
-+ (BCDSUB): Likewise.
-+ (BCDSUB_LT): Likewise.
-+ (BCDSUB_EQ): Likewise.
-+ (BCDSUB_GT): Likewise.
-+ (BCDSUB_OV): Likewise.
-+ (PACK_TD): Add new pack/unpack 128-bit type builtin functions.
-+ (UNPACK_TD): Likewise.
-+ (PACK_TF): Likewise.
-+ (UNPACK_TF): Likewise.
-+ (UNPACK_TF_0): Likewise.
-+ (UNPACK_TF_1): Likewise.
-+ (PACK_V1TI): Likewise.
-+ (UNPACK_V1TI): Likewise.
-+
-+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
-+ support for decimal floating point builtin functions.
-+ (rs6000_expand_ternop_builtin): Add checks for the new builtin
-+ functions that take constant arguments.
-+ (rs6000_invalid_builtin): Add decimal floating point builtin
-+ support.
-+ (rs6000_init_builtins): Setup long double, _Decimal64, and
-+ _Decimal128 types for new builtin functions.
-+ (builtin_function_type): Set the unsigned flags appropriately for
-+ the new builtin functions.
-+ (rs6000_opt_masks): Add support for decimal floating point builtin
-+ functions.
-+
-+ * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal
-+ floating point builtin functions.
-+ (RS6000_BTM_COMMON): Likewise.
-+ (RS6000_BTI_long_double): Likewise.
-+ (RS6000_BTI_dfloat64): Likewise.
-+ (RS6000_BTI_dfloat128): Likewise.
-+ (long_double_type_internal_node): Likewise.
-+ (dfloat64_type_internal_node): Likewise.
-+ (dfloat128_type_internal_node): Likewise.
-+
-+ * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA
-+ 2.07 bcd arithmetic instructions.
-+ (UNSPEC_BCDSUB): Likewise.
-+ (UNSPEC_BCD_OVERFLOW): Likewise.
-+ (UNSPEC_BCD_ADD_SUB): Likewise.
-+ (bcd_add_sub): Likewise.
-+ (BCD_TEST): Likewise.
-+ (bcd<bcd_add_sub>): Likewise.
-+ (bcd<bcd_add_sub>_test): Likewise.
-+ (bcd<bcd_add_sub>_test2): Likewise.
-+ (bcd<bcd_add_sub>_<code>): Likewise.
-+ (peephole2 for combined bcd ops): Likewise.
-+
-+ * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new
-+ decimal floating point builtin functions.
-+ (UNSPEC_DENBCD): Likewise.
-+ (UNSPEC_DXEX): Likewise.
-+ (UNSPEC_DIEX): Likewise.
-+ (UNSPEC_DSCLI): Likewise.
-+ (UNSPEC_DSCRI): Likewise.
-+ (D64_D128): Likewise.
-+ (dfp_suffix): Likewise.
-+ (dfp_ddedpd_<mode>): Likewise.
-+ (dfp_denbcd_<mode>): Likewise.
-+ (dfp_dxex_<mode>): Likewise.
-+ (dfp_diex_<mode>): Likewise.
-+ (dfp_dscli_<mode>): Likewise.
-+ (dfp_dscri_<mode>): Likewise.
-+
-+ * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD
-+ builtin functions.
-+ (UNSPEC_CDTBCD): Likewise.
-+ (UNSPEC_CBCDTD): Likewise.
-+ (UNSPEC_DIVE): Add support for new extended divide builtin
-+ functions.
-+ (UNSPEC_DIVEO): Likewise.
-+ (UNSPEC_DIVEU): Likewise.
-+ (UNSPEC_DIVEUO): Likewise.
-+ (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to
-+ pack/unpack 128-bit types.
-+ (UNSPEC_PACK_128BIT): Likewise.
-+ (idiv_ldiv): New mode attribute to set the 32/64-bit divide type.
-+ (udiv<mode>3): Use idiv_ldiv mode attribute.
-+ (div<mode>3): Likewise.
-+ (addg6s): Add new BCD builtin functions.
-+ (cdtbcd): Likewise.
-+ (cbcdtd): Likewise.
-+ (UNSPEC_DIV_EXTEND): Add support for new extended divide
-+ instructions.
-+ (div_extend): Likewise.
-+ (div<div_extend>_<mode>"): Likewise.
-+ (FP128_64): Add support for new builtin functions to pack/unpack
-+ 128-bit types.
-+ (unpack<mode>): Likewise.
-+ (unpacktf_0): Likewise.
-+ (unpacktf_1): Likewise.
-+ (unpack<mode>_dm): Likewise.
-+ (unpack<mode>_nodm): Likewise.
-+ (pack<mode>): Likewise.
-+ (unpackv1ti): Likewise.
-+ (packv1ti): Likewise.
-+
-+2014-04-29 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ Backport from mainline
-+ 2014-04-17 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * config/rs6000/rs6000.md (addti3, subti3): New.
-+
-+2014-04-28 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ Backport from mainline
-+ 2014-04-28 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * config/rs6000/sync.md (AINT mode_iterator): Move definition.
-+ (loadsync_<mode>): Change mode.
-+ (load_quadpti, store_quadpti): New.
-+ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.
-+ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.
-+
-+2014-04-28 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * configure.ac: Tweak GAS check for LEON instructions on SPARC.
-+ * configure: Regenerate.
-+ * config/sparc/sparc.opt (muser-mode): New option.
-+ * config/sparc/sync.md (atomic_compare_and_swap<mode>_1): Do not enable
-+ for LEON3.
-+ (atomic_compare_and_swap_leon3_1): New instruction for LEON3.
-+ * doc/invoke.texi (SPARC options): Document -muser-mode.
-+
-+2014-04-25 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR target/60941
-+ * config/sparc/sparc.md (ashlsi3_extend): Delete.
-+
-+2014-04-22 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ Back port from main line:
-+ 2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000-builtins.def (VBPERMQ): Add vbpermq builtin
-+ for ISA 2.07.
-+
-+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
-+ vbpermq builtins.
-+
-+ * config/rs6000/altivec.md (UNSPEC_VBPERMQ): Add support for the
-+ vbpermq instruction.
-+ (altivec_vbpermq): Likewise.
-+
-+ PR target/60672
-+ * config/rs6000/altivec.h (vec_xxsldwi): Add missing define to
-+ enable use of xxsldwi and xxpermdi builtin functions.
-+ (vec_xxpermdi): Likewise.
-+
-+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
-+ Document use of vec_xxsldwi and vec_xxpermdi builtins.
-+
-+2014-04-23 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-04-21 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/60909
-+ * config/i386/i386.c (ix86_expand_builtin)
-+ <case IX86_BUILTIN_RDRAND{16,32,64}_STEP>: Use temporary
-+ register for target RTX.
-+ <case IX86_BUILTIN_RDSEED{16,32,64}_STEP>: Ditto.
-+
-+2014-04-23 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-04-02 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60729
-+ * optabs.c (expand_abs_nojump): Honor flag_trapv only for
-+ MODE_INTs. Properly use negv_optab.
-+ (expand_abs): Likewise.
-+
-+ 2014-04-03 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60740
-+ * graphite-scop-detection.c (stmt_simple_for_scop_p): Iterate
-+ over all GIMPLE_COND operands.
-+
-+2014-04-23 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60635
-+ * gimplify.c (gimple_regimplify_operands): Update the
-+ re-gimplifed stmt.
-+
-+2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ Back port from the trunk, subversion id 209546.
-+
-+ 2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/60735
-+ * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64 case):
-+ If mode is DDmode and TARGET_E500_DOUBLE allow move.
-+
-+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print some
-+ more debug information for E500 if -mdebug=reg.
-+
-+2014-04-18 Richard Henderson <rth@redhat.com>
-+
-+ * config/aarch64/aarch64.c (aarch64_register_move_cost): Pass a mode
-+ to GET_MODE_SIZE, not a reg_class_t.
-+
-+2014-04-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vsx.md (vsx_xxmrghw_<mode>): Adjust for
-+ little-endian.
-+ (vsx_xxmrglw_<mode>): Likewise.
-+
-+2014-04-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ PR target/60839
-+ Revert the following patch
-+
-+ 2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Back port mainline subversion id 209025.
-+ 2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/60735
-+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
-+ software floating point or no floating point registers, do not
-+ allow any type in the FPRs. Eliminate a test for SPE SIMD types
-+ in GPRs that occurs after we tested for GPRs that would never be
-+ true.
-+
-+ * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
-+ Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
-+ since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,
-+ specifically allow DDmode, since that does not use the SPE SIMD
-+ instructions.
-+
-+2014-04-10 Vladimir Makarov <vmakarov@redhat.com>
-+
-+ PR rtl-optimization/60769
-+ * lra-constraints.c (simplify_operand_subreg): Force reload of
-+ paradoxical subreg if it is not in the class contents.
-+
-+2014-04-10 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-03-12 Jakub Jelinek <jakub@redhat.com>
-+ Marc Glisse <marc.glisse@inria.fr>
-+
-+ PR tree-optimization/60502
-+ * tree-ssa-reassoc.c (eliminate_not_pairs): Use build_all_ones_cst
-+ instead of build_low_bits_mask.
-+
-+ 2013-06-13 Marc Glisse <marc.glisse@inria.fr>
-+
-+ * tree.c (build_all_ones_cst): New function.
-+ * tree.h (build_all_ones_cst): Declare it.
-+
-+ 2013-05-10 Marc Glisse <marc.glisse@inria.fr>
-+
-+ * tree.c (build_minus_one_cst): New function.
-+ * tree.h (build_minus_one_cst): Declare new function.
-+
-+2014-04-10 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/60693
-+ * config/i386/i386.c (ix86_copy_addr_to_reg): Call copy_addr_to_reg
-+ also if addr has VOIDmode.
-+
-+ 2014-03-17 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/60516
-+ * config/i386/i386.c (ix86_expand_epilogue): Adjust REG_CFA_ADJUST_CFA
-+ note creation for the 2010-08-31 changes.
-+
-+ 2014-03-06 Jakub Jelinek <jakub@redhat.com>
-+ Meador Inge <meadori@codesourcery.com>
-+
-+ PR target/58595
-+ * config/arm/arm.c (arm_tls_symbol_p): Remove.
-+ (arm_legitimize_address): Call legitimize_tls_address for any
-+ arm_tls_referenced_p expression, handle constant addend. Call it
-+ before testing for !TARGET_ARM.
-+ (thumb_legitimize_address): Don't handle arm_tls_symbol_p here.
-+
-+2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r208750
-+ 2014-03-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate a
-+ pattern for vector nor instead of subtract from splat(-1).
-+ (altivec_expand_vec_perm_const_le): Likewise.
-+
-+ Backport from mainline r209235
-+ 2014-04-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Use vnand
-+ instead of vnor to exploit possible fusion opportunity in the
-+ future.
-+ (altivec_expand_vec_perm_const_le): Likewise.
-+
-+2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Revert following patch
-+ 2014-04-08 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ Backport from mainline
-+ 2014-04-08 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * config/rs6000/sync.md (AINT mode_iterator): Move definition.
-+ (loadsync_<mode>): Change mode.
-+ (load_quadpti, store_quadpti): New.
-+ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.
-+ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.
-+
-+2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r202642
-+ 2013-09-17 Alan Modra <amodra@gmail.com>
-+
-+ PR target/57589
-+ * config/rs6000/driver-rs6000.c (elf_platform): Revert 2013-06-11
-+ patch (r199972).
-+
-+2014-04-08 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ Backport from mainline
-+ 2014-04-08 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * config/rs6000/sync.md (AINT mode_iterator): Move definition.
-+ (loadsync_<mode>): Change mode.
-+ (load_quadpti, store_quadpti): New.
-+ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.
-+ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.
-+
-+2014-04-07 Martin Jambor <mjambor@suse.cz>
-+
-+ PR ipa/60640
-+ * ipa-cp.c (propagate_constants_accross_call): Do not propagate
-+ accross thunks.
-+
-+2014-04-07 Dominique d'Humieres <dominiq@lps.ens.fr>
-+
-+ Backport from mainline
-+ 2013-09-14 Iain Sandoe <iains@gcc.gnu.org>
-+
-+ PR target/48094
-+ * config/darwin.c (darwin_objc2_section): Note if ObjC Metadata
-+ is seen.
-+ (darwin_objc1_section): Likewise.
-+ (darwin_file_end): Emit Image Info section when required.
-+
-+2014-04-05 Alan Modra <amodra@gmail.com>
-+
-+ Apply from mainline
-+ 2014-01-28 Alan Modra <amodra@gmail.com>
-+ * Makefile.in (BUILD_CPPFLAGS): Do not use ALL_CPPFLAGS.
-+ * configure.ac <recursive call for build != host>: Define
-+ GENERATOR_FILE. Comment. Use CXX_FOR_BUILD, CXXFLAGS_FOR_BUILD
-+ and LD_FOR_BUILD too.
-+ * configure: Regenerate.
-+
-+2014-04-04 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ Backport from mainline r208895:
-+ 2014-03-28 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (fusion_gpr_load_p): Refuse optimization
-+ if it would clobber the stack pointer, even temporarily.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Back port from main line:
-+ 2014-04-01 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
-+ Document vec_vgbbd.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Back port mainline subversion id 209025.
-+ 2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/60735
-+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
-+ software floating point or no floating point registers, do not
-+ allow any type in the FPRs. Eliminate a test for SPE SIMD types
-+ in GPRs that occurs after we tested for GPRs that would never be
-+ true.
-+
-+ * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
-+ Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
-+ since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,
-+ specifically allow DDmode, since that does not use the SPE SIMD
-+ instructions.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r205308
-+ 2013-11-23 David Edelsohn <dje.gcc@gmail.com>
-+
-+ * config/rs6000/rs6000.c (IN_NAMED_SECTION): New macro.
-+ (rs6000_xcoff_select_section): Place decls with stricter alignment
-+ into named sections.
-+ (rs6000_xcoff_unique_section): Allow unique sections for
-+ uninitialized data with strict alignment.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * gcc/configure: Regenerate.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Back port from trunk
-+ 2013-04-25 Alan Modra <amodra@gmail.com>
-+
-+ PR target/57052
-+ * config/rs6000/rs6000.md (rotlsi3_internal7): Rename to
-+ rotlsi3_internal7le and condition on !BYTES_BIG_ENDIAN.
-+ (rotlsi3_internal8be): New BYTES_BIG_ENDIAN insn.
-+ Repeat for many other rotate/shift and mask patterns using subregs.
-+ Name lshiftrt insns.
-+ (ashrdisi3_noppc64): Rename to ashrdisi3_noppc64be and condition
-+ on WORDS_BIG_ENDIAN.
-+
-+ 2013-06-07 Alan Modra <amodra@gmail.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
-+ override user -mfp-in-toc.
-+ (offsettable_ok_by_alignment): Consider just the current access
-+ rather than the whole object, unless BLKmode. Handle
-+ CONSTANT_POOL_ADDRESS_P constants that lack a decl too.
-+ (use_toc_relative_ref): Allow CONSTANT_POOL_ADDRESS_P constants
-+ for -mcmodel=medium.
-+ * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't
-+ override user -mfp-in-toc or -msum-in-toc. Default to
-+ -mno-fp-in-toc for -mcmodel=medium.
-+
-+ 2013-06-18 Alan Modra <amodra@gmail.com>
-+
-+ * config/rs6000/rs6000.h (enum data_align): New.
-+ (LOCAL_ALIGNMENT, DATA_ALIGNMENT): Use rs6000_data_alignment.
-+ (DATA_ABI_ALIGNMENT): Define.
-+ (CONSTANT_ALIGNMENT): Correct comment.
-+ * config/rs6000/rs6000-protos.h (rs6000_data_alignment): Declare.
-+ * config/rs6000/rs6000.c (rs6000_data_alignment): New function.
-+
-+ 2013-07-11 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.md (""*tls_gd_low<TLSmode:tls_abi_suffix>"):
-+ Require GOT register as additional operand in UNSPEC.
-+ ("*tls_ld_low<TLSmode:tls_abi_suffix>"): Likewise.
-+ ("*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"): Likewise.
-+ ("*tls_got_tprel_low<TLSmode:tls_abi_suffix>"): Likewise.
-+ ("*tls_gd<TLSmode:tls_abi_suffix>"): Update splitter.
-+ ("*tls_ld<TLSmode:tls_abi_suffix>"): Likewise.
-+ ("tls_got_dtprel_<TLSmode:tls_abi_suffix>"): Likewise.
-+ ("tls_got_tprel_<TLSmode:tls_abi_suffix>"): Likewise.
-+
-+ 2014-01-23 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
-+ force flag_ira_loop_pressure if set via command line.
-+
-+ 2014-02-06 Alan Modra <amodra@gmail.com>
-+
-+ PR target/60032
-+ * config/rs6000/rs6000.c (rs6000_secondary_memory_needed_mode): Only
-+ change SDmode to DDmode when lra_in_progress.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ V1TImode Support
-+ Back port from trunk
-+ 2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (VEC_L): Add V1TI mode to vector types.
-+ (VEC_M): Likewise.
-+ (VEC_N): Likewise.
-+ (VEC_R): Likewise.
-+ (VEC_base): Likewise.
-+ (mov<MODE>, VEC_M modes): If we are loading TImode into VSX
-+ registers, we need to swap double words in little endian mode.
-+
-+ * config/rs6000/rs6000-modes.def (V1TImode): Add new vector mode
-+ to be a container mode for 128-bit integer operations added in ISA
-+ 2.07. Unlike TImode and PTImode, the preferred register set is
-+ the Altivec/VMX registers for the 128-bit operations.
-+
-+ * config/rs6000/rs6000-protos.h (rs6000_move_128bit_ok_p): Add
-+ declarations.
-+ (rs6000_split_128bit_ok_p): Likewise.
-+
-+ * config/rs6000/rs6000-builtin.def (BU_P8V_AV_3): Add new support
-+ macros for creating ISA 2.07 normal and overloaded builtin
-+ functions with 3 arguments.
-+ (BU_P8V_OVERLOAD_3): Likewise.
-+ (VPERM_1T): Add support for V1TImode in 128-bit vector operations
-+ for use as overloaded functions.
-+ (VPERM_1TI_UNS): Likewise.
-+ (VSEL_1TI): Likewise.
-+ (VSEL_1TI_UNS): Likewise.
-+ (ST_INTERNAL_1ti): Likewise.
-+ (LD_INTERNAL_1ti): Likewise.
-+ (XXSEL_1TI): Likewise.
-+ (XXSEL_1TI_UNS): Likewise.
-+ (VPERM_1TI): Likewise.
-+ (VPERM_1TI_UNS): Likewise.
-+ (XXPERMDI_1TI): Likewise.
-+ (SET_1TI): Likewise.
-+ (LXVD2X_V1TI): Likewise.
-+ (STXVD2X_V1TI): Likewise.
-+ (VEC_INIT_V1TI): Likewise.
-+ (VEC_SET_V1TI): Likewise.
-+ (VEC_EXT_V1TI): Likewise.
-+ (EQV_V1TI): Likewise.
-+ (NAND_V1TI): Likewise.
-+ (ORC_V1TI): Likewise.
-+ (VADDCUQ): Add support for 128-bit integer arithmetic instructions
-+ added in ISA 2.07. Add both normal 'altivec' builtins, and the
-+ overloaded builtin.
-+ (VADDUQM): Likewise.
-+ (VSUBCUQ): Likewise.
-+ (VADDEUQM): Likewise.
-+ (VADDECUQ): Likewise.
-+ (VSUBEUQM): Likewise.
-+ (VSUBECUQ): Likewise.
-+
-+ * config/rs6000/rs6000-c.c (__int128_type): New static to hold
-+ __int128_t and __uint128_t types.
-+ (__uint128_type): Likewise.
-+ (altivec_categorize_keyword): Add support for vector __int128_t,
-+ vector __uint128_t, vector __int128, and vector unsigned __int128
-+ as a container type for TImode operations that need to be done in
-+ VSX/Altivec registers.
-+ (rs6000_macro_to_expand): Likewise.
-+ (altivec_overloaded_builtins): Add ISA 2.07 overloaded functions
-+ to support 128-bit integer instructions vaddcuq, vadduqm,
-+ vaddecuq, vaddeuqm, vsubcuq, vsubuqm, vsubecuq, vsubeuqm.
-+ (altivec_resolve_overloaded_builtin): Add support for V1TImode.
-+
-+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support
-+ for V1TImode, and set up preferences to use VSX/Altivec
-+ registers. Setup VSX reload handlers.
-+ (rs6000_debug_reg_global): Likewise.
-+ (rs6000_init_hard_regno_mode_ok): Likewise.
-+ (rs6000_preferred_simd_mode): Likewise.
-+ (vspltis_constant): Do not allow V1TImode as easy altivec
-+ constants.
-+ (easy_altivec_constant): Likewise.
-+ (output_vec_const_move): Likewise.
-+ (rs6000_expand_vector_set): Convert V1TImode set and extract to
-+ simple move.
-+ (rs6000_expand_vector_extract): Likewise.
-+ (reg_offset_addressing_ok_p): Setup V1TImode to use VSX reg+reg
-+ addressing.
-+ (rs6000_const_vec): Add support for V1TImode.
-+ (rs6000_emit_le_vsx_load): Swap double words when loading or
-+ storing TImode/V1TImode.
-+ (rs6000_emit_le_vsx_store): Likewise.
-+ (rs6000_emit_le_vsx_move): Likewise.
-+ (rs6000_emit_move): Add support for V1TImode.
-+ (altivec_expand_ld_builtin): Likewise.
-+ (altivec_expand_st_builtin): Likewise.
-+ (altivec_expand_vec_init_builtin): Likewise.
-+ (altivec_expand_builtin): Likewise.
-+ (rs6000_init_builtins): Add support for V1TImode type. Add
-+ support for ISA 2.07 128-bit integer builtins. Define type names
-+ for the VSX/Altivec vector types.
-+ (altivec_init_builtins): Add support for overloaded vector
-+ functions with V1TImode type.
-+ (rs6000_preferred_reload_class): Prefer Altivec registers for
-+ V1TImode.
-+ (rs6000_move_128bit_ok_p): Move 128-bit move/split validation to
-+ external function.
-+ (rs6000_split_128bit_ok_p): Likewise.
-+ (rs6000_handle_altivec_attribute): Create V1TImode from vector
-+ __int128_t and vector __uint128_t.
-+
-+ * config/rs6000/vsx.md (VSX_L): Add V1TImode to vector iterators
-+ and mode attributes.
-+ (VSX_M): Likewise.
-+ (VSX_M2): Likewise.
-+ (VSm): Likewise.
-+ (VSs): Likewise.
-+ (VSr): Likewise.
-+ (VSv): Likewise.
-+ (VS_scalar): Likewise.
-+ (VS_double): Likewise.
-+ (vsx_set_v1ti): New builtin function to create V1TImode from
-+ TImode.
-+
-+ * config/rs6000/rs6000.h (TARGET_VADDUQM): New macro to say
-+ whether we support the ISA 2.07 128-bit integer arithmetic
-+ instructions.
-+ (ALTIVEC_OR_VSX_VECTOR_MODE): Add V1TImode.
-+ (enum rs6000_builtin_type_index): Add fields to hold V1TImode
-+ and TImode types for use with the builtin functions.
-+ (V1TI_type_node): Likewise.
-+ (unsigned_V1TI_type_node): Likewise.
-+ (intTI_type_internal_node): Likewise.
-+ (uintTI_type_internal_node): Likewise.
-+
-+ * config/rs6000/altivec.md (UNSPEC_VADDCUQ): New unspecs for ISA
-+ 2.07 128-bit builtin functions.
-+ (UNSPEC_VADDEUQM): Likewise.
-+ (UNSPEC_VADDECUQ): Likewise.
-+ (UNSPEC_VSUBCUQ): Likewise.
-+ (UNSPEC_VSUBEUQM): Likewise.
-+ (UNSPEC_VSUBECUQ): Likewise.
-+ (VM): Add V1TImode to vector mode iterators.
-+ (VM2): Likewise.
-+ (VI_unit): Likewise.
-+ (altivec_vadduqm): Add ISA 2.07 128-bit binary builtins.
-+ (altivec_vaddcuq): Likewise.
-+ (altivec_vsubuqm): Likewise.
-+ (altivec_vsubcuq): Likewise.
-+ (altivec_vaddeuqm): Likewise.
-+ (altivec_vaddecuq): Likewise.
-+ (altivec_vsubeuqm): Likewise.
-+ (altivec_vsubecuq): Likewise.
-+
-+ * config/rs6000/rs6000.md (FMOVE128_GPR): Add V1TImode to vector
-+ mode iterators.
-+ (BOOL_128): Likewise.
-+ (BOOL_REGS_OUTPUT): Likewise.
-+ (BOOL_REGS_OP1): Likewise.
-+ (BOOL_REGS_OP2): Likewise.
-+ (BOOL_REGS_UNARY): Likewise.
-+ (BOOL_REGS_AND_CR0): Likewise.
-+
-+ * config/rs6000/altivec.h (vec_vaddcuq): Add support for ISA 2.07
-+ 128-bit integer builtin support.
-+ (vec_vadduqm): Likewise.
-+ (vec_vaddecuq): Likewise.
-+ (vec_vaddeuqm): Likewise.
-+ (vec_vsubecuq): Likewise.
-+ (vec_vsubeuqm): Likewise.
-+ (vec_vsubcuq): Likewise.
-+ (vec_vsubuqm): Likewise.
-+
-+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
-+ Document vec_vaddcuq, vec_vadduqm, vec_vaddecuq, vec_vaddeuqm,
-+ vec_subecuq, vec_subeuqm, vec_vsubcuq, vec_vsubeqm builtins adding
-+ 128-bit integer add/subtract to ISA 2.07.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Apply mainline r207798
-+ 2014-02-26 Alan Modra <amodra@gmail.com>
-+ PR target/58675
-+ PR target/57935
-+ * config/rs6000/rs6000.c (rs6000_secondary_reload_inner): Use
-+ find_replacement on parts of insn rtl that might be reloaded.
-+
-+ Backport from mainline r208287
-+ 2014-03-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_preferred_reload_class): Disallow
-+ reload of PLUS rtx's outside of GENERAL_REGS or BASE_REGS; relax
-+ constraint on constants to permit them being loaded into
-+ GENERAL_REGS or BASE_REGS.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r207699.
-+ 2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/60137
-+ * config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter
-+ for VSX/Altivec vectors that land in GPR registers.
-+
-+ Backport from mainline r207808.
-+ 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/60203
-+ * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints.
-+ (mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves
-+ into 64-bit and 32-bit moves. On 64-bit moves, add support for
-+ using direct move instructions on ISA 2.07. Also adjust
-+ instruction length for 64-bit.
-+ (mov<mode>_64bit, TFmode/TDmode): Likewise.
-+ (mov<mode>_32bit, TFmode/TDmode): Likewise.
-+
-+ Backport from mainline r207868.
-+ 2014-02-18 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/60203
-+ * config/rs6000/rs6000.md (mov<mode>_64bit, TF/TDmode moves):
-+ Split 64-bit moves into 2 patterns. Do not allow the use of
-+ direct move for TDmode in little endian, since the decimal value
-+ has little endian bytes within a word, but the 64-bit pieces are
-+ ordered in a big endian fashion, and normal subreg's of TDmode are
-+ not allowed.
-+ (mov<mode>_64bit_dm): Likewise.
-+ (movtd_64bit_nodm): Likewise.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r207658
-+ 2014-02-06 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/sysv4.h (ENDIAN_SELECT): Do not attempt to enforce
-+ big-endian mode for -mcall-aixdesc, -mcall-freebsd, -mcall-netbsd,
-+ -mcall-openbsd, or -mcall-linux.
-+ (CC1_ENDIAN_BIG_SPEC): Remove.
-+ (CC1_ENDIAN_LITTLE_SPEC): Remove.
-+ (CC1_ENDIAN_DEFAULT_SPEC): Remove.
-+ (CC1_SPEC): Remove (always empty) %cc1_endian_... spec.
-+ (SUBTARGET_EXTRA_SPECS): Remove %cc1_endian_big, %cc1_endian_little,
-+ and %cc1_endian_default.
-+ * config/rs6000/sysv4le.h (CC1_ENDIAN_DEFAULT_SPEC): Remove.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Little Endian Vector API Support
-+ Backport from mainline r206443
-+ 2014-01-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove
-+ two duplicate entries.
-+
-+ Backport from mainline r206494
-+ 2014-01-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * doc/invoke.texi: Add -maltivec={be,le} options, and document
-+ default element-order behavior for -maltivec.
-+ * config/rs6000/rs6000.opt: Add -maltivec={be,le} options.
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Ensure
-+ that -maltivec={le,be} implies -maltivec; disallow -maltivec=le
-+ when targeting big endian, at least for now.
-+ * config/rs6000/rs6000.h: Add #define of VECTOR_ELT_ORDER_BIG.
-+
-+ Backport from mainline r206541
-+ 2014-01-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000-builtin.def: Fix pasto for VPKSDUS.
-+
-+ Backport from mainline r206590
-+ 2014-01-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
-+ Implement -maltivec=be for vec_insert and vec_extract.
-+
-+ Backport from mainline r206641
-+ 2014-01-15 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
-+
-+ * config/rs6000/altivec.md (mulv8hi3): Explicitly generate vmulesh
-+ and vmulosh rather than call gen_vec_widen_smult_*.
-+ (vec_widen_umult_even_v16qi): Test VECTOR_ELT_ORDER_BIG rather
-+ than BYTES_BIG_ENDIAN to determine use of even or odd instruction.
-+ (vec_widen_smult_even_v16qi): Likewise.
-+ (vec_widen_umult_even_v8hi): Likewise.
-+ (vec_widen_smult_even_v8hi): Likewise.
-+ (vec_widen_umult_odd_v16qi): Likewise.
-+ (vec_widen_smult_odd_v16qi): Likewise.
-+ (vec_widen_umult_odd_v8hi): Likewise.
-+ (vec_widen_smult_odd_v8hi): Likewise.
-+ (vec_widen_umult_hi_v16qi): Explicitly generate vmuleub and
-+ vmuloub rather than call gen_vec_widen_umult_*.
-+ (vec_widen_umult_lo_v16qi): Likewise.
-+ (vec_widen_smult_hi_v16qi): Explicitly generate vmulesb and
-+ vmulosb rather than call gen_vec_widen_smult_*.
-+ (vec_widen_smult_lo_v16qi): Likewise.
-+ (vec_widen_umult_hi_v8hi): Explicitly generate vmuleuh and vmulouh
-+ rather than call gen_vec_widen_umult_*.
-+ (vec_widen_umult_lo_v8hi): Likewise.
-+ (vec_widen_smult_hi_v8hi): Explicitly gnerate vmulesh and vmulosh
-+ rather than call gen_vec_widen_smult_*.
-+ (vec_widen_smult_lo_v8hi): Likewise.
-+
-+ Backport from mainline r207062
-+ 2014-01-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Remove
-+ correction for little endian...
-+ * config/rs6000/vsx.md (vsx_xxpermdi2_<mode>_1): ...and move it to
-+ here.
-+
-+ Backport from mainline r207262
-+ 2014-01-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Use
-+ CODE_FOR_altivec_vmrg*_direct rather than CODE_FOR_altivec_vmrg*.
-+ * config/rs6000/vsx.md (vsx_mergel_<mode>): Adjust for
-+ -maltivec=be with LE targets.
-+ (vsx_mergeh_<mode>): Likewise.
-+ * config/rs6000/altivec.md (UNSPEC_VMRG[HL]_DIRECT): New
-+ unspecs.
-+ (mulv8hi3): Use gen_altivec_vmrg[hl]w_direct.
-+ (altivec_vmrghb): Replace with define_expand and new
-+ *altivec_vmrghb_internal insn; adjust for -maltivec=be with LE
-+ targets.
-+ (altivec_vmrghb_direct): New define_insn.
-+ (altivec_vmrghh): Replace with define_expand and new
-+ *altivec_vmrghh_internal insn; adjust for -maltivec=be with LE
-+ targets.
-+ (altivec_vmrghh_direct): New define_insn.
-+ (altivec_vmrghw): Replace with define_expand and new
-+ *altivec_vmrghw_internal insn; adjust for -maltivec=be with LE
-+ targets.
-+ (altivec_vmrghw_direct): New define_insn.
-+ (*altivec_vmrghsf): Adjust for endianness.
-+ (altivec_vmrglb): Replace with define_expand and new
-+ *altivec_vmrglb_internal insn; adjust for -maltivec=be with LE
-+ targets.
-+ (altivec_vmrglb_direct): New define_insn.
-+ (altivec_vmrglh): Replace with define_expand and new
-+ *altivec_vmrglh_internal insn; adjust for -maltivec=be with LE
-+ targets.
-+ (altivec_vmrglh_direct): New define_insn.
-+ (altivec_vmrglw): Replace with define_expand and new
-+ *altivec_vmrglw_internal insn; adjust for -maltivec=be with LE
-+ targets.
-+ (altivec_vmrglw_direct): New define_insn.
-+ (*altivec_vmrglsf): Adjust for endianness.
-+ (vec_widen_umult_hi_v16qi): Use gen_altivec_vmrghh_direct.
-+ (vec_widen_umult_lo_v16qi): Use gen_altivec_vmrglh_direct.
-+ (vec_widen_smult_hi_v16qi): Use gen_altivec_vmrghh_direct.
-+ (vec_widen_smult_lo_v16qi): Use gen_altivec_vmrglh_direct.
-+ (vec_widen_umult_hi_v8hi): Use gen_altivec_vmrghw_direct.
-+ (vec_widen_umult_lo_v8hi): Use gen_altivec_vmrglw_direct.
-+ (vec_widen_smult_hi_v8hi): Use gen_altivec_vmrghw_direct.
-+ (vec_widen_smult_lo_v8hi): Use gen_altivec_vmrglw_direct.
-+
-+ Backport from mainline r207318
-+ 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc/config/rs6000/rs6000.c (rs6000_expand_vector_init): Use
-+ gen_vsx_xxspltw_v4sf_direct instead of gen_vsx_xxspltw_v4sf;
-+ remove element index adjustment for endian (now handled in vsx.md
-+ and altivec.md).
-+ (altivec_expand_vec_perm_const): Use
-+ gen_altivec_vsplt[bhw]_direct instead of gen_altivec_vsplt[bhw].
-+ * gcc/config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTW): New unspec.
-+ (vsx_xxspltw_<mode>): Adjust element index for little endian.
-+ * gcc/config/rs6000/altivec.md (altivec_vspltb): Divide into a
-+ define_expand and a new define_insn *altivec_vspltb_internal;
-+ adjust for -maltivec=be on a little endian target.
-+ (altivec_vspltb_direct): New.
-+ (altivec_vsplth): Divide into a define_expand and a new
-+ define_insn *altivec_vsplth_internal; adjust for -maltivec=be on a
-+ little endian target.
-+ (altivec_vsplth_direct): New.
-+ (altivec_vspltw): Divide into a define_expand and a new
-+ define_insn *altivec_vspltw_internal; adjust for -maltivec=be on a
-+ little endian target.
-+ (altivec_vspltw_direct): New.
-+ (altivec_vspltsf): Divide into a define_expand and a new
-+ define_insn *altivec_vspltsf_internal; adjust for -maltivec=be on
-+ a little endian target.
-+
-+ Backport from mainline r207326
-+ 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_expand_vector_init): Remove
-+ unused variable "field".
-+ * config/rs6000/vsx.md (vsx_mergel_<mode>): Add missing DONE.
-+ (vsx_mergeh_<mode>): Likewise.
-+ * config/rs6000/altivec.md (altivec_vmrghb): Likewise.
-+ (altivec_vmrghh): Likewise.
-+ (altivec_vmrghw): Likewise.
-+ (altivec_vmrglb): Likewise.
-+ (altivec_vmrglh): Likewise.
-+ (altivec_vmrglw): Likewise.
-+ (altivec_vspltb): Add missing uses.
-+ (altivec_vsplth): Likewise.
-+ (altivec_vspltw): Likewise.
-+ (altivec_vspltsf): Likewise.
-+
-+ Backport from mainline r207414
-+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec.
-+ (altivec_vsumsws): Add handling for -maltivec=be with a little
-+ endian target.
-+ (altivec_vsumsws_direct): New.
-+ (reduc_splus_<mode>): Call gen_altivec_vsumsws_direct instead of
-+ gen_altivec_vsumsws.
-+
-+ Backport from mainline r207415
-+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): Generalize
-+ for vector types other than V16QImode.
-+ * config/rs6000/altivec.md (altivec_vperm_<mode>): Change to a
-+ define_expand, and call altivec_expand_vec_perm_le when producing
-+ code with little endian element order.
-+ (*altivec_vperm_<mode>_internal): New insn having previous
-+ behavior of altivec_vperm_<mode>.
-+ (altivec_vperm_<mode>_uns): Change to a define_expand, and call
-+ altivec_expand_vec_perm_le when producing code with little endian
-+ element order.
-+ (*altivec_vperm_<mode>_uns_internal): New insn having previous
-+ behavior of altivec_vperm_<mode>_uns.
-+
-+ Backport from mainline r207520
-+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * altivec.md (UNSPEC_VPACK_UNS_UNS_MOD_DIRECT): New unspec.
-+ (UNSPEC_VUNPACK_HI_SIGN_DIRECT): Likewise.
-+ (UNSPEC_VUNPACK_LO_SIGN_DIRECT): Likewise.
-+ (mulv8hi3): Use gen_altivec_vpkuwum_direct instead of
-+ gen_altivec_vpkuwum.
-+ (altivec_vpkpx): Test for VECTOR_ELT_ORDER_BIG instead of for
-+ BYTES_BIG_ENDIAN.
-+ (altivec_vpks<VI_char>ss): Likewise.
-+ (altivec_vpks<VI_char>us): Likewise.
-+ (altivec_vpku<VI_char>us): Likewise.
-+ (altivec_vpku<VI_char>um): Likewise.
-+ (altivec_vpku<VI_char>um_direct): New (copy of
-+ altivec_vpku<VI_char>um that still relies on BYTES_BIG_ENDIAN, for
-+ internal use).
-+ (altivec_vupkhs<VU_char>): Emit vupkls* instead of vupkhs* when
-+ target is little endian and -maltivec=be is not specified.
-+ (*altivec_vupkhs<VU_char>_direct): New (copy of
-+ altivec_vupkhs<VU_char> that always emits vupkhs*, for internal
-+ use).
-+ (altivec_vupkls<VU_char>): Emit vupkhs* instead of vupkls* when
-+ target is little endian and -maltivec=be is not specified.
-+ (*altivec_vupkls<VU_char>_direct): New (copy of
-+ altivec_vupkls<VU_char> that always emits vupkls*, for internal
-+ use).
-+ (altivec_vupkhpx): Emit vupklpx instead of vupkhpx when target is
-+ little endian and -maltivec=be is not specified.
-+ (altivec_vupklpx): Emit vupkhpx instead of vupklpx when target is
-+ little endian and -maltivec=be is not specified.
-+
-+ Backport from mainline r207521
-+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (altivec_vsum2sws): Adjust code
-+ generation for -maltivec=be.
-+ (altivec_vsumsws): Simplify redundant test.
-+
-+ Backport from mainline r207525
-+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Change
-+ CODE_FOR_altivec_vpku[hw]um to
-+ CODE_FOR_altivec_vpku[hw]um_direct.
-+ * config/rs6000/altivec.md (vec_unpacks_hi_<VP_small_lc>): Change
-+ UNSPEC_VUNPACK_HI_SIGN to UNSPEC_VUNPACK_HI_SIGN_DIRECT.
-+ (vec_unpacks_lo_<VP_small_lc>): Change UNSPEC_VUNPACK_LO_SIGN to
-+ UNSPEC_VUNPACK_LO_SIGN_DIRECT.
-+
-+ Backport from mainline r207814.
-+ 2014-02-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vsx.md (vsx_xxpermdi_<mode>): Handle little
-+ endian targets.
-+
-+ Backport from mainline r207815.
-+ 2014-02-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (p8_vmrgew): Handle little endian
-+ targets.
-+ (p8_vmrgow): Likewise.
-+
-+ Backport from mainline r207919.
-+ 2014-02-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (vspltis_constant): Fix most significant
-+ bit of zero.
-+
-+ Backport from mainline 208019
-+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (altivec_lvxl): Rename as
-+ *altivec_lvxl_<mode>_internal and use VM2 iterator instead of
-+ V4SI.
-+ (altivec_lvxl_<mode>): New define_expand incorporating
-+ -maltivec=be semantics where needed.
-+ (altivec_lvx): Rename as *altivec_lvx_<mode>_internal.
-+ (altivec_lvx_<mode>): New define_expand incorporating -maltivec=be
-+ semantics where needed.
-+ (altivec_stvx): Rename as *altivec_stvx_<mode>_internal.
-+ (altivec_stvx_<mode>): New define_expand incorporating
-+ -maltivec=be semantics where needed.
-+ (altivec_stvxl): Rename as *altivec_stvxl_<mode>_internal and use
-+ VM2 iterator instead of V4SI.
-+ (altivec_stvxl_<mode>): New define_expand incorporating
-+ -maltivec=be semantics where needed.
-+ * config/rs6000/rs6000-builtin.def: Add new built-in definitions
-+ LVXL_V2DF, LVXL_V2DI, LVXL_V4SF, LVXL_V4SI, LVXL_V8HI, LVXL_V16QI,
-+ LVX_V2DF, LVX_V2DI, LVX_V4SF, LVX_V4SI, LVX_V8HI, LVX_V16QI,
-+ STVX_V2DF, STVX_V2DI, STVX_V4SF, STVX_V4SI, STVX_V8HI, STVX_V16QI,
-+ STVXL_V2DF, STVXL_V2DI, STVXL_V4SF, STVXL_V4SI, STVXL_V8HI,
-+ STVXL_V16QI.
-+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Replace
-+ ALTIVEC_BUILTIN_LVX with ALTIVEC_BUILTIN_LVX_<MODE> throughout;
-+ similarly for ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_STVX, and
-+ ALTIVEC_BUILTIN_STVXL.
-+ * config/rs6000/rs6000-protos.h (altivec_expand_lvx_be): New
-+ prototype.
-+ (altivec_expand_stvx_be): Likewise.
-+ * config/rs6000/rs6000.c (swap_selector_for_mode): New function.
-+ (altivec_expand_lvx_be): Likewise.
-+ (altivec_expand_stvx_be): Likewise.
-+ (altivec_expand_builtin): Add cases for
-+ ALTIVEC_BUILTIN_STVX_<MODE>, ALTIVEC_BUILTIN_STVXL_<MODE>,
-+ ALTIVEC_BUILTIN_LVXL_<MODE>, and ALTIVEC_BUILTIN_LVX_<MODE>.
-+ (altivec_init_builtins): Add definitions for
-+ __builtin_altivec_lvxl_<mode>, __builtin_altivec_lvx_<mode>,
-+ __builtin_altivec_stvx_<mode>, and
-+ __builtin_altivec_stvxl_<mode>.
-+
-+ Backport from mainline 208021
-+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (altivec_vsumsws): Replace second
-+ vspltw with vsldoi.
-+ (reduc_uplus_v16qi): Use gen_altivec_vsumsws_direct instead of
-+ gen_altivec_vsumsws.
-+
-+ Backport from mainline 208049
-+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (altivec_lve<VI_char>x): Replace
-+ define_insn with define_expand and new define_insn
-+ *altivec_lve<VI_char>x_internal.
-+ (altivec_stve<VI_char>x): Replace define_insn with define_expand
-+ and new define_insn *altivec_stve<VI_char>x_internal.
-+ * config/rs6000/rs6000-protos.h (altivec_expand_stvex_be): New
-+ prototype.
-+ * config/rs6000/rs6000.c (altivec_expand_lvx_be): Document use by
-+ lve*x built-ins.
-+ (altivec_expand_stvex_be): New function.
-+
-+ Backport from mainline
-+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+ * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Relax assert
-+ to permit subregs.
-+
-+ Backport from mainline
-+ 2014-02-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+ * config/rs6000/vector.md (*vector_unordered<mode>): Change split
-+ to use canonical form for nor<mode>3.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2014-02-04 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.opt (-mlra): Add switch to enable the LRA
-+ register allocator.
-+
-+ * config/rs6000/rs6000.c (TARGET_LRA_P): Add support for -mlra to
-+ enable the LRA register allocator. Back port the changes from the
-+ trunk to enable LRA.
-+ (rs6000_legitimate_offset_address_p): Likewise.
-+ (legitimate_lo_sum_address_p): Likewise.
-+ (use_toc_relative_ref): Likewise.
-+ (rs6000_legitimate_address_p): Likewise.
-+ (rs6000_emit_move): Likewise.
-+ (rs6000_secondary_memory_needed_mode): Likewise.
-+ (rs6000_alloc_sdmode_stack_slot): Likewise.
-+ (rs6000_lra_p): Likewise.
-+
-+ * config/rs6000/sync.md (load_lockedti): Copy TI/PTI variables by
-+ 64-bit parts to force the register allocator to allocate even/odd
-+ register pairs for the quad word atomic instructions.
-+ (store_conditionalti): Likewise.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Back port from mainline
-+ 2014-01-23 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/59909
-+ * doc/invoke.texi (RS/6000 and PowerPC Options): Document
-+ -mquad-memory-atomic. Update -mquad-memory documentation to say
-+ it is only used for non-atomic loads/stores.
-+
-+ * config/rs6000/predicates.md (quad_int_reg_operand): Allow either
-+ -mquad-memory or -mquad-memory-atomic switches.
-+
-+ * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
-+ -mquad-memory-atomic to ISA 2.07 support.
-+
-+ * config/rs6000/rs6000.opt (-mquad-memory-atomic): Add new switch
-+ to separate support of normal quad word memory operations (ldq,
-+ stq) from the atomic quad word memory operations.
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-+ support to separate non-atomic quad word operations from atomic
-+ quad word operations. Disable non-atomic quad word operations in
-+ little endian mode so that we don't have to swap words after the
-+ load and before the store.
-+ (quad_load_store_p): Add comment about atomic quad word support.
-+ (rs6000_opt_masks): Add -mquad-memory-atomic to the list of
-+ options printed with -mdebug=reg.
-+
-+ * config/rs6000/rs6000.h (TARGET_SYNC_TI): Use
-+ -mquad-memory-atomic as the test for whether we have quad word
-+ atomic instructions.
-+ (TARGET_SYNC_HI_QI): If either -mquad-memory-atomic,
-+ -mquad-memory, or -mp8-vector are used, allow byte/half-word
-+ atomic operations.
-+
-+ * config/rs6000/sync.md (load_lockedti): Insure that the address
-+ is a proper indexed or indirect address for the lqarx instruction.
-+ On little endian systems, swap the hi/lo registers after the lqarx
-+ instruction.
-+ (load_lockedpti): Use indexed_or_indirect_operand predicate to
-+ insure the address is valid for the lqarx instruction.
-+ (store_conditionalti): Insure that the address is a proper indexed
-+ or indirect address for the stqcrx. instruction. On little endian
-+ systems, swap the hi/lo registers before doing the stqcrx.
-+ instruction.
-+ (store_conditionalpti): Use indexed_or_indirect_operand predicate to
-+ insure the address is valid for the stqcrx. instruction.
-+
-+ * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):
-+ Define __QUAD_MEMORY__ and __QUAD_MEMORY_ATOMIC__ based on what
-+ type of quad memory support is available.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Apply mainline r202190, powerpc64le multilibs and multiarch dir
-+ 2013-09-03 Alan Modra <amodra@gmail.com>
-+
-+ * config.gcc (powerpc*-*-linux*): Add support for little-endian
-+ multilibs to big-endian target and vice versa.
-+ * config/rs6000/t-linux64: Use := assignment on all vars.
-+ (MULTILIB_EXTRA_OPTS): Remove fPIC.
-+ (MULTILIB_OSDIRNAMES): Specify using mapping from multilib_options.
-+ * config/rs6000/t-linux64le: New file.
-+ * config/rs6000/t-linux64bele: New file.
-+ * config/rs6000/t-linux64lebe: New file.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Back port from mainline
-+ 2014-01-16 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/59844
-+ * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little
-+ endian support, remove tests for WORDS_BIG_ENDIAN.
-+ (p8_mfvsrd_3_<mode>): Likewise.
-+ (reload_gpr_from_vsx<mode>): Likewise.
-+ (reload_gpr_from_vsxsf): Likewise.
-+ (p8_mfvsrd_4_disf): Likewise.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-04-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ PR target/56843
-+ * config/rs6000/rs6000.c (rs6000_emit_swdiv_high_precision): Remove.
-+ (rs6000_emit_swdiv_low_precision): Remove.
-+ (rs6000_emit_swdiv): Rewrite to handle between one and four
-+ iterations of Newton-Raphson generally; modify required number of
-+ iterations for some cases.
-+ * config/rs6000/rs6000.h (RS6000_RECIP_HIGH_PRECISION_P): Remove.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-08-19 Peter Bergner <bergner@vnet.ibm.com>
-+ Jakub Jelinek <jakub@redhat.com>
-+
-+ * builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin.
-+ (BUILT_IN_FABSD64): Likewise.
-+ (BUILT_IN_FABSD128): Likewise.
-+ * builtins.c (expand_builtin): Add support for
-+ new DFP ABS builtins.
-+ (fold_builtin_1): Likewise.
-+ * config/rs6000/dfp.md
-+ (*abstd2_fpr): Handle non-overlapping destination
-+ and source operands.
-+ (*nabstd2_fpr): Likewise.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Apply mainline r205060.
-+ 2013-11-20 Alan Modra <amodra@gmail.com>
-+ * config/rs6000/sysv4.h (CC1_ENDIAN_LITTLE_SPEC): Define as empty.
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Default
-+ to strict alignment on older processors when little-endian.
-+ * config/rs6000/linux64.h (PROCESSOR_DEFAULT64): Default to power8
-+ for ELFv2.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ POWER ELFv2 ABI Support
-+ Backport from mainline r204842:
-+
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * doc/invoke.texi (-mabi=elfv1, -mabi=elfv2): Document.
-+
-+ Backport from mainline r204809:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/sysv4le.h (LINUX64_DEFAULT_ABI_ELFv2): Define.
-+
-+ Backport from mainline r204808:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Alan Modra <amodra@gmail.com>
-+
-+ * config/rs6000/rs6000.h (RS6000_SAVE_AREA): Handle ABI_ELFv2.
-+ (RS6000_SAVE_TOC): Remove.
-+ (RS6000_TOC_SAVE_SLOT): New macro.
-+ * config/rs6000/rs6000.c (rs6000_parm_offset): New function.
-+ (rs6000_parm_start): Use it.
-+ (rs6000_function_arg_advance_1): Likewise.
-+ (rs6000_emit_prologue): Use RS6000_TOC_SAVE_SLOT.
-+ (rs6000_emit_epilogue): Likewise.
-+ (rs6000_call_aix): Likewise.
-+ (rs6000_output_function_prologue): Do not save/restore r11
-+ around calling _mcount for ABI_ELFv2.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Alan Modra <amodra@gmail.com>
-+
-+ * config/rs6000/rs6000-protos.h (rs6000_reg_parm_stack_space):
-+ Add prototype.
-+ * config/rs6000/rs6000.h (RS6000_REG_SAVE): Remove.
-+ (REG_PARM_STACK_SPACE): Call rs6000_reg_parm_stack_space.
-+ * config/rs6000/rs6000.c (rs6000_parm_needs_stack): New function.
-+ (rs6000_function_parms_need_stack): Likewise.
-+ (rs6000_reg_parm_stack_space): Likewise.
-+ (rs6000_function_arg): Do not replace BLKmode by Pmode when
-+ returning a register argument.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Michael Gschwind <mkg@us.ibm.com>
-+
-+ * config/rs6000/rs6000.h (FP_ARG_MAX_RETURN): New macro.
-+ (ALTIVEC_ARG_MAX_RETURN): Likewise.
-+ (FUNCTION_VALUE_REGNO_P): Use them.
-+ * config/rs6000/rs6000.c (TARGET_RETURN_IN_MSB): Define.
-+ (rs6000_return_in_msb): New function.
-+ (rs6000_return_in_memory): Handle ELFv2 homogeneous aggregates.
-+ Handle aggregates of up to 16 bytes for ELFv2.
-+ (rs6000_function_value): Handle ELFv2 homogeneous aggregates.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Michael Gschwind <mkg@us.ibm.com>
-+
-+ * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define.
-+ * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function.
-+ (rs6000_discover_homogeneous_aggregate): Likewise.
-+ (rs6000_function_arg_boundary): Handle homogeneous aggregates.
-+ (rs6000_function_arg_advance_1): Likewise.
-+ (rs6000_function_arg): Likewise.
-+ (rs6000_arg_partial_bytes): Likewise.
-+ (rs6000_psave_function_arg): Handle BLKmode arguments.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Michael Gschwind <mkg@us.ibm.com>
-+
-+ * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define.
-+ * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function.
-+ (rs6000_discover_homogeneous_aggregate): Likewise.
-+ (rs6000_function_arg_boundary): Handle homogeneous aggregates.
-+ (rs6000_function_arg_advance_1): Likewise.
-+ (rs6000_function_arg): Likewise.
-+ (rs6000_arg_partial_bytes): Likewise.
-+ (rs6000_psave_function_arg): Handle BLKmode arguments.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (machine_function): New member
-+ r2_setup_needed.
-+ (rs6000_emit_prologue): Set r2_setup_needed if necessary.
-+ (rs6000_output_mi_thunk): Set r2_setup_needed.
-+ (rs6000_output_function_prologue): Output global entry point
-+ prologue and local entry point marker if needed for ABI_ELFv2.
-+ Output -mprofile-kernel code here.
-+ (output_function_profiler): Do not output -mprofile-kernel
-+ code here; moved to rs6000_output_function_prologue.
-+ (rs6000_file_start): Output ".abiversion 2" for ABI_ELFv2.
-+
-+ (rs6000_emit_move): Do not handle dot symbols for ABI_ELFv2.
-+ (rs6000_output_function_entry): Likewise.
-+ (rs6000_assemble_integer): Likewise.
-+ (rs6000_elf_encode_section_info): Likewise.
-+ (rs6000_elf_declare_function_name): Do not create dot symbols
-+ or .opd section for ABI_ELFv2.
-+
-+ (rs6000_trampoline_size): Update for ABI_ELFv2 trampolines.
-+ (rs6000_trampoline_init): Likewise.
-+ (rs6000_elf_file_end): Call file_end_indicate_exec_stack
-+ for ABI_ELFv2.
-+
-+ (rs6000_call_aix): Handle ELFv2 indirect calls. Do not check
-+ for function descriptors in ABI_ELFv2.
-+
-+ * config/rs6000/rs6000.md ("*call_indirect_aix<mode>"): Support
-+ on ABI_AIX only, not ABI_ELFv2.
-+ ("*call_value_indirect_aix<mode>"): Likewise.
-+ ("*call_indirect_elfv2<mode>"): New pattern.
-+ ("*call_value_indirect_elfv2<mode>"): Likewise.
-+
-+ * config/rs6000/predicates.md ("symbol_ref_operand"): Do not
-+ check for function descriptors in ABI_ELFv2.
-+ ("current_file_function_operand"): Likewise.
-+
-+ * config/rs6000/ppc-asm.h [__powerpc64__ && _CALL_ELF == 2]:
-+ (toc): Undefine.
-+ (FUNC_NAME): Define ELFv2 variant.
-+ (JUMP_TARGET): Likewise.
-+ (FUNC_START): Likewise.
-+ (HIDDEN_FUNC): Likewise.
-+ (FUNC_END): Likeiwse.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config.gcc [powerpc*-*-* | rs6000-*-*]: Support --with-abi=elfv1
-+ and --with-abi=elfv2.
-+ * config/rs6000/option-defaults.h (OPTION_DEFAULT_SPECS): Add "abi".
-+ * config/rs6000/rs6000.opt (mabi=elfv1): New option.
-+ (mabi=elfv2): Likewise.
-+ * config/rs6000/rs6000-opts.h (enum rs6000_abi): Add ABI_ELFv2.
-+ * config/rs6000/linux64.h (DEFAULT_ABI): Do not hard-code to AIX_ABI
-+ if !RS6000_BI_ARCH.
-+ (ELFv2_ABI_CHECK): New macro.
-+ (SUBSUBTARGET_OVERRIDE_OPTIONS): Use it to decide whether to set
-+ rs6000_current_abi to ABI_AIX or ABI_ELFv2.
-+ (GLIBC_DYNAMIC_LINKER64): Support ELFv2 ld.so version.
-+ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Predefine
-+ _CALL_ELF and __STRUCT_PARM_ALIGN__ if appropriate.
-+
-+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Handle ABI_ELFv2.
-+ (debug_stack_info): Likewise.
-+ (rs6000_file_start): Treat ABI_ELFv2 the same as ABI_AIX.
-+ (rs6000_legitimize_tls_address): Likewise.
-+ (rs6000_conditional_register_usage): Likewise.
-+ (rs6000_emit_move): Likewise.
-+ (init_cumulative_args): Likewise.
-+ (rs6000_function_arg_advance_1): Likewise.
-+ (rs6000_function_arg): Likewise.
-+ (rs6000_arg_partial_bytes): Likewise.
-+ (rs6000_output_function_entry): Likewise.
-+ (rs6000_assemble_integer): Likewise.
-+ (rs6000_savres_strategy): Likewise.
-+ (rs6000_stack_info): Likewise.
-+ (rs6000_function_ok_for_sibcall): Likewise.
-+ (rs6000_emit_load_toc_table): Likewise.
-+ (rs6000_savres_routine_name): Likewise.
-+ (ptr_regno_for_savres): Likewise.
-+ (rs6000_emit_prologue): Likewise.
-+ (rs6000_emit_epilogue): Likewise.
-+ (rs6000_output_function_epilogue): Likewise.
-+ (output_profile_hook): Likewise.
-+ (output_function_profiler): Likewise.
-+ (rs6000_trampoline_size): Likewise.
-+ (rs6000_trampoline_init): Likewise.
-+ (rs6000_elf_output_toc_section_asm_op): Likewise.
-+ (rs6000_elf_encode_section_info): Likewise.
-+ (rs6000_elf_reloc_rw_mask): Likewise.
-+ (rs6000_elf_declare_function_name): Likewise.
-+ (rs6000_function_arg_boundary): Treat ABI_ELFv2 the same as ABI_AIX,
-+ except that rs6000_compat_align_parm is always assumed false.
-+ (rs6000_gimplify_va_arg): Likewise.
-+ (rs6000_call_aix): Update comment.
-+ (rs6000_sibcall_aix): Likewise.
-+ * config/rs6000/rs6000.md ("tls_gd_aix<TLSmode:tls_abi_suffix>"):
-+ Treat ABI_ELFv2 the same as ABI_AIX.
-+ ("*tls_gd_call_aix<TLSmode:tls_abi_suffix>"): Likewise.
-+ ("tls_ld_aix<TLSmode:tls_abi_suffix>"): Likewise.
-+ ("*tls_ld_call_aix<TLSmode:tls_abi_suffix>"): Likewise.
-+ ("load_toc_aix_si"): Likewise.
-+ ("load_toc_aix_di"): Likewise.
-+ ("call"): Likewise.
-+ ("call_value"): Likewise.
-+ ("*call_local_aix<mode>"): Likewise.
-+ ("*call_value_local_aix<mode>"): Likewise.
-+ ("*call_nonlocal_aix<mode>"): Likewise.
-+ ("*call_value_nonlocal_aix<mode>"): Likewise.
-+ ("*call_indirect_aix<mode>"): Likewise.
-+ ("*call_value_indirect_aix<mode>"): Likewise.
-+ ("sibcall"): Likewise.
-+ ("sibcall_value"): Likewise.
-+ ("*sibcall_aix<mode>"): Likewise.
-+ ("*sibcall_value_aix<mode>"): Likewise.
-+ * config/rs6000/predicates.md ("symbol_ref_operand"): Likewise.
-+ ("current_file_function_operand"): Likewise.
-+
-+ Backport from mainline r204807:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_arg_partial_bytes): Simplify logic
-+ by making use of the fact that for vector / floating point arguments
-+ passed both in VRs/FPRs and in the fixed parameter area, the partial
-+ bytes mechanism is in fact not used.
-+
-+ Backport from mainline r204806:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_psave_function_arg): New function.
-+ (rs6000_finish_function_arg): Likewise.
-+ (rs6000_function_arg): Use rs6000_psave_function_arg and
-+ rs6000_finish_function_arg to handle both vector and floating
-+ point arguments that are also passed in GPRs / the stack.
-+
-+ Backport from mainline r204805:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (USE_FP_FOR_ARG_P): Remove TYPE argument.
-+ (USE_ALTIVEC_FOR_ARG_P): Likewise.
-+ (rs6000_darwin64_record_arg_advance_recurse): Update uses.
-+ (rs6000_function_arg_advance_1):Likewise.
-+ (rs6000_darwin64_record_arg_recurse): Likewise.
-+ (rs6000_function_arg): Likewise.
-+ (rs6000_arg_partial_bytes): Likewise.
-+
-+ Backport from mainline r204804:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Replace
-+ "DEFAULT_ABI != ABI_AIX" test by testing for ABI_V4 or ABI_DARWIN.
-+ (rs6000_savres_strategy): Likewise.
-+ (rs6000_return_addr): Likewise.
-+ (rs6000_emit_load_toc_table): Replace "DEFAULT_ABI != ABI_AIX" by
-+ testing for ABI_V4 (since ABI_DARWIN is impossible here).
-+ (rs6000_emit_prologue): Likewise.
-+ (legitimate_lo_sum_address_p): Simplify DEFAULT_ABI test.
-+ (rs6000_elf_declare_function_name): Remove duplicated test.
-+ * config/rs6000/rs6000.md ("load_toc_v4_PIC_1"): Explicitly test
-+ for ABI_V4 (instead of "DEFAULT_ABI != ABI_AIX" test).
-+ ("load_toc_v4_PIC_1_normal"): Likewise.
-+ ("load_toc_v4_PIC_1_476"): Likewise.
-+ ("load_toc_v4_PIC_1b"): Likewise.
-+ ("load_toc_v4_PIC_1b_normal"): Likewise.
-+ ("load_toc_v4_PIC_1b_476"): Likewise.
-+ ("load_toc_v4_PIC_2"): Likewise.
-+ ("load_toc_v4_PIC_3b"): Likewise.
-+ ("load_toc_v4_PIC_3c"): Likewise.
-+ * config/rs6000/rs6000.h (RS6000_REG_SAVE): Simplify DEFAULT_ABI test.
-+ (RS6000_SAVE_AREA): Likewise.
-+ (FP_ARG_MAX_REG): Likewise.
-+ (RETURN_ADDRESS_OFFSET): Likewise.
-+ * config/rs6000/sysv.h (TARGET_TOC): Test for ABI_V4 instead
-+ of ABI_AIX.
-+ (SUBTARGET_OVERRIDE_OPTIONS): Likewise.
-+ (MINIMAL_TOC_SECTION_ASM_OP): Likewise.
-+
-+ Backport from mainline r204803:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_call_indirect_aix): Rename to ...
-+ (rs6000_call_aix): ... this. Handle both direct and indirect calls.
-+ Create call insn directly instead of via various gen_... routines.
-+ Mention special registers used by the call in CALL_INSN_FUNCTION_USAGE.
-+ (rs6000_sibcall_aix): New function.
-+ * config/rs6000/rs6000.md (TOC_SAVE_OFFSET_32BIT): Remove.
-+ (TOC_SAVE_OFFSET_64BIT): Likewise.
-+ (AIX_FUNC_DESC_TOC_32BIT): Likewise.
-+ (AIX_FUNC_DESC_TOC_64BIT): Likewise.
-+ (AIX_FUNC_DESC_SC_32BIT): Likewise.
-+ (AIX_FUNC_DESC_SC_64BIT): Likewise.
-+ ("call" expander): Call rs6000_call_aix.
-+ ("call_value" expander): Likewise.
-+ ("call_indirect_aix<ptrsize>"): Replace this pattern ...
-+ ("call_indirect_aix<ptrsize>_nor11"): ... and this pattern ...
-+ ("*call_indirect_aix<mode>"): ... by this insn pattern.
-+ ("call_value_indirect_aix<ptrsize>"): Replace this pattern ...
-+ ("call_value_indirect_aix<ptrsize>_nor11"): ... and this pattern ...
-+ ("*call_value_indirect_aix<mode>"): ... by this insn pattern.
-+ ("*call_nonlocal_aix32", "*call_nonlocal_aix64"): Replace by ...
-+ ("*call_nonlocal_aix<mode>"): ... this pattern.
-+ ("*call_value_nonlocal_aix32", "*call_value_nonlocal_aix64"): Replace
-+ ("*call_value_nonlocal_aix<mode>"): ... by this pattern.
-+ ("*call_local_aix<mode>"): New insn pattern.
-+ ("*call_value_local_aix<mode>"): Likewise.
-+ ("sibcall" expander): Call rs6000_sibcall_aix.
-+ ("sibcall_value" expander): Likewise. Move earlier in file.
-+ ("*sibcall_nonlocal_aix<mode>"): Replace by ...
-+ ("*sibcall_aix<mode>"): ... this pattern.
-+ ("*sibcall_value_nonlocal_aix<mode>"): Replace by ...
-+ ("*sibcall_value_aix<mode>"): ... this pattern.
-+ * config/rs6000/rs6000-protos.h (rs6000_call_indirect_aix): Remove.
-+ (rs6000_call_aix): Add prototype.
-+ (rs6000_sibcall_aix): Likewise.
-+
-+ Backport from mainline r204799:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_emit_prologue): Do not place a
-+ RTX_FRAME_RELATED_P marker on the UNSPEC_MOVESI_FROM_CR insn.
-+ Instead, add USEs of all modified call-saved CR fields to the
-+ insn storing the result to the stack slot, and provide an
-+ appropriate REG_FRAME_RELATED_EXPR for that insn.
-+ * config/rs6000/rs6000.md ("*crsave"): New insn pattern.
-+ * config/rs6000/predicates.md ("crsave_operation"): New predicate.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ ELFv2 ABI Call Support
-+ Backport from mainline r204798:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ Alan Modra <amodra@gmail.com>
-+
-+ * function.c (assign_parms): Use all.reg_parm_stack_space instead
-+ of re-evaluating REG_PARM_STACK_SPACE target macro.
-+ (locate_and_pad_parm): New parameter REG_PARM_STACK_SPACE. Use it
-+ instead of evaluating target macro REG_PARM_STACK_SPACE every time.
-+ (assign_parm_find_entry_rtl): Update call.
-+ * calls.c (initialize_argument_information): Update call.
-+ (emit_library_call_value_1): Likewise.
-+ * expr.h (locate_and_pad_parm): Update prototype.
-+
-+ Backport from mainline r204797:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * calls.c (store_unaligned_arguments_into_pseudos): Skip PARALLEL
-+ arguments.
-+
-+ Backport from mainline r197003:
-+
-+ 2013-03-23 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * calls.c (expand_call): Add missing guard to code handling return
-+ of non-BLKmode structures in MSB.
-+ * function.c (expand_function_end): Likewise.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r201750.
-+ Note: Default setting of -mcompat-align-parm inverted!
-+
-+ 2013-08-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ PR target/57949
-+ * doc/invoke.texi: Add documentation of mcompat-align-parm
-+ option.
-+ * config/rs6000/rs6000.opt: Add mcompat-align-parm option.
-+ * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX
-+ and Linux, correct BLKmode alignment when 128-bit alignment is
-+ required and compatibility flag is not set.
-+ (rs6000_gimplify_va_arg): For AIX and Linux, honor specified
-+ alignment for zero-size arguments when compatibility flag is not
-+ set.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Little Endian Vector Support
-+ Backport from mainline r205333
-+ 2013-11-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Correct
-+ for little endian.
-+
-+ Backport from mainline r205241
-+ 2013-11-21 Bill Schmidt <wschmidt@vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (vec_pack_trunc_v2df): Revert previous
-+ little endian change.
-+ (vec_pack_sfix_trunc_v2df): Likewise.
-+ (vec_pack_ufix_trunc_v2df): Likewise.
-+ * config/rs6000/rs6000.c (rs6000_expand_interleave): Correct
-+ double checking of endianness.
-+
-+ Backport from mainline r205146
-+ 2013-11-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vsx.md (vsx_set_<mode>): Adjust for little endian.
-+ (vsx_extract_<mode>): Likewise.
-+ (*vsx_extract_<mode>_one_le): New LE variant on
-+ *vsx_extract_<mode>_zero.
-+ (vsx_extract_v4sf): Adjust for little endian.
-+
-+ Backport from mainline r205080
-+ 2013-11-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Adjust
-+ V16QI vector splat case for little endian.
-+
-+ Backport from mainline r205045:
-+
-+ 2013-11-19 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/vector.md ("mov<mode>"): Do not call
-+ rs6000_emit_le_vsx_move to move into or out of GPRs.
-+ * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Assert
-+ source and destination are not GPR hard regs.
-+
-+ Backport from mainline r204920
-+ 2011-11-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_frame_related): Add split_reg
-+ parameter and use it in REG_FRAME_RELATED_EXPR note.
-+ (emit_frame_save): Call rs6000_frame_related with extra NULL_RTX
-+ parameter.
-+ (rs6000_emit_prologue): Likewise, but for little endian VSX
-+ stores, pass the source register of the store instead.
-+
-+ Backport from mainline r204862
-+ 2013-11-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (UNSPEC_VPERM_X, UNSPEC_VPERM_UNS_X):
-+ Remove.
-+ (altivec_vperm_<mode>): Revert earlier little endian change.
-+ (*altivec_vperm_<mode>_internal): Remove.
-+ (altivec_vperm_<mode>_uns): Revert earlier little endian change.
-+ (*altivec_vperm_<mode>_uns_internal): Remove.
-+ * config/rs6000/vector.md (vec_realign_load_<mode>): Revise
-+ commentary.
-+
-+ Backport from mainline r204441
-+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal):
-+ Remove restriction against use of VSX instructions when generating
-+ code for little endian mode.
-+
-+ Backport from mainline r204440
-+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (mulv4si3): Ensure we generate vmulouh
-+ for both big and little endian.
-+ (mulv8hi3): Swap input operands for merge high and merge low
-+ instructions for little endian.
-+
-+ Backport from mainline r204439
-+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (vec_widen_umult_even_v16qi): Change
-+ define_insn to define_expand that uses even patterns for big
-+ endian and odd patterns for little endian.
-+ (vec_widen_smult_even_v16qi): Likewise.
-+ (vec_widen_umult_even_v8hi): Likewise.
-+ (vec_widen_smult_even_v8hi): Likewise.
-+ (vec_widen_umult_odd_v16qi): Likewise.
-+ (vec_widen_smult_odd_v16qi): Likewise.
-+ (vec_widen_umult_odd_v8hi): Likewise.
-+ (vec_widen_smult_odd_v8hi): Likewise.
-+ (altivec_vmuleub): New define_insn.
-+ (altivec_vmuloub): Likewise.
-+ (altivec_vmulesb): Likewise.
-+ (altivec_vmulosb): Likewise.
-+ (altivec_vmuleuh): Likewise.
-+ (altivec_vmulouh): Likewise.
-+ (altivec_vmulesh): Likewise.
-+ (altivec_vmulosh): Likewise.
-+
-+ Backport from mainline r204395
-+ 2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (vec_pack_sfix_trunc_v2df): Adjust for
-+ little endian.
-+ (vec_pack_ufix_trunc_v2df): Likewise.
-+
-+ Backport from mainline r204363
-+ 2013-11-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (vec_widen_umult_hi_v16qi): Swap
-+ arguments to merge instruction for little endian.
-+ (vec_widen_umult_lo_v16qi): Likewise.
-+ (vec_widen_smult_hi_v16qi): Likewise.
-+ (vec_widen_smult_lo_v16qi): Likewise.
-+ (vec_widen_umult_hi_v8hi): Likewise.
-+ (vec_widen_umult_lo_v8hi): Likewise.
-+ (vec_widen_smult_hi_v8hi): Likewise.
-+ (vec_widen_smult_lo_v8hi): Likewise.
-+
-+ Backport from mainline r204350
-+ 2013-11-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vsx.md (*vsx_le_perm_store_<mode> for VSX_D):
-+ Replace the define_insn_and_split with a define_insn and two
-+ define_splits, with the split after reload re-permuting the source
-+ register to its original value.
-+ (*vsx_le_perm_store_<mode> for VSX_W): Likewise.
-+ (*vsx_le_perm_store_v8hi): Likewise.
-+ (*vsx_le_perm_store_v16qi): Likewise.
-+
-+ Backport from mainline r204321
-+ 2013-11-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (vec_pack_trunc_v2df): Adjust for
-+ little endian.
-+
-+ Backport from mainline r204321
-+ 2013-11-02 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Adjust for
-+ little endian.
-+
-+ Backport from mainline r203980
-+ 2013-10-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (mulv8hi3): Adjust for little endian.
-+
-+ Backport from mainline r203930
-+ 2013-10-22 Bill Schmidt <wschmidt@vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse
-+ meaning of merge-high and merge-low masks for little endian; avoid
-+ use of vector-pack masks for little endian for mismatched modes.
-+
-+ Backport from mainline r203877
-+ 2013-10-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/altivec.md (vec_unpacku_hi_v16qi): Adjust for
-+ little endian.
-+ (vec_unpacku_hi_v8hi): Likewise.
-+ (vec_unpacku_lo_v16qi): Likewise.
-+ (vec_unpacku_lo_v8hi): Likewise.
-+
-+ Backport from mainline r203863
-+ 2013-10-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (vspltis_constant): Make sure we check
-+ all elements for both endian flavors.
-+
-+ Backport from mainline r203714
-+ 2013-10-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for
-+ endianness.
-+ (vec_unpacks_lo_v4sf): Likewise.
-+ (vec_unpacks_float_hi_v4si): Likewise.
-+ (vec_unpacks_float_lo_v4si): Likewise.
-+ (vec_unpacku_float_hi_v4si): Likewise.
-+ (vec_unpacku_float_lo_v4si): Likewise.
-+
-+ Backport from mainline r203713
-+ 2013-10-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vsx.md (vsx_concat_<mode>): Adjust output for LE.
-+ (vsx_concat_v2sf): Likewise.
-+
-+ Backport from mainline r203458
-+ 2013-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to
-+ handle vector float as well.
-+ (*vsx_le_perm_load_v4si): Likewise.
-+ (*vsx_le_perm_store_v2di): Likewise.
-+ (*vsx_le_perm_store_v4si): Likewise.
-+
-+ Backport from mainline r203457
-+ 2013-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (vec_realign_load<mode>): Generate vperm
-+ directly to circumvent subtract from splat{31} workaround.
-+ * config/rs6000/rs6000-protos.h (altivec_expand_vec_perm_le): New
-+ prototype.
-+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): New.
-+ * config/rs6000/altivec.md (define_c_enum "unspec"): Add
-+ UNSPEC_VPERM_X and UNSPEC_VPERM_UNS_X.
-+ (altivec_vperm_<mode>): Convert to define_insn_and_split to
-+ separate big and little endian logic.
-+ (*altivec_vperm_<mode>_internal): New define_insn.
-+ (altivec_vperm_<mode>_uns): Convert to define_insn_and_split to
-+ separate big and little endian logic.
-+ (*altivec_vperm_<mode>_uns_internal): New define_insn.
-+ (vec_permv16qi): Add little endian logic.
-+
-+ Backport from mainline r203247
-+ 2013-10-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const_le): New.
-+ (altivec_expand_vec_perm_const): Call it.
-+
-+ Backport from mainline r203246
-+ 2013-10-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (mov<mode>): Emit permuted move
-+ sequences for LE VSX loads and stores at expand time.
-+ * config/rs6000/rs6000-protos.h (rs6000_emit_le_vsx_move): New
-+ prototype.
-+ * config/rs6000/rs6000.c (rs6000_const_vec): New.
-+ (rs6000_gen_le_vsx_permute): New.
-+ (rs6000_gen_le_vsx_load): New.
-+ (rs6000_gen_le_vsx_store): New.
-+ (rs6000_gen_le_vsx_move): New.
-+ * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): New.
-+ (*vsx_le_perm_load_v4si): New.
-+ (*vsx_le_perm_load_v8hi): New.
-+ (*vsx_le_perm_load_v16qi): New.
-+ (*vsx_le_perm_store_v2di): New.
-+ (*vsx_le_perm_store_v4si): New.
-+ (*vsx_le_perm_store_v8hi): New.
-+ (*vsx_le_perm_store_v16qi): New.
-+ (*vsx_xxpermdi2_le_<mode>): New.
-+ (*vsx_xxpermdi4_le_<mode>): New.
-+ (*vsx_xxpermdi8_le_V8HI): New.
-+ (*vsx_xxpermdi16_le_V16QI): New.
-+ (*vsx_lxvd2x2_le_<mode>): New.
-+ (*vsx_lxvd2x4_le_<mode>): New.
-+ (*vsx_lxvd2x8_le_V8HI): New.
-+ (*vsx_lxvd2x16_le_V16QI): New.
-+ (*vsx_stxvd2x2_le_<mode>): New.
-+ (*vsx_stxvd2x4_le_<mode>): New.
-+ (*vsx_stxvd2x8_le_V8HI): New.
-+ (*vsx_stxvd2x16_le_V16QI): New.
-+
-+ Backport from mainline r201235
-+ 2013-07-24 Bill Schmidt <wschmidt@linux.ibm.com>
-+ Anton Blanchard <anton@au1.ibm.com>
-+
-+ * config/rs6000/altivec.md (altivec_vpkpx): Handle little endian.
-+ (altivec_vpks<VI_char>ss): Likewise.
-+ (altivec_vpks<VI_char>us): Likewise.
-+ (altivec_vpku<VI_char>us): Likewise.
-+ (altivec_vpku<VI_char>um): Likewise.
-+
-+ Backport from mainline r201208
-+ 2013-07-24 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
-+ Anton Blanchard <anton@au1.ibm.com>
-+
-+ * config/rs6000/vector.md (vec_realign_load_<mode>): Reorder input
-+ operands to vperm for little endian.
-+ * config/rs6000/rs6000.c (rs6000_expand_builtin): Use lvsr instead
-+ of lvsl to create the control mask for a vperm for little endian.
-+
-+ Backport from mainline r201195
-+ 2013-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+ Anton Blanchard <anton@au1.ibm.com>
-+
-+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse
-+ two operands for little-endian.
-+
-+ Backport from mainline r201193
-+ 2013-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+ Anton Blanchard <anton@au1.ibm.com>
-+
-+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Correct
-+ selection of field for vector splat in little endian mode.
-+
-+ Backport from mainline r201149
-+ 2013-07-22 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
-+ Anton Blanchard <anton@au1.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_expand_vector_init): Fix
-+ endianness when selecting field to splat.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r205123:
-+
-+ 2013-11-20 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_cannot_change_mode_class): Do not
-+ allow subregs of TDmode in FPRs of smaller size in little-endian.
-+ (rs6000_split_multireg_move): When splitting an access to TDmode
-+ in FPRs, do not use simplify_gen_subreg.
-+
-+ Backport from mainline r204927:
-+
-+ 2013-11-17 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_emit_move): Use low word of
-+ sdmode_stack_slot also in little-endian mode.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Power8 HTM Support
-+ Backport from mainline
-+ 2013-12-03 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * config/rs6000/htmintrin.h (_TEXASR_INSTRUCTION_FETCH_CONFLICT): Fix
-+ typo in macro name.
-+ (_TEXASRU_INSTRUCTION_FETCH_CONFLICT): Likewise.
-+
-+ Backport from mainline r205233.
-+ 2013-11-21 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * doc/extend.texi: Document htm builtins.
-+
-+ Backport from mainline
-+ 2013-07-17 Iain Sandoe <iain@codesourcery.com>
-+
-+ * config/rs6000/darwin.h (REGISTER_NAMES): Add HTM registers.
-+
-+ Backport from mainline
-+ 2013-07-16 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not
-+ enable extra ISA flags with TARGET_HTM.
-+
-+ 2013-07-16 Jakub Jelinek <jakub@redhat.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM
-+ registers in the comment.
-+ (DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers.
-+ (DWARF_REG_TO_UNWIND_COLUMN): Use DWARF_FRAME_REGISTERS
-+ rather than FIRST_PSEUDO_REGISTERS.
-+
-+ * config.gcc (powerpc*-*-*): Install htmintrin.h and htmxlintrin.h.
-+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add htm.md.
-+ * config/rs6000/rs6000.opt: Add -mhtm option.
-+ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_HTM.
-+ (ISA_2_7_MASKS_SERVER): Add OPTION_MASK_HTM.
-+ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
-+ __HTM__ if the HTM instructions are available.
-+ * config/rs6000/predicates.md (u3bit_cint_operand, u10bit_cint_operand)
-+ (htm_spr_reg_operand): New define_predicates.
-+ * config/rs6000/rs6000.md (define_attr "type"): Add htm.
-+ (TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO): New define_constants.
-+ Include htm.md.
-+ * config/rs6000/rs6000-builtin.def (BU_HTM_0, BU_HTM_1, BU_HTM_2)
-+ (BU_HTM_3, BU_HTM_SPR0, BU_HTM_SPR1): Add support macros for defining
-+ HTM builtin functions.
-+ * config/rs6000/rs6000.c (RS6000_BUILTIN_H): New macro.
-+ (rs6000_reg_names, alt_reg_names): Add HTM SPR register names.
-+ (rs6000_init_hard_regno_mode_ok): Add support for HTM instructions.
-+ (rs6000_builtin_mask_calculate): Likewise.
-+ (rs6000_option_override_internal): Likewise.
-+ (bdesc_htm): Add new HTM builtin support.
-+ (htm_spr_num): New function.
-+ (htm_spr_regno): Likewise.
-+ (rs6000_htm_spr_icode): Likewise.
-+ (htm_expand_builtin): Likewise.
-+ (htm_init_builtins): Likewise.
-+ (rs6000_expand_builtin): Add support for HTM builtin functions.
-+ (rs6000_init_builtins): Likewise.
-+ (rs6000_invalid_builtin, rs6000_opt_mask): Add support for -mhtm option.
-+ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for -mhtm.
-+ (TARGET_HTM, MASK_HTM): Define macros.
-+ (FIRST_PSEUDO_REGISTER): Adjust for new HTM SPR registers.
-+ (FIXED_REGISTERS): Likewise.
-+ (CALL_USED_REGISTERS): Likewise.
-+ (CALL_REALLY_USED_REGISTERS): Likewise.
-+ (REG_ALLOC_ORDER): Likewise.
-+ (enum reg_class): Likewise.
-+ (REG_CLASS_NAMES): Likewise.
-+ (REG_CLASS_CONTENTS): Likewise.
-+ (REGISTER_NAMES): Likewise.
-+ (ADDITIONAL_REGISTER_NAMES): Likewise.
-+ (RS6000_BTC_SPR, RS6000_BTC_VOID, RS6000_BTC_32BIT, RS6000_BTC_64BIT)
-+ (RS6000_BTC_MISC_MASK, RS6000_BTM_HTM): New macros.
-+ (RS6000_BTM_COMMON): Add RS6000_BTM_HTM.
-+ * config/rs6000/htm.md: New file.
-+ * config/rs6000/htmintrin.h: New file.
-+ * config/rs6000/htmxlintrin.h: New file.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Power8 Base Support
-+ Apply mainline
-+ 2013-11-23 Alan Modra <amodra@gmail.com>
-+ * config/rs6000/vsx.md (fusion peepholes): Disable when !TARGET_VSX.
-+
-+ Backport from mainline
-+ 2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/59054
-+ * config/rs6000/rs6000.md (movdi_internal32): Eliminate
-+ constraints that would allow DImode into the traditional Altivec
-+ registers, but cause undesirable code generation when loading 0 as
-+ a constant.
-+ (movdi_internal64): Likewise.
-+ (cmp<mode>_fpr): Do not use %x for CR register output.
-+ (extendsfdf2_fpr): Fix constraints when -mallow-upper-df and
-+ -mallow-upper-sf debug switches are used.
-+
-+ Backport from mainline
-+ 2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (enum rs6000_reload_reg_type): Add new
-+ fields to the reg_addr array that describes the valid addressing
-+ mode for any register, general purpose registers, floating point
-+ registers, and Altivec registers.
-+ (FIRST_RELOAD_REG_CLASS): Likewise.
-+ (LAST_RELOAD_REG_CLASS): Likewise.
-+ (struct reload_reg_map_type): Likewise.
-+ (reload_reg_map_type): Likewise.
-+ (RELOAD_REG_VALID): Likewise.
-+ (RELOAD_REG_MULTIPLE): Likewise.
-+ (RELOAD_REG_INDEXED): Likewise.
-+ (RELOAD_REG_OFFSET): Likewise.
-+ (RELOAD_REG_PRE_INCDEC): Likewise.
-+ (RELOAD_REG_PRE_MODIFY): Likewise.
-+ (reg_addr): Likewise.
-+ (mode_supports_pre_incdec_p): New helper functions to say whether
-+ a given mode supports PRE_INC, PRE_DEC, and PRE_MODIFY.
-+ (mode_supports_pre_modify_p): Likewise.
-+ (rs6000_debug_vector_unit): Rearrange the -mdebug=reg output to
-+ print the valid address mode bits for each mode.
-+ (rs6000_debug_print_mode): Likewise.
-+ (rs6000_debug_reg_global): Likewise.
-+ (rs6000_setup_reg_addr_masks): New function to set up the address
-+ mask bits for each type.
-+ (rs6000_init_hard_regno_mode_ok): Use memset to clear arrays.
-+ Call rs6000_setup_reg_addr_masks to set up the address mask bits.
-+ (rs6000_legitimate_address_p): Use mode_supports_pre_incdec_p and
-+ mode_supports_pre_modify_p to determine if PRE_INC, PRE_DEC, and
-+ PRE_MODIFY are supported.
-+ (rs6000_output_move_128bit): Change to use {src,dest}_vmx_p for altivec
-+ registers, instead of {src,dest}_av_p.
-+ (rs6000_print_options_internal): Tweak the debug output slightly.
-+
-+ Backport from mainline
-+ 2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2,
-+ ceildf2, btruncdf2, instead of vsx_* name.
-+
-+ * config/rs6000/vsx.md (vsx_add<mode>3): Change arithmetic
-+ iterators to only do V2DF and V4SF here. Move the DF code to
-+ rs6000.md where it is combined with SF mode. Replace <VSv> with
-+ just 'v' since only vector operations are handled with these insns
-+ after moving the DF support to rs6000.md.
-+ (vsx_sub<mode>3): Likewise.
-+ (vsx_mul<mode>3): Likewise.
-+ (vsx_div<mode>3): Likewise.
-+ (vsx_fre<mode>2): Likewise.
-+ (vsx_neg<mode>2): Likewise.
-+ (vsx_abs<mode>2): Likewise.
-+ (vsx_nabs<mode>2): Likewise.
-+ (vsx_smax<mode>3): Likewise.
-+ (vsx_smin<mode>3): Likewise.
-+ (vsx_sqrt<mode>2): Likewise.
-+ (vsx_rsqrte<mode>2): Likewise.
-+ (vsx_fms<mode>4): Likewise.
-+ (vsx_nfma<mode>4): Likewise.
-+ (vsx_copysign<mode>3): Likewise.
-+ (vsx_btrunc<mode>2): Likewise.
-+ (vsx_floor<mode>2): Likewise.
-+ (vsx_ceil<mode>2): Likewise.
-+ (vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md.
-+ (vsx_sminsf3): Likewise.
-+ (vsx_fmadf4): Likewise.
-+ (vsx_fmsdf4): Likewise.
-+ (vsx_nfmadf4): Likewise.
-+ (vsx_nfmsdf4): Likewise.
-+ (vsx_cmpdf_internal1): Likewise.
-+
-+ * config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it
-+ simpler to select whether a target has SPE or traditional floating
-+ point support in iterators.
-+ (TARGET_DF_SPE): Likewise.
-+ (TARGET_SF_FPR): Likewise.
-+ (TARGET_DF_FPR): Likewise.
-+ (TARGET_SF_INSN): Macros to say whether floating point support
-+ exists for a given operation for expanders.
-+ (TARGET_DF_INSN): Likewise.
-+
-+ * config/rs6000/rs6000.c (Ftrad): New mode attributes to allow
-+ combining of SF/DF mode operations, using both traditional and VSX
-+ registers.
-+ (Fvsx): Likewise.
-+ (Ff): Likewise.
-+ (Fv): Likewise.
-+ (Fs): Likewise.
-+ (Ffre): Likewise.
-+ (FFRE): Likewise.
-+ (abs<mode>2): Combine SF/DF modes using traditional floating point
-+ instructions. Add support for using the upper DF registers with
-+ VSX support, and SF registers with power8-vector support. Update
-+ expanders for operations supported by both the SPE and traditional
-+ floating point units.
-+ (abs<mode>2_fpr): Likewise.
-+ (nabs<mode>2): Likewise.
-+ (nabs<mode>2_fpr): Likewise.
-+ (neg<mode>2): Likewise.
-+ (neg<mode>2_fpr): Likewise.
-+ (add<mode>3): Likewise.
-+ (add<mode>3_fpr): Likewise.
-+ (sub<mode>3): Likewise.
-+ (sub<mode>3_fpr): Likewise.
-+ (mul<mode>3): Likewise.
-+ (mul<mode>3_fpr): Likewise.
-+ (div<mode>3): Likewise.
-+ (div<mode>3_fpr): Likewise.
-+ (sqrt<mode>3): Likewise.
-+ (sqrt<mode>3_fpr): Likewise.
-+ (fre<Fs>): Likewise.
-+ (rsqrt<mode>2): Likewise.
-+ (cmp<mode>_fpr): Likewise.
-+ (smax<mode>3): Likewise.
-+ (smin<mode>3): Likewise.
-+ (smax<mode>3_vsx): Likewise.
-+ (smin<mode>3_vsx): Likewise.
-+ (negsf2): Delete SF operations that are merged with DF.
-+ (abssf2): Likewise.
-+ (addsf3): Likewise.
-+ (subsf3): Likewise.
-+ (mulsf3): Likewise.
-+ (divsf3): Likewise.
-+ (fres): Likewise.
-+ (fmasf4_fpr): Likewise.
-+ (fmssf4_fpr): Likewise.
-+ (nfmasf4_fpr): Likewise.
-+ (nfmssf4_fpr): Likewise.
-+ (sqrtsf2): Likewise.
-+ (rsqrtsf_internal1): Likewise.
-+ (smaxsf3): Likewise.
-+ (sminsf3): Likewise.
-+ (cmpsf_internal1): Likewise.
-+ (copysign<mode>3_fcpsgn): Add VSX/power8-vector support.
-+ (negdf2): Delete DF operations that are merged with SF.
-+ (absdf2): Likewise.
-+ (nabsdf2): Likewise.
-+ (adddf3): Likewise.
-+ (subdf3): Likewise.
-+ (muldf3): Likewise.
-+ (divdf3): Likewise.
-+ (fred): Likewise.
-+ (rsqrtdf_internal1): Likewise.
-+ (fmadf4_fpr): Likewise.
-+ (fmsdf4_fpr): Likewise.
-+ (nfmadf4_fpr): Likewise.
-+ (nfmsdf4_fpr): Likewise.
-+ (sqrtdf2): Likewise.
-+ (smaxdf3): Likewise.
-+ (smindf3): Likewise.
-+ (cmpdf_internal1): Likewise.
-+ (lrint<mode>di2): Use TARGET_<MODE>_FPR macro.
-+ (btrunc<mode>2): Delete separate expander, and combine with the
-+ insn and add VSX instruction support. Use TARGET_<MODE>_FPR.
-+ (btrunc<mode>2_fpr): Likewise.
-+ (ceil<mode>2): Likewise.
-+ (ceil<mode>2_fpr): Likewise.
-+ (floor<mode>2): Likewise.
-+ (floor<mode>2_fpr): Likewise.
-+ (fma<mode>4_fpr): Combine SF and DF fused multiply/add support.
-+ Add support for using the upper registers with VSX and
-+ power8-vector. Move insns to be closer to the define_expands. On
-+ VSX systems, prefer the traditional form of FMA over the VSX
-+ version, since the traditional form allows the target not to
-+ overlap with the inputs.
-+ (fms<mode>4_fpr): Likewise.
-+ (nfma<mode>4_fpr): Likewise.
-+ (nfms<mode>4_fpr): Likewise.
-+
-+ Backport from mainline
-+ 2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
-+ DFmode, DImode, and SFmode in the upper VSX registers based on the
-+ -mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS
-+ if -mpower8-vector. Combine -mvsx-timode handling with the rest
-+ of the VSX register handling.
-+
-+ * config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters.
-+ (f32_sv): Likewise.
-+ (zero_extendsidi2_lfiwzx): Add support for loading into the
-+ Altivec registers with -mpower8-vector. Use wu/wv constraints to
-+ only do VSX memory options on Altivec registers.
-+ (extendsidi2_lfiwax): Likewise.
-+ (extendsfdf2_fpr): Likewise.
-+ (mov<mode>_hardfloat, SF/SD modes): Likewise.
-+ (mov<mode>_hardfloat32, DF/DD modes): Likewise.
-+ (mov<mode>_hardfloat64, DF/DD modes): Likewise.
-+ (movdi_internal64): Likewise.
-+
-+ Backport from mainline
-+ 2013-09-23 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_vector_reload): Delete, combine
-+ reload helper function arrays into a single array reg_addr.
-+ (reload_fpr_gpr): Likewise.
-+ (reload_gpr_vsx): Likewise.
-+ (reload_vsx_gpr): Likewise.
-+ (struct rs6000_reg_addr): Likewise.
-+ (reg_addr): Likewise.
-+ (rs6000_debug_reg_global): Change rs6000_vector_reload,
-+ reload_fpr_gpr, reload_gpr_vsx, reload_vsx_gpr uses to reg_addr.
-+ (rs6000_init_hard_regno_mode_ok): Likewise.
-+ (rs6000_secondary_reload_direct_move): Likewise.
-+ (rs6000_secondary_reload): Likewise.
-+
-+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new
-+ constraints: wu, ww, and wy. Repurpose wv constraint added during
-+ power8 changes. Put wg constraint in alphabetical order.
-+
-+ * config/rs6000/rs6000.opt (-mvsx-scalar-float): New debug switch
-+ for future work to add ISA 2.07 VSX single precision support.
-+ (-mvsx-scalar-double): Change default from -1 to 1, update
-+ documentation comment.
-+ (-mvsx-scalar-memory): Rename debug switch to -mupper-regs-df.
-+ (-mupper-regs-df): New debug switch to control whether DF values
-+ can go in the traditional Altivec registers.
-+ (-mupper-regs-sf): New debug switch to control whether SF values
-+ can go in the traditional Altivec registers.
-+
-+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print wu, ww,
-+ and wy constraints.
-+ (rs6000_init_hard_regno_mode_ok): Use ssize_t instead of int for
-+ loop variables. Rename -mvsx-scalar-memory to -mupper-regs-df.
-+ Add new constraints, wu/ww/wy. Repurpose wv constraint.
-+ (rs6000_debug_legitimate_address_p): Print if we are running
-+ before, during, or after reload.
-+ (rs6000_secondary_reload): Add a comment.
-+ (rs6000_opt_masks): Add -mupper-regs-df, -mupper-regs-sf.
-+
-+ * config/rs6000/constraints.md (wa constraint): Sort w<x>
-+ constraints. Update documentation string.
-+ (wd constraint): Likewise.
-+ (wf constraint): Likewise.
-+ (wg constraint): Likewise.
-+ (wn constraint): Likewise.
-+ (ws constraint): Likewise.
-+ (wt constraint): Likewise.
-+ (wx constraint): Likewise.
-+ (wz constraint): Likewise.
-+ (wu constraint): New constraint for ISA 2.07 SFmode scalar
-+ instructions.
-+ (ww constraint): Likewise.
-+ (wy constraint): Likewise.
-+ (wv constraint): Repurpose ISA 2.07 constraint that did not use in
-+ the previous submissions.
-+ * doc/md.texi (PowerPC and IBM RS6000): Likewise.
-+
-+ Backport from mainline
-+ 2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/58673
-+ * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Only
-+ restrict TImode addresses to single indirect registers if both
-+ -mquad-memory and -mvsx-timode are used.
-+ (rs6000_output_move_128bit): Use quad_load_store_p to determine if
-+ we should emit load/store quad. Remove using %y for quad memory
-+ addresses.
-+
-+ * config/rs6000/rs6000.md (mov<mode>_ppc64, TI/PTImode): Add
-+ constraints to allow load/store quad on machines where TImode is
-+ not allowed in VSX registers. Use 'n' instead of 'F' constraint
-+ for TImode to load integer constants.
-+
-+ Backport from mainline
-+ 2013-10-02 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/58587
-+ * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off
-+ setting -mvsx-timode by default until the underlying problem is
-+ fixed.
-+ (RS6000_CPU, power7 defaults): Likewise.
-+
-+ Backport from trunk
-+ 2013-08-16 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/58160
-+ * config/rs6000/predicates.md (fusion_gpr_mem_load): Allow the
-+ memory rtx to contain ZERO_EXTEND and SIGN_EXTEND.
-+
-+ * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Pass operands
-+ array instead of each individual operand as a separate argument.
-+ (emit_fusion_gpr_load): Likewise.
-+ (expand_fusion_gpr_load): Add new function declaration.
-+
-+ * config/rs6000/rs6000.c (fusion_gpr_load_p): Change the calling
-+ signature to have the operands passed as an array, instead of as
-+ separate arguments. Allow ZERO_EXTEND to be in the memory
-+ address, and also SIGN_EXTEND if -mpower8-fusion-sign. Do not
-+ depend on the register live/dead flags when peepholes are run.
-+ (expand_fusion_gpr_load): New function to be called from the
-+ peephole2 pass, to change the register that addis sets to be the
-+ target register.
-+ (emit_fusion_gpr_load): Change the calling signature to have the
-+ operands passed as an array, instead of as separate arguments.
-+ Allow ZERO_EXTEND to be in the memory address, and also
-+ SIGN_EXTEND if -mpower8-fusion-sign.
-+
-+ * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): Delete unused
-+ unspec enumeration.
-+ (power8 fusion peephole/peephole2): Rework the fusion peepholes to
-+ adjust the register addis loads up in the peephole2 pass. Do not
-+ depend on the register live/dead state when the peephole pass is
-+ done.
-+
-+ Backport from trunk
-+ 2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (xor<mode>3): Move 128-bit boolean
-+ expanders to rs6000.md.
-+ (ior<mode>3): Likewise.
-+ (and<mode>3): Likewise.
-+ (one_cmpl<mode>2): Likewise.
-+ (nor<mode>3): Likewise.
-+ (andc<mode>3): Likewise.
-+ (eqv<mode>3): Likewise.
-+ (nand<mode>3): Likewise.
-+ (orc<mode>3): Likewise.
-+
-+ * config/rs6000/rs6000-protos.h (rs6000_split_logical): New
-+ declaration.
-+
-+ * config/rs6000/rs6000.c (rs6000_split_logical_inner): Add support
-+ to split multi-word logical operations.
-+ (rs6000_split_logical_di): Likewise.
-+ (rs6000_split_logical): Likewise.
-+
-+ * config/rs6000/vsx.md (VSX_L2): Delete, no longer used.
-+ (vsx_and<mode>3_32bit): Move 128-bit logical insns to rs6000.md,
-+ and allow TImode operations in 32-bit.
-+ (vsx_and<mode>3_64bit): Likewise.
-+ (vsx_ior<mode>3_32bit): Likewise.
-+ (vsx_ior<mode>3_64bit): Likewise.
-+ (vsx_xor<mode>3_32bit): Likewise.
-+ (vsx_xor<mode>3_64bit): Likewise.
-+ (vsx_one_cmpl<mode>2_32bit): Likewise.
-+ (vsx_one_cmpl<mode>2_64bit): Likewise.
-+ (vsx_nor<mode>3_32bit): Likewise.
-+ (vsx_nor<mode>3_64bit): Likewise.
-+ (vsx_andc<mode>3_32bit): Likewise.
-+ (vsx_andc<mode>3_64bit): Likewise.
-+ (vsx_eqv<mode>3_32bit): Likewise.
-+ (vsx_eqv<mode>3_64bit): Likewise.
-+ (vsx_nand<mode>3_32bit): Likewise.
-+ (vsx_nand<mode>3_64bit): Likewise.
-+ (vsx_orc<mode>3_32bit): Likewise.
-+ (vsx_orc<mode>3_64bit): Likewise.
-+
-+ * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Always allow vector
-+ logical types in GPRs.
-+
-+ * config/rs6000/altivec.md (altivec_and<mode>3): Move 128-bit
-+ logical insns to rs6000.md, and allow TImode operations in
-+ 32-bit.
-+ (altivec_ior<mode>3): Likewise.
-+ (altivec_xor<mode>3): Likewise.
-+ (altivec_one_cmpl<mode>2): Likewise.
-+ (altivec_nor<mode>3): Likewise.
-+ (altivec_andc<mode>3): Likewise.
-+
-+ * config/rs6000/rs6000.md (BOOL_128): New mode iterators and mode
-+ attributes for moving the 128-bit logical operations into
-+ rs6000.md.
-+ (BOOL_REGS_OUTPUT): Likewise.
-+ (BOOL_REGS_OP1): Likewise.
-+ (BOOL_REGS_OP2): Likewise.
-+ (BOOL_REGS_UNARY): Likewise.
-+ (BOOL_REGS_AND_CR0): Likewise.
-+ (one_cmpl<mode>2): Add support for DI logical operations on
-+ 32-bit, splitting the operations to 32-bit.
-+ (anddi3): Likewise.
-+ (iordi3): Likewise.
-+ (xordi3): Likewise.
-+ (and<mode>3, 128-bit types): Rewrite 2013-06-06 logical operator
-+ changes to combine the 32/64-bit code, allow logical operations on
-+ TI mode in 32-bit, and to use similar match_operator patterns like
-+ scalar mode uses. Combine the Altivec and VSX code for logical
-+ operations, and move it here.
-+ (ior<mode>3, 128-bit types): Likewise.
-+ (xor<mode>3, 128-bit types): Likewise.
-+ (one_cmpl<mode>3, 128-bit types): Likewise.
-+ (nor<mode>3, 128-bit types): Likewise.
-+ (andc<mode>3, 128-bit types): Likewise.
-+ (eqv<mode>3, 128-bit types): Likewise.
-+ (nand<mode>3, 128-bit types): Likewise.
-+ (orc<mode>3, 128-bit types): Likewise.
-+ (and<mode>3_internal): Likewise.
-+ (bool<mode>3_internal): Likewise.
-+ (boolc<mode>3_internal1): Likewise.
-+ (boolc<mode>3_internal2): Likewise.
-+ (boolcc<mode>3_internal1): Likewise.
-+ (boolcc<mode>3_internal2): Likewise.
-+ (eqv<mode>3_internal1): Likewise.
-+ (eqv<mode>3_internal2): Likewise.
-+ (one_cmpl1<mode>3_internal): Likewise.
-+
-+ Back port from mainline:
-+ 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * lib/target-supports.exp (check_p8vector_hw_available) Add power8
-+ support.
-+ (check_effective_target_powerpc_p8vector_ok): Likewise.
-+ (is-effective-target): Likewise.
-+ (check_vect_support_and_set_flags): Likewise.
-+
-+ Backport from mainline
-+ 2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/predicates.md (fusion_gpr_addis): New predicates
-+ to support power8 load fusion.
-+ (fusion_gpr_mem_load): Likewise.
-+
-+ * config/rs6000/rs6000-modes.def (PTImode): Update a comment.
-+
-+ * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): New
-+ declarations for power8 load fusion.
-+ (emit_fusion_gpr_load): Likewise.
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): If
-+ tuning for power8, turn on fusion mode by default. Turn on sign
-+ extending fusion mode if normal fusion mode is on, and we are at
-+ -O2 or -O3.
-+ (fusion_gpr_load_p): New function, return true if we can fuse an
-+ addis instruction with a dependent load to a GPR.
-+ (emit_fusion_gpr_load): Emit the instructions for power8 load
-+ fusion to GPRs.
-+
-+ * config/rs6000/vsx.md (VSX_M2): New iterator for fusion
-+ peepholes.
-+ (VSX load fusion peepholes): New peepholes to fuse together an
-+ addi instruction with a VSX load instruction.
-+
-+ * config/rs6000/rs6000.md (GPR load fusion peepholes): New
-+ peepholes to fuse an addis instruction with a load to a GPR base
-+ register. If we are supporting sign extending fusions, convert
-+ sign extending loads to zero extending loads and add an explicit
-+ sign extension.
-+
-+ Backport from mainline
-+ 2013-07-18 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Adjust flag
-+ interaction for new Power8 flags and VSX.
-+
-+ Back port from the trunk
-+ 2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/57744
-+ * config/rs6000/rs6000.h (MODES_TIEABLE_P): Do not allow PTImode
-+ to tie with any other modes. Eliminate Altivec vector mode tests,
-+ since these are a subset of ALTIVEC or VSX vector modes. Simplify
-+ code, to return 0 if testing MODE2 for a condition, if we've
-+ already tested MODE1 for the same condition.
-+
-+ Backport from mainline
-+ 2013-06-28 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * config/rs6000/rs6000.md (define_insn ""): Fix insn type.
-+
-+ Back port from the trunk
-+ 2013-06-26 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * config/rs6000/power8.md: New.
-+ * config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor
-+ setting for power8 entry.
-+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md.
-+ * config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust
-+ test for Power4/Power5 only.
-+ (insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8
-+ support.
-+ (force_new_group): Adjust comment.
-+ * config/rs6000/rs6000.md: Include power8.md.
-+
-+ Back port from the trunk
-+ 2013-06-14 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/57615
-+ * config/rs6000/rs6000.md (mov<mode>_ppc64): Call
-+ rs6000_output_move_128bit to handle emitting quad memory
-+ operations. Set attribute length to 8 bytes.
-+
-+ Back port from the trunk
-+ 2013-06-13 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Move
-+ test for clearing quad memory on 32-bit later.
-+
-+ Back port from the trunk
-+
-+ 2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * config/rs6000/rs6000.c (emit_load_locked): Add support for
-+ power8 byte, half-word, and quad-word atomic instructions.
-+ (emit_store_conditional): Likewise.
-+ (rs6000_expand_atomic_compare_and_swap): Likewise.
-+ (rs6000_expand_atomic_op): Likewise.
-+
-+ * config/rs6000/sync.md (larx): Add new modes for power8.
-+ (stcx): Likewise.
-+ (AINT): New mode iterator to include TImode as well as normal
-+ integer modes on power8.
-+ (fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so
-+ that VSX registers are not considered. Use AINT mode iterator
-+ instead of INT1 to allow inclusion of quad word atomic operations
-+ on power8.
-+ (load_locked<mode>): Likewise.
-+ (store_conditional<mode>): Likewise.
-+ (atomic_compare_and_swap<mode>): Likewise.
-+ (atomic_exchange<mode>): Likewise.
-+ (atomic_nand<mode>): Likewise.
-+ (atomic_fetch_<fetchop_name><mode>): Likewise.
-+ (atomic_nand_fetch<mode>): Likewise.
-+ (mem_thread_fence): Use gen_loadsync_<mode> instead of enumerating
-+ each type.
-+ (ATOMIC): On power8, add QImode, HImode modes.
-+ (load_locked<QHI:mode>_si): Varients of load_locked for QI/HI
-+ modes that promote to SImode.
-+ (load_lockedti): Convert TImode arguments to PTImode, so that we
-+ get a guaranteed even/odd register pair.
-+ (load_lockedpti): Likewise.
-+ (store_conditionalti): Likewise.
-+ (store_conditionalpti): Likewise.
-+
-+ * config/rs6000/rs6000.md (QHI): New mode iterator for power8
-+ atomic load/store instructions.
-+ (HSI): Likewise.
-+
-+ Back port from the trunk
-+
-+ 2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (GPR move splitter): Do not split moves
-+ of vectors in GPRS if they are direct moves or quad word load or
-+ store moves.
-+
-+ * config/rs6000/rs6000-protos.h (rs6000_output_move_128bit): Add
-+ declaration.
-+ (direct_move_p): Likewise.
-+ (quad_load_store_p): Likewise.
-+
-+ * config/rs6000/rs6000.c (enum rs6000_reg_type): Simplify register
-+ classes into bins based on the physical register type.
-+ (reg_class_to_reg_type): Likewise.
-+ (IS_STD_REG_TYPE): Likewise.
-+ (IS_FP_VECT_REG_TYPE): Likewise.
-+ (reload_fpr_gpr): Arrays to determine what insn to use if we can
-+ use direct move instructions.
-+ (reload_gpr_vsx): Likewise.
-+ (reload_vsx_gpr): Likewise.
-+ (rs6000_init_hard_regno_mode_ok): Precalculate the register type
-+ information that is a simplification of register classes. Also
-+ precalculate direct move reload helpers.
-+ (direct_move_p): New function to return true if the operation can
-+ be done as a direct move instruciton.
-+ (quad_load_store_p): New function to return true if the operation
-+ is a quad memory operation.
-+ (rs6000_legitimize_address): If quad memory, only allow register
-+ indirect for TImode addresses.
-+ (rs6000_legitimate_address_p): Likewise.
-+ (enum reload_reg_type): Delete, replace with rs6000_reg_type.
-+ (rs6000_reload_register_type): Likewise.
-+ (register_to_reg_type): Return register type.
-+ (rs6000_secondary_reload_simple_move): New helper function for
-+ secondary reload and secondary memory needed to identify anything
-+ that is a simple move, and does not need reloading.
-+ (rs6000_secondary_reload_direct_move): New helper function for
-+ secondary reload to identify cases that can be done with several
-+ instructions via the direct move instructions.
-+ (rs6000_secondary_reload_move): New helper function for secondary
-+ reload to identify moves between register types that can be done.
-+ (rs6000_secondary_reload): Add support for quad memory operations
-+ and for direct move.
-+ (rs6000_secondary_memory_needed): Likewise.
-+ (rs6000_debug_secondary_memory_needed): Change argument names.
-+ (rs6000_output_move_128bit): New function to return the move to
-+ use for 128-bit moves, including knowing about the various
-+ limitations of quad memory operations.
-+
-+ * config/rs6000/vsx.md (vsx_mov<mode>): Add support for quad
-+ memory operations. call rs6000_output_move_128bit for the actual
-+ instruciton(s) to generate.
-+ (vsx_movti_64bit): Likewise.
-+
-+ * config/rs6000/rs6000.md (UNSPEC_P8V_FMRGOW): New unspec values.
-+ (UNSPEC_P8V_MTVSRWZ): Likewise.
-+ (UNSPEC_P8V_RELOAD_FROM_GPR): Likewise.
-+ (UNSPEC_P8V_MTVSRD): Likewise.
-+ (UNSPEC_P8V_XXPERMDI): Likewise.
-+ (UNSPEC_P8V_RELOAD_FROM_VSX): Likewise.
-+ (UNSPEC_FUSION_GPR): Likewise.
-+ (FMOVE128_GPR): New iterator for direct move.
-+ (f32_lv): New mode attribute for load/store of SFmode/SDmode
-+ values.
-+ (f32_sv): Likewise.
-+ (f32_dm): Likewise.
-+ (zero_extend<mode>di2_internal1): Add support for power8 32-bit
-+ loads and direct move instructions.
-+ (zero_extendsidi2_lfiwzx): Likewise.
-+ (extendsidi2_lfiwax): Likewise.
-+ (extendsidi2_nocell): Likewise.
-+ (floatsi<mode>2_lfiwax): Likewise.
-+ (lfiwax): Likewise.
-+ (floatunssi<mode>2_lfiwzx): Likewise.
-+ (lfiwzx): Likewise.
-+ (fix_trunc<mode>_stfiwx): Likewise.
-+ (fixuns_trunc<mode>_stfiwx): Likewise.
-+ (mov<mode>_hardfloat, 32-bit floating point): Likewise.
-+ (mov<move>_hardfloat64, 64-bit floating point): Likewise.
-+ (parity<mode>2_cmpb): Set length/type attr.
-+ (unnamed shift right patterns, mov<mode>_internal2): Change type attr
-+ for 'mr.' to fast_compare.
-+ (bpermd_<mode>): Change type attr to popcnt.
-+ (p8_fmrgow_<mode>): New insns for power8 direct move support.
-+ (p8_mtvsrwz_1): Likewise.
-+ (p8_mtvsrwz_2): Likewise.
-+ (reload_fpr_from_gpr<mode>): Likewise.
-+ (p8_mtvsrd_1): Likewise.
-+ (p8_mtvsrd_2): Likewise.
-+ (p8_xxpermdi_<mode>): Likewise.
-+ (reload_vsx_from_gpr<mode>): Likewise.
-+ (reload_vsx_from_gprsf): Likewise.
-+ (p8_mfvsrd_3_<mode>): LIkewise.
-+ (reload_gpr_from_vsx<mode>): Likewise.
-+ (reload_gpr_from_vsxsf): Likewise.
-+ (p8_mfvsrd_4_disf): Likewise.
-+ (multi-word GPR splits): Do not split direct moves or quad memory
-+ operations.
-+
-+ Backport from the trunk
-+
-+ 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
-+ Document new power8 builtins.
-+
-+ * config/rs6000/vector.md (and<mode>3): Add a clobber/scratch of a
-+ condition code register, to allow 128-bit logical operations to be
-+ done in the VSX or GPR registers.
-+ (nor<mode>3): Use the canonical form for nor.
-+ (eqv<mode>3): Add expanders for power8 xxleqv, xxlnand, xxlorc,
-+ vclz*, and vpopcnt* vector instructions.
-+ (nand<mode>3): Likewise.
-+ (orc<mode>3): Likewise.
-+ (clz<mode>2): LIkewise.
-+ (popcount<mode>2): Likewise.
-+
-+ * config/rs6000/predicates.md (int_reg_operand): Rework tests so
-+ that only the GPRs are recognized.
-+
-+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
-+ support for new power8 builtins.
-+
-+ * config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8
-+ builtin functions.
-+ (xscvdpspn): Likewise.
-+ (vclz): Likewise.
-+ (vclzb): Likewise.
-+ (vclzh): Likewise.
-+ (vclzw): Likewise.
-+ (vclzd): Likewise.
-+ (vpopcnt): Likewise.
-+ (vpopcntb): Likewise.
-+ (vpopcnth): Likewise.
-+ (vpopcntw): Likewise.
-+ (vpopcntd): Likewise.
-+ (vgbbd): Likewise.
-+ (vmrgew): Likewise.
-+ (vmrgow): Likewise.
-+ (eqv): Likewise.
-+ (eqv_v16qi3): Likewise.
-+ (eqv_v8hi3): Likewise.
-+ (eqv_v4si3): Likewise.
-+ (eqv_v2di3): Likewise.
-+ (eqv_v4sf3): Likewise.
-+ (eqv_v2df3): Likewise.
-+ (nand): Likewise.
-+ (nand_v16qi3): Likewise.
-+ (nand_v8hi3): Likewise.
-+ (nand_v4si3): Likewise.
-+ (nand_v2di3): Likewise.
-+ (nand_v4sf3): Likewise.
-+ (nand_v2df3): Likewise.
-+ (orc): Likewise.
-+ (orc_v16qi3): Likewise.
-+ (orc_v8hi3): Likewise.
-+ (orc_v4si3): Likewise.
-+ (orc_v2di3): Likewise.
-+ (orc_v4sf3): Likewise.
-+ (orc_v2df3): Likewise.
-+
-+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Only
-+ allow power8 quad mode in 64-bit.
-+ (rs6000_builtin_vectorized_function): Add support to vectorize
-+ ISA 2.07 count leading zeros, population count builtins.
-+ (rs6000_expand_vector_init): On ISA 2.07 use xscvdpspn to form
-+ V4SF vectors instead of xscvdpsp to avoid IEEE related traps.
-+ (builtin_function_type): Add vgbbd builtin function which takes an
-+ unsigned argument.
-+ (altivec_expand_vec_perm_const): Add support for new power8 merge
-+ instructions.
-+
-+ * config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types,
-+ that does not include TImdoe for use with 32-bit.
-+ (UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn
-+ instructions.
-+ (UNSPEC_VSX_CVDPSPN): Likewise.
-+ (vsx_xscvdpspn): Likewise.
-+ (vsx_xscvspdpn): Likewise.
-+ (vsx_xscvdpspn_scalar): Likewise.
-+ (vsx_xscvspdpn_directmove): Likewise.
-+ (vsx_and<mode>3): Split logical operations into 32-bit and
-+ 64-bit. Add support to do logical operations on TImode as well as
-+ VSX vector types. Allow logical operations to be done in either
-+ VSX registers or in general purpose registers in 64-bit mode. Add
-+ splitters if GPRs were used. For AND, add clobber of CCmode to
-+ allow use of ANDI on GPRs. Rewrite nor to use the canonical RTL
-+ encoding.
-+ (vsx_and<mode>3_32bit): Likewise.
-+ (vsx_and<mode>3_64bit): Likewise.
-+ (vsx_ior<mode>3): Likewise.
-+ (vsx_ior<mode>3_32bit): Likewise.
-+ (vsx_ior<mode>3_64bit): Likewise.
-+ (vsx_xor<mode>3): Likewise.
-+ (vsx_xor<mode>3_32bit): Likewise.
-+ (vsx_xor<mode>3_64bit): Likewise.
-+ (vsx_one_cmpl<mode>2): Likewise.
-+ (vsx_one_cmpl<mode>2_32bit): Likewise.
-+ (vsx_one_cmpl<mode>2_64bit): Likewise.
-+ (vsx_nor<mode>3): Likewise.
-+ (vsx_nor<mode>3_32bit): Likewise.
-+ (vsx_nor<mode>3_64bit): Likewise.
-+ (vsx_andc<mode>3): Likewise.
-+ (vsx_andc<mode>3_32bit): Likewise.
-+ (vsx_andc<mode>3_64bit): Likewise.
-+ (vsx_eqv<mode>3_32bit): Add support for power8 xxleqv, xxlnand,
-+ and xxlorc instructions.
-+ (vsx_eqv<mode>3_64bit): Likewise.
-+ (vsx_nand<mode>3_32bit): Likewise.
-+ (vsx_nand<mode>3_64bit): Likewise.
-+ (vsx_orc<mode>3_32bit): Likewise.
-+ (vsx_orc<mode>3_64bit): Likewise.
-+
-+ * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment.
-+
-+ * config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd
-+ instruction.
-+ (p8_vmrgew): Add power8 vmrgew and vmrgow instructions.
-+ (p8_vmrgow): Likewise.
-+ (altivec_and<mode>3): Add clobber of CCmode to allow AND using
-+ GPRs to be split under VSX.
-+ (p8v_clz<mode>2): Add power8 count leading zero support.
-+ (p8v_popcount<mode>2): Add power8 population count support.
-+ (p8v_vgbbd): Add power8 gather bits by bytes by doubleword
-+ support.
-+
-+ * config/rs6000/rs6000.md (eqv<mode>3): Add support for powerp eqv
-+ instruction.
-+
-+ * config/rs6000/altivec.h (vec_eqv): Add defines to export power8
-+ builtin functions.
-+ (vec_nand): Likewise.
-+ (vec_vclz): Likewise.
-+ (vec_vclzb): Likewise.
-+ (vec_vclzd): Likewise.
-+ (vec_vclzh): Likewise.
-+ (vec_vclzw): Likewise.
-+ (vec_vgbbd): Likewise.
-+ (vec_vmrgew): Likewise.
-+ (vec_vmrgow): Likewise.
-+ (vec_vpopcnt): Likewise.
-+ (vec_vpopcntb): Likewise.
-+ (vec_vpopcntd): Likewise.
-+ (vec_vpopcnth): Likewise.
-+ (vec_vpopcntw): Likewise.
-+
-+ Backport from trunk
-+
-+ 2013-05-29 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI
-+ instructions.
-+ (VEC_A): Likewise.
-+ (VEC_C): Likewise.
-+ (vrotl<mode>3): Likewise.
-+ (vashl<mode>3): Likewise.
-+ (vlshr<mode>3): Likewise.
-+ (vashr<mode>3): Likewise.
-+
-+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
-+ support for power8 V2DI builtins.
-+
-+ * config/rs6000/rs6000-builtin.def (abs_v2di): Add support for
-+ power8 V2DI builtins.
-+ (vupkhsw): Likewise.
-+ (vupklsw): Likewise.
-+ (vaddudm): Likewise.
-+ (vminsd): Likewise.
-+ (vmaxsd): Likewise.
-+ (vminud): Likewise.
-+ (vmaxud): Likewise.
-+ (vpkudum): Likewise.
-+ (vpksdss): Likewise.
-+ (vpkudus): Likewise.
-+ (vpksdus): Likewise.
-+ (vrld): Likewise.
-+ (vsld): Likewise.
-+ (vsrd): Likewise.
-+ (vsrad): Likewise.
-+ (vsubudm): Likewise.
-+ (vcmpequd): Likewise.
-+ (vcmpgtsd): Likewise.
-+ (vcmpgtud): Likewise.
-+ (vcmpequd_p): Likewise.
-+ (vcmpgtsd_p): Likewise.
-+ (vcmpgtud_p): Likewise.
-+ (vupkhsw): Likewise.
-+ (vupklsw): Likewise.
-+ (vaddudm): Likewise.
-+ (vmaxsd): Likewise.
-+ (vmaxud): Likewise.
-+ (vminsd): Likewise.
-+ (vminud): Likewise.
-+ (vpksdss): Likewise.
-+ (vpksdus): Likewise.
-+ (vpkudum): Likewise.
-+ (vpkudus): Likewise.
-+ (vrld): Likewise.
-+ (vsld): Likewise.
-+ (vsrad): Likewise.
-+ (vsrd): Likewise.
-+ (vsubudm): Likewise.
-+
-+ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add
-+ support for power8 V2DI instructions.
-+
-+ * config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for
-+ power8 V2DI instructions. Combine pack and unpack insns to use an
-+ iterator for each mode. Check whether a particular mode supports
-+ Altivec instructions instead of just checking TARGET_ALTIVEC.
-+ (UNSPEC_VPKUWUM): Likewise.
-+ (UNSPEC_VPKSHSS): Likewise.
-+ (UNSPEC_VPKSWSS): Likewise.
-+ (UNSPEC_VPKUHUS): Likewise.
-+ (UNSPEC_VPKSHUS): Likewise.
-+ (UNSPEC_VPKUWUS): Likewise.
-+ (UNSPEC_VPKSWUS): Likewise.
-+ (UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise.
-+ (UNSPEC_VPACK_SIGN_UNS_SAT): Likewise.
-+ (UNSPEC_VPACK_UNS_UNS_SAT): Likewise.
-+ (UNSPEC_VPACK_UNS_UNS_MOD): Likewise.
-+ (UNSPEC_VUPKHSB): Likewise.
-+ (UNSPEC_VUNPACK_HI_SIGN): Likewise.
-+ (UNSPEC_VUNPACK_LO_SIGN): Likewise.
-+ (UNSPEC_VUPKHSH): Likewise.
-+ (UNSPEC_VUPKLSB): Likewise.
-+ (UNSPEC_VUPKLSH): Likewise.
-+ (VI2): Likewise.
-+ (VI_char): Likewise.
-+ (VI_scalar): Likewise.
-+ (VI_unit): Likewise.
-+ (VP): Likewise.
-+ (VP_small): Likewise.
-+ (VP_small_lc): Likewise.
-+ (VU_char): Likewise.
-+ (add<mode>3): Likewise.
-+ (altivec_vaddcuw): Likewise.
-+ (altivec_vaddu<VI_char>s): Likewise.
-+ (altivec_vadds<VI_char>s): Likewise.
-+ (sub<mode>3): Likewise.
-+ (altivec_vsubcuw): Likewise.
-+ (altivec_vsubu<VI_char>s): Likewise.
-+ (altivec_vsubs<VI_char>s): Likewise.
-+ (altivec_vavgs<VI_char>): Likewise.
-+ (altivec_vcmpbfp): Likewise.
-+ (altivec_eq<mode>): Likewise.
-+ (altivec_gt<mode>): Likewise.
-+ (altivec_gtu<mode>): Likewise.
-+ (umax<mode>3): Likewise.
-+ (smax<mode>3): Likewise.
-+ (umin<mode>3): Likewise.
-+ (smin<mode>3): Likewise.
-+ (altivec_vpkuhum): Likewise.
-+ (altivec_vpkuwum): Likewise.
-+ (altivec_vpkshss): Likewise.
-+ (altivec_vpkswss): Likewise.
-+ (altivec_vpkuhus): Likewise.
-+ (altivec_vpkshus): Likewise.
-+ (altivec_vpkuwus): Likewise.
-+ (altivec_vpkswus): Likewise.
-+ (altivec_vpks<VI_char>ss): Likewise.
-+ (altivec_vpks<VI_char>us): Likewise.
-+ (altivec_vpku<VI_char>us): Likewise.
-+ (altivec_vpku<VI_char>um): Likewise.
-+ (altivec_vrl<VI_char>): Likewise.
-+ (altivec_vsl<VI_char>): Likewise.
-+ (altivec_vsr<VI_char>): Likewise.
-+ (altivec_vsra<VI_char>): Likewise.
-+ (altivec_vsldoi_<mode>): Likewise.
-+ (altivec_vupkhsb): Likewise.
-+ (altivec_vupkhs<VU_char>): Likewise.
-+ (altivec_vupkls<VU_char>): Likewise.
-+ (altivec_vupkhsh): Likewise.
-+ (altivec_vupklsb): Likewise.
-+ (altivec_vupklsh): Likewise.
-+ (altivec_vcmpequ<VI_char>_p): Likewise.
-+ (altivec_vcmpgts<VI_char>_p): Likewise.
-+ (altivec_vcmpgtu<VI_char>_p): Likewise.
-+ (abs<mode>2): Likewise.
-+ (vec_unpacks_hi_v16qi): Likewise.
-+ (vec_unpacks_hi_v8hi): Likewise.
-+ (vec_unpacks_lo_v16qi): Likewise.
-+ (vec_unpacks_hi_<VP_small_lc>): Likewise.
-+ (vec_unpacks_lo_v8hi): Likewise.
-+ (vec_unpacks_lo_<VP_small_lc>): Likewise.
-+ (vec_pack_trunc_v8h): Likewise.
-+ (vec_pack_trunc_v4si): Likewise.
-+ (vec_pack_trunc_<mode>): Likewise.
-+
-+ * config/rs6000/altivec.h (vec_vaddudm): Add defines for power8
-+ V2DI builtins.
-+ (vec_vmaxsd): Likewise.
-+ (vec_vmaxud): Likewise.
-+ (vec_vminsd): Likewise.
-+ (vec_vminud): Likewise.
-+ (vec_vpksdss): Likewise.
-+ (vec_vpksdus): Likewise.
-+ (vec_vpkudum): Likewise.
-+ (vec_vpkudus): Likewise.
-+ (vec_vrld): Likewise.
-+ (vec_vsld): Likewise.
-+ (vec_vsrad): Likewise.
-+ (vec_vsrd): Likewise.
-+ (vec_vsubudm): Likewise.
-+ (vec_vupkhsw): Likewise.
-+ (vec_vupklsw): Likewise.
-+
-+ 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add
-+ documentation for the power8 crypto builtins.
-+
-+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add crypto.md.
-+
-+ * config/rs6000/rs6000-builtin.def (BU_P8V_AV_1): Add support
-+ macros for defining power8 builtin functions.
-+ (BU_P8V_AV_2): Likewise.
-+ (BU_P8V_AV_P): Likewise.
-+ (BU_P8V_VSX_1): Likewise.
-+ (BU_P8V_OVERLOAD_1): Likewise.
-+ (BU_P8V_OVERLOAD_2): Likewise.
-+ (BU_CRYPTO_1): Likewise.
-+ (BU_CRYPTO_2): Likewise.
-+ (BU_CRYPTO_3): Likewise.
-+ (BU_CRYPTO_OVERLOAD_1): Likewise.
-+ (BU_CRYPTO_OVERLOAD_2): Likewise.
-+ (XSCVSPDP): Fix typo, point to the correct instruction.
-+ (VCIPHER): Add power8 crypto builtins.
-+ (VCIPHERLAST): Likewise.
-+ (VNCIPHER): Likewise.
-+ (VNCIPHERLAST): Likewise.
-+ (VPMSUMB): Likewise.
-+ (VPMSUMH): Likewise.
-+ (VPMSUMW): Likewise.
-+ (VPERMXOR_V2DI): Likewise.
-+ (VPERMXOR_V4SI: Likewise.
-+ (VPERMXOR_V8HI: Likewise.
-+ (VPERMXOR_V16QI: Likewise.
-+ (VSHASIGMAW): Likewise.
-+ (VSHASIGMAD): Likewise.
-+ (VPMSUM): Likewise.
-+ (VPERMXOR): Likewise.
-+ (VSHASIGMA): Likewise.
-+
-+ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
-+ __CRYPTO__ if the crypto instructions are available.
-+ (altivec_overloaded_builtins): Add support for overloaded power8
-+ builtins.
-+
-+ * config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add
-+ support for power8 crypto builtins.
-+ (builtin_function_type): Likewise.
-+ (altivec_init_builtins): Add support for builtins that take vector
-+ long long (V2DI) arguments.
-+
-+ * config/rs6000/crypto.md: New file, define power8 crypto
-+ instructions.
-+
-+ 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * doc/invoke.texi (Option Summary): Add power8 options.
-+ (RS/6000 and PowerPC Options): Likewise.
-+
-+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use
-+ constraints.md instead of rs6000.h. Reorder w* constraints. Add
-+ wm, wn, wr documentation.
-+
-+ * gcc/config/rs6000/constraints.md (wm): New constraint for VSX
-+ registers if direct move instructions are enabled.
-+ (wn): New constraint for no registers.
-+ (wq): New constraint for quad word even GPR registers.
-+ (wr): New constraint if 64-bit instructions are enabled.
-+ (wv): New constraint if power8 vector instructions are enabled.
-+ (wQ): New constraint for quad word memory locations.
-+
-+ * gcc/config/rs6000/predicates.md (const_0_to_15_operand): New
-+ constraint for 0..15 for crypto instructions.
-+ (gpc_reg_operand): If VSX allow registers in VSX registers as well
-+ as GPR and floating point registers.
-+ (int_reg_operand): New predicate to match only GPR registers.
-+ (base_reg_operand): New predicate to match base registers.
-+ (quad_int_reg_operand): New predicate to match even GPR registers
-+ for quad memory operations.
-+ (vsx_reg_or_cint_operand): New predicate to allow vector logical
-+ operations in both GPR and VSX registers.
-+ (quad_memory_operand): New predicate for quad memory operations.
-+ (reg_or_indexed_operand): New predicate for direct move support.
-+
-+ * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED):
-+ Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS.
-+ (ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8).
-+ (POWERPC_MASKS): Add power8 options.
-+ (power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the
-+ various options.
-+
-+ * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):
-+ Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8.
-+
-+ * gcc/config/rs6000/rs6000.opt (-mvsx-timode): Add documentation.
-+ (-mpower8-fusion): New power8 options.
-+ (-mpower8-fusion-sign): Likewise.
-+ (-mpower8-vector): Likewise.
-+ (-mcrypto): Likewise.
-+ (-mdirect-move): Likewise.
-+ (-mquad-memory): Likewise.
-+
-+ * gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for
-+ power8.
-+ (rs6000_hard_regno_mode_ok): Make PTImode only match even GPR
-+ registers.
-+ (rs6000_debug_reg_print): Print the base register class if
-+ -mdebug=reg.
-+ (rs6000_debug_vector_unit): Add p8_vector.
-+ (rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint
-+ definitions. Also print fusion state.
-+ (rs6000_init_hard_regno_mode_ok): Set up power8 constraints.
-+ (rs6000_builtin_mask_calculate): Add power8 builtin support.
-+ (rs6000_option_override_internal): Add support for power8.
-+ (rs6000_common_init_builtins): Add debugging for skipped builtins
-+ if -mdebug=builtin.
-+ (rs6000_adjust_cost): Add power8 support.
-+ (rs6000_issue_rate): Likewise.
-+ (insn_must_be_first_in_group): Likewise.
-+ (insn_must_be_last_in_group): Likewise.
-+ (force_new_group): Likewise.
-+ (rs6000_register_move_cost): Likewise.
-+ (rs6000_opt_masks): Likewise.
-+
-+ * config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a
-+ power8 capable assembler, default to power7 options.
-+ (TARGET_DIRECT_MOVE): Likewise.
-+ (TARGET_CRYPTO): Likewise.
-+ (TARGET_P8_VECTOR): Likewise.
-+ (VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support.
-+ (VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise.
-+ (VECTOR_MEM_P8_VECTOR_P): Likewise.
-+ (VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise.
-+ (VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise.
-+ (TARGET_XSCVDPSPN): Likewise.
-+ (TARGET_XSCVSPDPN): Likewsie.
-+ (TARGET_SYNC_HI_QI): Likewise.
-+ (TARGET_SYNC_TI): Likewise.
-+ (MASK_CRYPTO): Likewise.
-+ (MASK_DIRECT_MOVE): Likewise.
-+ (MASK_P8_FUSION): Likewise.
-+ (MASK_P8_VECTOR): Likewise.
-+ (REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the
-+ TFmode temporary used by some of the direct move instructions to
-+ get two FP temporary registers does not force creation of a stack
-+ frame.
-+ (VLOGICAL_REGNO_P): Allow vector logical operations in GPRs.
-+ (MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so
-+ that any VSX registers are tieable, even if they are also an
-+ Altivec vector mode.
-+ (r6000_reg_class_enum): Add wm, wr, wv constraints.
-+ (RS6000_BTM_P8_VECTOR): Power8 builtin support.
-+ (RS6000_BTM_CRYPTO): Likewise.
-+ (RS6000_BTM_COMMON): Likewise.
-+
-+ * config/rs6000/rs6000.md (cpu attribute): Add power8.
-+ * config/rs6000/rs6000-opts.h (PROCESSOR_POWER8): Likewise.
-+ (enum rs6000_vector): Add power8 vector support.
-+
-+
-+ Backport from mainline
-+ 2013-03-20 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * config/rs6000/predicates.md (indexed_address, update_address_mem
-+ update_indexed_address_mem): New predicates.
-+ * config/rs6000/vsx.md (vsx_extract_<mode>_zero): Set correct "type"
-+ attribute for load/store instructions.
-+ * config/rs6000/dfp.md (movsd_store): Likewise.
-+ (movsd_load): Likewise.
-+ * config/rs6000/rs6000.md (zero_extend<mode>di2_internal1): Likewise.
-+ (unnamed HI->DI extend define_insn): Likewise.
-+ (unnamed SI->DI extend define_insn): Likewise.
-+ (unnamed QI->SI extend define_insn): Likewise.
-+ (unnamed QI->HI extend define_insn): Likewise.
-+ (unnamed HI->SI extend define_insn): Likewise.
-+ (unnamed HI->SI extend define_insn): Likewise.
-+ (extendsfdf2_fpr): Likewise.
-+ (movsi_internal1): Likewise.
-+ (movsi_internal1_single): Likewise.
-+ (movhi_internal): Likewise.
-+ (movqi_internal): Likewise.
-+ (movcc_internal1): Correct mnemonic for stw insn. Set correct "type"
-+ attribute for load/store instructions.
-+ (mov<mode>_hardfloat): Set correct "type" attribute for load/store
-+ instructions.
-+ (mov<mode>_softfloat): Likewise.
-+ (mov<mode>_hardfloat32): Likewise.
-+ (mov<mode>_hardfloat64): Likewise.
-+ (mov<mode>_softfloat64): Likewise.
-+ (movdi_internal32): Likewise.
-+ (movdi_internal64): Likewise.
-+ (probe_stack_<mode>): Likewise.
-+
-+ Backport from mainline
-+ 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary
-+ floating point, and decimal floating point to reload iterator.
-+
-+ * config/rs6000/constraints.md (wl constraint): New constraints to
-+ return FLOAT_REGS if certain options are used to reduce the number
-+ of separate patterns that exist in the file.
-+ (wx constraint): Likewise.
-+ (wz constraint): Likewise.
-+
-+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-+ -mdebug=reg, print wg, wl, wx, and wz constraints.
-+ (rs6000_init_hard_regno_mode_ok): Initialize new constraints.
-+ Initialize the reload functions for 64-bit binary/decimal floating
-+ point types.
-+ (reg_offset_addressing_ok_p): If we are on a power7 or later, use
-+ LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
-+ create the buffer on the stack to overcome not having a 32-bit
-+ load and store.
-+ (rs6000_emit_move): Likewise.
-+ (rs6000_secondary_memory_needed_rtx): Likewise.
-+ (rs6000_alloc_sdmode_stack_slot): Likewise.
-+ (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
-+ via xxlxor, just like DFmode 0.0.
-+
-+ * config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro)
-+ (define as 1 if we are running on a power7 or newer.
-+ (enum r6000_reg_class_enum): Add new constraints.
-+
-+ * config/rs6000/dfp.md (movsd): Delete, combine with binary
-+ floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
-+ with other moves by using conditional constraits (wg). Use LFIWZX
-+ and STFIWX for loading SDmode on power7. Use xxlxor to create
-+ 0.0f.
-+ (movsd splitter): Likewise.
-+ (movsd_hardfloat): Likewise.
-+ (movsd_softfloat): Likewise.
-+
-+ * config/rs6000/rs6000.md (FMOVE32): New iterators to combine
-+ binary and decimal floating point moves.
-+ (fmove_ok): New attributes to combine binary and decimal floating
-+ point moves, and to combine power6x (mfpgpr) moves along normal
-+ floating moves.
-+ (real_value_to_target): Likewise.
-+ (f32_lr): Likewise.
-+ (f32_lm): Likewise.
-+ (f32_li): Likewise.
-+ (f32_sr): Likewise.
-+ (f32_sm): Likewise.
-+ (f32_si): Likewise.
-+ (movsf): Combine binary and decimal floating point moves. Combine
-+ power6x (mfpgpr) moves with other moves by using conditional
-+ constraits (wg). Use LFIWZX and STFIWX for loading SDmode on
-+ power7.
-+ (mov<mode> for SFmode/SDmode); Likewise.
-+ (SFmode/SDmode splitters): Likewise.
-+ (movsf_hardfloat): Likewise.
-+ (mov<mode>_hardfloat for SFmode/SDmode): Likewise.
-+ (movsf_softfloat): Likewise.
-+ (mov<mode>_softfloat for SFmode/SDmode): Likewise.
-+
-+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl)
-+ (wx and wz constraints.
-+
-+ * config/rs6000/constraints.md (wg constraint): New constraint to
-+ return FLOAT_REGS if -mmfpgpr (power6x) was used.
-+
-+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg
-+ constraint.
-+
-+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-+ -mdebug=reg, print wg, wl, wx, and wz constraints.
-+ (rs6000_init_hard_regno_mode_ok): Initialize new constraints.
-+ Initialize the reload functions for 64-bit binary/decimal floating
-+ point types.
-+ (reg_offset_addressing_ok_p): If we are on a power7 or later, use
-+ LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
-+ create the buffer on the stack to overcome not having a 32-bit
-+ load and store.
-+ (rs6000_emit_move): Likewise.
-+ (rs6000_secondary_memory_needed_rtx): Likewise.
-+ (rs6000_alloc_sdmode_stack_slot): Likewise.
-+ (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
-+ via xxlxor, just like DFmode 0.0.
-+
-+
-+ * config/rs6000/dfp.md (movdd): Delete, combine with binary
-+ floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
-+ with other moves by using conditional constraits (wg). Use LFIWZX
-+ and STFIWX for loading SDmode on power7.
-+ (movdd splitters): Likewise.
-+ (movdd_hardfloat32): Likewise.
-+ (movdd_softfloat32): Likewise.
-+ (movdd_hardfloat64_mfpgpr): Likewise.
-+ (movdd_hardfloat64): Likewise.
-+ (movdd_softfloat64): Likewise.
-+
-+ * config/rs6000/rs6000.md (FMOVE64): New iterators to combine
-+ 64-bit binary and decimal floating point moves.
-+ (FMOVE64X): Likewise.
-+ (movdf): Combine 64-bit binary and decimal floating point moves.
-+ Combine power6x (mfpgpr) moves with other moves by using
-+ conditional constraits (wg).
-+ (mov<mode> for DFmode/DDmode): Likewise.
-+ (DFmode/DDmode splitters): Likewise.
-+ (movdf_hardfloat32): Likewise.
-+ (mov<mode>_hardfloat32 for DFmode/DDmode): Likewise.
-+ (movdf_softfloat32): Likewise.
-+ (movdf_hardfloat64_mfpgpr): Likewise.
-+ (movdf_hardfloat64): Likewise.
-+ (mov<mode>_hardfloat64 for DFmode/DDmode): Likewise.
-+ (movdf_softfloat64): Likewise.
-+ (mov<mode>_softfloat64 for DFmode/DDmode): Likewise.
-+ (reload_<mode>_load): Move to later in the file so they aren't in
-+ the middle of the floating point move insns.
-+ (reload_<mode>_store): Likewise.
-+
-+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg
-+ constraint.
-+
-+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg
-+ constraint if -mdebug=reg.
-+ (rs6000_initi_hard_regno_mode_ok): Enable wg constraint if
-+ -mfpgpr. Enable using dd reload support if needed.
-+
-+ * config/rs6000/dfp.md (movtd): Delete, combine with 128-bit
-+ binary and decimal floating point moves in rs6000.md.
-+ (movtd_internal): Likewise.
-+
-+ * config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and
-+ decimal floating point moves.
-+ (movtf): Likewise.
-+ (movtf_internal): Likewise.
-+ (mov<mode>_internal, TDmode/TFmode): Likewise.
-+ (movtf_softfloat): Likewise.
-+ (mov<mode>_softfloat, TDmode/TFmode): Likewise.
-+
-+ * config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with
-+ movdi_internal64, using wg constraint for move direct operations.
-+ (movdi_internal64): Likewise.
-+
-+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print
-+ MODES_TIEABLE_P for selected modes. Print the numerical value of
-+ the various virtual registers. Use GPR/FPR first/last values)
-+ (instead of hard coding the register numbers. Print which modes
-+ have reload functions registered.
-+ (rs6000_option_override_internal): If -mdebug=reg, trace the
-+ options settings before/after setting cpu, target and subtarget
-+ settings.
-+ (rs6000_secondary_reload_trace): Improve the RTL dump for
-+ -mdebug=addr and for secondary reload failures in
-+ rs6000_secondary_reload_inner.
-+ (rs6000_secondary_reload_fail): Likewise.
-+ (rs6000_secondary_reload_inner): Likewise.
-+
-+ * config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience
-+ macros for first/last GPR and FPR registers.
-+ (LAST_GPR_REGNO): Likewise.
-+ (FIRST_FPR_REGNO): Likewise.
-+ (LAST_FPR_REGNO): Likewise.
-+
-+ * config/rs6000/vector.md (mul<mode>3): Use the combined macro
-+ VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to
-+ VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P.
-+ (vcond<mode><mode>): Likewise.
-+ (vcondu<mode><mode>): Likewise.
-+ (vector_gtu<mode>): Likewise.
-+ (vector_gte<mode>): Likewise.
-+ (xor<mode>3): Don't allow logical operations on TImode in 32-bit
-+ to prevent the compiler from converting DImode operations to
-+ TImode.
-+ (ior<mode>3): Likewise.
-+ (and<mode>3): Likewise.
-+ (one_cmpl<mode>2): Likewise.
-+ (nor<mode>3): Likewise.
-+ (andc<mode>3): Likewise.
-+
-+ * config/rs6000/constraints.md (wt constraint): New constraint
-+ that returns VSX_REGS if TImode is allowed in VSX registers.
-+
-+ * config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy
-+ constant under VSX.
-+
-+ * config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is
-+ similar to TImode, but it is restricted to being in the GPRs.
-+
-+ * config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow
-+ TImode to occupy a single VSX register.
-+
-+ * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to
-+ -mvsx-timode for power7/power8.
-+ (power7 cpu): Likewise.
-+ (power8 cpu): Likewise.
-+
-+ * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make
-+ sure that TFmode/TDmode take up two registers if they are ever
-+ allowed in the upper VSX registers.
-+ (rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX
-+ registers.
-+ (rs6000_init_hard_regno_mode_ok): Likewise.
-+ (rs6000_debug_reg_global): Add debugging for PTImode and wt
-+ constraint. Print if LRA is turned on.
-+ (rs6000_option_override_internal): Give an error if -mvsx-timode
-+ and VSX is not enabled.
-+ (invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If
-+ -mvsx-timode, restrict TImode to reg+reg addressing, and PTImode
-+ to reg+offset addressing. Use PTImode when checking offset
-+ addresses for validity.
-+ (reg_offset_addressing_ok_p): Likewise.
-+ (rs6000_legitimate_offset_address_p): Likewise.
-+ (rs6000_legitimize_address): Likewise.
-+ (rs6000_legitimize_reload_address): Likewise.
-+ (rs6000_legitimate_address_p): Likewise.
-+ (rs6000_eliminate_indexed_memrefs): Likewise.
-+ (rs6000_emit_move): Likewise.
-+ (rs6000_secondary_reload): Likewise.
-+ (rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit
-+ reloads to fpr registers to continue to use reg+offset addressing)
-+ (but 64-bit reloads to altivec registers need reg+reg addressing.
-+ Drop test for PRE_MODIFY, since VSX loads/stores no longer support
-+ it. Treat LO_SUM like a PLUS operation.
-+ (rs6000_secondary_reload_class): If type is 64-bit, prefer to use
-+ FLOAT_REGS instead of VSX_RGS to allow use of reg+offset
-+ addressing.
-+ (rs6000_cannot_change_mode_class): Do not allow TImode in VSX
-+ registers to share a register with a smaller sized type, since VSX
-+ puts scalars in the upper 64-bits.
-+ (print_operand): Add support for PTImode.
-+ (rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of
-+ VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX
-+ registers, but don't have arithmetic support.
-+ (rs6000_memory_move_cost): Add test for VSX.
-+ (rs6000_opt_masks): Add -mvsx-timode.
-+
-+ * config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves
-+ for TImode.
-+ (VSs): Likewise.
-+ (VSr): Use wt constraint for TImode.
-+ (VSv): Drop TImode support.
-+ (vsx_movti): Delete, replace with versions for 32-bit and 64-bit.
-+ (vsx_movti_64bit): Likewise.
-+ (vsx_movti_32bit): Likewise.
-+ (vec_store_<mode>): Use VSX iterator instead of vector iterator.
-+ (vsx_and<mode>3): Delete use of '?' constraint on inputs, just put
-+ one '?' on the appropriate output constraint. Do not allow TImode
-+ logical operations on 32-bit systems.
-+ (vsx_ior<mode>3): Likewise.
-+ (vsx_xor<mode>3): Likewise.
-+ (vsx_one_cmpl<mode>2): Likewise.
-+ (vsx_nor<mode>3): Likewise.
-+ (vsx_andc<mode>3): Likewise.
-+ (vsx_concat_<mode>): Likewise.
-+ (vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes.
-+
-+ * config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from
-+ OPTION_MASK_VSX_TIMODE.
-+ (enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
-+ (STACK_SAVEAREA_MODE): Use PTImode instead of TImode.
-+
-+ * config/rs6000/rs6000.md (INT mode attribute): Add PTImode.
-+ (TI2 iterator): New iterator for TImode, PTImode.
-+ (wd mode attribute): Add values for vector types.
-+ (movti_string): Replace TI move operations with operations for
-+ TImode and PTImode. Add support for TImode being allowed in VSX
-+ registers.
-+ (mov<mode>_string, TImode/PTImode): Likewise.
-+ (movti_ppc64): Likewise.
-+ (mov<mode>_ppc64, TImode/PTImode): Likewise.
-+ (TI mode splitters): Likewise.
-+
-+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt
-+ constraint.
-+
-+2014-04-04 Richard Biener <rguenther@suse.de>
-+
-+ * tree-ssanames.c (make_ssa_name_fn): Fix assert.
-+
-+2014-04-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ * config/s390/s390.c (s390_expand_insv): Use GET_MODE_BITSIZE.
-+
-+2014-04-01 Richard Biener <rguenther@suse.de>
-+
-+ * gimple.h (struct gimple_statement_base): Align subcode to
-+ 16 bits.
-+
-+2014-04-01 Sebastian Huber <sebastian.huber@embedded-brains.de>
-+
-+ * doc/invoke.texi (mapp-regs): Clarify.
-+
-+2014-03-31 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR rtl-optimization/60700
-+ Backport from mainline
-+ 2013-07-30 Zhenqiang Chen <zhenqiang.chen@linaro.org>
-+
-+ PR rtl-optimization/57637
-+ * function.c (move_insn_for_shrink_wrap): Also check the
-+ GEN set of the LIVE problem for the liveness analysis
-+ if it exists, otherwise give up.
-+
-+2014-03-30 Kaz Kojima <kkojima@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2014-03-19 Kaz Kojima <kkojima@gcc.gnu.org>
-+
-+ PR target/60039
-+ * config/sh/sh.md (udivsi3_i1): Clobber R1 register.
-+
-+2014-03-26 Martin Jambor <mjambor@suse.cz>
-+
-+ PR ipa/60419
-+ * ipa.c (symtab_remove_unreachable_nodes): Clear thunk and
-+ alias flags of nodes in the border.
-+
-+2014-03-26 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR rtl-optimization/60452
-+ * rtlanal.c (rtx_addr_can_trap_p_1): Fix head comment.
-+ <case REG>: Return 1 for invalid offsets from the frame pointer.
-+
-+2014-03-24 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60429
-+ * tree-ssa-structalias.c (get_constraint_for_ptr_offset): Remove
-+ duplicated line.
-+
-+2014-03-23 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR rtl-optimization/60601
-+ * bb-reorder.c (fix_up_fall_thru_edges): Test EDGE_FALLTHRU everywhere.
-+
-+ * gcc.c (eval_spec_function): Initialize save_growing_value.
-+
-+2014-03-20 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/60568
-+ * config/i386/i386.c (x86_output_mi_thunk): Surround UNSPEC_GOT
-+ into CONST, put pic register as first operand of PLUS. Use
-+ gen_const_mem for both 32-bit and 64-bit PIC got loads.
-+
-+2014-03-20 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * config/sparc/sparc.c (sparc_do_work_around_errata): Implement work
-+ around for store forwarding issue in the FPU on the UT699.
-+ * config/sparc/sparc.md (in_branch_delay): Return false for single FP
-+ loads and operations if -mfix-ut699 is specified.
-+ (divtf3_hq): Tweak attribute.
-+ (sqrttf2_hq): Likewise.
-+
-+2014-03-18 Kai Tietz <ktietz@redhat.com>
-+
-+ PR rtl-optimization/56356
-+ * sdbout.c (sdbout_parms): Verify that parms'
-+ incoming argument is valid.
-+ (sdbout_reg_parms): Likewise.
-+
-+2014-03-18 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * config/sparc/sparc.c (sparc_do_work_around_errata): Speed up and use
-+ proper constant for the store mode.
-+
-+2014-03-17 Mikael Pettersson <mikpelinux@gmail.com>
-+ Committed by Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline:
-+
-+ 2013-06-20 Joern Rennecke <joern.rennecke@embecosm.com>
-+
-+ PR rtl-optimization/57425
-+ PR rtl-optimization/57569
-+ * alias.c (write_dependence_p): Remove parameters mem_mode and
-+ canon_mem_addr. Add parameters x_mode, x_addr and x_canonicalized.
-+ Changed all callers.
-+ (canon_anti_dependence): Get comments and semantics in sync.
-+ Add parameter mem_canonicalized. Changed all callers.
-+ * rtl.h (canon_anti_dependence): Update prototype.
-+
-+ 2013-06-16 Joern Rennecke <joern.rennecke@embecosm.com>
-+
-+ PR rtl-optimization/57425
-+ PR rtl-optimization/57569
-+ * alias.c (write_dependence_p): Add new parameters mem_mode,
-+ canon_mem_addr and mem_canonicalized. Change type of writep to bool.
-+ Changed all callers.
-+ (canon_anti_dependence): New function.
-+ * cse.c (check_dependence): Use canon_anti_dependence.
-+ * cselib.c (cselib_invalidate_mem): Likewise.
-+ * rtl.h (canon_anti_dependence): Declare.
-+
-+2014-03-17 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-03-11 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60429
-+ PR tree-optimization/60485
-+ * tree-ssa-structalias.c (set_union_with_increment): Properly
-+ take into account all fields that overlap the shifted vars.
-+ (do_sd_constraint): Likewise.
-+ (do_ds_constraint): Likewise.
-+ (get_constraint_for_ptr_offset): Likewise.
-+
-+2014-03-15 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * config/sparc/sparc-protos.h (tls_call_delay): Delete.
-+ (eligible_for_call_delay): New prototype.
-+ * config/sparc/sparc.c (tls_call_delay): Rename into...
-+ (eligible_for_call_delay): ...this. Return false if the instruction
-+ cannot be put in the delay slot of a branch.
-+ (eligible_for_restore_insn): Simplify.
-+ (eligible_for_return_delay): Return false if the instruction cannot be
-+ put in the delay slot of a branch and simplify.
-+ (eligible_for_sibcall_delay): Return false if the instruction cannot be
-+ put in the delay slot of a branch.
-+ * config/sparc/sparc.md (fix_ut699): New attribute.
-+ (tls_call_delay): Delete.
-+ (in_call_delay): Reimplement.
-+ (eligible_for_sibcall_delay): Rename into...
-+ (in_sibcall_delay): ...this.
-+ (eligible_for_return_delay): Rename into...
-+ (in_return_delay): ...this.
-+ (in_branch_delay): Reimplement.
-+ (in_uncond_branch_delay): Delete.
-+ (in_annul_branch_delay): Delete.
-+
-+2014-03-14 Georg-Johann Lay <avr@gjlay.de>
-+
-+ Backport from 2014-03-14 trunk r208562.
-+
-+ PR target/59396
-+ * config/avr/avr.c (avr_set_current_function): Pass function name
-+ through default_strip_name_encoding before sanity checking instead
-+ of skipping the first char of the assembler name.
-+
-+2014-03-13 Georg-Johann Lay <avr@gjlay.de>
-+
-+ Backport from 2014-03-13 trunk r208532.
-+
-+ PR target/60486
-+ * config/avr/avr.c (avr_out_plus): Swap cc_plus and cc_minus in
-+ calls of avr_out_plus_1.
-+
-+2014-03-13 Joey Ye <joey.ye@arm.com>
-+
-+ Backport from mainline
-+ 2014-03-12 Thomas Preud'homme <thomas.preudhomme@arm.com>
-+
-+ PR tree-optimization/60454
-+ * tree-ssa-math-opts.c (find_bswap_1): Fix bswap detection.
-+
-+2014-03-06 Matthias Klose <doko@ubuntu.com>
-+
-+ * Makefile.in (s-mlib): Only pass MULTIARCH_DIRNAME if
-+ MULTILIB_OSDIRNAMES is not defined.
-+
-+2014-03-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/60276
-+ * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Avoid
-+ a -Wsign-compare warning.
-+
-+ * Makefile.in (tree-ssa-uninit.o): Depend on $(PARAMS_H).
-+
-+ Backport from mainline
-+ 2014-02-21 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/56490
-+ * params.def (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS): New param.
-+ * tree-ssa-uninit.c: Include params.h.
-+ (compute_control_dep_chain): Add num_calls argument, return false
-+ if it exceed PARAM_UNINIT_CONTROL_DEP_ATTEMPTS param, pass
-+ num_calls to recursive call.
-+ (find_predicates): Change dep_chain into normal array, add num_calls
-+ variable and adjust compute_control_dep_chain caller.
-+ (find_def_preds): Likewise.
-+
-+ 2014-02-13 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/43546
-+ * expr.c (compress_float_constant): If x is a hard register,
-+ extend into a pseudo and then move to x.
-+
-+ 2014-02-11 Richard Henderson <rth@redhat.com>
-+ Jakub Jelinek <jakub@redhat.com>
-+
-+ PR debug/59776
-+ * tree-sra.c (load_assign_lhs_subreplacements): Add VIEW_CONVERT_EXPR
-+ around drhs if type conversion to lacc->type is not useless.
-+
-+ 2014-02-08 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR ipa/60026
-+ * ipa-cp.c (determine_versionability): Fail at -O0
-+ or __attribute__((optimize (0))) or -fno-ipa-cp functions.
-+ * tree-sra.c (ipa_sra_preliminary_function_checks): Similarly.
-+
-+ 2014-02-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/60062
-+ * tree.h (opts_for_fn): New inline function.
-+ (opt_for_fn): Define.
-+ * config/i386/i386.c (ix86_function_regparm): Use
-+ opt_for_fn (decl, optimize) instead of optimize.
-+
-+ 2014-02-05 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/57499
-+ * tree-eh.c (cleanup_empty_eh): Bail out on totally empty
-+ bb with no successors.
-+
-+2014-03-04 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60382
-+ * tree-vect-loop.c (vect_is_simple_reduction_1): Do not consider
-+ dead PHIs a reduction.
-+
-+2014-02-25 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-02-21 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60276
-+ * tree-vectorizer.h (struct _stmt_vec_info): Add min_neg_dist field.
-+ (STMT_VINFO_MIN_NEG_DIST): New macro.
-+ * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Record
-+ STMT_VINFO_MIN_NEG_DIST.
-+ * tree-vect-stmts.c (vectorizable_load): Verify if assumptions
-+ made for negative dependence distances still hold.
-+
-+2014-02-25 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-02-21 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60291
-+ * tree-ssa-live.c (mark_all_vars_used_1): Do not walk
-+ DECL_INITIAL for globals not in the current function context.
-+
-+ 2014-02-20 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60221
-+ * tree-eh.c (execute_cleanup_eh_1): Also cleanup empty EH
-+ regions at -O0.
-+
-+ 2014-02-14 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60183
-+ * tree-ssa-phiprop.c (propagate_with_phi): Avoid speculating
-+ loads.
-+ (tree_ssa_phiprop): Calculate and free post-dominators.
-+
-+2014-02-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-+
-+ PR target/55426
-+ * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit
-+ conversions.
-+
-+2014-02-24 John David Anglin <danglin@gcc.gnu.org>
-+
-+ * config/pa/pa.c (pa_output_move_double): Don't valididate when
-+ adjusting offsetable addresses.
-+
-+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ * config/microblaze/microblaze.md: Correct ashrsi_reg / lshrsi_reg names
-+
-+2014-02-23 Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-+
-+ * config/microblaze/microblaze.h: Remove SECONDARY_MEMORY_NEEDED
-+ definition.
-+
-+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ * /config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk
-+ and define TARGET_ASM_OUTPUT_MI_THUNK and
-+ TARGET_ASM_CAN_OUTPUT_MI_THUNK.
-+
-+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ * config/microblaze/predicates.md: Add cmp_op predicate.
-+ * config/microblaze/microblaze.md: Add branch_compare instruction
-+ which uses cmp_op predicate and emits cmp insn before branch.
-+ * config/microblaze/microblaze.c (microblaze_emit_compare): Rename
-+ to microblaze_expand_conditional_branch and consolidate logic.
-+ (microblaze_expand_conditional_branch): emit branch_compare
-+ insn instead of handling cmp op separate from branch insn.
-+
-+2014-02-21 Martin Jambor <mjambor@suse.cz>
-+
-+ PR ipa/55260
-+ * ipa-cp.c (cgraph_edge_brings_all_agg_vals_for_node): Uce correct
-+ info when checking whether lattices are bottom.
-+
-+2014-02-21 Jakub Jelinek <jakub@redhat.com>
-+
-+ * config/i386/i386.c (ix86_expand_vec_perm): Use V8SImode
-+ mode for mask of V8SFmode permutation.
-+
-+2014-02-20 Richard Henderson <rth@redhat.com>
-+
-+ PR c++/60272
-+ * builtins.c (expand_builtin_atomic_compare_exchange): Conditionalize
-+ on failure the store back into EXPECT. Always make a new pseudo for
-+ OLDVAL.
-+
-+2014-02-20 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/57896
-+ * config/i386/i386.c (expand_vec_perm_interleave2): Don't call
-+ gen_reg_rtx if d->testing_p.
-+ (expand_vec_perm_pshufb2, expand_vec_perm_even_odd_1,
-+ expand_vec_perm_broadcast_1): Return early if d->testing_p and
-+ we will certainly return true.
-+
-+2014-02-20 Richard Biener <rguenther@suse.de>
-+
-+ * tree-cfg.c (replace_uses_by): Mark altered BBs before
-+ doing the substitution.
-+
-+2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/60207
-+ * config/i386/i386.c (construct_container): Remove TFmode check
-+ for X86_64_INTEGER_CLASS.
-+
-+2014-02-19 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-02-19 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59794
-+ * config/i386/i386.c (type_natural_mode): Warn for ABI changes
-+ only when -Wpsabi is enabled.
-+
-+2014-02-19 Terry Guo <terry.guo@arm.com>
-+
-+ Backport from mainline
-+ 2014-02-08 Terry Guo <terry.guo@arm.com>
-+
-+ * doc/invoke.texi: Document ARM -march=armv7e-m.
-+
-+2014-02-18 Kai Tietz <ktietz@redhat.com>
-+
-+ Backport from mainline
-+ 2014-02-18 Kai Tietz <ktietz@redhat.com>
-+
-+ PR target/60193
-+ * config/i386/i386.c (ix86_expand_prologue): Use
-+ rax register as displacement for restoring %r10, %rax.
-+ Additional fix wrong offset for restoring both-registers.
-+
-+2014-02-18 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * ipa-prop.c (compute_complex_ancestor_jump_func): Replace overzealous
-+ assertion with conditional return.
-+
-+2014-02-18 Jakub Jelinek <jakub@redhat.com>
-+ Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR driver/60233
-+ * config/i386/driver-i386.c (host_detect_local_cpu): If
-+ YMM state is not saved by the OS, also clear has_f16c. Move
-+ CPUID 0x80000001 handling before YMM state saving checking.
-+
-+2014-02-14 Roland McGrath <mcgrathr@google.com>
-+
-+ * configure.ac (HAVE_AS_IX86_UD2): New test for 'ud2' mnemonic.
-+ * configure: Regenerated.
-+ * config.in: Regenerated.
-+ * config/i386/i386.md (trap) [HAVE_AS_IX86_UD2]: Use the mnemonic
-+ instead of ASM_SHORT.
-+
-+2014-02-13 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-02-13 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/sse.md (xop_vmfrcz<mode>2): Generate const0 in
-+ operands[2], not operands[3].
-+
-+2014-02-13 Dominik Vogt <vogt@linux.vnet.ibm.com>
-+
-+ * config/s390/s390.c (s390_asm_output_function_label): Fix crash
-+ caused by bad second argument to warning_at() with -mhotpatch and
-+ nested functions (e.g. with gfortran).
-+
-+2014-02-12 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2014-02-12 H.J. Lu <hongjiu.lu@intel.com>
-+ Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/60151
-+ * configure.ac (HAVE_AS_GOTOFF_IN_DATA): Pass --32 to GNU assembler.
-+
-+2014-02-12 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR rtl-optimization/60116
-+ * combine.c (try_combine): Also remove dangling REG_DEAD notes on the
-+ other_insn once the combination has been validated.
-+
-+2014-02-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
-+
-+ * config/microblaze/microblaze.md: Add movsi4_rev insn pattern.
-+ * config/microblaze/predicates.md: Add reg_or_mem_operand predicate.
-+
-+2014-02-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
-+
-+ * config/microblaze/microblaze.c: Extend mcpu version format
-+
-+2014-02-10 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ * config/microblaze/microblaze.h: Define SIZE_TYPE and PTRDIFF_TYPE.
-+
-+2014-02-10 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-01-30 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59903
-+ * tree-vect-loop.c (vect_transform_loop): Guard multiple-types
-+ check properly.
-+
-+ 2014-02-10 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60115
-+ * tree-eh.c (tree_could_trap_p): Unify TARGET_MEM_REF and
-+ MEM_REF handling. Properly verify that the accesses are not
-+ out of the objects bound.
-+
-+2014-02-05 James Greenhalgh <james.greenhalgh@arm.com>
-+
-+ Backport from mainline.
-+ 2014-02-05 James Greenhalgh <james.greenhalgh@arm.com>
-+
-+ PR target/59718
-+ * doc/invoke.texi (-march): Clarify documentation for ARM.
-+ (-mtune): Likewise.
-+ (-mcpu): Likewise.
-+
-+2014-02-04 John David Anglin <danglin@gcc.gnu.org>
-+
-+ PR target/59777
-+ * config/pa/pa.c (legitimize_tls_address): Return original address
-+ if not passed a SYMBOL_REF rtx.
-+ (hppa_legitimize_address): Call legitimize_tls_address for all TLS
-+ addresses.
-+ (pa_emit_move_sequence): Simplify TLS source operands.
-+ (pa_legitimate_constant_p): Reject all TLS constants.
-+ * config/pa/pa.h (PA_SYMBOL_REF_TLS_P): Correct comment.
-+ (CONSTANT_ADDRESS_P): Reject TLS CONST addresses.
-+
-+2014-02-04 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-02-02 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/60017
-+ * config/i386/i386.c (classify_argument): Fix handling of bit_offset
-+ when calculating size of integer atomic types.
-+
-+2014-02-02 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-01-30 Jakub Jelinek <jakub@redhat.com>
-+
-+ * config/i386/f16cintrin.h (_cvtsh_ss): Avoid -Wnarrowing warning.
-+
-+2014-01-31 Richard Henderson <rth@redhat.com>
-+
-+ PR middle-end/60004
-+ * tree-eh.c (lower_try_finally_switch): Delay lowering finally block
-+ until after else_eh is processed.
-+
-+2014-01-30 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ Backport from mainline
-+ * config/microblaze/microblaze.md(cstoresf4, cbranchsf4): Replace
-+ comparison_operator with ordered_comparison_operator.
-+
-+2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ Backport from mainline
-+ 2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and
-+ avoid clobbering a live register.
-+
-+2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ Backport from mainline
-+ 2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ * config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins):
-+ Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}.
-+ * config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins):
-+ Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}.
-+
-+2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ Backport from mainline
-+ 2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier
-+ insns before bundling.
-+ * config/tilegx/tilegx.md (tile_network_barrier): Update comment.
-+
-+2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ Backport from mainline
-+ 2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ * config/tilegx/tilegx.c (tilegx_expand_builtin): Set
-+ PREFETCH_SCHEDULE_BARRIER_P to true for prefetches.
-+ * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto.
-+
-+2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ Backport from mainline
-+ 2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ * config/tilepro/tilepro.md (ctzdi2): Use register_operand
-+ predicate.
-+ (clzdi2): Ditto.
-+ (ffsdi2): Ditto.
-+
-+2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ Backport from mainline
-+ 2014-01-25 Walter Lee <walt@tilera.com>
-+
-+ * config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New.
-+ (TARGET_EXPAND_TO_RTL_HOOK): Define.
-+
-+2014-01-24 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2014-01-23 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59929
-+ * config/i386/i386.md (pushsf splitter): Get stack adjustment
-+ from push operand if code of push isn't PRE_DEC.
-+
-+2014-01-23 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ Backport from mainline.
-+ * config/microblaze/microblaze.md: Add trap insn and attribute
-+
-+2014-01-23 Marek Polacek <polacek@redhat.com>
-+
-+ Backport from mainline
-+ 2013-10-21 Marek Polacek <polacek@redhat.com>
-+
-+ PR middle-end/58809
-+ * fold-const.c (fold_range_test): Return 0 if the type is not
-+ an integral type.
-+
-+2014-01-22 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ * config/microblaze/microblaze.md: Correct bswaphi2 insn.
-+
-+2014-01-22 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-01-20 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false
-+ for SImode_address_operand operands, having only a REG argument.
-+
-+ 2014-01-20 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/59880
-+ * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false
-+ if operands[1] is a REG or ZERO_EXTEND of a REG.
-+
-+ 2014-01-18 Uros Bizjak <ubizjak@gmail.com>
-+ H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59379
-+ * config/i386/i386.md (*lea<mode>): Zero-extend return register
-+ to DImode for zero-extended addresses.
-+
-+2014-01-21 Andrew Pinski <apinski@cavium.com>
-+ Steve Ellcey <sellcey@mips.com>
-+
-+ PR target/59462
-+ * config/mips/mips.c (mips_print_operand): Check operand mode instead
-+ of operator mode.
-+
-+2014-01-21 Andrey Belevantsev <abel@ispras.ru>
-+
-+ Backport from mainline
-+ 2013-12-23 Andrey Belevantsev <abel@ispras.ru>
-+
-+ PR rtl-optimization/57422
-+ * sel-sched.c (mark_unavailable_hard_regs): Fix typo when calling
-+ add_to_hard_reg_set.
-+
-+2014-01-20 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/59860
-+ * tree.h (fold_builtin_strcat): New prototype.
-+ * builtins.c (fold_builtin_strcat): No longer static. Add len
-+ argument, if non-NULL, don't call c_strlen. Optimize
-+ directly into __builtin_memcpy instead of __builtin_strcpy.
-+ (fold_builtin_2): Adjust fold_builtin_strcat caller.
-+ * gimple-fold.c (gimple_fold_builtin): Handle BUILT_IN_STRCAT.
-+
-+2014-01-20 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/59860
-+ * builtins.c (fold_builtin_strcat): Remove case better handled
-+ by tree-ssa-strlen.c.
-+
-+2014-01-19 John David Anglin <danglin@gcc.gnu.org>
-+
-+ * config/pa/pa.c (pa_attr_length_millicode_call): Correct length of
-+ long non-pic millicode calls.
-+
-+2014-01-17 John David Anglin <danglin@gcc.gnu.org>
-+
-+ * config/pa/pa.c (pa_attr_length_indirect_call): Don't output a short
-+ call to $$dyncall when TARGET_LONG_CALLS is true.
-+
-+2014-01-17 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2014-01-14 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59794
-+ * config/i386/i386.c (type_natural_mode): Add a bool parameter
-+ to indicate if type is used for function return value. Warn
-+ ABI change if the vector mode isn't available for function
-+ return value.
-+ (ix86_function_arg_advance): Pass false to type_natural_mode.
-+ (ix86_function_arg): Likewise.
-+ (ix86_gimplify_va_arg): Likewise.
-+ (function_arg_32): Don't warn ABI change.
-+ (ix86_function_value): Pass true to type_natural_mode.
-+ (ix86_return_in_memory): Likewise.
-+ (ix86_struct_value_rtx): Removed.
-+ (TARGET_STRUCT_VALUE_RTX): Likewise.
-+
-+2014-01-17 Charles Baylis <charles.baylis@linaro.org>
-+
-+ Backport from mainline
-+ 2013-12-19 Charles Baylis <charles.baylis@linaro.org>
-+
-+ PR target/59142
-+ * config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb
-+ patterns.
-+ * config/arm/ldmstm.md: Regenerate.
-+
-+ 2013-12-19 Charles Baylis <charles.baylis@linaro.org>
-+
-+ PR target/59142
-+ * config/arm/predicates.md (arm_hard_general_register_operand):
-+ New predicate.
-+ (arm_hard_register_operand): Remove.
-+ * config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand
-+ for all patterns.
-+ * config/arm/ldmstm.md: Regenerate.
-+
-+ 2013-12-19 Charles Baylis <charles.baylis@linaro.org>
-+
-+ PR target/59142
-+ * config/arm/predicates.md (vfp_hard_register_operand): New predicate.
-+ * config/arm/arm.md (vfp_pop_multiple_with_writeback): Use
-+ vfp_hard_register_operand.
-+
-+2014-01-17 Kugan Vivekanandarajah <kuganv@linaro.org>
-+
-+ Backport from mainline
-+ 2014-01-15 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org>
-+ Kugan Vivekanandarajah <kuganv@linaro.org>
-+
-+ PR target/59695
-+ * config/aarch64/aarch64.c (aarch64_build_constant): Fix incorrect
-+ truncation.
-+
-+2014-01-17 Terry Guo <terry.guo@arm.com>
-+
-+ PR target/59826
-+ * config/arm/arm.md (prefetch): Set insn type attribute to load1.
-+
-+2014-01-16 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/59839
-+ * config/i386/i386.c (ix86_expand_builtin): If target doesn't
-+ satisfy operand 0 predicate for gathers, use a new pseudo as
-+ subtarget.
-+
-+2014-01-16 Richard Henderson <rth@redhat.com>
-+
-+ PR debug/54694
-+ * reginfo.c (global_regs_decl): Globalize.
-+ * rtl.h (global_regs_decl): Declare.
-+ * ira.c (do_reload): Diagnose frame_pointer_needed and it
-+ reserved via global_regs.
-+
-+2014-01-16 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2014-01-15 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/i386.c (ix86_hard_regno_mode_ok): Use
-+ VALID_AVX256_REG_OR_OI_MODE.
-+
-+ 2013-09-05 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ PR target/58139
-+ * reginfo.c (choose_hard_reg_mode): Scan through all mode classes
-+ looking for widest mode.
-+
-+2014-01-16 Marek Polacek <polacek@redhat.com>
-+
-+ Backported from mainline
-+ 2014-01-16 Marek Polacek <polacek@redhat.com>
-+
-+ PR middle-end/59827
-+ * gimple-low.c (gimple_check_call_args): Don't use DECL_ARG_TYPE if
-+ it is error_mark_node.
-+
-+2014-01-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ PR target/59803
-+ * config/s390/s390.c (s390_preferred_reload_class): Don't return
-+ ADDR_REGS for invalid symrefs in non-PIC code.
-+
-+2014-01-14 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Revert:
-+ 2014-01-08 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/i386.c (ix86_data_alignment): Calculate max_align
-+ from prefetch_block tune setting.
-+
-+2014-01-13 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backported from mainline
-+ 2014-01-10 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59745
-+ * tree-predcom.c (tree_predictive_commoning_loop): Call
-+ free_affine_expand_cache if giving up because components is NULL.
-+
-+2014-01-10 Yufeng Zhang <yufeng.zhang@arm.com>
-+
-+ * config/arm/arm.c (arm_expand_neon_args): Call expand_expr
-+ with EXPAND_MEMORY for NEON_ARG_MEMORY; check if the returned
-+ rtx is const0_rtx or not.
-+
-+2014-01-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ * config/s390/s390.c (s390_expand_tbegin): Remove jump over CC
-+ extraction in good case.
-+
-+2014-01-10 Huacai Chen <chenhc@lemote.com>
-+
-+ * config/mips/driver-native.c (host_detect_local_cpu): Handle new
-+ kernel strings for Loongson-2E/2F/3A.
-+
-+2014-01-10 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59715
-+ * tree-flow.h (split_critical_edges): Declare.
-+ * tree-cfg.c (split_critical_edges): Export.
-+ * tree-ssa-sink.c (execute_sink_code): Split critical edges.
-+
-+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ * config/mips/mips.h (ISA_HAS_WSBH): Define.
-+ * config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New
-+ constants.
-+ (bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns.
-+
-+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ PR rtl-optimization/59137
-+ * reorg.c (steal_delay_list_from_target): Call update_block for
-+ elided insns.
-+ (steal_delay_list_from_fallthrough, relax_delay_slots): Likewise.
-+
-+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ Revert:
-+ 2012-10-07 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ * config/mips/mips.c (mips_truncated_op_cost): New function.
-+ (mips_rtx_costs): Adjust test for BADDU.
-+ * config/mips/mips.md (*baddu_di<mode>): Push truncates to operands.
-+
-+ 2012-10-02 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into...
-+ (*baddu_si): ...this new pattern.
-+
-+2014-01-09 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-18 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59125
-+ PR tree-optimization/54570
-+ * tree-ssa-sccvn.c (copy_reference_ops_from_ref): When inlining
-+ is not complete do not treat component-references with offset zero
-+ but different fields as equal.
-+ * tree-object-size.c: Include tree-phinodes.h and ssa-iterators.h.
-+ (compute_object_sizes): Apply TLC. Propagate the constant
-+ results into all uses and fold their stmts.
-+ * passes.def (pass_all_optimizations): Move pass_object_sizes
-+ after the first pass_forwprop and before pass_fre.
-+
-+ 2013-12-03 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59362
-+ * tree-object-size.c (object_sizes): Change into array of
-+ vec<unsigned HOST_WIDE_INT>.
-+ (compute_builtin_object_size): Check computed bitmap for
-+ non-NULL instead of object_sizes. Call safe_grow on object_sizes
-+ vector if new SSA_NAMEs appeared.
-+ (init_object_sizes): Check computed bitmap for non-NULL.
-+ Call safe_grow on object_sizes elements instead of initializing
-+ it with XNEWVEC.
-+ (fini_object_sizes): Call release on object_sizes elements, don't
-+ set it to NULL.
-+
-+2014-01-09 Richard Earnshaw <rearnsha@arm.com>
-+
-+ PR rtl-optimization/54300
-+ * regcprop.c (copyprop_hardreg_forward_1): Ensure any unused
-+ outputs in a single-set are killed from the value chains.
-+
-+2014-01-09 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR rtl-optimization/59724
-+ * ifcvt.c (cond_exec_process_if_block): Don't call
-+ flow_find_head_matching_sequence with 0 longest_match.
-+ * cfgcleanup.c (flow_find_head_matching_sequence): Count even
-+ non-active insns if !stop_after.
-+ (try_head_merge_bb): Revert 2014-01-07 changes.
-+
-+2014-01-09 Hans-Peter Nilsson <hp@axis.com>
-+
-+ Backport from mainline
-+ 2013-12-23 Hans-Peter Nilsson <hp@axis.com>
-+
-+ PR middle-end/59584
-+ * config/cris/predicates.md (cris_nonsp_register_operand):
-+ New define_predicate.
-+ * config/cris/cris.md: Replace register_operand with
-+ cris_nonsp_register_operand for destinations in all
-+ define_splits where a register is set more than once.
-+
-+2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2013-12-25 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59587
-+ * config/i386/i386.c (struct ptt): Add a field for processor name.
-+ (processor_target_table): Sync with processor_type. Add
-+ processor names.
-+ (cpu_names): Removed.
-+ (ix86_option_override_internal): Default x_ix86_tune_string
-+ to processor_target_table[TARGET_CPU_DEFAULT].name.
-+ (ix86_function_specific_print): Assert arch and tune <
-+ PROCESSOR_max. Use processor_target_table to print arch and
-+ tune names.
-+ * config/i386/i386.h (TARGET_CPU_DEFAULT): Default to
-+ PROCESSOR_GENERIC32.
-+ (target_cpu_default): Removed.
-+ (processor_type): Reordered.
-+
-+2014-01-08 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-01-05 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/i386.c (ix86_data_alignment): Calculate max_align
-+ from prefetch_block tune setting.
-+ (nocona_cost): Correct size of prefetch block to 64.
-+
-+2014-01-08 Martin Jambor <mjambor@suse.cz>
-+
-+ PR ipa/59610
-+ * ipa-prop.c (ipa_compute_jump_functions): Bail out if not optimizing.
-+ (parm_preserved_before_stmt_p): Assume modification present when not
-+ optimizing.
-+
-+2014-01-07 John David Anglin <danglin@gcc.gnu.org>
-+
-+ PR target/59652
-+ * config/pa/pa.c (pa_legitimate_address_p): Return false before reload
-+ for 14-bit register offsets when INT14_OK_STRICT is false.
-+
-+2014-01-07 Roland Stigge <stigge@antcom.de>
-+ Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR 57386/target
-+ * config/rs6000/rs6000.c (rs6000_legitimate_offset_address_p):
-+ Only check TFmode for SPE constants. Don't check TImode or TDmode.
-+
-+2014-01-07 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR rtl-optimization/58668
-+ * cfgcleanup.c (flow_find_cross_jump): Don't count
-+ any jumps if dir_p is NULL. Remove p1 variable and make USE/CLOBBER
-+ check consistent with other places.
-+ (flow_find_head_matching_sequence): Don't count USE or CLOBBER insns.
-+ (try_head_merge_bb): Adjust for the flow_find_head_matching_sequence
-+ counting change.
-+ * ifcvt.c (count_bb_insns): Don't count USE or CLOBBER insns.
-+
-+2014-01-07 Mike Stump <mikestump@comcast.net>
-+ Jakub Jelinek <jakub@redhat.com>
-+
-+ PR pch/59436
-+ * tree.h (struct tree_optimization_option): Change optabs
-+ type from unsigned char * to void *.
-+ * optabs.c (init_tree_optimization_optabs): Adjust
-+ TREE_OPTIMIZATION_OPTABS initialization.
-+
-+2014-01-07 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backported from mainline
-+ 2013-12-16 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/58956
-+ PR middle-end/59470
-+ * gimple.h (walk_stmt_load_store_addr_fn): New typedef.
-+ (walk_stmt_load_store_addr_ops, walk_stmt_load_store_ops): Use it
-+ for callback params.
-+ * gimple.c (walk_stmt_load_store_ops): Likewise.
-+ (walk_stmt_load_store_addr_ops): Likewise. Adjust all callback
-+ calls to supply the gimple operand containing the base tree
-+ as an extra argument.
-+ * tree-ssa-ter.c (find_ssaname, find_ssaname_in_store): New helper
-+ functions.
-+ (find_replaceable_in_bb): For calls or GIMPLE_ASM, only set
-+ same_root_var if USE is used somewhere in the stores of the stmt.
-+ * ipa-prop.c (visit_ref_for_mod_analysis): Remove name of the stmt
-+ argument and ATTRIBUTE_UNUSED, add another unnamed tree argument.
-+ * ipa-pure-const.c (check_load, check_store, check_ipa_load,
-+ check_ipa_store): Likewise.
-+ * gimple.c (gimple_ior_addresses_taken_1): Likewise.
-+ * ipa-split.c (test_nonssa_use, mark_nonssa_use): Likewise.
-+ (verify_non_ssa_vars, visit_bb): Adjust their callers.
-+ * cfgexpand.c (add_scope_conflicts_1): Use
-+ walk_stmt_load_store_addr_fn type for visit variable.
-+ (visit_op, visit_conflict): Remove name of the stmt
-+ argument and ATTRIBUTE_UNUSED, add another unnamed tree argument.
-+ * tree-sra.c (asm_visit_addr): Likewise. Remove name of the data
-+ argument and ATTRIBUTE_UNUSED.
-+ * cgraphbuild.c (mark_address, mark_load, mark_store): Add another
-+ unnamed tree argument.
-+
-+2014-01-03 Andreas Schwab <schwab@linux-m68k.org>
-+
-+ * config/m68k/m68k.c (handle_move_double): Handle pushes with
-+ overlapping registers also for registers other than the stack
-+ pointer.
-+
-+2014-01-03 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/59625
-+ * config/i386/i386.c (ix86_avoid_jump_mispredicts): Don't consider
-+ asm goto as jump.
-+
-+2014-01-01 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR rtl-optimization/59647
-+ * cse.c (cse_process_notes_1): Don't substitute negative VOIDmode
-+ new_rtx into UNSIGNED_FLOAT rtxes.
-+
-+2013-12-28 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * doc/invoke.texi (output file options): Document -fada-spec-parent.
-+
-+2013-12-26 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/driver-i386.c (decode_caches_intel): Add missing entries.
-+
-+2013-12-20 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c++/59255
-+ Backported from mainline
-+ 2013-08-19 Dehao Chen <dehao@google.com>
-+
-+ * value-prof.c (gimple_ic): Fix the bug of adding EH edge.
-+
-+2013-12-19 James Greenhalgh <james.greenhalgh@arm.com>
-+
-+ Backport from Mainline.
-+ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>
-+
-+ * config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to...
-+ (cmgeu): ...This.
-+ (cmhi): Rename to...
-+ (cmgtu): ...This.
-+ * config/aarch64/aarch64-simd.md
-+ (simd_mode): Add SF.
-+ (aarch64_vcond_internal): Use new names for unsigned comparison insns.
-+ (aarch64_cm<optab><mode>): Rewrite to not use UNSPECs.
-+ * config/aarch64/aarch64.md (*cstore<mode>_neg): Rename to...
-+ (cstore<mode>_neg): ...This.
-+ * config/aarch64/iterators.md
-+ (VALLF): new.
-+ (unspec): Remove UNSPEC_CM<EQ, LE, LT, GE, GT, HS, HI, TST>.
-+ (COMPARISONS): New.
-+ (UCOMPARISONS): Likewise.
-+ (optab): Add missing comparisons.
-+ (n_optab): New.
-+ (cmp_1): Likewise.
-+ (cmp_2): Likewise.
-+ (CMP): Likewise.
-+ (cmp): Remove.
-+ (VCMP_S): Likewise.
-+ (VCMP_U): Likewise.
-+ (V_cmp_result): Add DF, SF modes.
-+ (v_cmp_result): Likewise.
-+ (v): Likewise.
-+ (vmtype): Likewise.
-+ * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New.
-+
-+ Partial Backport from mainline.
-+ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>
-+
-+ * config/aarch64/arm_neon.h
-+ (vc<eq, lt, le, gt, ge, tst><qsd>_<u><8,16,32,64>): Remap
-+ to builtins or C as appropriate.
-+
-+2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>
-+ Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ Backport from mainline
-+ 2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>
-+ * config/s390/s390.c (s390_hotpatch_trampoline_halfwords_default): New
-+ constant
-+ (s390_hotpatch_trampoline_halfwords_max): New constant
-+ (s390_hotpatch_trampoline_halfwords): New static variable
-+ (get_hotpatch_attribute): New function
-+ (s390_handle_hotpatch_attribute): New function
-+ (s390_attribute_table): New target specific attribute table to implement
-+ the hotpatch attribute
-+ (s390_option_override): Parse hotpatch options
-+ (s390_function_num_hotpatch_trampoline_halfwords): New function
-+ (s390_can_inline_p): Implement target hook to
-+ suppress hotpatching for explicitly inlined functions
-+ (s390_asm_output_function_label): Generate hotpatch prologue
-+ (TARGET_ATTRIBUTE_TABLE): Define to implement target attribute table
-+ (TARGET_CAN_INLINE_P): Define to implement target hook
-+ * config/s390/s390.opt (mhotpatch): New options -mhotpatch, -mhotpatch=
-+ * config/s390/s390-protos.h (s390_asm_output_function_label): Add
-+ prototype
-+ * config/s390/s390.h (ASM_OUTPUT_FUNCTION_LABEL): Target specific
-+ function label generation for hotpatching
-+ (FUNCTION_BOUNDARY): Align functions to eight bytes
-+ * doc/extend.texi: Document hotpatch attribute
-+ * doc/invoke.texi: Document -mhotpatch option
-+
-+2013-12-18 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Fix thinko.
-+
-+2013-12-12 Vladimir Makarov <vmakarov@redhat.com>
-+
-+ PR middle-end/59470
-+ * lra-coalesce.c (lra_coalesce): Invalidate inheritance pseudo
-+ values if necessary.
-+
-+2013-12-12 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR libgomp/59467
-+ * gimplify.c (omp_check_private): Add copyprivate argument, if it
-+ is true, don't check omp_privatize_by_reference.
-+ (gimplify_scan_omp_clauses): For OMP_CLAUSE_COPYPRIVATE verify
-+ decl is private in outer context. Adjust omp_check_private caller.
-+
-+2013-12-10 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR rtl-optimization/58295
-+ * simplify-rtx.c (simplify_truncation): Restrict the distribution for
-+ WORD_REGISTER_OPERATIONS targets.
-+
-+2013-12-10 Kai Tietz <ktietz@redhat.com>
-+
-+ PR target/56807
-+ * config/i386/i386.c (ix86_expand_prologue): Address saved
-+ registers stack-relative, not via frame-pointer.
-+
-+2013-12-09 Alan Modra <amodra@gmail.com>
-+
-+ Apply from mainline
-+ 2013-12-05 Alan Modra <amodra@gmail.com>
-+ * configure.ac (BUILD_CXXFLAGS) Don't use ALL_CXXFLAGS for
-+ build != host.
-+ <recursive call for build != host>: Clear GMPINC. Don't bother
-+ saving CFLAGS.
-+ * configure: Regenerate.
-+
-+2013-12-08 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-12-06 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59405
-+ * config/i386/i386.c (type_natural_mode): Properly handle
-+ size 8 for !TARGET_64BIT.
-+
-+2013-12-07 Ralf Corsépius <ralf.corsepius@rtems.org>
-+
-+ * config.gcc (microblaze*-*-rtems*): Add TARGET_BIG_ENDIAN_DEFAULT.
-+
-+2013-12-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59388
-+ * tree-ssa-reassoc.c (update_range_test): If op == range->exp,
-+ gimplify tem after stmt rather than before it.
-+
-+2013-12-06 Oleg Endo <olegendo@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-11-26 Oleg Endo <olegendo@gcc.gnu.org>
-+
-+ PR target/58314
-+ PR target/50751
-+ * config/sh/sh.c (max_mov_insn_displacement, disp_addr_displacement):
-+ Prefix function names with 'sh_'. Make them non-static.
-+ * config/sh/sh-protos.h (sh_disp_addr_displacement,
-+ sh_max_mov_insn_displacement): Add declarations.
-+ * config/sh/constraints.md (Q): Reject QImode.
-+ (Sdd): Use match_code "mem".
-+ (Snd): Fix erroneous matching of non-memory operands.
-+ * config/sh/predicates.md (short_displacement_mem_operand): New
-+ predicate.
-+ (general_movsrc_operand): Disallow PC relative QImode loads.
-+ * config/sh/sh.md (*mov<mode>_reg_reg): Remove it.
-+ (*movqi, *movhi): Merge both insns into...
-+ (*mov<mode>): ... this new insn. Replace generic 'm' constraints with
-+ 'Snd' and 'Sdd' constraints. Calculate insn length dynamically based
-+ on the operand types.
-+
-+2013-12-06 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-29 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59334
-+ * tree-ssa-dce.c (eliminate_unnecessary_stmts): Fix bug
-+ in previous commit.
-+
-+ 2013-11-28 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59330
-+ * tree-ssa-dce.c (eliminate_unnecessary_stmts): Simplify
-+ and fix delayed marking of free calls not necessary.
-+
-+2013-12-06 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-27 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59288
-+ * tree-vect-loop.c (get_initial_def_for_induction): Do not
-+ re-analyze the PHI but use STMT_VINFO_LOOP_PHI_EVOLUTION_PART.
-+
-+ 2013-11-19 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59164
-+ * tree-vect-loop.c (vect_analyze_loop_operations): Adjust
-+ check whether we can create an epilogue loop to reflect the
-+ cases where we create one.
-+
-+ 2013-09-05 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/58137
-+ * tree-vect-stmts.c (get_vectype_for_scalar_type_and_size):
-+ Do not create vectors of pointers.
-+ * tree-vect-loop.c (get_initial_def_for_induction): Use proper
-+ types for the components of the vector initializer.
-+ * tree-cfg.c (verify_gimple_assign_binary): Remove special-casing
-+ allowing pointer vectors with PLUS_EXPR/MINUS_EXPR.
-+
-+2013-12-06 Oleg Endo <olegendo@gcc.gnu.org>
-+
-+ PR target/51244
-+ PR target/59343
-+ * config/sh/sh.md (*cbranch_t): Check that there are no labels between
-+ the s1 insn and the testing insn. Remove REG_DEAD note from s1 insn.
-+
-+2013-12-05 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-19 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/58956
-+ * tree-ssa-ter.c (find_replaceable_in_bb): Avoid forwarding
-+ loads into stmts that may clobber it.
-+
-+2013-12-04 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR rtl-optimization/58726
-+ * combine.c (force_to_mode): Fix comment typo. Don't destructively
-+ modify x for ROTATE, ROTATERT and IF_THEN_ELSE.
-+
-+2013-12-04 Jakub Jelinek <jakub@redhat.com>
-+ Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59163
-+ * config/i386/i386.c (ix86_legitimate_combined_insn): If for
-+ !TARGET_AVX there is misaligned MEM operand with vector mode
-+ and get_attr_ssememalign is 0, return false.
-+ (ix86_expand_special_args_builtin): Add get_pointer_alignment
-+ computed alignment and for non-temporal loads/stores also
-+ at least GET_MODE_ALIGNMENT as MEM_ALIGN.
-+ * config/i386/sse.md
-+ (<sse>_loadu<ssemodesuffix><avxsizesuffix>,
-+ <sse>_storeu<ssemodesuffix><avxsizesuffix>,
-+ <sse2>_loaddqu<avxsizesuffix>,
-+ <sse2>_storedqu<avxsizesuffix>, <sse3>_lddqu<avxsizesuffix>,
-+ sse_vmrcpv4sf2, sse_vmrsqrtv4sf2, sse2_cvtdq2pd, sse_movhlps,
-+ sse_movlhps, sse_storehps, sse_loadhps, sse_loadlps,
-+ *vec_interleave_highv2df, *vec_interleave_lowv2df,
-+ *vec_extractv2df_1_sse, sse2_loadhpd, sse2_loadlpd, sse2_movsd,
-+ sse4_1_<code>v8qiv8hi2, sse4_1_<code>v4qiv4si2,
-+ sse4_1_<code>v4hiv4si2, sse4_1_<code>v2qiv2di2,
-+ sse4_1_<code>v2hiv2di2, sse4_1_<code>v2siv2di2, sse4_2_pcmpestr,
-+ *sse4_2_pcmpestr_unaligned, sse4_2_pcmpestri, sse4_2_pcmpestrm,
-+ sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, *sse4_2_pcmpistr_unaligned,
-+ sse4_2_pcmpistri, sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Add
-+ ssememalign attribute.
-+ * config/i386/i386.md (ssememalign): New define_attr.
-+
-+2013-12-03 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/59011
-+ * gimplify.c (nonlocal_vla_vars): New variable.
-+ (gimplify_var_or_parm_decl): Put VAR_DECLs for VLAs into
-+ nonlocal_vla_vars chain.
-+ (gimplify_body): Call declare_vars on nonlocal_vla_vars chain
-+ if outer_bind has DECL_INITIAL (current_function_decl) block.
-+
-+ PR target/58864
-+ * optabs.c (emit_conditional_move): Save and restore
-+ pending_stack_adjust and stack_pointer_delta if cmove can't be used.
-+
-+2013-12-02 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59358
-+ * tree-vrp.c (union_ranges): To check for the partially
-+ overlapping ranges or adjacent ranges, also compare *vr0max
-+ with vr1max.
-+
-+2013-12-02 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59139
-+ * tree-ssa-loop-niter.c (chain_of_csts_start): Properly match
-+ code in get_val_for.
-+ (get_val_for): Use gcc_checking_asserts.
-+
-+2013-11-27 Tom de Vries <tom@codesourcery.com>
-+ Marc Glisse <marc.glisse@inria.fr>
-+
-+ PR middle-end/59037
-+ * fold-const.c (fold_indirect_ref_1): Don't create out-of-bounds
-+ BIT_FIELD_REF.
-+ * gimplify.c (gimple_fold_indirect_ref): Same.
-+
-+2013-12-01 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * config/i386/winnt.c (i386_pe_asm_named_section): Be prepared for an
-+ identifier node.
-+
-+2013-12-01 Bernd Edlinger <bernd.edlinger@hotmail.de>
-+
-+ * expr.c (emit_group_store): Fix off-by-one BITFIELD_END argument.
-+
-+2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-+
-+ Backport from mainline
-+ 2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-+
-+ * config/arm/iterators.md (vrint_conds): New int attribute.
-+ * config/arm/vfp.md (<vrint_pattern><SDF:mode>2): Set conds attribute.
-+ (smax<mode>3): Likewise.
-+ (smin<mode>3): Likewise.
-+
-+2013-11-28 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-11-27 Uros Bizjak <ubizjak@gmail.com>
-+ Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
-+
-+ PR target/56788
-+ * gcc.target/i386/xop-frczX.c: New test.
-+
-+2013-11-28 Terry Guo <terry.guo@arm.com>
-+
-+ Backport mainline r205391
-+ 2013-11-26 Terry Guo <terry.guo@arm.com>
-+
-+ * config/arm/arm.c (require_pic_register): Handle high pic base
-+ register for thumb-1.
-+ (arm_load_pic_register): Also initialize high pic base register.
-+ * doc/invoke.texi: Update documentation for option -mpic-register.
-+
-+2013-11-27 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backported from mainline
-+ 2013-11-26 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59014
-+ * tree-vrp.c (register_edge_assert_for_1): Don't look
-+ through conversions from non-integral types or through
-+ narrowing conversions.
-+
-+2013-11-27 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR middle-end/59138
-+ * expr.c (emit_group_store): Don't write past the end of the structure.
-+ (store_bit_field): Fix formatting.
-+
-+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
-+
-+ Backport from mainline
-+ 2013-09-17 Sebastian Huber <sebastian.huber@embedded-brains.de>
-+
-+ * config/sparc/t-rtems: Add leon3 multilibs.
-+
-+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
-+
-+ Backport from mainline
-+ 2013-08-09 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * configure.ac: Add GAS check for LEON instructions on SPARC.
-+ * configure: Regenerate.
-+ * config.in: Likewise.
-+ * config.gcc (with_cpu): Remove sparc-leon*-* and deal with LEON in the
-+ sparc*-*-* block.
-+ * config/sparc/sparc.opt (LEON, LEON3): New masks.
-+ * config/sparc/sparc.h (ASM_CPU32_DEFAULT_SPEC): Set to AS_LEON_FLAG
-+ for LEON or LEON3.
-+ (ASM_CPU_SPEC): Pass AS_LEON_FLAG if -mcpu=leon or -mcpu=leon3.
-+ (AS_LEON_FLAG): New macro.
-+ * config/sparc/sparc.c (sparc_option_override): Set MASK_LEON for leon
-+ and MASK_LEON3 for leon3 and unset them if HAVE_AS_LEON is not defined.
-+ Deal with LEON and LEON3 for the memory model.
-+ * config/sparc/sync.md (atomic_compare_and_swap<mode>): Enable if LEON3
-+ (atomic_compare_and_swap<mode>_1): Likewise.
-+ (*atomic_compare_and_swap<mode>_1): Likewise.
-+
-+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
-+
-+ Backport from mainline
-+ 2013-07-23 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * doc/invoke.texi (SPARC Options): Document new leon3 processor value.
-+
-+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
-+
-+ Backport from mainline
-+ 2013-07-22 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * config.gcc (sparc*-*-*): Accept leon3 processor.
-+ (sparc-leon*-*): Merge with sparc*-*-* and add leon3 support.
-+ * doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry.
-+ * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3.
-+ * config/sparc/sparc.opt (enum processor_type): Add leon3.
-+ (mfix-ut699): Adjust comment.
-+ * config/sparc/sparc.h (TARGET_CPU_leon3): New define.
-+ (CPP_CPU32_DEFAULT_SPEC): Add leon3 support.
-+ (CPP_CPU_SPEC): Likewise.
-+ (ASM_CPU_SPEC): Likewise.
-+ * config/sparc/sparc.c (leon3_cost): New constant.
-+ (sparc_option_override): Add leon3 support.
-+ (mem_ref): New function.
-+ (sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled.
-+ (sparc_do_work_around_errata): Look into the instruction in the delay
-+ slot and adjust accordingly. Add fix for the data cache nullify issues
-+ of the UT699. Change insertion position for the NOP.
-+ * config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete.
-+ (leon3_load): New reservation.
-+ (leon_store): Bump latency to 2.
-+ (grfpu): New automaton.
-+ (grfpu_alu): New unit.
-+ (grfpu_ds): Likewise.
-+ (leon_fp_alu): Adjust.
-+ (leon_fp_mult): Delete.
-+ (leon_fp_div): Split into leon_fp_divs and leon_fp_divd.
-+ (leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd.
-+ * config/sparc/sparc.md (cpu): Add leon3.
-+ * config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699.
-+ (swapsi): Likewise.
-+ (atomic_test_and_set): Likewise.
-+ (ldstub): Likewise.
-+
-+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
-+
-+ Backport from mainline
-+ 2013-04-10 Steven Bosscher <steven@gcc.gnu.org>
-+
-+ * config/sparc/sparc.c: Include tree-pass.h.
-+ (TARGET_MACHINE_DEPENDENT_REORG): Do not redefine.
-+ (sparc_reorg): Rename to sparc_do_work_around_errata. Move to
-+ head of file. Change return type. Split off gate function.
-+ (sparc_gate_work_around_errata): New function.
-+ (pass_work_around_errata): New pass definition.
-+ (insert_pass_work_around_errata) New pass insert definition to
-+ insert pass_work_around_errata just after delayed-branch scheduling.
-+ (sparc_option_override): Insert the pass.
-+ * config/sparc/t-sparc (sparc.o): Add TREE_PASS_H dependence.
-+
-+2013-11-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
-+
-+ Backport from mainline
-+ 2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * doc/invoke.texi (SPARC Options): Document -mfix-ut699.
-+ * builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the
-+ mode if the instruction isn't available in the original mode.
-+ * config/sparc/sparc.opt (mfix-ut699): New option.
-+ * config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699.
-+ (divdf3): Turn into expander.
-+ (divdf3_nofix): New insn.
-+ (divdf3_fix): Likewise.
-+ (divsf3): Disable if -mfix-ut699.
-+ (sqrtdf2): Turn into expander.
-+ (sqrtdf2_nofix): New insn.
-+ (sqrtdf2_fix): Likewise.
-+ (sqrtsf2): Disable if -mfix-ut699.
-+
-+2013-11-22 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * print-rtl.c (print_rtx) <case MEM>: Output a space if no MEM_EXPR.
-+
-+2013-11-21 Zhenqiang Chen <zhenqiang.chen@linaro.org>
-+
-+ PR bootstrap/57683
-+ Backport from mainline: r197467 and r198999.
-+ 2013-04-03 Jeff Law <law@redhat.com>
-+
-+ * Makefile.in (lra-constraints.o): Depend on $(OPTABS_H).
-+ (lra-eliminations.o): Likewise.
-+
-+ 2013-05-16 Jeff Law <law@redhat.com>
-+
-+ * Makefile.in (tree-switch-conversion.o): Depend on $(OPTABS_H).
-+
-+2013-11-20 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR target/59207
-+ * config/sparc/sparc.c (sparc_fold_builtin) <case CODE_FOR_pdist_vis>:
-+ Make sure neg2_ovf is set before being used.
-+
-+2013-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+ Dominik Vogt <vogt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ * config/s390/s390.c (s390_canonicalize_comparison): Don't fold
-+ int comparisons with an out of range condition code.
-+ (s390_optimize_nonescaping_tx): Skip empty BBs.
-+ Generate the new tbegin RTX when removing the FPR clobbers (with
-+ two SETs).
-+ (s390_expand_tbegin): Fix the retry loop counter. Copy CC to the
-+ result before doing the retry calculations.
-+ (s390_init_builtins): Make tbegin "returns_twice" and tabort
-+ "noreturn".
-+ * config/s390/s390.md (UNSPECV_TBEGIN_TDB): New constant used for
-+ the TDB setting part of an tbegin.
-+ ("tbegin_1", "tbegin_nofloat_1"): Add a set for the TDB.
-+ ("tx_assist"): Set unused argument to an immediate zero instead of
-+ loading zero into a GPR and pass it as argument.
-+ * config/s390/htmxlintrin.h (__TM_simple_begin, __TM_begin):
-+ Remove inline and related attributes.
-+ (__TM_nesting_depth, __TM_is_user_abort, __TM_is_named_user_abort)
-+ (__TM_is_illegal, __TM_is_footprint_exceeded)
-+ (__TM_is_nested_too_deep, __TM_is_conflict): Fix format value
-+ check.
-+
-+2013-11-19 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-11-18 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/i386.c (ix86_decompose_address): Use REG_P instead of
-+ ix86_address_subreg_operand. Move subreg checks to
-+ ix86_validate_address_register. Move address override check to
-+ ix86_legitimate_address_p.
-+ (ix86_validate_address_register): New function.
-+ (ix86_legitimate_address_p): Call ix86_validate_address_register
-+ to validate base and index registers. Add address override check
-+ from ix86_decompose_address.
-+ (ix86_decompose_address): Remove.
-+
-+ Backport from mainline
-+ 2013-11-17 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59153
-+ * config/i386/i386.c (ix86_address_subreg_operand): Do not
-+ reject non-integer subregs.
-+ (ix86_decompose_address): Do not reject invalid CONST_INT RTXes.
-+ Move check for invalid x32 constant addresses ...
-+ (ix86_legitimate_address_p): ... here.
-+
-+2013-11-19 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-07 Richard Biener <rguenther@suse.de>
-+
-+ * tree-dfa.c (get_ref_base_and_extent): Fix casting.
-+
-+2013-11-19 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/57517
-+ * tree-predcom.c (combinable_refs_p): Verify the combination
-+ is always executed when the refs are.
-+
-+2013-11-19 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-05 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/58941
-+ * tree-dfa.c (get_ref_base_and_extent): Merge common code
-+ in MEM_REF and TARGET_MEM_REF handling. Make sure to
-+ process trailing array detection before diving into the
-+ view-converted object (and possibly apply some extra offset).
-+
-+2013-11-18 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-10-21 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/58794
-+ * fold-const.c (operand_equal_p): Compare FIELD_DECL operand
-+ of COMPONENT_REFs with OEP_CONSTANT_ADDRESS_OF left in place.
-+
-+ 2013-10-21 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/58742
-+ * fold-const.c (fold_binary_loc): Fold ((T) (X /[ex] C)) * C
-+ to (T) X for sign-changing conversions (or no conversion).
-+
-+ 2013-11-06 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/58653
-+ * tree-predcom.c (ref_at_iteration): Rewrite to generate
-+ a MEM_REF.
-+ (prepare_initializers_chain): Adjust.
-+
-+ PR tree-optimization/59047
-+ * tree-predcom.c (ref_at_iteration): Handle bitfield accesses
-+ properly.
-+
-+ 2013-10-15 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/58143
-+ * tree-ssa-loop-im.c (arith_code_with_undefined_signed_overflow):
-+ New function.
-+ (rewrite_to_defined_overflow): Likewise.
-+ (move_computations_dom_walker::before_dom): Rewrite stmts
-+ with undefined signed overflow that are not always executed
-+ into unsigned arithmetic.
-+
-+2013-11-14 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-11-10 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * mode-switching.c (optimize_mode_switching): Mark block as
-+ nontransparent, if last_mode at block exit is different from no_mode.
-+
-+ Backport from mainline
-+ 2013-11-06 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59021
-+ * config/i386/i386.c (ix86_avx_u128_mode_needed): Require
-+ AVX_U128_DIRTY mode for call_insn RTXes that use AVX256 registers.
-+ (ix86_avx_u128_mode_needed): Return AVX_U128_DIRTY mode for call_insn
-+ RTXes that return in AVX256 register.
-+
-+2013-11-14 Jakub Jelinek <jakub@redhat.com>
-+ Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59101
-+ * config/i386/i386.md (*anddi_2): Only allow CCZmode if
-+ operands[2] satisfies_constraint_Z that might have bit 31 set.
-+
-+2013-11-12 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backported from mainline
-+ 2013-11-12 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59088
-+ * config/i386/i386.c (initial_ix86_tune_features): Set
-+ X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL and
-+ X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL for m_HASWELL.
-+
-+2013-11-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
-+
-+ Backported from mainline
-+ 2013-10-30 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
-+
-+ PR target/58854
-+ * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Emit blockage
-+
-+2013-11-11 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backported from mainline
-+ 2013-11-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/58970
-+ * expr.c (get_bit_range): Handle *offset == NULL_TREE.
-+ (expand_assignment): If *bitpos is negative, set *offset
-+ and adjust *bitpos, so that it is not negative.
-+
-+ 2013-11-05 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR rtl-optimization/58997
-+ * loop-iv.c (iv_subreg): For IV_UNKNOWN_EXTEND, expect
-+ get_iv_value to be in iv->mode rather than iv->extend_mode.
-+ (iv_extend): Likewise. Otherwise, if iv->extend != extend,
-+ use lowpart_subreg on get_iv_value before calling simplify_gen_unary.
-+ * loop-unswitch.c (may_unswitch_on): Make sure op[i] is in the right
-+ mode.
-+
-+2013-11-10 Karlson2k <k2k@narod.ru>
-+ Kai Tietz <ktietz@redhat.com>
-+
-+ Merged from trunk
-+ PR plugins/52872
-+ * configure.ac: Adding for exported symbols check
-+ and for rdynamic-check executable-extension.
-+ * configure: Regenerated.
-+
-+2013-11-07 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59034
-+ * config/i386/i386.md (push peepholer/splitter): Use Pmode
-+ with stack_pointer_rtx.
-+
-+2013-11-05 Uros Bizjak <ubizjak@gmail.com>
-+
-+ * config/i386/t-rtems (MULTILIB_MATCHES): Fix option typos.
-+
-+2013-11-05 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/58984
-+ * ipa-prop.c (ipa_load_from_parm_agg_1): Add SIZE_P argument,
-+ set *SIZE_P if non-NULL on success.
-+ (ipa_load_from_parm_agg, ipa_analyze_indirect_call_uses): Adjust
-+ callers.
-+ (ipcp_transform_function): Likewise. Punt if size of access
-+ is different from TYPE_SIZE on v->value's type.
-+
-+2013-11-03 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2013-10-12 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/58690
-+ * config/i386/i386.c (ix86_copy_addr_to_reg): New function.
-+ (ix86_expand_movmem): Replace copy_addr_to_reg with
-+ ix86_copy_addr_to_reg.
-+ (ix86_expand_setmem): Likewise.
-+
-+2013-10-29 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-08-08 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ PR rtl-optimization/58079
-+ * combine.c (combine_simplify_rtx): Avoid using SUBST if
-+ simplify_comparison has widened a comparison with an integer.
-+
-+2013-10-29 Martin Jambor <mjambor@suse.cz>
-+
-+ PR middle-end/58789
-+ Backport from mainline
-+ 2013-05-09 Martin Jambor <mjambor@suse.cz>
-+
-+ PR lto/57084
-+ * gimple-fold.c (canonicalize_constructor_val): Call
-+ cgraph_get_create_real_symbol_node instead of cgraph_get_create_node.
-+
-+ Backport from mainline
-+ 2013-03-16 Jan Hubicka <jh@suse.cz>
-+
-+ * cgraph.h (cgraph_get_create_real_symbol_node): Declare.
-+ * cgraph.c (cgraph_get_create_real_symbol_node): New function.
-+ * cgrpahbuild.c: Use cgraph_get_create_real_symbol_node instead
-+ of cgraph_get_create_node.
-+ * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
-+
-+2013-10-28 Tom de Vries <tom@codesourcery.com>
-+
-+ * cfgexpand.c (gimple_expand_cfg): Remove test for parm_birth_insn.
-+ Don't commit insertions after NOTE_INSN_FUNCTION_BEG.
-+
-+2013-10-26 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-10-22 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/58779
-+ * config/i386/i386.c (put_condition_code) <case GTU, case LEU>:
-+ Remove CCCmode handling.
-+ <case LTU>: Return 'c' suffix for CCCmode.
-+ <case GEU>: Return 'nc' suffix for CCCmode.
-+ (ix86_cc_mode) <case GTU, case LEU>: Do not generate overflow checks.
-+ * config/i386/i386.md (*sub<mode>3_cconly_overflow): Remove.
-+ (*sub<mode>3_cc_overflow): Ditto.
-+ (*subsi3_zext_cc_overflow): Ditto.
-+
-+2013-10-26 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-10-19 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/58792
-+ * config/i386/i386.c (ix86_function_value_regno): Add DX_REG,
-+ ST1_REG and XMM1_REG for 32bit and 64bit targets. Also add DI_REG
-+ and SI_REG for 64bit SYSV ABI targets.
-+
-+2013-08-25 Richard Henderson <rth@twiddle.net>
-+
-+ PR rtl/58542
-+ * optabs.c (maybe_emit_atomic_exchange): Use create_input_operand
-+ instead of create_convert_operand_to.
-+ (maybe_emit_sync_lock_test_and_set): Likewise.
-+ (expand_atomic_compare_and_swap): Likewise.
-+ (maybe_emit_compare_and_swap_exchange_loop): Don't convert_modes.
-+
-+2013-10-25 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR rtl-optimization/58831
-+ * alias.c (init_alias_analysis): At the beginning of each iteration, set
-+ the reg_seen[N] bit if static_reg_base_value[N] is non-null.
-+
-+2013-10-25 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * recog.c (search_ofs): New static variable moved from...
-+ (peep2_find_free_register): ...here.
-+ (peephole2_optimize): Initialize it.
-+
-+2013-10-24 David Edelsohn <dje.gcc@gmail.com>
-+
-+ Backport from mainline
-+ 2013-10-23 David Edelsohn <dje.gcc@gmail.com>
-+
-+ PR target/58838
-+ * config/rs6000/rs6000.md (mulsi3_internal1 and splitter): Add
-+ TARGET_32BIT final condition.
-+ (mulsi3_internal2 and splitter): Same.
-+
-+2013-10-23 Tom de Vries <tom@codesourcery.com>
-+
-+ PR tree-optimization/58805
-+ * tree-ssa-tail-merge.c (stmt_local_def): Add gimple_vdef check.
-+
-+2013-10-23 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-06-24 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/57488
-+ * tree-ssa-pre.c (insert): Clear NEW sets before each iteration.
-+
-+2013-10-16 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
-+
-+ Backport from mainline
-+ 2013-10-16 Ganesh Gopalasubramanian
-+ <Ganesh.Gopalasubramanian@amd.com>
-+
-+ * config/i386/i386.c (ix86_option_override_internal): Enable FMA4
-+ for AMD bdver3.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-@@ -639,7 +6115,7 @@
- 2013-07-31 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- Backport from mainline
-- 2013-03-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+ 2013-03-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * config/s390/s390.h (TARGET_FLT_EVAL_METHOD): Define.
-
-Index: gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_thumb1_ok } */
-+/* { dg-options "-mthumb -fpic -msingle-pic-base" } */
-+
-+int g_test;
-+
-+int
-+foo (int par)
-+{
-+ g_test = par;
-+}
-Index: gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,25 @@
-+/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */
-+
-+/* Detect ICE in the case of unaligned memory address. */
-+
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+
-+unsigned char dummy_store[1000];
-+
-+void
-+foo (char* addr)
-+{
-+ uint8x16_t vdata = vld1q_u8 (addr);
-+ vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0);
-+}
-+
-+uint64_t
-+bar (uint64x2_t vdata)
-+{
-+ vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0);
-+ return vgetq_lane_u64 (vdata, 0);
-+}
-Index: gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_thumb1_ok } */
-+/* { dg-options "-mthumb -fpic -mpic-register=9" } */
-+
-+int g_test;
-+
-+int
-+foo (int par)
-+{
-+ g_test = par;
-+}
-Index: gcc/testsuite/gcc.target/arm/require-pic-register-loc.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* { dg-do compile } */
-+/* { dg-options "-g -fPIC" } */
-+
-+void *v;
-+void a (void *x) { }
-+void b (void) { }
-+ /* line 7. */
-+int /* line 8. */
-+main (int argc) /* line 9. */
-+{ /* line 10. */
-+ if (argc == 12345) /* line 11. */
-+ {
-+ a (v);
-+ return 1;
-+ }
-+ b ();
-+
-+ return 0;
-+}
-+
-+/* { dg-final { scan-assembler-not "\.loc 1 7 0" } } */
-+/* { dg-final { scan-assembler-not "\.loc 1 8 0" } } */
-+/* { dg-final { scan-assembler-not "\.loc 1 9 0" } } */
-+
-+/* The loc at the start of the prologue. */
-+/* { dg-final { scan-assembler-times "\.loc 1 10 0" 1 } } */
-+
-+/* The loc at the end of the prologue, with the first user line. */
-+/* { dg-final { scan-assembler-times "\.loc 1 11 0" 1 } } */
-Index: gcc/testsuite/gcc.target/arm/vrinta-ce.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/arm/vrinta-ce.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/arm/vrinta-ce.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_v8_vfp_ok } */
-+/* { dg-options "-O2 -marm -march=armv8-a" } */
-+/* { dg-add-options arm_v8_vfp } */
-+
-+double foo (double a)
-+{
-+ if (a > 3.0)
-+ return __builtin_round (a);
-+
-+ return 0.0;
-+}
-+
-+/* { dg-final { scan-assembler-times "vrinta.f64\td\[0-9\]+" 1 } } */
-+
-Index: gcc/testsuite/gcc.target/arm/pr54300.C
-===================================================================
---- a/src/gcc/testsuite/gcc.target/arm/pr54300.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/arm/pr54300.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,61 @@
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon } */
-+/* { dg-options "-O2" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include <arm_neon.h>
-+#include <stdlib.h>
-+
-+struct __attribute__ ((aligned(8))) _v16u8_ {
-+ uint8x16_t val;
-+ _v16u8_( const int16x8_t &src) { val = vreinterpretq_u8_s16(src); }
-+ operator int16x8_t () const { return vreinterpretq_s16_u8(val); }
-+};
-+typedef struct _v16u8_ v16u8;
-+
-+struct __attribute__ ((aligned(4))) _v8u8_ {
-+ uint8x8_t val;
-+ _v8u8_( const uint8x8_t &src) { val = src; }
-+ operator int16x4_t () const { return vreinterpret_s16_u8(val); }
-+};
-+typedef struct _v8u8_ v8u8;
-+
-+typedef v16u8 v8i16;
-+typedef int32x4_t v4i32;
-+typedef const short cv1i16;
-+typedef const unsigned char cv1u8;
-+typedef const v8i16 cv8i16;
-+
-+static inline __attribute__((always_inline)) v8u8 zero_64(){ return vdup_n_u8( 0 ); }
-+
-+static inline __attribute__((always_inline)) v8i16 loadlo_8i16( cv8i16* p ){
-+ return vcombine_s16( vld1_s16( (cv1i16 *)p ), zero_64() );
-+}
-+static inline __attribute__((always_inline)) v8i16 _loadlo_8i16( cv8i16* p, int offset ){
-+ return loadlo_8i16( (cv8i16*)(&((cv1u8*)p)[offset]) );
-+}
-+
-+void __attribute__((noinline))
-+test(unsigned short *_Inp, int32_t *_Out,
-+ unsigned int s1v, unsigned int dv0,
-+ unsigned int smask_v)
-+{
-+ int32x4_t c = vdupq_n_s32(0);
-+
-+ for(unsigned int sv=0 ; sv!=dv0 ; sv=(sv+s1v)&smask_v )
-+ {
-+ int32x4_t s;
-+ s = vmovl_s16( vget_low_s16( _loadlo_8i16( (cv8i16*) _Inp, sv ) ) );
-+ c = vaddq_s32( c, s );
-+ }
-+ vst1q_s32( _Out, c );
-+}
-+
-+main()
-+{
-+ unsigned short a[4] = {1, 2, 3, 4};
-+ int32_t b[4] = {0, 0, 0, 0};
-+ test(a, b, 1, 1, ~0);
-+ if (b[0] != 1 || b[1] != 2 || b[2] != 3 || b[3] != 4)
-+ abort();
-+}
-Index: gcc/testsuite/gcc.target/arm/pr59826.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/arm/pr59826.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/arm/pr59826.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,35 @@
-+/* { dg-do compile } */
-+/* { dg-options "-mthumb -mcpu=cortex-m4 -fprefetch-loop-arrays -O2" } */
-+
-+typedef struct genxWriter_rec * genxWriter;
-+typedef unsigned char * utf8;
-+typedef const unsigned char * constUtf8;
-+
-+int genxScrubText(genxWriter w, constUtf8 in, utf8 out)
-+{
-+ int problems = 0;
-+ constUtf8 last = in;
-+
-+ while (*in)
-+ {
-+ int c = genxNextUnicodeChar(&in);
-+ if (c == -1)
-+ {
-+ problems++;
-+ last = in;
-+ continue;
-+ }
-+
-+ if (!isXMLChar(w, c))
-+ {
-+ problems++;
-+ last = in;
-+ continue;
-+ }
-+
-+ while (last < in)
-+ *out++ = *last++;
-+ }
-+ *out = 0;
-+ return problems;
-+}
-Index: gcc/testsuite/gcc.target/arm/pr57637.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/arm/pr57637.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/arm/pr57637.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,206 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fno-inline" } */
-+
-+typedef struct _GtkCssStyleProperty GtkCssStyleProperty;
-+
-+struct _GtkCssStyleProperty
-+{
-+ int *initial_value;
-+ unsigned int id;
-+ unsigned int inherit :1;
-+ unsigned int animated :1;
-+ unsigned int affects_size :1;
-+ unsigned int affects_font :1;
-+
-+ int * parse_value;
-+ int * query_value;
-+ int * assign_value;
-+};
-+
-+void
-+g_assertion_message_expr (const char *domain,
-+ const char *file,
-+ int line,
-+ const char *func,
-+ const char *expr) __attribute__((__noreturn__));
-+
-+void
-+g_assertion_message_expr (const char *domain,
-+ const char *file,
-+ int line,
-+ const char *func,
-+ const char *expr)
-+{
-+ __builtin_abort ();
-+}
-+int
-+get_id (GtkCssStyleProperty *property)
-+{
-+ return 1;
-+}
-+int
-+_gtk_css_style_property_get_type ()
-+{
-+ return 1;
-+}
-+
-+GtkCssStyleProperty *
-+g_object_new (int object_type,
-+ const char *first_property_name,
-+ ...)
-+{
-+ return (GtkCssStyleProperty *) __builtin_malloc (sizeof (GtkCssStyleProperty));
-+}
-+
-+typedef enum {
-+ INHERIT = (1 << 0),
-+ ANIMATED = (1 << 1),
-+ RESIZE = (1 << 2),
-+ FONT = (1 << 3)
-+} GtkStylePropertyFlags;
-+
-+int t = 0;
-+void
-+gtk_css_style_property_register (const char * name,
-+ int expected_id,
-+ int value_type,
-+ int flags,
-+ int *parse_value,
-+ int *query_value,
-+ int *assign_value,
-+ int *initial_value)
-+{
-+ GtkCssStyleProperty *node;
-+
-+ do
-+ {
-+ if (__builtin_expect (__extension__ (
-+ {
-+ int _g_boolean_var_;
-+ if (initial_value != ((void *)0))
-+ _g_boolean_var_ = 1;
-+ else
-+ _g_boolean_var_ = 0;
-+ _g_boolean_var_;
-+ }),
-+ 1))
-+ ;
-+ else
-+ g_assertion_message_expr ("Gtk",
-+ "gtkcssstylepropertyimpl.c",
-+ 85,
-+ ((const char*) (__PRETTY_FUNCTION__)),
-+ "initial_value != NULL");
-+ } while (0);
-+
-+ do
-+ {
-+ if (__builtin_expect (__extension__ (
-+ {
-+ int _g_boolean_var_;
-+ if (parse_value != ((void *)0))
-+ _g_boolean_var_ = 1;
-+ else
-+ _g_boolean_var_ = 0;
-+ _g_boolean_var_;
-+ }),
-+ 1))
-+ ;
-+ else
-+ g_assertion_message_expr ("Gtk",
-+ "gtkcssstylepropertyimpl.c",
-+ 86,
-+ ((const char*) (__PRETTY_FUNCTION__)),
-+ "parse_value != NULL");
-+ } while (0);
-+
-+ do
-+ {
-+ if (__builtin_expect (__extension__ (
-+ {
-+ int _g_boolean_var_;
-+ if (value_type == ((int) ((1) << (2)))
-+ || query_value != ((void *)0))
-+ _g_boolean_var_ = 1;
-+ else
-+ _g_boolean_var_ = 0;
-+ _g_boolean_var_;
-+ }),
-+ 1))
-+ ;
-+ else
-+ g_assertion_message_expr ("Gtk",
-+ "gtkcssstylepropertyimpl.c",
-+ 87, ((const char*) (__PRETTY_FUNCTION__)),
-+ "value_type == NONE || query_value != NULL");
-+ } while (0);
-+
-+ /* FLAGS is changed in a cond_exec instruction with pr57637. */
-+ if (flags == 15)
-+ t = 15;
-+
-+ do
-+ {
-+ if (__builtin_expect (__extension__ (
-+ {
-+ int _g_boolean_var_;
-+ if (value_type == ((1) << (2))
-+ || assign_value != ((void *)0))
-+ _g_boolean_var_ = 1;
-+ else
-+ _g_boolean_var_ = 0;
-+ _g_boolean_var_;
-+ }),
-+ 1))
-+ ;
-+ else
-+ g_assertion_message_expr ("Gtk",
-+ "gtkcssstylepropertyimpl.c",
-+ 88, ((const char*) (__PRETTY_FUNCTION__)),
-+ "value_type == NONE || assign_value != NULL");
-+ } while (0);
-+
-+ node = g_object_new ((_gtk_css_style_property_get_type ()),
-+ "value-type", value_type,
-+ "affects-size", (flags & RESIZE) ? (0) : (!(0)),
-+ "affects-font", (flags & FONT) ? (!(0)) : (0),
-+ "animated", (flags & ANIMATED) ? (!(0)) : (0),
-+ "inherit", (flags & INHERIT) ? (!(0)) : (0),
-+ "initial-value", initial_value,
-+ "name", name,
-+ ((void *)0));
-+
-+ node->parse_value = parse_value;
-+ node->query_value = query_value;
-+ node->assign_value = assign_value;
-+
-+ do
-+ {
-+ if (__builtin_expect (__extension__ (
-+ {
-+ int _g_boolean_var_;
-+ if (get_id (node) == expected_id)
-+ _g_boolean_var_ = 1;
-+ else
-+ _g_boolean_var_ = 0;
-+ _g_boolean_var_;
-+ }),
-+ 1))
-+ ;
-+ else
-+ g_assertion_message_expr ("Gtk",
-+ "gtkcssstylepropertyimpl.c",
-+ 106,
-+ ((const char*) (__PRETTY_FUNCTION__)),
-+ "get_id (node) == expected_id");
-+ } while (0);
-+}
-+
-+int main ()
-+{
-+ gtk_css_style_property_register ("test", 1, 4, 15, &t, &t, &t, &t);
-+
-+ if (t != 15)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/ppc-target-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c (.../branches/gcc-4_8-branch)
-@@ -5,8 +5,7 @@
- /* { dg-final { scan-assembler-times "fabs" 3 } } */
- /* { dg-final { scan-assembler-times "fnabs" 3 } } */
- /* { dg-final { scan-assembler-times "fsel" 3 } } */
--/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */
--/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */
-+/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */
-
- /* fabs/fnabs/fsel */
- double normal1 (double a, double b) { return __builtin_copysign (a, b); }
-Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,88 @@
-+/* { dg-do compile { target { powerpc*-*-linux* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-mcpu=power7 -O2" } */
-+/* { dg-final { scan-assembler-times "ddedpd " 4 } } */
-+/* { dg-final { scan-assembler-times "denbcd " 2 } } */
-+/* { dg-final { scan-assembler-times "dxex " 1 } } */
-+/* { dg-final { scan-assembler-times "diex " 1 } } */
-+/* { dg-final { scan-assembler-times "dscli " 2 } } */
-+/* { dg-final { scan-assembler-times "dscri " 2 } } */
-+/* { dg-final { scan-assembler-not "bl __builtin" } } */
-+/* { dg-final { scan-assembler-not "dctqpq" } } */
-+/* { dg-final { scan-assembler-not "drdpq" } } */
-+/* { dg-final { scan-assembler-not "stfd" } } */
-+/* { dg-final { scan-assembler-not "lfd" } } */
-+
-+_Decimal64
-+do_dedpd_0 (_Decimal64 a)
-+{
-+ return __builtin_ddedpd (0, a);
-+}
-+
-+_Decimal64
-+do_dedpd_1 (_Decimal64 a)
-+{
-+ return __builtin_ddedpd (1, a);
-+}
-+
-+_Decimal64
-+do_dedpd_2 (_Decimal64 a)
-+{
-+ return __builtin_ddedpd (2, a);
-+}
-+
-+_Decimal64
-+do_dedpd_3 (_Decimal64 a)
-+{
-+ return __builtin_ddedpd (3, a);
-+}
-+
-+_Decimal64
-+do_enbcd_0 (_Decimal64 a)
-+{
-+ return __builtin_denbcd (0, a);
-+}
-+
-+_Decimal64
-+do_enbcd_1 (_Decimal64 a)
-+{
-+ return __builtin_denbcd (1, a);
-+}
-+
-+_Decimal64
-+do_xex (_Decimal64 a)
-+{
-+ return __builtin_dxex (a);
-+}
-+
-+_Decimal64
-+do_iex (_Decimal64 a, _Decimal64 b)
-+{
-+ return __builtin_diex (a, b);
-+}
-+
-+_Decimal64
-+do_scli_1 (_Decimal64 a)
-+{
-+ return __builtin_dscli (a, 1);
-+}
-+
-+_Decimal64
-+do_scli_10 (_Decimal64 a)
-+{
-+ return __builtin_dscli (a, 10);
-+}
-+
-+_Decimal64
-+do_scri_1 (_Decimal64 a)
-+{
-+ return __builtin_dscri (a, 1);
-+}
-+
-+_Decimal64
-+do_scri_10 (_Decimal64 a)
-+{
-+ return __builtin_dscri (a, 10);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,65 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */
-+
-+#ifndef TYPE
-+#define TYPE long long
-+#endif
-+
-+#ifndef SIGN_TYPE
-+#define SIGN_TYPE signed TYPE
-+#endif
-+
-+#ifndef UNS_TYPE
-+#define UNS_TYPE unsigned TYPE
-+#endif
-+
-+typedef vector SIGN_TYPE v_sign;
-+typedef vector UNS_TYPE v_uns;
-+
-+v_sign sign_add (v_sign a, v_sign b)
-+{
-+ return a + b;
-+}
-+
-+v_sign sign_sub (v_sign a, v_sign b)
-+{
-+ return a - b;
-+}
-+
-+v_sign sign_shift_left (v_sign a, v_sign b)
-+{
-+ return a << b;
-+}
-+
-+v_sign sign_shift_right (v_sign a, v_sign b)
-+{
-+ return a >> b;
-+}
-+
-+v_uns uns_add (v_uns a, v_uns b)
-+{
-+ return a + b;
-+}
-+
-+v_uns uns_sub (v_uns a, v_uns b)
-+{
-+ return a - b;
-+}
-+
-+v_uns uns_shift_left (v_uns a, v_uns b)
-+{
-+ return a << b;
-+}
-+
-+v_uns uns_shift_right (v_uns a, v_uns b)
-+{
-+ return a >> b;
-+}
-+
-+/* { dg-final { scan-assembler-times "vaddudm" 2 } } */
-+/* { dg-final { scan-assembler-times "vsubudm" 2 } } */
-+/* { dg-final { scan-assembler-times "vsld" 2 } } */
-+/* { dg-final { scan-assembler-times "vsrad" 1 } } */
-+/* { dg-final { scan-assembler-times "vsrd" 1 } } */
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,200 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */
-+
-+#ifndef SIZE
-+#define SIZE 1024
-+#endif
-+
-+#ifndef ALIGN
-+#define ALIGN 32
-+#endif
-+
-+#ifndef TYPE
-+#define TYPE long long
-+#endif
-+
-+#ifndef SIGN_TYPE
-+#define SIGN_TYPE signed TYPE
-+#endif
-+
-+#ifndef UNS_TYPE
-+#define UNS_TYPE unsigned TYPE
-+#endif
-+
-+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
-+
-+SIGN_TYPE sa[SIZE] ALIGN_ATTR;
-+SIGN_TYPE sb[SIZE] ALIGN_ATTR;
-+SIGN_TYPE sc[SIZE] ALIGN_ATTR;
-+
-+UNS_TYPE ua[SIZE] ALIGN_ATTR;
-+UNS_TYPE ub[SIZE] ALIGN_ATTR;
-+UNS_TYPE uc[SIZE] ALIGN_ATTR;
-+
-+void
-+sign_add (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sa[i] = sb[i] + sc[i];
-+}
-+
-+void
-+sign_sub (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sa[i] = sb[i] - sc[i];
-+}
-+
-+void
-+sign_shift_left (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sa[i] = sb[i] << sc[i];
-+}
-+
-+void
-+sign_shift_right (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sa[i] = sb[i] >> sc[i];
-+}
-+
-+void
-+sign_max (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sa[i] = (sb[i] > sc[i]) ? sb[i] : sc[i];
-+}
-+
-+void
-+sign_min (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sa[i] = (sb[i] < sc[i]) ? sb[i] : sc[i];
-+}
-+
-+void
-+sign_abs (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sa[i] = (sb[i] < 0) ? -sb[i] : sb[i]; /* xor, vsubudm, vmaxsd. */
-+}
-+
-+void
-+sign_eq (SIGN_TYPE val1, SIGN_TYPE val2)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sa[i] = (sb[i] == sc[i]) ? val1 : val2;
-+}
-+
-+void
-+sign_lt (SIGN_TYPE val1, SIGN_TYPE val2)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sa[i] = (sb[i] < sc[i]) ? val1 : val2;
-+}
-+
-+void
-+uns_add (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ ua[i] = ub[i] + uc[i];
-+}
-+
-+void
-+uns_sub (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ ua[i] = ub[i] - uc[i];
-+}
-+
-+void
-+uns_shift_left (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ ua[i] = ub[i] << uc[i];
-+}
-+
-+void
-+uns_shift_right (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ ua[i] = ub[i] >> uc[i];
-+}
-+
-+void
-+uns_max (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ ua[i] = (ub[i] > uc[i]) ? ub[i] : uc[i];
-+}
-+
-+void
-+uns_min (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ ua[i] = (ub[i] < uc[i]) ? ub[i] : uc[i];
-+}
-+
-+void
-+uns_eq (UNS_TYPE val1, UNS_TYPE val2)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ ua[i] = (ub[i] == uc[i]) ? val1 : val2;
-+}
-+
-+void
-+uns_lt (UNS_TYPE val1, UNS_TYPE val2)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ ua[i] = (ub[i] < uc[i]) ? val1 : val2;
-+}
-+
-+/* { dg-final { scan-assembler-times "\[\t \]vaddudm\[\t \]" 2 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vsubudm\[\t \]" 3 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vmaxsd\[\t \]" 2 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vmaxud\[\t \]" 1 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vminsd\[\t \]" 1 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vminud\[\t \]" 1 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vsld\[\t \]" 2 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vsrad\[\t \]" 1 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vsrd\[\t \]" 1 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vcmpequd\[\t \]" 2 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vcmpgtsd\[\t \]" 1 } } */
-+/* { dg-final { scan-assembler-times "\[\t \]vcmpgtud\[\t \]" 1 } } */
-Index: gcc/testsuite/gcc.target/powerpc/pr57744.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr57744.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr57744.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,39 @@
-+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O3" } */
-+
-+void abort (void);
-+
-+typedef unsigned U_16 __attribute__((mode(TI)));
-+
-+extern int libat_compare_exchange_16 (U_16 *, U_16 *, U_16, int, int)
-+ __attribute__((__noinline__));
-+
-+/* PR 57744: lqarx/stqcx needs even/odd register pairs. The assembler will
-+ complain if the compiler gets an odd/even register pair. Create a function
-+ which has the 16 byte compare and exchange instructions, but don't actually
-+ execute it, so that we can detect these failures on older machines. */
-+
-+int
-+libat_compare_exchange_16 (U_16 *mptr, U_16 *eptr, U_16 newval,
-+ int smodel, int fmodel __attribute__((unused)))
-+{
-+ if (((smodel) == 0))
-+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 0, 0);
-+ else if (((smodel) != 5))
-+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 4, 0);
-+ else
-+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 5, 0);
-+}
-+
-+U_16 a = 1, b = 1, c = -2;
-+volatile int do_test = 0;
-+
-+int main (void)
-+{
-+ if (do_test && !libat_compare_exchange_16 (&a, &b, c, 0, 0))
-+ abort ();
-+
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/recip-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/recip-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-1.c (.../branches/gcc-4_8-branch)
-@@ -3,8 +3,8 @@
- /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power6" } */
- /* { dg-final { scan-assembler-times "frsqrte" 2 } } */
- /* { dg-final { scan-assembler-times "fmsub" 2 } } */
--/* { dg-final { scan-assembler-times "fmul" 8 } } */
--/* { dg-final { scan-assembler-times "fnmsub" 4 } } */
-+/* { dg-final { scan-assembler-times "fmul" 6 } } */
-+/* { dg-final { scan-assembler-times "fnmsub" 3 } } */
-
- double
- rsqrt_d (double a)
-Index: gcc/testsuite/gcc.target/powerpc/darwin-longlong.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c (.../branches/gcc-4_8-branch)
-@@ -11,7 +11,11 @@
- int i[2];
- } ud;
- ud.ll = in;
-+#ifdef __LITTLE_ENDIAN__
-+ return ud.i[1];
-+#else
- return ud.i[0];
-+#endif
- }
-
- int main()
-Index: gcc/testsuite/gcc.target/powerpc/bool2-p8.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,32 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-O2 -mcpu=power8" } */
-+/* { dg-final { scan-assembler-not "\[ \t\]and " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]or " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxland " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxleqv " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlorc " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlnand " } } */
-+
-+#ifndef TYPE
-+typedef int v4si __attribute__ ((vector_size (16)));
-+#define TYPE v4si
-+#endif
-+
-+#include "bool2.h"
-Index: gcc/testsuite/gcc.target/powerpc/mmfpgpr.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-O2 -mcpu=power6x -mmfpgpr" } */
-+/* { dg-final { scan-assembler "mffgpr" } } */
-+/* { dg-final { scan-assembler "mftgpr" } } */
-+
-+/* Test that we generate the instructions to move between the GPR and FPR
-+ registers under power6x. */
-+
-+extern long return_long (void);
-+extern double return_double (void);
-+
-+double return_double2 (void)
-+{
-+ return (double) return_long ();
-+}
-+
-+long return_long2 (void)
-+{
-+ return (long) return_double ();
-+}
-Index: gcc/testsuite/gcc.target/powerpc/pr60203.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr60203.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr60203.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,40 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O3" } */
-+
-+union u_ld { long double ld; double d[2]; };
-+
-+long double
-+pack (double a, double aa)
-+{
-+ union u_ld u;
-+ u.d[0] = a;
-+ u.d[1] = aa;
-+ return u.ld;
-+}
-+
-+double
-+unpack_0 (long double x)
-+{
-+ union u_ld u;
-+ u.ld = x;
-+ return u.d[0];
-+}
-+
-+double
-+unpack_1 (long double x)
-+{
-+ union u_ld u;
-+ u.ld = x;
-+ return u.d[1];
-+}
-+
-+/* { dg-final { scan-assembler-not "stfd" } } */
-+/* { dg-final { scan-assembler-not "lfd" } } */
-+/* { dg-final { scan-assembler-not "lxsdx" } } */
-+/* { dg-final { scan-assembler-not "stxsdx" } } */
-+/* { dg-final { scan-assembler-not "mfvsrd" } } */
-+/* { dg-final { scan-assembler-not "mtvsrd" } } */
-+
-+
-Index: gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+/* { dg-final { scan-assembler "mtvsrd" } } */
-+/* { dg-final { scan-assembler "mfvsrd" } } */
-+
-+/* Check code generation for direct move for vector types. */
-+
-+#define TYPE vector int
-+#define VSX_REG_ATTR "wa"
-+
-+#include "direct-move.h"
-Index: gcc/testsuite/gcc.target/powerpc/bool2-av.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,32 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_altivec_ok } */
-+/* { dg-options "-O2 -mcpu=power6 -maltivec" } */
-+/* { dg-final { scan-assembler-not "\[ \t\]and " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]or " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */
-+/* { dg-final { scan-assembler "\[ \t\]vand " } } */
-+/* { dg-final { scan-assembler "\[ \t\]vandc " } } */
-+/* { dg-final { scan-assembler "\[ \t\]vor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]vxor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]vnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
-+
-+#ifndef TYPE
-+typedef int v4si __attribute__ ((vector_size (16)));
-+#define TYPE v4si
-+#endif
-+
-+#include "bool2.h"
-Index: gcc/testsuite/gcc.target/powerpc/pr43154.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr43154.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr43154.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,6 @@
- /* { dg-do compile { target { powerpc*-*-* } } } */
- /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */
- /* { dg-require-effective-target powerpc_vsx_ok } */
- /* { dg-options "-O2 -mcpu=power7" } */
-
-Index: gcc/testsuite/gcc.target/powerpc/pr59054.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr59054.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr59054.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,9 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-mcpu=power7 -O0 -m64" } */
-+
-+long foo (void) { return 0; }
-+
-+/* { dg-final { scan-assembler-not "xxlor" } } */
-+/* { dg-final { scan-assembler-not "stfd" } } */
-Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,88 @@
-+/* { dg-do compile { target { powerpc*-*-linux* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-mcpu=power7 -O2" } */
-+/* { dg-final { scan-assembler-times "ddedpdq " 4 } } */
-+/* { dg-final { scan-assembler-times "denbcdq " 2 } } */
-+/* { dg-final { scan-assembler-times "dxexq " 1 } } */
-+/* { dg-final { scan-assembler-times "diexq " 1 } } */
-+/* { dg-final { scan-assembler-times "dscliq " 2 } } */
-+/* { dg-final { scan-assembler-times "dscriq " 2 } } */
-+/* { dg-final { scan-assembler-not "bl __builtin" } } */
-+/* { dg-final { scan-assembler-not "dctqpq" } } */
-+/* { dg-final { scan-assembler-not "drdpq" } } */
-+/* { dg-final { scan-assembler-not "stfd" } } */
-+/* { dg-final { scan-assembler-not "lfd" } } */
-+
-+_Decimal128
-+do_dedpdq_0 (_Decimal128 a)
-+{
-+ return __builtin_ddedpdq (0, a);
-+}
-+
-+_Decimal128
-+do_dedpdq_1 (_Decimal128 a)
-+{
-+ return __builtin_ddedpdq (1, a);
-+}
-+
-+_Decimal128
-+do_dedpdq_2 (_Decimal128 a)
-+{
-+ return __builtin_ddedpdq (2, a);
-+}
-+
-+_Decimal128
-+do_dedpdq_3 (_Decimal128 a)
-+{
-+ return __builtin_ddedpdq (3, a);
-+}
-+
-+_Decimal128
-+do_enbcdq_0 (_Decimal128 a)
-+{
-+ return __builtin_denbcdq (0, a);
-+}
-+
-+_Decimal128
-+do_enbcdq_1 (_Decimal128 a)
-+{
-+ return __builtin_denbcdq (1, a);
-+}
-+
-+_Decimal128
-+do_xexq (_Decimal128 a)
-+{
-+ return __builtin_dxexq (a);
-+}
-+
-+_Decimal128
-+do_iexq (_Decimal128 a, _Decimal128 b)
-+{
-+ return __builtin_diexq (a, b);
-+}
-+
-+_Decimal128
-+do_scliq_1 (_Decimal128 a)
-+{
-+ return __builtin_dscliq (a, 1);
-+}
-+
-+_Decimal128
-+do_scliq_10 (_Decimal128 a)
-+{
-+ return __builtin_dscliq (a, 10);
-+}
-+
-+_Decimal128
-+do_scriq_1 (_Decimal128 a)
-+{
-+ return __builtin_dscriq (a, 1);
-+}
-+
-+_Decimal128
-+do_scriq_10 (_Decimal128 a)
-+{
-+ return __builtin_dscriq (a, 10);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,204 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */
-+
-+#include <altivec.h>
-+
-+typedef vector long long v_sign;
-+typedef vector unsigned long long v_uns;
-+typedef vector bool long long v_bool;
-+
-+v_sign sign_add_1 (v_sign a, v_sign b)
-+{
-+ return __builtin_altivec_vaddudm (a, b);
-+}
-+
-+v_sign sign_add_2 (v_sign a, v_sign b)
-+{
-+ return vec_add (a, b);
-+}
-+
-+v_sign sign_add_3 (v_sign a, v_sign b)
-+{
-+ return vec_vaddudm (a, b);
-+}
-+
-+v_sign sign_sub_1 (v_sign a, v_sign b)
-+{
-+ return __builtin_altivec_vsubudm (a, b);
-+}
-+
-+v_sign sign_sub_2 (v_sign a, v_sign b)
-+{
-+ return vec_sub (a, b);
-+}
-+
-+
-+v_sign sign_sub_3 (v_sign a, v_sign b)
-+{
-+ return vec_vsubudm (a, b);
-+}
-+
-+v_sign sign_min_1 (v_sign a, v_sign b)
-+{
-+ return __builtin_altivec_vminsd (a, b);
-+}
-+
-+v_sign sign_min_2 (v_sign a, v_sign b)
-+{
-+ return vec_min (a, b);
-+}
-+
-+v_sign sign_min_3 (v_sign a, v_sign b)
-+{
-+ return vec_vminsd (a, b);
-+}
-+
-+v_sign sign_max_1 (v_sign a, v_sign b)
-+{
-+ return __builtin_altivec_vmaxsd (a, b);
-+}
-+
-+v_sign sign_max_2 (v_sign a, v_sign b)
-+{
-+ return vec_max (a, b);
-+}
-+
-+v_sign sign_max_3 (v_sign a, v_sign b)
-+{
-+ return vec_vmaxsd (a, b);
-+}
-+
-+v_sign sign_abs (v_sign a)
-+{
-+ return vec_abs (a); /* xor, vsubudm, vmaxsd. */
-+}
-+
-+v_bool sign_eq (v_sign a, v_sign b)
-+{
-+ return vec_cmpeq (a, b);
-+}
-+
-+v_bool sign_lt (v_sign a, v_sign b)
-+{
-+ return vec_cmplt (a, b);
-+}
-+
-+v_uns uns_add_2 (v_uns a, v_uns b)
-+{
-+ return vec_add (a, b);
-+}
-+
-+v_uns uns_add_3 (v_uns a, v_uns b)
-+{
-+ return vec_vaddudm (a, b);
-+}
-+
-+v_uns uns_sub_2 (v_uns a, v_uns b)
-+{
-+ return vec_sub (a, b);
-+}
-+
-+v_uns uns_sub_3 (v_uns a, v_uns b)
-+{
-+ return vec_vsubudm (a, b);
-+}
-+
-+v_uns uns_min_2 (v_uns a, v_uns b)
-+{
-+ return vec_min (a, b);
-+}
-+
-+v_uns uns_min_3 (v_uns a, v_uns b)
-+{
-+ return vec_vminud (a, b);
-+}
-+
-+v_uns uns_max_2 (v_uns a, v_uns b)
-+{
-+ return vec_max (a, b);
-+}
-+
-+v_uns uns_max_3 (v_uns a, v_uns b)
-+{
-+ return vec_vmaxud (a, b);
-+}
-+
-+v_bool uns_eq (v_uns a, v_uns b)
-+{
-+ return vec_cmpeq (a, b);
-+}
-+
-+v_bool uns_lt (v_uns a, v_uns b)
-+{
-+ return vec_cmplt (a, b);
-+}
-+
-+v_sign sign_rl_1 (v_sign a, v_sign b)
-+{
-+ return __builtin_altivec_vrld (a, b);
-+}
-+
-+v_sign sign_rl_2 (v_sign a, v_uns b)
-+{
-+ return vec_rl (a, b);
-+}
-+
-+v_uns uns_rl_2 (v_uns a, v_uns b)
-+{
-+ return vec_rl (a, b);
-+}
-+
-+v_sign sign_sl_1 (v_sign a, v_sign b)
-+{
-+ return __builtin_altivec_vsld (a, b);
-+}
-+
-+v_sign sign_sl_2 (v_sign a, v_uns b)
-+{
-+ return vec_sl (a, b);
-+}
-+
-+v_sign sign_sl_3 (v_sign a, v_uns b)
-+{
-+ return vec_vsld (a, b);
-+}
-+
-+v_uns uns_sl_2 (v_uns a, v_uns b)
-+{
-+ return vec_sl (a, b);
-+}
-+
-+v_uns uns_sl_3 (v_uns a, v_uns b)
-+{
-+ return vec_vsld (a, b);
-+}
-+
-+v_sign sign_sra_1 (v_sign a, v_sign b)
-+{
-+ return __builtin_altivec_vsrad (a, b);
-+}
-+
-+v_sign sign_sra_2 (v_sign a, v_uns b)
-+{
-+ return vec_sra (a, b);
-+}
-+
-+v_sign sign_sra_3 (v_sign a, v_uns b)
-+{
-+ return vec_vsrad (a, b);
-+}
-+
-+/* { dg-final { scan-assembler-times "vaddudm" 5 } } */
-+/* { dg-final { scan-assembler-times "vsubudm" 6 } } */
-+/* { dg-final { scan-assembler-times "vmaxsd" 4 } } */
-+/* { dg-final { scan-assembler-times "vminsd" 3 } } */
-+/* { dg-final { scan-assembler-times "vmaxud" 2 } } */
-+/* { dg-final { scan-assembler-times "vminud" 2 } } */
-+/* { dg-final { scan-assembler-times "vcmpequd" 2 } } */
-+/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */
-+/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */
-+/* { dg-final { scan-assembler-times "vrld" 3 } } */
-+/* { dg-final { scan-assembler-times "vsld" 5 } } */
-+/* { dg-final { scan-assembler-times "vsrad" 3 } } */
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,30 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */
-+
-+#include <stddef.h>
-+
-+#ifndef SIZE
-+#define SIZE 1024
-+#endif
-+
-+#ifndef ALIGN
-+#define ALIGN 32
-+#endif
-+
-+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
-+
-+long long sign_ll[SIZE] ALIGN_ATTR;
-+int sign_i [SIZE] ALIGN_ATTR;
-+
-+void copy_int_to_long_long (void)
-+{
-+ size_t i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sign_ll[i] = sign_i[i];
-+}
-+
-+/* { dg-final { scan-assembler "vupkhsw" } } */
-+/* { dg-final { scan-assembler "vupklsw" } } */
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,27 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-O3 -mcpu=power8" } */
-+/* { dg-final { scan-assembler "vbpermq" } } */
-+/* { dg-final { scan-assembler "mfvsrd" } } */
-+/* { dg-final { scan-assembler-not "stfd" } } */
-+/* { dg-final { scan-assembler-not "stxvd2x" } } */
-+
-+#include <altivec.h>
-+
-+#if __LITTLE_ENDIAN__
-+#define OFFSET 1
-+#else
-+#define OFFSET 0
-+#endif
-+
-+long foos (vector signed char a, vector signed char b)
-+{
-+ return vec_extract (vec_vbpermq (a, b), OFFSET);
-+}
-+
-+long foou (vector unsigned char a, vector unsigned char b)
-+{
-+ return vec_extract (vec_vbpermq (a, b), OFFSET);
-+}
-+
-Index: gcc/testsuite/gcc.target/powerpc/bcd-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,27 @@
-+/* { dg-do compile { target { powerpc*-*-linux* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-mcpu=power7 -O2" } */
-+/* { dg-final { scan-assembler-times "cdtbcd " 1 } } */
-+/* { dg-final { scan-assembler-times "cbcdtd " 1 } } */
-+/* { dg-final { scan-assembler-times "addg6s " 1 } } */
-+/* { dg-final { scan-assembler-not "bl __builtin" } } */
-+
-+unsigned int
-+to_bcd (unsigned int a)
-+{
-+ return __builtin_cdtbcd (a);
-+}
-+
-+unsigned int
-+from_bcd (unsigned int a)
-+{
-+ return __builtin_cbcdtd (a);
-+}
-+
-+unsigned int
-+bcd_arith (unsigned int a, unsigned int b)
-+{
-+ return __builtin_addg6s (a, b);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/pr60735.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr60735.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr60735.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-options "-mcpu=8548 -mspe -mabi=spe -O2" } */
-+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
-+
-+/* In PR60735, the type _Decimal64 generated an insn not found message. */
-+
-+void
-+pr60735 (_Decimal64 *p, _Decimal64 *q)
-+{
-+ *p = *q;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/extend-divide-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,34 @@
-+/* { dg-do compile { target { powerpc*-*-linux* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-mcpu=power7 -O2" } */
-+/* { dg-final { scan-assembler-times "divwe " 1 } } */
-+/* { dg-final { scan-assembler-times "divweo " 1 } } */
-+/* { dg-final { scan-assembler-times "divweu " 1 } } */
-+/* { dg-final { scan-assembler-times "divweuo " 1 } } */
-+/* { dg-final { scan-assembler-not "bl __builtin" } } */
-+
-+int
-+div_we (int a, int b)
-+{
-+ return __builtin_divwe (a, b);
-+}
-+
-+int
-+div_weo (int a, int b)
-+{
-+ return __builtin_divweo (a, b);
-+}
-+
-+unsigned int
-+div_weu (unsigned int a, unsigned int b)
-+{
-+ return __builtin_divweu (a, b);
-+}
-+
-+unsigned int
-+div_weuo (unsigned int a, unsigned int b)
-+{
-+ return __builtin_divweuo (a, b);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,23 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target powerpc_altivec_ok } */
-+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */
-+/* { dg-options "-O -maltivec -mno-vsx" } */
-+
-+typedef unsigned char V __attribute__((vector_size(16)));
-+
-+V p2(V x, V y)
-+{
-+ return __builtin_shuffle(x, y,
-+ (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 });
-+
-+}
-+
-+V p4(V x, V y)
-+{
-+ return __builtin_shuffle(x, y,
-+ (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 });
-+}
-+
-+/* { dg-final { scan-assembler-not "vperm" } } */
-+/* { dg-final { scan-assembler "vpkuhum" } } */
-+/* { dg-final { scan-assembler "vpkuwum" } } */
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,85 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */
-+
-+#include <altivec.h>
-+
-+#ifndef TYPE
-+#define TYPE vector __int128_t
-+#endif
-+
-+TYPE
-+do_addcuq (TYPE p, TYPE q)
-+{
-+ return __builtin_vec_vaddcuq (p, q);
-+}
-+
-+TYPE
-+do_adduqm (TYPE p, TYPE q)
-+{
-+ return __builtin_vec_add (p, q);
-+}
-+
-+TYPE
-+do_addeuqm (TYPE p, TYPE q, TYPE r)
-+{
-+ return __builtin_vec_vaddeuqm (p, q, r);
-+}
-+
-+TYPE
-+do_addecuq (TYPE p, TYPE q, TYPE r)
-+{
-+ return __builtin_vec_vaddecuq (p, q, r);
-+}
-+
-+TYPE
-+do_subeuqm (TYPE p, TYPE q, TYPE r)
-+{
-+ return __builtin_vec_vsubeuqm (p, q, r);
-+}
-+
-+TYPE
-+do_subecuq (TYPE p, TYPE q, TYPE r)
-+{
-+ return __builtin_vec_vsubecuq (p, q, r);
-+}
-+
-+TYPE
-+do_subcuq (TYPE p, TYPE q)
-+{
-+ return __builtin_vec_vsubcuq (p, q);
-+}
-+
-+TYPE
-+do_subuqm (TYPE p, TYPE q)
-+{
-+ return __builtin_vec_vsubuqm (p, q);
-+}
-+
-+TYPE
-+do_zero (void)
-+{
-+ return (TYPE) { 0 };
-+}
-+
-+TYPE
-+do_minus_one (void)
-+{
-+ return (TYPE) { -1 };
-+}
-+
-+/* { dg-final { scan-assembler "vaddcuq" } } */
-+/* { dg-final { scan-assembler "vadduqm" } } */
-+/* { dg-final { scan-assembler "vaddecuq" } } */
-+/* { dg-final { scan-assembler "vaddeuqm" } } */
-+/* { dg-final { scan-assembler "vsubecuq" } } */
-+/* { dg-final { scan-assembler "vsubeuqm" } } */
-+/* { dg-final { scan-assembler "vsubcuq" } } */
-+/* { dg-final { scan-assembler "vsubuqm" } } */
-+/* { dg-final { scan-assembler-not "mtvsrd" } } */
-+/* { dg-final { scan-assembler-not "mfvsrd" } } */
-+/* { dg-final { scan-assembler-not "ori 2,2,0" } } */
-+/* { dg-final { scan-assembler-not "xxpermdi" } } */
-+/* { dg-final { scan-assembler-not "stxvd2x" } } */
-+/* { dg-final { scan-assembler-not "stxvw4x" } } */
-Index: gcc/testsuite/gcc.target/powerpc/pr58673-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,78 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -m64 -O1" } */
-+
-+enum typecode
-+{
-+ QIcode, QUcode, HIcode, HUcode, SIcode, SUcode, DIcode, DUcode, SFcode,
-+ DFcode, XFcode, Pcode, Tcode, LAST_AND_UNUSED_TYPECODE
-+};
-+enum bytecode_opcode
-+{
-+ neverneverland, drop, duplicate, over, setstackSI, adjstackSI, constQI,
-+ constHI, constSI, constDI, constSF, constDF, constXF, constP, loadQI,
-+ loadHI, loadSI, loadDI, loadSF, loadDF, loadXF, loadP, storeQI, storeHI,
-+ storeSI, storeDI, storeSF, storeDF, storeXF, storeP, storeBLK, clearBLK,
-+ addconstPSI, newlocalSI, localP, argP, convertQIHI, convertHISI,
-+ convertSIDI, convertQISI, convertQUHU, convertHUSU, convertSUDU,
-+ convertQUSU, convertSFDF, convertDFXF, convertHIQI, convertSIHI,
-+ convertDISI, convertSIQI, convertSUQU, convertDFSF, convertXFDF,
-+ convertSISF, convertSIDF, convertSIXF, convertSUSF, convertSUDF,
-+ convertSUXF, convertDISF, convertDIDF, convertDIXF, convertDUSF,
-+ convertDUDF, convertDUXF, convertSFSI, convertDFSI, convertXFSI,
-+ convertSFSU, convertDFSU, convertXFSU, convertSFDI, convertDFDI,
-+ convertXFDI, convertSFDU, convertDFDU, convertXFDU, convertPSI,
-+ convertSIP, convertSIT, convertDIT, convertSFT, convertDFT, convertXFT,
-+ convertPT, zxloadBI, sxloadBI, sstoreBI, addSI, addDI, addSF, addDF,
-+ addXF, addPSI, subSI, subDI, subSF, subDF, subXF, subPP, mulSI, mulDI,
-+ mulSU, mulDU, mulSF, mulDF, mulXF, divSI, divDI, divSU, divDU, divSF,
-+ divDF, divXF, modSI, modDI, modSU, modDU, andSI, andDI, iorSI, iorDI,
-+ xorSI, xorDI, lshiftSI, lshiftSU, lshiftDI, lshiftDU, rshiftSI, rshiftSU,
-+ rshiftDI, rshiftDU, ltSI, ltSU, ltDI, ltDU, ltSF, ltDF, ltXF, ltP, leSI,
-+ leSU, leDI, leDU, leSF, leDF, leXF, leP, geSI, geSU, geDI, geDU, geSF,
-+ geDF, geXF, geP, gtSI, gtSU, gtDI, gtDU, gtSF, gtDF, gtXF, gtP, eqSI,
-+ eqDI, eqSF, eqDF, eqXF, eqP, neSI, neDI, neSF, neDF, neXF, neP, negSI,
-+ negDI, negSF, negDF, negXF, notSI, notDI, notT, predecQI, predecHI,
-+ predecSI, predecDI, predecP, predecSF, predecDF, predecXF, predecBI,
-+ preincQI, preincHI, preincSI, preincDI, preincP, preincSF, preincDF,
-+ preincXF, preincBI, postdecQI, postdecHI, postdecSI, postdecDI, postdecP,
-+ postdecSF, postdecDF, postdecXF, postdecBI, postincQI, postincHI,
-+ postincSI, postincDI, postincP, postincSF, postincDF, postincXF,
-+ postincBI, xjumpif, xjumpifnot, jump, jumpP, caseSI, caseSU, caseDI,
-+ caseDU, call, returnP, ret, linenote, LAST_AND_UNUSED_OPCODE
-+};
-+struct binary_operator
-+{
-+ enum bytecode_opcode opcode;
-+ enum typecode arg0;
-+};
-+static struct conversion_recipe
-+{
-+ unsigned char *opcodes;
-+ int cost;
-+}
-+conversion_recipe[((int) LAST_AND_UNUSED_TYPECODE)][((int)
-+ LAST_AND_UNUSED_TYPECODE)];
-+static struct conversion_recipe
-+deduce_conversion (from, to)
-+ enum typecode from, to;
-+{
-+ (conversion_recipe[(int) from][(int) to].
-+ opcodes ? 0 : (conversion_recipe[(int) from][(int) to] =
-+ deduce_conversion (from, to), 0));
-+}
-+
-+void
-+bc_expand_binary_operation (optab, resulttype, arg0, arg1)
-+ struct binary_operator optab[];
-+{
-+ int i, besti, cost, bestcost;
-+ enum typecode resultcode, arg0code;
-+ for (i = 0; optab[i].opcode != -1; ++i)
-+ {
-+ (conversion_recipe[(int) arg0code][(int) optab[i].arg0].
-+ opcodes ? 0 : (conversion_recipe[(int) arg0code][(int) optab[i].arg0] =
-+ deduce_conversion (arg0code, optab[i].arg0), 0));
-+ }
-+}
-Index: gcc/testsuite/gcc.target/powerpc/no-r11-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,6 @@
- /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
- /* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
- /* { dg-options "-O2 -mno-pointers-to-nested-functions" } */
-
- int
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-fp.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,139 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */
-+
-+float abs_sf (float *p)
-+{
-+ float f = *p;
-+ __asm__ ("# reg %x0" : "+v" (f));
-+ return __builtin_fabsf (f);
-+}
-+
-+float nabs_sf (float *p)
-+{
-+ float f = *p;
-+ __asm__ ("# reg %x0" : "+v" (f));
-+ return - __builtin_fabsf (f);
-+}
-+
-+float neg_sf (float *p)
-+{
-+ float f = *p;
-+ __asm__ ("# reg %x0" : "+v" (f));
-+ return - f;
-+}
-+
-+float add_sf (float *p, float *q)
-+{
-+ float f1 = *p;
-+ float f2 = *q;
-+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));
-+ return f1 + f2;
-+}
-+
-+float sub_sf (float *p, float *q)
-+{
-+ float f1 = *p;
-+ float f2 = *q;
-+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));
-+ return f1 - f2;
-+}
-+
-+float mul_sf (float *p, float *q)
-+{
-+ float f1 = *p;
-+ float f2 = *q;
-+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));
-+ return f1 * f2;
-+}
-+
-+float div_sf (float *p, float *q)
-+{
-+ float f1 = *p;
-+ float f2 = *q;
-+ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));
-+ return f1 / f2;
-+}
-+
-+float sqrt_sf (float *p)
-+{
-+ float f = *p;
-+ __asm__ ("# reg %x0" : "+v" (f));
-+ return __builtin_sqrtf (f);
-+}
-+
-+
-+double abs_df (double *p)
-+{
-+ double d = *p;
-+ __asm__ ("# reg %x0" : "+v" (d));
-+ return __builtin_fabs (d);
-+}
-+
-+double nabs_df (double *p)
-+{
-+ double d = *p;
-+ __asm__ ("# reg %x0" : "+v" (d));
-+ return - __builtin_fabs (d);
-+}
-+
-+double neg_df (double *p)
-+{
-+ double d = *p;
-+ __asm__ ("# reg %x0" : "+v" (d));
-+ return - d;
-+}
-+
-+double add_df (double *p, double *q)
-+{
-+ double d1 = *p;
-+ double d2 = *q;
-+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));
-+ return d1 + d2;
-+}
-+
-+double sub_df (double *p, double *q)
-+{
-+ double d1 = *p;
-+ double d2 = *q;
-+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));
-+ return d1 - d2;
-+}
-+
-+double mul_df (double *p, double *q)
-+{
-+ double d1 = *p;
-+ double d2 = *q;
-+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));
-+ return d1 * d2;
-+}
-+
-+double div_df (double *p, double *q)
-+{
-+ double d1 = *p;
-+ double d2 = *q;
-+ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));
-+ return d1 / d2;
-+}
-+
-+double sqrt_df (float *p)
-+{
-+ double d = *p;
-+ __asm__ ("# reg %x0" : "+v" (d));
-+ return __builtin_sqrt (d);
-+}
-+
-+/* { dg-final { scan-assembler "xsabsdp" } } */
-+/* { dg-final { scan-assembler "xsadddp" } } */
-+/* { dg-final { scan-assembler "xsaddsp" } } */
-+/* { dg-final { scan-assembler "xsdivdp" } } */
-+/* { dg-final { scan-assembler "xsdivsp" } } */
-+/* { dg-final { scan-assembler "xsmuldp" } } */
-+/* { dg-final { scan-assembler "xsmulsp" } } */
-+/* { dg-final { scan-assembler "xsnabsdp" } } */
-+/* { dg-final { scan-assembler "xsnegdp" } } */
-+/* { dg-final { scan-assembler "xssqrtdp" } } */
-+/* { dg-final { scan-assembler "xssqrtsp" } } */
-+/* { dg-final { scan-assembler "xssubdp" } } */
-+/* { dg-final { scan-assembler "xssubsp" } } */
-Index: gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target p8vector_hw } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+
-+/* Check whether we get the right bits for direct move at runtime. */
-+
-+#define TYPE vector int
-+#define DO_MAIN
-+#define VSX_REG_ATTR "wa"
-+
-+#include "direct-move.h"
-Index: gcc/testsuite/gcc.target/powerpc/bool3-p7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-O2 -mcpu=power7" } */
-+/* { dg-final { scan-assembler "\[ \t\]and " } } */
-+/* { dg-final { scan-assembler "\[ \t\]or " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]nor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]andc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
-+
-+/* On power7, for 128-bit types, ORC/ANDC/EQV might not show up, since the
-+ vector unit doesn't support these, so the appropriate combine patterns may
-+ not be generated. */
-+
-+#ifndef TYPE
-+#ifdef _ARCH_PPC64
-+#define TYPE __int128_t
-+#else
-+typedef int v4si __attribute__ ((vector_size (16)));
-+#define TYPE v4si
-+#endif
-+#endif
-+
-+#include "bool3.h"
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,104 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */
-+
-+#include <altivec.h>
-+
-+typedef vector long long vll_sign;
-+typedef vector unsigned long long vll_uns;
-+typedef vector bool long long vll_bool;
-+
-+typedef vector int vi_sign;
-+typedef vector unsigned int vi_uns;
-+typedef vector bool int vi_bool;
-+
-+typedef vector short vs_sign;
-+typedef vector unsigned short vs_uns;
-+typedef vector bool short vs_bool;
-+
-+typedef vector signed char vc_sign;
-+typedef vector unsigned char vc_uns;
-+typedef vector bool char vc_bool;
-+
-+
-+vi_sign vi_pack_1 (vll_sign a, vll_sign b)
-+{
-+ return __builtin_altivec_vpkudum (a, b);
-+}
-+
-+vi_sign vi_pack_2 (vll_sign a, vll_sign b)
-+{
-+ return vec_pack (a, b);
-+}
-+
-+vi_sign vi_pack_3 (vll_sign a, vll_sign b)
-+{
-+ return vec_vpkudum (a, b);
-+}
-+
-+vs_sign vs_pack_1 (vi_sign a, vi_sign b)
-+{
-+ return __builtin_altivec_vpkuwum (a, b);
-+}
-+
-+vs_sign vs_pack_2 (vi_sign a, vi_sign b)
-+{
-+ return vec_pack (a, b);
-+}
-+
-+vs_sign vs_pack_3 (vi_sign a, vi_sign b)
-+{
-+ return vec_vpkuwum (a, b);
-+}
-+
-+vc_sign vc_pack_1 (vs_sign a, vs_sign b)
-+{
-+ return __builtin_altivec_vpkuhum (a, b);
-+}
-+
-+vc_sign vc_pack_2 (vs_sign a, vs_sign b)
-+{
-+ return vec_pack (a, b);
-+}
-+
-+vc_sign vc_pack_3 (vs_sign a, vs_sign b)
-+{
-+ return vec_vpkuhum (a, b);
-+}
-+
-+vll_sign vll_unpack_hi_1 (vi_sign a)
-+{
-+ return __builtin_altivec_vupkhsw (a);
-+}
-+
-+vll_sign vll_unpack_hi_2 (vi_sign a)
-+{
-+ return vec_unpackh (a);
-+}
-+
-+vll_sign vll_unpack_hi_3 (vi_sign a)
-+{
-+ return __builtin_vec_vupkhsw (a);
-+}
-+
-+vll_sign vll_unpack_lo_1 (vi_sign a)
-+{
-+ return vec_vupklsw (a);
-+}
-+
-+vll_sign vll_unpack_lo_2 (vi_sign a)
-+{
-+ return vec_unpackl (a);
-+}
-+
-+vll_sign vll_unpack_lo_3 (vi_sign a)
-+{
-+ return vec_vupklsw (a);
-+}
-+
-+/* { dg-final { scan-assembler-times "vpkudum" 3 } } */
-+/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */
-+/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */
-+/* { dg-final { scan-assembler-times "vupklsw" 3 } } */
-+/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */
-+
-+#include <stddef.h>
-+
-+#ifndef SIZE
-+#define SIZE 1024
-+#endif
-+
-+#ifndef ALIGN
-+#define ALIGN 32
-+#endif
-+
-+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
-+
-+long long sign_ll[SIZE] ALIGN_ATTR;
-+int sign_i [SIZE] ALIGN_ATTR;
-+
-+void copy_long_long_to_int (void)
-+{
-+ size_t i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ sign_i[i] = sign_ll[i];
-+}
-+
-+/* { dg-final { scan-assembler "vpkudum" } } */
-Index: gcc/testsuite/gcc.target/powerpc/direct-move.h
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move.h (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,188 @@
-+/* Test functions for direct move support. */
-+
-+#include <math.h>
-+extern void abort (void);
-+
-+#ifndef VSX_REG_ATTR
-+#define VSX_REG_ATTR "wa"
-+#endif
-+
-+void __attribute__((__noinline__))
-+copy (TYPE *a, TYPE *b)
-+{
-+ *b = *a;
-+}
-+
-+#ifndef NO_GPR
-+void __attribute__((__noinline__))
-+load_gpr (TYPE *a, TYPE *b)
-+{
-+ TYPE c = *a;
-+ __asm__ ("# gpr, reg = %0" : "+b" (c));
-+ *b = c;
-+}
-+#endif
-+
-+#ifndef NO_FPR
-+void __attribute__((__noinline__))
-+load_fpr (TYPE *a, TYPE *b)
-+{
-+ TYPE c = *a;
-+ __asm__ ("# fpr, reg = %0" : "+d" (c));
-+ *b = c;
-+}
-+#endif
-+
-+#ifndef NO_ALTIVEC
-+void __attribute__((__noinline__))
-+load_altivec (TYPE *a, TYPE *b)
-+{
-+ TYPE c = *a;
-+ __asm__ ("# altivec, reg = %0" : "+v" (c));
-+ *b = c;
-+}
-+#endif
-+
-+#ifndef NO_VSX
-+void __attribute__((__noinline__))
-+load_vsx (TYPE *a, TYPE *b)
-+{
-+ TYPE c = *a;
-+ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));
-+ *b = c;
-+}
-+#endif
-+
-+#ifndef NO_GPR_TO_VSX
-+void __attribute__((__noinline__))
-+load_gpr_to_vsx (TYPE *a, TYPE *b)
-+{
-+ TYPE c = *a;
-+ TYPE d;
-+ __asm__ ("# gpr, reg = %0" : "+b" (c));
-+ d = c;
-+ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (d));
-+ *b = d;
-+}
-+#endif
-+
-+#ifndef NO_VSX_TO_GPR
-+void __attribute__((__noinline__))
-+load_vsx_to_gpr (TYPE *a, TYPE *b)
-+{
-+ TYPE c = *a;
-+ TYPE d;
-+ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));
-+ d = c;
-+ __asm__ ("# gpr, reg = %0" : "+b" (d));
-+ *b = d;
-+}
-+#endif
-+
-+#ifdef DO_MAIN
-+typedef void (fn_type (TYPE *, TYPE *));
-+
-+struct test_struct {
-+ fn_type *func;
-+ const char *name;
-+};
-+
-+const struct test_struct test_functions[] = {
-+ { copy, "copy" },
-+#ifndef NO_GPR
-+ { load_gpr, "load_gpr" },
-+#endif
-+#ifndef NO_FPR
-+ { load_fpr, "load_fpr" },
-+#endif
-+#ifndef NO_ALTIVEC
-+ { load_altivec, "load_altivec" },
-+#endif
-+#ifndef NO_VSX
-+ { load_vsx, "load_vsx" },
-+#endif
-+#ifndef NO_GPR_TO_VSX
-+ { load_gpr_to_vsx, "load_gpr_to_vsx" },
-+#endif
-+#ifndef NO_VSX_TO_GPR
-+ { load_vsx_to_gpr, "load_vsx_to_gpr" },
-+#endif
-+};
-+
-+/* Test a given value for each of the functions. */
-+void __attribute__((__noinline__))
-+test_value (TYPE a)
-+{
-+ long i;
-+
-+ for (i = 0; i < sizeof (test_functions) / sizeof (test_functions[0]); i++)
-+ {
-+ TYPE b;
-+
-+ test_functions[i].func (&a, &b);
-+ if (memcmp ((void *)&a, (void *)&b, sizeof (TYPE)) != 0)
-+ abort ();
-+ }
-+}
-+
-+/* Main program. */
-+int
-+main (void)
-+{
-+ long i,j;
-+ union {
-+ TYPE value;
-+ unsigned char bytes[sizeof (TYPE)];
-+ } u;
-+
-+#if IS_INT
-+ TYPE value = (TYPE)-5;
-+ for (i = 0; i < 12; i++)
-+ {
-+ test_value (value);
-+ value++;
-+ }
-+
-+ for (i = 0; i < 8*sizeof (TYPE); i++)
-+ test_value (((TYPE)1) << i);
-+
-+#elif IS_UNS
-+ TYPE value = (TYPE)0;
-+ for (i = 0; i < 10; i++)
-+ {
-+ test_value (value);
-+ test_value (~ value);
-+ value++;
-+ }
-+
-+ for (i = 0; i < 8*sizeof (TYPE); i++)
-+ test_value (((TYPE)1) << i);
-+
-+#elif IS_FLOAT
-+ TYPE value = (TYPE)-5;
-+ for (i = 0; i < 12; i++)
-+ {
-+ test_value (value);
-+ value++;
-+ }
-+
-+ test_value ((TYPE)3.1415926535);
-+ test_value ((TYPE)1.23456);
-+ test_value ((TYPE)(-0.0));
-+ test_value ((TYPE)NAN);
-+ test_value ((TYPE)+INFINITY);
-+ test_value ((TYPE)-INFINITY);
-+#else
-+
-+ for (j = 0; j < 10; j++)
-+ {
-+ for (i = 0; i < sizeof (TYPE); i++)
-+ u.bytes[i] = (unsigned char) (random () >> 4);
-+
-+ test_value (u.value);
-+ }
-+#endif
-+
-+ return 0;
-+}
-+#endif
-Index: gcc/testsuite/gcc.target/powerpc/sd-vsx.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-O2 -mcpu=power7 -mhard-dfp" } */
-+/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
-+/* { dg-final { scan-assembler-times "stfiwx" 1 } } */
-+/* { dg-final { scan-assembler-not "lfd" } } */
-+/* { dg-final { scan-assembler-not "stfd" } } */
-+/* { dg-final { scan-assembler-times "dctdp" 2 } } */
-+/* { dg-final { scan-assembler-times "dadd" 1 } } */
-+/* { dg-final { scan-assembler-times "drsp" 1 } } */
-+
-+/* Test that power7 can directly load/store SDmode variables without using a
-+ bounce buffer. */
-+_Decimal32 a;
-+
-+void inc_dec32 (void)
-+{
-+ a += (_Decimal32) 1.0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/bcd-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,44 @@
-+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+/* { dg-final { scan-assembler-times "bcdadd\[.\] " 2 } } */
-+/* { dg-final { scan-assembler-times "bcdsub\[.\] " 2 } } */
-+/* { dg-final { scan-assembler-not "bl __builtin" } } */
-+/* { dg-final { scan-assembler-not "mtvsr" } } */
-+/* { dg-final { scan-assembler-not "mfvsr" } } */
-+/* { dg-final { scan-assembler-not "lvx" } } */
-+/* { dg-final { scan-assembler-not "lxvw4x" } } */
-+/* { dg-final { scan-assembler-not "lxvd2x" } } */
-+/* { dg-final { scan-assembler-not "stvx" } } */
-+/* { dg-final { scan-assembler-not "stxvw4x" } } */
-+/* { dg-final { scan-assembler-not "stxvd2x" } } */
-+
-+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;
-+typedef __int128_t scalar_128_t;
-+typedef unsigned long long scalar_64_t;
-+
-+vector_128_t
-+do_add_0 (vector_128_t a, vector_128_t b)
-+{
-+ return __builtin_bcdadd (a, b, 0);
-+}
-+
-+vector_128_t
-+do_add_1 (vector_128_t a, vector_128_t b)
-+{
-+ return __builtin_bcdadd (a, b, 1);
-+}
-+
-+vector_128_t
-+do_sub_0 (vector_128_t a, vector_128_t b)
-+{
-+ return __builtin_bcdsub (a, b, 0);
-+}
-+
-+vector_128_t
-+do_sub_1 (vector_128_t a, vector_128_t b)
-+{
-+ return __builtin_bcdsub (a, b, 1);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/extend-divide-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,34 @@
-+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-mcpu=power7 -O2" } */
-+/* { dg-final { scan-assembler-times "divde " 1 } } */
-+/* { dg-final { scan-assembler-times "divdeo " 1 } } */
-+/* { dg-final { scan-assembler-times "divdeu " 1 } } */
-+/* { dg-final { scan-assembler-times "divdeuo " 1 } } */
-+/* { dg-final { scan-assembler-not "bl __builtin" } } */
-+
-+long
-+div_de (long a, long b)
-+{
-+ return __builtin_divde (a, b);
-+}
-+
-+long
-+div_deo (long a, long b)
-+{
-+ return __builtin_divdeo (a, b);
-+}
-+
-+unsigned long
-+div_deu (unsigned long a, unsigned long b)
-+{
-+ return __builtin_divdeu (a, b);
-+}
-+
-+unsigned long
-+div_deuo (unsigned long a, unsigned long b)
-+{
-+ return __builtin_divdeuo (a, b);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,177 @@
-+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target p8vector_hw } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+
-+#include <stddef.h>
-+#include <stdlib.h>
-+#include <altivec.h>
-+
-+#ifdef DEBUG
-+#include <stdio.h>
-+#define UNUSED
-+
-+#ifdef __LITTLE_ENDIAN__
-+#define HI_WORD 1
-+#define LO_WORD 0
-+#else
-+#define HI_WORD 0
-+#define LO_WORD 1
-+#endif
-+
-+#else
-+#define UNUSED __attribute__((__unused__))
-+#endif
-+
-+#ifndef S_TYPE
-+#define S_TYPE __uint128_t
-+#endif
-+
-+#ifndef V_TYPE
-+#define V_TYPE vector S_TYPE
-+#endif
-+
-+static int compare (S_TYPE, V_TYPE, const char *, const char *)
-+ __attribute__((__noinline__));
-+
-+static int
-+compare (S_TYPE scalar,
-+ V_TYPE vect,
-+ const char *nl UNUSED,
-+ const char *which UNUSED)
-+{
-+ unsigned long scalar_lo = (unsigned long) scalar;
-+ unsigned long scalar_hi = (unsigned long) (scalar >> 64);
-+ unsigned long vect_lo;
-+ unsigned long vect_hi;
-+ vector long long tmp;
-+ int ret;
-+
-+ __asm__ ("mfvsrd %0,%x3\n\t"
-+ "xxpermdi %x2,%x3,%x3,3\n\t"
-+ "mfvsrd %1,%x2"
-+ : "=r" (vect_hi),
-+ "=r" (vect_lo),
-+ "=wa" (tmp)
-+ : "wa" (vect));
-+
-+ ret = (scalar_lo != vect_lo) || (scalar_hi != vect_hi);
-+
-+#ifdef DEBUG
-+ printf ("%s%s: 0x%.16lx %.16lx %s 0x%.16lx %.16lx\n",
-+ nl, which,
-+ scalar_hi, scalar_lo,
-+ (ret) ? "!=" : "==",
-+ vect_hi, vect_lo);
-+
-+ fflush (stdout);
-+#endif
-+
-+ return ret;
-+}
-+
-+static void convert_via_mem (V_TYPE *, S_TYPE *)
-+ __attribute__((__noinline__));
-+
-+static void
-+convert_via_mem (V_TYPE *v, S_TYPE *s)
-+{
-+ *v = (V_TYPE) { *s };
-+ __asm__ volatile ("nop"
-+ : "+m" (*s), "+m" (*v)
-+ :
-+ : "memory");
-+
-+}
-+
-+
-+/* Check if vadduqm returns the same values as normal 128-bit add. */
-+
-+/* Values to add together. */
-+const static struct {
-+ unsigned long hi_1;
-+ unsigned long lo_1;
-+ unsigned long hi_2;
-+ unsigned long lo_2;
-+} values[] = {
-+ { 0x0000000000000000UL, 0xfffffffffffffffeUL,
-+ 0x0000000000000000UL, 0x0000000000000002UL },
-+ { 0x0000000000000000UL, 0x0000000000000002UL,
-+ 0x0000000000000000UL, 0xfffffffffffffffeUL },
-+ { 0xffffffffffffffffUL, 0xfffffffffffffffeUL,
-+ 0x0000000000000000UL, 0x0000000000000002UL },
-+ { 0xfffffffffffffff2UL, 0xffffffffffffffffUL,
-+ 0x0000000000000002UL, 0x0000000000000000UL },
-+ { 0x7fffffffffffffffUL, 0xfffffffffffffffeUL,
-+ 0x0000000000000000UL, 0x0000000000000002UL },
-+ { 0x7ffffffffffffff2UL, 0xffffffffffffffffUL,
-+ 0x0000000000000002UL, 0x0000000000000000UL },
-+};
-+
-+int
-+main (void)
-+{
-+ int reg_errors = 0;
-+ int mem_errors = 0;
-+ size_t i;
-+ const char *nl = "";
-+
-+ for (i = 0; i < sizeof (values) / sizeof (values[0]); i++)
-+ {
-+ S_TYPE s_reg_res, s_reg_in1, s_reg_in2, s_mem_res, s_mem_in1, s_mem_in2;
-+ V_TYPE v_reg_res, v_reg_in1, v_reg_in2, v_mem_res, v_mem_in1, v_mem_in2;
-+
-+ s_reg_in1 = ((((S_TYPE)values[i].hi_1 << 64)) + ((S_TYPE)values[i].lo_1));
-+ reg_errors += compare (s_reg_in1, (V_TYPE) { s_reg_in1 }, nl, "reg, in1");
-+
-+ s_reg_in2 = ((((S_TYPE)values[i].hi_2 << 64)) + ((S_TYPE)values[i].lo_2));
-+ reg_errors += compare (s_reg_in2, (V_TYPE) { s_reg_in2 }, "", "reg, in2");
-+
-+ s_reg_res = s_reg_in1 + s_reg_in2;
-+
-+ v_reg_in1 = (V_TYPE) { s_reg_in1 };
-+ v_reg_in2 = (V_TYPE) { s_reg_in2 };
-+ v_reg_res = vec_vadduqm (v_reg_in1, v_reg_in2);
-+ reg_errors += compare (s_reg_res, v_reg_res, "", "reg, res");
-+
-+ s_mem_in1 = s_reg_in1;
-+ convert_via_mem (&v_mem_in1, &s_mem_in1);
-+ mem_errors += compare (s_mem_in1, (V_TYPE) { s_mem_in1 }, "\n", "mem, in1");
-+
-+ s_mem_in2 = s_reg_in2;
-+ convert_via_mem (&v_mem_in2, &s_mem_in2);
-+ mem_errors += compare (s_mem_in2, (V_TYPE) { s_mem_in2 }, "", "mem, in2");
-+
-+ s_mem_res = s_mem_in1 + s_mem_in2;
-+ v_mem_res = vec_vadduqm (v_mem_in1, v_mem_in2);
-+ mem_errors += compare (s_mem_res, v_mem_res, "", "mem, res");
-+
-+ nl = "\n";
-+ }
-+
-+#ifdef DEBUG
-+ putchar ('\n');
-+
-+ if (!reg_errors)
-+ fputs ("no errors found on register operations\n", stdout);
-+ else
-+ printf ("%d error%s found on register operations\n",
-+ reg_errors,
-+ (reg_errors == 1) ? "s" : "");
-+
-+ if (!mem_errors)
-+ fputs ("no errors found on memory operations\n", stdout);
-+ else
-+ printf ("%d error%s found on memory operations\n",
-+ mem_errors,
-+ (mem_errors == 1) ? "s" : "");
-+
-+ fflush (stdout);
-+#endif
-+
-+ if ((reg_errors + mem_errors) != 0)
-+ abort ();
-+
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/pr58673-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,217 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O3 -m64 -funroll-loops" } */
-+
-+#include <stddef.h>
-+#include <stdlib.h>
-+#include <math.h>
-+#include <string.h>
-+
-+typedef long unsigned int size_t;
-+typedef struct _IO_FILE FILE;
-+typedef float real;
-+typedef real rvec[3];
-+typedef real matrix[3][3];
-+typedef real tensor[3][3];
-+enum
-+{
-+ F_BONDS, F_G96BONDS, F_MORSE, F_CUBICBONDS, F_CONNBONDS, F_HARMONIC,
-+ F_ANGLES, F_G96ANGLES, F_PDIHS, F_RBDIHS, F_IDIHS, F_LJ14, F_COUL14, F_LJ,
-+ F_BHAM, F_LJLR, F_DISPCORR, F_SR, F_LR, F_WPOL, F_POSRES, F_DISRES,
-+ F_DISRESVIOL, F_ORIRES, F_ORIRESDEV, F_ANGRES, F_ANGRESZ, F_SHAKE,
-+ F_SHAKENC, F_SETTLE, F_DUMMY2, F_DUMMY3, F_DUMMY3FD, F_DUMMY3FAD,
-+ F_DUMMY3OUT, F_DUMMY4FD, F_EQM, F_EPOT, F_EKIN, F_ETOT, F_TEMP, F_PRES,
-+ F_DVDL, F_DVDLKIN, F_NRE
-+};
-+typedef union
-+{
-+ struct
-+ {
-+ }
-+ bham;
-+ struct
-+ {
-+ real rA, krA, rB, krB;
-+ }
-+ harmonic;
-+}
-+t_iparams;
-+typedef struct
-+{
-+ t_iparams *iparams;
-+}
-+t_idef;
-+typedef struct
-+{
-+}
-+t_inputrec;
-+typedef struct
-+{
-+}
-+t_commrec;
-+typedef struct
-+{
-+}
-+t_forcerec;
-+typedef struct
-+{
-+}
-+t_mdatoms;
-+typedef struct
-+{
-+}
-+t_filenm;
-+enum
-+{
-+ eoPres, eoEpot, eoVir, eoDist, eoMu, eoForce, eoFx, eoFy, eoFz, eoPx, eoPy,
-+ eoPz, eoPolarizability, eoDipole, eoObsNR, eoMemory =
-+ eoObsNR, eoInter, eoUseVirial, eoNR
-+};
-+extern char *eoNames[eoNR];
-+typedef struct
-+{
-+ int bPrint;
-+}
-+t_coupl_LJ;
-+typedef struct
-+{
-+ int eObs;
-+ t_iparams xi;
-+}
-+t_coupl_iparams;
-+typedef struct
-+{
-+ real act_value[eoObsNR];
-+ real av_value[eoObsNR];
-+ real ref_value[eoObsNR];
-+ int bObsUsed[eoObsNR];
-+ int nLJ, nBU, nQ, nIP;
-+ t_coupl_LJ *tcLJ;
-+}
-+t_coupl_rec;
-+static void
-+pr_ff (t_coupl_rec * tcr, real time, t_idef * idef, t_commrec * cr, int nfile,
-+ t_filenm fnm[])
-+{
-+ static FILE *prop;
-+ static FILE **out = ((void *) 0);
-+ static FILE **qq = ((void *) 0);
-+ static FILE **ip = ((void *) 0);
-+ char buf[256];
-+ char *leg[] = {
-+ "C12", "C6"
-+ };
-+ char **raleg;
-+ int i, j, index;
-+ if ((prop == ((void *) 0)) && (out == ((void *) 0)) && (qq == ((void *) 0))
-+ && (ip == ((void *) 0)))
-+ {
-+ for (i = j = 0; (i < eoObsNR); i++)
-+ {
-+ if (tcr->bObsUsed[i])
-+ {
-+ raleg[j++] =
-+ (__extension__
-+ (__builtin_constant_p (eoNames[i])
-+ && ((size_t) (const void *) ((eoNames[i]) + 1) -
-+ (size_t) (const void *) (eoNames[i]) ==
-+ 1) ? (((const char *) (eoNames[i]))[0] ==
-+ '\0' ? (char *) calloc ((size_t) 1,
-+ (size_t) 1) : (
-+ {
-+ size_t
-+ __len
-+ =
-+ strlen
-+ (eoNames
-+ [i])
-+ +
-+ 1;
-+ char
-+ *__retval
-+ =
-+ (char
-+ *)
-+ malloc
-+ (__len);
-+ __retval;}
-+ )): __strdup (eoNames[i])));
-+ raleg[j++] =
-+ (__extension__
-+ (__builtin_constant_p (buf)
-+ && ((size_t) (const void *) ((buf) + 1) -
-+ (size_t) (const void *) (buf) ==
-+ 1) ? (((const char *) (buf))[0] ==
-+ '\0' ? (char *) calloc ((size_t) 1,
-+ (size_t) 1) : (
-+ {
-+ size_t
-+ __len
-+ =
-+ strlen
-+ (buf)
-+ +
-+ 1;
-+ char
-+ *__retval
-+ =
-+ (char
-+ *)
-+ malloc
-+ (__len);
-+ __retval;}
-+ )): __strdup (buf)));
-+ }
-+ }
-+ if (tcr->nLJ)
-+ {
-+ for (i = 0; (i < tcr->nLJ); i++)
-+ {
-+ if (tcr->tcLJ[i].bPrint)
-+ {
-+ xvgr_legend (out[i], (sizeof (leg) / sizeof ((leg)[0])),
-+ leg);
-+ }
-+ }
-+ }
-+ }
-+}
-+
-+void
-+do_coupling (FILE * log, int nfile, t_filenm fnm[], t_coupl_rec * tcr, real t,
-+ int step, real ener[], t_forcerec * fr, t_inputrec * ir,
-+ int bMaster, t_mdatoms * md, t_idef * idef, real mu_aver,
-+ int nmols, t_commrec * cr, matrix box, tensor virial,
-+ tensor pres, rvec mu_tot, rvec x[], rvec f[], int bDoIt)
-+{
-+ int i, j, ati, atj, atnr2, type, ftype;
-+ real deviation[eoObsNR], prdev[eoObsNR], epot0, dist, rmsf;
-+ real ff6, ff12, ffa, ffb, ffc, ffq, factor, dt, mu_ind;
-+ int bTest, bPrint;
-+ t_coupl_iparams *tip;
-+ if (bPrint)
-+ {
-+ pr_ff (tcr, t, idef, cr, nfile, fnm);
-+ }
-+ for (i = 0; (i < eoObsNR); i++)
-+ {
-+ deviation[i] =
-+ calc_deviation (tcr->av_value[i], tcr->act_value[i],
-+ tcr->ref_value[i]);
-+ prdev[i] = tcr->ref_value[i] - tcr->act_value[i];
-+ }
-+ if (bPrint)
-+ pr_dev (tcr, t, prdev, cr, nfile, fnm);
-+ for (i = 0; (i < atnr2); i++)
-+ {
-+ factor = dt * deviation[tip->eObs];
-+ switch (ftype)
-+ {
-+ case F_BONDS:
-+ if (fabs (tip->xi.harmonic.krA) > 1.2e-38)
-+ idef->iparams[type].harmonic.krA *=
-+ (1 + factor / tip->xi.harmonic.krA);
-+ }
-+ }
-+}
-Index: gcc/testsuite/gcc.target/powerpc/atomic-p7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,207 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-mcpu=power7 -O2" } */
-+/* { dg-final { scan-assembler-not "lbarx" } } */
-+/* { dg-final { scan-assembler-not "lharx" } } */
-+/* { dg-final { scan-assembler-times "lwarx" 18 } } */
-+/* { dg-final { scan-assembler-times "ldarx" 6 } } */
-+/* { dg-final { scan-assembler-not "lqarx" } } */
-+/* { dg-final { scan-assembler-not "stbcx" } } */
-+/* { dg-final { scan-assembler-not "sthcx" } } */
-+/* { dg-final { scan-assembler-times "stwcx" 18 } } */
-+/* { dg-final { scan-assembler-times "stdcx" 6 } } */
-+/* { dg-final { scan-assembler-not "stqcx" } } */
-+/* { dg-final { scan-assembler-times "bl __atomic" 6 } } */
-+/* { dg-final { scan-assembler-times "isync" 12 } } */
-+/* { dg-final { scan-assembler-times "lwsync" 8 } } */
-+/* { dg-final { scan-assembler-not "mtvsrd" } } */
-+/* { dg-final { scan-assembler-not "mtvsrwa" } } */
-+/* { dg-final { scan-assembler-not "mtvsrwz" } } */
-+/* { dg-final { scan-assembler-not "mfvsrd" } } */
-+/* { dg-final { scan-assembler-not "mfvsrwz" } } */
-+
-+/* Test for the byte atomic operations on power8 using lbarx/stbcx. */
-+char
-+char_fetch_add_relaxed (char *ptr, int value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+char
-+char_fetch_sub_consume (char *ptr, int value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+char
-+char_fetch_and_acquire (char *ptr, int value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+char
-+char_fetch_ior_release (char *ptr, int value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+char
-+char_fetch_xor_acq_rel (char *ptr, int value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+char
-+char_fetch_nand_seq_cst (char *ptr, int value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-+
-+/* Test for the half word atomic operations on power8 using lharx/sthcx. */
-+short
-+short_fetch_add_relaxed (short *ptr, int value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+short
-+short_fetch_sub_consume (short *ptr, int value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+short
-+short_fetch_and_acquire (short *ptr, int value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+short
-+short_fetch_ior_release (short *ptr, int value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+short
-+short_fetch_xor_acq_rel (short *ptr, int value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+short
-+short_fetch_nand_seq_cst (short *ptr, int value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-+
-+/* Test for the word atomic operations on power8 using lwarx/stwcx. */
-+int
-+int_fetch_add_relaxed (int *ptr, int value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+int
-+int_fetch_sub_consume (int *ptr, int value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+int
-+int_fetch_and_acquire (int *ptr, int value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+int
-+int_fetch_ior_release (int *ptr, int value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+int
-+int_fetch_xor_acq_rel (int *ptr, int value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+int
-+int_fetch_nand_seq_cst (int *ptr, int value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-+
-+/* Test for the double word atomic operations on power8 using ldarx/stdcx. */
-+long
-+long_fetch_add_relaxed (long *ptr, long value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+long
-+long_fetch_sub_consume (long *ptr, long value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+long
-+long_fetch_and_acquire (long *ptr, long value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+long
-+long_fetch_ior_release (long *ptr, long value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+long
-+long_fetch_xor_acq_rel (long *ptr, long value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+long
-+long_fetch_nand_seq_cst (long *ptr, long value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-+
-+/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */
-+__int128_t
-+quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+__int128_t
-+quad_fetch_sub_consume (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+__int128_t
-+quad_fetch_and_acquire (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+__int128_t
-+quad_fetch_ior_release (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+__int128_t
-+quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+__int128_t
-+quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/recip-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/recip-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-3.c (.../branches/gcc-4_8-branch)
-@@ -1,14 +1,14 @@
- /* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */
- /* { dg-require-effective-target powerpc_fprs } */
- /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power7" } */
--/* { dg-final { scan-assembler-times "xsrsqrtedp" 1 } } */
-+/* { dg-final { scan-assembler-times "xsrsqrtedp\|frsqrte\ " 1 } } */
- /* { dg-final { scan-assembler-times "xsmsub.dp\|fmsub\ " 1 } } */
--/* { dg-final { scan-assembler-times "xsmuldp" 4 } } */
-+/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 4 } } */
- /* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 2 } } */
--/* { dg-final { scan-assembler-times "frsqrtes" 1 } } */
--/* { dg-final { scan-assembler-times "fmsubs" 1 } } */
--/* { dg-final { scan-assembler-times "fmuls" 4 } } */
--/* { dg-final { scan-assembler-times "fnmsubs" 2 } } */
-+/* { dg-final { scan-assembler-times "xsrsqrtesp\|frsqrtes" 1 } } */
-+/* { dg-final { scan-assembler-times "xsmsub.sp\|fmsubs" 1 } } */
-+/* { dg-final { scan-assembler-times "xsmulsp\|fmuls" 2 } } */
-+/* { dg-final { scan-assembler-times "xsnmsub.sp\|fnmsubs" 1 } } */
-
- double
- rsqrt_d (double a)
-Index: gcc/testsuite/gcc.target/powerpc/timode_off.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/timode_off.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/timode_off.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* { dg-do assemble { target { lp64 } } } */
--/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */
-+/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps -mcpu=power5" } */
-
- typedef int TImode __attribute__ ((mode (TI)));
-
-@@ -46,6 +46,12 @@
- TImode r20 (void *x) { return *(TImode *) (x + 32748); }
-
- /* test should really be == 616, see pr54110 */
-+/* When TImode is allowed in VSX registers, the allowable address modes for
-+ TImode is just a single indirect address in order for the value to be loaded
-+ and store in either GPR or VSX registers. This affects the generated code,
-+ and it would cause this test to fail, when such an option is used. Fall
-+ back to power5 to test the code. */
-+
- /* { dg-final { object-size text <= 700 } } */
- /* { dg-final { scan-assembler-not "(st|l)fd" } } */
- /* { dg-final { cleanup-saved-temps "timode_off" } } */
-Index: gcc/testsuite/gcc.target/powerpc/no-r11-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,6 @@
- /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
- /* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
- /* { dg-options "-O2 -mpointers-to-nested-functions" } */
-
- int
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,42 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
-+
-+float load_sf (float *p)
-+{
-+ float f = *p;
-+ __asm__ ("# reg %x0" : "+v" (f));
-+ return f;
-+}
-+
-+double load_df (double *p)
-+{
-+ double d = *p;
-+ __asm__ ("# reg %x0" : "+v" (d));
-+ return d;
-+}
-+
-+double load_dfsf (float *p)
-+{
-+ double d = (double) *p;
-+ __asm__ ("# reg %x0" : "+v" (d));
-+ return d;
-+}
-+
-+void store_sf (float *p, float f)
-+{
-+ __asm__ ("# reg %x0" : "+v" (f));
-+ *p = f;
-+}
-+
-+void store_df (double *p, double d)
-+{
-+ __asm__ ("# reg %x0" : "+v" (d));
-+ *p = d;
-+}
-+
-+/* { dg-final { scan-assembler "lxsspx" } } */
-+/* { dg-final { scan-assembler "lxsdx" } } */
-+/* { dg-final { scan-assembler "stxsspx" } } */
-+/* { dg-final { scan-assembler "stxsdx" } } */
-Index: gcc/testsuite/gcc.target/powerpc/pack01.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pack01.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pack01.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,91 @@
-+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target p8vector_hw } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+
-+#include <stddef.h>
-+#include <stdlib.h>
-+#include <altivec.h>
-+
-+#ifdef DEBUG
-+#include <stdio.h>
-+#endif
-+
-+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;
-+typedef __int128_t scalar_128_t;
-+typedef unsigned long long scalar_64_t;
-+
-+volatile scalar_64_t one = 1;
-+volatile scalar_64_t two = 2;
-+
-+int
-+main (void)
-+{
-+ scalar_128_t a = (((scalar_128_t)one) << 64) | ((scalar_128_t)two);
-+ vector_128_t v1 = (vector_128_t) { a };
-+ vector_128_t v2 = __builtin_pack_vector_int128 (one, two);
-+ scalar_64_t x0 = __builtin_unpack_vector_int128 (v1, 0);
-+ scalar_64_t x1 = __builtin_unpack_vector_int128 (v1, 1);
-+ vector_128_t v3 = __builtin_pack_vector_int128 (x0, x1);
-+
-+ size_t i;
-+ union {
-+ scalar_128_t i128;
-+ vector_128_t v128;
-+ scalar_64_t u64;
-+ unsigned char uc[sizeof (scalar_128_t)];
-+ char c[sizeof (scalar_128_t)];
-+ } u, u2;
-+
-+#ifdef DEBUG
-+ {
-+ printf ("a = 0x");
-+ u.i128 = a;
-+ for (i = 0; i < sizeof (scalar_128_t); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf ("\nv1 = 0x");
-+ u.v128 = v1;
-+ for (i = 0; i < sizeof (scalar_128_t); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf ("\nv2 = 0x");
-+ u.v128 = v2;
-+ for (i = 0; i < sizeof (scalar_128_t); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf ("\nv3 = 0x");
-+ u.v128 = v3;
-+ for (i = 0; i < sizeof (scalar_128_t); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf ("\nx0 = 0x");
-+ u.u64 = x0;
-+ for (i = 0; i < sizeof (scalar_64_t); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf ("\nx1 = 0x");
-+ u.u64 = x1;
-+ for (i = 0; i < sizeof (scalar_64_t); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf ("\n");
-+ }
-+#endif
-+
-+ u2.i128 = a;
-+ u.v128 = v1;
-+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)
-+ abort ();
-+
-+ u.v128 = v2;
-+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)
-+ abort ();
-+
-+ u.v128 = v3;
-+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)
-+ abort ();
-+
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/bool3-p8.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,36 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-O2 -mcpu=power8" } */
-+/* { dg-final { scan-assembler "\[ \t\]and " } } */
-+/* { dg-final { scan-assembler "\[ \t\]or " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]nor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]andc " } } */
-+/* { dg-final { scan-assembler "\[ \t\]eqv " } } */
-+/* { dg-final { scan-assembler "\[ \t\]orc " } } */
-+/* { dg-final { scan-assembler "\[ \t\]nand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
-+
-+#ifndef TYPE
-+#ifdef _ARCH_PPC64
-+#define TYPE __int128_t
-+#else
-+typedef int v4si __attribute__ ((vector_size (16)));
-+#define TYPE v4si
-+#endif
-+#endif
-+
-+#include "bool3.h"
-Index: gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,32 @@
-+/* This checks the availability of the XL compiler intrinsics for
-+ transactional execution with the expected prototypes. */
-+
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_htm_ok } */
-+/* { dg-options "-O2 -mhtm" } */
-+
-+#include <htmxlintrin.h>
-+
-+void
-+foo (void *TM_buff, long *result, unsigned char *code)
-+{
-+ *result++ = __TM_simple_begin ();
-+ *result++ = __TM_begin (TM_buff);
-+ *result++ = __TM_end ();
-+ __TM_abort ();
-+ __TM_named_abort (*code);
-+ __TM_resume ();
-+ __TM_suspend ();
-+ *result++ = __TM_is_user_abort (TM_buff);
-+ *result++ = __TM_is_named_user_abort (TM_buff, code);
-+ *result++ = __TM_is_illegal (TM_buff);
-+ *result++ = __TM_is_footprint_exceeded (TM_buff);
-+ *result++ = __TM_nesting_depth (TM_buff);
-+ *result++ = __TM_is_nested_too_deep (TM_buff);
-+ *result++ = __TM_is_conflict (TM_buff);
-+ *result++ = __TM_is_failure_persistent (TM_buff);
-+ *result++ = __TM_failure_address (TM_buff);
-+ *result++ = __TM_failure_code (TM_buff);
-+}
-+
-Index: gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* Test accuracy of long double division (glibc bug 15396). */
-+/* { dg-do run { target powerpc*-*-linux* powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } } */
-+/* { dg-options "-mlong-double-128" } */
-+
-+extern void exit (int);
-+extern void abort (void);
-+
-+volatile long double a = 0x1p-1024L;
-+volatile long double b = 0x3p-53L;
-+volatile long double r;
-+volatile long double expected = 0x1.55555555555555555555555555p-973L;
-+
-+int
-+main (void)
-+{
-+ r = a / b;
-+ /* Allow error up to 2ulp. */
-+ if (__builtin_fabsl (r - expected) > 0x1p-1073L)
-+ abort ();
-+ exit (0);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,249 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */
-+
-+#include <altivec.h>
-+
-+typedef vector long long vll_sign;
-+typedef vector unsigned long long vll_uns;
-+typedef vector bool long long vll_bool;
-+
-+typedef vector int vi_sign;
-+typedef vector unsigned int vi_uns;
-+typedef vector bool int vi_bool;
-+
-+typedef vector short vs_sign;
-+typedef vector unsigned short vs_uns;
-+typedef vector bool short vs_bool;
-+
-+typedef vector signed char vc_sign;
-+typedef vector unsigned char vc_uns;
-+typedef vector bool char vc_bool;
-+
-+vll_sign vll_clz_1 (vll_sign a)
-+{
-+ return __builtin_altivec_vclzd (a);
-+}
-+
-+vll_sign vll_clz_2 (vll_sign a)
-+{
-+ return vec_vclz (a);
-+}
-+
-+vll_sign vll_clz_3 (vll_sign a)
-+{
-+ return vec_vclzd (a);
-+}
-+
-+vll_uns vll_clz_4 (vll_uns a)
-+{
-+ return vec_vclz (a);
-+}
-+
-+vll_uns vll_clz_5 (vll_uns a)
-+{
-+ return vec_vclzd (a);
-+}
-+
-+vi_sign vi_clz_1 (vi_sign a)
-+{
-+ return __builtin_altivec_vclzw (a);
-+}
-+
-+vi_sign vi_clz_2 (vi_sign a)
-+{
-+ return vec_vclz (a);
-+}
-+
-+vi_sign vi_clz_3 (vi_sign a)
-+{
-+ return vec_vclzw (a);
-+}
-+
-+vi_uns vi_clz_4 (vi_uns a)
-+{
-+ return vec_vclz (a);
-+}
-+
-+vi_uns vi_clz_5 (vi_uns a)
-+{
-+ return vec_vclzw (a);
-+}
-+
-+vs_sign vs_clz_1 (vs_sign a)
-+{
-+ return __builtin_altivec_vclzh (a);
-+}
-+
-+vs_sign vs_clz_2 (vs_sign a)
-+{
-+ return vec_vclz (a);
-+}
-+
-+vs_sign vs_clz_3 (vs_sign a)
-+{
-+ return vec_vclzh (a);
-+}
-+
-+vs_uns vs_clz_4 (vs_uns a)
-+{
-+ return vec_vclz (a);
-+}
-+
-+vs_uns vs_clz_5 (vs_uns a)
-+{
-+ return vec_vclzh (a);
-+}
-+
-+vc_sign vc_clz_1 (vc_sign a)
-+{
-+ return __builtin_altivec_vclzb (a);
-+}
-+
-+vc_sign vc_clz_2 (vc_sign a)
-+{
-+ return vec_vclz (a);
-+}
-+
-+vc_sign vc_clz_3 (vc_sign a)
-+{
-+ return vec_vclzb (a);
-+}
-+
-+vc_uns vc_clz_4 (vc_uns a)
-+{
-+ return vec_vclz (a);
-+}
-+
-+vc_uns vc_clz_5 (vc_uns a)
-+{
-+ return vec_vclzb (a);
-+}
-+
-+vll_sign vll_popcnt_1 (vll_sign a)
-+{
-+ return __builtin_altivec_vpopcntd (a);
-+}
-+
-+vll_sign vll_popcnt_2 (vll_sign a)
-+{
-+ return vec_vpopcnt (a);
-+}
-+
-+vll_sign vll_popcnt_3 (vll_sign a)
-+{
-+ return vec_vpopcntd (a);
-+}
-+
-+vll_uns vll_popcnt_4 (vll_uns a)
-+{
-+ return vec_vpopcnt (a);
-+}
-+
-+vll_uns vll_popcnt_5 (vll_uns a)
-+{
-+ return vec_vpopcntd (a);
-+}
-+
-+vi_sign vi_popcnt_1 (vi_sign a)
-+{
-+ return __builtin_altivec_vpopcntw (a);
-+}
-+
-+vi_sign vi_popcnt_2 (vi_sign a)
-+{
-+ return vec_vpopcnt (a);
-+}
-+
-+vi_sign vi_popcnt_3 (vi_sign a)
-+{
-+ return vec_vpopcntw (a);
-+}
-+
-+vi_uns vi_popcnt_4 (vi_uns a)
-+{
-+ return vec_vpopcnt (a);
-+}
-+
-+vi_uns vi_popcnt_5 (vi_uns a)
-+{
-+ return vec_vpopcntw (a);
-+}
-+
-+vs_sign vs_popcnt_1 (vs_sign a)
-+{
-+ return __builtin_altivec_vpopcnth (a);
-+}
-+
-+vs_sign vs_popcnt_2 (vs_sign a)
-+{
-+ return vec_vpopcnt (a);
-+}
-+
-+vs_sign vs_popcnt_3 (vs_sign a)
-+{
-+ return vec_vpopcnth (a);
-+}
-+
-+vs_uns vs_popcnt_4 (vs_uns a)
-+{
-+ return vec_vpopcnt (a);
-+}
-+
-+vs_uns vs_popcnt_5 (vs_uns a)
-+{
-+ return vec_vpopcnth (a);
-+}
-+
-+vc_sign vc_popcnt_1 (vc_sign a)
-+{
-+ return __builtin_altivec_vpopcntb (a);
-+}
-+
-+vc_sign vc_popcnt_2 (vc_sign a)
-+{
-+ return vec_vpopcnt (a);
-+}
-+
-+vc_sign vc_popcnt_3 (vc_sign a)
-+{
-+ return vec_vpopcntb (a);
-+}
-+
-+vc_uns vc_popcnt_4 (vc_uns a)
-+{
-+ return vec_vpopcnt (a);
-+}
-+
-+vc_uns vc_popcnt_5 (vc_uns a)
-+{
-+ return vec_vpopcntb (a);
-+}
-+
-+vc_uns vc_gbb_1 (vc_uns a)
-+{
-+ return __builtin_altivec_vgbbd (a);
-+}
-+
-+vc_sign vc_gbb_2 (vc_sign a)
-+{
-+ return vec_vgbbd (a);
-+}
-+
-+vc_uns vc_gbb_3 (vc_uns a)
-+{
-+ return vec_vgbbd (a);
-+}
-+
-+/* { dg-final { scan-assembler-times "vclzd" 5 } } */
-+/* { dg-final { scan-assembler-times "vclzw" 5 } } */
-+/* { dg-final { scan-assembler-times "vclzh" 5 } } */
-+/* { dg-final { scan-assembler-times "vclzb" 5 } } */
-+
-+/* { dg-final { scan-assembler-times "vpopcntd" 5 } } */
-+/* { dg-final { scan-assembler-times "vpopcntw" 5 } } */
-+/* { dg-final { scan-assembler-times "vpopcnth" 5 } } */
-+/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */
-+
-+/* { dg-final { scan-assembler-times "vgbbd" 3 } } */
-Index: gcc/testsuite/gcc.target/powerpc/bool3-av.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_altivec_ok } */
-+/* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */
-+/* { dg-final { scan-assembler "\[ \t\]and " } } */
-+/* { dg-final { scan-assembler "\[ \t\]or " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]nor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]andc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
-+
-+/* On altivec, for 128-bit types, ORC/ANDC/EQV might not show up, since the
-+ vector unit doesn't support these, so the appropriate combine patterns may
-+ not be generated. */
-+
-+#ifndef TYPE
-+#ifdef _ARCH_PPC64
-+#define TYPE __int128_t
-+#else
-+typedef int v4si __attribute__ ((vector_size (16)));
-+#define TYPE v4si
-+#endif
-+#endif
-+
-+#include "bool3.h"
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,69 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */
-+
-+#ifndef SIZE
-+#define SIZE 1024
-+#endif
-+
-+#ifndef ALIGN
-+#define ALIGN 32
-+#endif
-+
-+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
-+
-+#define DO_BUILTIN(PREFIX, TYPE, CLZ, POPCNT) \
-+TYPE PREFIX ## _a[SIZE] ALIGN_ATTR; \
-+TYPE PREFIX ## _b[SIZE] ALIGN_ATTR; \
-+ \
-+void \
-+PREFIX ## _clz (void) \
-+{ \
-+ unsigned long i; \
-+ \
-+ for (i = 0; i < SIZE; i++) \
-+ PREFIX ## _a[i] = CLZ (PREFIX ## _b[i]); \
-+} \
-+ \
-+void \
-+PREFIX ## _popcnt (void) \
-+{ \
-+ unsigned long i; \
-+ \
-+ for (i = 0; i < SIZE; i++) \
-+ PREFIX ## _a[i] = POPCNT (PREFIX ## _b[i]); \
-+}
-+
-+#if !defined(DO_LONG_LONG) && !defined(DO_LONG) && !defined(DO_INT) && !defined(DO_SHORT) && !defined(DO_CHAR)
-+#define DO_INT 1
-+#endif
-+
-+#if DO_LONG_LONG
-+/* At the moment, only int is auto vectorized. */
-+DO_BUILTIN (sll, long long, __builtin_clzll, __builtin_popcountll)
-+DO_BUILTIN (ull, unsigned long long, __builtin_clzll, __builtin_popcountll)
-+#endif
-+
-+#if defined(_ARCH_PPC64) && DO_LONG
-+DO_BUILTIN (sl, long, __builtin_clzl, __builtin_popcountl)
-+DO_BUILTIN (ul, unsigned long, __builtin_clzl, __builtin_popcountl)
-+#endif
-+
-+#if DO_INT
-+DO_BUILTIN (si, int, __builtin_clz, __builtin_popcount)
-+DO_BUILTIN (ui, unsigned int, __builtin_clz, __builtin_popcount)
-+#endif
-+
-+#if DO_SHORT
-+DO_BUILTIN (ss, short, __builtin_clz, __builtin_popcount)
-+DO_BUILTIN (us, unsigned short, __builtin_clz, __builtin_popcount)
-+#endif
-+
-+#if DO_CHAR
-+DO_BUILTIN (sc, signed char, __builtin_clz, __builtin_popcount)
-+DO_BUILTIN (uc, unsigned char, __builtin_clz, __builtin_popcount)
-+#endif
-+
-+/* { dg-final { scan-assembler-times "vclzw" 2 } } */
-+/* { dg-final { scan-assembler-times "vpopcntw" 2 } } */
-Index: gcc/testsuite/gcc.target/powerpc/bcd-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,103 @@
-+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+/* { dg-final { scan-assembler-times "bcdadd\[.\] " 4 } } */
-+/* { dg-final { scan-assembler-times "bcdsub\[.\] " 4 } } */
-+/* { dg-final { scan-assembler-not "bl __builtin" } } */
-+/* { dg-final { scan-assembler-not "mtvsr" } } */
-+/* { dg-final { scan-assembler-not "mfvsr" } } */
-+/* { dg-final { scan-assembler-not "lvx" } } */
-+/* { dg-final { scan-assembler-not "lxvw4x" } } */
-+/* { dg-final { scan-assembler-not "lxvd2x" } } */
-+/* { dg-final { scan-assembler-not "stvx" } } */
-+/* { dg-final { scan-assembler-not "stxvw4x" } } */
-+/* { dg-final { scan-assembler-not "stxvd2x" } } */
-+
-+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;
-+typedef __int128_t scalar_128_t;
-+typedef unsigned long long scalar_64_t;
-+
-+/* Test whether the peephole works to allow folding a bcdadd, with a
-+ bcdadd_<test> into a single instruction. */
-+
-+vector_128_t
-+do_add_lt (vector_128_t a, vector_128_t b, int *p)
-+{
-+ vector_128_t ret = __builtin_bcdadd (a, b, 0);
-+ if (__builtin_bcdadd_lt (a, b, 0))
-+ *p = 1;
-+
-+ return ret;
-+}
-+
-+vector_128_t
-+do_add_eq (vector_128_t a, vector_128_t b, int *p)
-+{
-+ vector_128_t ret = __builtin_bcdadd (a, b, 0);
-+ if (__builtin_bcdadd_eq (a, b, 0))
-+ *p = 1;
-+
-+ return ret;
-+}
-+
-+vector_128_t
-+do_add_gt (vector_128_t a, vector_128_t b, int *p)
-+{
-+ vector_128_t ret = __builtin_bcdadd (a, b, 0);
-+ if (__builtin_bcdadd_gt (a, b, 0))
-+ *p = 1;
-+
-+ return ret;
-+}
-+
-+vector_128_t
-+do_add_ov (vector_128_t a, vector_128_t b, int *p)
-+{
-+ vector_128_t ret = __builtin_bcdadd (a, b, 0);
-+ if (__builtin_bcdadd_ov (a, b, 0))
-+ *p = 1;
-+
-+ return ret;
-+}
-+
-+vector_128_t
-+do_sub_lt (vector_128_t a, vector_128_t b, int *p)
-+{
-+ vector_128_t ret = __builtin_bcdsub (a, b, 0);
-+ if (__builtin_bcdsub_lt (a, b, 0))
-+ *p = 1;
-+
-+ return ret;
-+}
-+
-+vector_128_t
-+do_sub_eq (vector_128_t a, vector_128_t b, int *p)
-+{
-+ vector_128_t ret = __builtin_bcdsub (a, b, 0);
-+ if (__builtin_bcdsub_eq (a, b, 0))
-+ *p = 1;
-+
-+ return ret;
-+}
-+
-+vector_128_t
-+do_sub_gt (vector_128_t a, vector_128_t b, int *p)
-+{
-+ vector_128_t ret = __builtin_bcdsub (a, b, 0);
-+ if (__builtin_bcdsub_gt (a, b, 0))
-+ *p = 1;
-+
-+ return ret;
-+}
-+
-+vector_128_t
-+do_sub_ov (vector_128_t a, vector_128_t b, int *p)
-+{
-+ vector_128_t ret = __builtin_bcdsub (a, b, 0);
-+ if (__builtin_bcdsub_ov (a, b, 0))
-+ *p = 1;
-+
-+ return ret;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/pr57949-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
-+/* { dg-options "-O2 -mcpu=power7 -mno-compat-align-parm" } */
-+
-+/* Verify that vs is 16-byte aligned with -mcompat-align-parm. */
-+
-+typedef float v4sf __attribute__ ((vector_size (16)));
-+struct s { long m; v4sf v; };
-+long n;
-+v4sf ve;
-+
-+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,
-+ long d7, long d8, long d9, struct s vs) {
-+ n = vs.m;
-+ ve = vs.v;
-+}
-+
-+/* { dg-final { scan-assembler "li \.\*,144" } } */
-+/* { dg-final { scan-assembler "ld \.\*,128\\(1\\)" } } */
-Index: gcc/testsuite/gcc.target/powerpc/atomic-p8.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,237 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+/* { dg-final { scan-assembler-times "lbarx" 7 } } */
-+/* { dg-final { scan-assembler-times "lharx" 7 } } */
-+/* { dg-final { scan-assembler-times "lwarx" 7 } } */
-+/* { dg-final { scan-assembler-times "ldarx" 7 } } */
-+/* { dg-final { scan-assembler-times "lqarx" 7 } } */
-+/* { dg-final { scan-assembler-times "stbcx" 7 } } */
-+/* { dg-final { scan-assembler-times "sthcx" 7 } } */
-+/* { dg-final { scan-assembler-times "stwcx" 7 } } */
-+/* { dg-final { scan-assembler-times "stdcx" 7 } } */
-+/* { dg-final { scan-assembler-times "stqcx" 7 } } */
-+/* { dg-final { scan-assembler-not "bl __atomic" } } */
-+/* { dg-final { scan-assembler-times "isync" 20 } } */
-+/* { dg-final { scan-assembler-times "lwsync" 10 } } */
-+/* { dg-final { scan-assembler-not "mtvsrd" } } */
-+/* { dg-final { scan-assembler-not "mtvsrwa" } } */
-+/* { dg-final { scan-assembler-not "mtvsrwz" } } */
-+/* { dg-final { scan-assembler-not "mfvsrd" } } */
-+/* { dg-final { scan-assembler-not "mfvsrwz" } } */
-+
-+/* Test for the byte atomic operations on power8 using lbarx/stbcx. */
-+char
-+char_fetch_add_relaxed (char *ptr, int value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+char
-+char_fetch_sub_consume (char *ptr, int value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+char
-+char_fetch_and_acquire (char *ptr, int value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+char
-+char_fetch_ior_release (char *ptr, int value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+char
-+char_fetch_xor_acq_rel (char *ptr, int value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+char
-+char_fetch_nand_seq_cst (char *ptr, int value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-+
-+void
-+char_val_compare_and_swap (char *p, int i, int j, char *q)
-+{
-+ *q = __sync_val_compare_and_swap (p, i, j);
-+}
-+
-+/* Test for the half word atomic operations on power8 using lharx/sthcx. */
-+short
-+short_fetch_add_relaxed (short *ptr, int value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+short
-+short_fetch_sub_consume (short *ptr, int value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+short
-+short_fetch_and_acquire (short *ptr, int value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+short
-+short_fetch_ior_release (short *ptr, int value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+short
-+short_fetch_xor_acq_rel (short *ptr, int value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+short
-+short_fetch_nand_seq_cst (short *ptr, int value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-+
-+void
-+short_val_compare_and_swap (short *p, int i, int j, short *q)
-+{
-+ *q = __sync_val_compare_and_swap (p, i, j);
-+}
-+
-+/* Test for the word atomic operations on power8 using lwarx/stwcx. */
-+int
-+int_fetch_add_relaxed (int *ptr, int value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+int
-+int_fetch_sub_consume (int *ptr, int value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+int
-+int_fetch_and_acquire (int *ptr, int value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+int
-+int_fetch_ior_release (int *ptr, int value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+int
-+int_fetch_xor_acq_rel (int *ptr, int value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+int
-+int_fetch_nand_seq_cst (int *ptr, int value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-+
-+void
-+int_val_compare_and_swap (int *p, int i, int j, int *q)
-+{
-+ *q = __sync_val_compare_and_swap (p, i, j);
-+}
-+
-+/* Test for the double word atomic operations on power8 using ldarx/stdcx. */
-+long
-+long_fetch_add_relaxed (long *ptr, long value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+long
-+long_fetch_sub_consume (long *ptr, long value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+long
-+long_fetch_and_acquire (long *ptr, long value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+long
-+long_fetch_ior_release (long *ptr, long value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+long
-+long_fetch_xor_acq_rel (long *ptr, long value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+long
-+long_fetch_nand_seq_cst (long *ptr, long value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-+
-+void
-+long_val_compare_and_swap (long *p, long i, long j, long *q)
-+{
-+ *q = __sync_val_compare_and_swap (p, i, j);
-+}
-+
-+/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */
-+__int128_t
-+quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
-+}
-+
-+__int128_t
-+quad_fetch_sub_consume (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
-+}
-+
-+__int128_t
-+quad_fetch_and_acquire (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+__int128_t
-+quad_fetch_ior_release (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
-+}
-+
-+__int128_t
-+quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
-+}
-+
-+__int128_t
-+quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
-+}
-+
-+void
-+quad_val_compare_and_swap (__int128_t *p, __int128_t i, __int128_t j, __int128_t *q)
-+{
-+ *q = __sync_val_compare_and_swap (p, i, j);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/sd-pwr6.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,19 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-O2 -mcpu=power6 -mhard-dfp" } */
-+/* { dg-final { scan-assembler-not "lfiwzx" } } */
-+/* { dg-final { scan-assembler-times "lfd" 2 } } */
-+/* { dg-final { scan-assembler-times "dctdp" 2 } } */
-+/* { dg-final { scan-assembler-times "dadd" 1 } } */
-+/* { dg-final { scan-assembler-times "drsp" 1 } } */
-+
-+/* Test that for power6 we need to use a bounce buffer on the stack to load
-+ SDmode variables because the power6 does not have a way to directly load
-+ 32-bit values from memory. */
-+_Decimal32 a;
-+
-+void inc_dec32 (void)
-+{
-+ a += (_Decimal32) 1.0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/recip-4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/recip-4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-4.c (.../branches/gcc-4_8-branch)
-@@ -7,8 +7,8 @@
- /* { dg-final { scan-assembler-times "xvnmsub.dp" 2 } } */
- /* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */
- /* { dg-final { scan-assembler-times "xvmsub.sp" 1 } } */
--/* { dg-final { scan-assembler-times "xvmulsp" 4 } } */
--/* { dg-final { scan-assembler-times "xvnmsub.sp" 2 } } */
-+/* { dg-final { scan-assembler-times "xvmulsp" 2 } } */
-+/* { dg-final { scan-assembler-times "xvnmsub.sp" 1 } } */
-
- #define SIZE 1024
-
-Index: gcc/testsuite/gcc.target/powerpc/no-r11-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,6 @@
- /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
- /* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
- /* { dg-options "-O2 -mno-pointers-to-nested-functions" } */
-
- extern void ext_call (int (func) (void));
-Index: gcc/testsuite/gcc.target/powerpc/pack02.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pack02.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pack02.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,95 @@
-+/* { dg-do run { target { powerpc*-*-linux* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_fprs } */
-+/* { dg-options "-O2 -mhard-float" } */
-+
-+#include <stddef.h>
-+#include <stdlib.h>
-+#include <math.h>
-+
-+#ifdef DEBUG
-+#include <stdio.h>
-+#endif
-+
-+int
-+main (void)
-+{
-+ double high = pow (2.0, 60);
-+ double low = 2.0;
-+ long double a = ((long double)high) + ((long double)low);
-+ double x0 = __builtin_unpack_longdouble (a, 0);
-+ double x1 = __builtin_unpack_longdouble (a, 1);
-+ long double b = __builtin_pack_longdouble (x0, x1);
-+
-+#ifdef DEBUG
-+ {
-+ size_t i;
-+ union {
-+ long double ld;
-+ double d;
-+ unsigned char uc[sizeof (long double)];
-+ char c[sizeof (long double)];
-+ } u;
-+
-+ printf ("a = 0x");
-+ u.ld = a;
-+ for (i = 0; i < sizeof (long double); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf (", %Lg\n", a);
-+
-+ printf ("b = 0x");
-+ u.ld = b;
-+ for (i = 0; i < sizeof (long double); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf (", %Lg\n", b);
-+
-+ printf ("hi = 0x");
-+ u.d = high;
-+ for (i = 0; i < sizeof (double); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", high);
-+
-+ printf ("lo = 0x");
-+ u.d = low;
-+ for (i = 0; i < sizeof (double); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", low);
-+
-+ printf ("x0 = 0x");
-+ u.d = x0;
-+ for (i = 0; i < sizeof (double); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x0);
-+
-+ printf ("x1 = 0x");
-+ u.d = x1;
-+ for (i = 0; i < sizeof (double); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x1);
-+ }
-+#endif
-+
-+ if (high != x0)
-+ abort ();
-+
-+ if (low != x1)
-+ abort ();
-+
-+ if (a != b)
-+ abort ();
-+
-+ if (x0 != high)
-+ abort ();
-+
-+ if (x1 != low)
-+ abort ();
-+
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,130 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */
-+
-+typedef vector unsigned long long crypto_t;
-+typedef vector unsigned long long v2di_t;
-+typedef vector unsigned int v4si_t;
-+typedef vector unsigned short v8hi_t;
-+typedef vector unsigned char v16qi_t;
-+
-+crypto_t crpyto1 (crypto_t a)
-+{
-+ return __builtin_crypto_vsbox (a);
-+}
-+
-+crypto_t crypto2 (crypto_t a, crypto_t b)
-+{
-+ return __builtin_crypto_vcipher (a, b);
-+}
-+
-+crypto_t crypto3 (crypto_t a, crypto_t b)
-+{
-+ return __builtin_crypto_vcipherlast (a, b);
-+}
-+
-+crypto_t crypto4 (crypto_t a, crypto_t b)
-+{
-+ return __builtin_crypto_vncipher (a, b);
-+}
-+
-+crypto_t crypto5 (crypto_t a, crypto_t b)
-+{
-+ return __builtin_crypto_vncipherlast (a, b);
-+}
-+
-+v16qi_t crypto6a (v16qi_t a, v16qi_t b, v16qi_t c)
-+{
-+ return __builtin_crypto_vpermxor (a, b, c);
-+}
-+
-+v8hi_t crypto6b (v8hi_t a, v8hi_t b, v8hi_t c)
-+{
-+ return __builtin_crypto_vpermxor (a, b, c);
-+}
-+
-+v4si_t crypto6c (v4si_t a, v4si_t b, v4si_t c)
-+{
-+ return __builtin_crypto_vpermxor (a, b, c);
-+}
-+
-+v2di_t crypto6d (v2di_t a, v2di_t b, v2di_t c)
-+{
-+ return __builtin_crypto_vpermxor (a, b, c);
-+}
-+
-+v16qi_t crypto7a (v16qi_t a, v16qi_t b)
-+{
-+ return __builtin_crypto_vpmsumb (a, b);
-+}
-+
-+v16qi_t crypto7b (v16qi_t a, v16qi_t b)
-+{
-+ return __builtin_crypto_vpmsum (a, b);
-+}
-+
-+v8hi_t crypto7c (v8hi_t a, v8hi_t b)
-+{
-+ return __builtin_crypto_vpmsumh (a, b);
-+}
-+
-+v8hi_t crypto7d (v8hi_t a, v8hi_t b)
-+{
-+ return __builtin_crypto_vpmsum (a, b);
-+}
-+
-+v4si_t crypto7e (v4si_t a, v4si_t b)
-+{
-+ return __builtin_crypto_vpmsumw (a, b);
-+}
-+
-+v4si_t crypto7f (v4si_t a, v4si_t b)
-+{
-+ return __builtin_crypto_vpmsum (a, b);
-+}
-+
-+v2di_t crypto7g (v2di_t a, v2di_t b)
-+{
-+ return __builtin_crypto_vpmsumd (a, b);
-+}
-+
-+v2di_t crypto7h (v2di_t a, v2di_t b)
-+{
-+ return __builtin_crypto_vpmsum (a, b);
-+}
-+
-+v2di_t crypto8a (v2di_t a)
-+{
-+ return __builtin_crypto_vshasigmad (a, 0, 8);
-+}
-+
-+v2di_t crypto8b (v2di_t a)
-+{
-+ return __builtin_crypto_vshasigma (a, 0, 8);
-+}
-+
-+v4si_t crypto8c (v4si_t a)
-+{
-+ return __builtin_crypto_vshasigmaw (a, 1, 15);
-+}
-+
-+v4si_t crypto8d (v4si_t a)
-+{
-+ return __builtin_crypto_vshasigma (a, 1, 15);
-+}
-+
-+/* Note space is used after the instruction so that vcipherlast does not match
-+ vcipher. */
-+/* { dg-final { scan-assembler-times "vcipher " 1 } } */
-+/* { dg-final { scan-assembler-times "vcipherlast " 1 } } */
-+/* { dg-final { scan-assembler-times "vncipher " 1 } } */
-+/* { dg-final { scan-assembler-times "vncipherlast " 1 } } */
-+/* { dg-final { scan-assembler-times "vpermxor " 4 } } */
-+/* { dg-final { scan-assembler-times "vpmsumb " 2 } } */
-+/* { dg-final { scan-assembler-times "vpmsumd " 2 } } */
-+/* { dg-final { scan-assembler-times "vpmsumh " 2 } } */
-+/* { dg-final { scan-assembler-times "vpmsumw " 2 } } */
-+/* { dg-final { scan-assembler-times "vsbox " 1 } } */
-+/* { dg-final { scan-assembler-times "vshasigmad " 2 } } */
-+/* { dg-final { scan-assembler-times "vshasigmaw " 2 } } */
-Index: gcc/testsuite/gcc.target/powerpc/pr42747.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr42747.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr42747.c (.../branches/gcc-4_8-branch)
-@@ -5,4 +5,4 @@
-
- double foo (double x) { return __builtin_sqrt (x); }
-
--/* { dg-final { scan-assembler "xssqrtdp" } } */
-+/* { dg-final { scan-assembler "xssqrtdp\|fsqrt" } } */
-Index: gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,26 @@
-+/* Test generation of DFP instructions for POWER6. */
-+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
-+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */
-+
-+/* { dg-final { scan-assembler-times "fneg" 1 } } */
-+/* { dg-final { scan-assembler-times "fabs" 1 } } */
-+/* { dg-final { scan-assembler-times "fnabs" 1 } } */
-+/* { dg-final { scan-assembler-times "fmr" 0 } } */
-+
-+_Decimal64
-+func1 (_Decimal64 a, _Decimal64 b)
-+{
-+ return -b;
-+}
-+
-+_Decimal64
-+func2 (_Decimal64 a, _Decimal64 b)
-+{
-+ return __builtin_fabsd64 (b);
-+}
-+
-+_Decimal64
-+func3 (_Decimal64 a, _Decimal64 b)
-+{
-+ return - __builtin_fabsd64 (b);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+/* { dg-final { scan-assembler "mtvsrd" } } */
-+/* { dg-final { scan-assembler "mfvsrd" } } */
-+/* { dg-final { scan-assembler "xscvdpspn" } } */
-+/* { dg-final { scan-assembler "xscvspdpn" } } */
-+
-+/* Check code generation for direct move for float types. */
-+
-+#define TYPE float
-+#define IS_FLOAT 1
-+#define NO_ALTIVEC 1
-+#define VSX_REG_ATTR "ww"
-+
-+#include "direct-move.h"
-Index: gcc/testsuite/gcc.target/powerpc/dfp-td-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* Test generation of DFP instructions for POWER6. */
-+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
-+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */
-+
-+/* { dg-final { scan-assembler-times "fneg" 1 } } */
-+/* { dg-final { scan-assembler-times "fabs" 1 } } */
-+/* { dg-final { scan-assembler-times "fnabs" 1 } } */
-+/* { dg-final { scan-assembler-times "fmr" 0 } } */
-+
-+/* These tests verify we only generate fneg, fabs and fnabs
-+ instructions and no fmr's since these are done in place. */
-+
-+_Decimal128
-+func1 (_Decimal128 a)
-+{
-+ return -a;
-+}
-+
-+_Decimal128
-+func2 (_Decimal128 a)
-+{
-+ return __builtin_fabsd128 (a);
-+}
-+
-+_Decimal128
-+func3 (_Decimal128 a)
-+{
-+ return - __builtin_fabsd128 (a);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,105 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */
-+
-+#include <altivec.h>
-+
-+#ifndef SIZE
-+#define SIZE 1024
-+#endif
-+
-+#ifndef ALIGN
-+#define ALIGN 32
-+#endif
-+
-+#ifndef ATTR_ALIGN
-+#define ATTR_ALIGN __attribute__((__aligned__(ALIGN)))
-+#endif
-+
-+#define DOIT(TYPE, PREFIX) \
-+TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \
-+{ \
-+ return vec_eqv (a, b); \
-+} \
-+ \
-+TYPE PREFIX ## _eqv_arith (TYPE a, TYPE b) \
-+{ \
-+ return ~(a ^ b); \
-+} \
-+ \
-+TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \
-+{ \
-+ return vec_nand (a, b); \
-+} \
-+ \
-+TYPE PREFIX ## _nand_arith1 (TYPE a, TYPE b) \
-+{ \
-+ return ~(a & b); \
-+} \
-+ \
-+TYPE PREFIX ## _nand_arith2 (TYPE a, TYPE b) \
-+{ \
-+ return (~a) | (~b); \
-+} \
-+ \
-+TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \
-+{ \
-+ return vec_orc (a, b); \
-+} \
-+ \
-+TYPE PREFIX ## _orc_arith1 (TYPE a, TYPE b) \
-+{ \
-+ return (~ a) | b; \
-+} \
-+ \
-+TYPE PREFIX ## _orc_arith2 (TYPE a, TYPE b) \
-+{ \
-+ return a | (~ b); \
-+}
-+
-+#define DOIT_FLOAT(TYPE, PREFIX) \
-+TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \
-+{ \
-+ return vec_eqv (a, b); \
-+} \
-+ \
-+TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \
-+{ \
-+ return vec_nand (a, b); \
-+} \
-+ \
-+TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \
-+{ \
-+ return vec_orc (a, b); \
-+}
-+
-+typedef vector signed char sign_char_vec;
-+typedef vector short sign_short_vec;
-+typedef vector int sign_int_vec;
-+typedef vector long long sign_llong_vec;
-+
-+typedef vector unsigned char uns_char_vec;
-+typedef vector unsigned short uns_short_vec;
-+typedef vector unsigned int uns_int_vec;
-+typedef vector unsigned long long uns_llong_vec;
-+
-+typedef vector float float_vec;
-+typedef vector double double_vec;
-+
-+DOIT(sign_char_vec, sign_char)
-+DOIT(sign_short_vec, sign_short)
-+DOIT(sign_int_vec, sign_int)
-+DOIT(sign_llong_vec, sign_llong)
-+
-+DOIT(uns_char_vec, uns_char)
-+DOIT(uns_short_vec, uns_short)
-+DOIT(uns_int_vec, uns_int)
-+DOIT(uns_llong_vec, uns_llong)
-+
-+DOIT_FLOAT(float_vec, float)
-+DOIT_FLOAT(double_vec, double)
-+
-+/* { dg-final { scan-assembler-times "xxleqv" 18 } } */
-+/* { dg-final { scan-assembler-times "xxlnand" 26 } } */
-+/* { dg-final { scan-assembler-times "xxlorc" 26 } } */
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,87 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */
-+
-+#ifndef SIZE
-+#define SIZE 1024
-+#endif
-+
-+#ifndef ALIGN
-+#define ALIGN 32
-+#endif
-+
-+#ifndef ATTR_ALIGN
-+#define ATTR_ALIGN __attribute__((__aligned__(ALIGN)))
-+#endif
-+
-+#ifndef TYPE
-+#define TYPE unsigned int
-+#endif
-+
-+TYPE in1 [SIZE] ATTR_ALIGN;
-+TYPE in2 [SIZE] ATTR_ALIGN;
-+TYPE eqv [SIZE] ATTR_ALIGN;
-+TYPE nand1[SIZE] ATTR_ALIGN;
-+TYPE nand2[SIZE] ATTR_ALIGN;
-+TYPE orc1 [SIZE] ATTR_ALIGN;
-+TYPE orc2 [SIZE] ATTR_ALIGN;
-+
-+void
-+do_eqv (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ {
-+ eqv[i] = ~(in1[i] ^ in2[i]);
-+ }
-+}
-+
-+void
-+do_nand1 (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ {
-+ nand1[i] = ~(in1[i] & in2[i]);
-+ }
-+}
-+
-+void
-+do_nand2 (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ {
-+ nand2[i] = (~in1[i]) | (~in2[i]);
-+ }
-+}
-+
-+void
-+do_orc1 (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ {
-+ orc1[i] = (~in1[i]) | in2[i];
-+ }
-+}
-+
-+void
-+do_orc2 (void)
-+{
-+ unsigned long i;
-+
-+ for (i = 0; i < SIZE; i++)
-+ {
-+ orc1[i] = in1[i] | (~in2[i]);
-+ }
-+}
-+
-+/* { dg-final { scan-assembler-times "xxleqv" 1 } } */
-+/* { dg-final { scan-assembler-times "xxlnand" 2 } } */
-+/* { dg-final { scan-assembler-times "xxlorc" 2 } } */
-Index: gcc/testsuite/gcc.target/powerpc/pr57949-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
-+/* { dg-options "-O2 -mcpu=power7" } */
-+
-+/* Verify that vs is not 16-byte aligned in the absence of -mno-compat-align-parm. */
-+
-+typedef float v4sf __attribute__ ((vector_size (16)));
-+struct s { long m; v4sf v; };
-+long n;
-+v4sf ve;
-+
-+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,
-+ long d7, long d8, long d9, struct s vs) {
-+ n = vs.m;
-+ ve = vs.v;
-+}
-+
-+/* { dg-final { scan-assembler "ld .\*,136\\(1\\)" } } */
-+/* { dg-final { scan-assembler "ld .\*,120\\(1\\)" } } */
-Index: gcc/testsuite/gcc.target/powerpc/recip-5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/recip-5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/recip-5.c (.../branches/gcc-4_8-branch)
-@@ -4,8 +4,16 @@
- /* { dg-options "-O3 -ftree-vectorize -mrecip=all -ffast-math -mcpu=power7 -fno-unroll-loops" } */
- /* { dg-final { scan-assembler-times "xvredp" 4 } } */
- /* { dg-final { scan-assembler-times "xvresp" 5 } } */
--/* { dg-final { scan-assembler-times "xsredp" 2 } } */
--/* { dg-final { scan-assembler-times "fres" 2 } } */
-+/* { dg-final { scan-assembler-times "xsredp\|fre\ " 2 } } */
-+/* { dg-final { scan-assembler-times "xsresp\|fres" 2 } } */
-+/* { dg-final { scan-assembler-times "xsmulsp\|fmuls" 2 } } */
-+/* { dg-final { scan-assembler-times "xsnmsub.sp\|fnmsubs" 2 } } */
-+/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 2 } } */
-+/* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 4 } } */
-+/* { dg-final { scan-assembler-times "xvmulsp" 7 } } */
-+/* { dg-final { scan-assembler-times "xvnmsub.sp" 5 } } */
-+/* { dg-final { scan-assembler-times "xvmuldp" 6 } } */
-+/* { dg-final { scan-assembler-times "xvnmsub.dp" 8 } } */
-
- #include <altivec.h>
-
-Index: gcc/testsuite/gcc.target/powerpc/pack03.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pack03.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pack03.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,88 @@
-+/* { dg-do run { target { powerpc*-*-linux* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target dfp_hw } */
-+/* { dg-options "-O2 -mhard-dfp" } */
-+
-+#include <stddef.h>
-+#include <stdlib.h>
-+#include <math.h>
-+
-+#ifdef DEBUG
-+#include <stdio.h>
-+#endif
-+
-+int
-+main (void)
-+{
-+ _Decimal128 one = (_Decimal128)1.0;
-+ _Decimal128 two = (_Decimal128)2.0;
-+ _Decimal128 ten = (_Decimal128)10.0;
-+ _Decimal128 a = one;
-+ _Decimal128 b;
-+ _Decimal128 c;
-+ unsigned long long x0;
-+ unsigned long long x1;
-+ size_t i;
-+
-+ for (i = 0; i < 25; i++)
-+ a *= ten;
-+
-+ a += two;
-+
-+ x0 = __builtin_unpack_dec128 (a, 0);
-+ x1 = __builtin_unpack_dec128 (a, 1);
-+ b = __builtin_pack_dec128 (x0, x1);
-+ c = __builtin_dscliq (one, 25) + two;
-+
-+#ifdef DEBUG
-+ {
-+ union {
-+ _Decimal128 d;
-+ unsigned long long ull;
-+ unsigned char uc[sizeof (_Decimal128)];
-+ } u;
-+
-+ printf ("a = 0x");
-+ u.d = a;
-+ for (i = 0; i < sizeof (_Decimal128); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf (", %Lg\n", (long double)a);
-+
-+ printf ("b = 0x");
-+ u.d = b;
-+ for (i = 0; i < sizeof (_Decimal128); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf (", %Lg\n", (long double)b);
-+
-+ printf ("c = 0x");
-+ u.d = c;
-+ for (i = 0; i < sizeof (_Decimal128); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf (", %Lg\n", (long double)c);
-+
-+ printf ("x0 = 0x");
-+ u.ull = x0;
-+ for (i = 0; i < sizeof (unsigned long long); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf ("\nx1 = 0x");
-+ u.ull = x1;
-+ for (i = 0; i < sizeof (unsigned long long); i++)
-+ printf ("%.2x", u.uc[i]);
-+
-+ printf ("\n");
-+ }
-+#endif
-+
-+ if (a != b)
-+ abort ();
-+
-+ if (a != c)
-+ abort ();
-+
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c (.../branches/gcc-4_8-branch)
-@@ -89,8 +89,10 @@
- long a1;
- long a2;
- long a3;
-+#if _CALL_ELF != 2
- long a4;
- long a5;
-+#endif
- parm_t slot[100];
- } stack_frame_t;
-
-Index: gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target p8vector_hw } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+
-+/* Check whether we get the right bits for direct move at runtime. */
-+
-+#define TYPE float
-+#define IS_FLOAT 1
-+#define NO_ALTIVEC 1
-+#define DO_MAIN
-+#define VSX_REG_ATTR "ww"
-+
-+#include "direct-move.h"
-Index: gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+/* { dg-final { scan-assembler "mtvsrd" } } */
-+/* { dg-final { scan-assembler "mfvsrd" } } */
-+
-+/* Check code generation for direct move for double types. */
-+
-+#define TYPE double
-+#define IS_FLOAT 1
-+#define NO_ALTIVEC 1
-+#define VSX_REG_ATTR "ws"
-+
-+#include "direct-move.h"
-Index: gcc/testsuite/gcc.target/powerpc/dfp-td-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* Test generation of DFP instructions for POWER6. */
-+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
-+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */
-+
-+/* { dg-final { scan-assembler-times "fneg" 1 } } */
-+/* { dg-final { scan-assembler-times "fabs" 1 } } */
-+/* { dg-final { scan-assembler-times "fnabs" 1 } } */
-+/* { dg-final { scan-assembler-times "fmr" 3 } } */
-+
-+/* These tests verify we generate fneg, fabs and fnabs and
-+ associated fmr's since these are not done in place. */
-+
-+_Decimal128
-+func1 (_Decimal128 a, _Decimal128 b)
-+{
-+ return -b;
-+}
-+
-+_Decimal128
-+func2 (_Decimal128 a, _Decimal128 b)
-+{
-+ return __builtin_fabsd128 (b);
-+}
-+
-+_Decimal128
-+func3 (_Decimal128 a, _Decimal128 b)
-+{
-+ return - __builtin_fabsd128 (b);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+
-+vector float dbl_to_float_p8 (double x) { return __builtin_vsx_xscvdpspn (x); }
-+double float_to_dbl_p8 (vector float x) { return __builtin_vsx_xscvspdpn (x); }
-+
-+/* { dg-final { scan-assembler "xscvdpspn" } } */
-+/* { dg-final { scan-assembler "xscvspdpn" } } */
-Index: gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (.../branches/gcc-4_8-branch)
-@@ -16,9 +16,9 @@
- /* { dg-final { scan-assembler "xvrspiz" } } */
- /* { dg-final { scan-assembler "xsrdpi" } } */
- /* { dg-final { scan-assembler "xsrdpic" } } */
--/* { dg-final { scan-assembler "xsrdpim" } } */
--/* { dg-final { scan-assembler "xsrdpip" } } */
--/* { dg-final { scan-assembler "xsrdpiz" } } */
-+/* { dg-final { scan-assembler "xsrdpim\|frim" } } */
-+/* { dg-final { scan-assembler "xsrdpip\|frip" } } */
-+/* { dg-final { scan-assembler "xsrdpiz\|friz" } } */
- /* { dg-final { scan-assembler "xsmaxdp" } } */
- /* { dg-final { scan-assembler "xsmindp" } } */
- /* { dg-final { scan-assembler "xxland" } } */
-Index: gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,51 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_htm_ok } */
-+/* { dg-options "-O2 -mhtm" } */
-+
-+/* { dg-final { scan-assembler-times "tbegin\\." 1 } } */
-+/* { dg-final { scan-assembler-times "tend\\." 2 } } */
-+/* { dg-final { scan-assembler-times "tabort\\." 2 } } */
-+/* { dg-final { scan-assembler-times "tabortdc\\." 1 } } */
-+/* { dg-final { scan-assembler-times "tabortdci\\." 1 } } */
-+/* { dg-final { scan-assembler-times "tabortwc\\." 1 } } */
-+/* { dg-final { scan-assembler-times "tabortwci\\." 2 } } */
-+/* { dg-final { scan-assembler-times "tcheck\\." 1 } } */
-+/* { dg-final { scan-assembler-times "trechkpt\\." 1 } } */
-+/* { dg-final { scan-assembler-times "treclaim\\." 1 } } */
-+/* { dg-final { scan-assembler-times "tsr\\." 3 } } */
-+/* { dg-final { scan-assembler-times "mfspr" 4 } } */
-+/* { dg-final { scan-assembler-times "mtspr" 4 } } */
-+
-+void use_builtins (long *p, char code, long *a, long *b)
-+{
-+ p[0] = __builtin_tbegin (0);
-+ p[1] = __builtin_tend (0);
-+ p[2] = __builtin_tendall ();
-+ p[3] = __builtin_tabort (0);
-+ p[4] = __builtin_tabort (code);
-+
-+ p[5] = __builtin_tabortdc (0xf, a[5], b[5]);
-+ p[6] = __builtin_tabortdci (0xf, a[6], 13);
-+ p[7] = __builtin_tabortwc (0xf, a[7], b[7]);
-+ p[8] = __builtin_tabortwci (0xf, a[8], 13);
-+
-+ p[9] = __builtin_tcheck (5);
-+ p[10] = __builtin_trechkpt ();
-+ p[11] = __builtin_treclaim (0);
-+ p[12] = __builtin_tresume ();
-+ p[13] = __builtin_tsuspend ();
-+ p[14] = __builtin_tsr (0);
-+ p[15] = __builtin_ttest (); /* This expands to a tabortwci. */
-+
-+
-+ p[16] = __builtin_get_texasr ();
-+ p[17] = __builtin_get_texasru ();
-+ p[18] = __builtin_get_tfhar ();
-+ p[19] = __builtin_get_tfiar ();
-+
-+ __builtin_set_texasr (a[20]);
-+ __builtin_set_texasru (a[21]);
-+ __builtin_set_tfhar (a[22]);
-+ __builtin_set_tfiar (a[23]);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/bool.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-options "-O2" } */
-+/* { dg-final { scan-assembler "eqv" } } */
-+/* { dg-final { scan-assembler "nand" } } */
-+/* { dg-final { scan-assembler "nor" } } */
-+
-+#ifndef TYPE
-+#define TYPE unsigned long
-+#endif
-+
-+TYPE op1 (TYPE a, TYPE b) { return ~(a ^ b); } /* eqv */
-+TYPE op2 (TYPE a, TYPE b) { return ~(a & b); } /* nand */
-+TYPE op3 (TYPE a, TYPE b) { return ~(a | b); } /* nor */
-+
-Index: gcc/testsuite/gcc.target/powerpc/bool2-p5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,32 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_altivec_ok } */
-+/* { dg-options "-O2 -mcpu=power5 -mabi=altivec -mno-altivec -mno-vsx" } */
-+/* { dg-final { scan-assembler "\[ \t\]and " } } */
-+/* { dg-final { scan-assembler "\[ \t\]or " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]nor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]andc " } } */
-+/* { dg-final { scan-assembler "\[ \t\]eqv " } } */
-+/* { dg-final { scan-assembler "\[ \t\]orc " } } */
-+/* { dg-final { scan-assembler "\[ \t\]nand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
-+
-+#ifndef TYPE
-+typedef int v4si __attribute__ ((vector_size (16)));
-+#define TYPE v4si
-+#endif
-+
-+#include "bool2.h"
-Index: gcc/testsuite/gcc.target/powerpc/fusion.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/fusion.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/fusion.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,24 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power7 -mtune=power8 -O3" } */
-+
-+#define LARGE 0x12345
-+
-+int fusion_uchar (unsigned char *p){ return p[LARGE]; }
-+int fusion_schar (signed char *p){ return p[LARGE]; }
-+int fusion_ushort (unsigned short *p){ return p[LARGE]; }
-+int fusion_short (short *p){ return p[LARGE]; }
-+int fusion_int (int *p){ return p[LARGE]; }
-+unsigned fusion_uns (unsigned *p){ return p[LARGE]; }
-+
-+vector double fusion_vector (vector double *p) { return p[2]; }
-+
-+/* { dg-final { scan-assembler-times "gpr load fusion" 6 } } */
-+/* { dg-final { scan-assembler-times "vector load fusion" 1 } } */
-+/* { dg-final { scan-assembler-times "lbz" 2 } } */
-+/* { dg-final { scan-assembler-times "extsb" 1 } } */
-+/* { dg-final { scan-assembler-times "lhz" 2 } } */
-+/* { dg-final { scan-assembler-times "extsh" 1 } } */
-+/* { dg-final { scan-assembler-times "lwz" 2 } } */
-Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c (.../branches/gcc-4_8-branch)
-@@ -107,8 +107,10 @@
- long a1;
- long a2;
- long a3;
-+#if _CALL_ELF != 2
- long a4;
- long a5;
-+#endif
- parm_t slot[100];
- } stack_frame_t;
-
-@@ -119,6 +121,12 @@
- vector int v;
- } vector_int_t;
-
-+#ifdef __LITTLE_ENDIAN__
-+#define MAKE_SLOT(x, y) ((long)x | ((long)y << 32))
-+#else
-+#define MAKE_SLOT(x, y) ((long)y | ((long)x << 32))
-+#endif
-+
- /* Paramter passing.
- s : gpr 3
- v : vpr 2
-@@ -226,8 +234,8 @@
- sp = __builtin_frame_address(0);
- sp = sp->backchain;
-
-- if (sp->slot[2].l != 0x100000002ULL
-- || sp->slot[4].l != 0x500000006ULL)
-+ if (sp->slot[2].l != MAKE_SLOT (1, 2)
-+ || sp->slot[4].l != MAKE_SLOT (5, 6))
- abort();
- }
-
-@@ -268,8 +276,8 @@
- sp = __builtin_frame_address(0);
- sp = sp->backchain;
-
-- if (sp->slot[4].l != 0x100000002ULL
-- || sp->slot[6].l != 0x500000006ULL)
-+ if (sp->slot[4].l != MAKE_SLOT (1, 2)
-+ || sp->slot[6].l != MAKE_SLOT (5, 6))
- abort();
- }
-
-@@ -296,8 +304,8 @@
- sp = __builtin_frame_address(0);
- sp = sp->backchain;
-
-- if (sp->slot[4].l != 0x100000002ULL
-- || sp->slot[6].l != 0x500000006ULL)
-+ if (sp->slot[4].l != MAKE_SLOT (1, 2)
-+ || sp->slot[6].l != MAKE_SLOT (5, 6))
- abort();
- }
-
-Index: gcc/testsuite/gcc.target/powerpc/direct-move-long1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+/* { dg-final { scan-assembler "mtvsrd" } } */
-+/* { dg-final { scan-assembler "mfvsrd" } } */
-+
-+/* Check code generation for direct move for long types. */
-+
-+#define TYPE long
-+#define IS_INT 1
-+#define NO_ALTIVEC 1
-+#define VSX_REG_ATTR "d"
-+
-+#include "direct-move.h"
-Index: gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target p8vector_hw } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+
-+/* Check whether we get the right bits for direct move at runtime. */
-+
-+#define TYPE double
-+#define IS_FLOAT 1
-+#define NO_ALTIVEC 1
-+#define DO_MAIN
-+#define VSX_REG_ATTR "ws"
-+
-+#include "direct-move.h"
-Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,32 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+
-+#include <altivec.h>
-+
-+typedef vector int v_sign;
-+typedef vector unsigned int v_uns;
-+
-+v_sign even_sign (v_sign a, v_sign b)
-+{
-+ return vec_vmrgew (a, b);
-+}
-+
-+v_uns even_uns (v_uns a, v_uns b)
-+{
-+ return vec_vmrgew (a, b);
-+}
-+
-+v_sign odd_sign (v_sign a, v_sign b)
-+{
-+ return vec_vmrgow (a, b);
-+}
-+
-+v_uns odd_uns (v_uns a, v_uns b)
-+{
-+ return vec_vmrgow (a, b);
-+}
-+
-+/* { dg-final { scan-assembler-times "vmrgew" 2 } } */
-+/* { dg-final { scan-assembler-times "vmrgow" 2 } } */
-Index: gcc/testsuite/gcc.target/powerpc/bool2.h
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool2.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2.h (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* Test various logical operations. */
-+
-+TYPE arg1 (TYPE p, TYPE q) { return p & q; } /* AND */
-+TYPE arg2 (TYPE p, TYPE q) { return p | q; } /* OR */
-+TYPE arg3 (TYPE p, TYPE q) { return p ^ q; } /* XOR */
-+TYPE arg4 (TYPE p) { return ~ p; } /* NOR */
-+TYPE arg5 (TYPE p, TYPE q) { return ~(p & q); } /* NAND */
-+TYPE arg6 (TYPE p, TYPE q) { return ~(p | q); } /* NOR */
-+TYPE arg7 (TYPE p, TYPE q) { return ~(p ^ q); } /* EQV */
-+TYPE arg8 (TYPE p, TYPE q) { return (~p) & q; } /* ANDC */
-+TYPE arg9 (TYPE p, TYPE q) { return (~p) | q; } /* ORC */
-+TYPE arg10(TYPE p, TYPE q) { return (~p) ^ q; } /* EQV */
-+TYPE arg11(TYPE p, TYPE q) { return p & (~q); } /* ANDC */
-+TYPE arg12(TYPE p, TYPE q) { return p | (~q); } /* ORC */
-+TYPE arg13(TYPE p, TYPE q) { return p ^ (~q); } /* EQV */
-+
-+void ptr1 (TYPE *p) { p[0] = p[1] & p[2]; } /* AND */
-+void ptr2 (TYPE *p) { p[0] = p[1] | p[2]; } /* OR */
-+void ptr3 (TYPE *p) { p[0] = p[1] ^ p[2]; } /* XOR */
-+void ptr4 (TYPE *p) { p[0] = ~p[1]; } /* NOR */
-+void ptr5 (TYPE *p) { p[0] = ~(p[1] & p[2]); } /* NAND */
-+void ptr6 (TYPE *p) { p[0] = ~(p[1] | p[2]); } /* NOR */
-+void ptr7 (TYPE *p) { p[0] = ~(p[1] ^ p[2]); } /* EQV */
-+void ptr8 (TYPE *p) { p[0] = ~(p[1]) & p[2]; } /* ANDC */
-+void ptr9 (TYPE *p) { p[0] = (~p[1]) | p[2]; } /* ORC */
-+void ptr10(TYPE *p) { p[0] = (~p[1]) ^ p[2]; } /* EQV */
-+void ptr11(TYPE *p) { p[0] = p[1] & (~p[2]); } /* ANDC */
-+void ptr12(TYPE *p) { p[0] = p[1] | (~p[2]); } /* ORC */
-+void ptr13(TYPE *p) { p[0] = p[1] ^ (~p[2]); } /* EQV */
-Index: gcc/testsuite/gcc.target/powerpc/pr48258-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,6 @@
- /* { dg-do compile } */
- /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */
- /* { dg-require-effective-target powerpc_vsx_ok } */
- /* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */
- /* { dg-final { scan-assembler-times "xvaddsp" 3 } } */
-Index: gcc/testsuite/gcc.target/powerpc/quad-atomic.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/quad-atomic.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/quad-atomic.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,67 @@
-+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target p8vector_hw } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+
-+/* Test whether we get the right bits for quad word atomic instructions. */
-+#include <stdlib.h>
-+
-+static __int128_t quad_fetch_and (__int128_t *, __int128_t value) __attribute__((__noinline__));
-+static __int128_t quad_fetch_or (__int128_t *, __int128_t value) __attribute__((__noinline__));
-+static __int128_t quad_fetch_add (__int128_t *, __int128_t value) __attribute__((__noinline__));
-+
-+static __int128_t
-+quad_fetch_and (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+static __int128_t
-+quad_fetch_or (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_or (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+static __int128_t
-+quad_fetch_add (__int128_t *ptr, __int128_t value)
-+{
-+ return __atomic_fetch_add (ptr, value, __ATOMIC_ACQUIRE);
-+}
-+
-+int
-+main (void)
-+{
-+ __int128_t result;
-+ __int128_t value;
-+ __int128_t and_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));
-+ __int128_t and_value = ((((__int128_t) 0xfffffffffffffff0ULL) << 64) | ((__int128_t) 0xfffffffffffffff0ULL));
-+ __int128_t and_exp = ((((__int128_t) 0x1234567890abcde0ULL) << 64) | ((__int128_t) 0xfedcba0987654320ULL));
-+
-+ __int128_t or_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));
-+ __int128_t or_value = ((((__int128_t) 0x0000000000000010ULL) << 64) | ((__int128_t) 0x000000000000000eULL));
-+ __int128_t or_exp = ((((__int128_t) 0x1234567890abcdffULL) << 64) | ((__int128_t) 0xfedcba098765432fULL));
-+
-+ __int128_t add_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));
-+ __int128_t add_value = ((((__int128_t) 0x0000000001000000ULL) << 64) | ((__int128_t) 0x0000001000000000ULL));
-+ __int128_t add_exp = ((((__int128_t) 0x1234567891abcdefULL) << 64) | ((__int128_t) 0xfedcba1987654321ULL));
-+
-+
-+ value = and_input;
-+ result = quad_fetch_and (&value, and_value);
-+ if (result != and_input || value != and_exp)
-+ abort ();
-+
-+ value = or_input;
-+ result = quad_fetch_or (&value, or_value);
-+ if (result != or_input || value != or_exp)
-+ abort ();
-+
-+ value = add_input;
-+ result = quad_fetch_add (&value, add_value);
-+ if (result != add_input || value != add_exp)
-+ abort ();
-+
-+ return 0;
-+}
-+
-Index: gcc/testsuite/gcc.target/powerpc/ti_math1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-options "-O2" } */
-+/* { dg-final { scan-assembler-times "addc" 1 } } */
-+/* { dg-final { scan-assembler-times "adde" 1 } } */
-+/* { dg-final { scan-assembler-times "subfc" 1 } } */
-+/* { dg-final { scan-assembler-times "subfe" 1 } } */
-+/* { dg-final { scan-assembler-not "subf " } } */
-+
-+__int128
-+add_128 (__int128 *ptr, __int128 val)
-+{
-+ return (*ptr + val);
-+}
-+
-+__int128
-+sub_128 (__int128 *ptr, __int128 val)
-+{
-+ return (*ptr - val);
-+}
-+
-Index: gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+/* { dg-final { scan-assembler-times "lq" 1 } } */
-+/* { dg-final { scan-assembler-times "stq" 1 } } */
-+/* { dg-final { scan-assembler-not "bl __atomic" } } */
-+/* { dg-final { scan-assembler-not "lqarx" } } */
-+/* { dg-final { scan-assembler-not "stqcx" } } */
-+
-+__int128
-+atomic_load_128_relaxed (__int128 *ptr)
-+{
-+ return __atomic_load_n (ptr, __ATOMIC_RELAXED);
-+}
-+
-+void
-+atomic_store_128_relaxed (__int128 *ptr, __int128 val)
-+{
-+ __atomic_store_n (ptr, val, __ATOMIC_RELAXED);
-+}
-+
-Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (.../branches/gcc-4_8-branch)
-@@ -33,15 +33,27 @@
-
-
- /* Wrapper to save the GPRs and FPRs and then jump to the real function. */
-+#if _CALL_ELF != 2
-+#define FUNC_START(NAME) \
-+ "\t.globl\t" NAME "\n\t" \
-+ ".section \".opd\",\"aw\"\n\t" \
-+ ".align 3\n" \
-+ NAME ":\n\t" \
-+ ".quad .L." NAME ",.TOC.@tocbase,0\n\t" \
-+ ".text\n\t" \
-+ ".type " NAME ", @function\n" \
-+ ".L." NAME ":\n\t"
-+#else
-+#define FUNC_START(NAME) \
-+ "\t.globl\t" NAME "\n\t" \
-+ ".text\n\t" \
-+ NAME ":\n" \
-+ "0:\taddis 2,12,(.TOC.-0b)@ha\n\t" \
-+ "addi 2,2,(.TOC.-0b)@l\n\t" \
-+ ".localentry " NAME ",.-" NAME "\n\t"
-+#endif
- #define WRAPPER(NAME) \
--__asm__ ("\t.globl\t" #NAME "_asm\n\t" \
-- ".section \".opd\",\"aw\"\n\t" \
-- ".align 3\n" \
-- #NAME "_asm:\n\t" \
-- ".quad .L." #NAME "_asm,.TOC.@tocbase,0\n\t" \
-- ".text\n\t" \
-- ".type " #NAME "_asm, @function\n" \
-- ".L." #NAME "_asm:\n\t" \
-+__asm__ (FUNC_START (#NAME "_asm") \
- "ld 11,gparms@got(2)\n\t" \
- "std 3,0(11)\n\t" \
- "std 4,8(11)\n\t" \
-@@ -75,8 +87,10 @@
- long a1;
- long a2;
- long a3;
-+#if _CALL_ELF != 2
- long a4;
- long a5;
-+#endif
- unsigned long slot[100];
- } stack_frame_t;
-
-Index: gcc/testsuite/gcc.target/powerpc/direct-move-long2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
-+/* { dg-require-effective-target p8vector_hw } */
-+/* { dg-options "-mcpu=power8 -O2" } */
-+
-+/* Check whether we get the right bits for direct move at runtime. */
-+
-+#define TYPE long
-+#define IS_INT 1
-+#define NO_ALTIVEC 1
-+#define DO_MAIN
-+#define VSX_REG_ATTR "d"
-+
-+#include "direct-move.h"
-Index: gcc/testsuite/gcc.target/powerpc/vsx-float0.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-O2 -mcpu=power7" } */
-+/* { dg-final { scan-assembler "xxlxor" } } */
-+
-+/* Test that we generate xxlor to clear a SFmode register. */
-+
-+float sum (float *p, unsigned long n)
-+{
-+ float sum = 0.0f; /* generate xxlxor instead of load */
-+ while (n-- > 0)
-+ sum += *p++;
-+
-+ return sum;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/ppc-target-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c (.../branches/gcc-4_8-branch)
-@@ -5,8 +5,7 @@
- /* { dg-final { scan-assembler-times "fabs" 3 } } */
- /* { dg-final { scan-assembler-times "fnabs" 3 } } */
- /* { dg-final { scan-assembler-times "fsel" 3 } } */
--/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */
--/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */
-+/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */
-
- double normal1 (double, double);
- double power5 (double, double) __attribute__((__target__("cpu=power5")));
-Index: gcc/testsuite/gcc.target/powerpc/pr60137.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr60137.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr60137.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,17 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_p8vector_ok } */
-+/* { dg-options "-mcpu=power8 -O3 -mno-vsx" } */
-+
-+/* target/60137, compiler got a 'could not split insn error'. */
-+
-+extern int target_flags;
-+extern char fixed_regs[53];
-+extern char call_used_regs[53];
-+
-+void init_reg_sets_1(void)
-+{
-+ int i;
-+ for (i = 0; i < 53; i++)
-+ fixed_regs[i] = call_used_regs[i] = (call_used_regs[i] &((target_flags & 0x02000000) ? 2 : 1)) != 0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/bool3.h
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool3.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool3.h (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,186 @@
-+/* Test forcing 128-bit logical types into GPR registers. */
-+
-+#if defined(NO_ASM)
-+#define FORCE_REG1(X)
-+#define FORCE_REG2(X,Y)
-+
-+#else
-+#if defined(USE_ALTIVEC)
-+#define REG_CLASS "+v"
-+#define PRINT_REG1 "# altivec reg %0"
-+#define PRINT_REG2 "# altivec reg %0, %1"
-+
-+#elif defined(USE_FPR)
-+#define REG_CLASS "+d"
-+#define PRINT_REG1 "# fpr reg %0"
-+#define PRINT_REG2 "# fpr reg %0, %1"
-+
-+#elif defined(USE_VSX)
-+#define REG_CLASS "+wa"
-+#define PRINT_REG1 "# vsx reg %x0"
-+#define PRINT_REG2 "# vsx reg %x0, %x1"
-+
-+#else
-+#define REG_CLASS "+r"
-+#define PRINT_REG1 "# gpr reg %0"
-+#define PRINT_REG2 "# gpr reg %0, %1"
-+#endif
-+
-+#define FORCE_REG1(X) __asm__ (PRINT_REG1 : REG_CLASS (X))
-+#define FORCE_REG2(X,Y) __asm__ (PRINT_REG2 : REG_CLASS (X), REG_CLASS (Y))
-+#endif
-+
-+void ptr1 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = a & b; /* AND */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr2 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = a | b; /* OR */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr3 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = a ^ b; /* XOR */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr4 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b;
-+
-+ FORCE_REG1 (a);
-+ b = ~a; /* NOR */
-+ FORCE_REG1 (b);
-+ p[0] = b;
-+}
-+
-+void ptr5 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = ~(a & b); /* NAND */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr6 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = ~(a | b); /* AND */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr7 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = ~(a ^ b); /* EQV */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr8 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = (~a) & b; /* ANDC */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr9 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = (~a) | b; /* ORC */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr10 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = (~a) ^ b; /* EQV */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr11 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = a & (~b); /* ANDC */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr12 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = a | (~b); /* ORC */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-+
-+void ptr13 (TYPE *p)
-+{
-+ TYPE a = p[1];
-+ TYPE b = p[2];
-+ TYPE c;
-+
-+ FORCE_REG2 (a, b);
-+ c = a ^ (~b); /* AND */
-+ FORCE_REG1 (c);
-+ p[0] = c;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c (.../branches/gcc-4_8-branch)
-@@ -19,19 +19,6 @@
- return __builtin_shuffle(x, (V){ 4,5,6,7, 4,5,6,7, 4,5,6,7, 4,5,6,7, });
- }
-
--V p2(V x, V y)
--{
-- return __builtin_shuffle(x, y,
-- (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 });
--
--}
--
--V p4(V x, V y)
--{
-- return __builtin_shuffle(x, y,
-- (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 });
--}
--
- V h1(V x, V y)
- {
- return __builtin_shuffle(x, y,
-@@ -72,5 +59,3 @@
- /* { dg-final { scan-assembler "vspltb" } } */
- /* { dg-final { scan-assembler "vsplth" } } */
- /* { dg-final { scan-assembler "vspltw" } } */
--/* { dg-final { scan-assembler "vpkuhum" } } */
--/* { dg-final { scan-assembler "vpkuwum" } } */
-Index: gcc/testsuite/gcc.target/powerpc/bool2-p7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,31 @@
-+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-O2 -mcpu=power7" } */
-+/* { dg-final { scan-assembler-not "\[ \t\]and " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]or " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxland " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */
-+/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */
-+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
-+
-+#ifndef TYPE
-+typedef int v4si __attribute__ ((vector_size (16)));
-+#define TYPE v4si
-+#endif
-+
-+#include "bool2.h"
-Index: gcc/testsuite/gcc.target/powerpc/ti_math2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,73 @@
-+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-options "-O2 -fno-inline" } */
-+
-+union U {
-+ __int128 i128;
-+ struct {
-+ long l1;
-+ long l2;
-+ } s;
-+};
-+
-+union U u1,u2;
-+
-+__int128
-+create_128 (long most_sig, long least_sig)
-+{
-+ union U u;
-+
-+#if __LITTLE_ENDIAN__
-+ u.s.l1 = least_sig;
-+ u.s.l2 = most_sig;
-+#else
-+ u.s.l1 = most_sig;
-+ u.s.l2 = least_sig;
-+#endif
-+ return u.i128;
-+}
-+
-+long most_sig (union U * u)
-+{
-+#if __LITTLE_ENDIAN__
-+ return (*u).s.l2;
-+#else
-+ return (*u).s.l1;
-+#endif
-+}
-+
-+long least_sig (union U * u)
-+{
-+#if __LITTLE_ENDIAN__
-+ return (*u).s.l1;
-+#else
-+ return (*u).s.l2;
-+#endif
-+}
-+
-+__int128
-+add_128 (__int128 *ptr, __int128 val)
-+{
-+ return (*ptr + val);
-+}
-+
-+__int128
-+sub_128 (__int128 *ptr, __int128 val)
-+{
-+ return (*ptr - val);
-+}
-+
-+int
-+main (void)
-+{
-+ /* Do a simple add/sub to make sure carry is happening between the dwords
-+ and that dwords are in correct endian order. */
-+ u1.i128 = create_128 (1, -1);
-+ u2.i128 = add_128 (&u1.i128, 1);
-+ if ((most_sig (&u2) != 2) || (least_sig (&u2) != 0))
-+ __builtin_abort ();
-+ u2.i128 = sub_128 (&u2.i128, 1);
-+ if ((most_sig (&u2) != 1) || (least_sig (&u2) != -1))
-+ __builtin_abort ();
-+ return 0;
-+}
-+
-Index: gcc/testsuite/gcc.target/microblaze/others/mem_reload.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,74 @@
-+/* { dg-options "-O2 -fPIC" } */
-+
-+typedef struct test_struct
-+{
-+ unsigned long long h[8];
-+ unsigned long long Nl,Nh;
-+ union {
-+ unsigned long long d[16];
-+ unsigned char p[(16*8)];
-+ } u;
-+ unsigned int num,md_len;
-+} TEST_STRUCT;
-+
-+static const unsigned long long K512[12] = {
-+ 0x428a2f98d728ae22,0x7137449123ef65cd,
-+ 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc,
-+ 0x3956c25bf348b538,0x59f111f1b605d019,
-+ 0x923f82a4af194f9b,0xab1c5ed5da6d8118,
-+ 0xd807aa98a3030242,0x12835b0145706fbe,
-+ 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2};
-+
-+#define ROTR(x,s) (((x)>>s) | (x)<<(64-s))
-+#define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
-+#define Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
-+#define Ch(x,y,z) (((x) & (y)) ^ ((~(x)) & (z)))
-+#define Maj(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
-+
-+#define ROUND_00_15(i,a,b,c,d,e,f,g,h) do { \
-+ T1 += h + Sigma1(e) + Ch(e,f,g) + K512[i]; \
-+ h = Sigma0(a) + Maj(a,b,c); \
-+ d += T1; h += T1; } while (0)
-+
-+#define ROUND_16_80(i,a,b,c,d,e,f,g,h,X) do { \
-+ T1 = X[(i)&0x0f] += s0 + s1 + X[(i+9)&0x0f]; \
-+ ROUND_00_15(i,a,b,c,d,e,f,g,h); } while (0)
-+
-+static void testfunc1 (TEST_STRUCT *ctx, const void *in, unsigned int num)
-+{
-+ const unsigned long long *W=in;
-+ unsigned long long a,b,c,d,e,f,g,h,s0,s1,T1;
-+ unsigned long long X[16];
-+ int i;
-+
-+ while (num--) {
-+
-+ T1 = X[0] = W[0]; ROUND_00_15(0,a,b,c,d,e,f,g,h);
-+ T1 = X[1] = W[1]; ROUND_00_15(1,h,a,b,c,d,e,f,g);
-+ T1 = X[2] = W[2]; ROUND_00_15(2,g,h,a,b,c,d,e,f);
-+ T1 = X[3] = W[3]; ROUND_00_15(3,f,g,h,a,b,c,d,e);
-+ T1 = X[4] = W[4]; ROUND_00_15(4,e,f,g,h,a,b,c,d);
-+ T1 = X[5] = W[5]; ROUND_00_15(5,d,e,f,g,h,a,b,c);
-+ T1 = X[6] = W[6]; ROUND_00_15(6,c,d,e,f,g,h,a,b);
-+ T1 = X[7] = W[7]; ROUND_00_15(7,b,c,d,e,f,g,h,a);
-+ T1 = X[8] = W[8]; ROUND_00_15(8,a,b,c,d,e,f,g,h);
-+ T1 = X[9] = W[9]; ROUND_00_15(9,h,a,b,c,d,e,f,g);
-+
-+ for (i=16;i<80;i+=8)
-+ {
-+ ROUND_16_80(i+0,a,b,c,d,e,f,g,h,X);
-+ }
-+
-+ ctx->h[4] += e; ctx->h[5] += f; ctx->h[6] += g; ctx->h[7] += h;
-+ }
-+}
-+
-+int testfunc2 (TEST_STRUCT *c, const void *_data, unsigned int len)
-+{
-+ const unsigned char *data=(const unsigned char *)_data;
-+
-+ unsigned char *p=(unsigned char *)c->u.p;
-+
-+ testfunc1 (c,p,0);
-+ testfunc1 (c,data,len/sizeof(c->u));
-+}
-Index: gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,8 @@
-+/* { dg-do compile } */
-+
-+void trap ()
-+{
-+ __builtin_trap ();
-+}
-+
-+/* { dg-final { scan-assembler "brki\tr0,-1" } } */
-\ No newline at end of file
-Index: gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,9 @@
-+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
-+
-+void float_func(float f1, float f2, float f3)
-+{
-+ /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-+ /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-+ if(f1==f2 && f1<=f3)
-+ print ("f1 eq f2 && f1 le f3");
-+}
-Index: gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,14 @@
- /* { dg-do compile } */
- /* { dg-options "-O2" } */
-
--#include "../../../config/aarch64/arm_neon.h"
-+#include <arm_neon.h>
-
-+/* Used to force a variable to a SIMD register. */
-+#define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \
-+ : "=w"(V1) \
-+ : "w"(V1) \
-+ : /* No clobbers */);
-+
- /* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */
-
- uint64x1_t
-@@ -31,7 +37,12 @@
- uint64x1_t
- test_vceqd_s64 (int64x1_t a, int64x1_t b)
- {
-- return vceqd_s64 (a, b);
-+ uint64x1_t res;
-+ force_simd (a);
-+ force_simd (b);
-+ res = vceqd_s64 (a, b);
-+ force_simd (res);
-+ return res;
- }
-
- /* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
-@@ -39,7 +50,11 @@
- uint64x1_t
- test_vceqzd_s64 (int64x1_t a)
- {
-- return vceqzd_s64 (a);
-+ uint64x1_t res;
-+ force_simd (a);
-+ res = vceqzd_s64 (a);
-+ force_simd (res);
-+ return res;
- }
-
- /* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
-@@ -47,21 +62,36 @@
- uint64x1_t
- test_vcged_s64 (int64x1_t a, int64x1_t b)
- {
-- return vcged_s64 (a, b);
-+ uint64x1_t res;
-+ force_simd (a);
-+ force_simd (b);
-+ res = vcged_s64 (a, b);
-+ force_simd (res);
-+ return res;
- }
-
- uint64x1_t
- test_vcled_s64 (int64x1_t a, int64x1_t b)
- {
-- return vcled_s64 (a, b);
-+ uint64x1_t res;
-+ force_simd (a);
-+ force_simd (b);
-+ res = vcled_s64 (a, b);
-+ force_simd (res);
-+ return res;
- }
-
--/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
-+/* Idiom recognition will cause this testcase not to generate
-+ the expected cmge instruction, so do not check for it. */
-
- uint64x1_t
- test_vcgezd_s64 (int64x1_t a)
- {
-- return vcgezd_s64 (a);
-+ uint64x1_t res;
-+ force_simd (a);
-+ res = vcgezd_s64 (a);
-+ force_simd (res);
-+ return res;
- }
-
- /* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
-@@ -69,7 +99,12 @@
- uint64x1_t
- test_vcged_u64 (uint64x1_t a, uint64x1_t b)
- {
-- return vcged_u64 (a, b);
-+ uint64x1_t res;
-+ force_simd (a);
-+ force_simd (b);
-+ res = vcged_u64 (a, b);
-+ force_simd (res);
-+ return res;
- }
-
- /* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
-@@ -77,13 +112,23 @@
- uint64x1_t
- test_vcgtd_s64 (int64x1_t a, int64x1_t b)
- {
-- return vcgtd_s64 (a, b);
-+ uint64x1_t res;
-+ force_simd (a);
-+ force_simd (b);
-+ res = vcgtd_s64 (a, b);
-+ force_simd (res);
-+ return res;
- }
-
- uint64x1_t
- test_vcltd_s64 (int64x1_t a, int64x1_t b)
- {
-- return vcltd_s64 (a, b);
-+ uint64x1_t res;
-+ force_simd (a);
-+ force_simd (b);
-+ res = vcltd_s64 (a, b);
-+ force_simd (res);
-+ return res;
- }
-
- /* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
-@@ -91,7 +136,11 @@
- uint64x1_t
- test_vcgtzd_s64 (int64x1_t a)
- {
-- return vcgtzd_s64 (a);
-+ uint64x1_t res;
-+ force_simd (a);
-+ res = vcgtzd_s64 (a);
-+ force_simd (res);
-+ return res;
- }
-
- /* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
-@@ -99,7 +148,12 @@
- uint64x1_t
- test_vcgtd_u64 (uint64x1_t a, uint64x1_t b)
- {
-- return vcgtd_u64 (a, b);
-+ uint64x1_t res;
-+ force_simd (a);
-+ force_simd (b);
-+ res = vcgtd_u64 (a, b);
-+ force_simd (res);
-+ return res;
- }
-
- /* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
-@@ -107,15 +161,24 @@
- uint64x1_t
- test_vclezd_s64 (int64x1_t a)
- {
-- return vclezd_s64 (a);
-+ uint64x1_t res;
-+ force_simd (a);
-+ res = vclezd_s64 (a);
-+ force_simd (res);
-+ return res;
- }
-
--/* { dg-final { scan-assembler-times "\\tcmlt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
-+/* Idiom recognition will cause this testcase not to generate
-+ the expected cmlt instruction, so do not check for it. */
-
- uint64x1_t
- test_vcltzd_s64 (int64x1_t a)
- {
-- return vcltzd_s64 (a);
-+ uint64x1_t res;
-+ force_simd (a);
-+ res = vcltzd_s64 (a);
-+ force_simd (res);
-+ return res;
- }
-
- /* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */
-@@ -179,13 +242,23 @@
- int64x1_t
- test_vtst_s64 (int64x1_t a, int64x1_t b)
- {
-- return vtstd_s64 (a, b);
-+ uint64x1_t res;
-+ force_simd (a);
-+ force_simd (b);
-+ res = vtstd_s64 (a, b);
-+ force_simd (res);
-+ return res;
- }
-
- uint64x1_t
- test_vtst_u64 (uint64x1_t a, uint64x1_t b)
- {
-- return vtstd_u64 (a, b);
-+ uint64x1_t res;
-+ force_simd (a);
-+ force_simd (b);
-+ res = vtstd_s64 (a, b);
-+ force_simd (res);
-+ return res;
- }
-
- /* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
-@@ -722,8 +795,11 @@
- return vrshld_u64 (a, b);
- }
-
--/* { dg-final { scan-assembler-times "\\tasr\\tx\[0-9\]+" 1 } } */
-+/* Other intrinsics can generate an asr instruction (vcltzd, vcgezd),
-+ so we cannot check scan-assembler-times. */
-
-+/* { dg-final { scan-assembler "\\tasr\\tx\[0-9\]+" } } */
-+
- int64x1_t
- test_vshrd_n_s64 (int64x1_t a)
- {
-Index: gcc/testsuite/gcc.target/avr/torture/pr61055.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/avr/torture/pr61055.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/avr/torture/pr61055.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,88 @@
-+/* { dg-do run } */
-+/* { dg-options { -fno-peephole2 } } */
-+
-+#include <stdlib.h>
-+
-+typedef __UINT16_TYPE__ uint16_t;
-+typedef __INT16_TYPE__ int16_t;
-+typedef __UINT8_TYPE__ uint8_t;
-+
-+uint8_t __attribute__((noinline,noclone))
-+fun_inc (uint8_t c0)
-+{
-+ register uint8_t c asm ("r15") = c0;
-+
-+ /* Force target value into R15 (lower register) */
-+ asm ("" : "+l" (c));
-+
-+ c++;
-+ if (c >= 0x80)
-+ c = 0;
-+
-+ asm ("" : "+l" (c));
-+
-+ return c;
-+}
-+
-+uint8_t __attribute__((noinline,noclone))
-+fun_dec (uint8_t c0)
-+{
-+ register uint8_t c asm ("r15") = c0;
-+
-+ /* Force target value into R15 (lower register) */
-+ asm ("" : "+l" (c));
-+
-+ c--;
-+ if (c < 0x80)
-+ c = 0;
-+
-+ asm ("" : "+l" (c));
-+
-+ return c;
-+}
-+
-+
-+uint8_t __attribute__((noinline,noclone))
-+fun_neg (uint8_t c0)
-+{
-+ register uint8_t c asm ("r15") = c0;
-+
-+ c = -c;
-+ if (c >= 0x80)
-+ c = 0;
-+
-+ return c;
-+}
-+
-+uint16_t __attribute__((noinline,noclone))
-+fun_adiw (uint16_t c0)
-+{
-+ register uint16_t c asm ("r24") = c0;
-+
-+ /* Force target value into R24 (for ADIW) */
-+ asm ("" : "+r" (c));
-+
-+ c += 2;
-+ if (c >= 0x8000)
-+ c = 0;
-+
-+ asm ("" : "+r" (c));
-+
-+ return c;
-+}
-+
-+
-+int main()
-+{
-+ if (fun_inc (0x7f) != 0)
-+ abort();
-+
-+ if (fun_neg (0x80) != 0)
-+ abort();
-+
-+ if (fun_adiw (0x7ffe) != 0)
-+ abort();
-+
-+ exit (0);
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/avr/pr60991.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/avr/pr60991.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/avr/pr60991.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* { dg-do run } */
-+/* { dg-options "-O1" } */
-+
-+/* This testcase (simplified from the original bug report) exposes
-+ PR60991. The code generated for writing the __int24 value corrupts
-+ the frame pointer if the offset is <= 63 + MAX_LD_OFFSET */
-+
-+#include <stdlib.h>
-+
-+int main(void)
-+{
-+ volatile char junk[62];
-+ junk[0] = 5;
-+ volatile __int24 staticConfig = 0;
-+
-+ if (junk[0] != 5)
-+ abort();
-+
-+ exit(0);
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59405.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59405.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59405.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,24 @@
-+/* { dg-do run } */
-+/* { dg-options "-mmmx -mfpmath=387" } */
-+
-+#include "mmx-check.h"
-+
-+#include <mmintrin.h>
-+
-+typedef float float32x2_t __attribute__ ((vector_size (8)));
-+
-+float
-+foo32x2_be (float32x2_t x)
-+{
-+ _mm_empty ();
-+ return x[1];
-+}
-+
-+static void
-+mmx_test (void)
-+{
-+ float32x2_t b = { 0.0f, 1.0f };
-+
-+ if (foo32x2_be (b) != 1.0f)
-+ abort ();
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59794-5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59794-5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-5.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* PR target/59794 */
-+/* { dg-do compile { target { ia32 } } } */
-+/* { dg-options "-O2 -mno-sse" } */
-+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */
-+
-+typedef int __v4si __attribute__ ((__vector_size__ (16)));
-+
-+extern __v4si x;
-+
-+__v4si
-+foo (void)
-+{ /* { dg-warning "SSE vector return without SSE enabled changes the ABI" } */
-+ return x;
-+}
-Index: gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* { dg-do compile { target lp64 } } */
--/* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */
-+/* { dg-options "-O2 -mavx -mabi=ms -maccumulate-outgoing-args -dp" } */
-
- typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));
-
-Index: gcc/testsuite/gcc.target/i386/pr54694.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr54694.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr54694.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O" } */
-+
-+register void *hfp __asm__("%ebp"); /* { dg-message "note: for" } */
-+
-+extern void g(void *);
-+
-+void f(int x) /* { dg-error "frame pointer required" } */
-+{
-+ g(__builtin_alloca(x));
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59470.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59470.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59470.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,17 @@
-+/* PR middle-end/58956 */
-+/* PR middle-end/59470 */
-+/* { dg-do run } */
-+/* { dg-options "-O2" } */
-+
-+int a, b, d[1024];
-+
-+int
-+main ()
-+{
-+ int c = a;
-+ asm ("{movl $6, (%2); movl $1, %0|mov dword ptr [%2], 6; mov %0, 1}"
-+ : "=r" (d[c]) : "rm" (b), "r" (&a) : "memory");
-+ if (d[0] != 1 || d[6] != 0)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59034-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59034-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59034-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+/* { dg-do compile { target { ! { ia32 } } } } */
-+/* { dg-require-effective-target maybe_x32 } */
-+/* { dg-options "-O -mx32 -mtune=corei7 -maddress-mode=short" } */
-+
-+extern int foo(int, ...);
-+int bar(void) {
-+ long double l = 1.2345E6;
-+ foo(0, l);
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr58690.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr58690.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr58690.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* { dg-do compile { target { ! { ia32 } } } } */
-+/* { dg-require-effective-target maybe_x32 } */
-+/* { dg-options "-O2 -mx32 -maddress-mode=short" } */
-+
-+struct gomp_thread
-+{
-+ char foo[41];
-+};
-+extern __thread struct gomp_thread gomp_tls_data;
-+void
-+foo (void)
-+{
-+ __builtin_memset (&gomp_tls_data, '\0', sizeof (gomp_tls_data));
-+}
-Index: gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c (.../branches/gcc-4_8-branch)
-@@ -15,7 +15,7 @@
- avx_test (void)
- {
- union256d u;
-- double e [4] __attribute__ ((aligned (8))) = {0.0};
-+ double e [4] __attribute__ ((aligned (32))) = {0.0};
-
- u.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215);
-
-Index: gcc/testsuite/gcc.target/i386/pr9771-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr9771-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr9771-1.c (.../branches/gcc-4_8-branch)
-@@ -45,7 +45,17 @@
- exit(0);
- }
-
--int main()
-+/* main usually performs dynamic realignment of the stack in case
-+ _start would fail to properly align the stack, but for dynamic
-+ stack realignment we need frame pointer which is incompatible
-+ with -ffixed-ebp and the global register var. So, cheat here
-+ and hide from the compiler that main is really main. */
-+#define ASMNAME(cname) ASMNAME2 (__USER_LABEL_PREFIX__, cname)
-+#define ASMNAME2(prefix, cname) STRING (prefix) cname
-+#define STRING(x) #x
-+int real_main() __asm (ASMNAME ("main"));
-+
-+int real_main()
- {
- test();
- return 0;
-Index: gcc/testsuite/gcc.target/i386/pr60700.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr60700.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr60700.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,59 @@
-+/* PR rtl-optimization/60700 */
-+/* { dg-do run { target ia32 } } */
-+/* { dg-options "-O3 -march=i686" } */
-+
-+int
-+__attribute__((noinline))
-+foo (void)
-+{
-+ return 0;
-+}
-+
-+void *g = (void *)1;
-+
-+struct st {
-+ char data[36]; /* must be greater than 32. */
-+};
-+
-+int
-+__attribute__((noinline))
-+repro(struct st **out)
-+{
-+ int status = 0;
-+
-+ *out = 0;
-+
-+ status = foo();
-+ if (status != 0) {
-+ return status;
-+ }
-+
-+ if (0 == g) {
-+ status = 999;
-+ return status;
-+ }
-+
-+ *out = (struct st *)__builtin_malloc(sizeof(struct st));
-+ if (0 == *out) {
-+ status = 42;
-+ return status;
-+ }
-+
-+ __builtin_memset(*out, 0, sizeof(struct st));
-+
-+ return status;
-+}
-+
-+int
-+main ()
-+{
-+ struct st *p;
-+ int ret = repro (&p);
-+ unsigned int i;
-+
-+ for (i = 0; i < sizeof (p->data)/sizeof (p->data[0]); i++)
-+ if (p->data[i] != 0)
-+ __builtin_abort ();
-+
-+ return ret;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59794-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59794-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* PR target/59794 */
-+/* { dg-prune-output "ABI for passing parameters" } */
-+/* { dg-options "-O2 -mno-sse" } */
-+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */
-+
-+typedef double __v2df __attribute__ ((__vector_size__ (16)));
-+
-+extern __v2df x;
-+
-+extern void bar (__v2df);
-+void
-+foo (void)
-+{
-+ bar (x); /* { dg-message "warning: SSE vector argument without SSE enabled changes the ABI" } */
-+}
-Index: gcc/testsuite/gcc.target/i386/pr57003.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr57003.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr57003.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,6 @@
- /* PR rtl-optimization/57003 */
- /* { dg-do run } */
--/* { dg-options "-O2" } */
-+/* { dg-options "-O2 -maccumulate-outgoing-args" } */
-
- #define N 2001
- unsigned short *b, *c, *d;
-Index: gcc/testsuite/gcc.target/i386/pr59929.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59929.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59929.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,55 @@
-+/* { dg-do run } */
-+/* { dg-options "-O0 -mno-accumulate-outgoing-args" } */
-+/* { dg-options "-O0 -mno-accumulate-outgoing-args -mx32 -maddress-mode=short" { target x32 } } */
-+
-+void
-+__attribute__ ((noinline))
-+test (float x1, float x2, float x3, float x4, float x5, float x6,
-+ float x7, float x8, float x9, float x10, float x11, float x12,
-+ float x13, float x14, float x15, float x16)
-+{
-+ if (x1 != 91
-+ || x2 != 92
-+ || x3 != 93
-+ || x4 != 94
-+ || x5 != 95
-+ || x6 != 96
-+ || x7 != 97
-+ || x8 != 98
-+ || x9 != 99
-+ || x10 != 100
-+ || x11 != 101
-+ || x12 != 102
-+ || x13 != 103
-+ || x14 != 104
-+ || x15 != 105
-+ || x16 != 106)
-+ __builtin_abort ();
-+}
-+
-+float x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13,
-+ x14, x15, x16;
-+
-+int
-+main ()
-+{
-+ x1 = 91;
-+ x2 = 92;
-+ x3 = 93;
-+ x4 = 94;
-+ x5 = 95;
-+ x6 = 96;
-+ x7 = 97;
-+ x8 = 98;
-+ x9 = 99;
-+ x10 = 100;
-+ x11 = 101;
-+ x12 = 102;
-+ x13 = 103;
-+ x14 = 104;
-+ x15 = 105;
-+ x16 = 106;
-+ test (x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13,
-+ x14, x15, x16);
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59794-6.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59794-6.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-6.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* PR target/59794 */
-+/* { dg-do compile { target { ! ia32 } } } */
-+/* { dg-options "-O2 -mno-sse" } */
-+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */
-+
-+typedef int __v4si __attribute__ ((__vector_size__ (16)));
-+
-+extern __v4si x;
-+
-+__v4si
-+foo (void)
-+{ /* { dg-error "SSE register return with SSE disabled" } */
-+ return x;
-+}
-Index: gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* { dg-do compile { target lp64 } } */
--/* { dg-options "-O0 -mavx -mabi=ms -mtune=generic -dp" } */
-+/* { dg-options "-O0 -mavx -mabi=ms -maccumulate-outgoing-args -dp" } */
-
- typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));
-
-Index: gcc/testsuite/gcc.target/i386/sse2-movapd-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c (.../branches/gcc-4_8-branch)
-@@ -25,7 +25,7 @@
- TEST (void)
- {
- union128d u;
-- double e[2] __attribute__ ((aligned (8))) = {2134.3343,1234.635654};
-+ double e[2] __attribute__ ((aligned (16))) = {2134.3343,1234.635654};
-
- u.x = test (e);
-
-Index: gcc/testsuite/gcc.target/i386/pr59021.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59021.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59021.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,23 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -mavx -mvzeroupper" } */
-+
-+extern void abort (void);
-+
-+struct S {
-+ int i1;
-+ int i2;
-+ int i3;
-+};
-+
-+typedef double v4df __attribute__ ((vector_size (32)));
-+
-+extern int foo (v4df, int i1, int i2, int i3, int i4, int i5, struct S s);
-+
-+void bar (v4df v, struct S s)
-+{
-+ int r = foo (v, 1, 2, 3, 4, 5, s);
-+ if (r)
-+ abort ();
-+}
-+
-+/* { dg-final { scan-assembler-not "vzeroupper" } } */
-Index: gcc/testsuite/gcc.target/i386/pr59034-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59034-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59034-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+/* { dg-do compile { target { ! { ia32 } } } } */
-+/* { dg-require-effective-target maybe_x32 } */
-+/* { dg-options "-O -mx32 -mtune=corei7 -maddress-mode=long" } */
-+
-+extern int foo(int, ...);
-+int bar(void) {
-+ long double l = 1.2345E6;
-+ foo(0, l);
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr60693.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr60693.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr60693.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+/* PR target/60693 */
-+/* { dg-do compile } */
-+/* { dg-options "-O0" } */
-+
-+void bar (char *);
-+
-+void
-+foo (void)
-+{
-+ char buf[4096];
-+ __builtin_memcpy (buf, (void *) 0x8000, 4096);
-+ bar (buf);
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59794-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59794-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* PR target/59794 */
-+/* { dg-prune-output "ABI for passing parameters" } */
-+/* { dg-options "-O2 -mno-avx" } */
-+/* { dg-skip-if "no AVX vector" { *-*-mingw* } } */
-+
-+typedef int __v8si __attribute__ ((__vector_size__ (32)));
-+
-+extern __v8si x;
-+
-+extern void bar (__v8si);
-+void
-+foo (void)
-+{
-+ bar (x); /* { dg-message "warning: AVX vector argument without AVX enabled changes the ABI" } */
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59839.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59839.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59839.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+/* PR target/59839 */
-+/* { dg-do compile } */
-+/* { dg-options "-O0 -mavx2" } */
-+
-+#include <x86intrin.h>
-+
-+void
-+test (const float *x)
-+{
-+ __m256i i = _mm256_set1_epi32 (1);
-+ __m256 d = _mm256_i32gather_ps (x, i, 1);
-+}
-Index: gcc/testsuite/gcc.target/i386/pr60516.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr60516.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr60516.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* PR target/60516 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2" } */
-+
-+struct S { char c[65536]; };
-+
-+__attribute__((ms_abi, thiscall)) void
-+foo (void *x, struct S y)
-+{
-+}
-+
-+__attribute__((ms_abi, fastcall)) void
-+bar (void *x, void *y, struct S z)
-+{
-+}
-+
-+__attribute__((ms_abi, stdcall)) void
-+baz (struct S x)
-+{
-+}
-Index: gcc/testsuite/gcc.target/i386/xop-frczX.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/xop-frczX.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/xop-frczX.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,60 @@
-+/* { dg-do run } */
-+/* { dg-require-effective-target xop } */
-+/* { dg-options "-O2 -mxop" } */
-+
-+#include "xop-check.h"
-+
-+#include <x86intrin.h>
-+
-+void
-+check_mm_vmfrcz_sd (__m128d __A, __m128d __B)
-+{
-+ union128d a, b, c;
-+ double d[2];
-+
-+ a.x = __A;
-+ b.x = __B;
-+ c.x = _mm_frcz_sd (__A, __B);
-+ d[0] = b.a[0] - (int)b.a[0] ;
-+ d[1] = a.a[1];
-+ if (check_union128d (c, d))
-+ abort ();
-+}
-+
-+void
-+check_mm_vmfrcz_ss (__m128 __A, __m128 __B)
-+{
-+ union128 a, b, c;
-+ float f[4];
-+
-+ a.x = __A;
-+ b.x = __B;
-+ c.x = _mm_frcz_ss (__A, __B);
-+ f[0] = b.a[0] - (int)b.a[0] ;
-+ f[1] = a.a[1];
-+ f[2] = a.a[2];
-+ f[3] = a.a[3];
-+ if (check_union128 (c, f))
-+ abort ();
-+}
-+
-+static void
-+xop_test (void)
-+{
-+ union128 a, b;
-+ union128d c,d;
-+ int i;
-+
-+ for (i = 0; i < 4; i++)
-+ {
-+ a.a[i] = i + 3.5;
-+ b.a[i] = i + 7.9;
-+ }
-+ for (i = 0; i < 2; i++)
-+ {
-+ c.a[i] = i + 3.5;
-+ d.a[i] = i + 7.987654321;
-+ }
-+ check_mm_vmfrcz_ss (a.x, b.x);
-+ check_mm_vmfrcz_sd (c.x, d.x);
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59794-7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59794-7.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-7.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+/* PR target/59794 */
-+/* { dg-options "-O2 -mno-avx" } */
-+/* { dg-skip-if "no AVX vector" { *-*-mingw* } } */
-+
-+typedef int __v8si __attribute__ ((__vector_size__ (32)));
-+
-+extern __v8si x;
-+
-+__v8si
-+foo (void)
-+{ /* { dg-warning "AVX vector return without AVX enabled changes the ABI" } */
-+ return x;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59625.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59625.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59625.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,36 @@
-+/* PR target/59625 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -mtune=atom" } */
-+
-+int
-+foo (void)
-+{
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ asm goto ("" : : : : lab);
-+ return 0;
-+lab:
-+ return 1;
-+}
-+
-+/* Verify we don't consider asm goto as a jump for four jumps limit
-+ optimization. asm goto doesn't have to contain a jump at all,
-+ the branching to labels can happen through different means. */
-+/* { dg-final { scan-assembler-not "(p2align\[^\n\r\]*\[\n\r]*\[^\n\r\]*){8}p2align" } } */
-Index: gcc/testsuite/gcc.target/i386/sse2-movapd-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c (.../branches/gcc-4_8-branch)
-@@ -25,7 +25,7 @@
- TEST (void)
- {
- union128d u;
-- double e[2] __attribute__ ((aligned (8))) = {0.0};
-+ double e[2] __attribute__ ((aligned (16))) = {0.0};
-
- u.x = _mm_set_pd (2134.3343,1234.635654);
-
-Index: gcc/testsuite/gcc.target/i386/sse-5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/sse-5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/sse-5.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,7 @@
- /* { dg-do compile } */
- /* { dg-require-effective-target ia32 } */
--/* { dg-options "-Winline -Wno-psabi -O2 -mno-sse" } */
-+/* { dg-prune-output "ABI for passing parameters" } */
-+/* { dg-options "-Winline -O2 -mno-sse" } */
-
- typedef double v2df __attribute__ ((vector_size (16)));
- v2df p;
-Index: gcc/testsuite/gcc.target/i386/pr39162.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr39162.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr39162.c (.../branches/gcc-4_8-branch)
-@@ -1,11 +1,14 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -Wno-psabi -msse2 -mno-avx" } */
-+/* { dg-prune-output "ABI for passing parameters" } */
-+/* { dg-options "-O2 -msse2 -mno-avx" } */
- /* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */
-
- typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__));
-
--__m256i
-+extern __m256i y;
-+
-+void
- bar (__m256i x) /* { dg-warning "AVX" "" } */
- {
-- return x;
-+ y = x;
- }
-Index: gcc/testsuite/gcc.target/i386/pr60909-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr60909-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr60909-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-options "-mrdrnd" } */
-+
-+extern void bar (int);
-+
-+void
-+foo (unsigned *u)
-+{
-+ int i = __builtin_ia32_rdrand32_step (u);
-+ bar (i);
-+}
-Index: gcc/testsuite/gcc.target/i386/pr58137.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr58137.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr58137.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,33 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -mavx2" } */
-+
-+typedef unsigned int U32;
-+
-+struct sv {
-+ void* sv_any;
-+ U32 sv_refcnt;
-+ U32 sv_flags;
-+};
-+typedef struct sv SV;
-+
-+struct xrv {
-+ SV * xrv_rv;
-+};
-+typedef struct xrv XRV;
-+
-+extern XRV * PL_xrv_root;
-+
-+void
-+more_xrv (void)
-+{
-+ register XRV* xrv;
-+ register XRV* xrvend;
-+ xrv = PL_xrv_root;
-+ xrvend = &xrv[200 / sizeof (XRV) - 1];
-+ while (xrv < xrvend)
-+ {
-+ xrv->xrv_rv = (SV*)(xrv + 1);
-+ xrv++;
-+ }
-+ xrv->xrv_rv = 0;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59794-4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59794-4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-4.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* PR target/59794 */
-+/* { dg-do compile { target { ia32 } } } */
-+/* { dg-options "-O2 -mno-mmx" } */
-+/* { dg-skip-if "no MMX vector" { *-*-mingw* } } */
-+
-+typedef int __v2si __attribute__ ((__vector_size__ (8)));
-+
-+extern __v2si x;
-+
-+__v2si
-+foo (void)
-+{ /* { dg-warning "MMX vector return without MMX enabled changes the ABI" } */
-+ return x;
-+}
-Index: gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* { dg-do compile { target lp64 } } */
--/* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */
-+/* { dg-options "-O2 -mavx -mabi=ms -maccumulate-outgoing-args -dp" } */
-
- typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));
-
-Index: gcc/testsuite/gcc.target/i386/pr30315.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr30315.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr30315.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,6 @@
- /* { dg-do compile } */
- /* { dg-options "-O2" } */
--/* { dg-final { scan-assembler-times "cmp" 4 } } */
-+/* { dg-final { scan-assembler-not "cmp" } } */
-
- extern void abort (void);
- int c;
-@@ -34,39 +34,10 @@
- }
- #define PLUSCCONLY(T, t) PLUSCCONLY1(T, t, a) PLUSCCONLY1(T, t, b)
-
--#define MINUSCC(T, t) \
--T minuscc##t (T a, T b) \
--{ \
-- T difference = a - b; \
-- if (difference > a) \
-- abort (); \
-- return difference; \
--}
--
--#define DECCC(T, t) \
--T deccc##t (T a, T b) \
--{ \
-- T difference = a - b; \
-- if (difference > a) \
-- c --; \
-- return difference; \
--}
--
--#define MINUSCCONLY(T, t) \
--void minuscconly##t (T a, T b) \
--{ \
-- T difference = a - b; \
-- if (difference > a) \
-- abort (); \
--}
--
- #define TEST(T, t) \
- PLUSCC(T, t) \
- PLUSCCONLY(T, t) \
-- INCCC(T, t) \
-- MINUSCC(T, t) \
-- MINUSCCONLY(T, t) \
-- DECCC(T, t)
-+ INCCC(T, t)
-
- TEST (unsigned long, l)
- TEST (unsigned int, i)
-@@ -84,14 +55,3 @@
-
- PLUSCCZEXT(a)
- PLUSCCZEXT(b)
--
--#define MINUSCCZEXT \
--unsigned long minuscczext (unsigned int a, unsigned int b) \
--{ \
-- unsigned int difference = a - b; \
-- if (difference > a) \
-- abort (); \
-- return difference; \
--}
--
--MINUSCCZEXT
-Index: gcc/testsuite/gcc.target/i386/pr43869.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr43869.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr43869.c (.../branches/gcc-4_8-branch)
-@@ -1,4 +1,5 @@
- /* { dg-do compile { target lp64 } } */
-+/* { dg-options "-maccumulate-outgoing-args" } */
-
- int __attribute__((__noinline__))
- bugged(float f1, float f2, float f3, float f4,
-Index: gcc/testsuite/gcc.target/i386/pr43546.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr43546.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr43546.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+/* PR target/43546 */
-+/* { dg-do compile } */
-+/* { dg-options "-O1" } */
-+/* { dg-additional-options "-mpreferred-stack-boundary=2 -msseregparm -msse" { target ia32 } } */
-+
-+extern void bar (double);
-+
-+void
-+foo (void)
-+{
-+ bar (1.0);
-+}
-Index: gcc/testsuite/gcc.target/i386/pr43662.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr43662.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr43662.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* { dg-do compile { target lp64 } } */
--/* { dg-options "-O2" } */
-+/* { dg-options "-O2 -maccumulate-outgoing-args" } */
-
- void __attribute__ ((ms_abi)) foo (void)
- {
-Index: gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c (.../branches/gcc-4_8-branch)
-@@ -15,7 +15,7 @@
- avx_test (void)
- {
- union256d u;
-- double e [4] __attribute__ ((aligned (8))) = {41124.234,2344.2354,8653.65635,856.43576};
-+ double e [4] __attribute__ ((aligned (32))) = {41124.234,2344.2354,8653.65635,856.43576};
-
- u.x = test (e);
-
-Index: gcc/testsuite/gcc.target/i386/nest-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/nest-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/nest-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* { dg-do compile { target llp64 } } */
-+/* { dg-options "" } */
-+
-+void foo (int i)
-+{
-+ void nested (void)
-+ {
-+ char arr[(1U << 31) + 4U];
-+ arr[i] = 0;
-+ }
-+
-+ nested ();
-+}
-+
-Index: gcc/testsuite/gcc.target/i386/pr60909-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr60909-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr60909-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-options "-mrdseed" } */
-+
-+extern void bar (int);
-+
-+void
-+foo (unsigned *u)
-+{
-+ int i = __builtin_ia32_rdseed_si_step (u);
-+ bar (i);
-+}
-Index: gcc/testsuite/gcc.target/i386/pr59794-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59794-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59794-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* PR target/59794 */
-+/* { dg-do compile { target { ia32 } } } */
-+/* { dg-options "-O2 -mno-mmx" } */
-+/* { dg-skip-if "no MMX vector" { *-*-mingw* } } */
-+
-+typedef int __v2si __attribute__ ((__vector_size__ (8)));
-+
-+extern __v2si x;
-+
-+extern void bar (__v2si);
-+void
-+foo (void)
-+{
-+ bar (x); /* { dg-message "warning: MMX vector argument without MMX enabled changes the ABI" } */
-+}
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c (.../branches/gcc-4_8-branch)
-@@ -1,7 +1,7 @@
- /* Test for cross x86_64<->w64 abi standard calls.
- */
- /* { dg-do compile } */
--/* { dg-options "-mno-sse" } */
-+/* { dg-options "-mno-sse -maccumulate-outgoing-args" } */
- #include "callabi.h"
-
- long double
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c (.../branches/gcc-4_8-branch)
-@@ -2,7 +2,7 @@
- */
- /* Origin: Kai Tietz <kai.tietz@onevision.com> */
- /* { dg-do run } */
--/* { dg-options "-std=gnu99" } */
-+/* { dg-options "-std=gnu99 -maccumulate-outgoing-args" } */
- #include "callabi.h"
-
- extern __SIZE_TYPE__ strlen (const char *);
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c (.../branches/gcc-4_8-branch)
-@@ -2,7 +2,7 @@
- */
- /* Origin: Kai Tietz <kai.tietz@onevision.com> */
- /* { dg-do run } */
--/* { dg-options "-std=gnu99" } */
-+/* { dg-options "-std=gnu99 -maccumulate-outgoing-args" } */
- #include "callabi.h"
-
- extern void abort (void);
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c (.../branches/gcc-4_8-branch)
-@@ -2,7 +2,7 @@
- */
- /* Origin: Kai Tietz <kai.tietz@onevision.com> */
- /* { dg-do run } */
--/* { dg-options "-std=gnu99" } */
-+/* { dg-options "-std=gnu99 -maccumulate-outgoing-args" } */
- #include "callabi.h"
-
- extern void abort (void);
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,6 @@
- /* Test for cross x86_64<->w64 abi va_list calls. */
- /* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
--/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
-+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */
- /* { dg-additional-sources "vaarg-4b.c" } */
-
- extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *);
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,6 @@
- /* Test for cross x86_64<->w64 abi va_list calls. */
- /* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
--/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
-+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */
- /* { dg-additional-sources "vaarg-5b.c" } */
-
- extern void __attribute__ ((sysv_abi)) abort (void);
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* Test for cross x86_64<->w64 abi va_list calls. */
--/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
-+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */
-
- #include <stdarg.h>
-
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* Test for cross x86_64<->w64 abi va_list calls. */
--/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
-+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin -maccumulate-outgoing-args" } */
-
- #include <stdarg.h>
-
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -mabi=sysv" } */
-+/* { dg-options "-O2 -mabi=sysv -maccumulate-outgoing-args" } */
-
- __attribute__ ((ms_abi))
- int foo (void)
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -mabi=sysv" } */
-+/* { dg-options "-O2 -mabi=sysv -maccumulate-outgoing-args" } */
-
- extern int glb1, gbl2, gbl3;
-
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c (.../branches/gcc-4_8-branch)
-@@ -2,7 +2,7 @@
- */
- /* Origin: Kai Tietz <kai.tietz@onevision.com> */
- /* { dg-do run } */
--/* { dg-options "-std=gnu99 -ffast-math" } */
-+/* { dg-options "-std=gnu99 -ffast-math -maccumulate-outgoing-args" } */
- #include "callabi.h"
-
- extern void abort (void);
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,6 @@
- /* Test for cross x86_64<->w64 abi standard calls via variable. */
- /* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
--/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
-+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */
- /* { dg-additional-sources "func-indirect-2b.c" } */
-
- extern void __attribute__ ((sysv_abi)) abort (void);
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c (.../branches/gcc-4_8-branch)
-@@ -2,7 +2,7 @@
- */
- /* Origin: Kai Tietz <kai.tietz@onevision.com> */
- /* { dg-do run } */
--/* { dg-options "-std=gnu99 -ffast-math" } */
-+/* { dg-options "-std=gnu99 -ffast-math -maccumulate-outgoing-args" } */
- #include "callabi.h"
-
- extern void abort (void);
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,6 @@
- /* Test for cross x86_64<->w64 abi standard calls. */
- /* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
--/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
-+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */
- /* { dg-additional-sources "func-2b.c" } */
-
- extern void __attribute__ ((sysv_abi)) abort (void);
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* Test for cross x86_64<->w64 abi standard calls via variable. */
--/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
-+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */
-
- typedef int (*func)(void *, char *, char *, short, long long);
-
-Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* Test for cross x86_64<->w64 abi standard calls. */
--/* { dg-options "-mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
-+/* { dg-options "-mabi=ms -std=gnu99 -ffast-math -fno-builtin -maccumulate-outgoing-args" } */
-
- long double func_cross (long double a, double b, float c, long d, int e,
- char f)
-Index: gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c (.../branches/gcc-4_8-branch)
-@@ -1,37 +0,0 @@
--/* This checks the availability of the XL compiler intrinsics for
-- transactional execution with the expected prototypes. */
--
--/* { dg-do compile } */
--/* { dg-options "-O3 -march=zEC12 -mzarch" } */
--
--#include <htmxlintrin.h>
--
--int a = 0;
--unsigned long g;
--
--int
--foo ()
--{
-- struct __htm_tdb *tdb_struct;
-- void * const tdb = tdb_struct;
-- long result;
-- unsigned char code;
--
-- result = __TM_simple_begin ();
-- result = __TM_begin (tdb);
-- result = __TM_end ();
-- __TM_abort ();
-- __TM_named_abort (42);
-- __TM_non_transactional_store (&g, 42);
-- result = __TM_nesting_depth (tdb);
--
-- result = __TM_is_user_abort (tdb);
-- result = __TM_is_named_user_abort (tdb, &code);
-- result = __TM_is_illegal (tdb);
-- result = __TM_is_footprint_exceeded (tdb);
-- result = __TM_is_nested_too_deep (tdb);
-- result = __TM_is_conflict (tdb);
-- result = __TM_is_failure_persistent (result);
-- result = __TM_failure_address (tdb);
-- result = __TM_failure_code (tdb);
--}
-Index: gcc/testsuite/gcc.target/s390/htm-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-1.c (.../branches/gcc-4_8-branch)
-@@ -1,73 +0,0 @@
--/* This checks the availability of the low-level builtins introduced
-- for transactional execution. */
--
--/* { dg-do compile } */
--/* { dg-options "-O3 -march=zEC12 -mzarch" } */
--
--#include <stdint.h>
--#include <htmintrin.h>
--
--int global = 0;
--uint64_t g;
--struct __htm_tdb global_tdb;
--
--int
--foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)
--{
--
-- int cc;
-- int n;
--
-- cc = __builtin_tbegin (0);
-- cc = __builtin_tbegin (tdb);
-- cc = __builtin_tbegin (&global_tdb);
--
-- cc = __builtin_tbegin_nofloat (0);
-- cc = __builtin_tbegin_nofloat (&global_tdb);
--
-- cc = __builtin_tbegin_retry (0, 42);
-- cc = __builtin_tbegin_retry (0, reg);
-- cc = __builtin_tbegin_retry (0, *mem);
-- cc = __builtin_tbegin_retry (0, global);
-- cc = __builtin_tbegin_retry (tdb, 42);
-- cc = __builtin_tbegin_retry (&global_tdb, 42);
--
-- cc = __builtin_tbegin_retry_nofloat (0, 42);
-- cc = __builtin_tbegin_retry_nofloat (0, reg);
-- cc = __builtin_tbegin_retry_nofloat (0, *mem);
-- cc = __builtin_tbegin_retry_nofloat (0, global);
-- cc = __builtin_tbegin_retry_nofloat (&global_tdb, 42);
--
-- __builtin_tbeginc ();
--
-- n = __builtin_tx_nesting_depth();
--
-- __builtin_non_tx_store(&g, 23);
-- __builtin_non_tx_store(mem64, 23);
-- __builtin_non_tx_store(&g, reg);
-- __builtin_non_tx_store(&g, *mem);
-- __builtin_non_tx_store(&g, global);
--
-- __builtin_tabort (42 + 255);
-- __builtin_tabort (reg);
-- /* { dg-final { scan-assembler-times "tabort\t255" 1 } } */
-- __builtin_tabort (reg + 255);
-- __builtin_tabort (*mem);
-- __builtin_tabort (global);
-- /* Here global + 255 gets reloaded into a reg. Better would be to
-- just reload global or *mem and get the +255 for free as address
-- arithmetic. */
-- __builtin_tabort (*mem + 255);
-- __builtin_tabort (global + 255);
--
-- __builtin_tend();
--
-- __builtin_tx_assist (23);
-- __builtin_tx_assist (reg);
-- __builtin_tx_assist (*mem);
-- __builtin_tx_assist (global);
--}
--
--/* Make sure the tdb NULL argument ends up as immediate value in the
-- instruction. */
--/* { dg-final { scan-assembler-times "tbegin\t0," 10 } } */
-Index: gcc/testsuite/gcc.target/s390/htm-nofloat-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c (.../branches/gcc-4_8-branch)
-@@ -1,55 +0,0 @@
--/* { dg-do run } */
--/* { dg-options "-O3 -mhtm -Wa,-march=zEC12,-mzarch --save-temps" } */
--
--/* __builtin_tbegin has to emit clobbers for all FPRs since the tbegin
-- instruction does not automatically preserves them. If the
-- transaction body is fully contained in a function the backend tries
-- after reload to get rid of the FPR save/restore operations
-- triggered by the clobbers. This testcase failed since the backend
-- was able to get rid of all FPR saves/restores and since these were
-- the only stack operations also of the entire stack space. So even
-- the save/restore of the stack pointer was omitted in the end.
-- However, since the frame layout has been fixed before, the prologue
-- still generated the stack pointer decrement making foo return with
-- a modified stack pointer. */
--
--void abort(void);
--
--void __attribute__((noinline))
--foo (int a)
--{
-- /* This is just to prevent the tbegin code from actually being
-- executed. That way the test may even run on machines prior to
-- zEC12. */
-- if (a == 42)
-- return;
--
-- if (__builtin_tbegin (0) == 0)
-- __builtin_tend ();
--}
--
--#ifdef __s390x__
--#define GET_STACK_POINTER(SP) \
-- asm volatile ("stg %%r15, %0" : "=QRST" (SP));
--#else
--#define GET_STACK_POINTER(SP) \
-- asm volatile ("st %%r15, %0" : "=QR" (SP));
--#endif
--
--int main(void)
--{
-- unsigned long new_sp, old_sp;
--
-- GET_STACK_POINTER (old_sp);
-- foo(42);
-- GET_STACK_POINTER (new_sp);
--
-- if (old_sp != new_sp)
-- abort ();
--
-- return 0;
--}
--
--/* Make sure no FPR saves/restores are emitted. */
--/* { dg-final { scan-assembler-not "\tstd\t" } } */
--/* { dg-final { scan-assembler-not "\tld\t" } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,27 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch" } */
-+
-+#include <stdio.h>
-+
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+inline void hp2(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((always_inline))
-+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */
-+{
-+ printf("hello, world!\n");
-+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */
-+
-+int main (void)
-+{
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,27 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch=0" } */
-+
-+#include <stdio.h>
-+
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+inline void hp2(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((always_inline))
-+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */
-+{
-+ printf("hello, world!\n");
-+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */
-+
-+int main (void)
-+{
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,27 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch=1" } */
-+
-+#include <stdio.h>
-+
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+inline void hp2(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((always_inline))
-+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */
-+{
-+ printf("hello, world!\n");
-+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */
-+
-+int main (void)
-+{
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -mzarch -mhotpatch=-1" } */
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* { dg-excess-errors "argument to '-mhotpatch=' should be a non-negative integer" } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,28 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -mzarch -mhotpatch=1000000" } */
-+
-+#include <stdio.h>
-+
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((hotpatch(1000000)))
-+void hp2(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((hotpatch(1000001)))
-+void hp3(void)
-+{ /* { dg-error "requested 'hotpatch' attribute is not a non-negative integer constant or too large .max. 1000000." } */
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -mzarch -mhotpatch=1000001" } */
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* { dg-excess-errors "argument to '-mhotpatch=' is too large .max. 1000000." } */
-Index: gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,164 @@
-+/* This checks the availability of the low-level builtins introduced
-+ for transactional execution. */
-+
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
-+
-+#include <stdint.h>
-+#include <htmintrin.h>
-+
-+int global = 0;
-+uint64_t g;
-+struct __htm_tdb global_tdb;
-+
-+int
-+foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)
-+{
-+
-+ int cc;
-+ int n;
-+
-+ __builtin_tbegin ((void *)0);
-+ __builtin_tbegin ((void *)-99999);
-+ __builtin_tbegin ((void *)99999);
-+ while (__builtin_tbegin ((void *)0) != 0)
-+ {
-+ }
-+ cc = __builtin_tbegin ((void *)0x12345678);
-+ cc = __builtin_tbegin (tdb);
-+ cc = __builtin_tbegin (&global_tdb);
-+ cc = __builtin_tbegin ((void *)(long)(reg + 0x12345678));
-+ cc = __builtin_tbegin ((void *)(long)(reg));
-+
-+ __builtin_tbegin_nofloat ((void *)0);
-+ __builtin_tbegin_nofloat ((void *)-99999);
-+ __builtin_tbegin_nofloat ((void *)99999);
-+ cc = __builtin_tbegin_nofloat ((void *)0x12345678);
-+ cc = __builtin_tbegin_nofloat (tdb);
-+ cc = __builtin_tbegin_nofloat (&global_tdb);
-+ cc = __builtin_tbegin_nofloat ((void *)(long)(reg + 0x12345678));
-+ cc = __builtin_tbegin_nofloat ((void *)(long)(reg));
-+
-+ __builtin_tbegin_retry ((void *)0, 0);
-+ cc = __builtin_tbegin_retry ((void *)0, 1);
-+ cc = __builtin_tbegin_retry ((void *)0, -1);
-+ cc = __builtin_tbegin_retry ((void *)0, 42);
-+ cc = __builtin_tbegin_retry ((void *)0, reg);
-+ cc = __builtin_tbegin_retry ((void *)0, *mem);
-+ cc = __builtin_tbegin_retry ((void *)0, global);
-+ cc = __builtin_tbegin_retry (tdb, 42);
-+ cc = __builtin_tbegin_retry (&global_tdb, 42);
-+ cc = __builtin_tbegin_retry ((void *)0x12345678, global);
-+ cc = __builtin_tbegin_retry (
-+ (void *)(long) (reg + 0x12345678), global + 1);
-+ cc = __builtin_tbegin_retry (
-+ (void *)(long)(reg), global - 1);
-+
-+ __builtin_tbegin_retry_nofloat ((void *)0, 0);
-+ cc = __builtin_tbegin_retry_nofloat ((void *)0, 1);
-+ cc = __builtin_tbegin_retry_nofloat ((void *)0, -1);
-+ cc = __builtin_tbegin_retry_nofloat ((void *)0, 42);
-+ cc = __builtin_tbegin_retry_nofloat ((void *)0, reg);
-+ cc = __builtin_tbegin_retry_nofloat ((void *)0, *mem);
-+ cc = __builtin_tbegin_retry_nofloat ((void *)0, global);
-+ cc = __builtin_tbegin_retry_nofloat (tdb, 42);
-+ cc = __builtin_tbegin_retry_nofloat (&global_tdb, 42);
-+ cc = __builtin_tbegin_retry_nofloat ((void *)0x12345678, global);
-+ cc = __builtin_tbegin_retry_nofloat (
-+ (void *)(long) (reg + 0x12345678), global + 1);
-+ cc = __builtin_tbegin_retry_nofloat (
-+ (void *)(long)(reg), global - 1);
-+
-+ __builtin_tbeginc ();
-+
-+ __builtin_tx_nesting_depth ();
-+ n = __builtin_tx_nesting_depth ();
-+
-+ __builtin_non_tx_store (mem64, 0);
-+ {
-+ const uint64_t val_var = 0x1122334455667788;
-+
-+ __builtin_non_tx_store (mem64, val_var);
-+ }
-+ __builtin_non_tx_store (mem64, (uint64_t)reg);
-+ __builtin_non_tx_store (mem64, g);
-+ __builtin_non_tx_store ((uint64_t *)0, 0);
-+ __builtin_non_tx_store ((uint64_t *)0x12345678, 0);
-+ __builtin_non_tx_store (&g, 23);
-+ __builtin_non_tx_store (&g, reg);
-+ __builtin_non_tx_store (&g, *mem);
-+ __builtin_non_tx_store (&g, global);
-+
-+ __builtin_tend();
-+
-+ __builtin_tx_assist (0);
-+ __builtin_tx_assist (1);
-+ __builtin_tx_assist (reg);
-+ __builtin_tx_assist (*mem);
-+ __builtin_tx_assist (global);
-+}
-+
-+/* The taborts must go into separate function since they are
-+ "noreturn". */
-+
-+void
-+tabort1 ()
-+{
-+ __builtin_tabort (256);
-+}
-+
-+void
-+tabort2 (int reg)
-+{
-+ __builtin_tabort (reg);
-+}
-+
-+void
-+tabort3 (int reg)
-+{
-+ /* { dg-final { scan-assembler-times "tabort\t255" 1 } } */
-+ __builtin_tabort (reg + 255);
-+}
-+
-+void
-+tabort4 (int *mem)
-+{
-+ __builtin_tabort (*mem);
-+}
-+
-+void
-+tabort5 ()
-+{
-+ __builtin_tabort (global);
-+}
-+
-+void
-+tabort6 (int *mem)
-+{
-+ /* Here global + 255 gets reloaded into a reg. Better would be to
-+ just reload global or *mem and get the +255 for free as address
-+ arithmetic. */
-+ __builtin_tabort (*mem + 255);
-+}
-+
-+void
-+tabort7 ()
-+{
-+ __builtin_tabort (global + 255);
-+}
-+
-+void
-+tabort8 ()
-+{
-+ __builtin_tabort (-1);
-+}
-+
-+
-+/* Make sure the tdb NULL argument ends up as immediate value in the
-+ instruction. */
-+/* { dg-final { scan-assembler-times "tbegin\t0," 17 } } */
-+/* { dg-final { scan-assembler-times "tbegin\t" 41 } } */
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-times "tbeginc\t" 1 } } */
-+/* { dg-final { scan-assembler-times "tabort\t" 8 } } */
-+/* { dg-final { scan-assembler "ppa\t" } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,68 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mno-hotpatch" } */
-+
-+#include <stdio.h>
-+
-+__attribute__ ((hotpatch))
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((hotpatch))
-+inline void hp2(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((hotpatch))
-+__attribute__ ((always_inline))
-+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */
-+{
-+ printf("hello, world!\n");
-+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */
-+
-+__attribute__ ((hotpatch(0)))
-+void hp4(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((hotpatch(0)))
-+inline void hp5(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((hotpatch(0)))
-+__attribute__ ((always_inline))
-+void hp6(void) /* { dg-warning "always_inline function might not be inlinable" } */
-+{
-+ printf("hello, world!\n");
-+} /* { dg-warning "function 'hp6' with the 'always_inline' attribute is not hotpatchable" } */
-+
-+__attribute__ ((hotpatch(1)))
-+void hp7(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((hotpatch(1)))
-+inline void hp8(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((hotpatch(1)))
-+__attribute__ ((always_inline))
-+void hp9(void) /* { dg-warning "always_inline function might not be inlinable" } */
-+{
-+ printf("hello, world!\n");
-+} /* { dg-warning "function 'hp9' with the 'always_inline' attribute is not hotpatchable" } */
-+
-+int main (void)
-+{
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
-+
-+void must_not_compile1 (void)
-+{
-+ __builtin_tabort (0); /* { dg-error "Invalid transaction abort code:" } */
-+}
-+
-+void must_not_compile2 (void)
-+{
-+ __builtin_tabort (255); /* { dg-error "Invalid transaction abort code:" } */
-+}
-Index: gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,23 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch" } */
-+
-+#include <stdio.h>
-+
-+int hp1(void)
-+{
-+ int nested1(void) /* { dg-warning "hotpatching is not compatible with nested functions" } */
-+ { return 1; }
-+
-+ __attribute__ ((hotpatch))
-+ int nested2(void) /* { dg-warning "hotpatching is not compatible with nested functions" } */
-+ { return 1; }
-+
-+ return nested1() - nested2();
-+}
-+
-+int main (void)
-+{
-+ return hp1();
-+}
-Index: gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+/* This checks the availability of the XL compiler intrinsics for
-+ transactional execution with the expected prototypes. */
-+
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
-+
-+#include <htmxlintrin.h>
-+
-+int a = 0;
-+unsigned long g;
-+
-+int
-+foo ()
-+{
-+ struct __htm_tdb *tdb_struct;
-+ void * const tdb = tdb_struct;
-+ long result;
-+ unsigned char code;
-+
-+ result = __TM_simple_begin ();
-+ result = __TM_begin (tdb);
-+ result = __TM_end ();
-+ __TM_abort ();
-+ __TM_named_abort (42);
-+ __TM_non_transactional_store (&g, 42);
-+ result = __TM_nesting_depth (tdb);
-+
-+ result = __TM_is_user_abort (tdb);
-+ result = __TM_is_named_user_abort (tdb, &code);
-+ result = __TM_is_illegal (tdb);
-+ result = __TM_is_footprint_exceeded (tdb);
-+ result = __TM_is_nested_too_deep (tdb);
-+ result = __TM_is_conflict (tdb);
-+ result = __TM_is_failure_persistent (result);
-+ result = __TM_failure_address (tdb);
-+ result = __TM_failure_code (tdb);
-+}
-Index: gcc/testsuite/gcc.target/s390/s390.exp
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/s390.exp (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/s390.exp (.../branches/gcc-4_8-branch)
-@@ -24,6 +24,19 @@
- # Load support procs.
- load_lib gcc-dg.exp
-
-+# Return 1 if htm (etnd - extract nesting depth) instructions are
-+# understood by the assembler and can be executed.
-+proc check_effective_target_htm { } {
-+ if { ![check_runtime s390_check_htm [subst {
-+ int main (void)
-+ {
-+ unsigned int nd;
-+ asm ("etnd %0" : "=d" (nd));
-+ return nd;
-+ }
-+ }] "-march=zEC12 -mzarch" ] } { return 0 } else { return 1 }
-+}
-+
- # If a testcase doesn't have special options, use these.
- global DEFAULT_CFLAGS
- if ![info exists DEFAULT_CFLAGS] then {
-Index: gcc/testsuite/gcc.target/s390/htm-nofloat-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c (.../branches/gcc-4_8-branch)
-@@ -1,12 +1,50 @@
--/* { dg-do compile } */
--/* { dg-options "-O3 -march=zEC12 -mzarch" } */
-+/* { dg-do run } */
-+/* { dg-require-effective-target htm } */
-+/* { dg-options "-O3 -march=zEC12 -mzarch --save-temps" } */
-
--int
--foo ()
-+/* __builtin_tbegin has to emit clobbers for all FPRs since the tbegin
-+ instruction does not automatically preserves them. If the
-+ transaction body is fully contained in a function the backend tries
-+ after reload to get rid of the FPR save/restore operations
-+ triggered by the clobbers. This testcase failed since the backend
-+ was able to get rid of all FPR saves/restores and since these were
-+ the only stack operations also of the entire stack space. So even
-+ the save/restore of the stack pointer was omitted in the end.
-+ However, since the frame layout has been fixed before, the prologue
-+ still generated the stack pointer decrement making foo return with
-+ a modified stack pointer. */
-+
-+void abort(void);
-+
-+void __attribute__((noinline))
-+foo (int a)
- {
-- __builtin_tbegin_nofloat (0);
-- __builtin_tbegin_retry_nofloat (0, 42);
-+ if (__builtin_tbegin (0) == 0)
-+ __builtin_tend ();
- }
-+
-+#ifdef __s390x__
-+#define GET_STACK_POINTER(SP) \
-+ asm volatile ("stg %%r15, %0" : "=QRST" (SP));
-+#else
-+#define GET_STACK_POINTER(SP) \
-+ asm volatile ("st %%r15, %0" : "=QR" (SP));
-+#endif
-+
-+int main(void)
-+{
-+ unsigned long new_sp, old_sp;
-+
-+ GET_STACK_POINTER (old_sp);
-+ foo(42);
-+ GET_STACK_POINTER (new_sp);
-+
-+ if (old_sp != new_sp)
-+ abort ();
-+
-+ return 0;
-+}
-+
- /* Make sure no FPR saves/restores are emitted. */
--/* { dg-final { scan-assembler-not "std" } } */
--/* { dg-final { scan-assembler-not "ld" } } */
-+/* { dg-final { scan-assembler-not "\tstd\t" } } */
-+/* { dg-final { scan-assembler-not "\tld\t" } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
-+
-+#include <stdio.h>
-+
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-times "nopr\t%r7" 12 } } */
-+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch=1 --save-temps" } */
-+
-+#include <stdio.h>
-+
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */
-+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch=0 --save-temps" } */
-+
-+#include <stdio.h>
-+
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
-+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-4.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,26 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
-+
-+#include <stdio.h>
-+
-+inline void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((always_inline))
-+void hp2(void) /* { dg-warning "always_inline function might not be inlinable" } */
-+{
-+ printf("hello, world!\n");
-+} /* { dg-warning "function 'hp2' with the 'always_inline' attribute is not hotpatchable" } */
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
-+/* { dg-final { scan-assembler-not "nop\t0" } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-5.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
-+
-+#include <stdio.h>
-+
-+__attribute__ ((hotpatch))
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-times "nopr\t%r7" 12 } } */
-+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
-Index: gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
-+
-+int
-+foo ()
-+{
-+ __builtin_tbegin_nofloat (0);
-+ __builtin_tbegin_retry_nofloat (0, 42);
-+}
-+/* Make sure no FPR saves/restores are emitted. */
-+/* { dg-final { scan-assembler-not "std" } } */
-+/* { dg-final { scan-assembler-not "ld" } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-6.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-6.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-6.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
-+
-+#include <stdio.h>
-+
-+__attribute__ ((hotpatch(1)))
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */
-+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
-Index: gcc/testsuite/gcc.target/s390/htm-builtins-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,1073 @@
-+/* Functional tests of the htm __builtin_... macros. */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target htm } */
-+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
-+
-+/* ---------------------------- included header files ---------------------- */
-+
-+#include <stdio.h>
-+#include <string.h>
-+#include <stdint.h>
-+#include <htmintrin.h>
-+
-+/* ---------------------------- local definitions -------------------------- */
-+
-+#define DEFAULT_MAX_REPETITIONS 5
-+#define DEFAULT_REQUIRED_QUORUM ((DEFAULT_MAX_REPETITIONS) - 1)
-+#define NUM_WARMUP_RUNS 10
-+
-+/* ---------------------------- local macros ------------------------------- */
-+
-+#define TEST_DF_REP(name) \
-+ { #name, name, DEFAULT_MAX_REPETITIONS, DEFAULT_REQUIRED_QUORUM }
-+#define TEST_NO_REP(name) { #name, name, 1, 1 }
-+
-+/* ---------------------------- local types -------------------------------- */
-+
-+typedef int (*test_func_t)(void);
-+
-+typedef struct
-+{
-+ const char *name;
-+ test_func_t test_func;
-+ int max_repetitions;
-+ int required_quorum;
-+} test_table_entry_t;
-+
-+/* ---------------------------- local variables ---------------------------- */
-+
-+__attribute__ ((aligned(256))) static struct __htm_tdb local_tdb256;
-+static struct __htm_tdb local_tdb;
-+static int do_dump_tdb = 0;
-+
-+/* ---------------------------- exported variables (globals) --------------- */
-+
-+__attribute__ ((aligned(256))) struct
-+{
-+ float float_1;
-+ float float_2;
-+ float float_3;
-+} global = { 1.0, 2.5, 0.0 };
-+
-+__attribute__ ((aligned(256))) struct
-+{
-+ volatile uint64_t c1;
-+ volatile uint64_t c2;
-+ volatile uint64_t c3;
-+} counters = { 0, 0, 0 };
-+
-+/* ---------------------------- local helper functions --------------------- */
-+
-+static void dump_tdb (struct __htm_tdb *tdb)
-+{
-+ unsigned char *p;
-+ int i;
-+ int j;
-+
-+ if (do_dump_tdb == 0)
-+ {
-+ return;
-+ }
-+ p = (unsigned char *)tdb;
-+ for (i = 0; i < 16; i++)
-+ {
-+ fprintf (stderr, "0x%02x ", i * 16);
-+ for (j = 0; j < 16; j++)
-+ {
-+ fprintf (stderr, "%02x", (int)p[i * 16 + j]);
-+ if (j < 15)
-+ {
-+ fprintf (stderr, " ");
-+ }
-+ if (j == 7)
-+ {
-+ fprintf (stderr, " ");
-+ }
-+ }
-+ fprintf (stderr, "\n");
-+ }
-+
-+ return;
-+}
-+
-+/* ---------------------------- local test functions ----------------------- */
-+
-+/* Check values of the constants defined in htmintrin.h. */
-+static int test_constants (void)
-+{
-+ if (_HTM_TBEGIN_STARTED != 0)
-+ {
-+ return 100 * _HTM_TBEGIN_STARTED + 1;
-+ }
-+ if (_HTM_TBEGIN_INDETERMINATE != 1)
-+ {
-+ return 100 * _HTM_TBEGIN_INDETERMINATE + 2;
-+ }
-+ if (_HTM_TBEGIN_TRANSIENT != 2)
-+ {
-+ return 100 * _HTM_TBEGIN_TRANSIENT + 3;
-+ }
-+ if (_HTM_TBEGIN_PERSISTENT != 3)
-+ {
-+ return 100 * _HTM_TBEGIN_PERSISTENT + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_ntstg_tend (void)
-+{
-+ int rc;
-+
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ if ((rc = __builtin_tbegin ((void *)0)) == 0)
-+ {
-+ __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);
-+ counters.c2 = 2;
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 5;
-+ }
-+ if (counters.c1 != 1)
-+ {
-+ return 100 * counters.c1 + 2;
-+ }
-+ if (counters.c2 != 2)
-+ {
-+ return 100 * counters.c2 + 3;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_ntstg_tabort (void)
-+{
-+ float f;
-+
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ f = 0;
-+ if (__builtin_tbegin ((void *)0) == 0)
-+ {
-+ __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);
-+ counters.c2 = 2;
-+ f = 1;
-+ __builtin_tabort (256);
-+ return 1;
-+ }
-+ if (counters.c1 != 1)
-+ {
-+ return 100 * counters.c1 + 2;
-+ }
-+ if (counters.c2 != 0)
-+ {
-+ return 100 * counters.c2 + 3;
-+ }
-+ if (f != 0)
-+ {
-+ return 100 * f + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_nofloat (void)
-+{
-+ int rc;
-+
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
-+ {
-+ __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);
-+ counters.c2 = 2;
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 5;
-+ }
-+ if (counters.c1 != 1)
-+ {
-+ return 100 * counters.c1 + 2;
-+ }
-+ if (counters.c2 != 2)
-+ {
-+ return 100 * counters.c2 + 3;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_retry (void)
-+{
-+ int rc;
-+
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ counters.c3 = 0;
-+ if ((rc = __builtin_tbegin_retry ((void *)0, 5)) == 0)
-+ {
-+ int do_abort;
-+
-+ do_abort = (counters.c1 == 0) ? 1 : 0;
-+ __builtin_non_tx_store (
-+ (uint64_t *)&counters.c1, counters.c1 + 1);
-+ if (do_abort == 1)
-+ {
-+ __builtin_tabort (256);
-+ }
-+ counters.c2 = counters.c2 + 10;
-+ __builtin_non_tx_store ((uint64_t *)&counters.c3, 3);
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 5;
-+ }
-+ if (counters.c1 != 2)
-+ {
-+ return 100 * counters.c1 + 2;
-+ }
-+ if (counters.c2 != 10)
-+ {
-+ return 100 * counters.c2 + 3;
-+ }
-+ if (counters.c3 != 3)
-+ {
-+ return 100 * counters.c3 + 6;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_retry_nofloat (void)
-+{
-+ int rc;
-+
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ counters.c3 = 0;
-+ if ((rc = __builtin_tbegin_retry_nofloat ((void *)0, 5)) == 0)
-+ {
-+ int do_abort;
-+
-+ do_abort = (counters.c1 == 0) ? 1 : 0;
-+ __builtin_non_tx_store (
-+ (uint64_t *)&counters.c1, counters.c1 + 1);
-+ if (do_abort == 1)
-+ {
-+ __builtin_tabort (256);
-+ }
-+ counters.c2 = counters.c2 + 10;
-+ __builtin_non_tx_store ((uint64_t *)&counters.c3, 3);
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 5;
-+ }
-+ if (counters.c1 != 2)
-+ {
-+ return 100 * counters.c1 + 2;
-+ }
-+ if (counters.c2 != 10)
-+ {
-+ return 100 * counters.c2 + 3;
-+ }
-+ if (counters.c3 != 3)
-+ {
-+ return 100 * counters.c3 + 6;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_aborts (void)
-+{
-+ float f;
-+ int rc;
-+
-+ f = 77;
-+ if ((rc = __builtin_tbegin ((void *)0)) == 0)
-+ {
-+ f = 88;
-+ __builtin_tabort (256);
-+ return 2;
-+ }
-+ else if (rc != 2)
-+ {
-+ return 3;
-+ }
-+ if (f != 77)
-+ {
-+ return 4;
-+ }
-+ f = 66;
-+ if ((rc = __builtin_tbegin ((void *)0)) == 0)
-+ {
-+ f = 99;
-+ __builtin_tabort (257);
-+ return 5;
-+ }
-+ else if (rc != 3)
-+ {
-+ return 100 * rc + 6;
-+ }
-+ if (f != 66)
-+ {
-+ return 100 * f + 7;
-+ }
-+ if ((rc = __builtin_tbegin ((void *)0)) == 0)
-+ {
-+ global.float_3 = global.float_1 + global.float_2;
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 8;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 9;
-+ }
-+ if (global.float_3 != global.float_1 + global.float_2)
-+ {
-+ return 100 * rc + 10;
-+ }
-+
-+ return 0;
-+}
-+
-+static __attribute__((noinline)) void indirect_abort(int abort_code)
-+{
-+ __builtin_tabort (abort_code);
-+
-+ return;
-+}
-+
-+static int test_tbegin_indirect_aborts (void)
-+{
-+ float f;
-+ int rc;
-+
-+ f = 77;
-+ if ((rc = __builtin_tbegin ((void *)0)) == 0)
-+ {
-+ f = 88;
-+ indirect_abort(256);
-+ return 2;
-+ }
-+ else if (rc != 2)
-+ {
-+ return 100 * rc + 3;
-+ }
-+ if (f != 77)
-+ {
-+ return 100 * rc + 4;
-+ }
-+ f = 66;
-+ if ((rc = __builtin_tbegin ((void *)0)) == 0)
-+ {
-+ f = 99;
-+ indirect_abort(257);
-+ return 5;
-+ }
-+ else if (rc != 3)
-+ {
-+ return 100 * rc + 6;
-+ }
-+ if (f != 66)
-+ {
-+ return 100 * f + 7;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_nofloat_aborts (void)
-+{
-+ int rc;
-+
-+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
-+ {
-+ __builtin_tabort (256);
-+ return 2;
-+ }
-+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
-+ {
-+ __builtin_tabort (257);
-+ return 1005;
-+ }
-+ else if (rc != 3)
-+ {
-+ return 1000 * rc + 6;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_nofloat_indirect_aborts (void)
-+{
-+ int rc;
-+
-+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
-+ {
-+ indirect_abort (256);
-+ return 2;
-+ }
-+ if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
-+ {
-+ indirect_abort (257);
-+ return 1005;
-+ }
-+ else if (rc != 3)
-+ {
-+ return 1000 * rc + 6;
-+ }
-+
-+ return 0;
-+}
-+
-+static
-+int _test_tbegin_retry_aborts (int retries, uint64_t abort_code)
-+{
-+ int rc;
-+
-+ counters.c1 = 0;
-+ if ((rc = __builtin_tbegin_retry ((void *)0, retries)) == 0)
-+ {
-+ __builtin_non_tx_store ((uint64_t *)&counters.c1, counters.c1 + 1);
-+ __builtin_tabort (abort_code);
-+ return 2;
-+ }
-+ else
-+ {
-+ if ((abort_code & 1) == 0)
-+ {
-+ if (rc != 2)
-+ {
-+ return 100 * rc + 2003;
-+ }
-+ else if (counters.c1 != (uint64_t)retries + 1)
-+ {
-+ return 1000 * counters.c1 + 100 * retries + 4;
-+ }
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 100 * rc + 3005;
-+ }
-+ else if (counters.c1 != 1)
-+ {
-+ return 1000 * counters.c1 + 100 * retries + 6;
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_retry_aborts (void)
-+{
-+ int rc;
-+ int retries;
-+
-+ for (retries = 1; retries <= 3; retries++)
-+ {
-+ rc = _test_tbegin_retry_aborts (retries, 256);
-+ if (rc != 0)
-+ {
-+ return 10000 + rc;
-+ }
-+ }
-+ for (retries = 1; retries <= 3; retries++)
-+ {
-+ rc = _test_tbegin_retry_aborts (retries, 257);
-+ if (rc != 0)
-+ {
-+ return 20000 + rc;
-+ }
-+ }
-+ if ((rc = __builtin_tbegin_retry ((void *)0, 5)) == 0)
-+ {
-+ global.float_3 = global.float_1 + global.float_2;
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 30000 + 100 * rc + 6;
-+ }
-+ }
-+ else
-+ {
-+ return 30000 + 100 * rc + 7;
-+ }
-+
-+ return 0;
-+}
-+
-+static int _test_tbegin_retry_nofloat_aborts (int retries, uint64_t abort_code)
-+{
-+ int rc;
-+
-+ counters.c1 = 0;
-+ if ((rc = __builtin_tbegin_retry_nofloat ((void *)0, retries)) == 0)
-+ {
-+ __builtin_non_tx_store ((uint64_t *)&counters.c1, counters.c1 + 1);
-+ __builtin_tabort (abort_code);
-+ return 2;
-+ }
-+ else
-+ {
-+ if ((abort_code & 1) == 0)
-+ {
-+ if (rc != 2)
-+ {
-+ return 100 * rc + 2003;
-+ }
-+ else if (counters.c1 != (uint64_t)retries + 1)
-+ {
-+ return 1000 * counters.c1 + 100 * retries + 4;
-+ }
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 100 * rc + 3005;
-+ }
-+ else if (counters.c1 != 1)
-+ {
-+ return 1000 * counters.c1 + 100 * retries + 6;
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_retry_nofloat_aborts (void)
-+{
-+ int rc;
-+ int retries;
-+
-+ for (retries = 1; retries <= 3; retries++)
-+ {
-+ rc = _test_tbegin_retry_nofloat_aborts (retries, 256);
-+ if (rc != 0)
-+ {
-+ return 10 * retries + rc;
-+ }
-+ }
-+ for (retries = 1; retries <= 3; retries++)
-+ {
-+ rc = _test_tbegin_retry_nofloat_aborts (retries, 257);
-+ if (rc != 0)
-+ {
-+ return 10000 + 10 * retries + rc;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_tdb (void)
-+{
-+ int rc;
-+
-+ local_tdb.format = 0;
-+ if ((rc = __builtin_tbegin (&local_tdb)) == 0)
-+ {
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 1;
-+ }
-+ if (local_tdb.format != 0)
-+ {
-+ dump_tdb (&local_tdb);
-+ return 100 * local_tdb.format + 2;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 3;
-+ }
-+ local_tdb.format = 0;
-+ if ((rc = __builtin_tbegin (&local_tdb)) == 0)
-+ {
-+ __builtin_tabort (257);
-+ return 4;
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 100 * rc + 5;
-+ }
-+ if (local_tdb.format != 1)
-+ {
-+ dump_tdb (&local_tdb);
-+ return 100 * local_tdb.format + 6;
-+ }
-+ }
-+ local_tdb256.format = 0;
-+ if ((rc = __builtin_tbegin (&local_tdb256)) == 0)
-+ {
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 1100 * rc + 1;
-+ }
-+ if (local_tdb256.format != 0)
-+ {
-+ dump_tdb (&local_tdb256);
-+ return 1100 * local_tdb256.format + 2;
-+ }
-+ }
-+ else
-+ {
-+ return 1100 * rc + 3;
-+ }
-+ local_tdb256.format = 0;
-+ if ((rc = __builtin_tbegin (&local_tdb256)) == 0)
-+ {
-+ __builtin_tabort (257);
-+ return 2004;
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 2100 * rc + 5;
-+ }
-+ if (local_tdb256.format != 1)
-+ {
-+ dump_tdb (&local_tdb256);
-+ return 2100 * local_tdb256.format + 6;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_nofloat_tdb (void)
-+{
-+ int rc;
-+
-+ local_tdb.format = 0;
-+ if ((rc = __builtin_tbegin_nofloat (&local_tdb)) == 0)
-+ {
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 1;
-+ }
-+ if (local_tdb.format != 0)
-+ {
-+ dump_tdb (&local_tdb);
-+ return 100 * local_tdb.format + 2;
-+ }
-+ }
-+ else
-+ {
-+ return 3;
-+ }
-+ local_tdb.format = 0;
-+ if ((rc = __builtin_tbegin_nofloat (&local_tdb)) == 0)
-+ {
-+ __builtin_tabort (257);
-+ return 4;
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 100 * rc + 5;
-+ }
-+ if (local_tdb.format != 1)
-+ {
-+ dump_tdb (&local_tdb);
-+ return 100 * local_tdb.format + 6;
-+ }
-+ }
-+ local_tdb256.format = 0;
-+ if ((rc = __builtin_tbegin_nofloat (&local_tdb256)) == 0)
-+ {
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 1100 * rc + 1;
-+ }
-+ if (local_tdb256.format != 0)
-+ {
-+ dump_tdb (&local_tdb256);
-+ return 1100 * local_tdb256.format + 2;
-+ }
-+ }
-+ else
-+ {
-+ return 1003;
-+ }
-+ local_tdb256.format = 0;
-+ if ((rc = __builtin_tbegin_nofloat (&local_tdb256)) == 0)
-+ {
-+ __builtin_tabort (257);
-+ return 2004;
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 2100 * rc + 5;
-+ }
-+ if (local_tdb256.format != 1)
-+ {
-+ dump_tdb (&local_tdb256);
-+ return 2100 * local_tdb256.format + 6;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_retry_tdb (void)
-+{
-+ int rc;
-+
-+ local_tdb256.format = 0;
-+ if ((rc = __builtin_tbegin_retry (&local_tdb256, 2)) == 0)
-+ {
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 1100 * rc + 1;
-+ }
-+ if (local_tdb256.format != 0)
-+ {
-+ dump_tdb (&local_tdb256);
-+ return 1100 * local_tdb256.format + 2;
-+ }
-+ }
-+ else
-+ {
-+ return 1003;
-+ }
-+ local_tdb256.format = 0;
-+ if ((rc = __builtin_tbegin_retry (&local_tdb256, 2)) == 0)
-+ {
-+ __builtin_tabort (257);
-+ return 2004;
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 2100 * rc + 5;
-+ }
-+ if (local_tdb256.format != 1)
-+ {
-+ dump_tdb (&local_tdb256);
-+ return 2100 * local_tdb256.format + 6;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_retry_nofloat_tdb (void)
-+{
-+ int rc;
-+
-+ local_tdb.format = 0;
-+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb, 2)) == 0)
-+ {
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 1;
-+ }
-+ if (local_tdb.format != 0)
-+ {
-+ dump_tdb (&local_tdb);
-+ return 100 * local_tdb.format + 2;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 3;
-+ }
-+ local_tdb.format = 0;
-+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb, 2)) == 0)
-+ {
-+ __builtin_tabort (257);
-+ return 4;
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 100 * rc + 5;
-+ }
-+ if (local_tdb.format != 1)
-+ {
-+ dump_tdb (&local_tdb);
-+ return 100 * local_tdb.format + 6;
-+ }
-+ }
-+ local_tdb256.format = 0;
-+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb256, 2)) == 0)
-+ {
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 1100 * rc + 1;
-+ }
-+ if (local_tdb256.format != 0)
-+ {
-+ dump_tdb (&local_tdb256);
-+ return 1100 * local_tdb256.format + 2;
-+ }
-+ }
-+ else
-+ {
-+ return 1100 * rc + 3;
-+ }
-+ local_tdb256.format = 0;
-+ if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb256, 2)) == 0)
-+ {
-+ __builtin_tabort (257);
-+ return 2004;
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 2100 * rc + 5;
-+ }
-+ if (local_tdb256.format != 1)
-+ {
-+ dump_tdb (&local_tdb256);
-+ return 2100 * local_tdb256.format + 6;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_etnd (void)
-+{
-+ int rc;
-+
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ counters.c3 = 0;
-+ if ((rc = __builtin_tbegin ((void *)0)) == 0)
-+ {
-+ counters.c1 = __builtin_tx_nesting_depth ();
-+ if (__builtin_tbegin ((void *)0) == 0)
-+ {
-+ counters.c2 = __builtin_tx_nesting_depth ();
-+ if (__builtin_tbegin ((void *)0) == 0)
-+ {
-+ counters.c3 = __builtin_tx_nesting_depth ();
-+ __builtin_tend ();
-+ }
-+ __builtin_tend ();
-+ }
-+ __builtin_tend ();
-+ }
-+ else
-+ {
-+ return 100 * rc + 1;
-+ }
-+ if (counters.c1 != 1)
-+ {
-+ return 100 * counters.c1 + 2;
-+ }
-+ if (counters.c2 != 2)
-+ {
-+ return 100 * counters.c2 + 3;
-+ }
-+ if (counters.c3 != 3)
-+ {
-+ return 100 * counters.c3 + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbeginc (void)
-+{
-+ int rc;
-+
-+ counters.c1 = 0;
-+ __builtin_tbeginc ();
-+ counters.c1 = 1;
-+ rc = __builtin_tend ();
-+ if (rc != 0)
-+ {
-+ return 10000 * rc + 1;
-+ }
-+ if (counters.c1 != 1)
-+ {
-+ return 100000 * counters.c1 + 3;
-+ }
-+
-+ return 0;
-+}
-+
-+/* ---------------------------- local testing framework functions ---------- */
-+
-+static int run_one_test (const test_table_entry_t *test_entry)
-+{
-+ int do_print_passes;
-+ int succeeded;
-+ int rc;
-+ int i;
-+
-+ /* Warmup run to get all necessary data and instruction pages into the page
-+ * tables. */
-+ {
-+ int run;
-+
-+ do_dump_tdb = 0;
-+ for (run = 0; run < NUM_WARMUP_RUNS; run++)
-+ {
-+ test_entry->test_func ();
-+ }
-+ do_dump_tdb = 1;
-+ }
-+ do_print_passes = (
-+ test_entry->required_quorum != 1 ||
-+ test_entry->max_repetitions != 1);
-+ printf ("RRR RUN %s\n", test_entry->name);
-+ if (do_print_passes == 1)
-+ {
-+ printf (
-+ " (requires %d successful out of %d runs)\n",
-+ test_entry->required_quorum,
-+ test_entry->max_repetitions);
-+ }
-+ succeeded = 0;
-+ rc = 0;
-+ for (rc = 0, i = 0; i < test_entry->max_repetitions; i++)
-+ {
-+ if (do_print_passes == 1)
-+ {
-+ if (i == 0)
-+ {
-+ printf (" ");
-+ }
-+ else
-+ {
-+ printf (",");
-+ }
-+ }
-+ rc = test_entry->test_func ();
-+ if (rc == 0)
-+ {
-+ if (do_print_passes == 1)
-+ {
-+ printf (" success");
-+ }
-+ succeeded++;
-+ if (succeeded >= test_entry->required_quorum)
-+ {
-+ break;
-+ }
-+ }
-+ else
-+ {
-+ printf (" failed (rc = %d)", rc);
-+ }
-+ }
-+ if (do_print_passes == 1 || rc != 0)
-+ {
-+ printf ("\n");
-+ }
-+ if (succeeded >= test_entry->required_quorum)
-+ {
-+ printf ("+++ OK %s\n", test_entry->name);
-+
-+ return 0;
-+ }
-+ else
-+ {
-+ printf ("--- FAIL %s\n", test_entry->name);
-+
-+ return (rc != 0) ? rc : -1;
-+ }
-+}
-+
-+static int run_all_tests (const test_table_entry_t *test_table)
-+{
-+ const test_table_entry_t *test;
-+ int rc;
-+
-+ for (
-+ rc = 0, test = &test_table[0];
-+ test->test_func != NULL && rc == 0; test++)
-+ {
-+ rc = run_one_test (test);
-+ }
-+
-+ return rc;
-+}
-+
-+/* ---------------------------- interface functions ------------------------ */
-+
-+int main (void)
-+{
-+ const test_table_entry_t test_table[] = {
-+ TEST_NO_REP (test_constants),
-+ TEST_DF_REP (test_tbegin_ntstg_tend),
-+ TEST_DF_REP (test_tbegin_ntstg_tabort),
-+ TEST_DF_REP (test_tbegin_nofloat),
-+ TEST_NO_REP (test_tbegin_retry),
-+ TEST_NO_REP (test_tbegin_retry_nofloat),
-+ TEST_DF_REP (test_tbegin_aborts),
-+ TEST_DF_REP (test_tbegin_indirect_aborts),
-+ TEST_DF_REP (test_tbegin_nofloat_aborts),
-+ TEST_DF_REP (test_tbegin_nofloat_indirect_aborts),
-+ TEST_NO_REP (test_tbegin_retry_aborts),
-+ TEST_NO_REP (test_tbegin_retry_nofloat_aborts),
-+ TEST_DF_REP (test_tbegin_tdb),
-+ TEST_DF_REP (test_tbegin_nofloat_tdb),
-+ TEST_NO_REP (test_tbegin_retry_tdb),
-+ TEST_NO_REP (test_tbegin_retry_nofloat_tdb),
-+ TEST_DF_REP (test_etnd),
-+ TEST_DF_REP (test_tbeginc),
-+ { (void *)0, 0, 0 }
-+ };
-+
-+ {
-+ int rc;
-+
-+ rc = run_all_tests (test_table);
-+
-+ return rc;
-+ }
-+}
-Index: gcc/testsuite/gcc.target/s390/hotpatch-7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-7.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-7.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
-+
-+#include <stdio.h>
-+
-+__attribute__ ((hotpatch(0)))
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
-+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
-Index: gcc/testsuite/gcc.target/s390/htm-builtins-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/htm-builtins-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/htm-builtins-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,682 @@
-+/* Functional tests of the htm __TM_... macros. */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target htm } */
-+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
-+
-+/* ---------------------------- included header files ---------------------- */
-+
-+#include <stdio.h>
-+#include <string.h>
-+#include <inttypes.h>
-+#include <htmxlintrin.h>
-+
-+/* ---------------------------- local definitions -------------------------- */
-+
-+#define DEFAULT_MAX_REPETITIONS 5
-+#define DEFAULT_REQUIRED_QUORUM ((DEFAULT_MAX_REPETITIONS) - 1)
-+#define DEFAULT_ABORT_ADDRESS (0x12345678u)
-+
-+/* ---------------------------- local macros ------------------------------- */
-+
-+#define TEST_DF_REP(name) \
-+ { #name, name, DEFAULT_MAX_REPETITIONS, DEFAULT_REQUIRED_QUORUM }
-+#define TEST_NO_REP(name) { #name, name, 1, 1 }
-+
-+/* ---------------------------- local types -------------------------------- */
-+
-+typedef int (*test_func_t)(void);
-+
-+typedef struct
-+{
-+ const char *name;
-+ test_func_t test_func;
-+ int max_repetitions;
-+ int required_quorum;
-+} test_table_entry_t;
-+
-+typedef enum
-+{
-+ ABORT_T_SYSTEM = 0,
-+ ABORT_T_USER = 1,
-+} abort_user_t;
-+
-+typedef enum
-+{
-+ ABORT_T_NONE = 0,
-+ ABORT_T_ILLEGAL,
-+ ABORT_T_FOOTPRINT_EXCEEDED,
-+ ABORT_T_NESTED_TOO_DEEP,
-+ ABORT_T_CONFLICT,
-+
-+ ABORT_T_INVALID_ABORT_CODE
-+} abort_t;
-+
-+/* ---------------------------- local variables ---------------------------- */
-+
-+__attribute__ ((aligned(256))) static struct __htm_tdb local_tdb256;
-+static struct __htm_tdb local_tdb;
-+
-+static abort_t const abort_classes[] =
-+{
-+ ABORT_T_INVALID_ABORT_CODE,
-+ ABORT_T_NONE,
-+ ABORT_T_NONE,
-+ ABORT_T_NONE,
-+
-+ ABORT_T_ILLEGAL,
-+ ABORT_T_NONE,
-+ ABORT_T_NONE,
-+ ABORT_T_FOOTPRINT_EXCEEDED,
-+
-+ ABORT_T_FOOTPRINT_EXCEEDED,
-+ ABORT_T_CONFLICT,
-+ ABORT_T_CONFLICT,
-+ ABORT_T_ILLEGAL,
-+
-+ ABORT_T_NONE,
-+ ABORT_T_NESTED_TOO_DEEP,
-+ ABORT_T_NONE,
-+ ABORT_T_NONE,
-+
-+ ABORT_T_NONE
-+};
-+
-+static size_t num_abort_classes = sizeof(abort_classes) / sizeof(abort_t);
-+
-+/* ---------------------------- exported variables (globals) --------------- */
-+
-+int global_int = 0;
-+uint64_t global_u64 = 0;
-+float global_float_1 = 1.0;
-+float global_float_2 = 2.5;
-+float global_float_3 = 0.0;
-+__attribute__ ((aligned(256))) struct
-+{
-+ volatile uint64_t c1;
-+ volatile uint64_t c2;
-+ volatile uint64_t c3;
-+} counters = { 0, 0, 0 };
-+
-+/* ---------------------------- local helper functions --------------------- */
-+
-+static void dump_tdb(struct __htm_tdb *tdb)
-+{
-+ unsigned char *p;
-+ int i;
-+ int j;
-+
-+ p = (unsigned char *)tdb;
-+ for (i = 0; i < 16; i++)
-+ {
-+ fprintf(stderr, "0x%02x ", i * 16);
-+ for (j = 0; j < 16; j++)
-+ {
-+ fprintf(stderr, "%02x", (int)p[i * 16 + j]);
-+ if (j < 15)
-+ {
-+ fprintf(stderr, " ");
-+ }
-+ if (j == 7)
-+ {
-+ fprintf(stderr, " ");
-+ }
-+ }
-+ fprintf(stderr, "\n");
-+ }
-+
-+ return;
-+}
-+
-+static void make_fake_tdb(struct __htm_tdb *tdb)
-+{
-+ memset(tdb, 0, sizeof(*tdb));
-+ tdb->format = 1;
-+ tdb->nesting_depth = 1;
-+ tdb->atia = DEFAULT_ABORT_ADDRESS;
-+ tdb->abort_code = 11;
-+
-+ return;
-+}
-+
-+static int check_abort_code_in_tdb(struct __htm_tdb *tdb, uint64_t abort_code)
-+{
-+ long expect_rc;
-+ long rc;
-+
-+ if (abort_code != 0)
-+ {
-+ long addr;
-+
-+ addr = __TM_failure_address(&local_tdb);
-+ if (addr != DEFAULT_ABORT_ADDRESS)
-+ {
-+ return 11;
-+ }
-+ }
-+ {
-+ long long tdb_abort_code;
-+
-+ tdb_abort_code = __TM_failure_code(tdb);
-+ if ((uint64_t)tdb_abort_code != abort_code)
-+ {
-+ fprintf(
-+ stderr, "tm_ac %" PRIu64 ", ac %" PRIu64
-+ ", tdb_ac %" PRIu64 "\n",
-+ (uint64_t)tdb_abort_code, abort_code,
-+ (uint64_t)tdb->abort_code);
-+ return 10;
-+ }
-+ }
-+ expect_rc = (abort_code >= 256) ? 1 : 0;
-+ rc = __TM_is_user_abort(tdb);
-+ if (rc != expect_rc)
-+ {
-+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
-+ return 1;
-+ }
-+ {
-+ unsigned char code;
-+
-+ code = 0xffu;
-+ rc = __TM_is_named_user_abort(tdb, &code);
-+ if (rc != expect_rc)
-+ {
-+ fprintf(
-+ stderr, "rc %ld, expect_rc %ld\n", rc,
-+ expect_rc);
-+ return 2;
-+ }
-+ if (expect_rc == 1 && code != abort_code - 256)
-+ {
-+ return 3;
-+ }
-+ }
-+ if (abort_code > (uint64_t)num_abort_classes)
-+ {
-+ abort_code = (uint64_t)num_abort_classes;
-+ }
-+ expect_rc = (abort_classes[abort_code] == ABORT_T_ILLEGAL) ? 1 : 0;
-+ rc = __TM_is_illegal(tdb);
-+ if (rc != expect_rc)
-+ {
-+ dump_tdb(tdb);
-+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
-+ return 4;
-+ }
-+ expect_rc =
-+ (abort_classes[abort_code] == ABORT_T_FOOTPRINT_EXCEEDED) ?
-+ 1 : 0;
-+ rc = __TM_is_footprint_exceeded(tdb);
-+ if (rc != expect_rc)
-+ {
-+ dump_tdb(tdb);
-+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
-+ return 5;
-+ }
-+ expect_rc =
-+ (abort_classes[abort_code] == ABORT_T_NESTED_TOO_DEEP) ? 1 : 0;
-+ rc = __TM_is_nested_too_deep(tdb);
-+ if (rc != expect_rc)
-+ {
-+ dump_tdb(tdb);
-+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
-+ return 6;
-+ }
-+ expect_rc = (abort_classes[abort_code] == ABORT_T_CONFLICT) ? 1 : 0;
-+ rc = __TM_is_conflict(tdb);
-+ if (rc != expect_rc)
-+ {
-+ dump_tdb(tdb);
-+ fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
-+ return 7;
-+ }
-+
-+ return 0;
-+}
-+
-+/* ---------------------------- local test functions ----------------------- */
-+
-+/* Not a test; make sure that the involved global cachelines are reserved for
-+ * writing. */
-+static int init_cache(void)
-+{
-+ make_fake_tdb(&local_tdb);
-+ make_fake_tdb(&local_tdb256);
-+ global_int = 0;
-+ global_u64 = 0;
-+ global_float_1 = 1.0;
-+ global_float_2 = 2.5;
-+ global_float_3 = 0.0;
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ counters.c3 = 0;
-+
-+ return 0;
-+}
-+
-+static int test_abort_classification(void)
-+{
-+ int i;
-+
-+ make_fake_tdb(&local_tdb);
-+ for (i = 0; i <= 256; i++)
-+ {
-+ int rc;
-+
-+ local_tdb.abort_code = (uint64_t)i;
-+ rc = check_abort_code_in_tdb(&local_tdb, (uint64_t)i);
-+ if (rc != 0)
-+ {
-+ return 100 * i + rc;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_cc_classification(void)
-+{
-+ long rc;
-+
-+ rc = __TM_is_failure_persistent(0);
-+ if (rc != 0)
-+ {
-+ return 1;
-+ }
-+ rc = __TM_is_failure_persistent(1);
-+ if (rc != 0)
-+ {
-+ return 2;
-+ }
-+ rc = __TM_is_failure_persistent(2);
-+ if (rc != 0)
-+ {
-+ return 3;
-+ }
-+ rc = __TM_is_failure_persistent(3);
-+ if (rc != 1)
-+ {
-+ return 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_ntstg_tend(void)
-+{
-+ long rc;
-+
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ if ((rc = __TM_simple_begin()) == 0)
-+ {
-+ __TM_non_transactional_store((uint64_t *)&counters.c1, 1);
-+ counters.c2 = 2;
-+ rc = __TM_end();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 5;
-+ }
-+ if (counters.c1 != 1)
-+ {
-+ return 100 * counters.c1 + 2;
-+ }
-+ if (counters.c2 != 2)
-+ {
-+ return 100 * counters.c2 + 3;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_ntstg_tabort(void)
-+{
-+ register float f;
-+
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ f = 0;
-+ if (__TM_simple_begin() == 0)
-+ {
-+ __TM_non_transactional_store((uint64_t *)&counters.c1, 1);
-+ counters.c2 = 2;
-+ f = 1;
-+ __TM_named_abort(0);
-+ return 1;
-+ }
-+ if (counters.c1 != 1)
-+ {
-+ return 100 * counters.c1 + 2;
-+ }
-+ if (counters.c2 != 0)
-+ {
-+ return 100 * counters.c2 + 3;
-+ }
-+ if (f != 0)
-+ {
-+ return 100 * f + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_aborts(void)
-+{
-+ float f;
-+ long rc;
-+
-+ f = 77;
-+ if ((rc = __TM_simple_begin()) == 0)
-+ {
-+ f = 88;
-+ __TM_abort();
-+ return 2;
-+ }
-+ else if (rc != 2)
-+ {
-+ return 3;
-+ }
-+ if (f != 77)
-+ {
-+ return 4;
-+ }
-+ f = 66;
-+ if ((rc = __TM_simple_begin()) == 0)
-+ {
-+ f = 99;
-+ __TM_named_abort(3);
-+ return 5;
-+ }
-+ else if (rc != 3)
-+ {
-+ return 100 * rc + 6;
-+ }
-+ if (f != 66)
-+ {
-+ return 100 * f + 7;
-+ }
-+ if ((rc = __TM_simple_begin()) == 0)
-+ {
-+ global_float_3 = global_float_1 + global_float_2;
-+ rc = __TM_end();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 8;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 9;
-+ }
-+ if (global_float_3 != global_float_1 + global_float_2)
-+ {
-+ return 100 * rc + 10;
-+ }
-+
-+ return 0;
-+}
-+
-+static int test_tbegin_tdb(void)
-+{
-+ long rc;
-+
-+ local_tdb.format = 0;
-+ if ((rc = __TM_begin(&local_tdb)) == 0)
-+ {
-+ rc = __TM_end();
-+ if (rc != 0)
-+ {
-+ return 100 * rc + 1;
-+ }
-+ if (local_tdb.format != 0)
-+ {
-+ dump_tdb(&local_tdb);
-+ return 100 * local_tdb.format + 2;
-+ }
-+ }
-+ else
-+ {
-+ return 100 * rc + 3;
-+ }
-+ local_tdb.format = 0;
-+ if ((rc = __TM_begin(&local_tdb)) == 0)
-+ {
-+ __TM_named_abort(1);
-+ return 4;
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 100 * rc + 5;
-+ }
-+ if (local_tdb.format != 1)
-+ {
-+ dump_tdb(&local_tdb);
-+ return 100 * local_tdb.format + 6;
-+ }
-+ }
-+ local_tdb256.format = 0;
-+ if ((rc = __TM_begin(&local_tdb256)) == 0)
-+ {
-+ rc = __TM_end();
-+ if (rc != 0)
-+ {
-+ return 1100 * rc + 1;
-+ }
-+ if (local_tdb256.format != 0)
-+ {
-+ dump_tdb(&local_tdb256);
-+ return 1100 * local_tdb256.format + 2;
-+ }
-+ }
-+ else
-+ {
-+ return 1100 * rc + 3;
-+ }
-+#if 1 /*!!!does not work*/
-+ local_tdb256.format = 0;
-+ if ((rc = __TM_begin(&local_tdb256)) == 0)
-+ {
-+ __TM_named_abort(1);
-+ return 2004;
-+ }
-+ else
-+ {
-+ if (rc != 3)
-+ {
-+ return 2100 * rc + 5;
-+ }
-+ if (local_tdb256.format != 1)
-+ {
-+ dump_tdb(&local_tdb256);
-+ return 2100 * local_tdb256.format + 6;
-+ }
-+ }
-+#endif
-+
-+ return 0;
-+}
-+
-+static int test_etnd(void)
-+{
-+ long rc;
-+
-+ {
-+ long nd;
-+
-+ make_fake_tdb(&local_tdb);
-+ local_tdb.nesting_depth = 0;
-+ nd = __TM_nesting_depth(&local_tdb);
-+ if (nd != 0)
-+ {
-+ return 1;
-+ }
-+ local_tdb.nesting_depth = 7;
-+ nd = __TM_nesting_depth(&local_tdb);
-+ if (nd != 7)
-+ {
-+ return 7;
-+ }
-+ local_tdb.format = 0;
-+ nd = __TM_nesting_depth(&local_tdb);
-+ if (nd != 0)
-+ {
-+ return 2;
-+ }
-+ }
-+ counters.c1 = 0;
-+ counters.c1 = 0;
-+ counters.c2 = 0;
-+ counters.c3 = 0;
-+ if ((rc = __TM_simple_begin()) == 0)
-+ {
-+ counters.c1 = __TM_nesting_depth(0);
-+ if (__TM_simple_begin() == 0)
-+ {
-+ counters.c2 = __TM_nesting_depth(0);
-+ if (__TM_simple_begin() == 0)
-+ {
-+ counters.c3 = __TM_nesting_depth(0);
-+ __TM_end();
-+ }
-+ __TM_end();
-+ }
-+ __TM_end();
-+ }
-+ else
-+ {
-+ return 100 * rc + 1;
-+ }
-+ if (counters.c1 != 1)
-+ {
-+ return 100 * counters.c1 + 2;
-+ }
-+ if (counters.c2 != 2)
-+ {
-+ return 100 * counters.c2 + 3;
-+ }
-+ if (counters.c3 != 3)
-+ {
-+ return 100 * counters.c3 + 4;
-+ }
-+
-+ return 0;
-+}
-+
-+/* ---------------------------- local testing framework functions ---------- */
-+
-+static int run_one_test(const test_table_entry_t *test_entry)
-+{
-+ int do_print_passes;
-+ int succeeded;
-+ int rc;
-+ int i;
-+
-+ do_print_passes = (
-+ test_entry->required_quorum != 1 ||
-+ test_entry->max_repetitions != 1);
-+ printf("RRR RUN %s\n", test_entry->name);
-+ if (do_print_passes == 1)
-+ {
-+ printf(
-+ " (requires %d successful out of %d runs)\n",
-+ test_entry->required_quorum,
-+ test_entry->max_repetitions);
-+ }
-+ succeeded = 0;
-+ rc = 0;
-+ for (rc = 0, i = 0; i < test_entry->max_repetitions; i++)
-+ {
-+ if (do_print_passes == 1)
-+ {
-+ if (i == 0)
-+ {
-+ printf(" ");
-+ }
-+ else
-+ {
-+ printf(",");
-+ }
-+ }
-+ rc = test_entry->test_func();
-+ if (rc == 0)
-+ {
-+ if (do_print_passes == 1)
-+ {
-+ printf(" success");
-+ }
-+ succeeded++;
-+ if (succeeded >= test_entry->required_quorum)
-+ {
-+ break;
-+ }
-+ }
-+ else
-+ {
-+ printf(" failed (rc = %d)", rc);
-+ }
-+ }
-+ if (do_print_passes == 1 || rc != 0)
-+ {
-+ printf("\n");
-+ }
-+ if (succeeded >= test_entry->required_quorum)
-+ {
-+ printf("+++ OK %s\n", test_entry->name);
-+
-+ return 0;
-+ }
-+ else
-+ {
-+ printf("--- FAIL %s\n", test_entry->name);
-+
-+ return (rc != 0) ? rc : -1;
-+ }
-+}
-+
-+static int run_all_tests(const test_table_entry_t *test_table)
-+{
-+ const test_table_entry_t *test;
-+ int rc;
-+
-+ for (
-+ rc = 0, test = &test_table[0];
-+ test->test_func != NULL && rc == 0; test++)
-+ {
-+ rc = run_one_test(test);
-+ }
-+
-+ return rc;
-+}
-+
-+/* ---------------------------- interface functions ------------------------ */
-+
-+int main(void)
-+{
-+ const test_table_entry_t test_table[] = {
-+ TEST_NO_REP(init_cache),
-+ TEST_NO_REP(test_abort_classification),
-+ TEST_NO_REP(test_cc_classification),
-+ TEST_DF_REP(test_tbegin_ntstg_tend),
-+ TEST_DF_REP(test_tbegin_ntstg_tabort),
-+ TEST_DF_REP(test_tbegin_aborts),
-+ TEST_DF_REP(test_tbegin_tdb),
-+ TEST_DF_REP(test_etnd),
-+ { (void *)0, 0, 0 }
-+ };
-+
-+ {
-+ int rc;
-+
-+ rc = run_all_tests(test_table);
-+
-+ return rc;
-+ }
-+}
-Index: gcc/testsuite/gcc.target/s390/hotpatch-8.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-8.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-8.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,28 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
-+
-+#include <stdio.h>
-+
-+__attribute__ ((hotpatch))
-+inline void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+__attribute__ ((hotpatch))
-+__attribute__ ((always_inline))
-+void hp2(void) /* { dg-warning "always_inline function might not be inlinable" } */
-+{
-+ printf("hello, world!\n");
-+} /* { dg-warning "function 'hp2' with the 'always_inline' attribute is not hotpatchable" } */
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
-+/* { dg-final { scan-assembler-not "nop\t0" } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-9.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-9.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-9.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch=1 --save-temps" } */
-+
-+#include <stdio.h>
-+
-+__attribute__ ((hotpatch(2)))
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-times "nopr\t%r7" 2 } } */
-+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-10.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-10.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-10.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mno-hotpatch --save-temps" } */
-+
-+#include <stdio.h>
-+
-+__attribute__ ((hotpatch(2)))
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-times "nopr\t%r7" 2 } } */
-+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-11.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-11.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-11.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mhotpatch -mno-hotpatch --save-temps" } */
-+
-+#include <stdio.h>
-+
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
-+/* { dg-final { scan-assembler-not "nop\t0" } } */
-Index: gcc/testsuite/gcc.target/s390/hotpatch-12.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/s390/hotpatch-12.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/s390/hotpatch-12.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* Functional tests for the function hotpatching feature. */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O3 -mzarch -mno-hotpatch -mhotpatch=1 --save-temps" } */
-+
-+#include <stdio.h>
-+
-+void hp1(void)
-+{
-+ printf("hello, world!\n");
-+}
-+
-+int main (void)
-+{
-+ return 0;
-+}
-+
-+/* Check number of occurences of certain instructions. */
-+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */
-+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
-Index: gcc/testsuite/gcc.target/mips/bswap-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/mips/bswap-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/mips/bswap-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+/* { dg-options "isa_rev>=2" } */
-+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
-+
-+NOMIPS16 unsigned short
-+foo (unsigned short x)
-+{
-+ return ((x << 8) & 0xff00) | ((x >> 8) & 0xff);
-+}
-+
-+/* { dg-final { scan-assembler "\twsbh\t" } } */
-Index: gcc/testsuite/gcc.target/mips/bswap-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/mips/bswap-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/mips/bswap-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,9 @@
-+/* { dg-options "isa_rev>=2" } */
-+
-+NOMIPS16 unsigned short
-+foo (unsigned short x)
-+{
-+ return __builtin_bswap16 (x);
-+}
-+
-+/* { dg-final { scan-assembler "\twsbh\t" } } */
-Index: gcc/testsuite/gcc.target/mips/pr59137.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/mips/pr59137.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/mips/pr59137.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,34 @@
-+/* { dg-do run } */
-+/* { dg-options "-mno-plt" } */
-+
-+extern void abort (void);
-+
-+struct lispstruct
-+{
-+ int e;
-+ int t;
-+};
-+
-+struct lispstruct Cnil_body;
-+struct lispstruct Ct_body;
-+int nvalues;
-+
-+struct lispstruct * __attribute__ ((noinline))
-+fLlistp (struct lispstruct *x0)
-+{
-+ if (x0 == &Cnil_body
-+ || (((unsigned long) x0 >= 0x80000000) ? 0
-+ : (!x0->e ? (x0 != &Cnil_body) : x0->t)))
-+ x0 = &Ct_body;
-+ else
-+ x0 = &Cnil_body;
-+ nvalues = 1;
-+ return x0;
-+}
-+
-+int main ()
-+{
-+ if (fLlistp ((struct lispstruct *) 0xa0000001) != &Cnil_body)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.target/mips/bswap-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/mips/bswap-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/mips/bswap-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* { dg-options "isa_rev>=2" } */
-+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
-+
-+NOMIPS16 unsigned int
-+foo (unsigned int x)
-+{
-+ return (((x << 24) & 0xff000000)
-+ | ((x << 8) & 0xff0000)
-+ | ((x >> 8) & 0xff00)
-+ | ((x >> 24) & 0xff));
-+}
-+
-+/* { dg-final { scan-assembler "\twsbh\t" } } */
-+/* { dg-final { scan-assembler "\tror\t" } } */
-Index: gcc/testsuite/gcc.target/mips/bswap-4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/mips/bswap-4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/mips/bswap-4.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+/* { dg-options "isa_rev>=2" } */
-+
-+NOMIPS16 unsigned int
-+foo (unsigned int x)
-+{
-+ return __builtin_bswap32 (x);
-+}
-+
-+/* { dg-final { scan-assembler "\twsbh\t" } } */
-+/* { dg-final { scan-assembler "\tror\t" } } */
-Index: gcc/testsuite/gcc.target/mips/bswap-5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/mips/bswap-5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/mips/bswap-5.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* { dg-options "isa_rev>=2 -mgp64" } */
-+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
-+
-+typedef unsigned long long uint64_t;
-+
-+NOMIPS16 uint64_t
-+foo (uint64_t x)
-+{
-+ return (((x << 56) & 0xff00000000000000ull)
-+ | ((x << 40) & 0xff000000000000ull)
-+ | ((x << 24) & 0xff0000000000ull)
-+ | ((x << 8) & 0xff00000000ull)
-+ | ((x >> 8) & 0xff000000)
-+ | ((x >> 24) & 0xff0000)
-+ | ((x >> 40) & 0xff00)
-+ | ((x >> 56) & 0xff));
-+}
-+
-+/* { dg-final { scan-assembler "\tdsbh\t" } } */
-+/* { dg-final { scan-assembler "\tdshd\t" } } */
-Index: gcc/testsuite/gcc.target/mips/bswap-6.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/mips/bswap-6.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/mips/bswap-6.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+/* { dg-options "isa_rev>=2 -mgp64" } */
-+
-+typedef unsigned long long uint64_t;
-+
-+NOMIPS16 uint64_t
-+foo (uint64_t x)
-+{
-+ return __builtin_bswap64 (x);
-+}
-+
-+/* { dg-final { scan-assembler "\tdsbh\t" } } */
-+/* { dg-final { scan-assembler "\tdshd\t" } } */
-Index: gcc/testsuite/gcc.target/sh/pr51244-19.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/sh/pr51244-19.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/sh/pr51244-19.c (.../branches/gcc-4_8-branch)
-@@ -22,11 +22,16 @@
- unwanted sequences. Thus, if we see any movt insns, something is not
- working as expected. This test requires -O2 because the T bit stores
- in question will be eliminated in additional insn split passes after
-- reload. */
-+ reload.
-+
-+ Notice: When this test case was initially added, the T bit optimization
-+ was buggy and this test case resulted in wrong code. The movt
-+ instructions actually have to be present in this case to get
-+ correct code. */
- /* { dg-do compile { target "sh*-*-*" } } */
- /* { dg-options "-O2" } */
- /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
--/* { dg-final { scan-assembler-not "movt" } } */
-+/* { dg-final { scan-assembler "movt" } } */
-
- struct request
- {
-Index: gcc/testsuite/gcc.target/sh/pr54089-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/sh/pr54089-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.target/sh/pr54089-3.c (.../branches/gcc-4_8-branch)
-@@ -5,7 +5,7 @@
- /* { dg-options "-O1" } */
- /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2" "-m2e*" } } */
- /* { dg-final { scan-assembler-not "and" } } */
--/* { dg-final { scan-assembler-not "31" } } */
-+/* { dg-final { scan-assembler-not "#31" } } */
-
- int
- test00 (unsigned int a, int* b, int c, int* d, unsigned int e)
-Index: gcc/testsuite/go.test/go-test.exp
-===================================================================
---- a/src/gcc/testsuite/go.test/go-test.exp (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/go.test/go-test.exp (.../branches/gcc-4_8-branch)
-@@ -333,17 +333,16 @@
- }
-
- if { ( [file tail $test] == "select2.go" \
-- || [file tail $test] == "stack.go" ) \
-+ || [file tail $test] == "stack.go" \
-+ || [file tail $test] == "peano.go" ) \
- && ! [check_effective_target_split_stack] } {
-- # chan/select2.go fails on targets without split stack,
-- # because they allocate a large stack segment that blows
-- # out the memory calculations.
-+ # These tests fails on targets without split stack.
- untested $name
- continue
- }
-
-- if { [file tail $test] == "rotate.go" } {
-- # This test produces a temporary file that takes too long
-+ if [string match "*go.test/test/rotate\[0123\].go" $test] {
-+ # These tests produces a temporary file that takes too long
- # to compile--5 minutes on my laptop without optimization.
- # When compiling without optimization it tests nothing
- # useful, since the point of the test is to see whether
-Index: gcc/testsuite/lib/target-supports.exp
-===================================================================
---- a/src/gcc/testsuite/lib/target-supports.exp (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/lib/target-supports.exp (.../branches/gcc-4_8-branch)
-@@ -1311,6 +1311,32 @@
- return 0
- }
-
-+# Return 1 if the target supports executing power8 vector instructions, 0
-+# otherwise. Cache the result.
-+
-+proc check_p8vector_hw_available { } {
-+ return [check_cached_effective_target p8vector_hw_available {
-+ # Some simulators are known to not support VSX/power8 instructions.
-+ # For now, disable on Darwin
-+ if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
-+ expr 0
-+ } else {
-+ set options "-mpower8-vector"
-+ check_runtime_nocache p8vector_hw_available {
-+ int main()
-+ {
-+ #ifdef __MACH__
-+ asm volatile ("xxlorc vs0,vs0,vs0");
-+ #else
-+ asm volatile ("xxlorc 0,0,0");
-+ #endif
-+ return 0;
-+ }
-+ } $options
-+ }
-+ }]
-+}
-+
- # Return 1 if the target supports executing VSX instructions, 0
- # otherwise. Cache the result.
-
-@@ -1858,6 +1884,32 @@
- }]
- }
-
-+# Return 1 if the target supports executing DFP hardware instructions,
-+# 0 otherwise. Cache the result.
-+
-+proc check_dfp_hw_available { } {
-+ return [check_cached_effective_target dfp_hw_available {
-+ # For now, disable on Darwin
-+ if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
-+ expr 0
-+ } else {
-+ check_runtime_nocache dfp_hw_available {
-+ volatile _Decimal64 r;
-+ volatile _Decimal64 a = 4.0DD;
-+ volatile _Decimal64 b = 2.0DD;
-+ int main()
-+ {
-+ asm volatile ("dadd %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
-+ asm volatile ("dsub %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
-+ asm volatile ("dmul %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
-+ asm volatile ("ddiv %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
-+ return 0;
-+ }
-+ } "-mcpu=power6 -mhard-float"
-+ }
-+ }]
-+}
-+
- # Return 1 if the target supports compiling and assembling UCN, 0 otherwise.
-
- proc check_effective_target_ucn_nocache { } {
-@@ -2672,6 +2724,33 @@
- }
- }
-
-+# Return 1 if this is a PowerPC target supporting -mpower8-vector
-+
-+proc check_effective_target_powerpc_p8vector_ok { } {
-+ if { ([istarget powerpc*-*-*]
-+ && ![istarget powerpc-*-linux*paired*])
-+ || [istarget rs6000-*-*] } {
-+ # AltiVec is not supported on AIX before 5.3.
-+ if { [istarget powerpc*-*-aix4*]
-+ || [istarget powerpc*-*-aix5.1*]
-+ || [istarget powerpc*-*-aix5.2*] } {
-+ return 0
-+ }
-+ return [check_no_compiler_messages powerpc_p8vector_ok object {
-+ int main (void) {
-+#ifdef __MACH__
-+ asm volatile ("xxlorc vs0,vs0,vs0");
-+#else
-+ asm volatile ("xxlorc 0,0,0");
-+#endif
-+ return 0;
-+ }
-+ } "-mpower8-vector"]
-+ } else {
-+ return 0
-+ }
-+}
-+
- # Return 1 if this is a PowerPC target supporting -mvsx
-
- proc check_effective_target_powerpc_vsx_ok { } {
-@@ -2699,6 +2778,27 @@
- }
- }
-
-+# Return 1 if this is a PowerPC target supporting -mhtm
-+
-+proc check_effective_target_powerpc_htm_ok { } {
-+ if { ([istarget powerpc*-*-*]
-+ && ![istarget powerpc-*-linux*paired*])
-+ || [istarget rs6000-*-*] } {
-+ # HTM is not supported on AIX yet.
-+ if { [istarget powerpc*-*-aix*] } {
-+ return 0
-+ }
-+ return [check_no_compiler_messages powerpc_htm_ok object {
-+ int main (void) {
-+ asm volatile ("tbegin. 0");
-+ return 0;
-+ }
-+ } "-mhtm"]
-+ } else {
-+ return 0
-+ }
-+}
-+
- # Return 1 if this is a PowerPC target supporting -mcpu=cell.
-
- proc check_effective_target_powerpc_ppu_ok { } {
-@@ -2794,6 +2894,22 @@
- }
- }
-
-+# Return 1 if this is a PowerPC target using the ELFv2 ABI.
-+
-+proc check_effective_target_powerpc_elfv2 { } {
-+ if { [istarget powerpc*-*-*] } {
-+ return [check_no_compiler_messages powerpc_elfv2 object {
-+ #if _CALL_ELF != 2
-+ #error not ELF v2 ABI
-+ #else
-+ int dummy;
-+ #endif
-+ }]
-+ } else {
-+ return 0
-+ }
-+}
-+
- # Return 1 if this is a SPU target with a toolchain that
- # supports automatic overlay generation.
-
-@@ -4499,7 +4615,9 @@
- switch $arg {
- "vmx_hw" { set selected [check_vmx_hw_available] }
- "vsx_hw" { set selected [check_vsx_hw_available] }
-+ "p8vector_hw" { set selected [check_p8vector_hw_available] }
- "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] }
-+ "dfp_hw" { set selected [check_dfp_hw_available] }
- "named_sections" { set selected [check_named_sections_available] }
- "gc_sections" { set selected [check_gc_sections_available] }
- "cxa_atexit" { set selected [check_cxa_atexit_available] }
-@@ -4520,7 +4638,9 @@
- switch $arg {
- "vmx_hw" { return 1 }
- "vsx_hw" { return 1 }
-+ "p8vector_hw" { return 1 }
- "ppc_recip_hw" { return 1 }
-+ "dfp_hw" { return 1 }
- "named_sections" { return 1 }
- "gc_sections" { return 1 }
- "cxa_atexit" { return 1 }
-@@ -5077,7 +5197,9 @@
- }
-
- lappend DEFAULT_VECTCFLAGS "-maltivec"
-- if [check_vsx_hw_available] {
-+ if [check_p8vector_hw_available] {
-+ lappend DEFAULT_VECTCFLAGS "-mpower8-vector" "-mno-allow-movmisalign"
-+ } elseif [check_vsx_hw_available] {
- lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
- }
-
-Index: gcc/testsuite/gfortran.dg/shape_8.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/shape_8.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/shape_8.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+! { dg-do compile }
-+!
-+! PR 60450: [4.7/4.8 Regression] ICE with SHAPE intrinsic
-+!
-+! Contributed by Dave Allured <dave.allured@noaa.gov>
-+
-+ real, allocatable :: x(:,:)
-+ allocate (x(3,2), source=99.)
-+ print *, shape (x / 10.0)
-+end
-Index: gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+! { dg-do compile }
-+!
-+! PR fortran/58803
-+!
-+! Contributed by Vittorio Zecca
-+!
-+! Was before ICEing due to a double free
-+!
-+ type t
-+ procedure(real), pointer, nopass :: f1, f2
-+ end type
-+ end
-Index: gcc/testsuite/gfortran.dg/where_4.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/where_4.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/where_4.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,18 @@
-+! { dg-do compile }
-+! PR 60522 - this used to ICE.
-+! Original test case Roger Ferrer Ibanez
-+subroutine foo(a, b)
-+ implicit none
-+ integer, dimension(:), intent(inout) :: a
-+ integer, dimension(:), intent(in) :: b
-+
-+ where (b(:) > 0)
-+ where (b(:) > 100)
-+ a(lbound(a, 1):ubound(a, 1)) = b(lbound(b, 1):ubound(b, 1)) * b(lbound(b, 1):ubound(b, 1)) - 100
-+ elsewhere
-+ a(lbound(a, 1):ubound(a, 1)) = b(lbound(b, 1):ubound(b, 1)) * b(lbound(b, 1):ubound(b, 1))
-+ end where
-+ elsewhere
-+ a(lbound(a, 1):ubound(a, 1)) = - b(lbound(b, 1):ubound(b, 1)) * b(lbound(b, 1):ubound(b, 1))
-+ end where
-+end subroutine foo
-Index: gcc/testsuite/gfortran.dg/gomp/pr59467.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/gomp/pr59467.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/gomp/pr59467.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,24 @@
-+! PR libgomp/59467
-+! { dg-do compile }
-+! { dg-options "-fopenmp" }
-+ FUNCTION t()
-+ INTEGER :: a, b, t
-+ a = 0
-+ b = 0
-+ !$OMP PARALLEL REDUCTION(+:b)
-+ !$OMP SINGLE ! { dg-error "is not threadprivate or private in outer context" }
-+ !$OMP ATOMIC WRITE
-+ a = 6
-+ !$OMP END SINGLE COPYPRIVATE (a)
-+ b = a
-+ !$OMP END PARALLEL
-+ t = b
-+ b = 0
-+ !$OMP PARALLEL REDUCTION(+:b)
-+ !$OMP SINGLE
-+ !$OMP ATOMIC WRITE
-+ b = 6
-+ !$OMP END SINGLE COPYPRIVATE (b)
-+ !$OMP END PARALLEL
-+ t = t + b
-+ END FUNCTION
-Index: gcc/testsuite/gfortran.dg/allocate_class_3.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/allocate_class_3.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/allocate_class_3.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,107 @@
-+! { dg-do run }
-+! Tests the fix for PR59414, comment #3, in which the allocate
-+! expressions were not correctly being stripped to provide the
-+! vpointer as an lhs to the pointer assignment of the vptr from
-+! the SOURCE expression.
-+!
-+! Contributed by Antony Lewis <antony@cosmologist.info>
-+!
-+module ObjectLists
-+ implicit none
-+
-+ type :: t
-+ integer :: i
-+ end type
-+
-+ type Object_array_pointer
-+ class(t), pointer :: p(:)
-+ end type
-+
-+contains
-+
-+ subroutine AddArray1 (P, Pt)
-+ class(t) :: P(:)
-+ class(Object_array_pointer) :: Pt
-+
-+ select type (Pt)
-+ class is (Object_array_pointer)
-+ if (associated (Pt%P)) deallocate (Pt%P)
-+ allocate(Pt%P(1:SIZE(P)), source=P)
-+ end select
-+ end subroutine
-+
-+ subroutine AddArray2 (P, Pt)
-+ class(t) :: P(:)
-+ class(Object_array_pointer) :: Pt
-+
-+ select type (Pt)
-+ type is (Object_array_pointer)
-+ if (associated (Pt%P)) deallocate (Pt%P)
-+ allocate(Pt%P(1:SIZE(P)), source=P)
-+ end select
-+ end subroutine
-+
-+ subroutine AddArray3 (P, Pt)
-+ class(t) :: P
-+ class(Object_array_pointer) :: Pt
-+
-+ select type (Pt)
-+ class is (Object_array_pointer)
-+ if (associated (Pt%P)) deallocate (Pt%P)
-+ allocate(Pt%P(1:4), source=P)
-+ end select
-+ end subroutine
-+
-+ subroutine AddArray4 (P, Pt)
-+ type(t) :: P(:)
-+ class(Object_array_pointer) :: Pt
-+
-+ select type (Pt)
-+ class is (Object_array_pointer)
-+ if (associated (Pt%P)) deallocate (Pt%P)
-+ allocate(Pt%P(1:SIZE(P)), source=P)
-+ end select
-+ end subroutine
-+end module
-+
-+ use ObjectLists
-+ type(Object_array_pointer), pointer :: Pt
-+ class(t), pointer :: P(:)
-+
-+ allocate (P(2), source = [t(1),t(2)])
-+ allocate (Pt, source = Object_array_pointer(NULL()))
-+ call AddArray1 (P, Pt)
-+ select type (x => Pt%p)
-+ type is (t)
-+ if (any (x%i .ne. [1,2])) call abort
-+ end select
-+ deallocate (P)
-+ deallocate (pt)
-+
-+ allocate (P(3), source = [t(3),t(4),t(5)])
-+ allocate (Pt, source = Object_array_pointer(NULL()))
-+ call AddArray2 (P, Pt)
-+ select type (x => Pt%p)
-+ type is (t)
-+ if (any (x%i .ne. [3,4,5])) call abort
-+ end select
-+ deallocate (P)
-+ deallocate (pt)
-+
-+ allocate (Pt, source = Object_array_pointer(NULL()))
-+ call AddArray3 (t(6), Pt)
-+ select type (x => Pt%p)
-+ type is (t)
-+ if (any (x%i .ne. [6,6,6,6])) call abort
-+ end select
-+ deallocate (pt)
-+
-+ allocate (Pt, source = Object_array_pointer(NULL()))
-+ call AddArray4 ([t(7), t(8)], Pt)
-+ select type (x => Pt%p)
-+ type is (t)
-+ if (any (x%i .ne. [7,8])) call abort
-+ end select
-+ deallocate (pt)
-+ end
-+
-Index: gcc/testsuite/gfortran.dg/reshape_6.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/reshape_6.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/reshape_6.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,19 @@
-+! { dg-do compile }
-+! PR fortran/58989
-+!
-+program test
-+
-+ real(8), dimension(4,4) :: fluxes
-+ real(8), dimension(2,2,2,2) :: f
-+ integer, dimension(3) :: dmmy
-+ integer, parameter :: indx(4)=(/2,2,2,2/)
-+
-+ fluxes = 1
-+
-+ dmmy = (/2,2,2/)
-+
-+ f = reshape(fluxes,(/dmmy,2/)) ! Caused an ICE
-+ f = reshape(fluxes,(/2,2,2,2/)) ! Works as expected
-+ f = reshape(fluxes,indx) ! Works as expected
-+
-+end program test
-Index: gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,36 @@
-+! { dg-do compile }
-+!
-+! PR fortran/58007
-+! Unresolved fiixup while loading a module.
-+!
-+! This tests that the specification expression A%MAX_DEGREE in module BSR is
-+! correctly loaded and resolved in program MAIN.
-+!
-+! Original testcase from Daniel Shapiro <shapero@uw.edu>
-+
-+module matrix
-+ type :: sparse_matrix
-+ integer :: max_degree
-+ end type
-+end module
-+
-+module bsr
-+ use matrix
-+
-+ type, extends(sparse_matrix) :: bsr_matrix
-+ end type
-+
-+ integer :: i1
-+ integer :: i2
-+ integer :: i3
-+contains
-+ function get_neighbors (A)
-+ type(bsr_matrix), intent(in) :: A
-+ integer :: get_neighbors(A%max_degree)
-+ end function
-+end module
-+
-+program main
-+ use matrix
-+ use bsr
-+end
-Index: gcc/testsuite/gfortran.dg/init_flag_12.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/init_flag_12.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/init_flag_12.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+! { dg-do compile }
-+! { dg-options "-fno-automatic -finit-local-zero" }
-+!
-+! PR 55907: [4.7/4.8/4.9 Regression] ICE with -fno-automatic -finit-local-zero
-+!
-+! Contributed by J.R. Garcia <garcia.espinosa.jr@gmail.com>
-+
-+subroutine cchaine (i)
-+ implicit none
-+ integer :: i
-+ character(len=i) :: chaine
-+ write(*,*) chaine
-+end subroutine
-Index: gcc/testsuite/gfortran.dg/derived_external_function_1.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/derived_external_function_1.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/derived_external_function_1.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,27 @@
-+! { dg-do run }
-+!
-+! PR fortran/58771
-+!
-+! Contributed by Vittorio Secca <zeccav@gmail.com>
-+!
-+! ICEd on the write statement with f() because the derived type backend
-+! declaration not built.
-+!
-+module m
-+ type t
-+ integer(4) g
-+ end type
-+end
-+
-+type(t) function f() result(ff)
-+ use m
-+ ff%g = 42
-+end
-+
-+ use m
-+ character (20) :: line1, line2
-+ type(t) f
-+ write (line1, *) f()
-+ write (line2, *) 42_4
-+ if (line1 .ne. line2) call abort
-+end
-Index: gcc/testsuite/gfortran.dg/implicit_pure_4.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/implicit_pure_4.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/implicit_pure_4.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+! { dg-do compile }
-+!
-+! PR fortran/60543
-+! PR fortran/60283
-+!
-+module m
-+contains
-+ REAL(8) FUNCTION random()
-+ CALL RANDOM_NUMBER(random)
-+ END FUNCTION random
-+ REAL(8) FUNCTION random2()
-+ block
-+ block
-+ block
-+ CALL RANDOM_NUMBER(random2)
-+ end block
-+ end block
-+ end block
-+ END FUNCTION random2
-+end module m
-+
-+! { dg-final { scan-module-absence "m" "IMPLICIT_PURE" } }
-Index: gcc/testsuite/gfortran.dg/null_6.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/null_6.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/null_6.f90 (.../branches/gcc-4_8-branch)
-@@ -30,5 +30,5 @@
-
- subroutine test_PR34547_3 ()
- integer, allocatable :: i(:)
-- print *, NULL(i)
-+ print *, NULL(i) ! { dg-error "Invalid context for NULL" }
- end subroutine test_PR34547_3
-Index: gcc/testsuite/gfortran.dg/fmt_en.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/fmt_en.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/fmt_en.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,186 @@
-+! { dg-do run { target fd_truncate } }
-+! PR60128 Invalid outputs with EN descriptors
-+! Test case provided by Walt Brainerd.
-+program pr60128
-+use ISO_FORTRAN_ENV
-+ implicit none
-+ integer, parameter :: j(size(real_kinds)+4)=[REAL_KINDS, [4, 4, 4, 4]]
-+ logical :: l_skip(4) = .false.
-+ integer :: i
-+ integer :: n_tst = 0, n_cnt = 0, n_skip = 0
-+ character(len=20) :: s, s1
-+
-+ open (unit = 10, file = 'fmt_en.res')
-+! Check that the default rounding mode is to nearest and to even on tie.
-+ do i=1,size(real_kinds)
-+ if (i == 1) then
-+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(1)), &
-+ real(9.49999905,kind=j(1)), &
-+ real(9.5,kind=j(1)), real(8.5,kind=j(1))
-+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(1)), &
-+ real(98765.0,kind=j(1))
-+ else if (i == 2) then
-+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(2)), &
-+ real(9.49999905,kind=j(2)), &
-+ real(9.5,kind=j(2)), real(8.5,kind=j(2))
-+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(2)), &
-+ real(98765.0,kind=j(2))
-+ else if (i == 3) then
-+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(3)), &
-+ real(9.49999905,kind=j(3)), &
-+ real(9.5,kind=j(3)), real(8.5,kind=j(3))
-+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(3)), &
-+ real(98765.0,kind=j(3))
-+ else if (i == 4) then
-+ write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(4)), &
-+ real(9.49999905,kind=j(4)), &
-+ real(9.5,kind=j(4)), real(8.5,kind=j(4))
-+ write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(4)), &
-+ real(98765.0,kind=j(4))
-+ end if
-+ if (s /= '-9.5 9.5 10. 8.' .or. s1 /= ' 987.4E+03 98.76E+03') then
-+ l_skip(i) = .true.
-+! print "('Unsupported rounding for real(',i0,')')", j(i)
-+ end if
-+ end do
-+
-+
-+! Original test.
-+ call checkfmt("(en15.2)", -.44444, " -444.44E-03")
-+
-+! Test for the bug in comment 6.
-+ call checkfmt("(en15.0)", 1.0, " 1.E+00")
-+ call checkfmt("(en15.0)", 1.00000012, " 1.E+00")
-+ call checkfmt("(en15.0)", 0.99999994, " 1.E+00")
-+ call checkfmt("(en15.0)", 10.0, " 10.E+00")
-+ call checkfmt("(en15.0)", 10.0000010, " 10.E+00")
-+ call checkfmt("(en15.0)", 9.99999905, " 10.E+00")
-+ call checkfmt("(en15.0)", 100.0, " 100.E+00")
-+ call checkfmt("(en15.0)", 100.000008, " 100.E+00")
-+ call checkfmt("(en15.0)", 99.9999924, " 100.E+00")
-+ call checkfmt("(en15.0)", 1000.0, " 1.E+03")
-+ call checkfmt("(en15.0)", 1000.00006, " 1.E+03")
-+ call checkfmt("(en15.0)", 999.999939, " 1.E+03")
-+ call checkfmt("(en15.0)", 9.5, " 10.E+00")
-+ call checkfmt("(en15.0)", 9.50000095, " 10.E+00")
-+ call checkfmt("(en15.0)", 9.49999905, " 9.E+00")
-+ call checkfmt("(en15.0)", 99.5, " 100.E+00")
-+ call checkfmt("(en15.0)", 99.5000076, " 100.E+00")
-+ call checkfmt("(en15.0)", 99.4999924, " 99.E+00")
-+ call checkfmt("(en15.0)", 999.5, " 1.E+03")
-+ call checkfmt("(en15.0)", 999.500061, " 1.E+03")
-+ call checkfmt("(en15.0)", 999.499939, " 999.E+00")
-+ call checkfmt("(en15.0)", 9500.0, " 10.E+03")
-+ call checkfmt("(en15.0)", 9500.00098, " 10.E+03")
-+ call checkfmt("(en15.0)", 9499.99902, " 9.E+03")
-+ call checkfmt("(en15.1)", 9950.0, " 10.0E+03")
-+ call checkfmt("(en15.2)", 9995.0, " 10.00E+03")
-+ call checkfmt("(en15.3)", 9999.5, " 10.000E+03")
-+ call checkfmt("(en15.1)", 9.5, " 9.5E+00")
-+ call checkfmt("(en15.1)", 9.50000095, " 9.5E+00")
-+ call checkfmt("(en15.1)", 9.49999905, " 9.5E+00")
-+ call checkfmt("(en15.1)", 0.099951, " 100.0E-03")
-+ call checkfmt("(en15.1)", 0.009951, " 10.0E-03")
-+ call checkfmt("(en15.1)", 0.000999951," 1.0E-03")
-+
-+ call checkfmt("(en15.0)", -1.0, " -1.E+00")
-+ call checkfmt("(en15.0)", -1.00000012, " -1.E+00")
-+ call checkfmt("(en15.0)", -0.99999994, " -1.E+00")
-+ call checkfmt("(en15.0)", -10.0, " -10.E+00")
-+ call checkfmt("(en15.0)", -10.0000010, " -10.E+00")
-+ call checkfmt("(en15.0)", -9.99999905, " -10.E+00")
-+ call checkfmt("(en15.0)", -100.0, " -100.E+00")
-+ call checkfmt("(en15.0)", -100.000008, " -100.E+00")
-+ call checkfmt("(en15.0)", -99.9999924, " -100.E+00")
-+ call checkfmt("(en15.0)", -1000.0, " -1.E+03")
-+ call checkfmt("(en15.0)", -1000.00006, " -1.E+03")
-+ call checkfmt("(en15.0)", -999.999939, " -1.E+03")
-+ call checkfmt("(en15.0)", -9.5, " -10.E+00")
-+ call checkfmt("(en15.0)", -9.50000095, " -10.E+00")
-+ call checkfmt("(en15.0)", -9.49999905, " -9.E+00")
-+ call checkfmt("(en15.0)", -99.5, " -100.E+00")
-+ call checkfmt("(en15.0)", -99.5000076, " -100.E+00")
-+ call checkfmt("(en15.0)", -99.4999924, " -99.E+00")
-+ call checkfmt("(en15.0)", -999.5, " -1.E+03")
-+ call checkfmt("(en15.0)", -999.500061, " -1.E+03")
-+ call checkfmt("(en15.0)", -999.499939, " -999.E+00")
-+ call checkfmt("(en15.0)", -9500.0, " -10.E+03")
-+ call checkfmt("(en15.0)", -9500.00098, " -10.E+03")
-+ call checkfmt("(en15.0)", -9499.99902, " -9.E+03")
-+ call checkfmt("(en15.1)", -9950.0, " -10.0E+03")
-+ call checkfmt("(en15.2)", -9995.0, " -10.00E+03")
-+ call checkfmt("(en15.3)", -9999.5, " -10.000E+03")
-+ call checkfmt("(en15.1)", -9.5, " -9.5E+00")
-+ call checkfmt("(en15.1)", -9.50000095, " -9.5E+00")
-+ call checkfmt("(en15.1)", -9.49999905, " -9.5E+00")
-+ call checkfmt("(en15.1)", -0.099951, " -100.0E-03")
-+ call checkfmt("(en15.1)", -0.009951, " -10.0E-03")
-+ call checkfmt("(en15.1)", -0.000999951," -1.0E-03")
-+
-+ call checkfmt("(en15.1)", 987350., " 987.4E+03")
-+ call checkfmt("(en15.2)", 98735., " 98.74E+03")
-+ call checkfmt("(en15.3)", 9873.5, " 9.874E+03")
-+ call checkfmt("(en15.1)", 987650., " 987.6E+03")
-+ call checkfmt("(en15.2)", 98765., " 98.76E+03")
-+ call checkfmt("(en15.3)", 9876.5, " 9.876E+03")
-+ call checkfmt("(en15.1)", 3.125E-02, " 31.2E-03")
-+ call checkfmt("(en15.1)", 9.375E-02, " 93.8E-03")
-+ call checkfmt("(en15.2)", 1.5625E-02, " 15.62E-03")
-+ call checkfmt("(en15.2)", 4.6875E-02, " 46.88E-03")
-+ call checkfmt("(en15.3)", 7.8125E-03, " 7.812E-03")
-+ call checkfmt("(en15.3)", 2.34375E-02, " 23.438E-03")
-+ call checkfmt("(en15.3)", 9.765625E-04," 976.562E-06")
-+ call checkfmt("(en15.6)", 2.9296875E-03," 2.929688E-03")
-+
-+ call checkfmt("(en15.1)", -987350., " -987.4E+03")
-+ call checkfmt("(en15.2)", -98735., " -98.74E+03")
-+ call checkfmt("(en15.3)", -9873.5, " -9.874E+03")
-+ call checkfmt("(en15.1)", -987650., " -987.6E+03")
-+ call checkfmt("(en15.2)", -98765., " -98.76E+03")
-+ call checkfmt("(en15.3)", -9876.5, " -9.876E+03")
-+ call checkfmt("(en15.1)", -3.125E-02, " -31.2E-03")
-+ call checkfmt("(en15.1)", -9.375E-02, " -93.8E-03")
-+ call checkfmt("(en15.2)", -1.5625E-02, " -15.62E-03")
-+ call checkfmt("(en15.2)", -4.6875E-02, " -46.88E-03")
-+ call checkfmt("(en15.3)", -7.8125E-03, " -7.812E-03")
-+ call checkfmt("(en15.3)", -2.34375E-02, " -23.438E-03")
-+ call checkfmt("(en15.3)", -9.765625E-04," -976.562E-06")
-+ call checkfmt("(en15.6)", -2.9296875E-03," -2.929688E-03")
-+
-+ ! print *, n_tst, n_cnt, n_skip
-+ if (n_cnt /= 0) call abort
-+ if (all(.not. l_skip)) write (10, *) "All kinds rounded to nearest"
-+ close (10)
-+
-+contains
-+ subroutine checkfmt(fmt, x, cmp)
-+ implicit none
-+ integer :: i
-+ character(len=*), intent(in) :: fmt
-+ real, intent(in) :: x
-+ character(len=*), intent(in) :: cmp
-+ do i=1,size(real_kinds)
-+ if (i == 1) then
-+ write(s, fmt) real(x,kind=j(1))
-+ else if (i == 2) then
-+ write(s, fmt) real(x,kind=j(2))
-+ else if (i == 3) then
-+ write(s, fmt) real(x,kind=j(3))
-+ else if (i == 4) then
-+ write(s, fmt) real(x,kind=j(4))
-+ end if
-+ n_tst = n_tst + 1
-+ if (s /= cmp) then
-+ if (l_skip(i)) then
-+ n_skip = n_skip + 1
-+ else
-+ print "(a,1x,a,' expected: ',1x,a)", fmt, s, cmp
-+ n_cnt = n_cnt + 1
-+ end if
-+ end if
-+ end do
-+
-+ end subroutine
-+end program
-+! { dg-final { scan-file fmt_en.res "All kinds rounded to nearest" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } } }
-+! { dg-final { cleanup-saved-temps } }
-Index: gcc/testsuite/gfortran.dg/constructor_9.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/constructor_9.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/constructor_9.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+! { dg-do compile }
-+! { dg-options "-Wall" }
-+!
-+! PR 58471: [4.8/4.9 Regression] ICE on invalid with missing type constructor and -Wall
-+!
-+! Contributed by Andrew Benson <abensonca@gmail.com>
-+
-+module cf
-+ implicit none
-+ type :: cfmde
-+ end type
-+ interface cfmde
-+ module procedure mdedc ! { dg-error "is neither function nor subroutine" }
-+ end interface
-+contains
-+ subroutine cfi()
-+ type(cfmde), pointer :: cfd
-+ cfd=cfmde() ! { dg-error "Can't convert" }
-+ end subroutine
-+end module
-+
-+! { dg-final { cleanup-modules "cf" } }
-Index: gcc/testsuite/gfortran.dg/round_3.f08
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/round_3.f08 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/round_3.f08 (.../branches/gcc-4_8-branch)
-@@ -16,19 +16,44 @@
- call checkfmt("(RU,1P,G6.0E2)", 2.0, "2.E+00")
- call checkfmt("(RU,1P,G10.4E2)", 2.3456e5, "2.3456E+05")
-
-- call checkfmt("(RU,F2.0)", 0.09, "1.") ! 0.
-+ call checkfmt("(RC,G10.2)", 99.5, " 0.10E+03") ! pr59774
-+ call checkfmt("(RC,G10.2)", 995., " 0.10E+04") ! pr59774
-+ call checkfmt("(RC,G10.3)", 999.5, " 0.100E+04") ! pr59774
-+ call checkfmt("(RC,G10.3)", 9995., " 0.100E+05") ! pr59774
-+ call checkfmt("(RU,G10.2)", .099, " 0.10 ") ! pr59774
-+ call checkfmt("(RC,G10.1)", .095, " 0.1 ") ! pr59774
-+ call checkfmt("(RU,G10.3)", .0999, " 0.100 ") ! pr59774
-+ call checkfmt("(RC,G10.2)", .0995, " 0.10 ") ! pr59774
-+
-+ call checkfmt("(RU,G9.3)", 891.1, " 892.") ! pr59836
-+ call checkfmt("(RD,G9.3)", -891.1, "-892.") ! pr59836
-+
-+ call checkfmt("(RU,F6.4)", 0.00006, "0.0001")! 0.
-+ call checkfmt("(RU,F5.3)", 0.0007, "0.001") ! 0.
-+ call checkfmt("(RU,F4.2)", 0.008, "0.01") ! 0.
-+ call checkfmt("(RU,F3.1)", 0.09, "0.1") ! 0.
-+
-+ call checkfmt("(RU,F2.0)", 0.09, "1.") ! 0.
- call checkfmt("(RD,F3.0)", -0.09, "-1.") ! -0.
-- call checkfmt("(RU,F2.0)", 2.0, "2.") ! 3.
-- call checkfmt("(RD,F3.0)", -2.0, "-2.") ! -3.
-- call checkfmt("(RU,F6.4)", 2.0, "2.0000") ! 2.0001
-- call checkfmt("(RD,F7.4)", -2.0, "-2.0000") ! -2.0001
-- call checkfmt("(RU,1P,E6.0E2)", 2.0, "2.E+00") ! 3.E+00
-+ call checkfmt("(RU,F2.0)", 0.9, "1.") ! pr59836
-+ call checkfmt("(RC,F2.0)", 0.4, "0.") ! pr59836
-+ call checkfmt("(RC,F2.0)", 0.5, "1.") ! pr59836
-+ call checkfmt("(RC,F2.0)", 0.6, "1.") ! pr59836
-+ call checkfmt("(RD,F3.0)", -0.9, "-1.") ! pr59836
-+ call checkfmt("(RC,F3.0)", -0.4, "-0.") ! pr59836
-+ call checkfmt("(RC,F3.0)", -0.5, "-1.") ! pr59836
-+ call checkfmt("(RC,F3.0)", -0.6, "-1.") ! pr59836
-+ call checkfmt("(RU,F2.0)", 2.0, "2.") ! 3.
-+ call checkfmt("(RD,F3.0)", -2.0, "-2.") ! -3.
-+ call checkfmt("(RU,F6.4)", 2.0, "2.0000") ! 2.0001
-+ call checkfmt("(RD,F7.4)", -2.0, "-2.0000") ! -2.0001
-+ call checkfmt("(RU,1P,E6.0E2)", 2.0, "2.E+00") ! 3.E+00
- call checkfmt("(RD,1P,E7.0E2)", -2.0, "-2.E+00") ! -3.E+00
-- call checkfmt("(RU,1P,E7.1E2)", 2.5, "2.5E+00") ! 2.6E+00
-+ call checkfmt("(RU,1P,E7.1E2)", 2.5, "2.5E+00") ! 2.6E+00
- call checkfmt("(RD,1P,E8.1E2)", -2.5, "-2.5E+00") ! -2.6E+00
- call checkfmt("(RU,1P,E10.4E2)", 2.5, "2.5000E+00") ! 2.5001E+00
- call checkfmt("(RD,1P,E11.4E2)", -2.5, "-2.5000E+00") ! -2.5001E+00
-- call checkfmt("(RU,1P,G6.0E2)", 2.0, "2.E+00") ! 3.E+00
-+ call checkfmt("(RU,1P,G6.0E2)", 2.0, "2.E+00") ! 3.E+00
- call checkfmt("(RD,1P,G7.0E2)", -2.0, "-2.E+00") ! -3.E+00
- call checkfmt("(RU,1P,G10.4E2)", 2.3456e5, "2.3456E+05") ! 2.3457E+05
- call checkfmt("(RD,1P,G11.4E2)", -2.3456e5, "-2.3456E+05") ! -2.3457E+05
-Index: gcc/testsuite/gfortran.dg/default_initialization_7.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/default_initialization_7.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/default_initialization_7.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+! { dg-do compile }
-+!
-+! PR fortran/57033
-+! ICE on a structure constructor of an extended derived type whose parent
-+! type last component has a default initializer
-+!
-+! Contributed by Tilo Schwarz <tilo@tilo-schwarz.de>
-+
-+program ice
-+
-+type m
-+ integer i
-+ logical :: f = .false.
-+end type m
-+
-+type, extends(m) :: me
-+end type me
-+
-+type(me) meo
-+
-+meo = me(1) ! ICE
-+end program ice
-Index: gcc/testsuite/gfortran.dg/proc_ptr_46.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/proc_ptr_46.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_46.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+! { dg-do compile }
-+!
-+! PR fortran/49397
-+!
-+! Invalid per IR F08/0060 and F2008Corr2, C729
-+!
-+
-+! Print *,f() ! << Valid when uncommented
-+Contains
-+ Subroutine s
-+ Procedure(Real),Pointer :: p
-+ p => f ! { dg-error "Procedure pointer target 'f' at .1. must be either an intrinsic, host or use associated, referenced or have the EXTERNAL attribute" }
-+ End Subroutine
-+End
-Index: gcc/testsuite/gfortran.dg/pr52370.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/pr52370.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/pr52370.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+! PR fortran/52370
-+! { dg-do compile }
-+! { dg-options "-O1 -Wall" }
-+
-+module pr52370
-+contains
-+ subroutine foo(a,b)
-+ real, intent(out) :: a
-+ real, dimension(:), optional, intent(out) :: b
-+ a=0.5
-+ if (present(b)) then
-+ b=1.0
-+ end if
-+ end subroutine foo
-+end module pr52370
-+
-+program prg52370
-+ use pr52370
-+ real :: a
-+ call foo(a)
-+end program prg52370
-Index: gcc/testsuite/gfortran.dg/graphite/pr59817.f
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/graphite/pr59817.f (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/graphite/pr59817.f (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+! { dg-do compile }
-+! { dg-options "-O2 -floop-interchange" }
-+ SUBROUTINE PREPD(ICAST,ICAS,ICASX,ICAS1,ICAS2,NDET,NM,III,IMP,
-+ * CASMIN)
-+ LOGICAL CASMIN
-+ DIMENSION ICAST(NDET,NM),IMP(NM)
-+ IF(CASMIN) THEN
-+ DO K=1,NDET
-+ DO L=1,NM
-+ IF(L.EQ.K-1) ICAST(K,L) = 1
-+ END DO
-+ END DO
-+ END IF
-+ END SUBROUTINE
-Index: gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+! { dg-do compile }
-+! { dg-options "-ffrontend-optimize" }
-+!
-+! PR fortran/60341
-+! An unguarded union access was wrongly enabling a frontend optimization on a
-+! string comparison, leading to an ICE.
-+!
-+! Original testcase from Steve Chapel <steve.chapel@a2pg.com>.
-+! Reduced by Steven G. Kargl <kargl@gcc.gnu.org>.
-+!
-+
-+ subroutine modelg(ncm)
-+ implicit none
-+ integer, parameter :: pc = 30, pm = pc - 1
-+ integer i
-+ character*4 catt(pm,2)
-+ integer ncm,iatt(pm,pc)
-+ do i=1,ncm
-+ if (catt(i,1)//catt(i,2).eq.'central') exit
-+ end do
-+ iatt(i,4)=1
-+ end
-Index: gcc/testsuite/gfortran.dg/list_read_12.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/list_read_12.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/list_read_12.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+! { dg-do run }
-+! PR58324 Bogus end of file condition
-+integer :: i, ios
-+open(99, access='stream', form='unformatted')
-+write(99) "5 a"
-+close(99)
-+
-+open(99, access='sequential', form='formatted')
-+read(99, *, iostat=ios) i
-+if (ios /= 0) call abort
-+end
-Index: gcc/testsuite/gfortran.dg/generic_28.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/generic_28.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/generic_28.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,18 @@
-+! { dg-do compile }
-+!
-+! PR 58998: [4.8/4.9 Regression] Generic interface problem with gfortran
-+!
-+! Contributed by Paul van Delst
-+
-+ interface iargc
-+ procedure iargc_8
-+ end interface
-+
-+contains
-+
-+ integer(8) function iargc_8()
-+ integer(4) iargc
-+ iargc_8 = iargc()
-+ end function
-+
-+end
-Index: gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,44 @@
-+! { dg-do compile }
-+!
-+! PR fortran/58007
-+! Unresolved fixup while loading a module.
-+!
-+! This tests that the specification expression A%MAX_DEGREE in module BSR is
-+! correctly loaded and resolved in program MAIN.
-+!
-+! Original testcase from Daniel Shapiro <shapero@uw.edu>
-+! Reduced by Tobias Burnus <burnus@net-b.de> and Janus Weil <janus@gcc.gnu.org>
-+
-+module matrix
-+ type :: sparse_matrix
-+ integer :: max_degree
-+ end type
-+contains
-+ subroutine init_interface (A)
-+ class(sparse_matrix), intent(in) :: A
-+ end subroutine
-+ real function get_value_interface()
-+ end function
-+end module
-+
-+module ellpack
-+ use matrix
-+end module
-+
-+module bsr
-+ use matrix
-+ type, extends(sparse_matrix) :: bsr_matrix
-+ contains
-+ procedure :: get_neighbors
-+ end type
-+contains
-+ function get_neighbors (A)
-+ class(bsr_matrix), intent(in) :: A
-+ integer :: get_neighbors(A%max_degree)
-+ end function
-+end module
-+
-+program main
-+ use ellpack
-+ use bsr
-+end
-Index: gcc/testsuite/gfortran.dg/lto/pr60635_1.c
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/lto/pr60635_1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/lto/pr60635_1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+#include <stdint.h>
-+#include <stdbool.h>
-+
-+static bool littleendian=true;
-+
-+uint16_t bigendc16(union{uint16_t * n;uint8_t* b;}x){
-+
-+ if (!littleendian) return *x.n;
-+
-+ uint16_t res = ((uint16_t)(x.b[1])<<0) |
-+ ((uint16_t)(x.b[0])<<8);
-+ return res;
-+}
-+
-Index: gcc/testsuite/gfortran.dg/lto/pr60635_0.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/lto/pr60635_0.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/lto/pr60635_0.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+! { dg-lto-do link }
-+program test
-+ use iso_fortran_env
-+
-+ interface
-+ integer(int16) function bigendc16(x) bind(C)
-+ import
-+ integer(int16), intent(in) :: x
-+ end function
-+ end interface
-+
-+ integer(int16) :: x16 = 12345
-+ x16 = bigendc16(x16)
-+ print *,x16
-+end program
-+
-Index: gcc/testsuite/gfortran.dg/arrayio_13.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/arrayio_13.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/arrayio_13.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+! { dg-do run }
-+! PR60810 Bogus end-of-file
-+program readstrlist
-+ character(len=80), dimension(2) :: ver
-+ integer :: a, b, c
-+ a = 1
-+ b = 2
-+ c = 3
-+ ver(1) = '285 383'
-+ ver(2) = '985'
-+ read( ver, *) a, b, c
-+ if (a /= 285 .or. b /= 383 .or. c /= 985) call abort
-+ !write ( *, *) a, b, c
-+end
-Index: gcc/testsuite/gfortran.dg/null_5.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/null_5.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/null_5.f90 (.../branches/gcc-4_8-branch)
-@@ -34,7 +34,7 @@
- end subroutine test_PR34547_1
-
- subroutine test_PR34547_2 ()
-- print *, null () ! { dg-error "in data transfer statement requires MOLD" }
-+ print *, null () ! { dg-error "Invalid context" }
- end subroutine test_PR34547_2
-
- subroutine test_PR34547_3 ()
-Index: gcc/testsuite/gfortran.dg/proc_ptr_43.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/proc_ptr_43.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_43.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,19 @@
-+! { dg-do compile }
-+!
-+! PR 58099: [4.8/4.9 Regression] [F03] over-zealous procedure-pointer error checking
-+!
-+! Contributed by Daniel Price <daniel.price@monash.edu>
-+
-+ implicit none
-+ procedure(real), pointer :: wfunc
-+
-+ wfunc => w_cubic
-+
-+contains
-+
-+ pure real function w_cubic(q2)
-+ real, intent(in) :: q2
-+ w_cubic = 0.
-+ end function
-+
-+end
-Index: gcc/testsuite/gfortran.dg/nan_7.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/nan_7.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/nan_7.f90 (.../branches/gcc-4_8-branch)
-@@ -2,6 +2,7 @@
- ! { dg-options "-fno-range-check" }
- ! { dg-require-effective-target fortran_real_16 }
- ! { dg-require-effective-target fortran_integer_16 }
-+! { dg-skip-if "" { "powerpc*le-*-*" } { "*" } { "" } }
- ! PR47293 NAN not correctly read
- character(len=200) :: str
- real(16) :: r
-Index: gcc/testsuite/gfortran.dg/typebound_generic_15.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/typebound_generic_15.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/typebound_generic_15.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,18 @@
-+! { dg-do compile }
-+!
-+! PR 60231: [4.8/4.9 Regression] ICE on undefined generic
-+!
-+! Contributed by Antony Lewis <antony@cosmologist.info>
-+
-+module Objects
-+
-+ Type TObjectList
-+ contains
-+ procedure :: Add1 ! { dg-error "must be a module procedure" }
-+ procedure :: Add2 ! { dg-error "must be a module procedure" }
-+ generic :: Add => Add1, Add2 ! { dg-error "are ambiguous" }
-+ end Type
-+
-+end module
-+
-+! { dg-final { cleanup-modules "Objects" } }
-Index: gcc/testsuite/gfortran.dg/extends_15.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/extends_15.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/extends_15.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+! { dg-do compile }
-+!
-+! PR 58355: [4.7/4.8/4.9 Regression] [F03] ICE with TYPE, EXTENDS before parent TYPE defined
-+!
-+! Contributed by Andrew Benson <abensonca@gmail.com>
-+
-+module ct
-+ public :: t1
-+
-+ type, extends(t1) :: t2 ! { dg-error "has not been previously defined" }
-+
-+ type :: t1
-+ end type
-+end
-+
-+! { dg-final { cleanup-modules "ct" } }
-Index: gcc/testsuite/gfortran.dg/optional_class_1.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/optional_class_1.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/optional_class_1.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,45 @@
-+! { dg-do run }
-+!
-+! PR fortran/57445
-+!
-+! Contributed by Tobias Burnus <burnus@gcc.gnu.org>
-+!
-+! Spurious assert was added at revision 192495
-+!
-+module m
-+ implicit none
-+ type t
-+ integer :: i
-+ end type t
-+contains
-+ subroutine opt(xa, xc, xaa, xca)
-+ type(t), allocatable, intent(out), optional :: xa
-+ class(t), allocatable, intent(out), optional :: xc
-+ type(t), allocatable, intent(out), optional :: xaa(:)
-+ class(t), allocatable, intent(out), optional :: xca(:)
-+ if (present (xca)) call foo_opt(xca=xca)
-+ end subroutine opt
-+ subroutine foo_opt(xa, xc, xaa, xca)
-+ type(t), allocatable, intent(out), optional :: xa
-+ class(t), allocatable, intent(out), optional :: xc
-+ type(t), allocatable, intent(out), optional :: xaa(:)
-+ class(t), allocatable, intent(out), optional :: xca(:)
-+ if (present (xca)) then
-+ if (allocated (xca)) deallocate (xca)
-+ allocate (xca(3), source = [t(9),t(99),t(999)])
-+ end if
-+ end subroutine foo_opt
-+end module m
-+ use m
-+ class(t), allocatable :: xca(:)
-+ allocate (xca(1), source = t(42))
-+ select type (xca)
-+ type is (t)
-+ if (any (xca%i .ne. [42])) call abort
-+ end select
-+ call opt (xca = xca)
-+ select type (xca)
-+ type is (t)
-+ if (any (xca%i .ne. [9,99,999])) call abort
-+ end select
-+end
-Index: gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,74 @@
-+! { dg-do run }
-+!
-+! PR 59654: [4.8/4.9 Regression] [OOP] Broken function table with complex OO use case
-+!
-+! Contributed by Thomas Clune <Thomas.L.Clune@nasa.gov>
-+
-+module TestResult_mod
-+ implicit none
-+
-+ type TestResult
-+ integer :: numRun = 0
-+ contains
-+ procedure :: run
-+ procedure, nopass :: getNumRun
-+ end type
-+
-+contains
-+
-+ subroutine run (this)
-+ class (TestResult) :: this
-+ this%numRun = this%numRun + 1
-+ end subroutine
-+
-+ subroutine getNumRun()
-+ end subroutine
-+
-+end module
-+
-+
-+module BaseTestRunner_mod
-+ implicit none
-+
-+ type :: BaseTestRunner
-+ contains
-+ procedure, nopass :: norun
-+ end type
-+
-+contains
-+
-+ function norun () result(result)
-+ use TestResult_mod, only: TestResult
-+ type (TestResult) :: result
-+ end function
-+
-+end module
-+
-+
-+module TestRunner_mod
-+ use BaseTestRunner_mod, only: BaseTestRunner
-+ implicit none
-+end module
-+
-+
-+program main
-+ use TestRunner_mod, only: BaseTestRunner
-+ use TestResult_mod, only: TestResult
-+ implicit none
-+
-+ type (TestResult) :: result
-+
-+ call runtest (result)
-+
-+contains
-+
-+ subroutine runtest (result)
-+ use TestResult_mod, only: TestResult
-+ class (TestResult) :: result
-+ call result%run()
-+ if (result%numRun /= 1) call abort()
-+ end subroutine
-+
-+end
-+
-+! { dg-final { cleanup-modules "TestResult_mod BaseTestRunner_mod TestRunner_mod" } }
-Index: gcc/testsuite/gfortran.dg/proc_ptr_45.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/proc_ptr_45.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/proc_ptr_45.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,24 @@
-+! { dg-do compile }
-+!
-+! PR fortran/49397
-+!
-+! Valid per IR F08/0060 and F2008Corr2, C729
-+!
-+Program m5
-+ Print *,f()
-+Contains
-+ Subroutine s
-+ Procedure(Real),Pointer :: p
-+ Print *,g()
-+ p => f ! (1)
-+ Print *,p()
-+ p => g ! (2)
-+ Print *,p()
-+ End Subroutine
-+End Program
-+Function f()
-+ f = 1
-+End Function
-+Function g()
-+ g = 2
-+End Function
-Index: gcc/testsuite/gfortran.dg/pr59700.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/pr59700.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/pr59700.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,40 @@
-+! { dg-do run }
-+! PR59700 Test case by Steve Kargl
-+program foo
-+
-+ implicit none
-+
-+ character(len=80) msg
-+ integer, parameter :: fd = 10
-+ integer i1, i2, i3, i4
-+ real x1, x2, x3, x4
-+ complex c1, c2
-+ logical a
-+
-+ open(unit=fd, status='scratch')
-+ write(fd, '(A)') '1 2 3.4 q'
-+
-+ rewind(fd)
-+ msg = 'ok'
-+ read(fd, *, err=10, iomsg=msg) i1, i2, i3, i4
-+10 if (msg /= 'Bad integer for item 3 in list input') call abort
-+ rewind(fd)
-+ msg = 'ok'
-+ read(fd, *, err=20, iomsg=msg) x1, x2, x3, x4
-+20 if (msg /= 'Bad real number in item 4 of list input') call abort
-+ rewind(fd)
-+ msg = 'ok'
-+ read(fd, *, err=30, iomsg=msg) i1, x2, x1, a
-+30 if (msg /= 'Bad logical value while reading item 4') call abort
-+ rewind(fd)
-+ read(fd, *, err=31, iomsg=msg) i1, x2, a, x1
-+31 if (msg /= 'Bad repeat count in item 3 of list input') call abort
-+ close(fd)
-+ open(unit=fd, status='scratch')
-+ write(fd, '(A)') '(1, 2) (3.4, q)'
-+ rewind(fd)
-+ msg = 'ok'
-+ read(fd, *, err=40, iomsg=msg) c1, c2
-+40 if (msg /= 'Bad floating point number for item 2') call abort
-+ close(fd)
-+end program foo
-Index: gcc/testsuite/gfortran.dg/ichar_3.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/ichar_3.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/ichar_3.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+! { dg-do compile }
-+!
-+! PR fortran/59599
-+! The call to ichar was triggering an ICE.
-+!
-+! Original testcase from Fran Martinez Fadrique <fmartinez@gmv.com>
-+
-+character(1) cpk(2)
-+integer res(2)
-+cpk = 'a'
-+res = ichar( cpk, kind=1 )
-+print *, ichar( cpk, kind=1 )
-+end
-Index: gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,17 @@
-+! { dg-do compile }
-+!
-+! PR 59493: [OOP] ICE: Segfault on Class(*) pointer association
-+!
-+! Contributed by Hossein Talebi <talebi.hossein@gmail.com>
-+
-+ implicit none
-+
-+ type ty_mytype1
-+ end type
-+
-+ class(ty_mytype1), allocatable, target:: cla1
-+ class(*), pointer :: ptr
-+
-+ ptr => cla1
-+
-+end
-Index: gcc/testsuite/gfortran.dg/fmt_g_1.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/fmt_g_1.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/fmt_g_1.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+! { dg-do run }
-+! PR59771 Cleanup handling of Gw.0 and Gw.0Ee format
-+! Test case prepared by Dominique d'Humieres <dominiq@lps.ens.fr>
-+ PROGRAM FOO
-+ character(len=60) :: buffer, buffer1
-+
-+ write (buffer ,'(6(1X,1PG9.0e2))') 0.0, 0.04, 0.06, 0.4, 0.6, 243.0
-+ write (buffer1,'(6(1X,1PE9.0e2))') 0.0, 0.04, 0.06, 0.4, 0.6, 243.0
-+
-+ if (buffer /= buffer1) call abort
-+ end
-Index: gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,39 @@
-+! { dg-do run }
-+!
-+! PR fortran/59906
-+!
-+! Contributed by H Anlauf <anlauf@gmx.de>
-+!
-+! Failed generate character scalar for scalarized loop for elemantal call.
-+!
-+program x
-+ implicit none
-+ call y('bbb')
-+contains
-+
-+ subroutine y(str)
-+ character(len=*), intent(in) :: str
-+ character(len=len_trim(str)) :: str_aux
-+ character(len=3) :: str3 = 'abc'
-+
-+ str_aux = str
-+
-+ ! Compiled but did not give correct result
-+ if (any (str_cmp((/'aaa','bbb'/), str) .neqv. [.FALSE.,.TRUE.])) call abort
-+
-+ ! Did not compile
-+ if (any (str_cmp((/'bbb', 'aaa'/), str_aux) .neqv. [.TRUE.,.FALSE.])) call abort
-+
-+ ! Verify patch
-+ if (any (str_cmp((/'bbb', 'aaa'/), str3) .neqv. [.FALSE.,.FALSE.])) call abort
-+ if (any (str_cmp((/'bbb', 'aaa'/), 'aaa') .neqv. [.FALSE.,.TRUE.])) call abort
-+
-+ end subroutine y
-+
-+ elemental logical function str_cmp(str1, str2)
-+ character(len=*), intent(in) :: str1
-+ character(len=*), intent(in) :: str2
-+ str_cmp = (str1 == str2)
-+ end function str_cmp
-+
-+end program x
-Index: gcc/testsuite/gcc.c-torture/execute/20140212-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/20140212-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/20140212-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+/* PR rtl-optimization/60116 */
-+/* Reported by Zhendong Su <su@cs.ucdavis.edu> */
-+
-+extern void abort (void);
-+
-+int a, b, c, d = 1, e, f = 1, h, i, k;
-+char g, j;
-+
-+void
-+fn1 (void)
-+{
-+ int l;
-+ e = 0;
-+ c = 0;
-+ for (;;)
-+ {
-+ k = a && b;
-+ j = k * 54;
-+ g = j * 147;
-+ l = ~g + (long long) e && 1;
-+ if (d)
-+ c = l;
-+ else
-+ h = i = l * 9UL;
-+ if (f)
-+ return;
-+ }
-+}
-+
-+int
-+main (void)
-+{
-+ fn1 ();
-+ if (c != 1)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr58984.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr58984.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr58984.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,57 @@
-+/* PR tree-optimization/58984 */
-+
-+struct S { int f0 : 8; int : 6; int f1 : 5; };
-+struct T { char f0; int : 6; int f1 : 5; };
-+
-+int a, *c = &a, e, n, b, m;
-+
-+static int
-+foo (struct S p)
-+{
-+ const unsigned short *f[36];
-+ for (; e < 2; e++)
-+ {
-+ const unsigned short **i = &f[0];
-+ *c ^= 1;
-+ if (p.f1)
-+ {
-+ *i = 0;
-+ return b;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static int
-+bar (struct T p)
-+{
-+ const unsigned short *f[36];
-+ for (; e < 2; e++)
-+ {
-+ const unsigned short **i = &f[0];
-+ *c ^= 1;
-+ if (p.f1)
-+ {
-+ *i = 0;
-+ return b;
-+ }
-+ }
-+ return 0;
-+}
-+
-+int
-+main ()
-+{
-+ struct S o = { 1, 1 };
-+ foo (o);
-+ m = n || o.f0;
-+ if (a != 1)
-+ __builtin_abort ();
-+ e = 0;
-+ struct T p = { 1, 1 };
-+ bar (p);
-+ m |= n || p.f0;
-+ if (a != 0)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr60454.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr60454.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60454.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,31 @@
-+#ifdef __UINT32_TYPE__
-+typedef __UINT32_TYPE__ uint32_t;
-+#else
-+typedef unsigned uint32_t;
-+#endif
-+
-+#define __fake_const_swab32(x) ((uint32_t)( \
-+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
-+ (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \
-+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 8) | \
-+ (((uint32_t)(x) & (uint32_t)0x0000ff00UL) ) | \
-+ (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
-+
-+/* Previous version of bswap optimization would detect byte swap when none
-+ happen. This test aims at catching such wrong detection to avoid
-+ regressions. */
-+
-+__attribute__ ((noinline, noclone)) uint32_t
-+fake_swap32 (uint32_t in)
-+{
-+ return __fake_const_swab32 (in);
-+}
-+
-+int main(void)
-+{
-+ if (sizeof (uint32_t) * __CHAR_BIT__ != 32)
-+ return 0;
-+ if (fake_swap32 (0x12345678UL) != 0x78567E12UL)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr60017.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr60017.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60017.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,33 @@
-+/* PR target/60017 */
-+
-+extern void abort (void);
-+
-+struct S0
-+{
-+ short m0;
-+ short m1;
-+};
-+
-+struct S1
-+{
-+ unsigned m0:1;
-+ char m1[2][2];
-+ struct S0 m2[2];
-+};
-+
-+struct S1 x = { 1, {{2, 3}, {4, 5}}, {{6, 7}, {8, 9}} };
-+
-+struct S1 func (void)
-+{
-+ return x;
-+}
-+
-+int main (void)
-+{
-+ struct S1 ret = func ();
-+
-+ if (ret.m2[1].m1 != 9)
-+ abort ();
-+
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/20131127-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/20131127-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/20131127-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,34 @@
-+/* PR middle-end/59138 */
-+/* Testcase by John Regehr <regehr@cs.utah.edu> */
-+
-+extern void abort (void);
-+
-+#pragma pack(1)
-+
-+struct S0 {
-+ int f0;
-+ int f1;
-+ int f2;
-+ short f3;
-+};
-+
-+short a = 1;
-+
-+struct S0 b = { 1 }, c, d, e;
-+
-+struct S0 fn1() { return c; }
-+
-+void fn2 (void)
-+{
-+ b = fn1 ();
-+ a = 0;
-+ d = e;
-+}
-+
-+int main (void)
-+{
-+ fn2 ();
-+ if (a != 0)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr59358.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr59358.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59358.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,44 @@
-+/* PR tree-optimization/59358 */
-+
-+__attribute__((noinline, noclone)) int
-+foo (int *x, int y)
-+{
-+ int z = *x;
-+ if (y > z && y <= 16)
-+ while (y > z)
-+ z *= 2;
-+ return z;
-+}
-+
-+int
-+main ()
-+{
-+ int i;
-+ for (i = 1; i < 17; i++)
-+ {
-+ int j = foo (&i, 16);
-+ int k;
-+ if (i >= 8 && i <= 15)
-+ k = 16 + (i - 8) * 2;
-+ else if (i >= 4 && i <= 7)
-+ k = 16 + (i - 4) * 4;
-+ else if (i == 3)
-+ k = 24;
-+ else
-+ k = 16;
-+ if (j != k)
-+ __builtin_abort ();
-+ j = foo (&i, 7);
-+ if (i >= 7)
-+ k = i;
-+ else if (i >= 4)
-+ k = 8 + (i - 4) * 2;
-+ else if (i == 3)
-+ k = 12;
-+ else
-+ k = 8;
-+ if (j != k)
-+ __builtin_abort ();
-+ }
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr60062.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr60062.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60062.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,25 @@
-+/* PR target/60062 */
-+
-+int a;
-+
-+static void
-+foo (const char *p1, int p2)
-+{
-+ if (__builtin_strcmp (p1, "hello") != 0)
-+ __builtin_abort ();
-+}
-+
-+static void
-+bar (const char *p1)
-+{
-+ if (__builtin_strcmp (p1, "hello") != 0)
-+ __builtin_abort ();
-+}
-+
-+__attribute__((optimize (0))) int
-+main ()
-+{
-+ foo ("hello", a);
-+ bar ("hello");
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/20140425-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,23 @@
-+/* PR target/60941 */
-+/* Reported by Martin Husemann <martin@netbsd.org> */
-+
-+extern void abort (void);
-+
-+static void __attribute__((noinline))
-+set (unsigned long *l)
-+{
-+ *l = 31;
-+}
-+
-+int main (void)
-+{
-+ unsigned long l;
-+ int i;
-+
-+ set (&l);
-+ i = (int) l;
-+ l = (unsigned long)(2U << i);
-+ if (l != 0)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr59014-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr59014-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59014-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,23 @@
-+/* PR tree-optimization/59014 */
-+
-+__attribute__((noinline, noclone)) long long int
-+foo (long long int x, long long int y)
-+{
-+ if (((int) x | (int) y) != 0)
-+ return 6;
-+ return x + y;
-+}
-+
-+int
-+main ()
-+{
-+ if (sizeof (long long) == sizeof (int))
-+ return 0;
-+ int shift_half = sizeof (int) * __CHAR_BIT__ / 2;
-+ long long int x = (3LL << shift_half) << shift_half;
-+ long long int y = (5LL << shift_half) << shift_half;
-+ long long int z = foo (x, y);
-+ if (z != ((8LL << shift_half) << shift_half))
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr59101.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr59101.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59101.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* PR target/59101 */
-+
-+__attribute__((noinline, noclone)) int
-+foo (int a)
-+{
-+ return (~a & 4102790424LL) > 0 | 6;
-+}
-+
-+int
-+main ()
-+{
-+ if (foo (0) != 7)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr58831.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr58831.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr58831.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,40 @@
-+#include <assert.h>
-+
-+int a, *b, c, d, f, **i, p, q, *r;
-+short o, j;
-+
-+static int __attribute__((noinline, noclone))
-+fn1 (int *p1, int **p2)
-+{
-+ int **e = &b;
-+ for (; p; p++)
-+ *p1 = 1;
-+ *e = *p2 = &d;
-+
-+ assert (r);
-+
-+ return c;
-+}
-+
-+static int ** __attribute__((noinline, noclone))
-+fn2 (void)
-+{
-+ for (f = 0; f != 42; f++)
-+ {
-+ int *g[3] = {0, 0, 0};
-+ for (o = 0; o; o--)
-+ for (; a > 1;)
-+ {
-+ int **h[1] = { &g[2] };
-+ }
-+ }
-+ return &r;
-+}
-+
-+int
-+main (void)
-+{
-+ i = fn2 ();
-+ fn1 (b, i);
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr58726.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr58726.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr58726.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,26 @@
-+/* PR rtl-optimization/58726 */
-+
-+int a, c;
-+union { int f1; int f2 : 1; } b;
-+
-+short
-+foo (short p)
-+{
-+ return p < 0 ? p : a;
-+}
-+
-+int
-+main ()
-+{
-+ if (sizeof (short) * __CHAR_BIT__ != 16
-+ || sizeof (int) * __CHAR_BIT__ != 32)
-+ return 0;
-+ b.f1 = 56374;
-+ unsigned short d;
-+ int e = b.f2;
-+ d = e == 0 ? b.f1 : 0;
-+ c = foo (d);
-+ if (c != (short) 56374)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr59014.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr59014.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59014.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,25 @@
-+/* PR tree-optimization/59014 */
-+
-+int a = 2, b, c, d;
-+
-+int
-+foo ()
-+{
-+ for (;; c++)
-+ if ((b > 0) | (a & 1))
-+ ;
-+ else
-+ {
-+ d = a;
-+ return 0;
-+ }
-+}
-+
-+int
-+main ()
-+{
-+ foo ();
-+ if (d != 2)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr60960.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,38 @@
-+/* PR tree-optimization/60960 */
-+
-+typedef unsigned char v4qi __attribute__ ((vector_size (4)));
-+
-+__attribute__((noinline, noclone)) v4qi
-+f1 (v4qi v)
-+{
-+ return v / 2;
-+}
-+
-+__attribute__((noinline, noclone)) v4qi
-+f2 (v4qi v)
-+{
-+ return v / (v4qi) { 2, 2, 2, 2 };
-+}
-+
-+__attribute__((noinline, noclone)) v4qi
-+f3 (v4qi x, v4qi y)
-+{
-+ return x / y;
-+}
-+
-+int
-+main ()
-+{
-+ v4qi x = { 5, 5, 5, 5 };
-+ v4qi y = { 2, 2, 2, 2 };
-+ v4qi z = f1 (x);
-+ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)
-+ __builtin_abort ();
-+ z = f2 (x);
-+ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)
-+ __builtin_abort ();
-+ z = f3 (x, y);
-+ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr60072.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr60072.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60072.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+/* PR target/60072 */
-+
-+int c = 1;
-+
-+__attribute__ ((optimize (1)))
-+static int *foo (int *p)
-+{
-+ return p;
-+}
-+
-+int
-+main ()
-+{
-+ *foo (&c) = 2;
-+ return c - 2;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/20140326-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/20140326-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/20140326-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+int a;
-+
-+int
-+main (void)
-+{
-+ char e[2] = { 0, 0 }, f = 0;
-+ if (a == 131072)
-+ f = e[a];
-+ return f;
-+}
-Index: gcc/testsuite/gcc.c-torture/execute/pr59388.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr59388.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr59388.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* PR tree-optimization/59388 */
-+
-+int a;
-+struct S { unsigned int f:1; } b;
-+
-+int
-+main ()
-+{
-+ a = (0 < b.f) | b.f;
-+ return a;
-+}
-Index: gcc/testsuite/gcc.c-torture/compile/pr58970-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/compile/pr58970-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr58970-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* PR middle-end/58970 */
-+
-+struct T { int b : 1; };
-+struct S { struct T t[1]; };
-+
-+void
-+foo (int x, struct S *s)
-+{
-+ if (x == -1)
-+ s->t[x].b = 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/compile/pr59803.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/compile/pr59803.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr59803.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,27 @@
-+/* PR target/59803 */
-+
-+extern void baz (void) __attribute__ ((__noreturn__));
-+struct A { int g, h; };
-+extern struct A a;
-+struct B { unsigned char i, j, k, l, m; };
-+int c, d, e;
-+static int f;
-+
-+void
-+foo (void)
-+{
-+ f = 1;
-+}
-+
-+void
-+bar (struct B *x)
-+{
-+ x->i = e;
-+ x->k = c;
-+ x->l = d;
-+ x->j = a.h;
-+ x->m = f;
-+ if (x->i != e) baz ();
-+ if (x->k != c) baz ();
-+ if (x->j != a.h) baz ();
-+}
-Index: gcc/testsuite/gcc.c-torture/compile/pr58997.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/compile/pr58997.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr58997.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,19 @@
-+/* PR rtl-optimization/58997 */
-+
-+int a, b, c, e;
-+short d;
-+char h;
-+
-+void
-+foo ()
-+{
-+ while (b)
-+ {
-+ d = a ? c : 1 % a;
-+ c = d;
-+ h = d;
-+ if (!h)
-+ while (e)
-+ ;
-+ }
-+}
-Index: gcc/testsuite/gcc.c-torture/compile/pr60502.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/compile/pr60502.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr60502.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,18 @@
-+/* PR tree-optimization/60502 */
-+
-+typedef signed char v16i8 __attribute__ ((vector_size (16)));
-+typedef unsigned char v16u8 __attribute__ ((vector_size (16)));
-+
-+void
-+foo (v16i8 *x)
-+{
-+ v16i8 m1 = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 };
-+ *x |= *x ^ m1;
-+}
-+
-+void
-+bar (v16u8 *x)
-+{
-+ v16u8 m1 = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 };
-+ *x |= *x ^ m1;
-+}
-Index: gcc/testsuite/gcc.c-torture/compile/pr58970-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/compile/pr58970-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr58970-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* PR middle-end/58970 */
-+
-+struct T { char a : 8; char b : 1; };
-+struct S { char x; struct T t[1]; };
-+
-+void
-+foo (int x, struct S *s)
-+{
-+ if (x == -1)
-+ s->t[x].b = 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/compile/pr59362.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/compile/pr59362.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr59362.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* PR tree-optimization/59362 */
-+
-+char *
-+foo (char *r, int s)
-+{
-+ r = __builtin___stpcpy_chk (r, "abc", __builtin_object_size (r, 1));
-+ if (s)
-+ r = __builtin___stpcpy_chk (r, "d", __builtin_object_size (r, 1));
-+ return r;
-+}
-+
-+char *a;
-+long int b;
-+
-+void
-+bar (void)
-+{
-+ b = __builtin_object_size (0, 0);
-+ a = __builtin___stpcpy_chk (0, "", b);
-+ b = __builtin_object_size (a, 0);
-+}
-Index: gcc/testsuite/gnat.dg/opt32.adb
-===================================================================
---- a/src/gcc/testsuite/gnat.dg/opt32.adb (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gnat.dg/opt32.adb (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+-- { dg-do compile }
-+-- { dg-options "-O2" }
-+
-+with Ada.Containers; use Ada.Containers;
-+with Ada.Containers.Vectors;
-+
-+function Opt32 return Natural is
-+
-+ package My_Vectors
-+ is new Vectors (Index_Type => Natural, Element_Type => Integer);
-+ use My_Vectors;
-+
-+ V : Vector;
-+
-+ function Sign_Changes return Natural is
-+ Cur : Cursor := To_Cursor (V, 0);
-+ R : Natural := 0;
-+ Negative : Boolean;
-+ begin
-+ Negative := Element (Cur) < 0;
-+
-+ loop
-+ Cur := Next (Cur);
-+ exit when R > 100;
-+
-+ if (Element (Cur) < 0) /= Negative then
-+ Negative := not Negative;
-+ R := R + 1;
-+ end if;
-+ end loop;
-+
-+ return R;
-+ end;
-+
-+begin
-+ return Sign_Changes;
-+end;
-Index: gcc/testsuite/gcc.dg/pr58668.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr58668.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr58668.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,25 @@
-+/* PR rtl-optimization/58668 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2" } */
-+/* { dg-additional-options "-mthumb" { target { { arm*-*-* } && arm_thumb2_ok } } } */
-+
-+void *fn1 (void *);
-+void *fn2 (void *, const char *);
-+void fn3 (void *);
-+void fn4 (void *, int);
-+
-+void *
-+test (void *x)
-+{
-+ void *a, *b;
-+ if (!(a = fn1 (x)))
-+ return (void *) 0;
-+ if (!(b = fn2 (a, "w")))
-+ {
-+ fn3 (a);
-+ return (void *) 0;
-+ }
-+ fn3 (a);
-+ fn4 (b, 1);
-+ return b;
-+}
-Index: gcc/testsuite/gcc.dg/pr57518.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr57518.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr57518.c (.../branches/gcc-4_8-branch)
-@@ -1,8 +1,8 @@
--/* PR rtl-optimization/57130 */
-+/* PR rtl-optimization/57518 */
-
- /* { dg-do compile } */
- /* { dg-options "-O2 -fdump-rtl-ira" } */
--/* { dg-final { scan-rtl-dump-not "REG_EQUIV.*mem.*\"ip\"" "ira" } } */
-+/* { dg-final { scan-rtl-dump-not "REG_EQUIV\[^\n\]*mem\[^\n\]*\"ip\".*subreg" "ira" } } */
-
- char ip[10];
- int total;
-Index: gcc/testsuite/gcc.dg/builtin-object-size-14.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/builtin-object-size-14.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/builtin-object-size-14.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,28 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2" } */
-+
-+extern void abort (void);
-+extern char *strncpy(char *, const char *, __SIZE_TYPE__);
-+
-+union u {
-+ struct {
-+ char vi[8];
-+ char pi[16];
-+ };
-+ char all[8+16+4];
-+};
-+
-+void __attribute__((noinline,noclone))
-+f(union u *u)
-+{
-+ char vi[8+1];
-+ __builtin_strncpy(vi, u->vi, sizeof(u->vi));
-+ if (__builtin_object_size (u->all, 1) != -1)
-+ abort ();
-+}
-+int main()
-+{
-+ union u u;
-+ f (&u);
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/gomp/pr58809.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/gomp/pr58809.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/gomp/pr58809.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+/* PR middle-end/58809 */
-+/* { dg-do compile } */
-+/* { dg-options "-fopenmp -O" } */
-+
-+int i;
-+#pragma omp threadprivate (i)
-+
-+void foo()
-+{
-+ _Complex int j;
-+#pragma omp parallel copyin (i) reduction (&&:j)
-+ ;
-+}
-Index: gcc/testsuite/gcc.dg/20050922-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/20050922-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/20050922-1.c (.../branches/gcc-4_8-branch)
-@@ -4,7 +4,7 @@
- /* { dg-do run } */
- /* { dg-options "-O1 -std=c99" } */
-
--#include <stdlib.h>
-+extern void abort (void);
-
- #if __INT_MAX__ == 2147483647
- typedef unsigned int uint32_t;
-Index: gcc/testsuite/gcc.dg/pr46309.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr46309.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr46309.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* PR tree-optimization/46309 */
--/* { dg-do compile } */
-+/* { dg-do compile { target { ! { cris*-*-* } } } } */
- /* { dg-options "-O2 -fdump-tree-reassoc-details" } */
- /* The transformation depends on BRANCH_COST being greater than 1
- (see the notes in the PR), so try to force that. */
-Index: gcc/testsuite/gcc.dg/pr60485-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr60485-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr60485-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,38 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2" } */
-+
-+extern void abort (void);
-+struct S {
-+ int *i[4];
-+ int *p1;
-+ int *p2;
-+ int *p3;
-+ int *p4;
-+ int **x;
-+};
-+int **b;
-+int main()
-+{
-+ int i = 1;
-+ struct S s;
-+ s.p3 = &i;
-+ int **p;
-+ if (b)
-+ p = b;
-+ else
-+ p = &s.i[2];
-+ p += 4;
-+ /* prevert fowrprop from creating an offsetted sd constraint and
-+ preserve the pointer offsetting constraint. */
-+ s.x = p;
-+ p = s.x;
-+ if (!b)
-+ {
-+ int *z = *p;
-+ /* z should point to i (and non-local/escaped). */
-+ *z = 0;
-+ }
-+ if (i != 0)
-+ abort ();
-+ return i;
-+}
-Index: gcc/testsuite/gcc.dg/atomic-store-6.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/atomic-store-6.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/atomic-store-6.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+/* { dg-do run } */
-+/* { dg-require-effective-target sync_int_128_runtime } */
-+/* { dg-options "-mcx16" { target { i?86-*-* x86_64-*-* } } } */
-+
-+__int128_t i;
-+
-+int main()
-+{
-+ __atomic_store_16(&i, -1, 0);
-+ if (i != -1)
-+ __builtin_abort();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/guality/pr59776.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/guality/pr59776.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/guality/pr59776.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* PR debug/59776 */
-+/* { dg-do run } */
-+/* { dg-options "-g" } */
-+
-+#include "../nop.h"
-+
-+struct S { float f, g; };
-+
-+__attribute__((noinline, noclone)) void
-+foo (struct S *p)
-+{
-+ struct S s1, s2; /* { dg-final { gdb-test pr59776.c:17 "s1.f" "5.0" } } */
-+ s1 = *p; /* { dg-final { gdb-test pr59776.c:17 "s1.g" "6.0" } } */
-+ s2 = s1; /* { dg-final { gdb-test pr59776.c:17 "s2.f" "0.0" } } */
-+ *(int *) &s2.f = 0; /* { dg-final { gdb-test pr59776.c:17 "s2.g" "6.0" } } */
-+ asm volatile (NOP : : : "memory"); /* { dg-final { gdb-test pr59776.c:20 "s1.f" "5.0" } } */
-+ asm volatile (NOP : : : "memory"); /* { dg-final { gdb-test pr59776.c:20 "s1.g" "6.0" } } */
-+ s2 = s1; /* { dg-final { gdb-test pr59776.c:20 "s2.f" "5.0" } } */
-+ asm volatile (NOP : : : "memory"); /* { dg-final { gdb-test pr59776.c:20 "s2.g" "6.0" } } */
-+ asm volatile (NOP : : : "memory");
-+}
-+
-+int
-+main ()
-+{
-+ struct S x = { 5.0f, 6.0f };
-+ foo (&x);
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/attr-weakref-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/attr-weakref-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/attr-weakref-1.c (.../branches/gcc-4_8-branch)
-@@ -4,12 +4,14 @@
- // This test requires support for undefined weak symbols. This support
- // is not available on hppa*-*-hpux*. The test is skipped rather than
- // xfailed to suppress the warning that would otherwise arise.
--// { dg-skip-if "" { "*-*-darwin*" "hppa*-*-hpux*" } "*" { "" } }
-+// { dg-skip-if "" { "hppa*-*-hpux*" } "*" { "" } }
- // For kernel modules and static RTPs, the loader treats undefined weak
- // symbols in the same way as undefined strong symbols. The test
- // therefore fails to load, so skip it.
- // { dg-skip-if "" { "*-*-vxworks*" && nonpic } "*" { "-non-static" } }
- // { dg-options "-O2" }
-+// { dg-additional-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } }
-+// { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } }
- // { dg-additional-sources "attr-weakref-1a.c" }
-
- // Copyright 2005 Free Software Foundation, Inc.
-Index: gcc/testsuite/gcc.dg/pr59827.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr59827.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr59827.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* PR middle-end/59827 */
-+/* { dg-do compile } */
-+
-+int
-+foo (int p[2][]) /* { dg-error "array type has incomplete element type" } */
-+{
-+ return p[0][0];
-+}
-+
-+void
-+bar (void)
-+{
-+ int p[2][1];
-+ foo (p); /* { dg-error "type of formal parameter 1 is incomplete" } */
-+}
-Index: gcc/testsuite/gcc.dg/vmx/stl-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/stl-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,83 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned char svbc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned short svbs[8] __attribute__ ((aligned (16)));
-+static unsigned short svp[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static unsigned int svbi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 16; ++i)
-+ {
-+ check (svuc[i] == i, "svuc");
-+ check (svsc[i] == i - 8, "svsc");
-+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");
-+ }
-+ for (i = 0; i < 8; ++i)
-+ {
-+ check (svus[i] == i, "svus");
-+ check (svss[i] == i - 4, "svss");
-+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");
-+ check (svp[i] == i, "svp");
-+ }
-+ for (i = 0; i < 4; ++i)
-+ {
-+ check (svui[i] == i, "svui");
-+ check (svsi[i] == i - 2, "svsi");
-+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");
-+ check (svf[i] == i * 1.0f, "svf");
-+ }
-+}
-+
-+static void test ()
-+{
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
-+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
-+ vector bool char vbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};
-+ vector unsigned short vus = {7,6,5,4,3,2,1,0};
-+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};
-+ vector bool short vbs = {65535,0,65535,0,65535,0,65535,0};
-+ vector pixel vp = {7,6,5,4,3,2,1,0};
-+ vector unsigned int vui = {3,2,1,0};
-+ vector signed int vsi = {1,0,-1,-2};
-+ vector bool int vbi = {0xffffffff,0,0xffffffff,0};
-+ vector float vf = {3.0,2.0,1.0,0.0};
-+#else
-+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
-+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};
-+ vector pixel vp = {0,1,2,3,4,5,6,7};
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};
-+ vector float vf = {0.0,1.0,2.0,3.0};
-+#endif
-+
-+ vec_stl (vuc, 0, (vector unsigned char *)svuc);
-+ vec_stl (vsc, 0, (vector signed char *)svsc);
-+ vec_stl (vbc, 0, (vector bool char *)svbc);
-+ vec_stl (vus, 0, (vector unsigned short *)svus);
-+ vec_stl (vss, 0, (vector signed short *)svss);
-+ vec_stl (vbs, 0, (vector bool short *)svbs);
-+ vec_stl (vp, 0, (vector pixel *)svp);
-+ vec_stl (vui, 0, (vector unsigned int *)svui);
-+ vec_stl (vsi, 0, (vector signed int *)svsi);
-+ vec_stl (vbi, 0, (vector bool int *)svbi);
-+ vec_stl (vf, 0, (vector float *)svf);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/vmx/perm-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/perm-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/perm-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,74 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned char vucb = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
-+ vector signed char vsca = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
-+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};
-+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed short vssb = {0,1,2,3,4,5,6,7};
-+ vector unsigned int vuia = {0,1,2,3};
-+ vector unsigned int vuib = {4,5,6,7};
-+ vector signed int vsia = {-4,-3,-2,-1};
-+ vector signed int vsib = {0,1,2,3};
-+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};
-+ vector float vfb = {0.0,1.0,2.0,3.0};
-+
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned char vucp = {15,16,14,17,13,18,12,19,11,20,10,21,9,22,8,23};
-+ vector unsigned char vscp = {15,16,14,17,13,18,12,19,11,20,10,21,9,22,8,23};
-+ vector unsigned char vusp = {15,14,17,16,13,12,19,18,11,10,21,20,9,8,23,22};
-+ vector unsigned char vssp = {15,14,17,16,13,12,19,18,11,10,21,20,9,8,23,22};
-+ vector unsigned char vuip = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};
-+ vector unsigned char vsip = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};
-+ vector unsigned char vfp = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};
-+#else
-+ vector unsigned char vucp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
-+ vector unsigned char vscp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
-+ vector unsigned char vusp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};
-+ vector unsigned char vssp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};
-+ vector unsigned char vuip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
-+ vector unsigned char vsip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
-+ vector unsigned char vfp = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
-+#endif
-+
-+ /* Result vectors. */
-+ vector unsigned char vuc;
-+ vector signed char vsc;
-+ vector unsigned short vus;
-+ vector signed short vss;
-+ vector unsigned int vui;
-+ vector signed int vsi;
-+ vector float vf;
-+
-+ /* Expected result vectors. */
-+ vector unsigned char vucr = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
-+ vector signed char vscr = {-16,15,-15,14,-14,13,-13,12,-12,11,-11,10,-10,9,-9,8};
-+ vector unsigned short vusr = {0,15,1,14,2,13,3,12};
-+ vector signed short vssr = {-8,7,-7,6,-6,5,-5,4};
-+ vector unsigned int vuir = {0,7,1,6};
-+ vector signed int vsir = {-4,3,-3,2};
-+ vector float vfr = {-4.0,3.0,-3.0,2.0};
-+
-+ vuc = vec_perm (vuca, vucb, vucp);
-+ vsc = vec_perm (vsca, vscb, vscp);
-+ vus = vec_perm (vusa, vusb, vusp);
-+ vss = vec_perm (vssa, vssb, vssp);
-+ vui = vec_perm (vuia, vuib, vuip);
-+ vsi = vec_perm (vsia, vsib, vsip);
-+ vf = vec_perm (vfa, vfb, vfp );
-+
-+ check (vec_all_eq (vuc, vucr), "vuc");
-+ check (vec_all_eq (vsc, vscr), "vsc");
-+ check (vec_all_eq (vus, vusr), "vus");
-+ check (vec_all_eq (vss, vssr), "vss");
-+ check (vec_all_eq (vui, vuir), "vui");
-+ check (vec_all_eq (vsi, vsir), "vsi");
-+ check (vec_all_eq (vf, vfr), "vf" );
-+}
-Index: gcc/testsuite/gcc.dg/vmx/insert-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/insert-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,65 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector unsigned short vc = {0,1,2,3,4,5,6,7};
-+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};
-+ vector unsigned int ve = {0,1,2,3};
-+ vector signed int vf = {-2,-1,0,1};
-+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};
-+
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ check (vec_all_eq (vec_insert (16, va, 5),
-+ ((vector unsigned char)
-+ {0,1,2,3,4,5,6,7,8,9,16,11,12,13,14,15})),
-+ "vec_insert (va LE)");
-+ check (vec_all_eq (vec_insert (-16, vb, 0),
-+ ((vector signed char)
-+ {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,-16})),
-+ "vec_insert (vb LE)");
-+ check (vec_all_eq (vec_insert (16, vc, 7),
-+ ((vector unsigned short){16,1,2,3,4,5,6,7})),
-+ "vec_insert (vc LE)");
-+ check (vec_all_eq (vec_insert (-16, vd, 3),
-+ ((vector signed short){-4,-3,-2,-1,-16,1,2,3})),
-+ "vec_insert (vd LE)");
-+ check (vec_all_eq (vec_insert (16, ve, 2),
-+ ((vector unsigned int){0,16,2,3})),
-+ "vec_insert (ve LE)");
-+ check (vec_all_eq (vec_insert (-16, vf, 1),
-+ ((vector signed int){-2,-1,-16,1})),
-+ "vec_insert (vf LE)");
-+ check (vec_all_eq (vec_insert (-16.0f, vg, 0),
-+ ((vector float){-2.0f,-1.0f,0.0f,-16.0f})),
-+ "vec_insert (vg LE)");
-+#else
-+ check (vec_all_eq (vec_insert (16, va, 5),
-+ ((vector unsigned char)
-+ {0,1,2,3,4,16,6,7,8,9,10,11,12,13,14,15})),
-+ "vec_insert (va BE)");
-+ check (vec_all_eq (vec_insert (-16, vb, 0),
-+ ((vector signed char)
-+ {-16,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7})),
-+ "vec_insert (vb BE)");
-+ check (vec_all_eq (vec_insert (16, vc, 7),
-+ ((vector unsigned short){0,1,2,3,4,5,6,16})),
-+ "vec_insert (vc BE)");
-+ check (vec_all_eq (vec_insert (-16, vd, 3),
-+ ((vector signed short){-4,-3,-2,-16,0,1,2,3})),
-+ "vec_insert (vd BE)");
-+ check (vec_all_eq (vec_insert (16, ve, 2),
-+ ((vector unsigned int){0,1,16,3})),
-+ "vec_insert (ve BE)");
-+ check (vec_all_eq (vec_insert (-16, vf, 1),
-+ ((vector signed int){-2,-16,0,1})),
-+ "vec_insert (vf BE)");
-+ check (vec_all_eq (vec_insert (-16.0f, vg, 0),
-+ ((vector float){-16.0f,-1.0f,0.0f,1.0f})),
-+ "vec_insert (vg BE)");
-+#endif
-+}
-+
-Index: gcc/testsuite/gcc.dg/vmx/ldl.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ldl.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,91 @@
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned char svbc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned short svbs[8] __attribute__ ((aligned (16)));
-+static unsigned short svp[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static unsigned int svbi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 16; ++i)
-+ {
-+ svuc[i] = i;
-+ svsc[i] = i - 8;
-+ svbc[i] = (i % 2) ? 0xff : 0;
-+ }
-+ for (i = 0; i < 8; ++i)
-+ {
-+ svus[i] = i;
-+ svss[i] = i - 4;
-+ svbs[i] = (i % 2) ? 0xffff : 0;
-+ svp[i] = i;
-+ }
-+ for (i = 0; i < 4; ++i)
-+ {
-+ svui[i] = i;
-+ svsi[i] = i - 2;
-+ svbi[i] = (i % 2) ? 0xffffffff : 0;
-+ svf[i] = i * 1.0f;
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
-+ vector unsigned short evus = {0,1,2,3,4,5,6,7};
-+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};
-+ vector pixel evp = {0,1,2,3,4,5,6,7};
-+ vector unsigned int evui = {0,1,2,3};
-+ vector signed int evsi = {-2,-1,0,1};
-+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};
-+ vector float evf = {0.0,1.0,2.0,3.0};
-+
-+ vector unsigned char vuc;
-+ vector signed char vsc;
-+ vector bool char vbc;
-+ vector unsigned short vus;
-+ vector signed short vss;
-+ vector bool short vbs;
-+ vector pixel vp;
-+ vector unsigned int vui;
-+ vector signed int vsi;
-+ vector bool int vbi;
-+ vector float vf;
-+
-+ init ();
-+
-+ vuc = vec_ldl (0, (vector unsigned char *)svuc);
-+ vsc = vec_ldl (0, (vector signed char *)svsc);
-+ vbc = vec_ldl (0, (vector bool char *)svbc);
-+ vus = vec_ldl (0, (vector unsigned short *)svus);
-+ vss = vec_ldl (0, (vector signed short *)svss);
-+ vbs = vec_ldl (0, (vector bool short *)svbs);
-+ vp = vec_ldl (0, (vector pixel *)svp);
-+ vui = vec_ldl (0, (vector unsigned int *)svui);
-+ vsi = vec_ldl (0, (vector signed int *)svsi);
-+ vbi = vec_ldl (0, (vector bool int *)svbi);
-+ vf = vec_ldl (0, (vector float *)svf);
-+
-+ check (vec_all_eq (vuc, evuc), "vuc");
-+ check (vec_all_eq (vsc, evsc), "vsc");
-+ check (vec_all_eq (vbc, evbc), "vbc");
-+ check (vec_all_eq (vus, evus), "vus");
-+ check (vec_all_eq (vss, evss), "vss");
-+ check (vec_all_eq (vbs, evbs), "vbs");
-+ check (vec_all_eq (vp, evp ), "vp" );
-+ check (vec_all_eq (vui, evui), "vui");
-+ check (vec_all_eq (vsi, evsi), "vsi");
-+ check (vec_all_eq (vbi, evbi), "vbi");
-+ check (vec_all_eq (vf, evf ), "vf" );
-+}
-Index: gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,34 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned long long svul[2] __attribute__ ((aligned (16)));
-+static double svd[2] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 2; ++i)
-+ {
-+ check (svul[i] == i, "svul");
-+ check (svd[i] == i * 1.0, "svd");
-+ }
-+}
-+
-+static void test ()
-+{
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned long long vul = {1,0};
-+ vector double vd = {1.0,0.0};
-+#else
-+ vector unsigned long long vul = {0,1};
-+ vector double vd = {0.0,1.0};
-+#endif
-+
-+ vec_stl (vul, 0, (vector unsigned long long *)svul);
-+ vec_stl (vd, 0, (vector double *)svd);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/vmx/vsums.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/vsums.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/vsums.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector signed int va = {-7,11,-13,17};
-+ vector signed int vb = {0,0,0,128};
-+ vector signed int evd = {0,0,0,136};
-+
-+ vector signed int vd = vec_sums (va, vb);
-+
-+ check (vec_all_eq (vd, evd), "sums");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,34 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static int vec_long_long_eq (vector long long x, vector long long y)
-+{
-+ return (x[0] == y[0] && x[1] == y[1]);
-+}
-+
-+static int vec_dbl_eq (vector double x, vector double y)
-+{
-+ return (x[0] == y[0] && x[1] == y[1]);
-+}
-+
-+static void test()
-+{
-+ vector long long vl = {0, 1};
-+ vector double vd = {0.0, 1.0};
-+ vector long long vlr = vec_insert (2, vl, 0);
-+ vector double vdr = vec_insert (2.0, vd, 1);
-+
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector long long vler = {0, 2};
-+ vector double vder = {2.0, 1.0};
-+#else
-+ vector long long vler = {2, 1};
-+ vector double vder = {0.0, 2.0};
-+#endif
-+
-+ check (vec_long_long_eq (vlr, vler), "vl");
-+ check (vec_dbl_eq (vdr, vder), "vd");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/unpack.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/unpack.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/unpack.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,67 @@
-+#include "harness.h"
-+
-+#define BIG 4294967295
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char vbc = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};
-+ vector pixel vp = {(0<<15) + (1<<10) + (2<<5) + 3,
-+ (1<<15) + (4<<10) + (5<<5) + 6,
-+ (0<<15) + (7<<10) + (8<<5) + 9,
-+ (1<<15) + (10<<10) + (11<<5) + 12,
-+ (1<<15) + (13<<10) + (14<<5) + 15,
-+ (0<<15) + (16<<10) + (17<<5) + 18,
-+ (1<<15) + (19<<10) + (20<<5) + 21,
-+ (0<<15) + (22<<10) + (23<<5) + 24};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short vbs = {0,65535,65535,0,0,0,65535,0};
-+
-+ /* Result vectors. */
-+ vector signed short vsch, vscl;
-+ vector bool short vbsh, vbsl;
-+ vector unsigned int vuih, vuil;
-+ vector signed int vsih, vsil;
-+ vector bool int vbih, vbil;
-+
-+ /* Expected result vectors. */
-+ vector signed short vschr = {-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed short vsclr = {0,1,2,3,4,5,6,7};
-+ vector bool short vbshr = {0,65535,65535,0,0,0,65535,0};
-+ vector bool short vbslr = {65535,0,0,65535,65535,65535,0,65535};
-+ vector unsigned int vuihr = {(0<<24) + (1<<16) + (2<<8) + 3,
-+ (65535<<24) + (4<<16) + (5<<8) + 6,
-+ (0<<24) + (7<<16) + (8<<8) + 9,
-+ (65535<<24) + (10<<16) + (11<<8) + 12};
-+ vector unsigned int vuilr = {(65535<<24) + (13<<16) + (14<<8) + 15,
-+ (0<<24) + (16<<16) + (17<<8) + 18,
-+ (65535<<24) + (19<<16) + (20<<8) + 21,
-+ (0<<24) + (22<<16) + (23<<8) + 24};
-+ vector signed int vsihr = {-4,-3,-2,-1};
-+ vector signed int vsilr = {0,1,2,3};
-+ vector bool int vbihr = {0,BIG,BIG,0};
-+ vector bool int vbilr = {0,0,BIG,0};
-+
-+ vsch = vec_unpackh (vsc);
-+ vscl = vec_unpackl (vsc);
-+ vbsh = vec_unpackh (vbc);
-+ vbsl = vec_unpackl (vbc);
-+ vuih = vec_unpackh (vp);
-+ vuil = vec_unpackl (vp);
-+ vsih = vec_unpackh (vss);
-+ vsil = vec_unpackl (vss);
-+ vbih = vec_unpackh (vbs);
-+ vbil = vec_unpackl (vbs);
-+
-+ check (vec_all_eq (vsch, vschr), "vsch");
-+ check (vec_all_eq (vscl, vsclr), "vscl");
-+ check (vec_all_eq (vbsh, vbshr), "vbsh");
-+ check (vec_all_eq (vbsl, vbslr), "vbsl");
-+ check (vec_all_eq (vuih, vuihr), "vuih");
-+ check (vec_all_eq (vuil, vuilr), "vuil");
-+ check (vec_all_eq (vsih, vsihr), "vsih");
-+ check (vec_all_eq (vsil, vsilr), "vsil");
-+ check (vec_all_eq (vbih, vbihr), "vbih");
-+ check (vec_all_eq (vbil, vbilr), "vbil");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/splat.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/splat.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/splat.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,47 @@
-+#include "harness.h"
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector float vf = {-2.0,-1.0,0.0,1.0};
-+
-+ /* Result vectors. */
-+ vector unsigned char vucr;
-+ vector signed char vscr;
-+ vector unsigned short vusr;
-+ vector signed short vssr;
-+ vector unsigned int vuir;
-+ vector signed int vsir;
-+ vector float vfr;
-+
-+ /* Expected result vectors. */
-+ vector unsigned char vucer = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
-+ vector signed char vscer = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
-+ vector unsigned short vuser = {7,7,7,7,7,7,7,7};
-+ vector signed short vsser = {-4,-4,-4,-4,-4,-4,-4,-4};
-+ vector unsigned int vuier = {2,2,2,2};
-+ vector signed int vsier = {1,1,1,1};
-+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};
-+
-+ vucr = vec_splat (vuc, 1);
-+ vscr = vec_splat (vsc, 8);
-+ vusr = vec_splat (vus, 7);
-+ vssr = vec_splat (vss, 0);
-+ vuir = vec_splat (vui, 2);
-+ vsir = vec_splat (vsi, 3);
-+ vfr = vec_splat (vf, 1);
-+
-+ check (vec_all_eq (vucr, vucer), "vuc");
-+ check (vec_all_eq (vscr, vscer), "vsc");
-+ check (vec_all_eq (vusr, vuser), "vus");
-+ check (vec_all_eq (vssr, vsser), "vss");
-+ check (vec_all_eq (vuir, vuier), "vui");
-+ check (vec_all_eq (vsir, vsier), "vsi");
-+ check (vec_all_eq (vfr, vfer ), "vf");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,44 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned long long svul[2] __attribute__ ((aligned (16)));
-+static double svd[2] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 2; ++i)
-+ {
-+ svul[i] = i;
-+ svd[i] = i * 1.0;
-+ }
-+}
-+
-+static void test ()
-+{
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned long long evul = {1,0};
-+ vector double evd = {1.0,0.0};
-+#else
-+ vector unsigned long long evul = {0,1};
-+ vector double evd = {0.0,1.0};
-+#endif
-+
-+ vector unsigned long long vul;
-+ vector double vd;
-+ unsigned i;
-+
-+ init ();
-+
-+ vul = vec_ldl (0, (vector unsigned long long *)svul);
-+ vd = vec_ldl (0, (vector double *)svd);
-+
-+ for (i = 0; i < 2; ++i)
-+ {
-+ check (vul[i] == evul[i], "vul");
-+ check (vd[i] == evd[i], "vd" );
-+ }
-+}
-Index: gcc/testsuite/gcc.dg/vmx/merge-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/merge-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,96 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned char vucb
-+ = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
-+ vector signed char vsca
-+ = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
-+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};
-+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed short vssb = {0,1,2,3,4,5,6,7};
-+ vector unsigned int vuia = {0,1,2,3};
-+ vector unsigned int vuib = {4,5,6,7};
-+ vector signed int vsia = {-4,-3,-2,-1};
-+ vector signed int vsib = {0,1,2,3};
-+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};
-+ vector float vfb = {0.0,1.0,2.0,3.0};
-+
-+ /* Result vectors. */
-+ vector unsigned char vuch, vucl;
-+ vector signed char vsch, vscl;
-+ vector unsigned short vush, vusl;
-+ vector signed short vssh, vssl;
-+ vector unsigned int vuih, vuil;
-+ vector signed int vsih, vsil;
-+ vector float vfh, vfl;
-+
-+ /* Expected result vectors. */
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned char vucrh = {24,8,25,9,26,10,27,11,28,12,29,13,30,14,31,15};
-+ vector unsigned char vucrl = {16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7};
-+ vector signed char vscrh = {8,-8,9,-7,10,-6,11,-5,12,-4,13,-3,14,-2,15,-1};
-+ vector signed char vscrl = {0,-16,1,-15,2,-14,3,-13,4,-12,5,-11,6,-10,7,-9};
-+ vector unsigned short vusrh = {12,4,13,5,14,6,15,7};
-+ vector unsigned short vusrl = {8,0,9,1,10,2,11,3};
-+ vector signed short vssrh = {4,-4,5,-3,6,-2,7,-1};
-+ vector signed short vssrl = {0,-8,1,-7,2,-6,3,-5};
-+ vector unsigned int vuirh = {6,2,7,3};
-+ vector unsigned int vuirl = {4,0,5,1};
-+ vector signed int vsirh = {2,-2,3,-1};
-+ vector signed int vsirl = {0,-4,1,-3};
-+ vector float vfrh = {2.0,-2.0,3.0,-1.0};
-+ vector float vfrl = {0.0,-4.0,1.0,-3.0};
-+#else
-+ vector unsigned char vucrh = {0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23};
-+ vector unsigned char vucrl = {8,24,9,25,10,26,11,27,12,28,13,29,14,30,15,31};
-+ vector signed char vscrh = {-16,0,-15,1,-14,2,-13,3,-12,4,-11,5,-10,6,-9,7};
-+ vector signed char vscrl = {-8,8,-7,9,-6,10,-5,11,-4,12,-3,13,-2,14,-1,15};
-+ vector unsigned short vusrh = {0,8,1,9,2,10,3,11};
-+ vector unsigned short vusrl = {4,12,5,13,6,14,7,15};
-+ vector signed short vssrh = {-8,0,-7,1,-6,2,-5,3};
-+ vector signed short vssrl = {-4,4,-3,5,-2,6,-1,7};
-+ vector unsigned int vuirh = {0,4,1,5};
-+ vector unsigned int vuirl = {2,6,3,7};
-+ vector signed int vsirh = {-4,0,-3,1};
-+ vector signed int vsirl = {-2,2,-1,3};
-+ vector float vfrh = {-4.0,0.0,-3.0,1.0};
-+ vector float vfrl = {-2.0,2.0,-1.0,3.0};
-+#endif
-+
-+ vuch = vec_mergeh (vuca, vucb);
-+ vucl = vec_mergel (vuca, vucb);
-+ vsch = vec_mergeh (vsca, vscb);
-+ vscl = vec_mergel (vsca, vscb);
-+ vush = vec_mergeh (vusa, vusb);
-+ vusl = vec_mergel (vusa, vusb);
-+ vssh = vec_mergeh (vssa, vssb);
-+ vssl = vec_mergel (vssa, vssb);
-+ vuih = vec_mergeh (vuia, vuib);
-+ vuil = vec_mergel (vuia, vuib);
-+ vsih = vec_mergeh (vsia, vsib);
-+ vsil = vec_mergel (vsia, vsib);
-+ vfh = vec_mergeh (vfa, vfb );
-+ vfl = vec_mergel (vfa, vfb );
-+
-+ check (vec_all_eq (vuch, vucrh), "vuch");
-+ check (vec_all_eq (vucl, vucrl), "vucl");
-+ check (vec_all_eq (vsch, vscrh), "vsch");
-+ check (vec_all_eq (vscl, vscrl), "vscl");
-+ check (vec_all_eq (vush, vusrh), "vush");
-+ check (vec_all_eq (vusl, vusrl), "vusl");
-+ check (vec_all_eq (vssh, vssrh), "vssh");
-+ check (vec_all_eq (vssl, vssrl), "vssl");
-+ check (vec_all_eq (vuih, vuirh), "vuih");
-+ check (vec_all_eq (vuil, vuirl), "vuil");
-+ check (vec_all_eq (vsih, vsirh), "vsih");
-+ check (vec_all_eq (vsil, vsirl), "vsil");
-+ check (vec_all_eq (vfh, vfrh), "vfh");
-+ check (vec_all_eq (vfl, vfrl), "vfl");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector float vf = {-2.0,-1.0,0.0,1.0};
-+
-+ /* Result vectors. */
-+ vector unsigned int vuir;
-+ vector signed int vsir;
-+ vector float vfr;
-+
-+ /* Expected result vectors. */
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned int vuier = {1,1,1,1};
-+ vector signed int vsier = {-2,-2,-2,-2};
-+ vector float vfer = {0.0,0.0,0.0,0.0};
-+#else
-+ vector unsigned int vuier = {2,2,2,2};
-+ vector signed int vsier = {1,1,1,1};
-+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};
-+#endif
-+
-+ vuir = vec_splat (vui, 2);
-+ vsir = vec_splat (vsi, 3);
-+ vfr = vec_splat (vf, 1);
-+
-+ check (vec_all_eq (vuir, vuier), "vui");
-+ check (vec_all_eq (vsir, vsier), "vsi");
-+ check (vec_all_eq (vfr, vfer ), "vf");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/merge.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/merge.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/merge.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,77 @@
-+#include "harness.h"
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned char vucb
-+ = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
-+ vector signed char vsca
-+ = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
-+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};
-+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed short vssb = {0,1,2,3,4,5,6,7};
-+ vector unsigned int vuia = {0,1,2,3};
-+ vector unsigned int vuib = {4,5,6,7};
-+ vector signed int vsia = {-4,-3,-2,-1};
-+ vector signed int vsib = {0,1,2,3};
-+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};
-+ vector float vfb = {0.0,1.0,2.0,3.0};
-+
-+ /* Result vectors. */
-+ vector unsigned char vuch, vucl;
-+ vector signed char vsch, vscl;
-+ vector unsigned short vush, vusl;
-+ vector signed short vssh, vssl;
-+ vector unsigned int vuih, vuil;
-+ vector signed int vsih, vsil;
-+ vector float vfh, vfl;
-+
-+ /* Expected result vectors. */
-+ vector unsigned char vucrh = {0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23};
-+ vector unsigned char vucrl = {8,24,9,25,10,26,11,27,12,28,13,29,14,30,15,31};
-+ vector signed char vscrh = {-16,0,-15,1,-14,2,-13,3,-12,4,-11,5,-10,6,-9,7};
-+ vector signed char vscrl = {-8,8,-7,9,-6,10,-5,11,-4,12,-3,13,-2,14,-1,15};
-+ vector unsigned short vusrh = {0,8,1,9,2,10,3,11};
-+ vector unsigned short vusrl = {4,12,5,13,6,14,7,15};
-+ vector signed short vssrh = {-8,0,-7,1,-6,2,-5,3};
-+ vector signed short vssrl = {-4,4,-3,5,-2,6,-1,7};
-+ vector unsigned int vuirh = {0,4,1,5};
-+ vector unsigned int vuirl = {2,6,3,7};
-+ vector signed int vsirh = {-4,0,-3,1};
-+ vector signed int vsirl = {-2,2,-1,3};
-+ vector float vfrh = {-4.0,0.0,-3.0,1.0};
-+ vector float vfrl = {-2.0,2.0,-1.0,3.0};
-+
-+ vuch = vec_mergeh (vuca, vucb);
-+ vucl = vec_mergel (vuca, vucb);
-+ vsch = vec_mergeh (vsca, vscb);
-+ vscl = vec_mergel (vsca, vscb);
-+ vush = vec_mergeh (vusa, vusb);
-+ vusl = vec_mergel (vusa, vusb);
-+ vssh = vec_mergeh (vssa, vssb);
-+ vssl = vec_mergel (vssa, vssb);
-+ vuih = vec_mergeh (vuia, vuib);
-+ vuil = vec_mergel (vuia, vuib);
-+ vsih = vec_mergeh (vsia, vsib);
-+ vsil = vec_mergel (vsia, vsib);
-+ vfh = vec_mergeh (vfa, vfb );
-+ vfl = vec_mergel (vfa, vfb );
-+
-+ check (vec_all_eq (vuch, vucrh), "vuch");
-+ check (vec_all_eq (vucl, vucrl), "vucl");
-+ check (vec_all_eq (vsch, vscrh), "vsch");
-+ check (vec_all_eq (vscl, vscrl), "vscl");
-+ check (vec_all_eq (vush, vusrh), "vush");
-+ check (vec_all_eq (vusl, vusrl), "vusl");
-+ check (vec_all_eq (vssh, vssrh), "vssh");
-+ check (vec_all_eq (vssl, vssrl), "vssl");
-+ check (vec_all_eq (vuih, vuirh), "vuih");
-+ check (vec_all_eq (vuil, vuirl), "vuil");
-+ check (vec_all_eq (vsih, vsirh), "vsih");
-+ check (vec_all_eq (vsil, vsirl), "vsil");
-+ check (vec_all_eq (vfh, vfrh), "vfh");
-+ check (vec_all_eq (vfl, vfrl), "vfl");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/vec-set.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/vec-set.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/vec-set.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+#include "harness.h"
-+
-+vector short
-+vec_set (short m)
-+{
-+ return (vector short){m, 0, 0, 0, 0, 0, 0, 0};
-+}
-+
-+static void test()
-+{
-+ check (vec_all_eq (vec_set (7),
-+ ((vector short){7, 0, 0, 0, 0, 0, 0, 0})),
-+ "vec_set");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,44 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned long long svul[2] __attribute__ ((aligned (16)));
-+static double svd[2] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 2; ++i)
-+ {
-+ svul[i] = i;
-+ svd[i] = i * 1.0;
-+ }
-+}
-+
-+static void test ()
-+{
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned long long evul = {1,0};
-+ vector double evd = {1.0,0.0};
-+#else
-+ vector unsigned long long evul = {0,1};
-+ vector double evd = {0.0,1.0};
-+#endif
-+
-+ vector unsigned long long vul;
-+ vector double vd;
-+ unsigned i;
-+
-+ init ();
-+
-+ vul = vec_ld (0, (vector unsigned long long *)svul);
-+ vd = vec_ld (0, (vector double *)svd);
-+
-+ for (i = 0; i < 2; ++i)
-+ {
-+ check (vul[i] == evul[i], "vul");
-+ check (vd[i] == evd[i], "vd" );
-+ }
-+}
-Index: gcc/testsuite/gcc.dg/vmx/extract.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/extract.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/extract.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector unsigned short vc = {0,1,2,3,4,5,6,7};
-+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};
-+ vector unsigned int ve = {0,1,2,3};
-+ vector signed int vf = {-2,-1,0,1};
-+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};
-+
-+ check (vec_extract (va, 5) == 5, "vec_extract (va, 5)");
-+ check (vec_extract (vb, 0) == -8, "vec_extract (vb, 0)");
-+ check (vec_extract (vc, 7) == 7, "vec_extract (vc, 7)");
-+ check (vec_extract (vd, 3) == -1, "vec_extract (vd, 3)");
-+ check (vec_extract (ve, 2) == 2, "vec_extract (ve, 2)");
-+ check (vec_extract (vf, 1) == -1, "vec_extract (vf, 1)");
-+ check (vec_extract (vg, 0) == -2.0f, "vec_extract (vg, 0)");
-+}
-+
-Index: gcc/testsuite/gcc.dg/vmx/pack-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/pack-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/pack-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,136 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+#define BIG 4294967295
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
-+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};
-+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed short vssb = {0,1,2,3,4,5,6,7};
-+ vector bool short vbsa = {0,65535,65535,0,0,0,65535,0};
-+ vector bool short vbsb = {65535,0,0,65535,65535,65535,0,65535};
-+ vector unsigned int vuia = {0,1,2,3};
-+ vector unsigned int vuib = {4,5,6,7};
-+ vector signed int vsia = {-4,-3,-2,-1};
-+ vector signed int vsib = {0,1,2,3};
-+ vector bool int vbia = {0,BIG,BIG,BIG};
-+ vector bool int vbib = {BIG,0,0,0};
-+ vector unsigned int vipa = {(0<<24) + (2<<19) + (3<<11) + (4<<3),
-+ (1<<24) + (5<<19) + (6<<11) + (7<<3),
-+ (0<<24) + (8<<19) + (9<<11) + (10<<3),
-+ (1<<24) + (11<<19) + (12<<11) + (13<<3)};
-+ vector unsigned int vipb = {(1<<24) + (14<<19) + (15<<11) + (16<<3),
-+ (0<<24) + (17<<19) + (18<<11) + (19<<3),
-+ (1<<24) + (20<<19) + (21<<11) + (22<<3),
-+ (0<<24) + (23<<19) + (24<<11) + (25<<3)};
-+ vector unsigned short vusc = {0,256,1,257,2,258,3,259};
-+ vector unsigned short vusd = {4,260,5,261,6,262,7,263};
-+ vector signed short vssc = {-1,-128,0,127,-2,-129,1,128};
-+ vector signed short vssd = {-3,-130,2,129,-4,-131,3,130};
-+ vector unsigned int vuic = {0,65536,1,65537};
-+ vector unsigned int vuid = {2,65538,3,65539};
-+ vector signed int vsic = {-1,-32768,0,32767};
-+ vector signed int vsid = {-2,-32769,1,32768};
-+
-+ /* Result vectors. */
-+ vector unsigned char vucr;
-+ vector signed char vscr;
-+ vector bool char vbcr;
-+ vector unsigned short vusr;
-+ vector signed short vssr;
-+ vector bool short vbsr;
-+ vector pixel vpr;
-+ vector unsigned char vucsr;
-+ vector signed char vscsr;
-+ vector unsigned short vussr;
-+ vector signed short vsssr;
-+ vector unsigned char vucsur1, vucsur2;
-+ vector unsigned short vussur1, vussur2;
-+
-+ /* Expected result vectors. */
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned char vucer = {8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7};
-+ vector signed char vscer = {0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector bool char vbcer = {255,0,0,255,255,255,0,255,0,255,255,0,0,0,255,0};
-+ vector unsigned short vuser = {4,5,6,7,0,1,2,3};
-+ vector signed short vsser = {0,1,2,3,-4,-3,-2,-1};
-+ vector bool short vbser = {65535,0,0,0,0,65535,65535,65535};
-+ vector pixel vper = {(1<<15) + (14<<10) + (15<<5) + 16,
-+ (0<<15) + (17<<10) + (18<<5) + 19,
-+ (1<<15) + (20<<10) + (21<<5) + 22,
-+ (0<<15) + (23<<10) + (24<<5) + 25,
-+ (0<<15) + (2<<10) + (3<<5) + 4,
-+ (1<<15) + (5<<10) + (6<<5) + 7,
-+ (0<<15) + (8<<10) + (9<<5) + 10,
-+ (1<<15) + (11<<10) + (12<<5) + 13};
-+ vector unsigned char vucser = {4,255,5,255,6,255,7,255,0,255,1,255,2,255,3,255};
-+ vector signed char vscser = {-3,-128,2,127,-4,-128,3,127,
-+ -1,-128,0,127,-2,-128,1,127};
-+ vector unsigned short vusser = {2,65535,3,65535,0,65535,1,65535};
-+ vector signed short vssser = {-2,-32768,1,32767,-1,-32768,0,32767};
-+ vector unsigned char vucsuer1 = {4,255,5,255,6,255,7,255,0,255,1,255,2,255,3,255};
-+ vector unsigned char vucsuer2 = {0,0,2,129,0,0,3,130,0,0,0,127,0,0,1,128};
-+ vector unsigned short vussuer1 = {2,65535,3,65535,0,65535,1,65535};
-+ vector unsigned short vussuer2 = {0,0,1,32768,0,0,0,32767};
-+#else
-+ vector unsigned char vucer = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vscer = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char vbcer = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};
-+ vector unsigned short vuser = {0,1,2,3,4,5,6,7};
-+ vector signed short vsser = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short vbser = {0,65535,65535,65535,65535,0,0,0};
-+ vector pixel vper = {(0<<15) + (2<<10) + (3<<5) + 4,
-+ (1<<15) + (5<<10) + (6<<5) + 7,
-+ (0<<15) + (8<<10) + (9<<5) + 10,
-+ (1<<15) + (11<<10) + (12<<5) + 13,
-+ (1<<15) + (14<<10) + (15<<5) + 16,
-+ (0<<15) + (17<<10) + (18<<5) + 19,
-+ (1<<15) + (20<<10) + (21<<5) + 22,
-+ (0<<15) + (23<<10) + (24<<5) + 25};
-+ vector unsigned char vucser = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};
-+ vector signed char vscser = {-1,-128,0,127,-2,-128,1,127,
-+ -3,-128,2,127,-4,-128,3,127};
-+ vector unsigned short vusser = {0,65535,1,65535,2,65535,3,65535};
-+ vector signed short vssser = {-1,-32768,0,32767,-2,-32768,1,32767};
-+ vector unsigned char vucsuer1 = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};
-+ vector unsigned char vucsuer2 = {0,0,0,127,0,0,1,128,0,0,2,129,0,0,3,130};
-+ vector unsigned short vussuer1 = {0,65535,1,65535,2,65535,3,65535};
-+ vector unsigned short vussuer2 = {0,0,0,32767,0,0,1,32768};
-+#endif
-+
-+ vucr = vec_pack (vusa, vusb);
-+ vscr = vec_pack (vssa, vssb);
-+ vbcr = vec_pack (vbsa, vbsb);
-+ vusr = vec_pack (vuia, vuib);
-+ vssr = vec_pack (vsia, vsib);
-+ vbsr = vec_pack (vbia, vbib);
-+ vpr = vec_packpx (vipa, vipb);
-+ vucsr = vec_packs (vusc, vusd);
-+ vscsr = vec_packs (vssc, vssd);
-+ vussr = vec_packs (vuic, vuid);
-+ vsssr = vec_packs (vsic, vsid);
-+ vucsur1 = vec_packsu (vusc, vusd);
-+ vucsur2 = vec_packsu (vssc, vssd);
-+ vussur1 = vec_packsu (vuic, vuid);
-+ vussur2 = vec_packsu (vsic, vsid);
-+
-+ check (vec_all_eq (vucr, vucer), "vucr");
-+ check (vec_all_eq (vscr, vscer), "vscr");
-+ check (vec_all_eq (vbcr, vbcer), "vbcr");
-+ check (vec_all_eq (vusr, vuser), "vusr");
-+ check (vec_all_eq (vssr, vsser), "vssr");
-+ check (vec_all_eq (vbsr, vbser), "vbsr");
-+ check (vec_all_eq (vpr, vper ), "vpr" );
-+ check (vec_all_eq (vucsr, vucser), "vucsr");
-+ check (vec_all_eq (vscsr, vscser), "vscsr");
-+ check (vec_all_eq (vussr, vusser), "vussr");
-+ check (vec_all_eq (vsssr, vssser), "vsssr");
-+ check (vec_all_eq (vucsur1, vucsuer1), "vucsur1");
-+ check (vec_all_eq (vucsur2, vucsuer2), "vucsur2");
-+ check (vec_all_eq (vussur1, vussuer1), "vussur1");
-+ check (vec_all_eq (vussur2, vussuer2), "vussur2");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/st-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/st-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/st-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,83 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned char svbc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned short svbs[8] __attribute__ ((aligned (16)));
-+static unsigned short svp[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static unsigned int svbi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 16; ++i)
-+ {
-+ check (svuc[i] == i, "svuc");
-+ check (svsc[i] == i - 8, "svsc");
-+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");
-+ }
-+ for (i = 0; i < 8; ++i)
-+ {
-+ check (svus[i] == i, "svus");
-+ check (svss[i] == i - 4, "svss");
-+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");
-+ check (svp[i] == i, "svp");
-+ }
-+ for (i = 0; i < 4; ++i)
-+ {
-+ check (svui[i] == i, "svui");
-+ check (svsi[i] == i - 2, "svsi");
-+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");
-+ check (svf[i] == i * 1.0f, "svf");
-+ }
-+}
-+
-+static void test ()
-+{
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
-+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
-+ vector bool char vbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};
-+ vector unsigned short vus = {7,6,5,4,3,2,1,0};
-+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};
-+ vector bool short vbs = {65535,0,65535,0,65535,0,65535,0};
-+ vector pixel vp = {7,6,5,4,3,2,1,0};
-+ vector unsigned int vui = {3,2,1,0};
-+ vector signed int vsi = {1,0,-1,-2};
-+ vector bool int vbi = {0xffffffff,0,0xffffffff,0};
-+ vector float vf = {3.0,2.0,1.0,0.0};
-+#else
-+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
-+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};
-+ vector pixel vp = {0,1,2,3,4,5,6,7};
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};
-+ vector float vf = {0.0,1.0,2.0,3.0};
-+#endif
-+
-+ vec_st (vuc, 0, (vector unsigned char *)svuc);
-+ vec_st (vsc, 0, (vector signed char *)svsc);
-+ vec_st (vbc, 0, (vector bool char *)svbc);
-+ vec_st (vus, 0, (vector unsigned short *)svus);
-+ vec_st (vss, 0, (vector signed short *)svss);
-+ vec_st (vbs, 0, (vector bool short *)svbs);
-+ vec_st (vp, 0, (vector pixel *)svp);
-+ vec_st (vui, 0, (vector unsigned int *)svui);
-+ vec_st (vsi, 0, (vector signed int *)svsi);
-+ vec_st (vbi, 0, (vector bool int *)svbi);
-+ vec_st (vf, 0, (vector float *)svf);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c (.../branches/gcc-4_8-branch)
-@@ -13,6 +13,20 @@
- #define DO_INLINE __attribute__ ((always_inline))
- #define DONT_INLINE __attribute__ ((noinline))
-
-+#ifdef __LITTLE_ENDIAN__
-+static inline DO_INLINE int inline_me(vector signed short data)
-+{
-+ union {vector signed short v; signed short s[8];} u;
-+ signed short x;
-+ unsigned char x1, x2;
-+
-+ u.v = data;
-+ x = u.s[7];
-+ x1 = (x >> 8) & 0xff;
-+ x2 = x & 0xff;
-+ return ((x2 << 8) | x1);
-+}
-+#else
- static inline DO_INLINE int inline_me(vector signed short data)
- {
- union {vector signed short v; signed short s[8];} u;
-@@ -19,6 +33,7 @@
- u.v = data;
- return u.s[7];
- }
-+#endif
-
- static DONT_INLINE int foo(vector signed short data)
- {
-Index: gcc/testsuite/gcc.dg/vmx/eg-5.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/eg-5.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/eg-5.c (.../branches/gcc-4_8-branch)
-@@ -6,12 +6,10 @@
- {
- /* Set result to a vector of f32 0's */
- vector float result = ((vector float){0.,0.,0.,0.});
--
- result = vec_madd (c0, vec_splat (v, 0), result);
- result = vec_madd (c1, vec_splat (v, 1), result);
- result = vec_madd (c2, vec_splat (v, 2), result);
- result = vec_madd (c3, vec_splat (v, 3), result);
--
- return result;
- }
-
-Index: gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,34 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned long long svul[2] __attribute__ ((aligned (16)));
-+static double svd[2] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 2; ++i)
-+ {
-+ check (svul[i] == i, "svul");
-+ check (svd[i] == i * 1.0, "svd");
-+ }
-+}
-+
-+static void test ()
-+{
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned long long vul = {1,0};
-+ vector double vd = {1.0,0.0};
-+#else
-+ vector unsigned long long vul = {0,1};
-+ vector double vd = {0.0,1.0};
-+#endif
-+
-+ vec_st (vul, 0, (vector unsigned long long *)svul);
-+ vec_st (vd, 0, (vector double *)svd);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/vmx/lde.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/lde.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/lde.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,59 @@
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 16; ++i)
-+ {
-+ svuc[i] = i;
-+ svsc[i] = i - 8;
-+ }
-+ for (i = 0; i < 8; ++i)
-+ {
-+ svus[i] = i;
-+ svss[i] = i - 4;
-+ }
-+ for (i = 0; i < 4; ++i)
-+ {
-+ svui[i] = i;
-+ svsi[i] = i - 2;
-+ svf[i] = i * 1.0f;
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned char vuc;
-+ vector signed char vsc;
-+ vector unsigned short vus;
-+ vector signed short vss;
-+ vector unsigned int vui;
-+ vector signed int vsi;
-+ vector float vf;
-+
-+ init ();
-+
-+ vuc = vec_lde (9*1, (unsigned char *)svuc);
-+ vsc = vec_lde (14*1, (signed char *)svsc);
-+ vus = vec_lde (7*2, (unsigned short *)svus);
-+ vss = vec_lde (1*2, (signed short *)svss);
-+ vui = vec_lde (3*4, (unsigned int *)svui);
-+ vsi = vec_lde (2*4, (signed int *)svsi);
-+ vf = vec_lde (0*4, (float *)svf);
-+
-+ check (vec_extract (vuc, 9) == 9, "vuc");
-+ check (vec_extract (vsc, 14) == 6, "vsc");
-+ check (vec_extract (vus, 7) == 7, "vus");
-+ check (vec_extract (vss, 1) == -3, "vss");
-+ check (vec_extract (vui, 3) == 3, "vui");
-+ check (vec_extract (vsi, 2) == 0, "vsi");
-+ check (vec_extract (vf, 0) == 0.0, "vf");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/pack.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/pack.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/pack.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,108 @@
-+#include "harness.h"
-+
-+#define BIG 4294967295
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
-+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};
-+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed short vssb = {0,1,2,3,4,5,6,7};
-+ vector bool short vbsa = {0,65535,65535,0,0,0,65535,0};
-+ vector bool short vbsb = {65535,0,0,65535,65535,65535,0,65535};
-+ vector unsigned int vuia = {0,1,2,3};
-+ vector unsigned int vuib = {4,5,6,7};
-+ vector signed int vsia = {-4,-3,-2,-1};
-+ vector signed int vsib = {0,1,2,3};
-+ vector bool int vbia = {0,BIG,BIG,BIG};
-+ vector bool int vbib = {BIG,0,0,0};
-+ vector unsigned int vipa = {(0<<24) + (2<<19) + (3<<11) + (4<<3),
-+ (1<<24) + (5<<19) + (6<<11) + (7<<3),
-+ (0<<24) + (8<<19) + (9<<11) + (10<<3),
-+ (1<<24) + (11<<19) + (12<<11) + (13<<3)};
-+ vector unsigned int vipb = {(1<<24) + (14<<19) + (15<<11) + (16<<3),
-+ (0<<24) + (17<<19) + (18<<11) + (19<<3),
-+ (1<<24) + (20<<19) + (21<<11) + (22<<3),
-+ (0<<24) + (23<<19) + (24<<11) + (25<<3)};
-+ vector unsigned short vusc = {0,256,1,257,2,258,3,259};
-+ vector unsigned short vusd = {4,260,5,261,6,262,7,263};
-+ vector signed short vssc = {-1,-128,0,127,-2,-129,1,128};
-+ vector signed short vssd = {-3,-130,2,129,-4,-131,3,130};
-+ vector unsigned int vuic = {0,65536,1,65537};
-+ vector unsigned int vuid = {2,65538,3,65539};
-+ vector signed int vsic = {-1,-32768,0,32767};
-+ vector signed int vsid = {-2,-32769,1,32768};
-+
-+ /* Result vectors. */
-+ vector unsigned char vucr;
-+ vector signed char vscr;
-+ vector bool char vbcr;
-+ vector unsigned short vusr;
-+ vector signed short vssr;
-+ vector bool short vbsr;
-+ vector pixel vpr;
-+ vector unsigned char vucsr;
-+ vector signed char vscsr;
-+ vector unsigned short vussr;
-+ vector signed short vsssr;
-+ vector unsigned char vucsur1, vucsur2;
-+ vector unsigned short vussur1, vussur2;
-+
-+ /* Expected result vectors. */
-+ vector unsigned char vucer = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vscer = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char vbcer = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};
-+ vector unsigned short vuser = {0,1,2,3,4,5,6,7};
-+ vector signed short vsser = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short vbser = {0,65535,65535,65535,65535,0,0,0};
-+ vector pixel vper = {(0<<15) + (2<<10) + (3<<5) + 4,
-+ (1<<15) + (5<<10) + (6<<5) + 7,
-+ (0<<15) + (8<<10) + (9<<5) + 10,
-+ (1<<15) + (11<<10) + (12<<5) + 13,
-+ (1<<15) + (14<<10) + (15<<5) + 16,
-+ (0<<15) + (17<<10) + (18<<5) + 19,
-+ (1<<15) + (20<<10) + (21<<5) + 22,
-+ (0<<15) + (23<<10) + (24<<5) + 25};
-+ vector unsigned char vucser = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};
-+ vector signed char vscser = {-1,-128,0,127,-2,-128,1,127,
-+ -3,-128,2,127,-4,-128,3,127};
-+ vector unsigned short vusser = {0,65535,1,65535,2,65535,3,65535};
-+ vector signed short vssser = {-1,-32768,0,32767,-2,-32768,1,32767};
-+ vector unsigned char vucsuer1 = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};
-+ vector unsigned char vucsuer2 = {0,0,0,127,0,0,1,128,0,0,2,129,0,0,3,130};
-+ vector unsigned short vussuer1 = {0,65535,1,65535,2,65535,3,65535};
-+ vector unsigned short vussuer2 = {0,0,0,32767,0,0,1,32768};
-+
-+ vucr = vec_pack (vusa, vusb);
-+ vscr = vec_pack (vssa, vssb);
-+ vbcr = vec_pack (vbsa, vbsb);
-+ vusr = vec_pack (vuia, vuib);
-+ vssr = vec_pack (vsia, vsib);
-+ vbsr = vec_pack (vbia, vbib);
-+ vpr = vec_packpx (vipa, vipb);
-+ vucsr = vec_packs (vusc, vusd);
-+ vscsr = vec_packs (vssc, vssd);
-+ vussr = vec_packs (vuic, vuid);
-+ vsssr = vec_packs (vsic, vsid);
-+ vucsur1 = vec_packsu (vusc, vusd);
-+ vucsur2 = vec_packsu (vssc, vssd);
-+ vussur1 = vec_packsu (vuic, vuid);
-+ vussur2 = vec_packsu (vsic, vsid);
-+
-+ check (vec_all_eq (vucr, vucer), "vucr");
-+ check (vec_all_eq (vscr, vscer), "vscr");
-+ check (vec_all_eq (vbcr, vbcer), "vbcr");
-+ check (vec_all_eq (vusr, vuser), "vusr");
-+ check (vec_all_eq (vssr, vsser), "vssr");
-+ check (vec_all_eq (vbsr, vbser), "vbsr");
-+ check (vec_all_eq (vpr, vper ), "vpr" );
-+ check (vec_all_eq (vucsr, vucser), "vucsr");
-+ check (vec_all_eq (vscsr, vscser), "vscsr");
-+ check (vec_all_eq (vussr, vusser), "vussr");
-+ check (vec_all_eq (vsssr, vssser), "vsssr");
-+ check (vec_all_eq (vucsur1, vucsuer1), "vucsur1");
-+ check (vec_all_eq (vucsur2, vucsuer2), "vucsur2");
-+ check (vec_all_eq (vussur1, vussuer1), "vussur1");
-+ check (vec_all_eq (vussur2, vussuer2), "vussur2");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/unpack-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,88 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+#define BIG 4294967295
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char vbc = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};
-+ vector pixel vp = {(0<<15) + (1<<10) + (2<<5) + 3,
-+ (1<<15) + (4<<10) + (5<<5) + 6,
-+ (0<<15) + (7<<10) + (8<<5) + 9,
-+ (1<<15) + (10<<10) + (11<<5) + 12,
-+ (1<<15) + (13<<10) + (14<<5) + 15,
-+ (0<<15) + (16<<10) + (17<<5) + 18,
-+ (1<<15) + (19<<10) + (20<<5) + 21,
-+ (0<<15) + (22<<10) + (23<<5) + 24};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short vbs = {0,65535,65535,0,0,0,65535,0};
-+
-+ /* Result vectors. */
-+ vector signed short vsch, vscl;
-+ vector bool short vbsh, vbsl;
-+ vector unsigned int vuih, vuil;
-+ vector signed int vsih, vsil;
-+ vector bool int vbih, vbil;
-+
-+ /* Expected result vectors. */
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector signed short vschr = {0,1,2,3,4,5,6,7};
-+ vector signed short vsclr = {-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector bool short vbshr = {65535,0,0,65535,65535,65535,0,65535};
-+ vector bool short vbslr = {0,65535,65535,0,0,0,65535,0};
-+ vector unsigned int vuihr = {(65535<<24) + (13<<16) + (14<<8) + 15,
-+ (0<<24) + (16<<16) + (17<<8) + 18,
-+ (65535<<24) + (19<<16) + (20<<8) + 21,
-+ (0<<24) + (22<<16) + (23<<8) + 24};
-+ vector unsigned int vuilr = {(0<<24) + (1<<16) + (2<<8) + 3,
-+ (65535<<24) + (4<<16) + (5<<8) + 6,
-+ (0<<24) + (7<<16) + (8<<8) + 9,
-+ (65535<<24) + (10<<16) + (11<<8) + 12};
-+ vector signed int vsihr = {0,1,2,3};
-+ vector signed int vsilr = {-4,-3,-2,-1};
-+ vector bool int vbihr = {0,0,BIG,0};
-+ vector bool int vbilr = {0,BIG,BIG,0};
-+#else
-+ vector signed short vschr = {-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed short vsclr = {0,1,2,3,4,5,6,7};
-+ vector bool short vbshr = {0,65535,65535,0,0,0,65535,0};
-+ vector bool short vbslr = {65535,0,0,65535,65535,65535,0,65535};
-+ vector unsigned int vuihr = {(0<<24) + (1<<16) + (2<<8) + 3,
-+ (65535<<24) + (4<<16) + (5<<8) + 6,
-+ (0<<24) + (7<<16) + (8<<8) + 9,
-+ (65535<<24) + (10<<16) + (11<<8) + 12};
-+ vector unsigned int vuilr = {(65535<<24) + (13<<16) + (14<<8) + 15,
-+ (0<<24) + (16<<16) + (17<<8) + 18,
-+ (65535<<24) + (19<<16) + (20<<8) + 21,
-+ (0<<24) + (22<<16) + (23<<8) + 24};
-+ vector signed int vsihr = {-4,-3,-2,-1};
-+ vector signed int vsilr = {0,1,2,3};
-+ vector bool int vbihr = {0,BIG,BIG,0};
-+ vector bool int vbilr = {0,0,BIG,0};
-+#endif
-+
-+ vsch = vec_unpackh (vsc);
-+ vscl = vec_unpackl (vsc);
-+ vbsh = vec_unpackh (vbc);
-+ vbsl = vec_unpackl (vbc);
-+ vuih = vec_unpackh (vp);
-+ vuil = vec_unpackl (vp);
-+ vsih = vec_unpackh (vss);
-+ vsil = vec_unpackl (vss);
-+ vbih = vec_unpackh (vbs);
-+ vbil = vec_unpackl (vbs);
-+
-+ check (vec_all_eq (vsch, vschr), "vsch");
-+ check (vec_all_eq (vscl, vsclr), "vscl");
-+ check (vec_all_eq (vbsh, vbshr), "vbsh");
-+ check (vec_all_eq (vbsl, vbslr), "vbsl");
-+ check (vec_all_eq (vuih, vuihr), "vuih");
-+ check (vec_all_eq (vuil, vuilr), "vuil");
-+ check (vec_all_eq (vsih, vsihr), "vsih");
-+ check (vec_all_eq (vsil, vsilr), "vsil");
-+ check (vec_all_eq (vbih, vbihr), "vbih");
-+ check (vec_all_eq (vbil, vbilr), "vbil");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/st.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/st.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/st.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,67 @@
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned char svbc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned short svbs[8] __attribute__ ((aligned (16)));
-+static unsigned short svp[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static unsigned int svbi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 16; ++i)
-+ {
-+ check (svuc[i] == i, "svuc");
-+ check (svsc[i] == i - 8, "svsc");
-+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");
-+ }
-+ for (i = 0; i < 8; ++i)
-+ {
-+ check (svus[i] == i, "svus");
-+ check (svss[i] == i - 4, "svss");
-+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");
-+ check (svp[i] == i, "svp");
-+ }
-+ for (i = 0; i < 4; ++i)
-+ {
-+ check (svui[i] == i, "svui");
-+ check (svsi[i] == i - 2, "svsi");
-+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");
-+ check (svf[i] == i * 1.0f, "svf");
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
-+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};
-+ vector pixel vp = {0,1,2,3,4,5,6,7};
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};
-+ vector float vf = {0.0,1.0,2.0,3.0};
-+
-+ vec_st (vuc, 0, (vector unsigned char *)svuc);
-+ vec_st (vsc, 0, (vector signed char *)svsc);
-+ vec_st (vbc, 0, (vector bool char *)svbc);
-+ vec_st (vus, 0, (vector unsigned short *)svus);
-+ vec_st (vss, 0, (vector signed short *)svss);
-+ vec_st (vbs, 0, (vector bool short *)svbs);
-+ vec_st (vp, 0, (vector pixel *)svp);
-+ vec_st (vui, 0, (vector unsigned int *)svui);
-+ vec_st (vsi, 0, (vector signed int *)svsi);
-+ vec_st (vbi, 0, (vector bool int *)svbi);
-+ vec_st (vf, 0, (vector float *)svf);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/vmx/ste-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ste-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ste-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,53 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ check (svuc[9] == 9, "svuc");
-+ check (svsc[14] == 6, "svsc");
-+ check (svus[7] == 7, "svus");
-+ check (svss[1] == -3, "svss");
-+ check (svui[3] == 3, "svui");
-+ check (svsi[2] == 0, "svsi");
-+ check (svf[0] == 0.0, "svf");
-+}
-+
-+static void test ()
-+{
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
-+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
-+ vector unsigned short vus = {7,6,5,4,3,2,1,0};
-+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};
-+ vector unsigned int vui = {3,2,1,0};
-+ vector signed int vsi = {1,0,-1,-2};
-+ vector float vf = {3.0,2.0,1.0,0.0};
-+#else
-+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector float vf = {0.0,1.0,2.0,3.0};
-+#endif
-+
-+ vec_ste (vuc, 9*1, (unsigned char *)svuc);
-+ vec_ste (vsc, 14*1, (signed char *)svsc);
-+ vec_ste (vus, 7*2, (unsigned short *)svus);
-+ vec_ste (vss, 1*2, (signed short *)svss);
-+ vec_ste (vui, 3*4, (unsigned int *)svui);
-+ vec_ste (vsi, 2*4, (signed int *)svsi);
-+ vec_ste (vf, 0*4, (float *)svf);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/vmx/insert.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/insert.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/insert.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector unsigned short vc = {0,1,2,3,4,5,6,7};
-+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};
-+ vector unsigned int ve = {0,1,2,3};
-+ vector signed int vf = {-2,-1,0,1};
-+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};
-+
-+ check (vec_all_eq (vec_insert (16, va, 5),
-+ ((vector unsigned char)
-+ {0,1,2,3,4,16,6,7,8,9,10,11,12,13,14,15})),
-+ "vec_insert (va)");
-+ check (vec_all_eq (vec_insert (-16, vb, 0),
-+ ((vector signed char)
-+ {-16,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7})),
-+ "vec_insert (vb)");
-+ check (vec_all_eq (vec_insert (16, vc, 7),
-+ ((vector unsigned short){0,1,2,3,4,5,6,16})),
-+ "vec_insert (vc)");
-+ check (vec_all_eq (vec_insert (-16, vd, 3),
-+ ((vector signed short){-4,-3,-2,-16,0,1,2,3})),
-+ "vec_insert (vd)");
-+ check (vec_all_eq (vec_insert (16, ve, 2),
-+ ((vector unsigned int){0,1,16,3})),
-+ "vec_insert (ve)");
-+ check (vec_all_eq (vec_insert (-16, vf, 1),
-+ ((vector signed int){-2,-16,0,1})),
-+ "vec_insert (vf)");
-+ check (vec_all_eq (vec_insert (-16.0f, vg, 0),
-+ ((vector float){-16.0f,-1.0f,0.0f,1.0f})),
-+ "vec_insert (vg)");
-+}
-+
-Index: gcc/testsuite/gcc.dg/vmx/ld-vsx.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ld-vsx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-vsx.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,39 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned long long svul[2] __attribute__ ((aligned (16)));
-+static double svd[2] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 2; ++i)
-+ {
-+ svul[i] = i;
-+ svd[i] = i * 1.0;
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned long long evul = {0,1};
-+ vector double evd = {0.0,1.0};
-+
-+ vector unsigned long long vul;
-+ vector double vd;
-+ unsigned i;
-+
-+ init ();
-+
-+ vul = vec_ld (0, (vector unsigned long long *)svul);
-+ vd = vec_ld (0, (vector double *)svd);
-+
-+ for (i = 0; i < 2; ++i)
-+ {
-+ check (vul[i] == evul[i], "vul");
-+ check (vd[i] == evd[i], "vd" );
-+ }
-+}
-Index: gcc/testsuite/gcc.dg/vmx/extract-vsx.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/extract-vsx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-vsx.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector long long vl = {0, 1};
-+ vector double vd = {0.0, 1.0};
-+
-+ check (vec_extract (vl, 0) == 0, "vec_extract, vl, 0");
-+ check (vec_extract (vd, 1) == 1.0, "vec_extract, vd, 1");
-+ check (vl[0] == 0, "[], vl, 0");
-+ check (vd[1] == 1.0, "[], vd, 0");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/perm.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/perm.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/perm.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,69 @@
-+#include "harness.h"
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned char vucb
-+ = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
-+ vector unsigned char vucp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
-+
-+ vector signed char vsca
-+ = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned char vscp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
-+
-+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
-+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};
-+ vector unsigned char vusp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};
-+
-+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
-+ vector signed short vssb = {0,1,2,3,4,5,6,7};
-+ vector unsigned char vssp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};
-+
-+ vector unsigned int vuia = {0,1,2,3};
-+ vector unsigned int vuib = {4,5,6,7};
-+ vector unsigned char vuip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
-+
-+ vector signed int vsia = {-4,-3,-2,-1};
-+ vector signed int vsib = {0,1,2,3};
-+ vector unsigned char vsip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
-+
-+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};
-+ vector float vfb = {0.0,1.0,2.0,3.0};
-+ vector unsigned char vfp = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
-+
-+ /* Result vectors. */
-+ vector unsigned char vuc;
-+ vector signed char vsc;
-+ vector unsigned short vus;
-+ vector signed short vss;
-+ vector unsigned int vui;
-+ vector signed int vsi;
-+ vector float vf;
-+
-+ /* Expected result vectors. */
-+ vector unsigned char vucr = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
-+ vector signed char vscr = {-16,15,-15,14,-14,13,-13,12,-12,11,-11,10,-10,9,-9,8};
-+ vector unsigned short vusr = {0,15,1,14,2,13,3,12};
-+ vector signed short vssr = {-8,7,-7,6,-6,5,-5,4};
-+ vector unsigned int vuir = {0,7,1,6};
-+ vector signed int vsir = {-4,3,-3,2};
-+ vector float vfr = {-4.0,3.0,-3.0,2.0};
-+
-+ vuc = vec_perm (vuca, vucb, vucp);
-+ vsc = vec_perm (vsca, vscb, vscp);
-+ vus = vec_perm (vusa, vusb, vusp);
-+ vss = vec_perm (vssa, vssb, vssp);
-+ vui = vec_perm (vuia, vuib, vuip);
-+ vsi = vec_perm (vsia, vsib, vsip);
-+ vf = vec_perm (vfa, vfb, vfp );
-+
-+ check (vec_all_eq (vuc, vucr), "vuc");
-+ check (vec_all_eq (vsc, vscr), "vsc");
-+ check (vec_all_eq (vus, vusr), "vus");
-+ check (vec_all_eq (vss, vssr), "vss");
-+ check (vec_all_eq (vui, vuir), "vui");
-+ check (vec_all_eq (vsi, vsir), "vsi");
-+ check (vec_all_eq (vf, vfr), "vf" );
-+}
-Index: gcc/testsuite/gcc.dg/vmx/extract-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/extract-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,33 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector unsigned char va = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vb = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector unsigned short vc = {0,1,2,3,4,5,6,7};
-+ vector signed short vd = {-4,-3,-2,-1,0,1,2,3};
-+ vector unsigned int ve = {0,1,2,3};
-+ vector signed int vf = {-2,-1,0,1};
-+ vector float vg = {-2.0f,-1.0f,0.0f,1.0f};
-+
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ check (vec_extract (va, 5) == 10, "vec_extract (va, 5)");
-+ check (vec_extract (vb, 0) == 7, "vec_extract (vb, 0)");
-+ check (vec_extract (vc, 7) == 0, "vec_extract (vc, 7)");
-+ check (vec_extract (vd, 3) == 0, "vec_extract (vd, 3)");
-+ check (vec_extract (ve, 2) == 1, "vec_extract (ve, 2)");
-+ check (vec_extract (vf, 1) == 0, "vec_extract (vf, 1)");
-+ check (vec_extract (vg, 0) == 1.0f, "vec_extract (vg, 0)");
-+#else
-+ check (vec_extract (va, 5) == 5, "vec_extract (va, 5)");
-+ check (vec_extract (vb, 0) == -8, "vec_extract (vb, 0)");
-+ check (vec_extract (vc, 7) == 7, "vec_extract (vc, 7)");
-+ check (vec_extract (vd, 3) == -1, "vec_extract (vd, 3)");
-+ check (vec_extract (ve, 2) == 2, "vec_extract (ve, 2)");
-+ check (vec_extract (vf, 1) == -1, "vec_extract (vf, 1)");
-+ check (vec_extract (vg, 0) == -2.0f, "vec_extract (vg, 0)");
-+#endif
-+}
-+
-Index: gcc/testsuite/gcc.dg/vmx/ldl-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,107 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned char svbc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned short svbs[8] __attribute__ ((aligned (16)));
-+static unsigned short svp[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static unsigned int svbi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 16; ++i)
-+ {
-+ svuc[i] = i;
-+ svsc[i] = i - 8;
-+ svbc[i] = (i % 2) ? 0xff : 0;
-+ }
-+ for (i = 0; i < 8; ++i)
-+ {
-+ svus[i] = i;
-+ svss[i] = i - 4;
-+ svbs[i] = (i % 2) ? 0xffff : 0;
-+ svp[i] = i;
-+ }
-+ for (i = 0; i < 4; ++i)
-+ {
-+ svui[i] = i;
-+ svsi[i] = i - 2;
-+ svbi[i] = (i % 2) ? 0xffffffff : 0;
-+ svf[i] = i * 1.0f;
-+ }
-+}
-+
-+static void test ()
-+{
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned char evuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
-+ vector signed char evsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
-+ vector bool char evbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};
-+ vector unsigned short evus = {7,6,5,4,3,2,1,0};
-+ vector signed short evss = {3,2,1,0,-1,-2,-3,-4};
-+ vector bool short evbs = {65535,0,65535,0,65535,0,65535,0};
-+ vector pixel evp = {7,6,5,4,3,2,1,0};
-+ vector unsigned int evui = {3,2,1,0};
-+ vector signed int evsi = {1,0,-1,-2};
-+ vector bool int evbi = {0xffffffff,0,0xffffffff,0};
-+ vector float evf = {3.0,2.0,1.0,0.0};
-+#else
-+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
-+ vector unsigned short evus = {0,1,2,3,4,5,6,7};
-+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};
-+ vector pixel evp = {0,1,2,3,4,5,6,7};
-+ vector unsigned int evui = {0,1,2,3};
-+ vector signed int evsi = {-2,-1,0,1};
-+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};
-+ vector float evf = {0.0,1.0,2.0,3.0};
-+#endif
-+
-+ vector unsigned char vuc;
-+ vector signed char vsc;
-+ vector bool char vbc;
-+ vector unsigned short vus;
-+ vector signed short vss;
-+ vector bool short vbs;
-+ vector pixel vp;
-+ vector unsigned int vui;
-+ vector signed int vsi;
-+ vector bool int vbi;
-+ vector float vf;
-+
-+ init ();
-+
-+ vuc = vec_ldl (0, (vector unsigned char *)svuc);
-+ vsc = vec_ldl (0, (vector signed char *)svsc);
-+ vbc = vec_ldl (0, (vector bool char *)svbc);
-+ vus = vec_ldl (0, (vector unsigned short *)svus);
-+ vss = vec_ldl (0, (vector signed short *)svss);
-+ vbs = vec_ldl (0, (vector bool short *)svbs);
-+ vp = vec_ldl (0, (vector pixel *)svp);
-+ vui = vec_ldl (0, (vector unsigned int *)svui);
-+ vsi = vec_ldl (0, (vector signed int *)svsi);
-+ vbi = vec_ldl (0, (vector bool int *)svbi);
-+ vf = vec_ldl (0, (vector float *)svf);
-+
-+ check (vec_all_eq (vuc, evuc), "vuc");
-+ check (vec_all_eq (vsc, evsc), "vsc");
-+ check (vec_all_eq (vbc, evbc), "vbc");
-+ check (vec_all_eq (vus, evus), "vus");
-+ check (vec_all_eq (vss, evss), "vss");
-+ check (vec_all_eq (vbs, evbs), "vbs");
-+ check (vec_all_eq (vp, evp ), "vp" );
-+ check (vec_all_eq (vui, evui), "vui");
-+ check (vec_all_eq (vsi, evsi), "vsi");
-+ check (vec_all_eq (vbi, evbi), "vbi");
-+ check (vec_all_eq (vf, evf ), "vf" );
-+}
-Index: gcc/testsuite/gcc.dg/vmx/mult-even-odd.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,43 @@
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};
-+ vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};
-+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
-+ vector unsigned short vusb = {2,3,2,3,2,3,2,3};
-+ vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};
-+ vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};
-+ vector unsigned short vuse, vuso;
-+ vector signed short vsse, vsso;
-+ vector unsigned int vuie, vuio;
-+ vector signed int vsie, vsio;
-+
-+ vuse = vec_mule (vuca, vucb);
-+ vuso = vec_mulo (vuca, vucb);
-+ vsse = vec_mule (vsca, vscb);
-+ vsso = vec_mulo (vsca, vscb);
-+ vuie = vec_mule (vusa, vusb);
-+ vuio = vec_mulo (vusa, vusb);
-+ vsie = vec_mule (vssa, vssb);
-+ vsio = vec_mulo (vssa, vssb);
-+
-+ check (vec_all_eq (vuse,
-+ ((vector unsigned short){0,4,8,12,16,20,24,28})),
-+ "vuse");
-+ check (vec_all_eq (vuso,
-+ ((vector unsigned short){3,9,15,21,27,33,39,45})),
-+ "vuso");
-+ check (vec_all_eq (vsse,
-+ ((vector signed short){-16,-12,-8,-4,0,4,8,12})),
-+ "vsse");
-+ check (vec_all_eq (vsso,
-+ ((vector signed short){21,15,9,3,-3,-9,-15,-21})),
-+ "vsso");
-+ check (vec_all_eq (vuie, ((vector unsigned int){0,4,8,12})), "vuie");
-+ check (vec_all_eq (vuio, ((vector unsigned int){3,9,15,21})), "vuio");
-+ check (vec_all_eq (vsie, ((vector signed int){-8,-4,0,4})), "vsie");
-+ check (vec_all_eq (vsio, ((vector signed int){9,3,-3,-9})), "vsio");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/splat-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/splat-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,59 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector float vf = {-2.0,-1.0,0.0,1.0};
-+
-+ /* Result vectors. */
-+ vector unsigned char vucr;
-+ vector signed char vscr;
-+ vector unsigned short vusr;
-+ vector signed short vssr;
-+ vector unsigned int vuir;
-+ vector signed int vsir;
-+ vector float vfr;
-+
-+ /* Expected result vectors. */
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned char vucer = {14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14};
-+ vector signed char vscer = {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1};
-+ vector unsigned short vuser = {0,0,0,0,0,0,0,0};
-+ vector signed short vsser = {3,3,3,3,3,3,3,3};
-+ vector unsigned int vuier = {1,1,1,1};
-+ vector signed int vsier = {-2,-2,-2,-2};
-+ vector float vfer = {0.0,0.0,0.0,0.0};
-+#else
-+ vector unsigned char vucer = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
-+ vector signed char vscer = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
-+ vector unsigned short vuser = {7,7,7,7,7,7,7,7};
-+ vector signed short vsser = {-4,-4,-4,-4,-4,-4,-4,-4};
-+ vector unsigned int vuier = {2,2,2,2};
-+ vector signed int vsier = {1,1,1,1};
-+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};
-+#endif
-+
-+ vucr = vec_splat (vuc, 1);
-+ vscr = vec_splat (vsc, 8);
-+ vusr = vec_splat (vus, 7);
-+ vssr = vec_splat (vss, 0);
-+ vuir = vec_splat (vui, 2);
-+ vsir = vec_splat (vsi, 3);
-+ vfr = vec_splat (vf, 1);
-+
-+ check (vec_all_eq (vucr, vucer), "vuc");
-+ check (vec_all_eq (vscr, vscer), "vsc");
-+ check (vec_all_eq (vusr, vuser), "vus");
-+ check (vec_all_eq (vssr, vsser), "vss");
-+ check (vec_all_eq (vuir, vuier), "vui");
-+ check (vec_all_eq (vsir, vsier), "vsi");
-+ check (vec_all_eq (vfr, vfer ), "vf");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,19 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector long long vl = {0, 1};
-+ vector double vd = {0.0, 1.0};
-+
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ check (vec_extract (vl, 0) == 1, "vl, 0");
-+ check (vec_extract (vd, 1) == 0.0, "vd, 1");
-+#else
-+ check (vec_extract (vl, 0) == 0, "vl, 0");
-+ check (vec_extract (vd, 1) == 1.0, "vd, 1");
-+#endif
-+}
-Index: gcc/testsuite/gcc.dg/vmx/ld-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ld-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,107 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned char svbc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned short svbs[8] __attribute__ ((aligned (16)));
-+static unsigned short svp[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static unsigned int svbi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 16; ++i)
-+ {
-+ svuc[i] = i;
-+ svsc[i] = i - 8;
-+ svbc[i] = (i % 2) ? 0xff : 0;
-+ }
-+ for (i = 0; i < 8; ++i)
-+ {
-+ svus[i] = i;
-+ svss[i] = i - 4;
-+ svbs[i] = (i % 2) ? 0xffff : 0;
-+ svp[i] = i;
-+ }
-+ for (i = 0; i < 4; ++i)
-+ {
-+ svui[i] = i;
-+ svsi[i] = i - 2;
-+ svbi[i] = (i % 2) ? 0xffffffff : 0;
-+ svf[i] = i * 1.0f;
-+ }
-+}
-+
-+static void test ()
-+{
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector unsigned char evuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
-+ vector signed char evsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
-+ vector bool char evbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};
-+ vector unsigned short evus = {7,6,5,4,3,2,1,0};
-+ vector signed short evss = {3,2,1,0,-1,-2,-3,-4};
-+ vector bool short evbs = {65535,0,65535,0,65535,0,65535,0};
-+ vector pixel evp = {7,6,5,4,3,2,1,0};
-+ vector unsigned int evui = {3,2,1,0};
-+ vector signed int evsi = {1,0,-1,-2};
-+ vector bool int evbi = {0xffffffff,0,0xffffffff,0};
-+ vector float evf = {3.0,2.0,1.0,0.0};
-+#else
-+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
-+ vector unsigned short evus = {0,1,2,3,4,5,6,7};
-+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};
-+ vector pixel evp = {0,1,2,3,4,5,6,7};
-+ vector unsigned int evui = {0,1,2,3};
-+ vector signed int evsi = {-2,-1,0,1};
-+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};
-+ vector float evf = {0.0,1.0,2.0,3.0};
-+#endif
-+
-+ vector unsigned char vuc;
-+ vector signed char vsc;
-+ vector bool char vbc;
-+ vector unsigned short vus;
-+ vector signed short vss;
-+ vector bool short vbs;
-+ vector pixel vp;
-+ vector unsigned int vui;
-+ vector signed int vsi;
-+ vector bool int vbi;
-+ vector float vf;
-+
-+ init ();
-+
-+ vuc = vec_ld (0, (vector unsigned char *)svuc);
-+ vsc = vec_ld (0, (vector signed char *)svsc);
-+ vbc = vec_ld (0, (vector bool char *)svbc);
-+ vus = vec_ld (0, (vector unsigned short *)svus);
-+ vss = vec_ld (0, (vector signed short *)svss);
-+ vbs = vec_ld (0, (vector bool short *)svbs);
-+ vp = vec_ld (0, (vector pixel *)svp);
-+ vui = vec_ld (0, (vector unsigned int *)svui);
-+ vsi = vec_ld (0, (vector signed int *)svsi);
-+ vbi = vec_ld (0, (vector bool int *)svbi);
-+ vf = vec_ld (0, (vector float *)svf);
-+
-+ check (vec_all_eq (vuc, evuc), "vuc");
-+ check (vec_all_eq (vsc, evsc), "vsc");
-+ check (vec_all_eq (vbc, evbc), "vbc");
-+ check (vec_all_eq (vus, evus), "vus");
-+ check (vec_all_eq (vss, evss), "vss");
-+ check (vec_all_eq (vbs, evbs), "vbs");
-+ check (vec_all_eq (vp, evp ), "vp" );
-+ check (vec_all_eq (vui, evui), "vui");
-+ check (vec_all_eq (vsi, evsi), "vsi");
-+ check (vec_all_eq (vbi, evbi), "vbi");
-+ check (vec_all_eq (vf, evf ), "vf" );
-+}
-Index: gcc/testsuite/gcc.dg/vmx/ld.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ld.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ld.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,91 @@
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned char svbc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned short svbs[8] __attribute__ ((aligned (16)));
-+static unsigned short svp[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static unsigned int svbi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 16; ++i)
-+ {
-+ svuc[i] = i;
-+ svsc[i] = i - 8;
-+ svbc[i] = (i % 2) ? 0xff : 0;
-+ }
-+ for (i = 0; i < 8; ++i)
-+ {
-+ svus[i] = i;
-+ svss[i] = i - 4;
-+ svbs[i] = (i % 2) ? 0xffff : 0;
-+ svp[i] = i;
-+ }
-+ for (i = 0; i < 4; ++i)
-+ {
-+ svui[i] = i;
-+ svsi[i] = i - 2;
-+ svbi[i] = (i % 2) ? 0xffffffff : 0;
-+ svf[i] = i * 1.0f;
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
-+ vector unsigned short evus = {0,1,2,3,4,5,6,7};
-+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};
-+ vector pixel evp = {0,1,2,3,4,5,6,7};
-+ vector unsigned int evui = {0,1,2,3};
-+ vector signed int evsi = {-2,-1,0,1};
-+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};
-+ vector float evf = {0.0,1.0,2.0,3.0};
-+
-+ vector unsigned char vuc;
-+ vector signed char vsc;
-+ vector bool char vbc;
-+ vector unsigned short vus;
-+ vector signed short vss;
-+ vector bool short vbs;
-+ vector pixel vp;
-+ vector unsigned int vui;
-+ vector signed int vsi;
-+ vector bool int vbi;
-+ vector float vf;
-+
-+ init ();
-+
-+ vuc = vec_ld (0, (vector unsigned char *)svuc);
-+ vsc = vec_ld (0, (vector signed char *)svsc);
-+ vbc = vec_ld (0, (vector bool char *)svbc);
-+ vus = vec_ld (0, (vector unsigned short *)svus);
-+ vss = vec_ld (0, (vector signed short *)svss);
-+ vbs = vec_ld (0, (vector bool short *)svbs);
-+ vp = vec_ld (0, (vector pixel *)svp);
-+ vui = vec_ld (0, (vector unsigned int *)svui);
-+ vsi = vec_ld (0, (vector signed int *)svsi);
-+ vbi = vec_ld (0, (vector bool int *)svbi);
-+ vf = vec_ld (0, (vector float *)svf);
-+
-+ check (vec_all_eq (vuc, evuc), "vuc");
-+ check (vec_all_eq (vsc, evsc), "vsc");
-+ check (vec_all_eq (vbc, evbc), "vbc");
-+ check (vec_all_eq (vus, evus), "vus");
-+ check (vec_all_eq (vss, evss), "vss");
-+ check (vec_all_eq (vbs, evbs), "vbs");
-+ check (vec_all_eq (vp, evp ), "vp" );
-+ check (vec_all_eq (vui, evui), "vui");
-+ check (vec_all_eq (vsi, evsi), "vsi");
-+ check (vec_all_eq (vbi, evbi), "vbi");
-+ check (vec_all_eq (vf, evf ), "vf" );
-+}
-Index: gcc/testsuite/gcc.dg/vmx/sn7153.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/sn7153.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/sn7153.c (.../branches/gcc-4_8-branch)
-@@ -34,7 +34,11 @@
-
- void validate_sat()
- {
-+#ifdef __LITTLE_ENDIAN__
-+ if (vec_any_ne(vec_splat(vec_mfvscr(), 0), ((vector unsigned short){1,1,1,1,1,1,1,1})))
-+#else
- if (vec_any_ne(vec_splat(vec_mfvscr(), 7), ((vector unsigned short){1,1,1,1,1,1,1,1})))
-+#endif
- {
- union {vector unsigned short v; unsigned short s[8];} u;
- u.v = vec_mfvscr();
-Index: gcc/testsuite/gcc.dg/vmx/stl.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/stl.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/stl.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,67 @@
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned char svbc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned short svbs[8] __attribute__ ((aligned (16)));
-+static unsigned short svp[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static unsigned int svbi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 16; ++i)
-+ {
-+ check (svuc[i] == i, "svuc");
-+ check (svsc[i] == i - 8, "svsc");
-+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");
-+ }
-+ for (i = 0; i < 8; ++i)
-+ {
-+ check (svus[i] == i, "svus");
-+ check (svss[i] == i - 4, "svss");
-+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");
-+ check (svp[i] == i, "svp");
-+ }
-+ for (i = 0; i < 4; ++i)
-+ {
-+ check (svui[i] == i, "svui");
-+ check (svsi[i] == i - 2, "svsi");
-+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");
-+ check (svf[i] == i * 1.0f, "svf");
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
-+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};
-+ vector pixel vp = {0,1,2,3,4,5,6,7};
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};
-+ vector float vf = {0.0,1.0,2.0,3.0};
-+
-+ vec_stl (vuc, 0, (vector unsigned char *)svuc);
-+ vec_stl (vsc, 0, (vector signed char *)svsc);
-+ vec_stl (vbc, 0, (vector bool char *)svbc);
-+ vec_stl (vus, 0, (vector unsigned short *)svus);
-+ vec_stl (vss, 0, (vector signed short *)svss);
-+ vec_stl (vbs, 0, (vector bool short *)svbs);
-+ vec_stl (vp, 0, (vector pixel *)svp);
-+ vec_stl (vui, 0, (vector unsigned int *)svui);
-+ vec_stl (vsi, 0, (vector signed int *)svsi);
-+ vec_stl (vbi, 0, (vector bool int *)svbi);
-+ vec_stl (vf, 0, (vector float *)svf);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/vmx/st-vsx.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/st-vsx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/st-vsx.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned long long svul[2] __attribute__ ((aligned (16)));
-+static double svd[2] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 2; ++i)
-+ {
-+ check (svul[i] == i, "svul");
-+ check (svd[i] == i * 1.0, "svd");
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned long long vul = {0,1};
-+ vector double vd = {0.0,1.0};
-+
-+ vec_st (vul, 0, (vector unsigned long long *)svul);
-+ vec_st (vd, 0, (vector double *)svd);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/vmx/sum2s.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/sum2s.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/sum2s.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector signed int vsia = {-10,1,2,3};
-+ vector signed int vsib = {100,101,102,-103};
-+ vector signed int vsir;
-+ vector signed int vsier = {0,92,0,-98};
-+
-+ vsir = vec_sum2s (vsia, vsib);
-+
-+ check (vec_all_eq (vsir, vsier), "vsir");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,84 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static int vec_long_long_eq (vector long long x, vector long long y)
-+{
-+ return (x[0] == y[0] && x[1] == y[1]);
-+}
-+
-+static int vec_double_eq (vector double x, vector double y)
-+{
-+ return (x[0] == y[0] && x[1] == y[1]);
-+}
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector long long vla = {-2,-1};
-+ vector long long vlb = {0,1};
-+ vector double vda = {-2.0,-1.0};
-+ vector double vdb = {0.0,1.0};
-+ vector unsigned int vuia = {0,1,2,3};
-+ vector unsigned int vuib = {4,5,6,7};
-+ vector signed int vsia = {-4,-3,-2,-1};
-+ vector signed int vsib = {0,1,2,3};
-+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};
-+ vector float vfb = {0.0,1.0,2.0,3.0};
-+
-+ /* Result vectors. */
-+ vector long long vlh, vll;
-+ vector double vdh, vdl;
-+ vector unsigned int vuih, vuil;
-+ vector signed int vsih, vsil;
-+ vector float vfh, vfl;
-+
-+ /* Expected result vectors. */
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector long long vlrh = {1,-1};
-+ vector long long vlrl = {0,-2};
-+ vector double vdrh = {1.0,-1.0};
-+ vector double vdrl = {0.0,-2.0};
-+ vector unsigned int vuirh = {6,2,7,3};
-+ vector unsigned int vuirl = {4,0,5,1};
-+ vector signed int vsirh = {2,-2,3,-1};
-+ vector signed int vsirl = {0,-4,1,-3};
-+ vector float vfrh = {2.0,-2.0,3.0,-1.0};
-+ vector float vfrl = {0.0,-4.0,1.0,-3.0};
-+#else
-+ vector long long vlrh = {-2,0};
-+ vector long long vlrl = {-1,1};
-+ vector double vdrh = {-2.0,0.0};
-+ vector double vdrl = {-1.0,1.0};
-+ vector unsigned int vuirh = {0,4,1,5};
-+ vector unsigned int vuirl = {2,6,3,7};
-+ vector signed int vsirh = {-4,0,-3,1};
-+ vector signed int vsirl = {-2,2,-1,3};
-+ vector float vfrh = {-4.0,0.0,-3.0,1.0};
-+ vector float vfrl = {-2.0,2.0,-1.0,3.0};
-+#endif
-+
-+ vlh = vec_mergeh (vla, vlb);
-+ vll = vec_mergel (vla, vlb);
-+ vdh = vec_mergeh (vda, vdb);
-+ vdl = vec_mergel (vda, vdb);
-+ vuih = vec_mergeh (vuia, vuib);
-+ vuil = vec_mergel (vuia, vuib);
-+ vsih = vec_mergeh (vsia, vsib);
-+ vsil = vec_mergel (vsia, vsib);
-+ vfh = vec_mergeh (vfa, vfb );
-+ vfl = vec_mergel (vfa, vfb );
-+
-+ check (vec_long_long_eq (vlh, vlrh), "vlh");
-+ check (vec_long_long_eq (vll, vlrl), "vll");
-+ check (vec_double_eq (vdh, vdrh), "vdh" );
-+ check (vec_double_eq (vdl, vdrl), "vdl" );
-+ check (vec_all_eq (vuih, vuirh), "vuih");
-+ check (vec_all_eq (vuil, vuirl), "vuil");
-+ check (vec_all_eq (vsih, vsirh), "vsih");
-+ check (vec_all_eq (vsil, vsirl), "vsil");
-+ check (vec_all_eq (vfh, vfrh), "vfh");
-+ check (vec_all_eq (vfl, vfrl), "vfl");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,64 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};
-+ vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};
-+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
-+ vector unsigned short vusb = {2,3,2,3,2,3,2,3};
-+ vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};
-+ vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};
-+ vector unsigned short vuse, vuso;
-+ vector signed short vsse, vsso;
-+ vector unsigned int vuie, vuio;
-+ vector signed int vsie, vsio;
-+
-+ vuse = vec_mule (vuca, vucb);
-+ vuso = vec_mulo (vuca, vucb);
-+ vsse = vec_mule (vsca, vscb);
-+ vsso = vec_mulo (vsca, vscb);
-+ vuie = vec_mule (vusa, vusb);
-+ vuio = vec_mulo (vusa, vusb);
-+ vsie = vec_mule (vssa, vssb);
-+ vsio = vec_mulo (vssa, vssb);
-+
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ check (vec_all_eq (vuse,
-+ ((vector unsigned short){3,9,15,21,27,33,39,45})),
-+ "vuse");
-+ check (vec_all_eq (vuso,
-+ ((vector unsigned short){0,4,8,12,16,20,24,28})),
-+ "vuso");
-+ check (vec_all_eq (vsse,
-+ ((vector signed short){21,15,9,3,-3,-9,-15,-21})),
-+ "vsse");
-+ check (vec_all_eq (vsso,
-+ ((vector signed short){-16,-12,-8,-4,0,4,8,12})),
-+ "vsso");
-+ check (vec_all_eq (vuie, ((vector unsigned int){3,9,15,21})), "vuie");
-+ check (vec_all_eq (vuio, ((vector unsigned int){0,4,8,12})), "vuio");
-+ check (vec_all_eq (vsie, ((vector signed int){9,3,-3,-9})), "vsie");
-+ check (vec_all_eq (vsio, ((vector signed int){-8,-4,0,4})), "vsio");
-+#else
-+ check (vec_all_eq (vuse,
-+ ((vector unsigned short){0,4,8,12,16,20,24,28})),
-+ "vuse");
-+ check (vec_all_eq (vuso,
-+ ((vector unsigned short){3,9,15,21,27,33,39,45})),
-+ "vuso");
-+ check (vec_all_eq (vsse,
-+ ((vector signed short){-16,-12,-8,-4,0,4,8,12})),
-+ "vsse");
-+ check (vec_all_eq (vsso,
-+ ((vector signed short){21,15,9,3,-3,-9,-15,-21})),
-+ "vsso");
-+ check (vec_all_eq (vuie, ((vector unsigned int){0,4,8,12})), "vuie");
-+ check (vec_all_eq (vuio, ((vector unsigned int){3,9,15,21})), "vuio");
-+ check (vec_all_eq (vsie, ((vector signed int){-8,-4,0,4})), "vsie");
-+ check (vec_all_eq (vsio, ((vector signed int){9,3,-3,-9})), "vsio");
-+#endif
-+}
-Index: gcc/testsuite/gcc.dg/vmx/insert-vsx.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/insert-vsx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-vsx.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,28 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static int vec_long_long_eq (vector long long x, vector long long y)
-+{
-+ return (x[0] == y[0] && x[1] == y[1]);
-+}
-+
-+static int vec_dbl_eq (vector double x, vector double y)
-+{
-+ return (x[0] == y[0] && x[1] == y[1]);
-+}
-+
-+static void test()
-+{
-+ vector long long vl = {0, 1};
-+ vector double vd = {0.0, 1.0};
-+ vector long long vlr = vec_insert (2, vl, 0);
-+ vector double vdr = vec_insert (2.0, vd, 1);
-+ vector long long vler = {2, 1};
-+ vector double vder = {0.0, 2.0};
-+
-+ check (vec_long_long_eq (vlr, vler), "vl");
-+ check (vec_dbl_eq (vdr, vder), "vd");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/vsums-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector signed int va = {-7,11,-13,17};
-+
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector signed int vb = {128,0,0,0};
-+ vector signed int evd = {136,0,0,0};
-+#else
-+ vector signed int vb = {0,0,0,128};
-+ vector signed int evd = {0,0,0,136};
-+#endif
-+
-+ vector signed int vd = vec_sums (va, vb);
-+
-+ check (vec_all_eq (vd, evd), "sums");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/ldl-vsx.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,39 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned long long svul[2] __attribute__ ((aligned (16)));
-+static double svd[2] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 2; ++i)
-+ {
-+ svul[i] = i;
-+ svd[i] = i * 1.0;
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned long long evul = {0,1};
-+ vector double evd = {0.0,1.0};
-+
-+ vector unsigned long long vul;
-+ vector double vd;
-+ unsigned i;
-+
-+ init ();
-+
-+ vul = vec_ldl (0, (vector unsigned long long *)svul);
-+ vd = vec_ldl (0, (vector double *)svd);
-+
-+ for (i = 0; i < 2; ++i)
-+ {
-+ check (vul[i] == evul[i], "vul");
-+ check (vd[i] == evd[i], "vd" );
-+ }
-+}
-Index: gcc/testsuite/gcc.dg/vmx/ste.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/ste.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/ste.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,41 @@
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ check (svuc[9] == 9, "svuc");
-+ check (svsc[14] == 6, "svsc");
-+ check (svus[7] == 7, "svus");
-+ check (svss[1] == -3, "svss");
-+ check (svui[3] == 3, "svui");
-+ check (svsi[2] == 0, "svsi");
-+ check (svf[0] == 0.0, "svf");
-+}
-+
-+static void test ()
-+{
-+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
-+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector float vf = {0.0,1.0,2.0,3.0};
-+
-+ vec_ste (vuc, 9*1, (unsigned char *)svuc);
-+ vec_ste (vsc, 14*1, (signed char *)svsc);
-+ vec_ste (vus, 7*2, (unsigned short *)svus);
-+ vec_ste (vss, 1*2, (signed short *)svss);
-+ vec_ste (vui, 3*4, (unsigned int *)svui);
-+ vec_ste (vsi, 2*4, (signed int *)svsi);
-+ vec_ste (vf, 0*4, (float *)svf);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/vmx/lde-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/lde-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/lde-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,73 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned char svuc[16] __attribute__ ((aligned (16)));
-+static signed char svsc[16] __attribute__ ((aligned (16)));
-+static unsigned short svus[8] __attribute__ ((aligned (16)));
-+static signed short svss[8] __attribute__ ((aligned (16)));
-+static unsigned int svui[4] __attribute__ ((aligned (16)));
-+static signed int svsi[4] __attribute__ ((aligned (16)));
-+static float svf[4] __attribute__ ((aligned (16)));
-+
-+static void init ()
-+{
-+ int i;
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ for (i = 15; i >= 0; --i)
-+#else
-+ for (i = 0; i < 16; ++i)
-+#endif
-+ {
-+ svuc[i] = i;
-+ svsc[i] = i - 8;
-+ }
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ for (i = 7; i >= 0; --i)
-+#else
-+ for (i = 0; i < 8; ++i)
-+#endif
-+ {
-+ svus[i] = i;
-+ svss[i] = i - 4;
-+ }
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ for (i = 3; i >= 0; --i)
-+#else
-+ for (i = 0; i < 4; ++i)
-+#endif
-+ {
-+ svui[i] = i;
-+ svsi[i] = i - 2;
-+ svf[i] = i * 1.0f;
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned char vuc;
-+ vector signed char vsc;
-+ vector unsigned short vus;
-+ vector signed short vss;
-+ vector unsigned int vui;
-+ vector signed int vsi;
-+ vector float vf;
-+
-+ init ();
-+
-+ vuc = vec_lde (9*1, (unsigned char *)svuc);
-+ vsc = vec_lde (14*1, (signed char *)svsc);
-+ vus = vec_lde (7*2, (unsigned short *)svus);
-+ vss = vec_lde (1*2, (signed short *)svss);
-+ vui = vec_lde (3*4, (unsigned int *)svui);
-+ vsi = vec_lde (2*4, (signed int *)svsi);
-+ vf = vec_lde (0*4, (float *)svf);
-+
-+ check (vec_extract (vuc, 9) == 9, "vuc");
-+ check (vec_extract (vsc, 14) == 6, "vsc");
-+ check (vec_extract (vus, 7) == 7, "vus");
-+ check (vec_extract (vss, 1) == -3, "vss");
-+ check (vec_extract (vui, 3) == 3, "vui");
-+ check (vec_extract (vsi, 2) == 0, "vsi");
-+ check (vec_extract (vf, 0) == 0.0, "vf");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/splat-vsx.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/splat-vsx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-vsx.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,31 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector unsigned int vui = {0,1,2,3};
-+ vector signed int vsi = {-2,-1,0,1};
-+ vector float vf = {-2.0,-1.0,0.0,1.0};
-+
-+ /* Result vectors. */
-+ vector unsigned int vuir;
-+ vector signed int vsir;
-+ vector float vfr;
-+
-+ /* Expected result vectors. */
-+ vector unsigned int vuier = {2,2,2,2};
-+ vector signed int vsier = {1,1,1,1};
-+ vector float vfer = {-1.0,-1.0,-1.0,-1.0};
-+
-+ vuir = vec_splat (vui, 2);
-+ vsir = vec_splat (vsi, 3);
-+ vfr = vec_splat (vf, 1);
-+
-+ check (vec_all_eq (vuir, vuier), "vui");
-+ check (vec_all_eq (vsir, vsier), "vsi");
-+ check (vec_all_eq (vfr, vfer ), "vf");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,19 @@
-+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
-+
-+#include "harness.h"
-+
-+static void test()
-+{
-+ vector signed int vsia = {-10,1,2,3};
-+ vector signed int vsib = {100,101,102,-103};
-+ vector signed int vsir;
-+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-+ vector signed int vsier = {91,0,107,0};
-+#else
-+ vector signed int vsier = {0,92,0,-98};
-+#endif
-+
-+ vsir = vec_sum2s (vsia, vsib);
-+
-+ check (vec_all_eq (vsir, vsier), "vsir");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/merge-vsx.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/merge-vsx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-vsx.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,71 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static int vec_long_long_eq (vector long long x, vector long long y)
-+{
-+ return (x[0] == y[0] && x[1] == y[1]);
-+}
-+
-+static int vec_double_eq (vector double x, vector double y)
-+{
-+ return (x[0] == y[0] && x[1] == y[1]);
-+}
-+
-+static void test()
-+{
-+ /* Input vectors. */
-+ vector long long vla = {-2,-1};
-+ vector long long vlb = {0,1};
-+ vector double vda = {-2.0,-1.0};
-+ vector double vdb = {0.0,1.0};
-+ vector unsigned int vuia = {0,1,2,3};
-+ vector unsigned int vuib = {4,5,6,7};
-+ vector signed int vsia = {-4,-3,-2,-1};
-+ vector signed int vsib = {0,1,2,3};
-+ vector float vfa = {-4.0,-3.0,-2.0,-1.0};
-+ vector float vfb = {0.0,1.0,2.0,3.0};
-+
-+ /* Result vectors. */
-+ vector long long vlh, vll;
-+ vector double vdh, vdl;
-+ vector unsigned int vuih, vuil;
-+ vector signed int vsih, vsil;
-+ vector float vfh, vfl;
-+
-+ /* Expected result vectors. */
-+ vector long long vlrh = {-2,0};
-+ vector long long vlrl = {-1,1};
-+ vector double vdrh = {-2.0,0.0};
-+ vector double vdrl = {-1.0,1.0};
-+ vector unsigned int vuirh = {0,4,1,5};
-+ vector unsigned int vuirl = {2,6,3,7};
-+ vector signed int vsirh = {-4,0,-3,1};
-+ vector signed int vsirl = {-2,2,-1,3};
-+ vector float vfrh = {-4.0,0.0,-3.0,1.0};
-+ vector float vfrl = {-2.0,2.0,-1.0,3.0};
-+
-+ vlh = vec_mergeh (vla, vlb);
-+ vll = vec_mergel (vla, vlb);
-+ vdh = vec_mergeh (vda, vdb);
-+ vdl = vec_mergel (vda, vdb);
-+ vuih = vec_mergeh (vuia, vuib);
-+ vuil = vec_mergel (vuia, vuib);
-+ vsih = vec_mergeh (vsia, vsib);
-+ vsil = vec_mergel (vsia, vsib);
-+ vfh = vec_mergeh (vfa, vfb );
-+ vfl = vec_mergel (vfa, vfb );
-+
-+ check (vec_long_long_eq (vlh, vlrh), "vlh");
-+ check (vec_long_long_eq (vll, vlrl), "vll");
-+ check (vec_double_eq (vdh, vdrh), "vdh" );
-+ check (vec_double_eq (vdl, vdrl), "vdl" );
-+ check (vec_all_eq (vuih, vuirh), "vuih");
-+ check (vec_all_eq (vuil, vuirl), "vuil");
-+ check (vec_all_eq (vsih, vsirh), "vsih");
-+ check (vec_all_eq (vsil, vsirl), "vsil");
-+ check (vec_all_eq (vfh, vfrh), "vfh");
-+ check (vec_all_eq (vfl, vfrl), "vfl");
-+}
-Index: gcc/testsuite/gcc.dg/vmx/stl-vsx.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vmx/stl-vsx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-vsx.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-+/* { dg-require-effective-target powerpc_vsx_ok } */
-+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
-+
-+#include "harness.h"
-+
-+static unsigned long long svul[2] __attribute__ ((aligned (16)));
-+static double svd[2] __attribute__ ((aligned (16)));
-+
-+static void check_arrays ()
-+{
-+ unsigned int i;
-+ for (i = 0; i < 2; ++i)
-+ {
-+ check (svul[i] == i, "svul");
-+ check (svd[i] == i * 1.0, "svd");
-+ }
-+}
-+
-+static void test ()
-+{
-+ vector unsigned long long vul = {0,1};
-+ vector double vd = {0.0,1.0};
-+
-+ vec_stl (vul, 0, (vector unsigned long long *)svul);
-+ vec_stl (vd, 0, (vector double *)svd);
-+
-+ check_arrays ();
-+}
-Index: gcc/testsuite/gcc.dg/strlenopt-4gf.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/strlenopt-4gf.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/strlenopt-4gf.c (.../branches/gcc-4_8-branch)
-@@ -7,13 +7,13 @@
- #include "strlenopt-4.c"
-
- /* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 4 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 1 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 5 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "stpcpy \\(" 5 "strlen" } } */
- /* { dg-final { cleanup-tree-dump "strlen" } } */
-Index: gcc/testsuite/gcc.dg/pr59351.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr59351.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr59351.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,8 @@
-+/* { dg-do compile } */
-+/* { dg-options "-std=c99 -Wpedantic" } */
-+
-+unsigned int
-+foo (void)
-+{
-+ return sizeof ((int[]) {}); /* { dg-warning "ISO C forbids empty initializer braces" } */
-+}
-Index: gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,7 @@
-+/* Test to make sure the macro info includes the predefined macros with line number 0. */
-+/* { dg-do compile } */
-+/* { dg-options "-g3 -gdwarf-2 -dA -fverbose-asm" } */
-+/* { dg-final { scan-assembler "At line number 0" } } */
-+
-+#define FOO 1
-+int i;
-Index: gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,7 @@
- /* { dg-do compile } */
- /* { dg-options "-O2 -Wall" } */
- /* { dg-options "-O2 -Wall -mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */
-+/* { dg-options "-O2 -Wall -msse2" { target { i?86-*-* x86_64-*-* } } } */
-
- typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-Index: gcc/testsuite/gcc.dg/builtin-object-size-8.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/builtin-object-size-8.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/builtin-object-size-8.c (.../branches/gcc-4_8-branch)
-@@ -1,4 +1,4 @@
--/* { dg-do run { xfail *-*-* } } */
-+/* { dg-do run } */
- /* { dg-options "-O2" } */
-
- typedef __SIZE_TYPE__ size_t;
-Index: gcc/testsuite/gcc.dg/20050922-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/20050922-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/20050922-2.c (.../branches/gcc-4_8-branch)
-@@ -4,7 +4,8 @@
- /* { dg-do run } */
- /* { dg-options "-O1 -std=c99" } */
-
--#include <stdlib.h>
-+extern void abort (void);
-+extern void exit (int);
-
- #if __INT_MAX__ == 2147483647
- typedef unsigned int uint32_t;
-Index: gcc/testsuite/gcc.dg/graphite/pr55022.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/graphite/pr55022.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/graphite/pr55022.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,27 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fgraphite-identity" } */
-+
-+extern void abort (void);
-+
-+void __attribute__((noinline,noclone))
-+f(int *limit, int minLen, int maxLen)
-+{
-+ int i;
-+
-+ for (i = minLen; i <= maxLen; i++) {
-+ limit[i] = i;
-+ }
-+}
-+
-+int main()
-+{
-+ int limit[256], i;
-+ f (limit, 0, 255);
-+ for (i = 0; i < 256; ++i)
-+ {
-+ if (limit[i] != i)
-+ abort ();
-+ __asm__ volatile ("" : : : "memory");
-+ }
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/graphite/pr59817-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/graphite/pr59817-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/graphite/pr59817-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -floop-interchange" } */
-+
-+void
-+xl(void)
-+{
-+ static int j3;
-+ for (j3 = 0; j3 < 1; ++j3) {
-+ static int f2;
-+ static int w7;
-+ short int b5;
-+ int ok;
-+ f2 = (b5 += ok) ? (w7 = 0): (w7 ? 0 : (f2 = ok));
-+ }
-+}
-Index: gcc/testsuite/gcc.dg/graphite/pr60740.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/graphite/pr60740.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/graphite/pr60740.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+/* { dg-options "-O2 -floop-interchange" } */
-+
-+int **db6 = 0;
-+
-+void
-+k26(void)
-+{
-+ static int geb = 0;
-+ int *a22 = &geb;
-+ int **l30 = &a22;
-+ int *c4b;
-+ int ndf;
-+ for (ndf = 0; ndf <= 1; ++ndf)
-+ *c4b = (db6 == l30) && (*a22)--;
-+}
-+
-Index: gcc/testsuite/gcc.dg/graphite/pr59817-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/graphite/pr59817-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/graphite/pr59817-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -floop-interchange" } */
-+
-+int kd;
-+
-+void
-+n2(void)
-+{
-+ static int so;
-+ static short int i5;
-+ int wj;
-+ int *il;
-+ int *nk = &so;
-+ for (wj = 0; wj < 2; ++wj)
-+ *nk = ((i5 += *il) || kd );
-+}
-Index: gcc/testsuite/gcc.dg/pr59860.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr59860.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr59860.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O" } */
-+
-+extern __inline __attribute__ ((__always_inline__)) __attribute__ ((__gnu_inline__)) __attribute__ ((__artificial__)) char * __attribute__ ((__nothrow__ , __leaf__))
-+strcat (char *__restrict __dest, const char *__restrict __src)
-+{
-+ return __builtin___strcat_chk (__dest, __src, __builtin_object_size (__dest, 2 > 1));
-+}
-+static char raw_decode;
-+void foo (char **argv, char *outfilename)
-+{
-+ if (**argv == 'r')
-+ raw_decode = 1;
-+ strcat (outfilename, raw_decode ? ".raw" : ".wav");
-+}
-Index: gcc/testsuite/gcc.dg/stack-usage-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/stack-usage-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/stack-usage-1.c (.../branches/gcc-4_8-branch)
-@@ -38,7 +38,11 @@
- # endif
- #elif defined (__powerpc64__) || defined (__ppc64__) || defined (__POWERPC64__) \
- || defined (__PPC64__)
--# define SIZE 180
-+# if _CALL_ELF == 2
-+# define SIZE 208
-+# else
-+# define SIZE 180
-+# endif
- #elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) \
- || defined (__POWERPC__) || defined (PPC) || defined (_IBMR2)
- # if defined (__ALTIVEC__)
-Index: gcc/testsuite/gcc.dg/pr59011.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr59011.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr59011.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+/* PR middle-end/59011 */
-+/* { dg-do compile } */
-+/* { dg-options "-std=gnu99" } */
-+
-+void
-+foo (int m)
-+{
-+ int a[m];
-+ void
-+ bar (void)
-+ {
-+ {
-+ int
-+ baz (void)
-+ {
-+ return a[0];
-+ }
-+ }
-+ a[0] = 42;
-+ }
-+ bar ();
-+}
-Index: gcc/testsuite/gcc.dg/pr58805.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr58805.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr58805.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,24 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -ftree-tail-merge -fdump-tree-pre" } */
-+
-+/* Type that matches the 'p' constraint. */
-+#define TYPE void *
-+
-+static inline
-+void bar (TYPE *r)
-+{
-+ TYPE t;
-+ __asm__ ("" : "=&p" (t), "=p" (*r));
-+}
-+
-+void
-+foo (int n, TYPE *x, TYPE *y)
-+{
-+ if (n == 0)
-+ bar (x);
-+ else
-+ bar (y);
-+}
-+
-+/* { dg-final { scan-tree-dump-times "__asm__" 2 "pre"} } */
-+/* { dg-final { cleanup-tree-dump "pre" } } */
-Index: gcc/testsuite/gcc.dg/strlenopt-14gf.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/strlenopt-14gf.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/strlenopt-14gf.c (.../branches/gcc-4_8-branch)
-@@ -11,14 +11,14 @@
- memcpy. */
- /* { dg-final { scan-tree-dump-times "strlen \\(" 4 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "__mempcpy_chk \\(" 2 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "__mempcpy_chk \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 3 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "mempcpy \\(" 0 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "memcpy \\(" 1 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "mempcpy \\(" 2 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "stpcpy \\(" 2 "strlen" } } */
- /* { dg-final { cleanup-tree-dump "strlen" } } */
-Index: gcc/testsuite/gcc.dg/torture/pr57425-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr57425-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr57425-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,31 @@
-+/* { dg-do run } */
-+
-+extern void abort (void) __attribute__((noreturn));
-+
-+int
-+main ()
-+{
-+ int sum = 0;
-+ {
-+ int a[20];
-+ int *c;
-+ c = a;
-+ asm ("": "=r" (c):"0" (c));
-+ *c = 0;
-+ asm ("": "=r" (c):"0" (c));
-+ sum += *c;
-+ }
-+ {
-+ long b[10];
-+ long *c;
-+ c = b;
-+ asm ("": "=r" (c):"0" (c));
-+ *c = 1;
-+ asm ("": "=r" (c):"0" (c));
-+ sum += *c;
-+ }
-+
-+ if (sum != 1)
-+ abort();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr57425-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr57425-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr57425-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,31 @@
-+/* { dg-do run } */
-+
-+extern void abort (void) __attribute__((noreturn));
-+
-+int
-+main ()
-+{
-+ int sum = 0;
-+ {
-+ long a[20];
-+ long *c;
-+ c = a;
-+ asm ("": "=r" (c):"0" (c));
-+ *c = 0;
-+ asm ("": "=r" (c):"0" (c));
-+ sum += *c;
-+ }
-+ {
-+ long long b[10];
-+ long long *c;
-+ c = b;
-+ asm ("": "=r" (c):"0" (c));
-+ *c = 1;
-+ asm ("": "=r" (c):"0" (c));
-+ sum += *c;
-+ }
-+
-+ if (sum != 1)
-+ abort();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr59047.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr59047.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr59047.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,39 @@
-+/* { dg-do run } */
-+
-+extern void abort (void);
-+
-+struct
-+{
-+ int f0;
-+ int f1:1;
-+ int f2:2;
-+} a = {0, 0, 1};
-+
-+int b, c, *d, e, f;
-+
-+int
-+fn1 ()
-+{
-+ for (; b < 1; ++b)
-+ {
-+ for (e = 0; e < 1; e = 1)
-+ {
-+ int **g = &d;
-+ *g = &c;
-+ }
-+ *d = 0;
-+ f = a.f1;
-+ if (f)
-+ return 0;
-+ }
-+ return 0;
-+}
-+
-+int
-+main ()
-+{
-+ fn1 ();
-+ if (b != 1)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr58956.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr58956.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr58956.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,30 @@
-+/* { dg-do run } */
-+
-+extern void abort (void);
-+
-+struct S
-+{
-+ int f0;
-+} a = {1}, b, g, *c = &b, **f = &c;
-+
-+int *d, **e = &d, h;
-+
-+struct S
-+foo ()
-+{
-+ *e = &h;
-+ if (!d)
-+ __builtin_unreachable ();
-+ *f = &g;
-+ return a;
-+}
-+
-+int
-+main ()
-+{
-+ struct S *i = c;
-+ *i = foo ();
-+ if (b.f0 != 1)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr60183.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr60183.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr60183.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,38 @@
-+/* { dg-do run } */
-+
-+/* Large so an out-of-bound read will crash. */
-+unsigned char c[0x30001] = { 1 };
-+int j = 2;
-+
-+static void
-+foo (unsigned long *x, unsigned char *y)
-+{
-+ int i;
-+ unsigned long w = x[0];
-+ for (i = 0; i < j; i++)
-+ {
-+ w += *y;
-+ y += 0x10000;
-+ w += *y;
-+ y += 0x10000;
-+ }
-+ x[1] = w;
-+}
-+
-+__attribute__ ((noinline, noclone)) void
-+bar (unsigned long *x)
-+{
-+ foo (x, c);
-+}
-+
-+int
-+main ()
-+{
-+ unsigned long a[2] = { 0, -1UL };
-+ asm volatile (""::"r" (c):"memory");
-+ c[0] = 0;
-+ bar (a);
-+ if (a[1] != 0)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr57517.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr57517.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr57517.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+/* { dg-do compile } */
-+
-+int x[1024], y[1024], z[1024], w[1024];
-+void foo (void)
-+{
-+ int i;
-+ for (i = 1; i < 1024; ++i)
-+ {
-+ int a = x[i];
-+ int b = y[i];
-+ int c = x[i-1];
-+ int d = y[i-1];
-+ if (w[i])
-+ z[i] = (a + b) + (c + d);
-+ }
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr59891.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr59891.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr59891.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,9 @@
-+/* PR c/59891 */
-+
-+unsigned int a;
-+
-+int
-+main ()
-+{
-+ return (0 ? a : 0) ? : 0 % 0; /* { dg-warning "division by zero" } */
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr59164.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr59164.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr59164.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+
-+int a, d, e;
-+long b[10];
-+int c[10][8];
-+
-+int fn1(p1)
-+{
-+ return 1 >> p1;
-+}
-+
-+void fn2(void)
-+{
-+ int f;
-+ for (a=1; a <= 4; a++)
-+ {
-+ f = fn1(0 < c[a][0]);
-+ if (f || d)
-+ e = b[a] = 1;
-+ }
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr58779.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr58779.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr58779.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+/* { dg-do run } */
-+
-+int a, c;
-+
-+int main ()
-+{
-+ int e = -1;
-+ short d = (c <= 0) ^ e;
-+ if ((unsigned int) a - (a || d) <= (unsigned int) a)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr59139.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr59139.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr59139.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+/* { dg-do compile } */
-+
-+int a, b, c, d, e;
-+int fn1(p1, p2) { return p2 == 0 ? p1 : 1 % p2; }
-+
-+void fn2()
-+{
-+ c = 0;
-+ for (;; c = (unsigned short)c)
-+ {
-+ b = 2;
-+ for (; b; b = a)
-+ {
-+ e = fn1(2, c && 1);
-+ d = c == 0 ? e : c;
-+ if (d)
-+ return;
-+ }
-+ }
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr58079.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr58079.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr58079.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,107 @@
-+/* { dg-options "-mlong-calls" { target mips*-*-* } } */
-+
-+typedef unsigned char u8;
-+typedef unsigned short u16;
-+typedef unsigned int __kernel_size_t;
-+typedef __kernel_size_t size_t;
-+struct list_head {
-+ struct list_head *next;
-+};
-+
-+struct dmx_ts_feed {
-+ int is_filtering;
-+};
-+struct dmx_section_feed {
-+ u16 secbufp;
-+ u16 seclen;
-+ u16 tsfeedp;
-+};
-+
-+typedef int (*dmx_ts_cb) (
-+ const u8 * buffer1,
-+ size_t buffer1_length,
-+ const u8 * buffer2,
-+ size_t buffer2_length
-+);
-+
-+struct dvb_demux_feed {
-+ union {
-+ struct dmx_ts_feed ts;
-+ struct dmx_section_feed sec;
-+ } feed;
-+ union {
-+ dmx_ts_cb ts;
-+ } cb;
-+ int type;
-+ u16 pid;
-+ int ts_type;
-+ struct list_head list_head;
-+};
-+
-+struct dvb_demux {
-+ int (*stop_feed)(struct dvb_demux_feed *feed);
-+ struct list_head feed_list;
-+};
-+
-+
-+static
-+inline
-+__attribute__((always_inline))
-+u8
-+payload(const u8 *tsp)
-+{
-+ if (tsp[3] & 0x20) {
-+ return 184 - 1 - tsp[4];
-+ }
-+ return 184;
-+}
-+
-+static
-+inline
-+__attribute__((always_inline))
-+int
-+dvb_dmx_swfilter_payload(struct dvb_demux_feed *feed, const u8 *buf)
-+{
-+ int count = payload(buf);
-+ int p;
-+ if (count == 0)
-+ return -1;
-+ return feed->cb.ts(&buf[p], count, ((void *)0), 0);
-+}
-+
-+static
-+inline
-+__attribute__((always_inline))
-+void
-+dvb_dmx_swfilter_packet_type(struct dvb_demux_feed *feed, const u8 *buf)
-+{
-+ switch (feed->type) {
-+ case 0:
-+ if (feed->ts_type & 1) {
-+ dvb_dmx_swfilter_payload(feed, buf);
-+ }
-+ if (dvb_dmx_swfilter_section_packet(feed, buf) < 0)
-+ feed->feed.sec.seclen = feed->feed.sec.secbufp = 0;
-+ }
-+}
-+
-+static
-+void
-+dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)
-+{
-+ struct dvb_demux_feed *feed;
-+ int dvr_done = 0;
-+
-+ for (feed = ({ const typeof( ((typeof(*feed) *)0)->list_head ) *__mptr = ((&demux->feed_list)->next); (typeof(*feed) *)( (char *)__mptr - __builtin_offsetof(typeof(*feed),list_head) );}); __builtin_prefetch(feed->list_head.next), &feed->list_head != (&demux->feed_list); feed = ({ const typeof( ((typeof(*feed) *)0)->list_head ) *__mptr = (feed->list_head.next); (typeof(*feed) *)( (char *)__mptr - __builtin_offsetof(typeof(*feed),list_head) );})) {
-+ if (((((feed)->type == 0) && ((feed)->feed.ts.is_filtering) && (((feed)->ts_type & (1 | 8)) == 1))) && (dvr_done++))
-+ dvb_dmx_swfilter_packet_type(feed, buf);
-+ else if (feed->pid == 0x2000)
-+ feed->cb.ts(buf, 188, ((void *)0), 0);
-+ }
-+}
-+void dvb_dmx_swfilter_packets(struct dvb_demux *demux, const u8 *buf, size_t count)
-+{
-+ while (count--) {
-+ dvb_dmx_swfilter_packet(demux, buf);
-+ }
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr60903.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr60903.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr60903.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+/* { dg-do compile } */
-+
-+extern int a, b, k, q;
-+
-+void
-+foo ()
-+{
-+ if (a)
-+ {
-+ while (q)
-+ {
-+ lbl:
-+ if (a)
-+ {
-+ a = 0;
-+ goto lbl;
-+ }
-+ }
-+ b = k;
-+ }
-+ goto lbl;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr58830.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr58830.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr58830.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,42 @@
-+/* { dg-do run } */
-+/* { dg-additional-options "-ftree-pre -ftree-partial-pre" } */
-+
-+extern void abort (void);
-+
-+int b, c, d, f, g, h, i, j[6], *l = &b, *m, n, *o, r;
-+char k;
-+
-+static int
-+foo ()
-+{
-+ char *p = &k;
-+
-+ for (; d; d++)
-+ if (i)
-+ h = 0;
-+ else
-+ h = c || (r = 0);
-+
-+ for (f = 0; f < 2; f++)
-+ {
-+ unsigned int q;
-+ *l = 0;
-+ if (n)
-+ *m = g;
-+ if (g)
-+ o = 0;
-+ for (q = -8; q >= 5; q++)
-+ (*p)--;
-+ }
-+
-+ return 0;
-+}
-+
-+int
-+main ()
-+{
-+ foo ();
-+ if (j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[j[0]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] ^ (k & 15)] != 0)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr60930.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr60930.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr60930.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+/* { dg-do run } */
-+
-+int x = 1;
-+
-+__attribute__((noinline, noclone)) void
-+foo (unsigned long long t)
-+{
-+ asm volatile ("" : : "r" (&t));
-+ if (t == 1)
-+ __builtin_abort ();
-+}
-+
-+int
-+main ()
-+{
-+#if __SIZEOF_LONG_LONG__ >= 8
-+ unsigned long long t = 0xffffffffffffffffULL * (0xffffffffUL * x);
-+ if (t != 0xffffffff00000001ULL)
-+ foo (t);;
-+#endif
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr59715.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr59715.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr59715.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* { dg-do run } */
-+
-+extern void abort (void);
-+
-+int a = 2, b;
-+
-+int
-+main ()
-+{
-+ int c;
-+ if (!b)
-+ {
-+ b = a;
-+ c = a == 0 ? 1 : 1 % a;
-+ if (c)
-+ b = 0;
-+ }
-+ if (b != 0)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr60115.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr60115.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr60115.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* { dg-do run } */
-+
-+int a, b[2];
-+
-+int
-+main ()
-+{
-+lbl:
-+ for (; a; a--)
-+ if (b[10000])
-+ goto lbl;
-+
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr59903.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr59903.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr59903.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,56 @@
-+/* { dg-do compile } */
-+
-+int a, b, c, d, e, f, g, h, i[3], l, m, n, o, p, q, r;
-+
-+struct S0
-+{
-+ int f0;
-+ int f1;
-+ int f2;
-+ int f3;
-+} j;
-+
-+static int
-+fn1 (int p1)
-+{
-+ return p1 || ((p1 > 0) > (e << 1));
-+}
-+
-+static struct S0
-+fn2 (struct S0 p1)
-+{
-+ char s;
-+ struct S0 t = {0,0,0,0};
-+ int u = 2;
-+ for (;;)
-+ {
-+ if (i[0])
-+ break;
-+ for (m = 0; m < 4; m++)
-+ for (p1.f0 = 0; p1.f0 < 3; p1.f0++)
-+ {
-+ j = t;
-+ t.f3 = i[p1.f0];
-+ o = b || 1 >> b ? 0 : a < 0;
-+ q = 1 % d;
-+ if ((g < fn1 ((1 ^ (q & 1)) | n)) ^ u)
-+ j.f3 |= p % 2;
-+ s = j.f3 > 0 ? j.f3 : j.f3 << 1;
-+ r = l = s && p1.f1 * c;
-+ h = p1.f1;
-+ }
-+ }
-+ return p1;
-+}
-+
-+int
-+main ()
-+{
-+ for (;f;)
-+ {
-+ struct S0 v = {0,0,0,0};
-+ fn2 (v);
-+ j.f3 = 0;
-+ }
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr58143-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr58143-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr58143-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,51 @@
-+/* { dg-do run } */
-+/* { dg-additional-options "-fstrict-overflow" } */
-+
-+extern void abort (void);
-+
-+int a, b, c, d, e, f, g, h = 1, i;
-+
-+int foo (int p)
-+{
-+ return p < 0 && a < - __INT_MAX__ - 1 - p ? 0 : 1;
-+}
-+
-+int *bar ()
-+{
-+ int j;
-+ i = h ? 0 : 1 % h;
-+ for (j = 0; j < 1; j++)
-+ for (d = 0; d; d++)
-+ for (e = 1; e;)
-+ return 0;
-+ return 0;
-+}
-+
-+int baz ()
-+{
-+ for (; b >= 0; b--)
-+ for (c = 1; c >= 0; c--)
-+ {
-+ int *k = &c;
-+ for (;;)
-+ {
-+ for (f = 0; f < 1; f++)
-+ {
-+ g = foo (*k);
-+ bar ();
-+ }
-+ if (*k)
-+ break;
-+ return 0;
-+ }
-+ }
-+ return 0;
-+}
-+
-+int main ()
-+{
-+ baz ();
-+ if (b != 0)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr58143-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr58143-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr58143-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,34 @@
-+/* { dg-do run } */
-+/* { dg-additional-options "-fstrict-overflow" } */
-+
-+int a, b, d, e, f, *g, h, i;
-+volatile int c;
-+
-+char foo (unsigned char p)
-+{
-+ return p + 1;
-+}
-+
-+int bar ()
-+{
-+ for (h = 0; h < 3; h = foo (h))
-+ {
-+ c;
-+ for (f = 0; f < 1; f++)
-+ {
-+ i = a && 0 < -__INT_MAX__ - h ? 0 : 1;
-+ if (e)
-+ for (; d;)
-+ b = 0;
-+ else
-+ g = 0;
-+ }
-+ }
-+ return 0;
-+}
-+
-+int main ()
-+{
-+ bar ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr58941.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr58941.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr58941.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,33 @@
-+/* { dg-do run } */
-+
-+extern void abort (void);
-+
-+typedef struct {
-+ int msgLength;
-+ unsigned char data[1000];
-+} SMsg;
-+
-+typedef struct {
-+ int dummy;
-+ int d[0];
-+} SData;
-+
-+int condition = 3;
-+
-+int main()
-+{
-+ SMsg msg;
-+ SData *pData = (SData*)(msg.data);
-+ unsigned int i = 0;
-+ for (i = 0; i < 1; i++)
-+ {
-+ pData->d[i] = 0;
-+ if(condition & 1)
-+ pData->d[i] |= 0x55;
-+ if(condition & 2)
-+ pData->d[i] |= 0xaa;
-+ }
-+ if (pData->d[0] != 0xff)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr57488.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr57488.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr57488.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,58 @@
-+/* { dg-do run } */
-+
-+extern void abort (void);
-+
-+int i, j, *pj = &j, **ppj = &pj;
-+int x, *px = &x;
-+
-+short s, *ps = &s, k;
-+
-+unsigned short u, *pu = &u, **ppu = &pu;
-+
-+char c, *pc = &c;
-+
-+unsigned char v = 48;
-+
-+static int
-+bar (int p)
-+{
-+ p = k;
-+ *px = **ppu = i;
-+ *ppj = &p;
-+ if (**ppj)
-+ *pj = p;
-+ return p;
-+}
-+
-+void __attribute__((noinline))
-+foo ()
-+{
-+ for (; i <= 3; i++)
-+ for (; j; j--);
-+
-+ u ^= bar (*pj);
-+
-+ for (k = 1; k >= 0; k--)
-+ {
-+ int l;
-+ bar (0);
-+ for (l = 1; l < 5; l++)
-+ {
-+ int m;
-+ for (m = 6; m; m--)
-+ {
-+ v--;
-+ *ps = *pc;
-+ }
-+ }
-+ }
-+}
-+
-+int
-+main ()
-+{
-+ foo ();
-+ if (v != 0)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr57569.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr57569.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr57569.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+/* { dg-do run } */
-+
-+extern void abort (void) __attribute__((noreturn));
-+
-+struct S { int f0; } a;
-+
-+int b, e, *d = &b, f;
-+
-+void
-+fn1 ()
-+{
-+ int **g[9][6];
-+ int ***h = &g[6][3];
-+ for (; e < 9; e++) {
-+ f = 0;
-+ for (; f < 6; f++)
-+ g[e][f] = &d;
-+ }
-+ ***h = 0;
-+}
-+
-+void
-+fn2 ()
-+{
-+ fn1 ();
-+ struct S c[4][10] = {};
-+ a = c[3][9];
-+}
-+
-+int
-+main ()
-+{
-+ fn2 ();
-+ if (a.f0 != 0)
-+ abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr58143-3.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr58143-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr58143-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,18 @@
-+/* { dg-do run } */
-+/* { dg-additional-options "-fstrict-overflow" } */
-+
-+int a, b, c, d, e;
-+
-+int
-+main ()
-+{
-+ for (b = 4; b > -30; b--)
-+ for (; c;)
-+ for (;;)
-+ {
-+ e = a > __INT_MAX__ - b;
-+ if (d)
-+ break;
-+ }
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr53922.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr53922.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr53922.c (.../branches/gcc-4_8-branch)
-@@ -3,6 +3,7 @@
- /* { dg-skip-if "No undefined" { *-*-mingw* } { "*" } { "" } } */
- /* { dg-skip-if "No undefined weak" { hppa*-*-hpux* && { ! lp64 } } { "*" } { "" } } */
- /* { dg-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } } */
-+/* { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } } */
-
- int x(int a)
- {
-Index: gcc/testsuite/gcc.dg/torture/pr57864.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr57864.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr57864.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+/* { dg-do compile } */
-+
-+union U {
-+ double val;
-+ union U *ptr;
-+};
-+
-+union U *d;
-+double a;
-+int b;
-+int c;
-+
-+static void fn1(union U *p1, int p2, _Bool p3)
-+{
-+ union U *e;
-+
-+ if (p2 == 0)
-+ a = ((union U*)((unsigned long)p1 & ~1))->val;
-+
-+ if (b) {
-+ e = p1;
-+ } else if (c) {
-+ e = ((union U*)((unsigned long)p1 & ~1))->ptr;
-+ d = e;
-+ } else {
-+ e = 0;
-+ d = ((union U*)0)->ptr;
-+ }
-+
-+ fn1 (e, 0, 0);
-+ fn1 (0, 0, p3);
-+}
-+
-+void fn2 (void)
-+{
-+ fn1 (0, 0, 0);
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr59288.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr59288.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr59288.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,9 @@
-+/* { dg-do compile } */
-+
-+void
-+baz (int *d)
-+{
-+ long int i, j, k;
-+ for (i = 0, j = 0, k = 0; i < 512; i = (int) i + 1, j = (int) j + 1, k = (int) k + 3)
-+ d[i] = j ^ (i * 3) ^ (2 * k + 2);
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr60766.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr60766.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr60766.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+/* { dg-do run } */
-+
-+int m = 9;
-+
-+int main()
-+{
-+ int n, x;
-+
-+ n = m;
-+ for (x = 0; x <= n; x++)
-+ if (n == x + (x + 1) + (x + 2))
-+ return 0;
-+
-+ __builtin_abort();
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr57425-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr57425-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr57425-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,37 @@
-+/* { dg-do run } */
-+
-+extern void abort (void) __attribute__((noreturn));
-+
-+union setconflict
-+{
-+ int a[20];
-+ long b[10];
-+};
-+
-+int
-+main ()
-+{
-+ int sum = 0;
-+ {
-+ union setconflict a;
-+ int *c;
-+ c = a.a;
-+ asm ("": "=r" (c):"0" (c));
-+ *c = 0;
-+ asm ("": "=r" (c):"0" (c));
-+ sum += *c;
-+ }
-+ {
-+ union setconflict a;
-+ long *c;
-+ c = a.b;
-+ asm ("": "=r" (c):"0" (c));
-+ *c = 1;
-+ asm ("": "=r" (c):"0" (c));
-+ sum += *c;
-+ }
-+
-+ if (sum != 1)
-+ abort();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr59330.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr59330.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr59330.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,17 @@
-+/* { dg-do run } */
-+
-+void free(void *ptr)
-+{
-+}
-+
-+void *foo(void)
-+{
-+ return 0;
-+}
-+
-+int main(void)
-+{
-+ void *p = foo();
-+ free(p);
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/unused-8b.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/unused-8b.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/unused-8b.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,4 @@
-+/* { dg-do compile } */
-+/* { dg-options "-Wall -Wno-unused -Wextra" } */
-+
-+void foo(int x) { }
-Index: gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c (.../branches/gcc-4_8-branch)
-@@ -16,6 +16,7 @@
- /* We used to treat malloc functions like pure and const functions, but
- malloc functions may clobber global memory. Only the function result
- does not alias any other pointer.
-- Hence, we must have a VDEF for a before and after the call to foo(). */
--/* { dg-final { scan-tree-dump-times "VDEF" 2 "alias"} } */
-+ Hence, we must have a VDEF for a before and after the call to foo().
-+ And one after the call to abort(). */
-+/* { dg-final { scan-tree-dump-times "VDEF" 3 "alias"} } */
- /* { dg-final { cleanup-tree-dump "alias" } } */
-Index: gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+/* { dg-do run } */
-+/* { dg-options "-O3" } */
-+
-+int a, c, e[5][2];
-+unsigned int d;
-+
-+int
-+main ()
-+{
-+ for (d = 0; d < 2; d++)
-+ if (a ? 0 : e[c + 3][d] & e[c + 4][d])
-+ break;
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,18 @@
-+/* { dg-do run } */
-+/* { dg-options "-O3 -fdump-tree-pcom-details" } */
-+
-+int b, f, d[5][2];
-+unsigned int c;
-+
-+int
-+main ()
-+{
-+ for (c = 0; c < 2; c++)
-+ if (d[b + 3][c] & d[b + 4][c])
-+ if (f)
-+ break;
-+ return 0;
-+}
-+
-+/* { dg-final { scan-tree-dump "Executing predictive commoning" "pcom" } } */
-+/* { dg-final { cleanup-tree-dump "pcom" } } */
-Index: gcc/testsuite/gcc.dg/tls/pr58595.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/tls/pr58595.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/tls/pr58595.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,28 @@
-+/* PR target/58595 */
-+/* { dg-do run } */
-+/* { dg-options "-O2" } */
-+/* { dg-additional-options "-fpic" { target fpic } } */
-+/* { dg-require-effective-target tls } */
-+/* { dg-require-effective-target sync_int_long } */
-+
-+struct S { unsigned long a, b; };
-+__thread struct S s;
-+void bar (unsigned long *);
-+
-+__attribute__((noinline)) void
-+foo (void)
-+{
-+ int i;
-+ for (i = 0; i < 10; i++)
-+ __sync_fetch_and_add (&s.b, 1L);
-+}
-+
-+int
-+main ()
-+{
-+ s.b = 12;
-+ foo ();
-+ if (s.b != 22)
-+ __builtin_abort ();
-+ return 0;
-+}
-Index: gcc/testsuite/gcc.dg/strlenopt-4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/strlenopt-4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/strlenopt-4.c (.../branches/gcc-4_8-branch)
-@@ -66,16 +66,10 @@
- return 0;
- }
-
--/* For targets providing a movstr pattern strcat is already decomposed
-- into strlen + strcpy by fold_builtin_strcat. */
--
--/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" { target { ! s390*-*-* } } } } */
--/* { dg-final { scan-tree-dump-times "strlen \\(" 6 "strlen" { target s390*-*-* } } } */
-+/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "strcpy \\(" 3 "strlen" { target { ! s390*-*-* } } } } */
--/* { dg-final { scan-tree-dump-times "strcpy \\(" 6 "strlen" { target s390*-*-* } } } */
--/* { dg-final { scan-tree-dump-times "strcat \\(" 3 "strlen" { target { ! s390*-*-* } } } } */
--/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" { target s390*-*-* } } } */
-+/* { dg-final { scan-tree-dump-times "strcpy \\(" 3 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "strcat \\(" 3 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
- /* { dg-final { cleanup-tree-dump "strlen" } } */
-Index: gcc/testsuite/gcc.dg/pr56824.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr56824.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr56824.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,18 @@
-+/* PR preprocessor/56824 */
-+/* { dg-do compile } */
-+/* { dg-options "-Waggregate-return" } */
-+
-+struct S { int i; };
-+struct S foo (void);
-+
-+#pragma GCC diagnostic push
-+#pragma GCC diagnostic ignored "-Waggregate-return"
-+
-+int
-+main ()
-+{
-+ foo ();
-+ return 0;
-+}
-+
-+#pragma GCC diagnostic pop
-Index: gcc/testsuite/gcc.dg/ipa/pr55260.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/ipa/pr55260.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/ipa/pr55260.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,38 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -fno-inline -fipa-cp-clone" } */
-+
-+typedef struct {
-+ int *ptr;
-+ int len;
-+} string;
-+typedef struct {
-+ string nantstr;
-+ int *nant;
-+} malv;
-+typedef struct {
-+ int *nor;
-+} list_heads;
-+int b;
-+list_heads *fn1(string, int *, unsigned);
-+void fn2(malv *p1, list_heads *p2, unsigned p3) {
-+ string a = p1->nantstr;
-+ fn1(a, p1->nant, p3);
-+}
-+
-+void fn3(unsigned p1) { fn2(0, 0, p1); }
-+
-+list_heads *fn1(string p1, int *p2, unsigned p3) {
-+ while (1) {
-+ if (p3)
-+ fn3(1);
-+ if (b)
-+ return 0;
-+ fn3(1);
-+ }
-+}
-+
-+void fn5() {
-+ list_heads c;
-+ c.nor = 0;
-+ fn2(0, &c, 1);
-+}
-Index: gcc/testsuite/gcc.dg/ipa/pr59610.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/ipa/pr59610.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/ipa/pr59610.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2" } */
-+
-+struct A { int a; };
-+extern void *y;
-+
-+__attribute__((optimize (0))) void
-+foo (void *p, struct A x)
-+{
-+ foo (y, x);
-+}
-Index: gcc/testsuite/gcc.dg/pr60485-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr60485-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr60485-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2" } */
-+
-+extern void abort (void);
-+struct S {
-+ int *i[4];
-+ int *p1;
-+ int *p2;
-+ int *p3;
-+ int *p4;
-+};
-+int **b;
-+int main()
-+{
-+ int i = 1;
-+ struct S s;
-+ s.p3 = &i;
-+ int **p;
-+ if (b)
-+ p = b;
-+ else
-+ p = &s.i[2];
-+ p += 4;
-+ if (!b)
-+ **p = 0;
-+ if (i != 0)
-+ abort ();
-+ return i;
-+}
-Index: gcc/testsuite/gcc.dg/strlenopt-1f.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/strlenopt-1f.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/strlenopt-1f.c (.../branches/gcc-4_8-branch)
-@@ -6,13 +6,13 @@
- #include "strlenopt-1.c"
-
- /* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 3 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 1 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */
--/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "memcpy \\(" 3 "strlen" } } */
-+/* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
- /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
- /* { dg-final { cleanup-tree-dump "strlen" } } */
-Index: gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c (.../branches/gcc-4_8-branch)
-@@ -1,4 +1,5 @@
- /* { dg-require-effective-target vect_int } */
-+/* { dg-skip-if "cost too high" { powerpc*le-*-* } { "*" } { "" } } */
-
- #include <stdarg.h>
- #include "../../tree-vect.h"
-Index: gcc/testsuite/gcc.dg/vect/pr60382.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vect/pr60382.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vect/pr60382.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,32 @@
-+#include "tree-vect.h"
-+
-+int a, b, c, e, f;
-+
-+void
-+foo ()
-+{
-+ for (b = 0; b < 3; b++)
-+ if (e)
-+ {
-+ for (c = 0; c < 4; c++)
-+ {
-+ if (b)
-+ continue;
-+ f = 1;
-+ for (a = 0; a < 2; a++)
-+ f |= 1;
-+ }
-+ for (;;)
-+ ;
-+ }
-+}
-+
-+int
-+main ()
-+{
-+ check_vect ();
-+ foo ();
-+ return 0;
-+}
-+
-+/* { dg-final { cleanup-tree-dump "vect" } } */
-Index: gcc/testsuite/gcc.dg/vect/pr60276.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vect/pr60276.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vect/pr60276.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,52 @@
-+/* { dg-do run } */
-+
-+extern void abort (void);
-+
-+static void
-+foo (int *out, const int *lp, unsigned samples)
-+{
-+ int x, target;
-+ for (x = 0, target = 0; x < (int)samples; x += 2, target++)
-+ {
-+ out[x] = lp[target];
-+ out[x - 1] = out[x - 2] + out[x];
-+ }
-+}
-+
-+static void
-+foo_novec (int *out, const int *lp, unsigned samples)
-+{
-+ int x, target;
-+ for (x = 0, target = 0; x < (int)samples; x += 2, target++)
-+ {
-+ out[x] = lp[target];
-+ out[x - 1] = out[x - 2] + out[x];
-+ __asm__ volatile ("" : : : "memory");
-+ }
-+}
-+
-+int main(void)
-+{
-+ const int lp[25] = {
-+ 0, 2, 4, 6, 8,
-+ 10, 12, 14, 16,
-+ 18, 20, 22, 24,
-+ 26, 28, 30, 32,
-+ 34, 36, 38, 40,
-+ 42, 44, 46, 48,
-+ };
-+ int out[49] = {0};
-+ int out2[49] = {0};
-+ int s;
-+
-+ foo (out + 2, lp + 1, 48);
-+ foo_novec (out2 + 2, lp + 1, 48);
-+
-+ for (s = 0; s < 49; s++)
-+ if (out[s] != out2[s])
-+ abort ();
-+
-+ return 0;
-+}
-+
-+/* { dg-final { cleanup-tree-dump "vect" } } */
-Index: gcc/testsuite/gcc.dg/pr53060.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr53060.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr53060.c (.../branches/gcc-4_8-branch)
-@@ -25,3 +25,4 @@
-
- /* Ignore a warning that is irrelevant to the purpose of this test. */
- /* { dg-prune-output ".*GCC vector returned by reference.*" } */
-+/* { dg-prune-output "changes the ABI" } */
-Index: gcc/testsuite/ChangeLog
-===================================================================
---- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,1861 @@
-+2014-05-14 Matthias Klose <doko@ubuntu.com>
-+
-+ PR driver/61106
-+ * gcc-dg/unused-8a.c: Remove.
-+
-+2014-05-13 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * lib/target-support.exp (check_dfp_hw_available): New function.
-+ (is-effective-target): Check $arg for dfp_hw.
-+ (is-effective-target-keyword): Likewise.
-+ * gcc.target/powerpc/pack03.c: (dg-require-effective-target):
-+ Change target to dfp_hw.
-+
-+2014-05-12 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
-+
-+ Backport from mainline
-+ 2014-05-12 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
-+
-+ PR target/60991
-+ * gcc.target/avr/pr60991.c: New testcase.
-+
-+2014-05-09 Georg-Johann Lay <avr@gjlay.de>
-+
-+ Backport from 2014-05-09 trunk r210267
-+
-+ PR target/61055
-+ * gcc.target/avr/torture/pr61055.c: New test.
-+
-+2014-05-08 Matthias Klose <doko@ubuntu.com>
-+
-+ PR driver/61106
-+ * gcc-dg/unused-8a.c: New.
-+ * gcc-dg/unused-8b.c: Likewise.
-+
-+2014-05-07 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/57864
-+ * gcc.dg/torture/pr57864.c: New testcase.
-+
-+2014-05-06 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-04-14 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/55022
-+ * gcc.dg/graphite/pr55022.c: New testcase.
-+
-+2014-05-06 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-04-17 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60849
-+ * g++.dg/opt/pr60849.C: New testcase.
-+
-+ 2014-04-07 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60766
-+ * gcc.dg/torture/pr60766.c: New testcase.
-+
-+ 2014-04-23 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60903
-+ * gcc.dg/torture/pr60903.c: New testcase.
-+
-+2014-05-05 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-04-23 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60895
-+ * g++.dg/torture/pr60895.C: New testcase.
-+
-+ 2014-04-07 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60750
-+ * g++.dg/torture/pr60750.C: New testcase.
-+ * gcc.dg/tree-ssa/20040517-1.c: Adjust.
-+
-+ 2014-04-14 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59817
-+ PR tree-optimization/60453
-+ * gfortran.dg/graphite/pr59817.f: New testcase.
-+ * gcc.dg/graphite/pr59817-1.c: Likewise.
-+ * gcc.dg/graphite/pr59817-2.c: Likewise.
-+
-+ 2014-04-17 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60836
-+ * g++.dg/vect/pr60836.cc: New testcase.
-+
-+2014-05-05 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backported from mainline
-+ 2014-04-25 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/60960
-+ * gcc.c-torture/execute/pr60960.c: New test.
-+
-+2014-05-04 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * gcc.target/powerpc/pack02.c (dg-options): Add -mhard-float.
-+ (dg-require-effective-target): Change target to powerpc_fprs.
-+ * gcc.target/powerpc/pack03.c (dg-options): Add -mhard-dfp.
-+ (dg-require-effective-target): Change target to dfprt.
-+
-+2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ PR tree-optimization/60930
-+ * gcc.dg/torture/pr60930.c: New test.
-+
-+2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ Back port from mainline
-+ 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/pack01.c: New test to test the new pack and
-+ unpack builtin functionss for 128-bit types.
-+ * gcc.target/powerpc/pack02.c: Likewise.
-+ * gcc.target/powerpc/pack03.c: Likewise.
-+ * gcc.target/powerpc/extend-divide-1.c: New test to test extended
-+ divide builtin functionss.
-+ * gcc.target/powerpc/extend-divide-2.c: Likewise.
-+ * gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin
-+ functions.
-+ * gcc.target/powerpc/bcd-2.c: Likewise.
-+ * gcc.target/powerpc/bcd-3.c: Likewise.
-+ * gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP
-+ builtin functionss.
-+ * gcc.target/powerpc/dfp-builtin-2.c: Likewise.
-+
-+2014-04-29 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ Backport from mainline
-+ 2014-04-17 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * gcc.target/powerpc/ti_math1.c: New.
-+ * gcc.target/powerpc/ti_math2.c: New.
-+
-+2014-04-25 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * gcc.c-torture/execute/20140425-1.c: New test.
-+
-+2014-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ Back port from main line:
-+ 2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/p8vector-vbpermq.c: New test to test the
-+ vbpermq builtin.
-+
-+2014-04-23 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-04-21 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/60909
-+ * gcc.target/i386/pr60909-1.c: New test.
-+ * gcc.target/i386/pr60909-2.c: Ditto.
-+
-+2014-04-23 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-04-02 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60729
-+ * g++.dg/vect/pr60729.cc: New testcase.
-+
-+ 2014-04-03 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60740
-+ * gcc.dg/graphite/pr60740.c: New testcase.
-+
-+2014-04-23 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/60635
-+ * gfortran.dg/lto/pr60635_0.f90: New testcase.
-+ * gfortran.dg/lto/pr60635_1.c: Likewise.
-+
-+2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ Back port from the trunk, subversion id 209546.
-+
-+ 2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/60735
-+ * gcc.target/powerpc/pr60735.c: New test. Insure _Decimal64 does
-+ not cause errors if -mspe.
-+
-+2014-04-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/merge-vsx.c: Add V4SI and V4SF tests.
-+ * gcc.dg/vmx/merge-vsx-be-order.c: Likewise.
-+
-+2014-04-12 Jerry DeLisle <jvdelisle@gcc.gnu>
-+
-+ Backport from mainline
-+ PR libfortran/60810
-+ * gfortran.dg/arrayio_13.f90: New test.
-+
-+2014-04-11 Hans-Peter Nilsson <hp@axis.com>
-+
-+ * gfortran.dg/fmt_en.f90: Gate test on effective_target
-+ fd_truncate.
-+
-+2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ * gcc.target/s390/htm-nofloat-1.c: Rename to ...
-+ * gcc.target/s390/htm-nofloat-compile-1.c: ... this one.
-+ * gcc.target/s390/htm-nofloat-2.c: Add check for htm target and
-+ rename to ...
-+ * gcc.target/s390/htm-nofloat-1.c: ... this one.
-+ * gcc.target/s390/s390.exp: Make sure the assembler supports htm
-+ instructions as well.
-+
-+2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ * gcc.target/s390/htm-builtins-compile-1.c: Replace long long with
-+ long.
-+
-+2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ * gcc.target/s390/htm-builtins-compile-1.c: Remove htm check.
-+ * gcc.target/s390/htm-builtins-compile-2.c: Remove htm check.
-+
-+2014-04-10 Vladimir Makarov <vmakarov@redhat.com>
-+
-+ PR rtl-optimization/60769
-+ * g++.dg/pr60769.C: New.
-+
-+2014-04-10 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-03-12 Jakub Jelinek <jakub@redhat.com>
-+ Marc Glisse <marc.glisse@inria.fr>
-+
-+ PR tree-optimization/60502
-+ * gcc.c-torture/compile/pr60502.c: New test.
-+
-+ 2014-03-28 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/60693
-+ * gcc.target/i386/pr60693.c: New test.
-+
-+ PR c++/60689
-+ * c-c++-common/pr60689.c: New test.
-+
-+ 2014-03-22 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR debug/60603
-+ * gcc.dg/debug/dwarf2/dwarf2-macro2.c: New test.
-+
-+ 2014-03-17 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/60516
-+ * gcc.target/i386/pr60516.c: New test.
-+
-+ 2014-03-13 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/36282
-+ * c-c++-common/pr36282-1.c: New test.
-+ * c-c++-common/pr36282-2.c: New test.
-+ * c-c++-common/pr36282-3.c: New test.
-+ * c-c++-common/pr36282-4.c: New test.
-+
-+ 2014-03-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/58595
-+ * gcc.dg/tls/pr58595.c: New test.
-+
-+2014-04-07 Martin Jambor <mjambor@suse.cz>
-+
-+ PR ipa/60640
-+ * g++.dg/ipa/pr60640-1.C: New test.
-+ * g++.dg/ipa/pr60640-2.C: Likewise.
-+ * g++.dg/ipa/pr60640-3.C: Likewise.
-+
-+2014-04-06 Dominique d'Humieres <dominiq@lps.ens.fr>
-+ Iain Sandoe <iain@codesourcery.com>
-+
-+ PR target/54083
-+ * gcc.dg/attr-weakref-1.c: Allow the test on darwin with
-+ the additional options -Wl,-undefined,dynamic_lookup and
-+ -Wl,-flat_namespace
-+ * gcc.dg/torture/pr53922.c: Additional option
-+ -Wl,-flat_namespace for darwin[89].
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-04-05 David Edelsohn <dje.gcc@gmail.com>
-+
-+ * gcc.target/powerpc/sd-vsx.c: Skip on AIX.
-+ * gcc.target/powerpc/sd-pwr6.c: Same.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Back port from trunk
-+ 2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/p8vector-int128-1.c: New test to test ISA
-+ 2.07 128-bit arithmetic.
-+ * gcc.target/powerpc/p8vector-int128-2.c: Likewise.
-+
-+ * gcc.target/powerpc/timode_off.c: Restrict cpu type to power5,
-+ due to when TImode is allowed in VSX registers, the allowable
-+ address modes for TImode is just a single indirect address in
-+ order for the value to be loaded and store in either GPR or VSX
-+ registers. This affects the generated code, and it would cause
-+ this test to fail, when such an option is used.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r207699.
-+ 2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/60137
-+ * gcc.target/powerpc/pr60137.c: New file.
-+
-+ Backport from mainline r207808.
-+ 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/60203
-+ * gcc.target/powerpc/pr60203.c: New testsuite.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Little Endian Vector API Support
-+ Backport from mainline r206590
-+ 2014-01-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/insert.c: New.
-+ * gcc.dg/vmx/insert-be-order.c: New.
-+ * gcc.dg/vmx/extract.c: New.
-+ * gcc.dg/vmx/extract-be-order.c: New.
-+
-+ Backport from mainline r206641
-+ 2014-01-15 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
-+
-+ * gcc.dg/vmx/mult-even-odd.c: New.
-+ * gcc.dg/vmx/mult-even-odd-be-order.c: New.
-+
-+ Backport from mainline r206926
-+ 2014-01-22 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/insert-vsx-be-order.c: New.
-+ * gcc.dg/vmx/extract-vsx.c: New.
-+ * gcc.dg/vmx/extract-vsx-be-order.c: New.
-+ * gcc.dg/vmx/insert-vsx.c: New.
-+
-+ Backport from mainline r207262
-+ 2014-01-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/merge-be-order.c: New.
-+ * gcc.dg/vmx/merge.c: New.
-+ * gcc.dg/vmx/merge-vsx-be-order.c: New.
-+ * gcc.dg/vmx/merge-vsx.c: New.
-+
-+ Backport from mainline r207318
-+ 2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/splat.c: New.
-+ * gcc.dg/vmx/splat-vsx.c: New.
-+ * gcc.dg/vmx/splat-be-order.c: New.
-+ * gcc.dg/vmx/splat-vsx-be-order.c: New.
-+ * gcc.dg/vmx/eg-5.c: Remove special casing for little endian.
-+ * gcc.dg/vmx/sn7153.c: Add special casing for little endian.
-+
-+ Backport from mainline r207414
-+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/vsums.c: New.
-+ * gcc.dg/vmx/vsums-be-order.c: New.
-+
-+ Backport from mainline r207415
-+ 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/3b-15.c: Remove special handling for little endian.
-+ * gcc.dg/vmx/perm.c: New.
-+ * gcc.dg/vmx/perm-be-order.c: New.
-+
-+ Backport from mainline r207520
-+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/pack.c: New.
-+ * gcc.dg/vmx/pack-be-order.c: New.
-+ * gcc.dg/vmx/unpack.c: New.
-+ * gcc.dg/vmx/unpack-be-order.c: New.
-+
-+ Backport from mainline r207521
-+ 2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/sum2s.c: New.
-+ * gcc.dg/vmx/sum2s-be-order.c: New.
-+
-+ Backport from mainline 208019
-+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/ld.c: New test.
-+ * gcc.dg/vmx/ld-be-order.c: New test.
-+ * gcc.dg/vmx/ld-vsx.c: New test.
-+ * gcc.dg/vmx/ld-vsx-be-order.c: New test.
-+ * gcc.dg/vmx/ldl.c: New test.
-+ * gcc.dg/vmx/ldl-be-order.c: New test.
-+ * gcc.dg/vmx/ldl-vsx.c: New test.
-+ * gcc.dg/vmx/ldl-vsx-be-order.c: New test.
-+ * gcc.dg/vmx/st.c: New test.
-+ * gcc.dg/vmx/st-be-order.c: New test.
-+ * gcc.dg/vmx/st-vsx.c: New test.
-+ * gcc.dg/vmx/st-vsx-be-order.c: New test.
-+ * gcc.dg/vmx/stl.c: New test.
-+ * gcc.dg/vmx/stl-be-order.c: New test.
-+ * gcc.dg/vmx/stl-vsx.c: New test.
-+ * gcc.dg/vmx/stl-vsx-be-order.c: New test.
-+
-+ Backport from mainline 208021
-+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/vsums.c: Check entire result vector.
-+ * gcc.dg/vmx/vsums-be-order.c: Likewise.
-+
-+ Backport from mainline 208049
-+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/lde.c: New test.
-+ * gcc.dg/vmx/lde-be-order.c: New test.
-+ * gcc.dg/vmx/ste.c: New test.
-+ * gcc.dg/vmx/ste-be-order.c: New test.
-+
-+ Backport from mainline 208120
-+ 2014-02-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/ld-vsx.c: Don't use vec_all_eq.
-+ * gcc.dg/vmx/ld-vsx-be-order.c: Likewise.
-+ * gcc.dg/vmx/ldl-vsx.c: Likewise.
-+ * gcc.dg/vmx/ldl-vsx-be-order.c: Likewise.
-+ * gcc.dg/vmx/merge-vsx.c: Likewise.
-+ * gcc.dg/vmx/merge-vsx-be-order.c: Likewise.
-+
-+ Backport from mainline 208321
-+ 2014-03-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/extract-vsx.c: Replace "vector long" with "vector
-+ long long" throughout.
-+ * gcc.dg/vmx/extract-vsx-be-order.c: Likewise.
-+ * gcc.dg/vmx/insert-vsx.c: Likewise.
-+ * gcc.dg/vmx/insert-vsx-be-order.c: Likewise.
-+ * gcc.dg/vmx/ld-vsx.c: Likewise.
-+ * gcc.dg/vmx/ld-vsx-be-order.c: Likewise.
-+ * gcc.dg/vmx/ldl-vsx.c: Likewise.
-+ * gcc.dg/vmx/ldl-vsx-be-order.c: Likewise.
-+ * gcc.dg/vmx/merge-vsx.c: Likewise.
-+ * gcc.dg/vmx/merge-vsx-be-order.c: Likewise.
-+ * gcc.dg/vmx/st-vsx.c: Likewise.
-+ * gcc.dg/vmx/st-vsx-be-order.c: Likewise.
-+ * gcc.dg/vmx/stl-vsx.c: Likewise.
-+ * gcc.dg/vmx/stl-vsx-be-order.c: Likewise.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Back port from mainline
-+ 2014-01-23 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/59909
-+ * gcc.target/powerpc/quad-atomic.c: New file to test power8 quad
-+ word atomic functions at runtime.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-10-23 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * gcc.target/powerpc/direct-move.h: Fix header for executable tests.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-04-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ PR target/56843
-+ * gcc.target/powerpc/recip-1.c: Modify expected output.
-+ * gcc.target/powerpc/recip-3.c: Likewise.
-+ * gcc.target/powerpc/recip-4.c: Likewise.
-+ * gcc.target/powerpc/recip-5.c: Add expected output for iterations.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-08-19 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * gcc.target/powerpc/dfp-dd-2.c: New test.
-+ * gcc.target/powerpc/dfp-td-2.c: Likewise.
-+ * gcc.target/powerpc/dfp-td-3.c: Likewise.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ ELFv2 ABI Support
-+ Backport from mainline r204808:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * gcc.target/powerpc/ppc64-abi-1.c (stack_frame_t): Remove
-+ compiler and linker field if _CALL_ELF == 2.
-+ * gcc.target/powerpc/ppc64-abi-2.c (stack_frame_t): Likewise.
-+ * gcc.target/powerpc/ppc64-abi-dfp-1.c (stack_frame_t): Likewise.
-+ * gcc.dg/stack-usage-1.c (SIZE): Update value for _CALL_ELF == 2.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * gcc.target/powerpc/ppc64-abi-dfp-1.c (FUNC_START): New macro.
-+ (WRAPPER): Use it.
-+ * gcc.target/powerpc/no-r11-1.c: Skip on powerpc_elfv2.
-+ * gcc.target/powerpc/no-r11-2.c: Skip on powerpc_elfv2.
-+ * gcc.target/powerpc/no-r11-3.c: Skip on powerpc_elfv2.
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * lib/target-supports.exp (check_effective_target_powerpc_elfv2):
-+ New function.
-+ * gcc.target/powerpc/pr57949-1.c: Disable for powerpc_elfv2.
-+ * gcc.target/powerpc/pr57949-2.c: Likewise.
-+
-+ Backport from mainline r204799:
-+
-+ 2013-11-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * g++.dg/eh/ppc64-sighandle-cr.C: New test.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline r201750.
-+ Note: Default setting of -mcompat-align-parm inverted!
-+
-+ 2013-08-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ PR target/57949
-+ * gcc.target/powerpc/pr57949-1.c: New.
-+ * gcc.target/powerpc/pr57949-2.c: New.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Little Endian Vector Support
-+ Backport from mainline r205638
-+ 2013-12-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c: Skip for little
-+ endian.
-+
-+ Backport from mainline r205146
-+ 2013-11-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/pr48258-1.c: Skip for little endian.
-+
-+ Backport from mainline r204862
-+ 2013-11-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/3b-15.c: Revise for little endian.
-+
-+ Backport from mainline r204321
-+ 2013-11-02 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
-+
-+ * gcc.dg/vmx/vec-set.c: New.
-+
-+ Backport from mainline r204138
-+ 2013-10-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.dg/vmx/gcc-bug-i.c: Add little endian variant.
-+ * gcc.dg/vmx/eg-5.c: Likewise.
-+
-+ Backport from mainline r203930
-+ 2013-10-22 Bill Schmidt <wschmidt@vnet.ibm.com>
-+
-+ * gcc.target/powerpc/altivec-perm-1.c: Move the two vector pack
-+ tests into...
-+ * gcc.target/powerpc/altivec-perm-3.c: ...this new test, which is
-+ restricted to big-endian targets.
-+
-+ Backport from mainline r203246
-+ 2013-10-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/pr43154.c: Skip for ppc64 little endian.
-+ * gcc.target/powerpc/fusion.c: Likewise.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-27 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * gfortran.dg/nan_7.f90: Disable for little endian PowerPC.
-+
-+ Backport from mainline r205106:
-+
-+ 2013-11-20 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * gcc.target/powerpc/darwin-longlong.c (msw): Make endian-safe.
-+
-+ Backport from mainline r205046:
-+
-+ 2013-11-19 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * gcc.target/powerpc/ppc64-abi-2.c (MAKE_SLOT): New macro to
-+ construct parameter slot value in endian-independent way.
-+ (fcevv, fciievv, fcvevv): Use it.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Power8 HTM Support
-+ Backport from mainline
-+ * lib/target-supports.exp (check_effective_target_powerpc_htm_ok): New
-+ function to test if HTM is available.
-+ * gcc.target/powerpc/htm-xl-intrin-1.c: New test.
-+ * gcc.target/powerpc/htm-builtin-1.c: New test.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Power8 Base Support
-+ Backport from mainline
-+ 2013-11-22 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/59054
-+ * gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to
-+ specify an appropriate register class for VSX operations.
-+ (load_vsx): Use it.
-+ (load_gpr_to_vsx): Likewise.
-+ (load_vsx_to_gpr): Likewise.
-+ * gcc.target/powerpc/direct-move-vint1.c: Use an appropriate
-+ register class for VSX registers that the type can handle. Remove
-+ checks for explicit number of instructions generated, just check
-+ if the instruction is generated.
-+ * gcc.target/powerpc/direct-move-vint2.c: Likewise.
-+ * gcc.target/powerpc/direct-move-float1.c: Likewise.
-+ * gcc.target/powerpc/direct-move-float2.c: Likewise.
-+ * gcc.target/powerpc/direct-move-double1.c: Likewise.
-+ * gcc.target/powerpc/direct-move-double2.c: Likewise.
-+ * gcc.target/powerpc/direct-move-long1.c: Likewise.
-+ * gcc.target/powerpc/direct-move-long2.c: Likewise.
-+
-+ * gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now.
-+ * gcc.target/powerpc/bool3-p7.c: Likewise.
-+ * gcc.target/powerpc/bool3-p8.c: Likewise.
-+
-+ * gcc.target/powerpc/p8vector-ldst.c: Just check that the
-+ appropriate instructions are generated, don't check the count.
-+
-+ 2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/59054
-+ * gcc.target/powerpc/pr59054.c: New test.
-+
-+ 2013-08-22 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/pr57744.c: Declare abort.
-+
-+ 2013-07-18 Pat Haugen <pthaugen@us.ibm.com>
-+
-+ * gcc.target/powerpc/pr57744.c: Fix typo.
-+
-+ Back port from mainline
-+ 2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/p8vector-fp.c: New test for floating point
-+ scalar operations when using -mupper-regs-sf and -mupper-regs-df.
-+ * gcc.target/powerpc/ppc-target-1.c: Update tests to allow either
-+ VSX scalar operations or the traditional floating point form of
-+ the instruction.
-+ * gcc.target/powerpc/ppc-target-2.c: Likewise.
-+ * gcc.target/powerpc/recip-3.c: Likewise.
-+ * gcc.target/powerpc/recip-5.c: Likewise.
-+ * gcc.target/powerpc/pr72747.c: Likewise.
-+ * gcc.target/powerpc/vsx-builtin-3.c: Likewise.
-+
-+ Back port from mainline
-+ 2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf
-+ and -mupper-regs-df.
-+
-+ Back port from mainline
-+ 2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/58673
-+ * gcc.target/powerpc/pr58673-1.c: New file to test whether
-+ -mquad-word + -mno-vsx-timode causes errors.
-+ * gcc.target/powerpc/pr58673-2.c: Likewise.
-+
-+
-+ Backport from trunk.
-+ 2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/bool2.h: New file, test the code generation
-+ of logical operations for power5, altivec, power7, and power8 systems.
-+ * gcc.target/powerpc/bool2-p5.c: Likewise.
-+ * gcc.target/powerpc/bool2-av.c: Likewise.
-+ * gcc.target/powerpc/bool2-p7.c: Likewise.
-+ * gcc.target/powerpc/bool2-p8.c: Likewise.
-+ * gcc.target/powerpc/bool3.h: Likewise.
-+ * gcc.target/powerpc/bool3-av.c: Likewise.
-+ * gcc.target/powerpc/bool2-p7.c: Likewise.
-+ * gcc.target/powerpc/bool2-p8.c: Likewise.
-+
-+ Backport from trunk.
-+ 2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/fusion.c: New file, test power8 fusion support.
-+
-+ Back port from the trunk
-+ 2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ PR target/57744
-+ * gcc.target/powerpc/pr57744.c: New test to make sure lqarx and
-+ stqcx. get even registers.
-+
-+ Back port from the trunk
-+
-+ 2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic
-+ load/store instructions on power7, power8.
-+ * gcc.target/powerpc/atomic-p8.c: Likewise.
-+
-+ Back port from the trunk
-+
-+ 2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * gcc.target/powerpc/direct-move-vint1.c: New tests for power8
-+ direct move instructions.
-+ * gcc.target/powerpc/direct-move-vint2.c: Likewise.
-+ * gcc.target/powerpc/direct-move.h: Likewise.
-+ * gcc.target/powerpc/direct-move-float1.c: Likewise.
-+ * gcc.target/powerpc/direct-move-float2.c: Likewise.
-+ * gcc.target/powerpc/direct-move-double1.c: Likewise.
-+ * gcc.target/powerpc/direct-move-double2.c: Likewise.
-+ * gcc.target/powerpc/direct-move-long1.c: Likewise.
-+ * gcc.target/powerpc/direct-move-long2.c: Likewise.
-+
-+ Backport from the trunk
-+
-+ 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * gcc.target/powerpc/p8vector-builtin-1.c: New test to test
-+ power8 builtin functions.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c: Likewise.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c: Likewise.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c: Likewise.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c: Likewise.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c: Likewise.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c: Likewise.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c: New
-+ tests to test power8 auto-vectorization.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c: Likewise.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c: Likewise.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c: Likewise.
-+ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c: Likewise.
-+
-+ * gcc.target/powerpc/crypto-builtin-1.c: Use effective target
-+ powerpc_p8vector_ok instead of powerpc_vsx_ok.
-+
-+ * gcc.target/powerpc/bool.c: New file, add eqv, nand, nor tests.
-+
-+ * lib/target-supports.exp (check_p8vector_hw_available) Add power8
-+ support.
-+ (check_effective_target_powerpc_p8vector_ok): Likewise.
-+ (is-effective-target): Likewise.
-+ (check_vect_support_and_set_flags): Likewise.
-+
-+ Backport from trunk
-+
-+ 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>
-+ Pat Haugen <pthaugen@us.ibm.com>
-+ Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8
-+ crypto builtins.
-+
-+ Backport from mainline
-+ 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
-+
-+ * gcc.target/powerpc/mmfpgpr.c: New test.
-+ * gcc.target/powerpc/sd-vsx.c: Likewise.
-+ * gcc.target/powerpc/sd-pwr6.c: Likewise.
-+ * gcc.target/powerpc/vsx-float0.c: Likewise.
-+
-+2014-04-01 Dominique d'Humieres <dominiq@lps.ens.fr>
-+
-+ PR libfortran/60128
-+ * gfortran.dg/fmt_en.f90: Skip unsupported rounding tests.
-+ XFAIL for i?86-*-solaris2.9* and hppa*-*-hpux*.
-+
-+2014-03-31 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2014-03-31 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR rtl-optimization/60700
-+ * gcc.target/i386/pr60700.c: New test.
-+
-+2014-03-28 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR rtl-optimization/60700
-+ Backport from mainline
-+ 2013-07-30 Zhenqiang Chen <zhenqiang.chen@linaro.org>
-+
-+ * gcc.target/arm/pr57637.c: New testcase.
-+
-+2014-04-28 Thomas Koenig <tkoenig@gcc.gnu.org>
-+
-+ PR fortran/60522
-+ * gfortran.dg/where_4.f90: New test case.
-+
-+2014-03-26 Martin Jambor <mjambor@suse.cz>
-+
-+ PR ipa/60419
-+ * g++.dg/ipa/pr60419.C: New test.
-+
-+2014-03-26 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * gcc.c-torture/execute/20140326-1.c: New test.
-+
-+2014-03-20 Tobias Burnus <burnus@net-b.de>
-+
-+ PR fortran/60543
-+ PR fortran/60283
-+ * gfortran.dg/implicit_pure_4.f90: New.
-+
-+2014-03-17 Mikael Pettersson <mikpelinux@gmail.com>
-+ Committed by Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline:
-+
-+ 2013-06-16 Joern Rennecke <joern.rennecke@embecosm.com>
-+
-+ PR rtl-optimization/57425
-+ PR rtl-optimization/57569
-+ * gcc.dg/torture/pr57425-1.c, gcc.dg/torture/pr57425-2.c: New files.
-+ * gcc.dg/torture/pr57425-3.c, gcc.dg/torture/pr57569.c: Likewise.
-+
-+2014-03-17 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-03-11 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60429
-+ PR tree-optimization/60485
-+ * gcc.dg/pr60485-1.c: New testcase.
-+ * gcc.dg/pr60485-2.c: Likewise.
-+
-+2014-03-15 Dominique d'Humieres <dominiq@lps.ens.fr>
-+
-+ Backport from mainline
-+ PR libfortran/60128
-+ * gfortran.dg/fmt_en.f90: New test.
-+
-+2014-03-15 Jerry DeLisle <jvdelisle@gcc.gnu>
-+
-+ Backport from mainline
-+ PR libfortran/58324
-+ * gfortran.dg/list_read_12.f90: New test.
-+
-+2014-03-13 Joey Ye <joey.ye@arm.com>
-+
-+ Backport from mainline
-+ 2014-03-12 Thomas Preud'homme <thomas.preudhomme@arm.com>
-+
-+ PR tree-optimization/60454
-+ * gcc.c-torture/execute/pr60454.c: New test.
-+
-+2014-03-08 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/60450
-+ * gfortran.dg/shape_8.f90: New.
-+
-+2014-03-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-02-19 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c/37743
-+ * g++.dg/ext/builtin-bswap1.C: New test.
-+ * c-c++-common/pr37743.c: New test.
-+
-+ PR preprocessor/58844
-+ * c-c++-common/cpp/pr58844-1.c: New test.
-+ * c-c++-common/cpp/pr58844-2.c: New test.
-+
-+ 2014-02-13 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/43546
-+ * gcc.target/i386/pr43546.c: New test.
-+
-+ 2014-02-12 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c/60101
-+ * c-c++-common/pr60101.c: New test.
-+
-+ 2014-02-11 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR fortran/52370
-+ * gfortran.dg/pr52370.f90: New test.
-+
-+ PR debug/59776
-+ * gcc.dg/guality/pr59776.c: New test.
-+
-+ 2014-02-07 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR preprocessor/56824
-+ * gcc.dg/pr56824.c: New test.
-+
-+ 2014-02-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/60062
-+ * gcc.c-torture/execute/pr60062.c: New test.
-+ * gcc.c-torture/execute/pr60072.c: New test.
-+
-+ 2014-02-04 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR ipa/60026
-+ * c-c++-common/torture/pr60026.c: New test.
-+
-+ 2014-02-05 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/57499
-+ * g++.dg/torture/pr57499.C: New test.
-+
-+ 2014-03-03 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR preprocessor/60400
-+ * c-c++-common/cpp/pr60400.c: New test.
-+ * c-c++-common/cpp/pr60400-1.h: New file.
-+ * c-c++-common/cpp/pr60400-2.h: New file.
-+
-+2014-03-04 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60382
-+ * gcc.dg/vect/pr60382.c: New testcase.
-+
-+2014-03-02 Mikael Morin <mikael@gcc.gnu.org>
-+
-+ PR fortran/60341
-+ * gfortran.dg/str_comp_optimize_1.f90: New test.
-+
-+2014-02-25 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-02-21 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60276
-+ * gcc.dg/vect/pr60276.c: New testcase.
-+
-+2014-02-25 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-02-14 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60183
-+ * gcc.dg/torture/pr60183.c: New testcase.
-+
-+2014-02-24 Fabien Chêne <fabien@gcc.gnu.org>
-+
-+ PR c++/37140
-+ * g++.dg/template/using27.C: New.
-+ * g++.dg/template/using28.C: New.
-+ * g++.dg/template/using29.C: New.
-+
-+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ * gcc/testsuite/gcc.target/microblaze/others/mem_reload.c: New test.
-+
-+2014-02-22 Mikael Morin <mikael@gcc.gnu.org>
-+
-+ PR fortran/59599
-+ * gfortran.dg/ichar_3.f90: New test.
-+
-+2014-02-21 Steven G. Kargl <kargl@gcc.gnu.org>
-+
-+ Backport from mainline
-+ PR fortran/59700
-+ * gfortran.dg/pr59700.f90: New test.
-+
-+2014-02-21 Martin Jambor <mjambor@suse.cz>
-+
-+ PR ipa/55260
-+ * gcc.dg/ipa/pr55260.c: New test.
-+
-+2014-02-19 Tobias Burnus <burnus@net-b.de>
-+
-+ PR fortran/49397
-+ * gfortran.dg/proc_ptr_45.f90: New.
-+ * gfortran.dg/proc_ptr_46.f90: New.
-+
-+2014-02-19 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-02-19 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59794
-+ * gcc.target/i386/pr39162.c: Add dg-prune-output.
-+ (dg-options): Remove -Wno-psabi.
-+ * gcc.target/i386/pr59794-2.c: Ditto.
-+ * gcc.target/i386/sse-5.c: Ditto.
-+
-+2014-02-19 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backports from mainline:
-+ 2014-02-17 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/55907
-+ * gfortran.dg/init_flag_12.f90: New.
-+
-+ 2014-02-18 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/60231
-+ * gfortran.dg/typebound_generic_15.f90: New.
-+
-+2014-02-18 Kai Tietz <ktietz@redhat.com>
-+
-+ PR target/60193
-+ * gcc.target/i386/nest-1.c: New testcase.
-+
-+2014-02-18 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * gnat.dg/opt32.adb: New test.
-+
-+2014-02-15 Jerry DeLisle <jvdelisle@gcc.gnu>
-+ Dominique d'Humieres <dominiq@lps.ens.fr>
-+
-+ Backport from mainline
-+ PR libfortran/59771
-+ PR libfortran/59774
-+ PR libfortran/59836
-+ * gfortran.dg/fmt_g_1.f90: New test.
-+ * gfortran.dg/round_3.f08: New cases added.
-+
-+2014-02-13 Dominik Vogt <vogt@linux.vnet.ibm.com>
-+
-+ * gcc.target/s390/hotpatch-compile-8.c: New test.
-+
-+2014-02-12 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * gcc.c-torture/execute/20140212-1.c: New test.
-+
-+2014-02-10 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2014-01-30 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59903
-+ * gcc.dg/torture/pr59903.c: New testcase.
-+
-+ 2014-02-10 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/60115
-+ * gcc.dg/torture/pr60115.c: New testcase.
-+
-+2014-02-09 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-10-21 Tobias Burnus <burnus@net-b.de>
-+
-+ PR fortran/58803
-+ PR fortran/59395
-+ * gfortran.dg/proc_ptr_comp_38.f90: New.
-+
-+2014-02-08 Mikael Morin <mikael@gcc.gnu.org>
-+
-+ PR fortran/57033
-+ * gfortran.dg/default_initialization_7.f90: New test.
-+
-+2014-02-07 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/59906
-+ * gfortran.dg/elemental_subroutine_9.f90 : New test
-+
-+2014-02-04 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2014-02-02 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/60017
-+ * gcc.c-torture/execute/pr60017.c: New test.
-+
-+2014-02-01 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/59414
-+ * gfortran.dg/allocate_class_3.f90 : New test
-+
-+2014-01-30 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ Backport from mainline.
-+ * gcc.target/microblaze/isa/fcmp4.c: New.
-+
-+2014-01-26 Mikael Morin <mikael@gcc.gnu.org>
-+
-+ PR fortran/58007
-+ * gfortran.dg/unresolved_fixup_1.f90: New test.
-+ * gfortran.dg/unresolved_fixup_2.f90: New test.
-+
-+2014-01-24 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline.
-+ 2014-01-23 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59929
-+ * gcc.target/i386/pr59929.c: New test.
-+
-+2014-01-24 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR c++/57524
-+ * g++.dg/ext/timevar2.C: New.
-+
-+2014-01-23 David Holsgrove <david.holsgrove@xilinx.com>
-+
-+ Backport from mainline.
-+ * gcc.target/microblaze/others/builtin-trap.c: New test.
-+
-+2014-01-23 Marek Polacek <polacek@redhat.com>
-+
-+ Backport from mainline
-+ 2013-10-21 Marek Polacek <polacek@redhat.com>
-+
-+ PR middle-end/58809
-+ * gcc.dg/gomp/pr58809.c: New test.
-+
-+2014-01-23 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/58809
-+ * c-c++-common/gomp/pr58809.c: New test.
-+
-+2014-01-22 Marek Polacek <polacek@redhat.com>
-+
-+ Backport from mainline
-+ 2014-01-22 Marek Polacek <polacek@redhat.com>
-+
-+ PR c/59891
-+ * gcc.dg/torture/pr59891.c: New test.
-+
-+2014-01-21 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/59860
-+ * gcc.dg/strlenopt-4.c: Expect the same counts on s390*-* as on all
-+ other targets.
-+
-+2014-01-20 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/59860
-+ * gcc.dg/pr59860.c: New testcase.
-+
-+2014-01-20 Marek Polacek <polacek@redhat.com>
-+
-+ Backported from mainline
-+ 2014-01-17 Marek Polacek <polacek@redhat.com>
-+
-+ PR c++/59838
-+ * g++.dg/diagnostic/pr59838.C: New test.
-+
-+2014-01-19 Paul Thomas <pault@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-12-01 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/34547
-+ * gfortran.dg/null_5.f90 : Include new error.
-+ * gfortran.dg/null_6.f90 : Include new error.
-+
-+2014-01-17 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2014-01-15 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59794
-+ * c-c++-common/convert-vec-1.c: Also prune ABI change for
-+ Linux/x86.
-+ * g++.dg/cpp0x/constexpr-53094-2.C: Likewise.
-+ * g++.dg/ext/attribute-test-1.C: Likewise.
-+ * g++.dg/ext/attribute-test-2.C: Likewise.
-+ * g++.dg/ext/attribute-test-3.C: Likewise.
-+ * g++.dg/ext/attribute-test-4.C: Likewise.
-+ * g++.dg/torture/pr38565.C: Likewise.
-+ * gcc.dg/pr53060.c: Likewise.
-+ * c-c++-common/scal-to-vec2.c: Add -msse2 for x86.
-+ * c-c++-common/vector-compare-2.c: Likewise.
-+ * gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c: Likewise.
-+ * g++.dg/conversion/simd1.C: Add -msse2 for x86. Adjust
-+ dg-message line number.
-+
-+2014-01-17 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2014-01-14 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59794
-+ * gcc.target/i386/pr39162.c (y): New __m256i variable.
-+ (bar): Change return type to void. Set y to x.
-+ * gcc.target/i386/pr59794-1.c: New testcase.
-+ * gcc.target/i386/pr59794-2.c: Likewise.
-+ * gcc.target/i386/pr59794-3.c: Likewise.
-+ * gcc.target/i386/pr59794-4.c: Likewise.
-+ * gcc.target/i386/pr59794-5.c: Likewise.
-+ * gcc.target/i386/pr59794-6.c: Likewise.
-+ * gcc.target/i386/pr59794-7.c: Likewise.
-+
-+2014-01-17 Matthias Klose <doko@ubuntu.com>
-+
-+ Backport from the trunk:
-+ 2014-01-09 Uros Bizjak <ubizjak@gmail.com>
-+ * go.test/go-test.exp (go-gc-tests): Don't run peano.go on systems
-+ which don't support -fsplit-stack. Skip rotate[0123].go tests.
-+
-+2014-01-15 Kugan Vivekanandarajah <kuganv@linaro.org>
-+
-+ Backport from mainline
-+ 2014-01-15 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org>
-+ Kugan Vivekanandarajah <kuganv@linaro.org>
-+
-+ PR target/59695
-+ * g++.dg/pr59695.C: New testcase.
-+
-+2014-01-17 Terry Guo <terry.guo@arm.com>
-+
-+ * gcc.target/arm/pr59826.c: New test.
-+
-+2014-01-16 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/59839
-+ * gcc.target/i386/pr59839.c: New test.
-+
-+ PR debug/54694
-+ * gcc.target/i386/pr9771-1.c (main): Rename to...
-+ (real_main): ... this. Add __asm name "main".
-+ (ASMNAME, ASMNAME2, STRING): Define.
-+
-+2014-01-16 Marek Polacek <polacek@redhat.com>
-+
-+ Backported from mainline
-+ 2014-01-16 Marek Polacek <polacek@redhat.com>
-+
-+ PR middle-end/59827
-+ * gcc.dg/pr59827.c: New test.
-+
-+2014-01-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ PR target/59803
-+ * gcc.c-torture/compile/pr59803.c: New testcase.
-+
-+2014-01-10 Yufeng Zhang <yufeng.zhang@arm.com>
-+
-+ * gcc.target/arm/neon/vst1Q_laneu64-1.c: New test.
-+
-+2014-01-10 Hans-Peter Nilsson <hp@axis.com>
-+
-+ * gcc.dg/pr46309.c: Disable for cris*-*-*.
-+
-+2014-01-10 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR c++/56060
-+ PR c++/59730
-+ * g++.dg/cpp0x/variadic144.C: New.
-+ * g++.dg/cpp0x/variadic145.C: Likewise.
-+
-+2014-01-10 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59715
-+ * gcc.dg/torture/pr59715.c: New testcase.
-+
-+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ * gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c,
-+ gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c,
-+ gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests.
-+
-+2014-01-09 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ PR rtl-optimization/59137
-+ * gcc.target/mips/pr59137.c: New test.
-+
-+2014-01-09 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-18 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59125
-+ PR tree-optimization/54570
-+ * gcc.dg/builtin-object-size-8.c: Un-xfail.
-+ * gcc.dg/builtin-object-size-14.c: New testcase.
-+ * gcc.dg/strlenopt-14gf.c: Adjust.
-+ * gcc.dg/strlenopt-1f.c: Likewise.
-+ * gcc.dg/strlenopt-4gf.c: Likewise.
-+
-+ 2013-12-03 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59362
-+ * gcc.c-torture/compile/pr59362.c: New test.
-+
-+2014-01-09 Richard Earnshaw <rearnsha@arm.com>
-+
-+ PR rtl-optimization/54300
-+ * gcc.target/arm/pr54300.C: New test.
-+
-+2014-01-08 Martin Jambor <mjambor@suse.cz>
-+
-+ PR ipa/59610
-+ * gcc.dg/ipa/pr59610.c: New test.
-+
-+2014-01-07 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR rtl-optimization/58668
-+ * gcc.dg/pr58668.c: New test.
-+
-+ Backported from mainline
-+ 2013-12-16 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/58956
-+ PR middle-end/59470
-+ * gcc.target/i386/pr59470.c: New test.
-+
-+2014-01-04 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2014-01-02 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/59654
-+ * gfortran.dg/dynamic_dispatch_12.f90: New.
-+
-+2014-01-03 Joseph Myers <joseph@codesourcery.com>
-+
-+ * gcc.target/powerpc/rs6000-ldouble-3.c: New test.
-+
-+2014-01-03 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/59625
-+ * gcc.target/i386/pr59625.c: New test.
-+
-+2014-01-01 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR rtl-optimization/59647
-+ * g++.dg/opt/pr59647.C: New test.
-+
-+2013-12-31 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-12-30 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/58998
-+ * gfortran.dg/generic_28.f90: New.
-+
-+2013-12-20 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c++/59255
-+ * g++.dg/tree-prof/pr59255.C: New test.
-+
-+2013-12-19 James Greenhalgh <james.greenhalgh@arm.com>
-+
-+ Backport from Mainline
-+ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>
-+
-+ * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New.
-+ (test_vceqd_s64): Force arguments to SIMD registers.
-+ (test_vceqzd_s64): Likewise.
-+ (test_vcged_s64): Likewise.
-+ (test_vcled_s64): Likewise.
-+ (test_vcgezd_s64): Likewise.
-+ (test_vcged_u64): Likewise.
-+ (test_vcgtd_s64): Likewise.
-+ (test_vcltd_s64): Likewise.
-+ (test_vcgtzd_s64): Likewise.
-+ (test_vcgtd_u64): Likewise.
-+ (test_vclezd_s64): Likewise.
-+ (test_vcltzd_s64): Likewise.
-+ (test_vtst_s64): Likewise.
-+ (test_vtst_u64): Likewise.
-+
-+2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>
-+ Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-+
-+ Backport from mainline
-+ 2013-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>
-+ * gcc/testsuite/gcc.target/s390/hotpatch-1.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-2.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-3.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-4.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-5.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-6.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-7.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-8.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-9.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-10.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-11.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-12.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c: New test
-+ * gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c: New test
-+
-+2013-12-18 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-12-15 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/59493
-+ * gfortran.dg/unlimited_polymorphic_15.f90: New.
-+
-+2013-12-15 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR testsuite/58630
-+ * gcc.target/i386/pr43662.c (dg-options):
-+ Add -maccumulate-outgoing-args.
-+ * gcc.target/i386/pr43869.c (dg-options): Ditto.
-+ * gcc.target/i386/pr57003.c (dg-options): Ditto.
-+ * gcc.target/i386/avx-vzeroupper-16.c (dg-options):
-+ Remove -mtune=generic and add -maccumulate-outgoing-args instead.
-+ * gcc.target/i386/avx-vzeroupper-17.c (dg-options): Ditto.
-+ * gcc.target/i386/avx-vzeroupper-18.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/func-1.c (dg-options):
-+ Add -maccumulate-outgoing-args.
-+ * gcc.target/x86_64/abi/callabi/func-2a.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/func-2b.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/func-indirect.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/func-indirect-2a.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/func-indirect-2b.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/leaf-1.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/leaf-2.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/pr38891.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/vaarg-1.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/vaarg-2.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/vaarg-3.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/vaarg-4a.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/vaarg-4b.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/vaarg-5a.c (dg-options): Ditto.
-+ * gcc.target/x86_64/abi/callabi/vaarg-5b.c (dg-options): Ditto.
-+
-+2013-12-12 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/59470
-+ * g++.dg/opt/pr59470.C: New test.
-+
-+ PR libgomp/59467
-+ * gfortran.dg/gomp/pr59467.f90: New test.
-+ * c-c++-common/gomp/pr59467.c: New test.
-+
-+2013-12-12 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-12-12 Ryan Mansfield <rmansfield@qnx.com>
-+
-+ PR testsuite/59442
-+ * gcc.target/i386/sse2-movapd-1.c: Fix alignment attributes.
-+ * gcc.target/i386/sse2-movapd-2.c: Likewise.
-+ * gcc.target/i386/avx-vmovapd-256-1.c: Likewise.
-+ * gcc.target/i386/avx-vmovapd-256-2.c: Likewise.
-+
-+2013-12-08 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-12-06 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59405
-+ * gcc.target/i386/pr59405.c: New test.
-+
-+2013-12-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59388
-+ * gcc.c-torture/execute/pr59388.c: New test.
-+
-+2013-12-06 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-28 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59330
-+ * gcc.dg/torture/pr59330.c: New testcase.
-+
-+2013-12-06 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-27 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59288
-+ * gcc.dg/torture/pr59288.c: New testcase.
-+
-+ 2013-11-19 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59164
-+ * gcc.dg/torture/pr59164.c: New testcase.
-+
-+ 2013-09-05 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/58137
-+ * gcc.target/i386/pr58137.c: New testcase.
-+
-+2013-12-06 Oleg Endo <olegendo@gcc.gnu.org>
-+
-+ PR target/51244
-+ PR target/59343
-+ * gcc.target/sh/pr51244-19.c: Adjust test case.
-+
-+2013-12-05 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-19 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/58956
-+ * gcc.dg/torture/pr58956.c: New testcase.
-+
-+2013-12-04 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c++/59268
-+ * g++.dg/cpp0x/constexpr-template6.C: New test.
-+
-+ PR rtl-optimization/58726
-+ * gcc.c-torture/execute/pr58726.c: New test.
-+
-+ PR target/59163
-+ * g++.dg/torture/pr59163.C: New test.
-+
-+2013-12-03 Marek Polacek <polacek@redhat.com>
-+
-+ Backport from mainline
-+ 2013-12-03 Marek Polacek <polacek@redhat.com>
-+
-+ PR c/59351
-+ * gcc.dg/pr59351.c: New test.
-+
-+2013-12-03 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/59011
-+ * gcc.dg/pr59011.c: New test.
-+
-+ PR target/58864
-+ * g++.dg/opt/pr58864.C: New test.
-+
-+2013-12-02 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59358
-+ * gcc.c-torture/execute/pr59358.c: New test.
-+
-+2013-12-02 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/59139
-+ * gcc.dg/torture/pr59139.c: New testcase.
-+
-+2013-11-27 Tom de Vries <tom@codesourcery.com>
-+ Marc Glisse <marc.glisse@inria.fr>
-+
-+ PR c++/59032
-+ * c-c++-common/pr59032.c: New testcase.
-+
-+2013-11-27 Tom de Vries <tom@codesourcery.com>
-+ Marc Glisse <marc.glisse@inria.fr>
-+
-+ PR middle-end/59037
-+ * c-c++-common/pr59037.c: New testcase.
-+
-+2013-11-30 Paul Thomas <pault@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-11-04 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/57445
-+ * gfortran.dg/optional_class_1.f90 : New test
-+
-+2013-11-29 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c/59280
-+ * c-c++-common/pr59280.c: New test.
-+
-+2013-11-28 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c++/59297
-+ * g++.dg/gomp/pr59297.C: New test.
-+
-+2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-+
-+ Backport from mainline
-+ 2013-11-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-+
-+ * gcc.target/arm/vrinta-ce.c: New testcase.
-+
-+2013-11-28 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-11-23 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/56788
-+ * config/i386/i386.c (bdesc_multi_arg) <IX86_BUILTIN_VFRCZSS>:
-+ Declare as MULTI_ARG_1_SF instruction.
-+ <IX86_BUILTIN_VFRCZSD>: Decleare as MULTI_ARG_1_DF instruction.
-+ * config/i386/sse.md (*xop_vmfrcz<mode>2): Rename
-+ from *xop_vmfrcz_<mode>.
-+ * config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss
-+ to merge scalar result with __A.
-+ (_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar
-+ result with __A.
-+
-+2013-11-28 Terry Guo <terry.guo@arm.com>
-+
-+ Backport mainline r205391
-+ 2013-11-26 Terry Guo <terry.guo@arm.com>
-+
-+ * gcc.target/arm/thumb1-pic-high-reg.c: New case.
-+ * gcc.target/arm/thumb1-pic-single-base.c: New case.
-+
-+2013-11-27 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backported from mainline
-+ 2013-11-27 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59014
-+ * gcc.c-torture/execute/pr59014-2.c: New test.
-+
-+ 2013-11-26 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/59014
-+ * gcc.c-torture/execute/pr59014.c: New test.
-+
-+2013-11-27 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * gcc.c-torture/execute/20131127-1.c: New test.
-+
-+2013-11-25 Vidya Praveen <vidyapraveen@arm.com>
-+
-+ Backport from mainline
-+ 2013-10-21 Vidya Praveen <vidyapraveen@arm.com>
-+
-+ * gcc.dg/20050922-1.c: Remove stdlib.h and declare abort().
-+ * gcc.dg/20050922-1.c: Remove stdlib.h and declare abort() and exit().
-+
-+2013-11-20 Dominik Vogt <vogt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ * gcc.target/s390/htm-1.c: Rename to ...
-+ * gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c: ... this
-+ one.
-+ * gcc.target/s390/htm-xl-intrin-1.c: Rename to ...
-+ * gcc.target/s390/htm-builtins-compile-3.c: ... this one.
-+ * gcc.target/s390/htm-builtins-compile-2.c: New testcase.
-+ * gcc.target/s390/htm-builtins-1.c: New testcase.
-+ * gcc.target/s390/htm-builtins-2.c: New testcase.
-+ * gcc.target/s390/s390.exp: Add check for htm machine.
-+
-+2013-11-19 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/57517
-+ * gfortran.fortran-torture/compile/pr57517.f90: New testcase.
-+ * gcc.dg/torture/pr57517.c: Likewise.
-+
-+2013-11-19 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-11-05 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/58941
-+ * gcc.dg/torture/pr58941.c: New testcase.
-+
-+2013-11-18 Richard Biener <rguenther@suse.de>
-+
-+ Backport from mainline
-+ 2013-10-21 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/58794
-+ * c-c++-common/torture/pr58794-1.c: New testcase.
-+ * c-c++-common/torture/pr58794-2.c: Likewise.
-+
-+ 2013-10-21 Richard Biener <rguenther@suse.de>
-+
-+ PR middle-end/58742
-+ * c-c++-common/fold-divmul-1.c: New testcase.
-+
-+ 2013-11-06 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/58653
-+ * gcc.dg/tree-ssa/predcom-6.c: New testcase.
-+ * gcc.dg/tree-ssa/predcom-7.c: Likewise.
-+
-+ PR tree-optimization/59047
-+ * gcc.dg/torture/pr59047.c: New testcase.
-+
-+ 2013-10-15 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/58143
-+ * gcc.dg/torture/pr58143-1.c: New testcase.
-+ * gcc.dg/torture/pr58143-2.c: Likewise.
-+ * gcc.dg/torture/pr58143-3.c: Likewise.
-+
-+2013-11-17 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-11-07 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/58471
-+ * gfortran.dg/constructor_9.f90: New.
-+
-+2013-11-16 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-09-20 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/58099
-+ * gfortran.dg/proc_ptr_43.f90: New.
-+
-+2013-11-16 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/58771
-+ * gfortran.dg/derived_external_function_1.f90 : New test
-+
-+2013-11-14 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-11-06 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/59021
-+ * gcc.target/i386/pr59021.c: New test.
-+
-+2013-11-14 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR target/59101
-+ * gcc.c-torture/execute/pr59101.c: New test.
-+
-+2013-11-11 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backported from mainline
-+ 2013-11-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/58970
-+ * gcc.c-torture/compile/pr58970-1.c: New test.
-+ * gcc.c-torture/compile/pr58970-2.c: New test.
-+
-+ 2013-11-05 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR rtl-optimization/58997
-+ * gcc.c-torture/compile/pr58997.c: New test.
-+
-+2013-11-10 Wei Mi <wmi@google.com>
-+
-+ * gcc.dg/pr57518.c: Backport regex fix from r200720.
-+
-+2013-11-07 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2013-11-07 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/59034
-+ * gcc.target/i386/pr59034-1.c: New test.
-+ * gcc.target/i386/pr59034-2.c: Likewise.
-+
-+2013-11-06 Wei Mi <wmi@google.com>
-+
-+ PR regression/58985
-+ * gcc.dg/pr57518.c: Add subreg in regexp pattern.
-+
-+2013-11-05 Steven G. Kargl <kargl@gcc.gnu.org>
-+
-+ PR fortran/58989
-+ * gfortran.dg/reshape_6.f90: New test.
-+
-+2013-11-05 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR tree-optimization/58984
-+ * gcc.c-torture/execute/pr58984.c: New test.
-+
-+2013-11-04 Marek Polacek <polacek@redhat.com>
-+
-+ Backport from mainline
-+ 2013-11-04 Marek Polacek <polacek@redhat.com>
-+
-+ PR c++/58979
-+ * g++.dg/diagnostic/pr58979.C: New test.
-+
-+2013-11-03 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ Backport from mainline
-+ 2013-10-12 H.J. Lu <hongjiu.lu@intel.com>
-+
-+ PR target/58690
-+ * gcc.target/i386/pr58690.c: New test
-+
-+2013-11-02 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-09-23 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/58355
-+ * gfortran.dg/extends_15.f90: New.
-+
-+2013-10-29 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-08-08 Richard Sandiford <rdsandiford@googlemail.com>
-+
-+ PR rtl-optimization/58079
-+ * gcc.dg/torture/pr58079.c: New test.
-+
-+2013-10-28 Tom de Vries <tom@codesourcery.com>
-+
-+ * gcc.target/arm/require-pic-register-loc.c: New test.
-+
-+2013-10-26 Uros Bizjak <ubizjak@gmail.com>
-+
-+ Backport from mainline
-+ 2013-10-22 Uros Bizjak <ubizjak@gmail.com>
-+
-+ PR target/58779
-+ * gcc.target/i386/pr30315.c: Remove MINUSCC, DECCC, MINUSCCONLY
-+ and MINUSCCZEXT defines. Update scan-assembler dg directive.
-+ * gcc.dg/torture/pr58779.c: New test.
-+
-+2013-10-25 Richard Henderson <rth@redhat.com>
-+
-+ PR rtl/58542
-+ * gcc.dg/atomic-store-6.c: New.
-+
-+2013-10-25 Tom de Vries <tom@codesourcery.com>
-+
-+ PR c++/58282
-+ * g++.dg/tm/noexcept-6.C: New test.
-+
-+2013-10-25 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * gcc.c-torture/execute/pr58831.c: New test.
-+
-+2013-10-23 Tom de Vries <tom@codesourcery.com>
-+
-+ PR tree-optimization/58805
-+ * gcc.dg/pr58805.c: New test.
-+
-+2013-10-23 Richard Biener <rguenther@suse.de>
-+
-+ * gcc.dg/torture/pr58830.c: New testcase.
-+
-+ Backport from mainline
-+ 2013-06-24 Richard Biener <rguenther@suse.de>
-+
-+ PR tree-optimization/57488
-+ * gcc.dg/torture/pr57488.c: New testcase.
-+
-+2013-10-19 Oleg Endo <olegendo@gcc.gnu.org>
-+
-+ * gcc.target/sh/pr54089-3.c: Fix test for load of constant 31.
-+
-+2013-10-17 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR c++/58596
-+ * g++.dg/cpp0x/lambda/lambda-nsdmi5.C: New
-+
-+2013-10-16 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR c++/58633
-+ * g++.dg/cpp0x/decltype57.C: New.
-+ * g++.dg/cpp0x/enum18.C: Revert r174385 changes.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-@@ -39,9 +1897,9 @@
- Backport from mainline
- 2013-06-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
-- * gcc.target/s390/htm-1.c: New file.
-- * gcc.target/s390/htm-nofloat-1.c: New file.
-- * gcc.target/s390/htm-xl-intrin-1.c: New file.
-+ * gcc.target/s390/htm-1.c: New file.
-+ * gcc.target/s390/htm-nofloat-1.c: New file.
-+ * gcc.target/s390/htm-xl-intrin-1.c: New file.
-
- 2013-10-04 Tobias Burnus <burnus@net-b.de>
-
-@@ -307,8 +2165,8 @@
- Backport from mainline
- 2013-08-12 Perez Read <netfirewall@gmail.com>
-
-- PR target/58132
-- * gcc.target/i386/movabs-1.c: New test.
-+ PR target/58132
-+ * gcc.target/i386/movabs-1.c: New test.
-
- 2013-08-11 Janus Weil <janus@gcc.gnu.org>
-
-@@ -494,7 +2352,7 @@
- 2013-06-19 Wei Mi <wmi@google.com>
-
- PR rtl-optimization/57518
-- * testsuite/gcc.dg/pr57518.c: New test.
-+ * gcc.dg/pr57518.c: New test.
-
- 2013-06-11 Tobias Burnus <burnus@net-b.de>
-
-@@ -623,8 +2481,8 @@
-
- 2013-05-09 Martin Jambor <mjambor@suse.cz>
-
-- PR middle-end/56988
-- * gcc.dg/ipa/pr56988.c: New test.
-+ PR middle-end/56988
-+ * gcc.dg/ipa/pr56988.c: New test.
-
- 2013-05-08 Marc Glisse <marc.glisse@inria.fr>
-
-@@ -701,7 +2559,7 @@
- 2013-04-25 Marek Polacek <polacek@redhat.com>
-
- PR tree-optimization/57066
-- * gcc.dg/torture/builtin-logb-1.c: Adjust testcase.
-+ * gcc.dg/torture/builtin-logb-1.c: Adjust testcase.
-
- 2013-05-02 Jakub Jelinek <jakub@redhat.com>
-
-@@ -727,8 +2585,8 @@
- Backport from mainline
- 2013-04-24 Vladimir Makarov <vmakarov@redhat.com>
-
-- PR rtl-optimizations/57046
-- * gcc.target/i386/pr57046.c: New test.
-+ PR rtl-optimizations/57046
-+ * gcc.target/i386/pr57046.c: New test.
-
- 2013-05-02 Vladimir Makarov <vmakarov@redhat.com>
-
-@@ -735,8 +2593,8 @@
- Backport from mainline
- 2013-04-22 Vladimir Makarov <vmakarov@redhat.com>
-
-- PR target/57018
-- * gcc.target/i386/pr57018.c: New test.
-+ PR target/57018
-+ * gcc.target/i386/pr57018.c: New test.
-
- 2013-05-02 Vladimir Makarov <vmakarov@redhat.com>
-
-@@ -743,8 +2601,8 @@
- Backport from mainline
- 2013-04-18 Jakub Jelinek <jakub@redhat.com>
-
-- PR rtl-optimization/56999
-- * g++.dg/opt/pr56999.C: New test.
-+ PR rtl-optimization/56999
-+ * g++.dg/opt/pr56999.C: New test.
-
- 2013-05-02 Vladimir Makarov <vmakarov@redhat.com>
-
-@@ -751,8 +2609,8 @@
- Backport from mainline
- 2013-04-19 Vladimir Makarov <vmakarov@redhat.com>
-
-- PR rtl-optimization/56847
-- * gcc.dg/pr56847.c: New test.
-+ PR rtl-optimization/56847
-+ * gcc.dg/pr56847.c: New test.
-
- 2013-05-02 Ian Bolton <ian.bolton@arm.com>
-
-@@ -1102,7 +2960,7 @@
- 2013-03-29 Tobias Burnus <burnus@net-b.de>
-
- PR fortran/56737
-- * testsuite/gfortran.dg/fmt_cache_3.f90: New.
-+ * gfortran.dg/fmt_cache_3.f90: New.
-
- 2013-04-02 Richard Biener <rguenther@suse.de>
-
-@@ -1636,7 +3494,7 @@
- 2013-02-20 Jan Hubicka <jh@suse.cz>
-
- PR tree-optimization/56265
-- * testsuite/g++.dg/ipa/devirt-11.C: New testcase.
-+ * g++.dg/ipa/devirt-11.C: New testcase.
-
- 2013-02-20 Richard Biener <rguenther@suse.de>
-
-@@ -1823,11 +3681,9 @@
-
- Avoid instrumenting duplicated memory access in the same basic block
- * c-c++-common/asan/no-redundant-instrumentation-1.c: New test.
-- * testsuite/c-c++-common/asan/no-redundant-instrumentation-2.c:
-- Likewise.
-- * testsuite/c-c++-common/asan/no-redundant-instrumentation-3.c:
-- Likewise.
-- * testsuite/c-c++-common/asan/inc.c: Likewise.
-+ * c-c++-common/asan/no-redundant-instrumentation-2.c: Likewise.
-+ * c-c++-common/asan/no-redundant-instrumentation-3.c: Likewise.
-+ * c-c++-common/asan/inc.c: Likewise.
-
- 2013-02-12 Vladimir Makarov <vmakarov@redhat.com>
-
-Index: gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90 (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+SUBROUTINE cal_helicity (uh, ph, phb, wavg, ims, ime, its, ite)
-+ INTEGER, INTENT( IN ) :: ims, ime, its, ite
-+ REAL, DIMENSION( ims:ime), INTENT( IN ) :: ph, phb, wavg
-+ REAL, DIMENSION( ims:ime), INTENT( INOUT ) :: uh
-+ INTEGER :: i
-+ REAL :: zu
-+ DO i = its, ite
-+ zu = (ph(i ) + phb(i)) + (ph(i-1) + phb(i-1))
-+ IF (wavg(i) .GT. 0) THEN
-+ uh(i) = uh(i) + zu
-+ ENDIF
-+ END DO
-+END SUBROUTINE cal_helicity
-Index: gcc/testsuite/g++.dg/ext/attribute-test-2.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/attribute-test-2.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-2.C (.../branches/gcc-4_8-branch)
-@@ -50,3 +50,4 @@
-
- /* Ignore a warning that is irrelevant to the purpose of this test. */
- /* { dg-prune-output ".*GCC vector returned by reference.*" } */
-+/* { dg-prune-output "changes the ABI" } */
-Index: gcc/testsuite/g++.dg/ext/attribute-test-3.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/attribute-test-3.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-3.C (.../branches/gcc-4_8-branch)
-@@ -52,3 +52,4 @@
-
- /* Ignore a warning that is irrelevant to the purpose of this test. */
- /* { dg-prune-output ".*GCC vector returned by reference.*" } */
-+/* { dg-prune-output "changes the ABI" } */
-Index: gcc/testsuite/g++.dg/ext/traits1.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/traits1.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/traits1.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,4 @@
-+// PR c++/58504
-+
-+template<bool = __has_nothrow_assign(void)> struct A {};
-+A<> a;
-Index: gcc/testsuite/g++.dg/ext/attribute-test-4.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/attribute-test-4.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-4.C (.../branches/gcc-4_8-branch)
-@@ -49,3 +49,4 @@
-
- /* Ignore a warning that is irrelevant to the purpose of this test. */
- /* { dg-prune-output ".*GCC vector returned by reference.*" } */
-+/* { dg-prune-output "changes the ABI" } */
-Index: gcc/testsuite/g++.dg/ext/stmtexpr15.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/stmtexpr15.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/stmtexpr15.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,7 @@
-+// PR c++/59097
-+// { dg-options "" }
-+
-+void foo()
-+{
-+ int x[({ return; })]; // { dg-error "non-integral" }
-+}
-Index: gcc/testsuite/g++.dg/ext/vector25.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/vector25.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/vector25.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,6 @@
-+volatile int i __attribute__((vector_size(8)));
-+
-+void foo()
-+{
-+ i += i;
-+}
-Index: gcc/testsuite/g++.dg/ext/builtin-bswap1.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/builtin-bswap1.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/builtin-bswap1.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+// PR c/37743
-+// { dg-do compile }
-+
-+#if defined(__UINT32_TYPE__) && defined(__INT32_TYPE__)
-+
-+void foo (__UINT32_TYPE__);
-+void foo (__INT32_TYPE__);
-+
-+void
-+bar (__UINT32_TYPE__ x)
-+{
-+ foo (__builtin_bswap32 (x));
-+}
-+
-+#else
-+
-+void
-+bar ()
-+{
-+}
-+
-+#endif
-Index: gcc/testsuite/g++.dg/ext/attrib48.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/attrib48.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/attrib48.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,6 @@
-+// PR c++/54652
-+
-+typedef unsigned L __attribute__ ((aligned));
-+typedef unsigned L __attribute__ ((aligned));
-+
-+L l;
-Index: gcc/testsuite/g++.dg/ext/vector27.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/vector27.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/vector27.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,7 @@
-+// PR c++/58845
-+
-+void foo()
-+{
-+ int v __attribute__((vector_size(8)));
-+ v = v || v; // { dg-bogus "" "" { xfail *-*-* } }
-+}
-Index: gcc/testsuite/g++.dg/ext/timevar2.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/timevar2.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/timevar2.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+// PR c++/57524
-+// { dg-options "-ftime-report" }
-+// { dg-prune-output "wall" }
-+// { dg-prune-output "times" }
-+// { dg-prune-output "TOTAL" }
-+// { dg-prune-output "checks" }
-+
-+namespace detail {
-+namespace indirect_traits {}
-+using namespace indirect_traits;
-+void fn1() {
-+using namespace detail;
-+}
-+}
-Index: gcc/testsuite/g++.dg/ext/attribute-test-1.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ext/attribute-test-1.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ext/attribute-test-1.C (.../branches/gcc-4_8-branch)
-@@ -36,3 +36,4 @@
-
- /* Ignore a warning that is irrelevant to the purpose of this test. */
- /* { dg-prune-output ".*GCC vector returned by reference.*" } */
-+/* { dg-prune-output "changes the ABI" } */
-Index: gcc/testsuite/g++.dg/vect/pr60836.cc
-===================================================================
---- a/src/gcc/testsuite/g++.dg/vect/pr60836.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/vect/pr60836.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,39 @@
-+// { dg-do compile }
-+
-+int a, b;
-+typedef double (*NormFunc) (const int &);
-+int &
-+max (int &p1, int &p2)
-+{
-+ if (p1 < p2)
-+ return p2;
-+ return p1;
-+}
-+
-+struct A
-+{
-+ int operator () (int p1, int p2)
-+ {
-+ return max (p1, p2);
-+ }
-+};
-+template < class, class > double
-+norm_ (const int &)
-+{
-+ char c, d;
-+ A e;
-+ for (; a; a++)
-+ {
-+ b = e (b, d);
-+ b = e (b, c);
-+ }
-+}
-+
-+void
-+norm ()
-+{
-+ static NormFunc f = norm_ < int, A >;
-+ f = 0;
-+}
-+
-+// { dg-final { cleanup-tree-dump "vect" } }
-Index: gcc/testsuite/g++.dg/vect/pr60729.cc
-===================================================================
---- a/src/gcc/testsuite/g++.dg/vect/pr60729.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/vect/pr60729.cc (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+// { dg-do compile }
-+// { dg-additional-options "-ftrapv" }
-+
-+void doSomething(int dim, double *Y, double *A)
-+{
-+ for (int k=0; k<dim; k++)
-+ Y[k] += __builtin_fabs (A[k]);
-+}
-+
-+// { dg-final { cleanup-tree-dump "vect" } }
-Index: gcc/testsuite/g++.dg/opt/pr60849.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/opt/pr60849.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/opt/pr60849.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+// { dg-do compile }
-+// { dg-options "-O2" }
-+
-+int g;
-+
-+extern "C" int isnan ();
-+
-+void foo(float a) {
-+ int (*xx)(...);
-+ xx = isnan;
-+ if (xx(a))
-+ g++;
-+}
-Index: gcc/testsuite/g++.dg/opt/pr59647.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/opt/pr59647.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/opt/pr59647.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,32 @@
-+// PR rtl-optimization/59647
-+// { dg-do compile }
-+// { dg-options "-O2 -fno-tree-vrp" }
-+// { dg-additional-options "-msse2 -mfpmath=sse" { target { { i?86-*-* x86_64-*-* } && ia32 } } }
-+
-+void f1 (int);
-+void f2 ();
-+double f3 (int);
-+
-+struct A
-+{
-+ int f4 () const
-+ {
-+ if (a == 0)
-+ return 1;
-+ return 0;
-+ }
-+ unsigned f5 ()
-+ {
-+ if (!f4 ())
-+ f2 ();
-+ return a;
-+ }
-+ int a;
-+};
-+
-+void
-+f6 (A *x)
-+{
-+ unsigned b = x->f5 ();
-+ f1 (b - 1 - f3 (x->f5 () - 1U));
-+}
-Index: gcc/testsuite/g++.dg/opt/pr59470.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/opt/pr59470.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/opt/pr59470.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,188 @@
-+// PR middle-end/59470
-+// { dg-do run }
-+// { dg-options "-O2 -fstack-protector" }
-+// { dg-additional-options "-fPIC" { target fpic } }
-+// { dg-require-effective-target fstack_protector }
-+
-+struct A
-+{
-+ int a1;
-+ A () throw () : a1 (0) {}
-+};
-+
-+struct B
-+{
-+ unsigned int b1 () throw ();
-+};
-+
-+__attribute__((noinline, noclone)) unsigned int
-+B::b1 () throw ()
-+{
-+ asm volatile ("" : : : "memory");
-+ return 0;
-+}
-+
-+struct C
-+{
-+ const A **c1;
-+ void c2 (const A *, unsigned int);
-+};
-+
-+__attribute__((noinline, noclone)) void
-+C::c2 (const A *, unsigned int)
-+{
-+ asm volatile ("" : : : "memory");
-+}
-+
-+struct D
-+{
-+ C *d1;
-+};
-+
-+struct E
-+{
-+ int e1;
-+ int e2;
-+ D e3;
-+};
-+
-+struct F
-+{
-+ virtual int f1 (const char * s, int n);
-+};
-+
-+struct G
-+{
-+ F *g1;
-+ bool g2;
-+ G & g3 (const char * ws, int len)
-+ {
-+ if (__builtin_expect (!g2, true)
-+ && __builtin_expect (this->g1->f1 (ws, len) != len, false))
-+ g2 = true;
-+ return *this;
-+ }
-+};
-+
-+struct H : public A
-+{
-+ const char *h1;
-+ unsigned int h2;
-+ bool h3;
-+ const char *h4;
-+ char h5;
-+ char h6;
-+ char h7[31];
-+ bool h8;
-+ H () : h1 (0), h2 (0), h4 (0), h5 (0), h6 (0), h8 (false) {}
-+ void h9 (const D &) __attribute__((noinline, noclone));
-+};
-+
-+void
-+H::h9 (const D &)
-+{
-+ h3 = true;
-+ __builtin_memset (h7, 0, sizeof (h7));
-+ asm volatile ("" : : : "memory");
-+};
-+
-+B b;
-+
-+inline const H *
-+foo (const D &x)
-+{
-+ const unsigned int i = b.b1 ();
-+ const A **j = x.d1->c1;
-+ if (!j[i])
-+ {
-+ H *k = 0;
-+ try
-+ {
-+ k = new H;
-+ k->h9 (x);
-+ }
-+ catch (...)
-+ {
-+ }
-+ x.d1->c2 (k, i);
-+ }
-+ return static_cast <const H *>(j[i]);
-+}
-+
-+__attribute__((noinline, noclone)) int
-+bar (char *x, unsigned long v, const char *y, int z, bool w)
-+{
-+ asm volatile ("" : : "r" (x), "r" (v), "r" (y) : "memory");
-+ asm volatile ("" : : "r" (z), "r" (w) : "memory");
-+ return 8;
-+}
-+
-+__attribute__((noinline, noclone)) void
-+baz (void *z, const char *g, unsigned int h, char s, E &e, char *n, char *c, int &l)
-+{
-+ asm volatile ("" : : "r" (z), "r" (g), "r" (h) : "memory");
-+ asm volatile ("" : : "r" (s), "r" (&e), "r" (n) : "memory");
-+ asm volatile ("" : : "r" (c), "r" (&l) : "memory");
-+ if (n == c)
-+ __builtin_abort ();
-+ int i = 0;
-+ asm ("" : "+r" (i));
-+ if (i == 0)
-+ __builtin_exit (0);
-+}
-+
-+__attribute__((noinline, noclone)) G
-+test (void *z, G s, E &x, char, long v)
-+{
-+ const D &d = x.e3;
-+ const H *h = foo (d);
-+ const char *q = h->h7;
-+ const int f = x.e2;
-+ const int i = 5 * sizeof (long);
-+ char *c = static_cast <char *>(__builtin_alloca (i));
-+ const int b = f & 74;
-+ const bool e = (b != 64 && b != 8);
-+ const unsigned long u = ((v > 0 || !e) ? (unsigned long) v : -(unsigned long) v);
-+ int l = bar (c + i, u, q, f, e);
-+ c += i - l;
-+ if (h->h3)
-+ {
-+ char *c2 = static_cast <char *>(__builtin_alloca ((l + 1) * 2));
-+ baz (z, h->h1, h->h2, h->h6, x, c2 + 2, c, l);
-+ c = c2 + 2;
-+ }
-+ if (__builtin_expect (e, true))
-+ {
-+ }
-+ else if ((f & 4096) && v)
-+ {
-+ {
-+ const bool m = f & 176;
-+ *--c = q[m];
-+ *--c = q[1];
-+ }
-+ }
-+ const int w = x.e1;
-+ if (w > l)
-+ {
-+ char * c3 = static_cast <char *>(__builtin_alloca (w));
-+ c = c3;
-+ }
-+ return s.g3 (c, l);
-+}
-+
-+int
-+main ()
-+{
-+ H h;
-+ const A *j[1];
-+ C c;
-+ G g;
-+ E e;
-+ h.h9 (e.e3);
-+ j[0] = &h;
-+ c.c1 = j;
-+ e.e3.d1 = &c;
-+ test (0, g, e, 0, 0);
-+ __builtin_abort ();
-+}
-Index: gcc/testsuite/g++.dg/opt/pr58864.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/opt/pr58864.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/opt/pr58864.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+// PR target/58864
-+// { dg-do compile }
-+// { dg-options "-Os" }
-+// { dg-additional-options "-march=i686" { target { { i?86-*-* x86_64-*-* } && ia32 } } }
-+
-+struct A { A (); ~A (); };
-+struct B { B (); };
-+
-+float d, e;
-+
-+void
-+foo ()
-+{
-+ A a;
-+ float c = d;
-+ while (1)
-+ {
-+ B b;
-+ e = c ? -c : 0;
-+ }
-+}
-Index: gcc/testsuite/g++.dg/tree-prof/pr59255.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tree-prof/pr59255.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tree-prof/pr59255.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+// PR c++/59255
-+// { dg-options "-O2 -std=c++11" }
-+
-+struct S
-+{
-+ __attribute__((noinline, noclone)) ~S () noexcept (true)
-+ {
-+ if (fn)
-+ fn (1);
-+ }
-+ void (*fn) (int);
-+};
-+
-+__attribute__((noinline, noclone)) void
-+foo (int x)
-+{
-+ if (x != 1)
-+ throw 1;
-+}
-+
-+int
-+main ()
-+{
-+ for (int i = 0; i < 100; i++)
-+ {
-+ S s;
-+ s.fn = foo;
-+ }
-+}
-Index: gcc/testsuite/g++.dg/expr/cast2.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/expr/cast2.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/expr/cast2.C (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,5 @@
-+// { dg-options "-pedantic" }
-+
- void (*p)();
-
- void f() {
-Index: gcc/testsuite/g++.dg/gomp/for-20.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/gomp/for-20.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/gomp/for-20.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+// PR c++/60146
-+// { dg-do compile }
-+// { dg-options -fopenmp }
-+
-+int foo() { return 0; }
-+
-+template<typename T> void bar()
-+{
-+#pragma omp parallel for
-+ for (T i = foo(); i < 8; ++i) {}
-+}
-+
-+void baz()
-+{
-+ bar<int>();
-+}
-Index: gcc/testsuite/g++.dg/gomp/pr59297.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/gomp/pr59297.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/gomp/pr59297.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,25 @@
-+// PR c++/59297
-+// { dg-do compile }
-+// { dg-options "-fopenmp" }
-+
-+template <typename T>
-+struct A
-+{
-+ ~A ();
-+ const T &operator[] (int) const;
-+};
-+
-+struct B
-+{
-+ int &operator () (A <int>);
-+};
-+
-+void
-+foo (B &x, int &z)
-+{
-+ A<A<int> > y;
-+ #pragma omp atomic
-+ x (y[0]) += 1;
-+ #pragma omp atomic
-+ z += x(y[1]);
-+}
-Index: gcc/testsuite/g++.dg/diagnostic/pr59838.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/diagnostic/pr59838.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/diagnostic/pr59838.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,4 @@
-+// PR c++/59838
-+// { dg-do compile }
-+
-+enum E { a, b = (E) a }; // { dg-error "conversion to incomplete type" }
-Index: gcc/testsuite/g++.dg/diagnostic/pedantic.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/diagnostic/pedantic.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/diagnostic/pedantic.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+// { dg-do compile }
-+// { dg-options "-pedantic" }
-+typedef void F(void);
-+
-+void foo()
-+{
-+ void* p = 0;
-+ F* f1 = reinterpret_cast<F*>(p); // { dg-warning "ISO" }
-+#pragma GCC diagnostic ignored "-pedantic"
-+ F* f2 = reinterpret_cast<F*>(p);
-+}
-Index: gcc/testsuite/g++.dg/diagnostic/pr58979.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/diagnostic/pr58979.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/diagnostic/pr58979.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,4 @@
-+// PR c++/58979
-+// { dg-do compile }
-+
-+int i = 0->*0; // { dg-error "invalid type argument of" }
-Index: gcc/testsuite/g++.dg/conversion/dr195.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/conversion/dr195.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/conversion/dr195.C (.../branches/gcc-4_8-branch)
-@@ -6,6 +6,7 @@
- // it (yet).
-
- // This checks we warn when being pedantic.
-+// { dg-options "-pedantic" }
-
- typedef void (*PF)(void);
- typedef void *PV;
-Index: gcc/testsuite/g++.dg/conversion/simd1.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/conversion/simd1.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/conversion/simd1.C (.../branches/gcc-4_8-branch)
-@@ -1,4 +1,5 @@
- /* { dg-do compile } */
-+/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */
-
- /* Test overload resolution of vector types.
- From Janis Johnson and Paolo Bonzini, based on PR/16882 */
-@@ -17,7 +18,7 @@
- void foo ()
- {
- vss = vld(i, vscp); /* { dg-error "no matching function for call" } */
-- // { dg-message "candidate" "candidate note" { target *-*-* } 19 }
-+ // { dg-message "candidate" "candidate note" { target *-*-* } 20 }
- vss = vld(i, vssp);
- vss = vld(i, cvssp);
- }
-Index: gcc/testsuite/g++.dg/tls/thread_local8.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tls/thread_local8.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tls/thread_local8.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+// PR c++/55800
-+// { dg-options "-std=c++11" }
-+// { dg-require-alias "" }
-+// { dg-require-effective-target tls }
-+// { dg-final { scan-assembler "_ZTH12foo_instance" { target tls_native } } }
-+
-+struct foo
-+{
-+ foo();
-+};
-+
-+thread_local foo foo_instance;
-Index: gcc/testsuite/g++.dg/tls/thread_local-ice2.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tls/thread_local-ice2.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tls/thread_local-ice2.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+// PR c++/58672
-+// { dg-options "-std=c++11" }
-+// { dg-require-effective-target tls }
-+
-+struct A
-+{
-+ A(int);
-+ i; // { dg-error "" }
-+};
-+
-+thread_local A a(0);
-Index: gcc/testsuite/g++.dg/pr60769.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/pr60769.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/pr60769.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,43 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O" } */
-+
-+template <class T> void fun(T);
-+struct B {};
-+struct R {
-+ int *x;
-+ B f;
-+};
-+R v(int &, R);
-+void rfun(R &);
-+struct A {
-+ void m_fn2(R p1) {
-+ R a = p1;
-+ rfun(p1);
-+ fun(this);
-+ fun(a);
-+ }
-+};
-+struct J {
-+ A ep;
-+ A ap;
-+ int c2a;
-+ void m_fn1(R &p2) {
-+ R d, e, b;
-+ v(c2a, p2);
-+ e = v(c2a, b);
-+ ap.m_fn2(e);
-+ v(c2a, p2);
-+ d = v(c2a, b);
-+ ep.m_fn2(d);
-+ }
-+};
-+struct N {
-+ int &p_;
-+ J cfo;
-+};
-+void fn3(N&n) {
-+ R h;
-+ n.cfo.m_fn1(h);
-+}
-+extern N &c;
-+void fn1() { fn3(c); }
-Index: gcc/testsuite/g++.dg/tm/pr60004.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tm/pr60004.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tm/pr60004.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+// { dg-do compile }
-+// { dg-options "-fgnu-tm" }
-+
-+int a;
-+int f() {
-+ __transaction_atomic {
-+ if (a == 5)
-+ return 1;
-+ }
-+}
-Index: gcc/testsuite/g++.dg/tm/noexcept-6.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tm/noexcept-6.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tm/noexcept-6.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,23 @@
-+// { dg-do compile }
-+// { dg-options "-fno-exceptions -fgnu-tm -O -std=c++0x -fdump-tree-tmlower" }
-+
-+struct TrueFalse
-+{
-+ static constexpr bool v() { return true; }
-+};
-+
-+int global;
-+
-+template<typename T> int foo()
-+{
-+ return __transaction_atomic noexcept(T::v()) (global + 1);
-+}
-+
-+int f1()
-+{
-+ return foo<TrueFalse>();
-+}
-+
-+/* { dg-final { scan-tree-dump-times "eh_must_not_throw" 0 "tmlower" } } */
-+/* { dg-final { scan-tree-dump-times "__transaction_atomic" 1 "tmlower" } } */
-+/* { dg-final { cleanup-tree-dump "tmlower" } } */
-Index: gcc/testsuite/g++.dg/pr59695.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/pr59695.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/pr59695.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,125 @@
-+
-+/* PR target/59695 */
-+/* { dg-do run } */
-+/* { dg-options "-O0" } */
-+
-+#define DEFINE_VIRTUALS_FNS(i) virtual void xxx##i () {} \
-+ virtual void foo1_##i () {}\
-+ virtual void foo2_##i () {}\
-+ virtual void foo3_##i () {}\
-+ virtual void foo4_##i () {}\
-+ virtual void foo5_##i () {}\
-+ virtual void foo6_##i () {}\
-+ virtual void foo7_##i () {}\
-+ virtual void foo8_##i () {}\
-+ virtual void foo9_##i () {}\
-+ virtual void foo10_##i () {}\
-+ virtual void foo11_##i () {}\
-+ virtual void foo12_##i () {}\
-+ virtual void foo13_##i () {}\
-+ virtual void foo14_##i () {}\
-+ virtual void foo15_##i () {}\
-+ virtual void foo16_##i () {}\
-+ virtual void foo17_##i () {}\
-+ virtual void foo18_##i () {}\
-+ virtual void foo19_##i () {}\
-+ virtual void foo20_##i () {}\
-+ virtual void foo21_##i () {}\
-+ virtual void foo22_##i () {}\
-+
-+class base_class_2
-+{
-+
-+public:
-+ /* Define lots of virtual functions */
-+ DEFINE_VIRTUALS_FNS (1)
-+ DEFINE_VIRTUALS_FNS (2)
-+ DEFINE_VIRTUALS_FNS (3)
-+ DEFINE_VIRTUALS_FNS (4)
-+ DEFINE_VIRTUALS_FNS (5)
-+ DEFINE_VIRTUALS_FNS (6)
-+ DEFINE_VIRTUALS_FNS (7)
-+ DEFINE_VIRTUALS_FNS (8)
-+ DEFINE_VIRTUALS_FNS (9)
-+ DEFINE_VIRTUALS_FNS (10)
-+ DEFINE_VIRTUALS_FNS (11)
-+ DEFINE_VIRTUALS_FNS (12)
-+ DEFINE_VIRTUALS_FNS (13)
-+ DEFINE_VIRTUALS_FNS (14)
-+ DEFINE_VIRTUALS_FNS (15)
-+ DEFINE_VIRTUALS_FNS (16)
-+ DEFINE_VIRTUALS_FNS (17)
-+ DEFINE_VIRTUALS_FNS (18)
-+ DEFINE_VIRTUALS_FNS (19)
-+ DEFINE_VIRTUALS_FNS (20)
-+
-+ base_class_2();
-+ virtual ~base_class_2 ();
-+};
-+
-+base_class_2::base_class_2()
-+{
-+}
-+
-+base_class_2::~base_class_2 ()
-+{
-+}
-+
-+class base_class_1
-+{
-+public:
-+ virtual ~base_class_1();
-+ base_class_1();
-+};
-+
-+base_class_1::base_class_1()
-+{
-+}
-+
-+base_class_1::~base_class_1()
-+{
-+}
-+
-+class base_Impl_class :
-+ virtual public base_class_2, public base_class_1
-+{
-+public:
-+ base_Impl_class ();
-+ virtual ~base_Impl_class ();
-+};
-+
-+base_Impl_class::base_Impl_class ()
-+{
-+}
-+
-+base_Impl_class::~base_Impl_class ()
-+{
-+}
-+
-+
-+class test_cls : public base_Impl_class
-+{
-+public:
-+ test_cls();
-+ virtual ~test_cls();
-+};
-+
-+test_cls::test_cls()
-+{
-+}
-+
-+test_cls::~test_cls()
-+{
-+}
-+
-+int main()
-+{
-+ test_cls *test = new test_cls;
-+ base_class_2 *p1 = test;
-+
-+ /* PR59695 destructor thunk offsets are not setup
-+ correctly resulting in crash. */
-+ delete p1;
-+ return 0;
-+}
-+
-Index: gcc/testsuite/g++.dg/cpp0x/initlist79.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/initlist79.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist79.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,8 @@
-+// PR c++/59646
-+// { dg-require-effective-target c++11 }
-+
-+#include <initializer_list>
-+
-+struct A {};
-+
-+std::initializer_list<volatile A> x = {{}};
-Index: gcc/testsuite/g++.dg/cpp0x/enum_base2.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/enum_base2.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/enum_base2.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,9 @@
-+// PR c++/60187
-+// { dg-require-effective-target c++11 }
-+
-+template<typename... T> struct A
-+{
-+ enum E : T {}; // { dg-error "parameter pack" }
-+};
-+
-+A<int> a;
-Index: gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,7 @@
-+// PR c++/58596
-+// { dg-do compile { target c++11 } }
-+
-+struct A
-+{
-+ int i = [] { return decltype(i)(); }();
-+};
-Index: gcc/testsuite/g++.dg/cpp0x/variadic149.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/variadic149.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic149.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+// PR c++/60248
-+// { dg-options "-std=c++11 -g -fabi-version=2" }
-+
-+template<int...> struct A {};
-+
-+template<> struct A<0>
-+{
-+ typedef enum { e } B;
-+};
-+
-+A<0> a;
-Index: gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C (.../branches/gcc-4_8-branch)
-@@ -2,6 +2,7 @@
- // { dg-options "-std=gnu++11" }
- // Ignore warning on some powerpc-ibm-aix configurations.
- // { dg-prune-output "non-standard ABI extension" }
-+// { dg-prune-output "changes the ABI" }
-
- typedef float __attribute__ ((vector_size (4 * sizeof (float)))) V4;
- constexpr V4 build (float x, float y, float z) { return (V4){ x, y, z, 0 };}
-Index: gcc/testsuite/g++.dg/cpp0x/defaulted48.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/defaulted48.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/defaulted48.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,17 @@
-+// PR c++/60108
-+// { dg-require-effective-target c++11 }
-+
-+template<int> struct A
-+{
-+ virtual ~A();
-+};
-+
-+template<typename> struct B : A<0>, A<1>
-+{
-+ ~B() = default;
-+};
-+
-+struct C : B<bool>
-+{
-+ C() {}
-+};
-Index: gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,18 @@
-+// PR c++/60182
-+// { dg-require-effective-target c++11 }
-+
-+class B {};
-+template <typename> using __allocator_base = B;
-+template <typename> class F : __allocator_base<int> {};
-+class C {};
-+template <typename, typename = F<int> > class G : C {};
-+template <typename> class D;
-+class A {
-+ using Container = G<D<char>>;
-+ A();
-+ A(D<char> const &);
-+ Container m_elements;
-+};
-+template <template <class, class> class C, class A = F<D<int>>>
-+void doSomething(C<D<char>, A> &);
-+A::A(D<char> const &) : A() { doSomething(m_elements); }
-Index: gcc/testsuite/g++.dg/cpp0x/initlist81.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/initlist81.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist81.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,25 @@
-+// PR c++/60713
-+// { dg-options "-O" }
-+// { dg-do compile { target c++11 } }
-+
-+template < class x0, class x1, class x2, class x3, class x4 >
-+int *x5 (x0 *, x2 (x1::*)(x3, x4));
-+
-+class x6
-+{
-+ void x7 ();
-+ struct x8
-+ {
-+ int *x9;
-+ };
-+ void x10 (x8);
-+ void x11 (int *, int *);
-+};
-+
-+void
-+x6::x7 ()
-+{
-+ x10 ({
-+ x5 (this, &x6::x11)
-+ });
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+// PR c++/58965
-+// { dg-require-effective-target c++11 }
-+
-+void foo()
-+{
-+ static union
-+ {
-+ int i = i;
-+ };
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/variadic144.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/variadic144.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic144.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+// PR c++/56060
-+// { dg-do compile { target c++11 } }
-+
-+template<typename T> struct baz { };
-+template<typename T> T bar();
-+
-+template<typename T, typename ... U>
-+baz<decltype(bar<T>()(bar<U> ...))> // { dg-error "cannot be used" }
-+foo();
-+
-+int main()
-+{
-+ foo<int>(); // { dg-error "no matching" }
-+ return 0;
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/enum18.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/enum18.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/enum18.C (.../branches/gcc-4_8-branch)
-@@ -4,5 +4,5 @@
- int main(void) {
- enum e {};
- e ev;
-- ev.e::~e_u(); // { dg-error "e_u. has not been declared" }
-+ ev.e::~e_u(); // { dg-error "" }
- }
-Index: gcc/testsuite/g++.dg/cpp0x/noexcept22.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/noexcept22.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/noexcept22.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+// PR c++/60046
-+// { dg-require-effective-target c++11 }
-+
-+constexpr bool foo () { return noexcept (true); }
-+template <typename T>
-+struct V
-+{
-+ void bar (V &) noexcept (foo ()) {}
-+};
-+template <typename T>
-+struct W : public V <int>
-+{
-+ void bar (W &x) { V <int>::bar (x); }
-+};
-+
-+int
-+main ()
-+{
-+ W <int> a, b;
-+ a.bar (b);
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/initlist76.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/initlist76.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist76.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,5 @@
-+// PR c++/58812
-+// { dg-require-effective-target c++11 }
-+
-+int i;
-+int&& j{{ i }}; // { dg-error "too many braces" }
-Index: gcc/testsuite/g++.dg/cpp0x/access02.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/access02.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/access02.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,39 @@
-+// PR c++/58954
-+// { dg-require-effective-target c++11 }
-+
-+template<class T>
-+T&& declval();
-+
-+template<class T>
-+struct foo_argument
-+{
-+ template<class Ret, class C, class Arg>
-+ static Arg test(Ret (C::*)(Arg));
-+
-+ typedef decltype(test(&T::template foo<>)) type;
-+};
-+
-+template<class T, class>
-+struct dependent { typedef T type; };
-+
-+template<class T>
-+struct base
-+{
-+ template<class Ignore = void>
-+ auto foo(int i) -> decltype(declval<
-+ typename dependent<T&, Ignore>::type
-+ >().foo_impl(i));
-+};
-+
-+struct derived : base<derived>
-+{
-+ friend struct base<derived>;
-+private:
-+ int foo_impl(int i);
-+};
-+
-+int main()
-+{
-+ foo_argument<derived>::type var = 0;
-+ return var;
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+// PR c++/59268
-+// { dg-do compile }
-+// { dg-options "-std=c++11" }
-+
-+template <typename>
-+struct A
-+{
-+ constexpr A (int) {}
-+ virtual void foo ()
-+ {
-+ constexpr A<void> a (0);
-+ }
-+};
-+
-+void
-+bar ()
-+{
-+ A<int> a (3);
-+ a.foo ();
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/initlist78.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/initlist78.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist78.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+// PR c++/58639
-+// { dg-require-effective-target c++11 }
-+
-+struct node {
-+ node &parent;
-+};
-+
-+struct vector {
-+ node n;
-+};
-+
-+vector v({}); // { dg-error "" }
-Index: gcc/testsuite/g++.dg/cpp0x/variadic148.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/variadic148.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic148.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,6 @@
-+// PR c++/59989
-+// { dg-require-effective-target c++11 }
-+
-+template<typename T> struct X {};
-+template<template<typename...> class D, typename ...U> int test(D<U...>*);
-+int n = test<X, int>(0); // { dg-error "no match" }
-Index: gcc/testsuite/g++.dg/cpp0x/auto42.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/auto42.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/auto42.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,9 @@
-+// PR c++/60628
-+// { dg-do compile { target c++11 } }
-+
-+#include <initializer_list>
-+
-+void foo(int i)
-+{
-+ auto x[1] = { 0 }; // { dg-error "array of .auto" }
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/nsdmi9.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/nsdmi9.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/nsdmi9.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+// PR c++/58162
-+// { dg-require-effective-target c++11 }
-+
-+struct A {
-+ A();
-+ A(A&&);
-+};
-+
-+struct B {
-+ A const a = A();
-+};
-+
-+B b;
-Index: gcc/testsuite/g++.dg/cpp0x/deleted3.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/deleted3.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/deleted3.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+// PR c++/60216
-+// { dg-require-effective-target c++11 }
-+
-+struct A
-+{
-+ template<typename T> A(T) = delete;
-+};
-+
-+template<> A::A<int>(int) {}
-+
-+A a(0);
-Index: gcc/testsuite/g++.dg/cpp0x/variadic150.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/variadic150.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic150.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,9 @@
-+// PR c++/60219
-+// { dg-require-effective-target c++11 }
-+
-+template<typename..., int> void foo();
-+
-+void bar()
-+{
-+ foo<0>; // { dg-error "" }
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/initlist82.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/initlist82.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist82.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,20 @@
-+// PR c++/60708
-+// { dg-do compile { target c++11 } }
-+
-+template <class T, class U> struct mypair {
-+ mypair(T, U) {}
-+};
-+
-+template<typename T> struct S {
-+ mypair<T *, int> get_pair() noexcept {
-+ return mypair<T*,int>(nullptr, 0);
-+ }
-+};
-+
-+static void foo(const mypair<char *, int> (&a)[2]) noexcept { }
-+
-+int main()
-+{
-+ S<char> s;
-+ foo({s.get_pair(), s.get_pair()});
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/static_assert9.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/static_assert9.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/static_assert9.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,7 @@
-+// PR c++/58837
-+// { dg-require-effective-target c++11 }
-+
-+void f();
-+static_assert(f, "");
-+struct A {};
-+static_assert(A::~A, ""); // { dg-error "non-static member function" }
-Index: gcc/testsuite/g++.dg/cpp0x/variadic145.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/variadic145.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic145.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+// PR c++/59730
-+// { dg-do compile { target c++11 } }
-+
-+template <typename> void declval();
-+template <typename> void forward();
-+template <typename> class D;
-+template <typename _Functor, typename... _Bound_args>
-+class D <_Functor(_Bound_args...)> {
-+ template <typename... _Args, decltype(declval<_Functor>)>
-+ void operator()(...) {
-+ 0(forward<_Args>...);
-+ }
-+};
-Index: gcc/testsuite/g++.dg/cpp0x/decltype57.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/decltype57.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/decltype57.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,8 @@
-+// PR c++/58633
-+// { dg-do compile { target c++11 } }
-+
-+void foo(int i)
-+{
-+ typedef int I;
-+ decltype(i.I::~I())* p;
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/variadic147.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/variadic147.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic147.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+// PR c++/58466
-+// { dg-require-effective-target c++11 }
-+
-+template<char, char...> struct A;
-+
-+template<typename> struct B;
-+
-+template<char... C> struct B<A<C...>> {};
-+
-+B<A<'X'>> b;
-Index: gcc/testsuite/g++.dg/eh/uncaught1.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/eh/uncaught1.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/eh/uncaught1.C (.../branches/gcc-4_8-branch)
-@@ -13,7 +13,7 @@
-
- static Check const data[] = {
- { 0, 0, false }, // construct [0]
-- { 1, 0, true }, // [1] = [0]
-+ { 1, 0, false }, // [1] = [0]
- { 0, 0, true }, // destruct [0]
- { 2, 1, true }, // [2] = [1]
- { 2, 2, true }, // destruct [2]
-Index: gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,54 @@
-+// { dg-do run { target { powerpc64*-*-linux* } } }
-+// { dg-options "-fexceptions -fnon-call-exceptions" }
-+
-+#include <signal.h>
-+#include <stdlib.h>
-+#include <fenv.h>
-+
-+#define SET_CR(R,V) __asm__ __volatile__ ("mtcrf %0,%1" : : "n" (1<<(7-R)), "r" (V<<(4*(7-R))) : "cr" #R)
-+#define GET_CR(R) ({ int tmp; __asm__ __volatile__ ("mfcr %0" : "=r" (tmp)); (tmp >> 4*(7-R)) & 15; })
-+
-+void sighandler (int signo, siginfo_t * si, void * uc)
-+{
-+ SET_CR(2, 3);
-+ SET_CR(3, 2);
-+ SET_CR(4, 1);
-+
-+ throw 0;
-+}
-+
-+float test (float a, float b) __attribute__ ((__noinline__));
-+float test (float a, float b)
-+{
-+ float x;
-+ asm ("mtcrf %1,%2" : "=f" (x) : "n" (1 << (7-3)), "r" (0), "0" (b) : "cr3");
-+ return a / x;
-+}
-+
-+int main ()
-+{
-+ struct sigaction sa;
-+ int status;
-+
-+ sa.sa_sigaction = sighandler;
-+ sa.sa_flags = SA_SIGINFO;
-+
-+ status = sigaction (SIGFPE, & sa, NULL);
-+
-+ feenableexcept (FE_DIVBYZERO);
-+
-+ SET_CR(2, 6);
-+ SET_CR(3, 9);
-+ SET_CR(4, 12);
-+
-+ try {
-+ test (1, 0);
-+ }
-+ catch (...) {
-+ return GET_CR(2) != 6 || GET_CR(3) != 9 || GET_CR(4) != 12;
-+ }
-+
-+ return 1;
-+}
-+
-+
-Index: gcc/testsuite/g++.dg/eh/uncaught4.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/eh/uncaught4.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/eh/uncaught4.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+// PR c++/41174
-+// { dg-do run }
-+
-+#include <exception>
-+
-+#define assert(E) if (!(E)) __builtin_abort();
-+
-+struct e {
-+ e()
-+ {
-+ assert( !std::uncaught_exception() );
-+ try {
-+ throw 1;
-+ } catch (int i) {
-+ assert( !std::uncaught_exception() );
-+ throw;
-+ }
-+ }
-+};
-+
-+int main()
-+{
-+ try {
-+ throw e();
-+ } catch (int i) {
-+ assert( !std::uncaught_exception() );
-+ }
-+ assert( !std::uncaught_exception() );
-+}
-Index: gcc/testsuite/g++.dg/inherit/virtual11.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/inherit/virtual11.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/inherit/virtual11.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,17 @@
-+// PR c++/59031
-+// { dg-do compile }
-+// { dg-options "-fdump-tree-gimple " }
-+class B {
-+ public:
-+ virtual int add (int a, int b) {return a+ b;}
-+};
-+
-+class D : public B {
-+};
-+
-+int foo (int a, int b) {
-+ D d;
-+ return d.add(a, b);
-+}
-+// { dg-final { scan-tree-dump-not "OBJ_TYPE_REF" "gimple" } }
-+// { dg-final { cleanup-tree-dump "gimple" } }
-Index: gcc/testsuite/g++.dg/torture/pr38565.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/torture/pr38565.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/torture/pr38565.C (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,7 @@
- // { dg-do compile }
- // Ignore warning on some powerpc-linux configurations.
- // { dg-prune-output "non-standard ABI extension" }
-+// { dg-prune-output "changes the ABI" }
- #define vector __attribute__((vector_size(16) ))
- vector unsigned int f(int a)
- {
-Index: gcc/testsuite/g++.dg/torture/pr60609.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/torture/pr60609.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/torture/pr60609.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,252 @@
-+/* { dg-do assemble } */
-+
-+class exception
-+{
-+};
-+class bad_alloc:exception
-+{
-+};
-+class logic_error:exception
-+{
-+};
-+class domain_error:logic_error
-+{
-+};
-+class invalid_argument:logic_error
-+{
-+};
-+class length_error:logic_error
-+{
-+};
-+class overflow_error:exception
-+{
-+};
-+typedef int mpz_t[];
-+template < class > class __gmp_expr;
-+template <> class __gmp_expr < mpz_t >
-+{
-+ ~__gmp_expr ();
-+};
-+
-+class PIP_Solution_Node;
-+class internal_exception
-+{
-+ ~internal_exception ();
-+};
-+class not_an_integer:internal_exception
-+{
-+};
-+class not_a_variable:internal_exception
-+{
-+};
-+class not_an_optimization_mode:internal_exception
-+{
-+};
-+class not_a_bounded_integer_type_width:internal_exception
-+{
-+};
-+class not_a_bounded_integer_type_representation:internal_exception
-+{
-+};
-+class not_a_bounded_integer_type_overflow:internal_exception
-+{
-+};
-+class not_a_complexity_class:internal_exception
-+{
-+};
-+class not_a_control_parameter_name:internal_exception
-+{
-+};
-+class not_a_control_parameter_value:internal_exception
-+{
-+};
-+class not_a_pip_problem_control_parameter_name:internal_exception
-+{
-+};
-+class not_a_pip_problem_control_parameter_value:internal_exception
-+{
-+};
-+class not_a_relation:internal_exception
-+{
-+};
-+class ppl_handle_mismatch:internal_exception
-+{
-+};
-+class timeout_exception
-+{
-+ ~timeout_exception ();
-+};
-+class deterministic_timeout_exception:timeout_exception
-+{
-+};
-+void __assert_fail (const char *, const char *, int, int *)
-+__attribute__ ((__noreturn__));
-+void PL_get_pointer (void *);
-+int Prolog_is_address ();
-+inline int
-+Prolog_get_address (void **p1)
-+{
-+ Prolog_is_address ()? static_cast <
-+ void >(0) : __assert_fail ("Prolog_is_address", "./swi_cfli.hh", 0, 0);
-+ PL_get_pointer (p1);
-+ return 0;
-+}
-+
-+class non_linear:internal_exception
-+{
-+};
-+class not_unsigned_integer:internal_exception
-+{
-+};
-+class not_universe_or_empty:internal_exception
-+{
-+};
-+class not_a_nil_terminated_list:internal_exception
-+{
-+};
-+class PPL_integer_out_of_range
-+{
-+ __gmp_expr < mpz_t > n;
-+};
-+void handle_exception ();
-+template < typename T > T * term_to_handle (int, const char *)
-+{
-+ if (Prolog_is_address ())
-+ {
-+ void *p;
-+ Prolog_get_address (&p);
-+ return static_cast < T * >(0);
-+ }
-+ throw;
-+}
-+
-+void
-+ppl_new_MIP_Problem_from_MIP_Problem ()
-+try
-+{
-+ term_to_handle < int >(0, "ppl_new_MIP_Problem_from_MIP_Problem/2");
-+}
-+
-+catch (exception &)
-+{
-+}
-+
-+int
-+ppl_PIP_Tree_Node_parametric_values ()
-+{
-+ try
-+ {
-+ PIP_Solution_Node *a = term_to_handle < PIP_Solution_Node > (0, 0);
-+ (void)a;
-+ return 1;
-+ }
-+ catch (internal_exception &)
-+ {
-+ }
-+ catch (not_unsigned_integer &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (non_linear &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_variable &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_an_integer &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (ppl_handle_mismatch &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_an_optimization_mode &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_complexity_class &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_bounded_integer_type_width &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_bounded_integer_type_representation &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_bounded_integer_type_overflow &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_control_parameter_name &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_control_parameter_value &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_pip_problem_control_parameter_name &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_pip_problem_control_parameter_value &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_universe_or_empty &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_relation &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (not_a_nil_terminated_list &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (PPL_integer_out_of_range &)
-+ {
-+ handle_exception ();
-+ }
-+ catch (int &)
-+ {
-+ } catch (timeout_exception &)
-+ {
-+ handle_exception ();
-+ } catch (deterministic_timeout_exception &)
-+ {
-+ handle_exception ();
-+ } catch (overflow_error &)
-+ {
-+ handle_exception ();
-+ } catch (domain_error &)
-+ {
-+ handle_exception ();
-+ } catch (length_error &)
-+ {
-+ handle_exception ();
-+ } catch (invalid_argument &)
-+ {
-+ handle_exception ();
-+ } catch (logic_error &)
-+ {
-+ handle_exception ();
-+ } catch (bad_alloc &)
-+ {
-+ handle_exception ();
-+ } catch (exception &)
-+ {
-+ handle_exception ();
-+ } catch ( ...)
-+ {
-+ handle_exception ();
-+ }
-+ return 0;
-+}
-Index: gcc/testsuite/g++.dg/torture/pr57499.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/torture/pr57499.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/torture/pr57499.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,14 @@
-+// PR middle-end/57499
-+// { dg-do compile }
-+
-+struct S
-+{
-+ ~S () __attribute__ ((noreturn)) {} // { dg-warning "function does return" }
-+};
-+
-+void
-+foo ()
-+{
-+ S s;
-+ throw 1;
-+}
-Index: gcc/testsuite/g++.dg/torture/pr60750.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/torture/pr60750.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/torture/pr60750.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+// { dg-do run }
-+// { dg-options "-std=c++11" }
-+
-+#include <string>
-+#include <stdexcept>
-+
-+const std::string err_prefix = "Problem: ";
-+void thrower (std::string msg)
-+{
-+ throw std::runtime_error(err_prefix + std::move(msg));
-+}
-+
-+int main(int argc, char **argv)
-+{
-+ try {
-+ std::string base = "hello";
-+ thrower(std::move(base));
-+ } catch (const std::runtime_error &e) {
-+ }
-+ return 0;
-+}
-Index: gcc/testsuite/g++.dg/torture/pr59163.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/torture/pr59163.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/torture/pr59163.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,30 @@
-+// PR target/59163
-+// { dg-do run }
-+
-+struct A { float a[4]; };
-+struct B { int b; A a; };
-+
-+__attribute__((noinline, noclone)) void
-+bar (A &a)
-+{
-+ if (a.a[0] != 36.0f || a.a[1] != 42.0f || a.a[2] != 48.0f || a.a[3] != 54.0f)
-+ __builtin_abort ();
-+}
-+
-+__attribute__((noinline, noclone)) void
-+foo (A &a)
-+{
-+ int i;
-+ A c = a;
-+ for (i = 0; i < 4; i++)
-+ c.a[i] *= 6.0f;
-+ a = c;
-+ bar (a);
-+}
-+
-+int
-+main ()
-+{
-+ B b = { 5, { 6, 7, 8, 9 } };
-+ foo (b.a);
-+}
-Index: gcc/testsuite/g++.dg/torture/pr60895.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/torture/pr60895.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/torture/pr60895.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,32 @@
-+// { dg-do compile }
-+
-+struct C
-+{
-+ double elems[3];
-+};
-+
-+C
-+foo ()
-+{
-+ C a;
-+ double *f = a.elems;
-+ int b;
-+ for (; b;)
-+ {
-+ *f = 0;
-+ ++f;
-+ }
-+ return a;
-+}
-+
-+struct J
-+{
-+ C c;
-+ __attribute__((always_inline)) J () : c (foo ()) {}
-+};
-+
-+void
-+bar ()
-+{
-+ J ();
-+}
-Index: gcc/testsuite/g++.dg/ipa/pr60640-1.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ipa/pr60640-1.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ipa/pr60640-1.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,50 @@
-+// { dg-do compile }
-+// { dg-options "-O3" }
-+
-+class ASN1Object
-+{
-+public:
-+ virtual ~ASN1Object ();
-+};
-+class A
-+{
-+ virtual unsigned m_fn1 () const;
-+};
-+class B
-+{
-+public:
-+ ASN1Object Element;
-+ virtual unsigned m_fn1 (bool) const;
-+};
-+template <class BASE> class C : public BASE
-+{
-+};
-+
-+class D : ASN1Object, public B
-+{
-+};
-+class G : public D
-+{
-+ unsigned m_fn1 (bool) const {}
-+};
-+class F : A
-+{
-+public:
-+ F (A);
-+ unsigned m_fn1 () const
-+ {
-+ int a;
-+ a = m_fn2 ().m_fn1 (0);
-+ return a;
-+ }
-+ const B &m_fn2 () const { return m_groupParameters; }
-+ C<G> m_groupParameters;
-+};
-+template <class D> void BenchMarkKeyAgreement (int *, int *, int)
-+{
-+ A f;
-+ D d (f);
-+}
-+
-+void BenchmarkAll2 () { BenchMarkKeyAgreement<F>(0, 0, 0); }
-+
-Index: gcc/testsuite/g++.dg/ipa/pr60640-2.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ipa/pr60640-2.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ipa/pr60640-2.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,15 @@
-+// { dg-do compile }
-+// { dg-options "-O3" }
-+
-+struct B { virtual unsigned f () const; };
-+struct C { virtual void f (); };
-+struct F { virtual unsigned f (bool) const; ~F (); };
-+struct J : C, F {};
-+struct G : J { unsigned f (bool) const { return 0; } };
-+struct H : B
-+{
-+ H (int);
-+ unsigned f () const { return ((const F &) h).f (0); }
-+ G h;
-+};
-+H h (0);
-Index: gcc/testsuite/g++.dg/ipa/pr60640-3.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ipa/pr60640-3.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ipa/pr60640-3.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,81 @@
-+// { dg-do run }
-+// { dg-options "-O3" }
-+
-+struct Distraction
-+{
-+ char fc[8];
-+ virtual Distraction * return_self ()
-+ { return this; }
-+};
-+
-+namespace {
-+
-+struct A;
-+static A * __attribute__ ((noinline, noclone)) get_an_A ();
-+
-+static int go;
-+
-+struct A
-+{
-+ int fi;
-+
-+ A () : fi(777) {}
-+ A (int pi) : fi (pi) {}
-+ virtual A * foo (int p) = 0;
-+};
-+
-+struct B;
-+static B * __attribute__ ((noinline, noclone)) get_a_B ();
-+
-+struct B : public Distraction, A
-+{
-+ B () : Distraction(), A() { }
-+ B (int pi) : Distraction (), A (pi) {}
-+ virtual B * foo (int p)
-+ {
-+ int o = fi;
-+ for (int i = 0; i < p; i++)
-+ o += i + i * i;
-+ go = o;
-+
-+ return get_a_B ();
-+ }
-+};
-+
-+
-+struct B gb1 (1111), gb2 (2);
-+static B * __attribute__ ((noinline, noclone))
-+get_a_B ()
-+{
-+ return &gb1;
-+}
-+
-+static A * __attribute__ ((noinline, noclone))
-+get_an_A ()
-+{
-+ return &gb2;
-+}
-+
-+}
-+
-+static int __attribute__ ((noinline, noclone))
-+get_a_number ()
-+{
-+ return 5;
-+}
-+
-+extern "C" void abort (void);
-+
-+int main (int argc, char *argv[])
-+{
-+ for (int i = 0; i < get_a_number (); i++)
-+ {
-+ struct A *p = get_an_A ();
-+ struct A *r = p->foo (4);
-+ if (r->fi != 1111)
-+ abort ();
-+ if (go != 22)
-+ abort ();
-+ }
-+ return 0;
-+}
-Index: gcc/testsuite/g++.dg/ipa/pr60419.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ipa/pr60419.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ipa/pr60419.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,80 @@
-+// PR middle-end/60419
-+// { dg-do compile }
-+// { dg-options "-O2" }
-+
-+struct C
-+{
-+};
-+
-+struct I : C
-+{
-+ I ();
-+};
-+
-+struct J
-+{
-+ void foo ();
-+ J ();
-+ virtual void foo (int &, int);
-+};
-+
-+template <class>
-+struct D
-+{
-+ virtual void foo (I &) const;
-+ void bar ()
-+ {
-+ I p;
-+ foo (p);
-+ }
-+};
-+
-+struct K : J, public D<int>
-+{
-+};
-+
-+struct F
-+{
-+ K *operator->();
-+};
-+
-+struct N : public K
-+{
-+ void foo (int &, int);
-+ I n;
-+ void foo (I &) const {}
-+};
-+
-+struct L : J
-+{
-+ F l;
-+};
-+
-+struct M : F
-+{
-+ L *operator->();
-+};
-+
-+struct G
-+{
-+ G ();
-+};
-+
-+M h;
-+
-+G::G ()
-+try
-+{
-+ N f;
-+ f.bar ();
-+ throw;
-+}
-+catch (int)
-+{
-+}
-+
-+void
-+baz ()
-+{
-+ h->l->bar ();
-+}
-Index: gcc/testsuite/g++.dg/overload/defarg8.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/overload/defarg8.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/overload/defarg8.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,22 @@
-+// PR c++/60367
-+// { dg-do run { target c++11 } }
-+
-+extern "C" int printf (const char *, ...);
-+extern "C" void abort();
-+
-+void *p;
-+struct foo {
-+ foo() { p = this; }
-+ foo (const foo &) { abort(); }
-+ ~foo() { if (p != this) abort(); }
-+};
-+
-+void do_something( foo f = {} )
-+{
-+ if (&f != p) abort();
-+}
-+
-+int main()
-+{
-+ do_something();
-+}
-Index: gcc/testsuite/g++.dg/template/ref7.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/ref7.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/ref7.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+// PR c++/60274
-+
-+typedef const char *const& ProtocolIdType;
-+
-+template <ProtocolIdType protocolId>
-+struct C {
-+ typedef int ProtocolVersion;
-+ struct D {
-+ ProtocolVersion GetProtocolVersion();
-+ };
-+};
-+template <ProtocolIdType protocolId>
-+typename C<protocolId>::ProtocolVersion C<protocolId>::D::GetProtocolVersion()
-+{
-+ return 1;
-+}
-Index: gcc/testsuite/g++.dg/template/using28.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/using28.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/using28.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,17 @@
-+// PR c++/37140
-+
-+struct C
-+{
-+ static const int block_size = 1;
-+};
-+
-+template <typename T> struct A {
-+ typedef C type;
-+};
-+
-+template <typename T> struct B : public A<T> {
-+ using typename A<T>::type;
-+ static const int block_size = type::block_size;
-+};
-+
-+template class B<int>;
-Index: gcc/testsuite/g++.dg/template/shadow1.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/shadow1.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/shadow1.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,4 @@
-+// PR c++/58632
-+
-+template<template<int I> class A> // { dg-message "shadows" }
-+class A {}; // { dg-error "declaration" }
-Index: gcc/testsuite/g++.dg/template/partial14.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/partial14.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/partial14.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,16 @@
-+// PR c++/59044
-+
-+template <class T>
-+class C {
-+private:
-+ template <T a, T b>
-+ struct Implementation {};
-+public:
-+ typedef typename Implementation<0, 0>::Typedef Type;
-+};
-+
-+template <class T>
-+template <T b>
-+struct C<T>::Implementation<0, b> { typedef void Typedef; };
-+
-+template class C<unsigned>;
-Index: gcc/testsuite/g++.dg/template/using27.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/using27.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/using27.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,33 @@
-+// PR c++/37140
-+
-+struct X
-+{
-+ typedef int nested_type;
-+};
-+
-+template <class T>
-+struct A
-+{
-+ typedef X type;
-+};
-+
-+template <class T>
-+struct B : A<T>
-+{
-+ using typename A<T>::type;
-+ typename type::nested_type x;
-+};
-+
-+template <class T>
-+struct C : B<T>
-+{
-+ using typename B<T>::type;
-+ typename type::nested_type y;
-+};
-+
-+struct D : C<int>
-+{
-+ using C<int>::type;
-+ type::nested_type z;
-+};
-+
-Index: gcc/testsuite/g++.dg/template/using29.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/using29.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/using29.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+// PR c++/58047
-+
-+template <int N>
-+struct print_arg { };
-+
-+struct const_holder {
-+ static const int CONSTANT = 42;
-+};
-+
-+template <typename T>
-+struct identity {
-+ typedef T type;
-+};
-+
-+template <class T>
-+struct test_case : public identity<T> {
-+ using typename identity<T>::type;
-+ print_arg<type::CONSTANT> printer;
-+};
-+
-+template struct test_case<const_holder>;
-Index: gcc/testsuite/g++.dg/template/partial15.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/partial15.C (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/partial15.C (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,19 @@
-+// PR c++/57043
-+// { dg-do link }
-+
-+template<typename D> struct complex { };
-+
-+template<typename Tp>
-+complex<Tp>
-+pow(const complex<Tp>& x, const complex<Tp>& y) { return complex<Tp>(); }
-+
-+template<typename T, typename U>
-+struct promote_2 { typedef T type; };
-+
-+template<typename Tp, typename Up>
-+complex<typename promote_2<Tp, Up>::type>
-+pow(const complex<Tp>& x, const complex<Up>& y);
-+
-+complex<double> (*powcc)(const complex<double>&, const complex<double>&) = pow;
-+
-+int main() {}
-Index: gcc/testsuite/c-c++-common/cpp/pr60400-1.h
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/cpp/pr60400-1.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/cpp/pr60400-1.h (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,3 @@
-+??=ifndef PR60400_1_H
-+??=define PR60400_1_H
-+??=endif
-Index: gcc/testsuite/c-c++-common/cpp/pr60400-2.h
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/cpp/pr60400-2.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/cpp/pr60400-2.h (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,4 @@
-+??=ifndef PR60400_2_H
-+??=define PR60400_2_H
-+??=include "pr60400-1.h"
-+??=endif
-Index: gcc/testsuite/c-c++-common/cpp/pr60400.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/cpp/pr60400.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/cpp/pr60400.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+/* PR preprocessor/60400 */
-+/* { dg-do compile } */
-+/* { dg-options "-trigraphs -Wtrigraphs" } */
-+
-+??=include "pr60400-1.h"
-+??=include "pr60400-2.h"
-+
-+/* { dg-warning "trigraph" "" { target *-*-* } 1 } */
-+/* { dg-warning "trigraph" "" { target *-*-* } 2 } */
-+/* { dg-warning "trigraph" "" { target *-*-* } 3 } */
-+/* { dg-warning "trigraph" "" { target *-*-* } 4 } */
-+/* { dg-warning "trigraph" "" { target *-*-* } 5 } */
-+/* { dg-warning "trigraph" "" { target *-*-* } 6 } */
-Index: gcc/testsuite/c-c++-common/cpp/pr58844-1.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/cpp/pr58844-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/cpp/pr58844-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,8 @@
-+/* PR preprocessor/58844 */
-+/* { dg-do compile } */
-+/* { dg-options "-ftrack-macro-expansion=0" } */
-+
-+#define A x######x
-+int A = 1;
-+#define A x######x /* { dg-message "previous definition" } */
-+#define A x##x /* { dg-warning "redefined" } */
-Index: gcc/testsuite/c-c++-common/cpp/pr58844-2.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/cpp/pr58844-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/cpp/pr58844-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,8 @@
-+/* PR preprocessor/58844 */
-+/* { dg-do compile } */
-+/* { dg-options "-ftrack-macro-expansion=2" } */
-+
-+#define A x######x
-+int A = 1;
-+#define A x######x /* { dg-message "previous definition" } */
-+#define A x##x /* { dg-warning "redefined" } */
-Index: gcc/testsuite/c-c++-common/convert-vec-1.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/convert-vec-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/convert-vec-1.c (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,4 @@
- /* { dg-do compile } */
-+/* { dg-prune-output "changes the ABI" } */
- typedef float v2sf __attribute__ ((vector_size (8)));
- v2sf sub (void) { return (v2sf) 0.0; } /* { dg-error "can't convert" } */
-Index: gcc/testsuite/c-c++-common/pr60101.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr60101.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr60101.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,112 @@
-+/* PR c/60101 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -Wall" } */
-+
-+extern int *a, b, *c, *d;
-+
-+void
-+foo (double _Complex *x, double _Complex *y, double _Complex *z, unsigned int l, int w)
-+{
-+ unsigned int e = (unsigned int) a[3];
-+ double _Complex (*v)[l][4][e][l][4] = (double _Complex (*)[l][4][e][l][4]) z;
-+ double _Complex (*f)[l][b][l] = (double _Complex (*)[l][b][l]) y;
-+ unsigned int g = c[0] * c[1] * c[2];
-+ unsigned int h = d[0] + c[0] * (d[1] + c[1] * d[2]);
-+ unsigned int i;
-+
-+ for (i = 0; i < e; i++)
-+ {
-+ int j = e * d[3] + i;
-+
-+ unsigned int n0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11;
-+ float _Complex s = 0.;
-+ unsigned int t = 0;
-+
-+ for (n0 = 0; n0 < l; n0++)
-+ for (n1 = 0; n1 < l; n1++)
-+ for (n2 = 0; n2 < l; n2++)
-+ for (n3 = 0; n3 < l; n3++)
-+ for (n4 = 0; n4 < l; n4++)
-+ for (n5 = 0; n5 < l; n5++)
-+ for (n6 = 0; n6 < l; n6++)
-+ for (n7 = 0; n7 < l; n7++)
-+ for (n8 = 0; n8 < l; n8++)
-+ for (n9 = 0; n9 < l; n9++)
-+ for (n10 = 0; n10 < l; n10++)
-+ for (n11 = 0; n11 < l; n11++)
-+ {
-+ if (t % g == h)
-+ s
-+ += f[n0][n4][j][n8] * f[n1][n5][j][n9] * ~(f[n2][n6][w][n10]) * ~(f[n3][n7][w][n11])
-+ * (+0.25 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1]
-+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0]
-+ + 0.25 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]
-+ - 0.5 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]
-+ + 0.25 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1]
-+ * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0]
-+ - 0.5 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]
-+ + 0.25 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]
-+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1]
-+ * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0]
-+ - 0.5 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]
-+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]
-+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1]
-+ * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0]
-+ + 0.25 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]
-+ - 0.5 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]
-+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]
-+ * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0]
-+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]
-+ * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0]
-+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]
-+ * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0]
-+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]
-+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0]
-+ + 1. * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]
-+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]
-+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]
-+ * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0]
-+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]
-+ * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0]
-+ + 0.25 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]
-+ * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0]
-+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]
-+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0]
-+ - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0]
-+ + 1. * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0]
-+ + 0.5 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]
-+ * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] * v[0][n10][0][i][n8][0]
-+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]
-+ * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0] * v[0][n10][0][i][n8][0]
-+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]
-+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n0][0] * v[0][n10][0][i][n1][0]
-+ + 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]
-+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n10][0][i][n0][0]
-+ + 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n0][0] * v[0][n10][0][i][n1][0]
-+ - 0.5 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1]
-+ * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n10][0][i][n0][0]
-+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1]
-+ * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] * v[0][n3][0][i][n8][0]
-+ - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1]
-+ * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n0][0] * v[0][n3][0][i][n1][0]);
-+ t++;
-+ }
-+ int u = (j - w + b) % b;
-+ int q = (j >= w ? +1 : -1);
-+ int r = q;
-+ x[u] += r * s;
-+ }
-+}
-Index: gcc/testsuite/c-c++-common/pr36282-3.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr36282-3.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr36282-3.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+/* PR middle-end/36282 */
-+/* { dg-do compile } */
-+
-+void bar (void);
-+#pragma weak bar
-+
-+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);
-+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */
-+
-+void
-+foo (void)
-+{
-+}
-Index: gcc/testsuite/c-c++-common/pr59037.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr59037.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr59037.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3" } */
-+
-+typedef int v4si __attribute__ ((vector_size (16)));
-+
-+int
-+main (int argc, char** argv)
-+{
-+ v4si x = {0,1,2,3};
-+ x = (v4si) {(x)[3], (x)[2], (x)[1], (x)[0]};
-+ return x[4];
-+}
-Index: gcc/testsuite/c-c++-common/pr59280.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr59280.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr59280.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,4 @@
-+/* PR c/59280 */
-+/* { dg-do compile } */
-+
-+void bar (char *) __attribute__((constructor(foo))); /* { dg-error "constructor priorities must be integers|was not declared|constructor priorities are not supported" } */
-Index: gcc/testsuite/c-c++-common/pr37743.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr37743.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr37743.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+/* PR c/37743 */
-+/* This needs to be run only on targets where __UINT32_TYPE__ is defined
-+ to unsigned int. */
-+/* { dg-do compile { target *-*-linux-gnu* } } */
-+/* { dg-options "-Wformat" } */
-+
-+int foo (const char *, ...) __attribute__ ((format (printf, 1, 2)));
-+
-+void
-+bar (unsigned int x)
-+{
-+ foo ("%x", __builtin_bswap32 (x));
-+}
-Index: gcc/testsuite/c-c++-common/fold-divmul-1.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/fold-divmul-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/fold-divmul-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-options "-fdump-tree-original" } */
-+
-+int *
-+fx (int *b, int *e)
-+{
-+ return b + (e - b);
-+}
-+
-+/* { dg-final { scan-tree-dump-not "/\\\[ex\\\]" "original" } } */
-+/* { dg-final { cleanup-tree-dump "original" } } */
-Index: gcc/testsuite/c-c++-common/torture/pr58794-1.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/torture/pr58794-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/torture/pr58794-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,29 @@
-+/* { dg-do compile } */
-+
-+struct S0
-+{
-+ int f;
-+};
-+
-+struct S1
-+{
-+ struct S0 f1;
-+ volatile int f2;
-+};
-+
-+struct S2
-+{
-+ struct S1 g;
-+} a, b;
-+
-+static int *c[1][2] = {{0, (int *)&a.g.f2}};
-+static int d;
-+
-+int
-+main ()
-+{
-+ for (d = 0; d < 1; d++)
-+ for (b.g.f1.f = 0; b.g.f1.f < 1; b.g.f1.f++)
-+ *c[b.g.f1.f][d + 1] = 0;
-+ return 0;
-+}
-Index: gcc/testsuite/c-c++-common/torture/pr58794-2.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/torture/pr58794-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/torture/pr58794-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+
-+struct S
-+{
-+ volatile int f;
-+} a;
-+
-+unsigned int b;
-+
-+static int *c[1][2] = {{0, (int *)&a.f}};
-+static unsigned int d;
-+
-+int
-+main ()
-+{
-+ for (; d < 1; d++)
-+ for (; b < 1; b++)
-+ *c[b][d + 1] = 0;
-+
-+ return 0;
-+}
-Index: gcc/testsuite/c-c++-common/torture/pr60026.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/torture/pr60026.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/torture/pr60026.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,28 @@
-+/* PR ipa/60026 */
-+/* { dg-do compile } */
-+
-+struct S { int f; } a;
-+
-+__attribute__((optimize (0)))
-+struct S foo (int x, struct S y)
-+{
-+ int b = y.f;
-+ return a;
-+}
-+
-+void
-+bar ()
-+{
-+ while (a.f)
-+ {
-+ struct S c = {0};
-+ foo (0, c);
-+ }
-+}
-+
-+int
-+main ()
-+{
-+ bar ();
-+ return 0;
-+}
-Index: gcc/testsuite/c-c++-common/vector-compare-2.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/vector-compare-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/vector-compare-2.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,7 @@
- /* { dg-do compile } */
- /* { dg-options "-fno-common" { target hppa*-*-hpux* } } */
- /* { dg-options "-mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */
-+/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */
- /* Ignore warning on some powerpc-ibm-aix configurations. */
- /* { dg-prune-output "non-standard ABI extension" } */
-
-Index: gcc/testsuite/c-c++-common/pr36282-4.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr36282-4.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr36282-4.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,13 @@
-+/* PR middle-end/36282 */
-+/* { dg-do compile } */
-+
-+#pragma weak bar
-+void bar (void);
-+
-+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);
-+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */
-+
-+void
-+foo (void)
-+{
-+}
-Index: gcc/testsuite/c-c++-common/gomp/pr58809.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/gomp/pr58809.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/gomp/pr58809.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,31 @@
-+/* PR middle-end/58809 */
-+/* { dg-do compile } */
-+/* { dg-options "-fopenmp" } */
-+
-+_Complex int j;
-+_Complex double d;
-+
-+void
-+foo (void)
-+{
-+ #pragma omp parallel reduction (&:j) /* { dg-error "has invalid type for" } */
-+ ;
-+ #pragma omp parallel reduction (|:j) /* { dg-error "has invalid type for" } */
-+ ;
-+ #pragma omp parallel reduction (^:j) /* { dg-error "has invalid type for" } */
-+ ;
-+ #pragma omp parallel reduction (min:j) /* { dg-error "has invalid type for" } */
-+ ;
-+ #pragma omp parallel reduction (max:j) /* { dg-error "has invalid type for" } */
-+ ;
-+ #pragma omp parallel reduction (&:d) /* { dg-error "has invalid type for" } */
-+ ;
-+ #pragma omp parallel reduction (|:d) /* { dg-error "has invalid type for" } */
-+ ;
-+ #pragma omp parallel reduction (^:d) /* { dg-error "has invalid type for" } */
-+ ;
-+ #pragma omp parallel reduction (min:d) /* { dg-error "has invalid type for" } */
-+ ;
-+ #pragma omp parallel reduction (max:d) /* { dg-error "has invalid type for" } */
-+ ;
-+}
-Index: gcc/testsuite/c-c++-common/gomp/pr59467.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/gomp/pr59467.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/gomp/pr59467.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,68 @@
-+/* PR libgomp/59467 */
-+
-+int v;
-+
-+void
-+foo (void)
-+{
-+ int x = 0, y = 0;
-+ #pragma omp parallel
-+ {
-+ int z;
-+ #pragma omp single copyprivate (x) /* { dg-error "is not threadprivate or private in outer context" } */
-+ {
-+ #pragma omp atomic write
-+ x = 6;
-+ }
-+ #pragma omp atomic read
-+ z = x;
-+ #pragma omp atomic
-+ y += z;
-+ }
-+ #pragma omp parallel
-+ {
-+ int z;
-+ #pragma omp single copyprivate (v) /* { dg-error "is not threadprivate or private in outer context" } */
-+ {
-+ #pragma omp atomic write
-+ v = 6;
-+ }
-+ #pragma omp atomic read
-+ z = v;
-+ #pragma omp atomic
-+ y += z;
-+ }
-+ #pragma omp parallel private (x)
-+ {
-+ int z;
-+ #pragma omp single copyprivate (x)
-+ {
-+ #pragma omp atomic write
-+ x = 6;
-+ }
-+ #pragma omp atomic read
-+ z = x;
-+ #pragma omp atomic
-+ y += z;
-+ }
-+ x = 0;
-+ #pragma omp parallel reduction (+:x)
-+ {
-+ #pragma omp single copyprivate (x)
-+ {
-+ #pragma omp atomic write
-+ x = 6;
-+ }
-+ #pragma omp atomic
-+ y += x;
-+ }
-+ #pragma omp single copyprivate (x)
-+ {
-+ x = 7;
-+ }
-+ #pragma omp single copyprivate (v) /* { dg-error "is not threadprivate or private in outer context" } */
-+ {
-+ #pragma omp atomic write
-+ v = 6;
-+ }
-+}
-Index: gcc/testsuite/c-c++-common/pr36282-1.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr36282-1.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr36282-1.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,12 @@
-+/* PR middle-end/36282 */
-+/* { dg-do compile } */
-+
-+#pragma weak bar
-+
-+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);
-+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */
-+
-+void
-+foo (void)
-+{
-+}
-Index: gcc/testsuite/c-c++-common/pr60689.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr60689.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr60689.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+/* PR c++/60689 */
-+/* { dg-do compile } */
-+
-+struct S { char x[9]; };
-+
-+void
-+foo (struct S *x, struct S *y, struct S *z)
-+{
-+ __atomic_exchange (x, y, z, __ATOMIC_SEQ_CST);
-+}
-Index: gcc/testsuite/c-c++-common/scal-to-vec2.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/scal-to-vec2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/scal-to-vec2.c (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,7 @@
- /* { dg-do compile } */
- /* { dg-options "-fno-common" { target hppa*-*-hpux* } } */
- /* { dg-options "-mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */
-+/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */
- /* Ignore warning on some powerpc-ibm-aix configurations. */
- /* { dg-prune-output "non-standard ABI extension" } */
-
-Index: gcc/testsuite/c-c++-common/pr59032.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr59032.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr59032.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,30 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2" } */
-+
-+void
-+foo()
-+{
-+ float v __attribute__((vector_size(8)));
-+ v++;
-+}
-+
-+void
-+foo2 ()
-+{
-+ float v __attribute__((vector_size(8)));
-+ ++v;
-+}
-+
-+void
-+foo3 ()
-+{
-+ float v __attribute__((vector_size(8)));
-+ v--;
-+}
-+
-+void
-+foo4 ()
-+{
-+ float v __attribute__((vector_size(8)));
-+ --v;
-+}
-Index: gcc/testsuite/c-c++-common/pr36282-2.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr36282-2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr36282-2.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,10 @@
-+/* PR middle-end/36282 */
-+/* { dg-do compile } */
-+
-+extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n);
-+extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */
-+
-+void
-+foo (void)
-+{
-+}
-Index: gcc/cp/typeck.c
-===================================================================
---- a/src/gcc/cp/typeck.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/typeck.c (.../branches/gcc-4_8-branch)
-@@ -4103,6 +4103,11 @@
- case TRUTH_ORIF_EXPR:
- case TRUTH_AND_EXPR:
- case TRUTH_OR_EXPR:
-+ if (TREE_CODE (type0) == VECTOR_TYPE || TREE_CODE (type1) == VECTOR_TYPE)
-+ {
-+ sorry ("logical operation on vector type");
-+ return error_mark_node;
-+ }
- result_type = boolean_type_node;
- break;
-
-@@ -5010,7 +5015,10 @@
- cp_truthvalue_conversion (tree expr)
- {
- tree type = TREE_TYPE (expr);
-- if (TYPE_PTRDATAMEM_P (type))
-+ if (TYPE_PTRDATAMEM_P (type)
-+ /* Avoid ICE on invalid use of non-static member function. */
-+ || (TREE_CODE (expr) == FUNCTION_DECL
-+ && DECL_NONSTATIC_MEMBER_FUNCTION_P (expr)))
- return build_binary_op (EXPR_LOCATION (expr),
- NE_EXPR, expr, nullptr_node, 1);
- else if (TYPE_PTR_P (type) || TYPE_PTRMEMFUNC_P (type))
-@@ -5588,7 +5596,9 @@
- inc = cxx_sizeof_nowarn (TREE_TYPE (argtype));
- }
- else
-- inc = integer_one_node;
-+ inc = (TREE_CODE (argtype) == VECTOR_TYPE
-+ ? build_one_cst (argtype)
-+ : integer_one_node);
-
- inc = cp_convert (argtype, inc, complain);
-
-@@ -6639,7 +6649,7 @@
- where possible, and it is necessary in some cases. DR 195
- addresses this issue, but as of 2004/10/26 is still in
- drafting. */
-- warning (0, "ISO C++ forbids casting between pointer-to-function and pointer-to-object");
-+ warning (OPT_Wpedantic, "ISO C++ forbids casting between pointer-to-function and pointer-to-object");
- return fold_if_not_in_template (build_nop (type, expr));
- }
- else if (TREE_CODE (type) == VECTOR_TYPE)
-@@ -7194,8 +7204,7 @@
- side effect associated with any single compound assignment
- operator. -- end note ] */
- lhs = stabilize_reference (lhs);
-- if (TREE_SIDE_EFFECTS (rhs))
-- rhs = mark_rvalue_use (rhs);
-+ rhs = rvalue (rhs);
- rhs = stabilize_expr (rhs, &init);
- newrhs = cp_build_binary_op (input_location,
- modifycode, lhs, rhs,
-@@ -7611,7 +7620,7 @@
- /* Handle null pointer to member function conversions. */
- if (null_ptr_cst_p (pfn))
- {
-- pfn = build_c_cast (input_location, type, pfn);
-+ pfn = cp_build_c_cast (type, pfn, complain);
- return build_ptrmemfunc1 (to_type,
- integer_zero_node,
- pfn);
-Index: gcc/cp/decl.c
-===================================================================
---- a/src/gcc/cp/decl.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/decl.c (.../branches/gcc-4_8-branch)
-@@ -1867,9 +1867,9 @@
- /* Merge the data types specified in the two decls. */
- newtype = merge_types (TREE_TYPE (newdecl), TREE_TYPE (olddecl));
-
-- /* If merge_types produces a non-typedef type, just use the old type. */
-- if (TREE_CODE (newdecl) == TYPE_DECL
-- && newtype == DECL_ORIGINAL_TYPE (newdecl))
-+ /* For typedefs use the old type, as the new type's DECL_NAME points
-+ at newdecl, which will be ggc_freed. */
-+ if (TREE_CODE (newdecl) == TYPE_DECL)
- newtype = oldtype;
-
- if (TREE_CODE (newdecl) == VAR_DECL)
-@@ -8193,7 +8193,9 @@
- abi_1_itype = error_mark_node;
- }
-
-- size = maybe_constant_value (size);
-+ if (INTEGRAL_OR_UNSCOPED_ENUMERATION_TYPE_P (type))
-+ size = maybe_constant_value (size);
-+
- if (!TREE_CONSTANT (size))
- size = osize;
- }
-@@ -8473,6 +8475,14 @@
- return error_mark_node;
- }
-
-+ /* 8.3.4p1: ...if the type of the identifier of D contains the auto
-+ type-specifier, the program is ill-formed. */
-+ if (type_uses_auto (type))
-+ {
-+ error ("%qD declared as array of %qT", name, type);
-+ return error_mark_node;
-+ }
-+
- /* Figure out the index type for the array. */
- if (size)
- itype = compute_array_index_type (name, size, tf_warning_or_error);
-@@ -11891,7 +11901,10 @@
-
- if (decl
- && (DECL_CLASS_TEMPLATE_P (decl)
-- || DECL_TEMPLATE_TEMPLATE_PARM_P (decl)))
-+ /* If scope is ts_current we're defining a class, so ignore a
-+ template template parameter. */
-+ || (scope != ts_current
-+ && DECL_TEMPLATE_TEMPLATE_PARM_P (decl))))
- decl = DECL_TEMPLATE_RESULT (decl);
-
- if (decl && TREE_CODE (decl) == TYPE_DECL)
-Index: gcc/cp/except.c
-===================================================================
---- a/src/gcc/cp/except.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/except.c (.../branches/gcc-4_8-branch)
-@@ -380,6 +380,9 @@
- {
- tree type = body ? TREE_TYPE (body) : void_type_node;
-
-+ if (!flag_exceptions)
-+ return body;
-+
- if (cond && !value_dependent_expression_p (cond))
- {
- cond = cxx_constant_value (cond);
-Index: gcc/cp/ChangeLog
-===================================================================
---- a/src/gcc/cp/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,268 @@
-+2014-05-13 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/60708
-+ * call.c (build_array_conv): Call complete_type.
-+
-+ PR c++/60713
-+ * typeck2.c (PICFLAG_SIDE_EFFECTS): New.
-+ (picflag_from_initializer): Return it.
-+ (process_init_constructor): Handle it.
-+
-+ PR c++/60628
-+ * decl.c (create_array_type_for_decl): Complain about array of auto.
-+
-+ PR c++/60367
-+ * call.c (convert_default_arg): Remove special handling for
-+ CONSTRUCTOR.
-+
-+2014-04-28 Daniel Gutson <daniel.gutson@tallertechnologies.com>
-+
-+ * typeck.c (build_reinterpret_cast_1): Pass proper argument to
-+ warn() in pedantic.
-+
-+2014-02-28 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/58845
-+ * typeck.c (cp_build_binary_op): Sorry on vector&&vector.
-+
-+2014-02-26 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/60182
-+ * pt.c (unify): Ignore alias templates when deducing a template
-+ template parameter.
-+
-+2014-02-24 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/60146
-+ * pt.c (tsubst_omp_for_iterator): Don't let substitution of the
-+ DECL_EXPR initialize a non-class iterator.
-+
-+2014-02-24 Fabien Chêne <fabien@gcc.gnu.org>
-+ PR c++/37140
-+ * parser.c (cp_parser_nonclass_name): Call strip_using_decl and
-+ move the code handling dependent USING_DECLs...
-+ * name-lookup.c (strip_using_decl): ...Here.
-+
-+2014-02-21 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/60108
-+ * semantics.c (expand_or_defer_fn_1): Check DECL_DEFAULTED_FN.
-+
-+ PR c++/60187
-+ * parser.c (cp_parser_enum_specifier): Call
-+ check_for_bare_parameter_packs.
-+
-+ PR c++/60216
-+ * pt.c (register_specialization): Copy DECL_DELETED_FN to clones.
-+
-+ PR c++/60219
-+ * pt.c (coerce_template_parms): Bail if argument packing fails.
-+
-+ PR c++/60248
-+ * mangle.c (mangle_decl): Don't make an alias for a TYPE_DECL.
-+
-+2014-02-20 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/60274
-+ Revert:
-+ PR c++/58606
-+ * pt.c (template_parm_to_arg): Call convert_from_reference.
-+ (tsubst_template_arg): Don't strip reference refs.
-+
-+2014-02-20 Kai Tietz <ktietz@redhat.com>
-+
-+ PR c++/58873
-+ * parser.c (cp_parser_functional_cast): Treat NULL_TREE
-+ valued type argument as error_mark_node.
-+
-+ PR c++/58835
-+ * semantics.c (finish_fname): Handle error_mark_node.
-+
-+2014-02-19 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/60046
-+ * pt.c (maybe_instantiate_noexcept): Don't instantiate exception
-+ spec from template context.
-+
-+2014-01-31 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/58672
-+ * decl2.c (handle_tls_init): Handle null init fn.
-+
-+ PR c++/55800
-+ * decl2.c (get_tls_init_fn): Copy DECL_EXTERNAL from the variable.
-+
-+ PR c++/59646
-+ * call.c (convert_like_real) [ck_aggr]: Set TARGET_EXPR_LIST_INIT_P.
-+ [ck_list]: Check for error_mark_node.
-+
-+ PR c++/57043
-+ * pt.c (fn_type_unification): Don't do DEDUCE_EXACT check
-+ during partial ordering.
-+
-+2014-01-30 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/57899
-+ * pt.c (instantiate_template_1): Save/restore local_specializations.
-+
-+2014-01-29 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/59989
-+ * pt.c (expand_template_argument_pack): Correct
-+ non_default_args_count calculation.
-+
-+ PR c++/58466
-+ * pt.c (unify_pack_expansion): Call expand_template_argument_pack.
-+
-+2014-01-28 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/58632
-+ * decl.c (lookup_and_check_tag): Ignore template parameters if
-+ scope == ts_current.
-+ * pt.c (check_template_shadow): Don't complain about the injected
-+ class name.
-+
-+2014-01-27 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/54652
-+ * decl.c (duplicate_decls): Always use oldtype for TYPE_DECL.
-+
-+ PR c++/58504
-+ * pt.c (tsubst_copy_and_build) [TRAIT_EXPR]: Use tsubst for
-+ types.
-+
-+ PR c++/58606
-+ * pt.c (template_parm_to_arg): Call convert_from_reference.
-+ (tsubst_template_arg): Don't strip reference refs.
-+
-+ PR c++/58639
-+ * call.c (build_aggr_conv): Reject value-initialization of reference.
-+
-+ PR c++/58812
-+ * call.c (convert_like_real): Give helpful error about excess braces
-+ for reference binding, too.
-+
-+ PR c++/58814
-+ * typeck.c (cp_build_modify_expr): Make the RHS an rvalue before
-+ stabilizing.
-+
-+ PR c++/58837
-+ * typeck.c (cp_truthvalue_conversion): Use explicit comparison for
-+ FUNCTION_DECL.
-+
-+ PR c++/59097
-+ * decl.c (compute_array_index_type): Don't call
-+ maybe_constant_value for a non-integral expression.
-+
-+ PR c++/58965
-+ * mangle.c (write_guarded_var_name): Handle null DECL_NAME.
-+
-+2014-01-24 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR c++/57524
-+ * name-lookup.c (push_using_directive): Use timevar_cond_start.
-+
-+2014-01-23 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR middle-end/58809
-+ * semantics.c (finish_omp_clauses): Reject MIN_EXPR, MAX_EXPR,
-+ BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs.
-+
-+2014-01-20 Marek Polacek <polacek@redhat.com>
-+
-+ Backported from mainline
-+ 2014-01-17 Marek Polacek <polacek@redhat.com>
-+
-+ PR c++/59838
-+ * cvt.c (ocp_convert): Don't segfault on non-existing
-+ ENUM_UNDERLYING_TYPE.
-+
-+2014-01-10 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR c++/56060
-+ PR c++/59730
-+ * pt.c (type_dependent_expression_p): Handle EXPR_PACK_EXPANSION.
-+
-+2013-12-12 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/58954
-+ * pt.c (resolve_overloaded_unification): Discard access checks.
-+
-+2013-12-05 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/59044
-+ PR c++/59052
-+ * pt.c (most_specialized_class): Use the partially instantiated
-+ template for deduction. Drop the TMPL parameter.
-+
-+2013-12-04 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c++/59268
-+ * pt.c (tsubst_copy_and_build): Handle POINTER_PLUS_EXPR.
-+
-+2013-11-27 Tom de Vries <tom@codesourcery.com>
-+ Marc Glisse <marc.glisse@inria.fr>
-+
-+ PR c++/59032
-+ * typeck.c (cp_build_unary_op): Allow vector increment and decrement.
-+
-+2013-11-27 Tom de Vries <tom@codesourcery.com>
-+ Marc Glisse <marc.glisse@inria.fr>
-+
-+ PR middle-end/59037
-+ * semantics.c (cxx_fold_indirect_ref): Don't create out-of-bounds
-+ BIT_FIELD_REF.
-+
-+2013-11-28 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR c++/59297
-+ * semantics.c (finish_omp_atomic): Call finish_expr_stmt
-+ rather than add_stmt.
-+
-+2013-11-23 Easwaran Raman <eraman@google.com>
-+
-+ PR c++/59031
-+ * call.c (build_new_method_call_1): Comnpare function context
-+ with BASELINK_BINFO type rather than instance type before
-+ marking the call with LOOKUP_NONVIRTUAL.
-+
-+2013-10-31 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/58162
-+ * parser.c (cp_parser_late_parse_one_default_arg): Set
-+ TARGET_EXPR_DIRECT_INIT_P.
-+
-+2013-11-11 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ * cvt.c (cp_convert_to_pointer): Call build_ptrmemfunc before
-+ maybe_warn_zero_as_null_pointer_constant to avoid duplicate
-+ -Wzero-as-null-pointer-constant diagnostics.
-+
-+ * typeck.c (build_ptrmemfunc): Use cp_build_c_cast.
-+
-+2013-10-25 Tom de Vries <tom@codesourcery.com>
-+
-+ PR c++/58282
-+ * except.c (build_must_not_throw_expr): Handle
-+ flag_exceptions.
-+
-+2013-10-17 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR c++/58596
-+ * semantics.c (lambda_expr_this_capture): Handle NSDMIs in the
-+ cp_unevaluated_operand case.
-+
-+2013-10-16 Paolo Carlini <paolo.carlini@oracle.com>
-+
-+ PR c++/58633
-+ * parser.c (cp_parser_pseudo_destructor_name): Revert r174385 changes.
-+
-+2013-10-16 Jason Merrill <jason@redhat.com>
-+
-+ PR c++/57850
-+ * decl2.c (dump_tu): Split out from...
-+ (cp_write_global_declarations): ...here. Call it in PCH mode.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: gcc/cp/typeck2.c
-===================================================================
---- a/src/gcc/cp/typeck2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/typeck2.c (.../branches/gcc-4_8-branch)
-@@ -1015,6 +1015,7 @@
- #define PICFLAG_ERRONEOUS 1
- #define PICFLAG_NOT_ALL_CONSTANT 2
- #define PICFLAG_NOT_ALL_SIMPLE 4
-+#define PICFLAG_SIDE_EFFECTS 8
-
- /* Given an initializer INIT, return the flag (PICFLAG_*) which better
- describe it. */
-@@ -1025,7 +1026,12 @@
- if (init == error_mark_node)
- return PICFLAG_ERRONEOUS;
- else if (!TREE_CONSTANT (init))
-- return PICFLAG_NOT_ALL_CONSTANT;
-+ {
-+ if (TREE_SIDE_EFFECTS (init))
-+ return PICFLAG_SIDE_EFFECTS;
-+ else
-+ return PICFLAG_NOT_ALL_CONSTANT;
-+ }
- else if (!initializer_constant_valid_p (init, TREE_TYPE (init)))
- return PICFLAG_NOT_ALL_SIMPLE;
- return 0;
-@@ -1392,7 +1398,12 @@
- TREE_TYPE (init) = type;
- if (TREE_CODE (type) == ARRAY_TYPE && TYPE_DOMAIN (type) == NULL_TREE)
- cp_complete_array_type (&TREE_TYPE (init), init, /*do_default=*/0);
-- if (flags & PICFLAG_NOT_ALL_CONSTANT)
-+ if (flags & PICFLAG_SIDE_EFFECTS)
-+ {
-+ TREE_CONSTANT (init) = false;
-+ TREE_SIDE_EFFECTS (init) = true;
-+ }
-+ else if (flags & PICFLAG_NOT_ALL_CONSTANT)
- /* Make sure TREE_CONSTANT isn't set from build_constructor. */
- TREE_CONSTANT (init) = false;
- else
-Index: gcc/cp/pt.c
-===================================================================
---- a/src/gcc/cp/pt.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/pt.c (.../branches/gcc-4_8-branch)
-@@ -170,7 +170,7 @@
- static tree tsubst_template_args (tree, tree, tsubst_flags_t, tree);
- static tree tsubst_template_parms (tree, tree, tsubst_flags_t);
- static void regenerate_decl_from_template (tree, tree);
--static tree most_specialized_class (tree, tree, tsubst_flags_t);
-+static tree most_specialized_class (tree, tsubst_flags_t);
- static tree tsubst_aggr_type (tree, tree, tsubst_flags_t, tree, int);
- static tree tsubst_arg_types (tree, tree, tree, tsubst_flags_t, tree);
- static tree tsubst_function_type (tree, tree, tsubst_flags_t, tree);
-@@ -1419,6 +1419,8 @@
- = DECL_DECLARED_INLINE_P (fn);
- DECL_SOURCE_LOCATION (clone)
- = DECL_SOURCE_LOCATION (fn);
-+ DECL_DELETED_FN (clone)
-+ = DECL_DELETED_FN (fn);
- }
- check_specialization_namespace (tmpl);
-
-@@ -3436,7 +3438,7 @@
- for (i = 0; i < num_packed; ++i, ++out_arg)
- TREE_VEC_ELT (result_args, out_arg) = TREE_VEC_ELT(packed, i);
- if (non_default_args_count > 0)
-- non_default_args_count += num_packed;
-+ non_default_args_count += num_packed - 1;
- }
- else
- {
-@@ -3491,6 +3493,11 @@
- || TEMPLATE_PARMS_FOR_INLINE (current_template_parms))
- return true;
-
-+ /* Don't complain about the injected class name, as we've already
-+ complained about the class itself. */
-+ if (DECL_SELF_REFERENCE_P (decl))
-+ return false;
-+
- error ("declaration of %q+#D", decl);
- error (" shadows template parm %q+#D", olddecl);
- return false;
-@@ -4261,7 +4268,7 @@
- if (COMPLETE_TYPE_P (inst_type)
- && CLASSTYPE_IMPLICIT_INSTANTIATION (inst_type))
- {
-- tree spec = most_specialized_class (inst_type, maintmpl, tf_none);
-+ tree spec = most_specialized_class (inst_type, tf_none);
- if (spec && TREE_TYPE (spec) == type)
- permerror (input_location,
- "partial specialization of %qT after instantiation "
-@@ -6672,6 +6679,8 @@
- /* Store this argument. */
- if (arg == error_mark_node)
- lost++;
-+ if (lost)
-+ break;
- TREE_VEC_ELT (new_inner_args, parm_idx) = arg;
-
- /* We are done with all of the arguments. */
-@@ -8572,7 +8581,7 @@
-
- /* Determine what specialization of the original template to
- instantiate. */
-- t = most_specialized_class (type, templ, tf_warning_or_error);
-+ t = most_specialized_class (type, tf_warning_or_error);
- if (t == error_mark_node)
- {
- TYPE_BEING_DEFINED (type) = 1;
-@@ -12694,27 +12703,43 @@
- tsubst_expr ((NODE), args, complain, in_decl, \
- integral_constant_expression_p)
- tree decl, init, cond, incr;
-- bool init_decl;
-
- init = TREE_VEC_ELT (OMP_FOR_INIT (t), i);
- gcc_assert (TREE_CODE (init) == MODIFY_EXPR);
- decl = TREE_OPERAND (init, 0);
- init = TREE_OPERAND (init, 1);
-- /* Do this before substituting into decl to handle 'auto'. */
-- init_decl = (init && TREE_CODE (init) == DECL_EXPR);
-- init = RECUR (init);
-- decl = RECUR (decl);
-- if (init_decl)
-+ tree decl_expr = NULL_TREE;
-+ if (init && TREE_CODE (init) == DECL_EXPR)
- {
-- gcc_assert (!processing_template_decl);
-- init = DECL_INITIAL (decl);
-- DECL_INITIAL (decl) = NULL_TREE;
-+ /* We need to jump through some hoops to handle declarations in the
-+ for-init-statement, since we might need to handle auto deduction,
-+ but we need to keep control of initialization. */
-+ decl_expr = init;
-+ init = DECL_INITIAL (DECL_EXPR_DECL (init));
-+ decl = tsubst_decl (decl, args, complain);
- }
-+ else
-+ decl = RECUR (decl);
-+ init = RECUR (init);
-
-+ tree auto_node = type_uses_auto (TREE_TYPE (decl));
-+ if (auto_node && init)
-+ TREE_TYPE (decl)
-+ = do_auto_deduction (TREE_TYPE (decl), init, auto_node);
-+
- gcc_assert (!type_dependent_expression_p (decl));
-
- if (!CLASS_TYPE_P (TREE_TYPE (decl)))
- {
-+ if (decl_expr)
-+ {
-+ /* Declare the variable, but don't let that initialize it. */
-+ tree init_sav = DECL_INITIAL (DECL_EXPR_DECL (decl_expr));
-+ DECL_INITIAL (DECL_EXPR_DECL (decl_expr)) = NULL_TREE;
-+ RECUR (decl_expr);
-+ DECL_INITIAL (DECL_EXPR_DECL (decl_expr)) = init_sav;
-+ }
-+
- cond = RECUR (TREE_VEC_ELT (OMP_FOR_COND (t), i));
- incr = TREE_VEC_ELT (OMP_FOR_INCR (t), i);
- if (TREE_CODE (incr) == MODIFY_EXPR)
-@@ -12731,8 +12756,14 @@
- return;
- }
-
-- if (init && !init_decl)
-+ if (decl_expr)
- {
-+ /* Declare and initialize the variable. */
-+ RECUR (decl_expr);
-+ init = NULL_TREE;
-+ }
-+ else if (init)
-+ {
- tree c;
- for (c = *clauses; c ; c = OMP_CLAUSE_CHAIN (c))
- {
-@@ -13710,6 +13741,10 @@
- RETURN (r);
- }
-
-+ case POINTER_PLUS_EXPR:
-+ return fold_build_pointer_plus (RECUR (TREE_OPERAND (t, 0)),
-+ RECUR (TREE_OPERAND (t, 1)));
-+
- case SCOPE_REF:
- RETURN (tsubst_qualified_id (t, args, complain, in_decl, /*done=*/true,
- /*address_p=*/false));
-@@ -14471,12 +14506,12 @@
-
- case TRAIT_EXPR:
- {
-- tree type1 = tsubst_copy (TRAIT_EXPR_TYPE1 (t), args,
-- complain, in_decl);
-+ tree type1 = tsubst (TRAIT_EXPR_TYPE1 (t), args,
-+ complain, in_decl);
-
- tree type2 = TRAIT_EXPR_TYPE2 (t);
- if (type2)
-- type2 = tsubst_copy (type2, args, complain, in_decl);
-+ type2 = tsubst (type2, args, complain, in_decl);
-
- RETURN (finish_trait_expr (TRAIT_EXPR_KIND (t), type1, type2));
- }
-@@ -14778,6 +14813,8 @@
- /* Instantiation of the function happens in the context of the function
- template, not the context of the overload resolution we're doing. */
- push_to_top_level ();
-+ struct pointer_map_t *saved_local_specializations = local_specializations;
-+ local_specializations = NULL;
- /* If there are dependent arguments, e.g. because we're doing partial
- ordering, make sure processing_template_decl stays set. */
- if (uses_template_parms (targ_ptr))
-@@ -14793,6 +14830,7 @@
- targ_ptr, complain, gen_tmpl);
- if (DECL_CLASS_SCOPE_P (gen_tmpl))
- pop_nested_class ();
-+ local_specializations = saved_local_specializations;
- pop_from_top_level ();
-
- if (fndecl == error_mark_node)
-@@ -15192,8 +15230,11 @@
-
- /* If we're looking for an exact match, check that what we got
- is indeed an exact match. It might not be if some template
-- parameters are used in non-deduced contexts. */
-- if (strict == DEDUCE_EXACT)
-+ parameters are used in non-deduced contexts. But don't check
-+ for an exact match if we have dependent template arguments;
-+ in that case we're doing partial ordering, and we already know
-+ that we have two candidates that will provide the actual type. */
-+ if (strict == DEDUCE_EXACT && !any_dependent_template_arguments_p (targs))
- {
- tree substed = TREE_TYPE (decl);
- unsigned int i;
-@@ -15749,7 +15790,7 @@
- if (subargs != error_mark_node
- && !any_dependent_template_arguments_p (subargs))
- {
-- elem = tsubst (TREE_TYPE (fn), subargs, tf_none, NULL_TREE);
-+ elem = TREE_TYPE (instantiate_template (fn, subargs, tf_none));
- if (try_one_overload (tparms, targs, tempargs, parm,
- elem, strict, sub_strict, addr_p, explain_p)
- && (!goodfn || !same_type_p (goodfn, elem)))
-@@ -16207,6 +16248,9 @@
- tree pattern = PACK_EXPANSION_PATTERN (parm);
- tree pack, packs = NULL_TREE;
- int i, start = TREE_VEC_LENGTH (packed_parms) - 1;
-+
-+ packed_args = expand_template_argument_pack (packed_args);
-+
- int len = TREE_VEC_LENGTH (packed_args);
-
- /* Determine the parameter packs we will be deducing from the
-@@ -16574,9 +16618,11 @@
- if (TREE_CODE (arg) != BOUND_TEMPLATE_TEMPLATE_PARM
- && !CLASSTYPE_SPECIALIZATION_OF_PRIMARY_TEMPLATE_P (arg))
- return unify_template_deduction_failure (explain_p, parm, arg);
--
- {
- tree parmvec = TYPE_TI_ARGS (parm);
-+ /* An alias template name is never deduced. */
-+ if (TYPE_ALIAS_P (arg))
-+ arg = strip_typedefs (arg);
- tree argvec = INNERMOST_TEMPLATE_ARGS (TYPE_TI_ARGS (arg));
- tree full_argvec = add_to_template_args (targs, argvec);
- tree parm_parms
-@@ -17553,7 +17599,7 @@
- return -1;
- }
-
--/* Determine which of two partial specializations of MAIN_TMPL is more
-+/* Determine which of two partial specializations of TMPL is more
- specialized.
-
- PAT1 is a TREE_LIST whose TREE_TYPE is the _TYPE node corresponding
-@@ -17569,7 +17615,7 @@
- two templates is more specialized. */
-
- static int
--more_specialized_class (tree main_tmpl, tree pat1, tree pat2)
-+more_specialized_class (tree tmpl, tree pat1, tree pat2)
- {
- tree targs;
- tree tmpl1, tmpl2;
-@@ -17584,7 +17630,7 @@
- types in the arguments, and we need our dependency check functions
- to behave correctly. */
- ++processing_template_decl;
-- targs = get_class_bindings (main_tmpl, TREE_VALUE (pat1),
-+ targs = get_class_bindings (tmpl, TREE_VALUE (pat1),
- CLASSTYPE_TI_ARGS (tmpl1),
- CLASSTYPE_TI_ARGS (tmpl2));
- if (targs)
-@@ -17593,7 +17639,7 @@
- any_deductions = true;
- }
-
-- targs = get_class_bindings (main_tmpl, TREE_VALUE (pat2),
-+ targs = get_class_bindings (tmpl, TREE_VALUE (pat2),
- CLASSTYPE_TI_ARGS (tmpl2),
- CLASSTYPE_TI_ARGS (tmpl1));
- if (targs)
-@@ -17673,7 +17719,7 @@
- }
-
- /* Return the innermost template arguments that, when applied to a partial
-- specialization of MAIN_TMPL whose innermost template parameters are
-+ specialization of TMPL whose innermost template parameters are
- TPARMS, and whose specialization arguments are SPEC_ARGS, yield the
- ARGS.
-
-@@ -17688,7 +17734,7 @@
- is bound to `double'. */
-
- static tree
--get_class_bindings (tree main_tmpl, tree tparms, tree spec_args, tree args)
-+get_class_bindings (tree tmpl, tree tparms, tree spec_args, tree args)
- {
- int i, ntparms = TREE_VEC_LENGTH (tparms);
- tree deduced_args;
-@@ -17728,8 +17774,8 @@
- `T' is `A' but unify () does not check whether `typename T::X'
- is `int'. */
- spec_args = tsubst (spec_args, deduced_args, tf_none, NULL_TREE);
-- spec_args = coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (main_tmpl),
-- spec_args, main_tmpl,
-+ spec_args = coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (tmpl),
-+ spec_args, tmpl,
- tf_none, false, false);
- if (spec_args == error_mark_node
- /* We only need to check the innermost arguments; the other
-@@ -17877,8 +17923,8 @@
- }
-
- /* Return the most specialized of the class template partial
-- specializations of TMPL which can produce TYPE, a specialization of
-- TMPL. The value returned is actually a TREE_LIST; the TREE_TYPE is
-+ specializations which can produce TYPE, a specialization of some class
-+ template. The value returned is actually a TREE_LIST; the TREE_TYPE is
- a _TYPE node corresponding to the partial specialization, while the
- TREE_PURPOSE is the set of template arguments that must be
- substituted into the TREE_TYPE in order to generate TYPE.
-@@ -17885,11 +17931,11 @@
-
- If the choice of partial specialization is ambiguous, a diagnostic
- is issued, and the error_mark_node is returned. If there are no
-- partial specializations of TMPL matching TYPE, then NULL_TREE is
-- returned. */
-+ partial specializations matching TYPE, then NULL_TREE is
-+ returned, indicating that the primary template should be used. */
-
- static tree
--most_specialized_class (tree type, tree tmpl, tsubst_flags_t complain)
-+most_specialized_class (tree type, tsubst_flags_t complain)
- {
- tree list = NULL_TREE;
- tree t;
-@@ -17896,11 +17942,11 @@
- tree champ;
- int fate;
- bool ambiguous_p;
-- tree args;
- tree outer_args = NULL_TREE;
-
-- tmpl = most_general_template (tmpl);
-- args = CLASSTYPE_TI_ARGS (type);
-+ tree tmpl = CLASSTYPE_TI_TEMPLATE (type);
-+ tree main_tmpl = most_general_template (tmpl);
-+ tree args = CLASSTYPE_TI_ARGS (type);
-
- /* For determining which partial specialization to use, only the
- innermost args are interesting. */
-@@ -17910,7 +17956,7 @@
- args = INNERMOST_TEMPLATE_ARGS (args);
- }
-
-- for (t = DECL_TEMPLATE_SPECIALIZATIONS (tmpl); t; t = TREE_CHAIN (t))
-+ for (t = DECL_TEMPLATE_SPECIALIZATIONS (main_tmpl); t; t = TREE_CHAIN (t))
- {
- tree partial_spec_args;
- tree spec_args;
-@@ -17944,8 +17990,7 @@
-
- partial_spec_args =
- coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (tmpl),
-- add_to_template_args (outer_args,
-- partial_spec_args),
-+ partial_spec_args,
- tmpl, tf_none,
- /*require_all_args=*/true,
- /*use_default_args=*/true);
-@@ -18553,6 +18598,10 @@
- {
- tree fntype, spec, noex, clone;
-
-+ /* Don't instantiate a noexcept-specification from template context. */
-+ if (processing_template_decl)
-+ return;
-+
- if (DECL_CLONED_FUNCTION_P (fn))
- fn = DECL_CLONED_FUNCTION (fn);
- fntype = TREE_TYPE (fn);
-@@ -19955,6 +20004,10 @@
- if (TREE_CODE (expression) == SCOPE_REF)
- return false;
-
-+ /* Always dependent, on the number of arguments if nothing else. */
-+ if (TREE_CODE (expression) == EXPR_PACK_EXPANSION)
-+ return true;
-+
- if (BASELINK_P (expression))
- expression = BASELINK_FUNCTIONS (expression);
-
-Index: gcc/cp/semantics.c
-===================================================================
---- a/src/gcc/cp/semantics.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/semantics.c (.../branches/gcc-4_8-branch)
-@@ -2501,7 +2501,8 @@
- tree decl;
-
- decl = fname_decl (input_location, C_RID_CODE (id), id);
-- if (processing_template_decl && current_function_decl)
-+ if (processing_template_decl && current_function_decl
-+ && decl != error_mark_node)
- decl = DECL_NAME (decl);
- return decl;
- }
-@@ -3853,7 +3854,7 @@
- linkage of all functions, and as that causes writes to
- the data mapped in from the PCH file, it's advantageous
- to mark the functions at this point. */
-- if (!DECL_IMPLICIT_INSTANTIATION (fn))
-+ if (!DECL_IMPLICIT_INSTANTIATION (fn) || DECL_DEFAULTED_FN (fn))
- {
- /* This function must have external linkage, as
- otherwise DECL_INTERFACE_KNOWN would have been
-@@ -4291,7 +4292,8 @@
- error ("%qE has invalid type for %<reduction%>", t);
- remove = true;
- }
-- else if (FLOAT_TYPE_P (TREE_TYPE (t)))
-+ else if (FLOAT_TYPE_P (TREE_TYPE (t))
-+ || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)
- {
- enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c);
- switch (r_code)
-@@ -4299,10 +4301,26 @@
- case PLUS_EXPR:
- case MULT_EXPR:
- case MINUS_EXPR:
-+ break;
- case MIN_EXPR:
- case MAX_EXPR:
-+ if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE)
-+ r_code = ERROR_MARK;
- break;
-+ case BIT_AND_EXPR:
-+ case BIT_XOR_EXPR:
-+ case BIT_IOR_EXPR:
- default:
-+ r_code = ERROR_MARK;
-+ break;
-+ case TRUTH_ANDIF_EXPR:
-+ case TRUTH_ORIF_EXPR:
-+ if (FLOAT_TYPE_P (TREE_TYPE (t)))
-+ r_code = ERROR_MARK;
-+ break;
-+ }
-+ if (r_code == ERROR_MARK)
-+ {
- error ("%qE has invalid type for %<reduction(%s)%>",
- t, operator_name_info[r_code].name);
- remove = true;
-@@ -5059,7 +5077,7 @@
- }
- stmt = build2 (OMP_ATOMIC, void_type_node, integer_zero_node, stmt);
- }
-- add_stmt (stmt);
-+ finish_expr_stmt (stmt);
- }
-
- void
-@@ -7543,7 +7561,7 @@
- unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT;
- tree index = bitsize_int (indexi);
-
-- if (offset/part_widthi <= TYPE_VECTOR_SUBPARTS (op00type))
-+ if (offset / part_widthi < TYPE_VECTOR_SUBPARTS (op00type))
- return fold_build3_loc (loc,
- BIT_FIELD_REF, type, op00,
- part_width, index);
-@@ -9481,7 +9499,14 @@
- /* In unevaluated context this isn't an odr-use, so just return the
- nearest 'this'. */
- if (cp_unevaluated_operand)
-- return lookup_name (this_identifier);
-+ {
-+ /* In an NSDMI the fake 'this' pointer that we're using for
-+ parsing is in scope_chain. */
-+ if (LAMBDA_EXPR_EXTRA_SCOPE (lambda)
-+ && TREE_CODE (LAMBDA_EXPR_EXTRA_SCOPE (lambda)) == FIELD_DECL)
-+ return scope_chain->x_current_class_ptr;
-+ return lookup_name (this_identifier);
-+ }
-
- /* Try to default capture 'this' if we can. */
- if (!this_capture
-Index: gcc/cp/decl2.c
-===================================================================
---- a/src/gcc/cp/decl2.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/decl2.c (.../branches/gcc-4_8-branch)
-@@ -2884,7 +2884,7 @@
- TREE_PUBLIC (fn) = TREE_PUBLIC (var);
- DECL_ARTIFICIAL (fn) = true;
- DECL_COMDAT (fn) = DECL_COMDAT (var);
-- DECL_EXTERNAL (fn) = true;
-+ DECL_EXTERNAL (fn) = DECL_EXTERNAL (var);
- if (DECL_ONE_ONLY (var))
- make_decl_one_only (fn, cxx_comdat_group (fn));
- if (TREE_PUBLIC (var))
-@@ -3946,6 +3946,8 @@
- if (TREE_PUBLIC (var))
- {
- tree single_init_fn = get_tls_init_fn (var);
-+ if (single_init_fn == NULL_TREE)
-+ continue;
- cgraph_node *alias
- = cgraph_same_body_alias (cgraph_get_create_node (fn),
- single_init_fn, fn);
-@@ -3960,6 +3962,22 @@
- expand_or_defer_fn (finish_function (0));
- }
-
-+/* The entire file is now complete. If requested, dump everything
-+ to a file. */
-+
-+static void
-+dump_tu (void)
-+{
-+ int flags;
-+ FILE *stream = dump_begin (TDI_tu, &flags);
-+
-+ if (stream)
-+ {
-+ dump_node (global_namespace, flags & ~TDF_SLIM, stream);
-+ dump_end (TDI_tu, stream);
-+ }
-+}
-+
- /* This routine is called at the end of compilation.
- Its job is to create all the code needed to initialize and
- destroy the global aggregates. We do the destruction
-@@ -3990,6 +4008,7 @@
- if (pch_file)
- {
- c_common_write_pch ();
-+ dump_tu ();
- return;
- }
-
-@@ -4359,17 +4378,8 @@
-
- /* The entire file is now complete. If requested, dump everything
- to a file. */
-- {
-- int flags;
-- FILE *stream = dump_begin (TDI_tu, &flags);
-+ dump_tu ();
-
-- if (stream)
-- {
-- dump_node (global_namespace, flags & ~TDF_SLIM, stream);
-- dump_end (TDI_tu, stream);
-- }
-- }
--
- if (flag_detailed_statistics)
- {
- dump_tree_statistics ();
-Index: gcc/cp/parser.c
-===================================================================
---- a/src/gcc/cp/parser.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/parser.c (.../branches/gcc-4_8-branch)
-@@ -6421,10 +6421,6 @@
- /* Look for the `~'. */
- cp_parser_require (parser, CPP_COMPL, RT_COMPL);
-
-- /* Once we see the ~, this has to be a pseudo-destructor. */
-- if (!processing_template_decl && !cp_parser_error_occurred (parser))
-- cp_parser_commit_to_tentative_parse (parser);
--
- /* Look for the type-name again. We are not responsible for
- checking that it matches the first type-name. */
- *type = cp_parser_nonclass_name (parser);
-@@ -14168,25 +14164,7 @@
- /* Look up the type-name. */
- type_decl = cp_parser_lookup_name_simple (parser, identifier, token->location);
-
-- if (TREE_CODE (type_decl) == USING_DECL)
-- {
-- if (!DECL_DEPENDENT_P (type_decl))
-- type_decl = strip_using_decl (type_decl);
-- else if (USING_DECL_TYPENAME_P (type_decl))
-- {
-- /* We have found a type introduced by a using
-- declaration at class scope that refers to a dependent
-- type.
--
-- using typename :: [opt] nested-name-specifier unqualified-id ;
-- */
-- type_decl = make_typename_type (TREE_TYPE (type_decl),
-- DECL_NAME (type_decl),
-- typename_type, tf_error);
-- if (type_decl != error_mark_node)
-- type_decl = TYPE_NAME (type_decl);
-- }
-- }
-+ type_decl = strip_using_decl (type_decl);
-
- if (TREE_CODE (type_decl) != TYPE_DECL
- && (objc_is_id (identifier) || objc_is_class_name (identifier)))
-@@ -14742,7 +14720,8 @@
- {
- underlying_type = grokdeclarator (NULL, &type_specifiers, TYPENAME,
- /*initialized=*/0, NULL);
-- if (underlying_type == error_mark_node)
-+ if (underlying_type == error_mark_node
-+ || check_for_bare_parameter_packs (underlying_type))
- underlying_type = NULL_TREE;
- }
- }
-@@ -22209,6 +22188,9 @@
- tree cast;
- bool nonconst_p;
-
-+ if (!type)
-+ type = error_mark_node;
-+
- if (cp_lexer_next_token_is (parser->lexer, CPP_OPEN_BRACE))
- {
- maybe_warn_cpp0x (CPP0X_INITIALIZER_LISTS);
-@@ -22576,6 +22558,9 @@
- && CONSTRUCTOR_IS_DIRECT_INIT (parsed_arg))
- flags = LOOKUP_NORMAL;
- parsed_arg = digest_init_flags (TREE_TYPE (decl), parsed_arg, flags);
-+ if (TREE_CODE (parsed_arg) == TARGET_EXPR)
-+ /* This represents the whole initialization. */
-+ TARGET_EXPR_DIRECT_INIT_P (parsed_arg) = true;
- }
- }
-
-Index: gcc/cp/call.c
-===================================================================
---- a/src/gcc/cp/call.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/call.c (.../branches/gcc-4_8-branch)
-@@ -892,6 +892,9 @@
-
- if (i < CONSTRUCTOR_NELTS (ctor))
- val = CONSTRUCTOR_ELT (ctor, i)->value;
-+ else if (TREE_CODE (ftype) == REFERENCE_TYPE)
-+ /* Value-initialization of reference is ill-formed. */
-+ return NULL;
- else
- {
- if (empty_ctor == NULL_TREE)
-@@ -940,6 +943,9 @@
- bool user = false;
- enum conversion_rank rank = cr_exact;
-
-+ /* We might need to propagate the size from the element to the array. */
-+ complete_type (type);
-+
- if (TYPE_DOMAIN (type))
- {
- unsigned HOST_WIDE_INT alen = tree_low_cst (array_type_nelts_top (type), 1);
-@@ -5806,9 +5812,11 @@
- && convs->kind != ck_ambig
- && (convs->kind != ck_ref_bind
- || convs->user_conv_p)
-- && convs->kind != ck_rvalue
-+ && (convs->kind != ck_rvalue
-+ || SCALAR_TYPE_P (totype))
- && convs->kind != ck_base)
- {
-+ bool complained = false;
- conversion *t = convs;
-
- /* Give a helpful error if this is bad because of excess braces. */
-@@ -5816,7 +5824,14 @@
- && SCALAR_TYPE_P (totype)
- && CONSTRUCTOR_NELTS (expr) > 0
- && BRACE_ENCLOSED_INITIALIZER_P (CONSTRUCTOR_ELT (expr, 0)->value))
-- permerror (loc, "too many braces around initializer for %qT", totype);
-+ {
-+ complained = true;
-+ permerror (loc, "too many braces around initializer "
-+ "for %qT", totype);
-+ while (BRACE_ENCLOSED_INITIALIZER_P (expr)
-+ && CONSTRUCTOR_NELTS (expr) == 1)
-+ expr = CONSTRUCTOR_ELT (expr, 0)->value;
-+ }
-
- for (; t ; t = next_conversion (t))
- {
-@@ -5853,8 +5868,9 @@
- break;
- }
-
-- permerror (loc, "invalid conversion from %qT to %qT",
-- TREE_TYPE (expr), totype);
-+ if (!complained)
-+ permerror (loc, "invalid conversion from %qT to %qT",
-+ TREE_TYPE (expr), totype);
- if (fn)
- permerror (DECL_SOURCE_LOCATION (fn),
- " initializing argument %P of %qD", argnum, fn);
-@@ -5999,6 +6015,8 @@
- to avoid the error about taking the address of a temporary. */
- array = cp_build_addr_expr (array, complain);
- array = cp_convert (build_pointer_type (elttype), array, complain);
-+ if (array == error_mark_node)
-+ return error_mark_node;
-
- /* Build up the initializer_list object. */
- totype = complete_type (totype);
-@@ -6023,8 +6041,11 @@
- return fold_if_not_in_template (expr);
- }
- expr = reshape_init (totype, expr, complain);
-- return get_target_expr_sfinae (digest_init (totype, expr, complain),
-+ expr = get_target_expr_sfinae (digest_init (totype, expr, complain),
- complain);
-+ if (expr != error_mark_node)
-+ TARGET_EXPR_LIST_INIT_P (expr) = true;
-+ return expr;
-
- default:
- break;
-@@ -6405,20 +6426,10 @@
- /* We must make a copy of ARG, in case subsequent processing
- alters any part of it. */
- arg = break_out_target_exprs (arg);
-- if (TREE_CODE (arg) == CONSTRUCTOR)
-- {
-- arg = digest_init (type, arg, complain);
-- arg = convert_for_initialization (0, type, arg, LOOKUP_IMPLICIT,
-- ICR_DEFAULT_ARGUMENT, fn, parmnum,
-- complain);
-- }
-- else
-- {
-- arg = convert_for_initialization (0, type, arg, LOOKUP_IMPLICIT,
-- ICR_DEFAULT_ARGUMENT, fn, parmnum,
-- complain);
-- arg = convert_for_arg_passing (type, arg, complain);
-- }
-+ arg = convert_for_initialization (0, type, arg, LOOKUP_IMPLICIT,
-+ ICR_DEFAULT_ARGUMENT, fn, parmnum,
-+ complain);
-+ arg = convert_for_arg_passing (type, arg, complain);
- pop_deferring_access_checks();
-
- pop_defarg_context ();
-@@ -7414,7 +7425,7 @@
- struct z_candidate *candidates = 0, *cand;
- tree explicit_targs = NULL_TREE;
- tree basetype = NULL_TREE;
-- tree access_binfo;
-+ tree access_binfo, binfo;
- tree optype;
- tree first_mem_arg = NULL_TREE;
- tree instance_ptr;
-@@ -7454,6 +7465,7 @@
- if (!conversion_path)
- conversion_path = BASELINK_BINFO (fns);
- access_binfo = BASELINK_ACCESS_BINFO (fns);
-+ binfo = BASELINK_BINFO (fns);
- optype = BASELINK_OPTYPE (fns);
- fns = BASELINK_FUNCTIONS (fns);
- if (TREE_CODE (fns) == TEMPLATE_ID_EXPR)
-@@ -7697,13 +7709,13 @@
- {
- /* Optimize away vtable lookup if we know that this
- function can't be overridden. We need to check if
-- the context and the instance type are the same,
-+ the context and the type where we found fn are the same,
- actually FN might be defined in a different class
- type because of a using-declaration. In this case, we
- do not want to perform a non-virtual call. */
- if (DECL_VINDEX (fn) && ! (flags & LOOKUP_NONVIRTUAL)
- && same_type_ignoring_top_level_qualifiers_p
-- (DECL_CONTEXT (fn), TREE_TYPE (instance))
-+ (DECL_CONTEXT (fn), BINFO_TYPE (binfo))
- && resolves_to_fixed_type_p (instance, 0))
- flags |= LOOKUP_NONVIRTUAL;
- if (explicit_targs)
-Index: gcc/cp/cvt.c
-===================================================================
---- a/src/gcc/cp/cvt.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/cvt.c (.../branches/gcc-4_8-branch)
-@@ -203,13 +203,13 @@
-
- if (null_ptr_cst_p (expr))
- {
-- if (complain & tf_warning)
-- maybe_warn_zero_as_null_pointer_constant (expr, loc);
--
- if (TYPE_PTRMEMFUNC_P (type))
- return build_ptrmemfunc (TYPE_PTRMEMFUNC_FN_TYPE (type), expr, 0,
- /*c_cast_p=*/false, complain);
-
-+ if (complain & tf_warning)
-+ maybe_warn_zero_as_null_pointer_constant (expr, loc);
-+
- /* A NULL pointer-to-data-member is represented by -1, not by
- zero. */
- tree val = (TYPE_PTRDATAMEM_P (type)
-@@ -743,6 +743,7 @@
- unspecified. */
- if ((complain & tf_warning)
- && TREE_CODE (e) == INTEGER_CST
-+ && ENUM_UNDERLYING_TYPE (type)
- && !int_fits_type_p (e, ENUM_UNDERLYING_TYPE (type)))
- warning_at (loc, OPT_Wconversion,
- "the result of the conversion is unspecified because "
-Index: gcc/cp/mangle.c
-===================================================================
---- a/src/gcc/cp/mangle.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/mangle.c (.../branches/gcc-4_8-branch)
-@@ -3478,6 +3478,7 @@
-
- if (G.need_abi_warning
- /* Don't do this for a fake symbol we aren't going to emit anyway. */
-+ && TREE_CODE (decl) != TYPE_DECL
- && !DECL_MAYBE_IN_CHARGE_CONSTRUCTOR_P (decl)
- && !DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P (decl))
- {
-@@ -3773,7 +3774,8 @@
- static void
- write_guarded_var_name (const tree variable)
- {
-- if (strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0)
-+ if (DECL_NAME (variable)
-+ && strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0)
- /* The name of a guard variable for a reference temporary should refer
- to the reference, not the temporary. */
- write_string (IDENTIFIER_POINTER (DECL_NAME (variable)) + 4);
-Index: gcc/cp/cp-tree.h
-===================================================================
---- a/src/gcc/cp/cp-tree.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/cp-tree.h (.../branches/gcc-4_8-branch)
-@@ -344,7 +344,8 @@
- /* Returns true iff NODE is a BASELINK. */
- #define BASELINK_P(NODE) \
- (TREE_CODE (NODE) == BASELINK)
--/* The BINFO indicating the base from which the BASELINK_FUNCTIONS came. */
-+/* The BINFO indicating the base in which lookup found the
-+ BASELINK_FUNCTIONS. */
- #define BASELINK_BINFO(NODE) \
- (((struct tree_baselink*) BASELINK_CHECK (NODE))->binfo)
- /* The functions referred to by the BASELINK; either a FUNCTION_DECL,
-Index: gcc/cp/name-lookup.c
-===================================================================
---- a/src/gcc/cp/name-lookup.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cp/name-lookup.c (.../branches/gcc-4_8-branch)
-@@ -394,7 +394,8 @@
- }
- }
-
--/* Strip non dependent using declarations. */
-+/* Strip non dependent using declarations. If DECL is dependent,
-+ surreptitiously create a typename_type and return it. */
-
- tree
- strip_using_decl (tree decl)
-@@ -404,6 +405,23 @@
-
- while (TREE_CODE (decl) == USING_DECL && !DECL_DEPENDENT_P (decl))
- decl = USING_DECL_DECLS (decl);
-+
-+ if (TREE_CODE (decl) == USING_DECL && DECL_DEPENDENT_P (decl)
-+ && USING_DECL_TYPENAME_P (decl))
-+ {
-+ /* We have found a type introduced by a using
-+ declaration at class scope that refers to a dependent
-+ type.
-+
-+ using typename :: [opt] nested-name-specifier unqualified-id ;
-+ */
-+ decl = make_typename_type (TREE_TYPE (decl),
-+ DECL_NAME (decl),
-+ typename_type, tf_error);
-+ if (decl != error_mark_node)
-+ decl = TYPE_NAME (decl);
-+ }
-+
- return decl;
- }
-
-@@ -5605,9 +5623,9 @@
- push_using_directive (tree used)
- {
- tree ret;
-- timevar_start (TV_NAME_LOOKUP);
-+ bool subtime = timevar_cond_start (TV_NAME_LOOKUP);
- ret = push_using_directive_1 (used);
-- timevar_stop (TV_NAME_LOOKUP);
-+ timevar_cond_stop (TV_NAME_LOOKUP, subtime);
- return ret;
- }
-
-Index: gcc/builtins.def
-===================================================================
---- a/src/gcc/builtins.def (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/builtins.def (.../branches/gcc-4_8-branch)
-@@ -252,6 +252,9 @@
- DEF_LIB_BUILTIN (BUILT_IN_FABS, "fabs", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST)
- DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSF, "fabsf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST)
- DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSL, "fabsl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST)
-+DEF_GCC_BUILTIN (BUILT_IN_FABSD32, "fabsd32", BT_FN_DFLOAT32_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST)
-+DEF_GCC_BUILTIN (BUILT_IN_FABSD64, "fabsd64", BT_FN_DFLOAT64_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST)
-+DEF_GCC_BUILTIN (BUILT_IN_FABSD128, "fabsd128", BT_FN_DFLOAT128_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST)
- DEF_C99_BUILTIN (BUILT_IN_FDIM, "fdim", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO)
- DEF_C99_BUILTIN (BUILT_IN_FDIMF, "fdimf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO)
- DEF_C99_BUILTIN (BUILT_IN_FDIML, "fdiml", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO)
-Index: gcc/tree-ssa-loop-ivopts.c
-===================================================================
---- a/src/gcc/tree-ssa-loop-ivopts.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-loop-ivopts.c (.../branches/gcc-4_8-branch)
-@@ -4236,8 +4236,10 @@
- tree steptype = type;
- if (POINTER_TYPE_P (type))
- steptype = sizetype;
-+ steptype = unsigned_type_for (type);
-
-- tree_to_aff_combination (iv->step, steptype, &step);
-+ tree_to_aff_combination (iv->step, TREE_TYPE (iv->step), &step);
-+ aff_combination_convert (&step, steptype);
- tree_to_aff_combination (niter, TREE_TYPE (niter), &nit);
- aff_combination_convert (&nit, steptype);
- aff_combination_mult (&nit, &step, &delta);
-@@ -4245,6 +4247,8 @@
- aff_combination_add (&delta, &step);
-
- tree_to_aff_combination (iv->base, type, val);
-+ if (!POINTER_TYPE_P (type))
-+ aff_combination_convert (val, steptype);
- aff_combination_add (val, &delta);
- }
-
-@@ -4623,7 +4627,8 @@
-
- cand_value_at (loop, cand, use->stmt, desc->niter, &bnd);
-
-- *bound = aff_combination_to_tree (&bnd);
-+ *bound = fold_convert (TREE_TYPE (cand->iv->base),
-+ aff_combination_to_tree (&bnd));
- *comp = iv_elimination_compare (data, use);
-
- /* It is unlikely that computing the number of iterations using division
-Index: gcc/mode-switching.c
-===================================================================
---- a/src/gcc/mode-switching.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/mode-switching.c (.../branches/gcc-4_8-branch)
-@@ -568,12 +568,15 @@
-
- info[bb->index].computing = last_mode;
- /* Check for blocks without ANY mode requirements.
-- N.B. because of MODE_AFTER, last_mode might still be different
-- from no_mode. */
-+ N.B. because of MODE_AFTER, last_mode might still
-+ be different from no_mode, in which case we need to
-+ mark the block as nontransparent. */
- if (!any_set_required)
- {
- ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now);
- add_seginfo (info + bb->index, ptr);
-+ if (last_mode != no_mode)
-+ bitmap_clear_bit (transp[bb->index], j);
- }
- }
- #if defined (MODE_ENTRY) && defined (MODE_EXIT)
-Index: gcc/ipa-pure-const.c
-===================================================================
---- a/src/gcc/ipa-pure-const.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ipa-pure-const.c (.../branches/gcc-4_8-branch)
-@@ -588,7 +588,7 @@
- /* Wrapper around check_decl for loads in local more. */
-
- static bool
--check_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)
-+check_load (gimple, tree op, tree, void *data)
- {
- if (DECL_P (op))
- check_decl ((funct_state)data, op, false, false);
-@@ -600,7 +600,7 @@
- /* Wrapper around check_decl for stores in local more. */
-
- static bool
--check_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)
-+check_store (gimple, tree op, tree, void *data)
- {
- if (DECL_P (op))
- check_decl ((funct_state)data, op, true, false);
-@@ -612,7 +612,7 @@
- /* Wrapper around check_decl for loads in ipa mode. */
-
- static bool
--check_ipa_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)
-+check_ipa_load (gimple, tree op, tree, void *data)
- {
- if (DECL_P (op))
- check_decl ((funct_state)data, op, false, true);
-@@ -624,7 +624,7 @@
- /* Wrapper around check_decl for stores in ipa mode. */
-
- static bool
--check_ipa_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)
-+check_ipa_store (gimple, tree op, tree, void *data)
- {
- if (DECL_P (op))
- check_decl ((funct_state)data, op, true, true);
-Index: gcc/cse.c
-===================================================================
---- a/src/gcc/cse.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cse.c (.../branches/gcc-4_8-branch)
-@@ -1824,7 +1824,7 @@
- }
- }
-
--/* Function called for each rtx to check whether true dependence exist. */
-+/* Function called for each rtx to check whether an anti dependence exist. */
- struct check_dependence_data
- {
- enum machine_mode mode;
-@@ -1837,7 +1837,7 @@
- {
- struct check_dependence_data *d = (struct check_dependence_data *) data;
- if (*x && MEM_P (*x))
-- return canon_true_dependence (d->exp, d->mode, d->addr, *x, NULL_RTX);
-+ return canon_anti_dependence (*x, true, d->exp, d->mode, d->addr);
- else
- return 0;
- }
-@@ -5659,9 +5659,10 @@
- invalidate (XEXP (dest, 0), GET_MODE (dest));
- }
-
-- /* A volatile ASM or an UNSPEC_VOLATILE invalidates everything. */
-+ /* A volatile ASM invalidates everything. */
- if (NONJUMP_INSN_P (insn)
-- && volatile_insn_p (PATTERN (insn)))
-+ && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
-+ && MEM_VOLATILE_P (PATTERN (insn)))
- flush_hash_table ();
-
- /* Don't cse over a call to setjmp; on some machines (eg VAX)
-@@ -6082,6 +6083,18 @@
- return x;
- }
-
-+ case UNSIGNED_FLOAT:
-+ {
-+ rtx new_rtx = cse_process_notes (XEXP (x, 0), object, changed);
-+ /* We don't substitute negative VOIDmode constants into these rtx,
-+ since they would impede folding. */
-+ if (GET_MODE (new_rtx) != VOIDmode
-+ || (CONST_INT_P (new_rtx) && INTVAL (new_rtx) >= 0)
-+ || (CONST_DOUBLE_P (new_rtx) && CONST_DOUBLE_HIGH (new_rtx) >= 0))
-+ validate_change (object, &XEXP (x, 0), new_rtx, 0);
-+ return x;
-+ }
-+
- case REG:
- i = REG_QTY (REGNO (x));
-
-Index: gcc/tree-ssa-math-opts.c
-===================================================================
---- a/src/gcc/tree-ssa-math-opts.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-math-opts.c (.../branches/gcc-4_8-branch)
-@@ -1718,7 +1718,9 @@
-
- if (rhs_class == GIMPLE_BINARY_RHS)
- {
-+ int i;
- struct symbolic_number n1, n2;
-+ unsigned HOST_WIDEST_INT mask;
- tree source_expr2;
-
- if (code != BIT_IOR_EXPR)
-@@ -1744,6 +1746,15 @@
- return NULL_TREE;
-
- n->size = n1.size;
-+ for (i = 0, mask = 0xff; i < n->size; i++, mask <<= BITS_PER_UNIT)
-+ {
-+ unsigned HOST_WIDEST_INT masked1, masked2;
-+
-+ masked1 = n1.n & mask;
-+ masked2 = n2.n & mask;
-+ if (masked1 && masked2 && masked1 != masked2)
-+ return NULL_TREE;
-+ }
- n->n = n1.n | n2.n;
-
- if (!verify_symbolic_number_p (n, stmt))
-Index: gcc/tree-ssa-propagate.c
-===================================================================
---- a/src/gcc/tree-ssa-propagate.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-propagate.c (.../branches/gcc-4_8-branch)
-@@ -556,8 +556,18 @@
- /* All constants are ok. */
- break;
-
-+ case tcc_comparison:
-+ /* GENERIC allows comparisons with non-boolean types, reject
-+ those for GIMPLE. Let vector-typed comparisons pass - rules
-+ for GENERIC and GIMPLE are the same here. */
-+ if (!(INTEGRAL_TYPE_P (TREE_TYPE (expr))
-+ && (TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE
-+ || TYPE_PRECISION (TREE_TYPE (expr)) == 1))
-+ && TREE_CODE (TREE_TYPE (expr)) != VECTOR_TYPE)
-+ return false;
-+
-+ /* Fallthru. */
- case tcc_binary:
-- case tcc_comparison:
- if (!is_gimple_val (TREE_OPERAND (expr, 0))
- || !is_gimple_val (TREE_OPERAND (expr, 1)))
- return false;
-Index: gcc/sel-sched.c
-===================================================================
---- a/src/gcc/sel-sched.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/sel-sched.c (.../branches/gcc-4_8-branch)
-@@ -1253,7 +1253,7 @@
-
- if (!HARD_FRAME_POINTER_IS_FRAME_POINTER)
- add_to_hard_reg_set (&reg_rename_p->unavailable_hard_regs,
-- Pmode, HARD_FRAME_POINTER_IS_FRAME_POINTER);
-+ Pmode, HARD_FRAME_POINTER_REGNUM);
- }
-
- #ifdef STACK_REGS
-Index: gcc/gimple-low.c
-===================================================================
---- a/src/gcc/gimple-low.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/gimple-low.c (.../branches/gcc-4_8-branch)
-@@ -238,6 +238,7 @@
- break;
- arg = gimple_call_arg (stmt, i);
- if (p == error_mark_node
-+ || DECL_ARG_TYPE (p) == error_mark_node
- || arg == error_mark_node
- || (!types_compatible_p (DECL_ARG_TYPE (p), TREE_TYPE (arg))
- && !fold_convertible_p (DECL_ARG_TYPE (p), arg)))
-Index: gcc/tree-ssa-sink.c
-===================================================================
---- a/src/gcc/tree-ssa-sink.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-sink.c (.../branches/gcc-4_8-branch)
-@@ -559,7 +559,7 @@
- execute_sink_code (void)
- {
- loop_optimizer_init (LOOPS_NORMAL);
--
-+ split_critical_edges ();
- connect_infinite_loops_to_exit ();
- memset (&sink_stats, 0, sizeof (sink_stats));
- calculate_dominance_info (CDI_DOMINATORS);
-Index: gcc/config.in
-===================================================================
---- a/src/gcc/config.in (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config.in (.../branches/gcc-4_8-branch)
-@@ -363,6 +363,12 @@
- #endif
-
-
-+/* Define if your assembler supports the 'ud2' mnemonic. */
-+#ifndef USED_FOR_TARGET
-+#undef HAVE_AS_IX86_UD2
-+#endif
-+
-+
- /* Define if your assembler supports the lituse_jsrdirect relocation. */
- #ifndef USED_FOR_TARGET
- #undef HAVE_AS_JSRDIRECT_RELOCS
-@@ -375,6 +381,12 @@
- #endif
-
-
-+/* Define if your assembler supports LEON instructions. */
-+#ifndef USED_FOR_TARGET
-+#undef HAVE_AS_LEON
-+#endif
-+
-+
- /* Define if the assembler won't complain about a line such as # 0 "" 2. */
- #ifndef USED_FOR_TARGET
- #undef HAVE_AS_LINE_ZERO
-Index: gcc/ifcvt.c
-===================================================================
---- a/src/gcc/ifcvt.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ifcvt.c (.../branches/gcc-4_8-branch)
-@@ -115,7 +115,11 @@
-
- while (1)
- {
-- if (CALL_P (insn) || NONJUMP_INSN_P (insn))
-+ if ((CALL_P (insn) || NONJUMP_INSN_P (insn))
-+ /* Don't count USE/CLOBBER insns, flow_find_cross_jump etc.
-+ don't count them either and we need consistency. */
-+ && GET_CODE (PATTERN (insn)) != USE
-+ && GET_CODE (PATTERN (insn)) != CLOBBER)
- count++;
-
- if (insn == BB_END (bb))
-@@ -505,7 +509,10 @@
- n_insns -= 2 * n_matching;
- }
-
-- if (then_start && else_start)
-+ if (then_start
-+ && else_start
-+ && then_n_insns > n_matching
-+ && else_n_insns > n_matching)
- {
- int longest_match = MIN (then_n_insns - n_matching,
- else_n_insns - n_matching);
-Index: gcc/expr.c
-===================================================================
---- a/src/gcc/expr.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/expr.c (.../branches/gcc-4_8-branch)
-@@ -1994,12 +1994,14 @@
- HOST_WIDE_INT bytepos = INTVAL (XEXP (XVECEXP (src, 0, i), 1));
- enum machine_mode mode = GET_MODE (tmps[i]);
- unsigned int bytelen = GET_MODE_SIZE (mode);
-- unsigned int adj_bytelen = bytelen;
-+ unsigned int adj_bytelen;
- rtx dest = dst;
-
- /* Handle trailing fragments that run over the size of the struct. */
- if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)
- adj_bytelen = ssize - bytepos;
-+ else
-+ adj_bytelen = bytelen;
-
- if (GET_CODE (dst) == CONCAT)
- {
-@@ -2040,6 +2042,7 @@
- }
- }
-
-+ /* Handle trailing fragments that run over the size of the struct. */
- if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)
- {
- /* store_bit_field always takes its value from the lsb.
-@@ -2057,16 +2060,22 @@
- tmps[i] = expand_shift (RSHIFT_EXPR, mode, tmps[i],
- shift, tmps[i], 0);
- }
-- bytelen = adj_bytelen;
-+
-+ /* Make sure not to write past the end of the struct. */
-+ store_bit_field (dest,
-+ adj_bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,
-+ bytepos * BITS_PER_UNIT, ssize * BITS_PER_UNIT - 1,
-+ VOIDmode, tmps[i]);
- }
-
- /* Optimize the access just a bit. */
-- if (MEM_P (dest)
-- && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (dest))
-- || MEM_ALIGN (dest) >= GET_MODE_ALIGNMENT (mode))
-- && bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0
-- && bytelen == GET_MODE_SIZE (mode))
-+ else if (MEM_P (dest)
-+ && (!SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (dest))
-+ || MEM_ALIGN (dest) >= GET_MODE_ALIGNMENT (mode))
-+ && bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0
-+ && bytelen == GET_MODE_SIZE (mode))
- emit_move_insn (adjust_address (dest, mode, bytepos), tmps[i]);
-+
- else
- store_bit_field (dest, bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,
- 0, 0, mode, tmps[i]);
-@@ -3602,12 +3611,21 @@
- into a new pseudo. This constant may be used in different modes,
- and if not, combine will put things back together for us. */
- trunc_y = force_reg (srcmode, trunc_y);
-- emit_unop_insn (ic, x, trunc_y, UNKNOWN);
-+
-+ /* If x is a hard register, perform the extension into a pseudo,
-+ so that e.g. stack realignment code is aware of it. */
-+ rtx target = x;
-+ if (REG_P (x) && HARD_REGISTER_P (x))
-+ target = gen_reg_rtx (dstmode);
-+
-+ emit_unop_insn (ic, target, trunc_y, UNKNOWN);
- last_insn = get_last_insn ();
-
-- if (REG_P (x))
-+ if (REG_P (target))
- set_unique_reg_note (last_insn, REG_EQUAL, y);
-
-+ if (target != x)
-+ return emit_move_insn (x, target);
- return last_insn;
- }
-
-@@ -4551,19 +4569,19 @@
- - tree_low_cst (DECL_FIELD_BIT_OFFSET (repr), 1));
-
- /* If the adjustment is larger than bitpos, we would have a negative bit
-- position for the lower bound and this may wreak havoc later. This can
-- occur only if we have a non-null offset, so adjust offset and bitpos
-- to make the lower bound non-negative. */
-+ position for the lower bound and this may wreak havoc later. Adjust
-+ offset and bitpos to make the lower bound non-negative in that case. */
- if (bitoffset > *bitpos)
- {
- HOST_WIDE_INT adjust = bitoffset - *bitpos;
--
- gcc_assert ((adjust % BITS_PER_UNIT) == 0);
-- gcc_assert (*offset != NULL_TREE);
-
- *bitpos += adjust;
-- *offset
-- = size_binop (MINUS_EXPR, *offset, size_int (adjust / BITS_PER_UNIT));
-+ if (*offset == NULL_TREE)
-+ *offset = size_int (-adjust / BITS_PER_UNIT);
-+ else
-+ *offset
-+ = size_binop (MINUS_EXPR, *offset, size_int (adjust / BITS_PER_UNIT));
- *bitstart = 0;
- }
- else
-@@ -4668,8 +4686,7 @@
- expand_insn (icode, 2, ops);
- }
- else
-- store_bit_field (mem, GET_MODE_BITSIZE (mode),
-- 0, 0, 0, mode, reg);
-+ store_bit_field (mem, GET_MODE_BITSIZE (mode), 0, 0, 0, mode, reg);
- return;
- }
-
-@@ -4698,6 +4715,15 @@
- tem = get_inner_reference (to, &bitsize, &bitpos, &offset, &mode1,
- &unsignedp, &volatilep, true);
-
-+ /* Make sure bitpos is not negative, it can wreak havoc later. */
-+ if (bitpos < 0)
-+ {
-+ gcc_assert (offset == NULL_TREE);
-+ offset = size_int (bitpos >> (BITS_PER_UNIT == 8
-+ ? 3 : exact_log2 (BITS_PER_UNIT)));
-+ bitpos &= BITS_PER_UNIT - 1;
-+ }
-+
- if (TREE_CODE (to) == COMPONENT_REF
- && DECL_BIT_FIELD_TYPE (TREE_OPERAND (to, 1)))
- get_bit_range (&bitregion_start, &bitregion_end, to, &bitpos, &offset);
-Index: gcc/expr.h
-===================================================================
---- a/src/gcc/expr.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/expr.h (.../branches/gcc-4_8-branch)
-@@ -521,8 +521,8 @@
- rtx, int);
- #endif
-
--extern void locate_and_pad_parm (enum machine_mode, tree, int, int, tree,
-- struct args_size *,
-+extern void locate_and_pad_parm (enum machine_mode, tree, int, int, int,
-+ tree, struct args_size *,
- struct locate_and_pad_arg_data *);
-
- /* Return the CODE_LABEL rtx for a LABEL_DECL, creating it if necessary. */
-Index: gcc/go/go-gcc.cc
-===================================================================
---- a/src/gcc/go/go-gcc.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/go-gcc.cc (.../branches/gcc-4_8-branch)
-@@ -232,6 +232,9 @@
- Bexpression*
- convert_expression(Btype* type, Bexpression* expr, Location);
-
-+ Bexpression*
-+ function_code_expression(Bfunction*, Location);
-+
- // Statements.
-
- Bstatement*
-@@ -334,6 +337,17 @@
- Bexpression*
- label_address(Blabel*, Location);
-
-+ // Functions.
-+
-+ Bfunction*
-+ error_function()
-+ { return this->make_function(error_mark_node); }
-+
-+ Bfunction*
-+ function(Btype* fntype, const std::string& name, const std::string& asm_name,
-+ bool is_visible, bool is_declaration, bool is_inlinable,
-+ bool disable_split_stack, bool in_unique_section, Location);
-+
- private:
- // Make a Bexpression from a tree.
- Bexpression*
-@@ -350,6 +364,10 @@
- make_type(tree t)
- { return new Btype(t); }
-
-+ Bfunction*
-+ make_function(tree t)
-+ { return new Bfunction(t); }
-+
- Btype*
- fill_in_struct(Btype*, const std::vector<Btyped_identifier>&);
-
-@@ -966,6 +984,19 @@
- return tree_to_expr(ret);
- }
-
-+// Get the address of a function.
-+
-+Bexpression*
-+Gcc_backend::function_code_expression(Bfunction* bfunc, Location location)
-+{
-+ tree func = bfunc->get_tree();
-+ if (func == error_mark_node)
-+ return this->error_expression();
-+
-+ tree ret = build_fold_addr_expr_loc(location.gcc_location(), func);
-+ return this->make_expression(ret);
-+}
-+
- // An expression as a statement.
-
- Bstatement*
-@@ -1724,6 +1755,56 @@
- return this->make_expression(ret);
- }
-
-+// Declare or define a new function.
-+
-+Bfunction*
-+Gcc_backend::function(Btype* fntype, const std::string& name,
-+ const std::string& asm_name, bool is_visible,
-+ bool is_declaration, bool is_inlinable,
-+ bool disable_split_stack, bool in_unique_section,
-+ Location location)
-+{
-+ tree functype = fntype->get_tree();
-+ if (functype != error_mark_node)
-+ {
-+ gcc_assert(FUNCTION_POINTER_TYPE_P(functype));
-+ functype = TREE_TYPE(functype);
-+ }
-+ tree id = get_identifier_from_string(name);
-+ if (functype == error_mark_node || id == error_mark_node)
-+ return this->error_function();
-+
-+ tree decl = build_decl(location.gcc_location(), FUNCTION_DECL, id, functype);
-+ if (!asm_name.empty())
-+ SET_DECL_ASSEMBLER_NAME(decl, get_identifier_from_string(asm_name));
-+ if (is_visible)
-+ TREE_PUBLIC(decl) = 1;
-+ if (is_declaration)
-+ DECL_EXTERNAL(decl) = 1;
-+ else
-+ {
-+ tree restype = TREE_TYPE(functype);
-+ tree resdecl =
-+ build_decl(location.gcc_location(), RESULT_DECL, NULL_TREE, restype);
-+ DECL_ARTIFICIAL(resdecl) = 1;
-+ DECL_IGNORED_P(resdecl) = 1;
-+ DECL_CONTEXT(resdecl) = decl;
-+ DECL_RESULT(decl) = resdecl;
-+ }
-+ if (!is_inlinable)
-+ DECL_UNINLINABLE(decl) = 1;
-+ if (disable_split_stack)
-+ {
-+ tree attr = get_identifier("__no_split_stack__");
-+ DECL_ATTRIBUTES(decl) = tree_cons(attr, NULL_TREE, NULL_TREE);
-+ }
-+ if (in_unique_section)
-+ resolve_unique_section(decl, 0, 1);
-+
-+ go_preserve_from_gc(decl);
-+ return new Bfunction(decl);
-+}
-+
- // The single backend.
-
- static Gcc_backend gcc_backend;
-@@ -1799,3 +1880,9 @@
- {
- return bv->get_tree();
- }
-+
-+tree
-+function_to_tree(Bfunction* bf)
-+{
-+ return bf->get_tree();
-+}
-Index: gcc/go/ChangeLog
-===================================================================
---- a/src/gcc/go/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,22 @@
-+2013-12-11 Ian Lance Taylor <iant@google.com>
-+
-+ * go-lang.c (go_langhook_post_options): Disable sibling calls by
-+ default.
-+
-+2013-10-16 Ian Lance Taylor <iant@google.com>
-+
-+ Bring in from mainline:
-+
-+ 2013-10-11 Chris Manghane <cmang@google.com>
-+ * go-gcc.cc (Gcc_backend::function_code_expression): New
-+ function.
-+
-+ 2013-10-10 Chris Manghane <cmang@google.com>
-+ * go-gcc.cc (Backend::error_function): New function.
-+ (Backend::function): New function.
-+ (Backend::make_function): New function.
-+ (function_to_tree): New function.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: gcc/go/go-lang.c
-===================================================================
---- a/src/gcc/go/go-lang.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/go-lang.c (.../branches/gcc-4_8-branch)
-@@ -269,6 +269,10 @@
- if (flag_excess_precision_cmdline == EXCESS_PRECISION_DEFAULT)
- flag_excess_precision_cmdline = EXCESS_PRECISION_STANDARD;
-
-+ /* Tail call optimizations can confuse uses of runtime.Callers. */
-+ if (!global_options_set.x_flag_optimize_sibling_calls)
-+ global_options.x_flag_optimize_sibling_calls = 0;
-+
- /* Returning false means that the backend should be used. */
- return false;
- }
-Index: gcc/go/gofrontend/gogo.cc
-===================================================================
---- a/src/gcc/go/gofrontend/gogo.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/gogo.cc (.../branches/gcc-4_8-branch)
-@@ -2822,7 +2822,10 @@
- if (orig_fntype->is_varargs())
- new_fntype->set_is_varargs();
-
-- std::string name = orig_no->name() + "$recover";
-+ std::string name = orig_no->name();
-+ if (orig_fntype->is_method())
-+ name += "$" + orig_fntype->receiver()->type()->mangled_name(gogo);
-+ name += "$recover";
- Named_object *new_no = gogo->start_function(name, new_fntype, false,
- location);
- Function *new_func = new_no->func_value();
-@@ -2916,7 +2919,25 @@
- && !orig_rec_no->var_value()->is_receiver());
- orig_rec_no->var_value()->set_is_receiver();
-
-- const std::string& new_receiver_name(orig_fntype->receiver()->name());
-+ std::string new_receiver_name(orig_fntype->receiver()->name());
-+ if (new_receiver_name.empty())
-+ {
-+ // Find the receiver. It was named "r.NNN" in
-+ // Gogo::start_function.
-+ for (Bindings::const_definitions_iterator p =
-+ new_bindings->begin_definitions();
-+ p != new_bindings->end_definitions();
-+ ++p)
-+ {
-+ const std::string& pname((*p)->name());
-+ if (pname[0] == 'r' && pname[1] == '.')
-+ {
-+ new_receiver_name = pname;
-+ break;
-+ }
-+ }
-+ go_assert(!new_receiver_name.empty());
-+ }
- Named_object* new_rec_no = new_bindings->lookup_local(new_receiver_name);
- if (new_rec_no == NULL)
- go_assert(saw_errors());
-@@ -3320,7 +3341,8 @@
- closure_var_(NULL), block_(block), location_(location), labels_(),
- local_type_count_(0), descriptor_(NULL), fndecl_(NULL), defer_stack_(NULL),
- is_sink_(false), results_are_named_(false), nointerface_(false),
-- calls_recover_(false), is_recover_thunk_(false), has_recover_thunk_(false),
-+ is_unnamed_type_stub_method_(false), calls_recover_(false),
-+ is_recover_thunk_(false), has_recover_thunk_(false),
- in_unique_section_(false)
- {
- }
-@@ -3819,6 +3841,81 @@
- *presults = results;
- }
-
-+// Get the backend representation.
-+
-+Bfunction*
-+Function::get_or_make_decl(Gogo* gogo, Named_object* no)
-+{
-+ if (this->fndecl_ == NULL)
-+ {
-+ std::string asm_name;
-+ bool is_visible = false;
-+ if (no->package() != NULL)
-+ ;
-+ else if (this->enclosing_ != NULL || Gogo::is_thunk(no))
-+ ;
-+ else if (Gogo::unpack_hidden_name(no->name()) == "init"
-+ && !this->type_->is_method())
-+ ;
-+ else if (Gogo::unpack_hidden_name(no->name()) == "main"
-+ && gogo->is_main_package())
-+ is_visible = true;
-+ // Methods have to be public even if they are hidden because
-+ // they can be pulled into type descriptors when using
-+ // anonymous fields.
-+ else if (!Gogo::is_hidden_name(no->name())
-+ || this->type_->is_method())
-+ {
-+ if (!this->is_unnamed_type_stub_method_)
-+ is_visible = true;
-+ std::string pkgpath = gogo->pkgpath_symbol();
-+ if (this->type_->is_method()
-+ && Gogo::is_hidden_name(no->name())
-+ && Gogo::hidden_name_pkgpath(no->name()) != gogo->pkgpath())
-+ {
-+ // This is a method we created for an unexported
-+ // method of an imported embedded type. We need to
-+ // use the pkgpath of the imported package to avoid
-+ // a possible name collision. See bug478 for a test
-+ // case.
-+ pkgpath = Gogo::hidden_name_pkgpath(no->name());
-+ pkgpath = Gogo::pkgpath_for_symbol(pkgpath);
-+ }
-+
-+ asm_name = pkgpath;
-+ asm_name.append(1, '.');
-+ asm_name.append(Gogo::unpack_hidden_name(no->name()));
-+ if (this->type_->is_method())
-+ {
-+ asm_name.append(1, '.');
-+ Type* rtype = this->type_->receiver()->type();
-+ asm_name.append(rtype->mangled_name(gogo));
-+ }
-+ }
-+
-+ // If a function calls the predeclared recover function, we
-+ // can't inline it, because recover behaves differently in a
-+ // function passed directly to defer. If this is a recover
-+ // thunk that we built to test whether a function can be
-+ // recovered, we can't inline it, because that will mess up
-+ // our return address comparison.
-+ bool is_inlinable = !(this->calls_recover_ || this->is_recover_thunk_);
-+
-+ // If this is a thunk created to call a function which calls
-+ // the predeclared recover function, we need to disable
-+ // stack splitting for the thunk.
-+ bool disable_split_stack = this->is_recover_thunk_;
-+
-+ Btype* functype = this->type_->get_backend_fntype(gogo);
-+ this->fndecl_ =
-+ gogo->backend()->function(functype, no->get_id(gogo), asm_name,
-+ is_visible, false, is_inlinable,
-+ disable_split_stack,
-+ this->in_unique_section_, this->location());
-+ }
-+ return this->fndecl_;
-+}
-+
- // Class Block.
-
- Block::Block(Block* enclosing, Location location)
-@@ -5110,6 +5207,75 @@
- go_unreachable();
- }
-
-+
-+// Return the external identifier for this object.
-+
-+std::string
-+Named_object::get_id(Gogo* gogo)
-+{
-+ go_assert(!this->is_variable() && !this->is_result_variable());
-+ std::string decl_name;
-+ if (this->is_function_declaration()
-+ && !this->func_declaration_value()->asm_name().empty())
-+ decl_name = this->func_declaration_value()->asm_name();
-+ else if (this->is_type()
-+ && Linemap::is_predeclared_location(this->type_value()->location()))
-+ {
-+ // We don't need the package name for builtin types.
-+ decl_name = Gogo::unpack_hidden_name(this->name_);
-+ }
-+ else
-+ {
-+ std::string package_name;
-+ if (this->package_ == NULL)
-+ package_name = gogo->package_name();
-+ else
-+ package_name = this->package_->package_name();
-+
-+ // Note that this will be misleading if this is an unexported
-+ // method generated for an embedded imported type. In that case
-+ // the unexported method should have the package name of the
-+ // package from which it is imported, but we are going to give
-+ // it our package name. Fixing this would require knowing the
-+ // package name, but we only know the package path. It might be
-+ // better to use package paths here anyhow. This doesn't affect
-+ // the assembler code, because we always set that name in
-+ // Function::get_or_make_decl anyhow. FIXME.
-+
-+ decl_name = package_name + '.' + Gogo::unpack_hidden_name(this->name_);
-+
-+ Function_type* fntype;
-+ if (this->is_function())
-+ fntype = this->func_value()->type();
-+ else if (this->is_function_declaration())
-+ fntype = this->func_declaration_value()->type();
-+ else
-+ fntype = NULL;
-+ if (fntype != NULL && fntype->is_method())
-+ {
-+ decl_name.push_back('.');
-+ decl_name.append(fntype->receiver()->type()->mangled_name(gogo));
-+ }
-+ }
-+ if (this->is_type())
-+ {
-+ unsigned int index;
-+ const Named_object* in_function = this->type_value()->in_function(&index);
-+ if (in_function != NULL)
-+ {
-+ decl_name += '$' + Gogo::unpack_hidden_name(in_function->name());
-+ if (index > 0)
-+ {
-+ char buf[30];
-+ snprintf(buf, sizeof buf, "%u", index);
-+ decl_name += '$';
-+ decl_name += buf;
-+ }
-+ }
-+ }
-+ return decl_name;
-+}
-+
- // Class Bindings.
-
- Bindings::Bindings(Bindings* enclosing)
-Index: gcc/go/gofrontend/runtime.def
-===================================================================
---- a/src/gcc/go/gofrontend/runtime.def (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/runtime.def (.../branches/gcc-4_8-branch)
-@@ -68,6 +68,12 @@
- P1(STRING), R1(SLICE))
-
-
-+// Complex division.
-+DEF_GO_RUNTIME(COMPLEX64_DIV, "__go_complex64_div",
-+ P2(COMPLEX64, COMPLEX64), R1(COMPLEX64))
-+DEF_GO_RUNTIME(COMPLEX128_DIV, "__go_complex128_div",
-+ P2(COMPLEX128, COMPLEX128), R1(COMPLEX128))
-+
- // Make a slice.
- DEF_GO_RUNTIME(MAKESLICE1, "__go_make_slice1", P2(TYPE, UINTPTR), R1(SLICE))
- DEF_GO_RUNTIME(MAKESLICE2, "__go_make_slice2", P3(TYPE, UINTPTR, UINTPTR),
-Index: gcc/go/gofrontend/gogo.h
-===================================================================
---- a/src/gcc/go/gofrontend/gogo.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/gogo.h (.../branches/gcc-4_8-branch)
-@@ -48,6 +48,7 @@
- class Bblock;
- class Bvariable;
- class Blabel;
-+class Bfunction;
-
- // This file declares the basic classes used to hold the internal
- // representation of Go which is built by the parser.
-@@ -952,6 +953,15 @@
- this->nointerface_ = true;
- }
-
-+ // Record that this function is a stub method created for an unnamed
-+ // type.
-+ void
-+ set_is_unnamed_type_stub_method()
-+ {
-+ go_assert(this->is_method());
-+ this->is_unnamed_type_stub_method_ = true;
-+ }
-+
- // Add a new field to the closure variable.
- void
- add_closure_field(Named_object* var, Location loc)
-@@ -1089,17 +1099,13 @@
- this->descriptor_ = descriptor;
- }
-
-- // Return the function's decl given an identifier.
-- tree
-- get_or_make_decl(Gogo*, Named_object*, tree id);
-+ // Return the backend representation.
-+ Bfunction*
-+ get_or_make_decl(Gogo*, Named_object*);
-
- // Return the function's decl after it has been built.
- tree
-- get_decl() const
-- {
-- go_assert(this->fndecl_ != NULL);
-- return this->fndecl_;
-- }
-+ get_decl() const;
-
- // Set the function decl to hold a tree of the function code.
- void
-@@ -1170,7 +1176,7 @@
- // The function descriptor, if any.
- Expression* descriptor_;
- // The function decl.
-- tree fndecl_;
-+ Bfunction* fndecl_;
- // The defer stack variable. A pointer to this variable is used to
- // distinguish the defer stack for one function from another. This
- // is NULL unless we actually need a defer stack.
-@@ -1181,6 +1187,9 @@
- bool results_are_named_ : 1;
- // True if this method should not be included in the type descriptor.
- bool nointerface_ : 1;
-+ // True if this function is a stub method created for an unnamed
-+ // type.
-+ bool is_unnamed_type_stub_method_ : 1;
- // True if this function calls the predeclared recover function.
- bool calls_recover_ : 1;
- // True if this a thunk built for a function which calls recover.
-@@ -1265,9 +1274,9 @@
- has_descriptor() const
- { return this->descriptor_ != NULL; }
-
-- // Return a decl for the function given an identifier.
-- tree
-- get_or_make_decl(Gogo*, Named_object*, tree id);
-+ // Return a backend representation.
-+ Bfunction*
-+ get_or_make_decl(Gogo*, Named_object*);
-
- // If there is a descriptor, build it into the backend
- // representation.
-@@ -1290,7 +1299,7 @@
- // The function descriptor, if any.
- Expression* descriptor_;
- // The function decl if needed.
-- tree fndecl_;
-+ Bfunction* fndecl_;
- };
-
- // A variable.
-@@ -2181,8 +2190,8 @@
- Bvariable*
- get_backend_variable(Gogo*, Named_object* function);
-
-- // Return a tree for the external identifier for this object.
-- tree
-+ // Return the external identifier for this object.
-+ std::string
- get_id(Gogo*);
-
- // Return a tree representing this object.
-Index: gcc/go/gofrontend/types.h
-===================================================================
---- a/src/gcc/go/gofrontend/types.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/types.h (.../branches/gcc-4_8-branch)
-@@ -1138,6 +1138,13 @@
- Function_type* equal_fntype, Named_object** hash_fn,
- Named_object** equal_fn);
-
-+ void
-+ write_named_hash(Gogo*, Named_type*, Function_type* hash_fntype,
-+ Function_type* equal_fntype);
-+
-+ void
-+ write_named_equal(Gogo*, Named_type*);
-+
- // Build a composite literal for the uncommon type information.
- Expression*
- uncommon_type_constructor(Gogo*, Type* uncommon_type,
-@@ -1717,7 +1724,8 @@
- Typed_identifier_list* results, Location location)
- : Type(TYPE_FUNCTION),
- receiver_(receiver), parameters_(parameters), results_(results),
-- location_(location), is_varargs_(false), is_builtin_(false)
-+ location_(location), is_varargs_(false), is_builtin_(false),
-+ fnbtype_(NULL)
- { }
-
- // Get the receiver.
-@@ -1789,6 +1797,12 @@
- Function_type*
- copy_with_receiver(Type*) const;
-
-+ // Return a copy of this type with the receiver treated as the first
-+ // parameter. If WANT_POINTER_RECEIVER is true, the receiver is
-+ // forced to be a pointer.
-+ Function_type*
-+ copy_with_receiver_as_param(bool want_pointer_receiver) const;
-+
- // Return a copy of this type ignoring any receiver and using dummy
- // names for all parameters. This is used for thunks for method
- // values.
-@@ -1798,6 +1812,11 @@
- static Type*
- make_function_type_descriptor_type();
-
-+ // Return the backend representation of this function type. This is used
-+ // as the real type of a backend function declaration or defintion.
-+ Btype*
-+ get_backend_fntype(Gogo*);
-+
- protected:
- int
- do_traverse(Traverse*);
-@@ -1851,6 +1870,9 @@
- // Whether this is a special builtin function which can not simply
- // be called. This is used for len, cap, etc.
- bool is_builtin_;
-+ // The backend representation of this type for backend function
-+ // declarations and definitions.
-+ Btype* fnbtype_;
- };
-
- // The type of a pointer.
-@@ -1915,7 +1937,7 @@
- {
- public:
- explicit Struct_field(const Typed_identifier& typed_identifier)
-- : typed_identifier_(typed_identifier), tag_(NULL)
-+ : typed_identifier_(typed_identifier), tag_(NULL), is_imported_(false)
- { }
-
- // The field name.
-@@ -1926,6 +1948,10 @@
- bool
- is_field_name(const std::string& name) const;
-
-+ // Return whether this struct field is an unexported field named NAME.
-+ bool
-+ is_unexported_field_name(Gogo*, const std::string& name) const;
-+
- // Return whether this struct field is an embedded built-in type.
- bool
- is_embedded_builtin(Gogo*) const;
-@@ -1963,6 +1989,11 @@
- set_tag(const std::string& tag)
- { this->tag_ = new std::string(tag); }
-
-+ // Record that this field is defined in an imported struct.
-+ void
-+ set_is_imported()
-+ { this->is_imported_ = true; }
-+
- // Set the type. This is only used in error cases.
- void
- set_type(Type* type)
-@@ -1973,6 +2004,8 @@
- Typed_identifier typed_identifier_;
- // The field tag. This is NULL if the field has no tag.
- std::string* tag_;
-+ // Whether this field is defined in an imported struct.
-+ bool is_imported_;
- };
-
- // A list of struct fields.
-Index: gcc/go/gofrontend/parse.cc
-===================================================================
---- a/src/gcc/go/gofrontend/parse.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/parse.cc (.../branches/gcc-4_8-branch)
-@@ -744,6 +744,8 @@
- return NULL;
-
- Parse::Names names;
-+ if (receiver != NULL)
-+ names[receiver->name()] = receiver;
- if (params != NULL)
- this->check_signature_names(params, &names);
- if (results != NULL)
-Index: gcc/go/gofrontend/import.h
-===================================================================
---- a/src/gcc/go/gofrontend/import.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/import.h (.../branches/gcc-4_8-branch)
-@@ -149,6 +149,11 @@
- location() const
- { return this->location_; }
-
-+ // Return the package we are importing.
-+ Package*
-+ package() const
-+ { return this->package_; }
-+
- // Return the next character.
- int
- peek_char()
-Index: gcc/go/gofrontend/runtime.cc
-===================================================================
---- a/src/gcc/go/gofrontend/runtime.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/runtime.cc (.../branches/gcc-4_8-branch)
-@@ -42,6 +42,8 @@
- RFT_RUNE,
- // Go type float64, C type double.
- RFT_FLOAT64,
-+ // Go type complex64, C type __complex float.
-+ RFT_COMPLEX64,
- // Go type complex128, C type __complex double.
- RFT_COMPLEX128,
- // Go type string, C type struct __go_string.
-@@ -126,6 +128,10 @@
- t = Type::lookup_float_type("float64");
- break;
-
-+ case RFT_COMPLEX64:
-+ t = Type::lookup_complex_type("complex64");
-+ break;
-+
- case RFT_COMPLEX128:
- t = Type::lookup_complex_type("complex128");
- break;
-@@ -216,6 +222,7 @@
- case RFT_UINTPTR:
- case RFT_RUNE:
- case RFT_FLOAT64:
-+ case RFT_COMPLEX64:
- case RFT_COMPLEX128:
- case RFT_STRING:
- case RFT_POINTER:
-Index: gcc/go/gofrontend/expressions.h
-===================================================================
---- a/src/gcc/go/gofrontend/expressions.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/expressions.h (.../branches/gcc-4_8-branch)
-@@ -1514,8 +1514,8 @@
- closure()
- { return this->closure_; }
-
-- // Return a tree for the code for a function.
-- static tree
-+ // Return a backend expression for the code of a function.
-+ static Bexpression*
- get_code_pointer(Gogo*, Named_object* function, Location loc);
-
- protected:
-Index: gcc/go/gofrontend/gogo-tree.cc
-===================================================================
---- a/src/gcc/go/gofrontend/gogo-tree.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/gogo-tree.cc (.../branches/gcc-4_8-branch)
-@@ -985,74 +985,6 @@
- delete[] vec;
- }
-
--// Get a tree for the identifier for a named object.
--
--tree
--Named_object::get_id(Gogo* gogo)
--{
-- go_assert(!this->is_variable() && !this->is_result_variable());
-- std::string decl_name;
-- if (this->is_function_declaration()
-- && !this->func_declaration_value()->asm_name().empty())
-- decl_name = this->func_declaration_value()->asm_name();
-- else if (this->is_type()
-- && Linemap::is_predeclared_location(this->type_value()->location()))
-- {
-- // We don't need the package name for builtin types.
-- decl_name = Gogo::unpack_hidden_name(this->name_);
-- }
-- else
-- {
-- std::string package_name;
-- if (this->package_ == NULL)
-- package_name = gogo->package_name();
-- else
-- package_name = this->package_->package_name();
--
-- // Note that this will be misleading if this is an unexported
-- // method generated for an embedded imported type. In that case
-- // the unexported method should have the package name of the
-- // package from which it is imported, but we are going to give
-- // it our package name. Fixing this would require knowing the
-- // package name, but we only know the package path. It might be
-- // better to use package paths here anyhow. This doesn't affect
-- // the assembler code, because we always set that name in
-- // Function::get_or_make_decl anyhow. FIXME.
--
-- decl_name = package_name + '.' + Gogo::unpack_hidden_name(this->name_);
--
-- Function_type* fntype;
-- if (this->is_function())
-- fntype = this->func_value()->type();
-- else if (this->is_function_declaration())
-- fntype = this->func_declaration_value()->type();
-- else
-- fntype = NULL;
-- if (fntype != NULL && fntype->is_method())
-- {
-- decl_name.push_back('.');
-- decl_name.append(fntype->receiver()->type()->mangled_name(gogo));
-- }
-- }
-- if (this->is_type())
-- {
-- unsigned int index;
-- const Named_object* in_function = this->type_value()->in_function(&index);
-- if (in_function != NULL)
-- {
-- decl_name += '$' + Gogo::unpack_hidden_name(in_function->name());
-- if (index > 0)
-- {
-- char buf[30];
-- snprintf(buf, sizeof buf, "%u", index);
-- decl_name += '$';
-- decl_name += buf;
-- }
-- }
-- }
-- return get_identifier_from_string(decl_name);
--}
--
- // Get a tree for a named object.
-
- tree
-@@ -1067,11 +999,6 @@
- return error_mark_node;
- }
-
-- tree name;
-- if (this->classification_ == NAMED_OBJECT_TYPE)
-- name = NULL_TREE;
-- else
-- name = this->get_id(gogo);
- tree decl;
- switch (this->classification_)
- {
-@@ -1099,6 +1026,7 @@
- decl = error_mark_node;
- else if (INTEGRAL_TYPE_P(TREE_TYPE(expr_tree)))
- {
-+ tree name = get_identifier_from_string(this->get_id(gogo));
- decl = build_decl(named_constant->location().gcc_location(),
- CONST_DECL, name, TREE_TYPE(expr_tree));
- DECL_INITIAL(decl) = expr_tree;
-@@ -1161,7 +1089,7 @@
- case NAMED_OBJECT_FUNC:
- {
- Function* func = this->u_.func_value;
-- decl = func->get_or_make_decl(gogo, this, name);
-+ decl = function_to_tree(func->get_or_make_decl(gogo, this));
- if (decl != error_mark_node)
- {
- if (func->block() != NULL)
-@@ -1286,124 +1214,13 @@
- return block_tree;
- }
-
--// Get a tree for a function decl.
-+// Get the backend representation.
-
--tree
--Function::get_or_make_decl(Gogo* gogo, Named_object* no, tree id)
-+Bfunction*
-+Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no)
- {
-- if (this->fndecl_ == NULL_TREE)
-+ if (this->fndecl_ == NULL)
- {
-- tree functype = type_to_tree(this->type_->get_backend(gogo));
--
-- if (functype != error_mark_node)
-- {
-- // The type of a function comes back as a pointer to a
-- // struct whose first field is the function, but we want the
-- // real function type for a function declaration.
-- go_assert(POINTER_TYPE_P(functype)
-- && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE);
-- functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype)));
-- go_assert(FUNCTION_POINTER_TYPE_P(functype));
-- functype = TREE_TYPE(functype);
-- }
--
-- if (functype == error_mark_node)
-- this->fndecl_ = error_mark_node;
-- else
-- {
-- tree decl = build_decl(this->location().gcc_location(), FUNCTION_DECL,
-- id, functype);
--
-- this->fndecl_ = decl;
--
-- if (no->package() != NULL)
-- ;
-- else if (this->enclosing_ != NULL || Gogo::is_thunk(no))
-- ;
-- else if (Gogo::unpack_hidden_name(no->name()) == "init"
-- && !this->type_->is_method())
-- ;
-- else if (Gogo::unpack_hidden_name(no->name()) == "main"
-- && gogo->is_main_package())
-- TREE_PUBLIC(decl) = 1;
-- // Methods have to be public even if they are hidden because
-- // they can be pulled into type descriptors when using
-- // anonymous fields.
-- else if (!Gogo::is_hidden_name(no->name())
-- || this->type_->is_method())
-- {
-- TREE_PUBLIC(decl) = 1;
-- std::string pkgpath = gogo->pkgpath_symbol();
-- if (this->type_->is_method()
-- && Gogo::is_hidden_name(no->name())
-- && Gogo::hidden_name_pkgpath(no->name()) != gogo->pkgpath())
-- {
-- // This is a method we created for an unexported
-- // method of an imported embedded type. We need to
-- // use the pkgpath of the imported package to avoid
-- // a possible name collision. See bug478 for a test
-- // case.
-- pkgpath = Gogo::hidden_name_pkgpath(no->name());
-- pkgpath = Gogo::pkgpath_for_symbol(pkgpath);
-- }
--
-- std::string asm_name = pkgpath;
-- asm_name.append(1, '.');
-- asm_name.append(Gogo::unpack_hidden_name(no->name()));
-- if (this->type_->is_method())
-- {
-- asm_name.append(1, '.');
-- Type* rtype = this->type_->receiver()->type();
-- asm_name.append(rtype->mangled_name(gogo));
-- }
-- SET_DECL_ASSEMBLER_NAME(decl,
-- get_identifier_from_string(asm_name));
-- }
--
-- // Why do we have to do this in the frontend?
-- tree restype = TREE_TYPE(functype);
-- tree resdecl =
-- build_decl(this->location().gcc_location(), RESULT_DECL, NULL_TREE,
-- restype);
-- DECL_ARTIFICIAL(resdecl) = 1;
-- DECL_IGNORED_P(resdecl) = 1;
-- DECL_CONTEXT(resdecl) = decl;
-- DECL_RESULT(decl) = resdecl;
--
-- // If a function calls the predeclared recover function, we
-- // can't inline it, because recover behaves differently in a
-- // function passed directly to defer. If this is a recover
-- // thunk that we built to test whether a function can be
-- // recovered, we can't inline it, because that will mess up
-- // our return address comparison.
-- if (this->calls_recover_ || this->is_recover_thunk_)
-- DECL_UNINLINABLE(decl) = 1;
--
-- // If this is a thunk created to call a function which calls
-- // the predeclared recover function, we need to disable
-- // stack splitting for the thunk.
-- if (this->is_recover_thunk_)
-- {
-- tree attr = get_identifier("__no_split_stack__");
-- DECL_ATTRIBUTES(decl) = tree_cons(attr, NULL_TREE, NULL_TREE);
-- }
--
-- if (this->in_unique_section_)
-- resolve_unique_section (decl, 0, 1);
--
-- go_preserve_from_gc(decl);
-- }
-- }
-- return this->fndecl_;
--}
--
--// Get a tree for a function declaration.
--
--tree
--Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no, tree id)
--{
-- if (this->fndecl_ == NULL_TREE)
-- {
- // Let Go code use an asm declaration to pick up a builtin
- // function.
- if (!this->asm_name_.empty())
-@@ -1412,58 +1229,46 @@
- builtin_functions.find(this->asm_name_);
- if (p != builtin_functions.end())
- {
-- this->fndecl_ = p->second;
-+ this->fndecl_ = tree_to_function(p->second);
- return this->fndecl_;
- }
- }
-
-- tree functype = type_to_tree(this->fntype_->get_backend(gogo));
-+ std::string asm_name;
-+ if (this->asm_name_.empty())
-+ {
-+ asm_name = (no->package() == NULL
-+ ? gogo->pkgpath_symbol()
-+ : no->package()->pkgpath_symbol());
-+ asm_name.append(1, '.');
-+ asm_name.append(Gogo::unpack_hidden_name(no->name()));
-+ if (this->fntype_->is_method())
-+ {
-+ asm_name.append(1, '.');
-+ Type* rtype = this->fntype_->receiver()->type();
-+ asm_name.append(rtype->mangled_name(gogo));
-+ }
-+ }
-
-- if (functype != error_mark_node)
-- {
-- // The type of a function comes back as a pointer to a
-- // struct whose first field is the function, but we want the
-- // real function type for a function declaration.
-- go_assert(POINTER_TYPE_P(functype)
-- && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE);
-- functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype)));
-- go_assert(FUNCTION_POINTER_TYPE_P(functype));
-- functype = TREE_TYPE(functype);
-- }
-+ Btype* functype = this->fntype_->get_backend_fntype(gogo);
-+ this->fndecl_ =
-+ gogo->backend()->function(functype, no->get_id(gogo), asm_name,
-+ true, true, true, false, false,
-+ this->location());
-+ }
-
-- tree decl;
-- if (functype == error_mark_node)
-- decl = error_mark_node;
-- else
-- {
-- decl = build_decl(this->location().gcc_location(), FUNCTION_DECL, id,
-- functype);
-- TREE_PUBLIC(decl) = 1;
-- DECL_EXTERNAL(decl) = 1;
--
-- if (this->asm_name_.empty())
-- {
-- std::string asm_name = (no->package() == NULL
-- ? gogo->pkgpath_symbol()
-- : no->package()->pkgpath_symbol());
-- asm_name.append(1, '.');
-- asm_name.append(Gogo::unpack_hidden_name(no->name()));
-- if (this->fntype_->is_method())
-- {
-- asm_name.append(1, '.');
-- Type* rtype = this->fntype_->receiver()->type();
-- asm_name.append(rtype->mangled_name(gogo));
-- }
-- SET_DECL_ASSEMBLER_NAME(decl,
-- get_identifier_from_string(asm_name));
-- }
-- }
-- this->fndecl_ = decl;
-- go_preserve_from_gc(decl);
-- }
- return this->fndecl_;
- }
-
-+// Return the function's decl after it has been built.
-+
-+tree
-+Function::get_decl() const
-+{
-+ go_assert(this->fndecl_ != NULL);
-+ return function_to_tree(this->fndecl_);
-+}
-+
- // We always pass the receiver to a method as a pointer. If the
- // receiver is actually declared as a non-pointer type, then we copy
- // the value into a local variable, so that it has the right type. In
-@@ -1558,7 +1363,7 @@
- void
- Function::build_tree(Gogo* gogo, Named_object* named_function)
- {
-- tree fndecl = this->fndecl_;
-+ tree fndecl = this->get_decl();
- go_assert(fndecl != NULL_TREE);
-
- tree params = NULL_TREE;
-@@ -1796,7 +1601,7 @@
- set = NULL_TREE;
- else
- set = fold_build2_loc(end_loc.gcc_location(), MODIFY_EXPR, void_type_node,
-- DECL_RESULT(this->fndecl_), retval);
-+ DECL_RESULT(this->get_decl()), retval);
- tree ret_stmt = fold_build1_loc(end_loc.gcc_location(), RETURN_EXPR,
- void_type_node, set);
- append_to_statement_list(ret_stmt, &stmt_list);
-@@ -1851,7 +1656,7 @@
- retval = this->return_value(gogo, named_function, end_loc,
- &stmt_list);
- set = fold_build2_loc(end_loc.gcc_location(), MODIFY_EXPR, void_type_node,
-- DECL_RESULT(this->fndecl_), retval);
-+ DECL_RESULT(this->get_decl()), retval);
- ret_stmt = fold_build1_loc(end_loc.gcc_location(), RETURN_EXPR,
- void_type_node, set);
-
-@@ -1869,7 +1674,7 @@
- *fini = stmt_list;
- }
-
--// Return the value to assign to DECL_RESULT(this->fndecl_). This may
-+// Return the value to assign to DECL_RESULT(this->get_decl()). This may
- // also add statements to STMT_LIST, which need to be executed before
- // the assignment. This is used for a return statement with no
- // explicit values.
-@@ -1902,7 +1707,7 @@
- }
- else
- {
-- tree rettype = TREE_TYPE(DECL_RESULT(this->fndecl_));
-+ tree rettype = TREE_TYPE(DECL_RESULT(this->get_decl()));
- retval = create_tmp_var(rettype, "RESULT");
- tree field = TYPE_FIELDS(rettype);
- int index = 0;
-@@ -2323,18 +2128,14 @@
- go_assert(m != NULL);
-
- Named_object* no = m->named_object();
--
-- tree fnid = no->get_id(this);
--
-- tree fndecl;
-+ Bfunction* bf;
- if (no->is_function())
-- fndecl = no->func_value()->get_or_make_decl(this, no, fnid);
-+ bf = no->func_value()->get_or_make_decl(this, no);
- else if (no->is_function_declaration())
-- fndecl = no->func_declaration_value()->get_or_make_decl(this, no,
-- fnid);
-+ bf = no->func_declaration_value()->get_or_make_decl(this, no);
- else
- go_unreachable();
-- fndecl = build_fold_addr_expr(fndecl);
-+ tree fndecl = build_fold_addr_expr(function_to_tree(bf));
-
- elt = pointers->quick_push(empty);
- elt->index = size_int(i);
-@@ -2353,10 +2154,11 @@
- TREE_CONSTANT(decl) = 1;
- DECL_INITIAL(decl) = constructor;
-
-- // If the interface type has hidden methods, then this is the only
-- // definition of the table. Otherwise it is a comdat table which
-- // may be defined in multiple packages.
-- if (has_hidden_methods)
-+ // If the interface type has hidden methods, and the table is for a
-+ // named type, then this is the only definition of the table.
-+ // Otherwise it is a comdat table which may be defined in multiple
-+ // packages.
-+ if (has_hidden_methods && type->named_type() != NULL)
- TREE_PUBLIC(decl) = 1;
- else
- {
-Index: gcc/go/gofrontend/lex.cc
-===================================================================
---- a/src/gcc/go/gofrontend/lex.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/lex.cc (.../branches/gcc-4_8-branch)
-@@ -873,7 +873,28 @@
- && (cc < 'a' || cc > 'z')
- && cc != '_'
- && (cc < '0' || cc > '9'))
-- break;
-+ {
-+ // Check for an invalid character here, as we get better
-+ // error behaviour if we swallow them as part of the
-+ // identifier we are building.
-+ if ((cc >= ' ' && cc < 0x7f)
-+ || cc == '\t'
-+ || cc == '\r'
-+ || cc == '\n')
-+ break;
-+
-+ this->lineoff_ = p - this->linebuf_;
-+ error_at(this->location(),
-+ "invalid character 0x%x in identifier",
-+ cc);
-+ if (!has_non_ascii_char)
-+ {
-+ buf.assign(pstart, p - pstart);
-+ has_non_ascii_char = true;
-+ }
-+ if (!Lex::is_invalid_identifier(buf))
-+ buf.append("$INVALID$");
-+ }
- ++p;
- if (is_first)
- {
-Index: gcc/go/gofrontend/backend.h
-===================================================================
---- a/src/gcc/go/gofrontend/backend.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/backend.h (.../branches/gcc-4_8-branch)
-@@ -23,7 +23,7 @@
- // The backend representation of a statement.
- class Bstatement;
-
--// The backend representation of a function definition.
-+// The backend representation of a function definition or declaration.
- class Bfunction;
-
- // The backend representation of a block.
-@@ -266,6 +266,11 @@
- virtual Bexpression*
- convert_expression(Btype* type, Bexpression* expr, Location) = 0;
-
-+ // Create an expression for the address of a function. This is used to
-+ // get the address of the code for a function.
-+ virtual Bexpression*
-+ function_code_expression(Bfunction*, Location) = 0;
-+
- // Statements.
-
- // Create an error statement. This is used for cases which should
-@@ -498,6 +503,32 @@
- // recover.
- virtual Bexpression*
- label_address(Blabel*, Location) = 0;
-+
-+ // Functions.
-+
-+ // Create an error function. This is used for cases which should
-+ // not occur in a correct program, in order to keep the compilation
-+ // going without crashing.
-+ virtual Bfunction*
-+ error_function() = 0;
-+
-+ // Declare or define a function of FNTYPE.
-+ // NAME is the Go name of the function. ASM_NAME, if not the empty string, is
-+ // the name that should be used in the symbol table; this will be non-empty if
-+ // a magic extern comment is used.
-+ // IS_VISIBLE is true if this function should be visible outside of the
-+ // current compilation unit. IS_DECLARATION is true if this is a function
-+ // declaration rather than a definition; the function definition will be in
-+ // another compilation unit.
-+ // IS_INLINABLE is true if the function can be inlined.
-+ // DISABLE_SPLIT_STACK is true if this function may not split the stack; this
-+ // is used for the implementation of recover.
-+ // IN_UNIQUE_SECTION is true if this function should be put into a unique
-+ // location if possible; this is used for field tracking.
-+ virtual Bfunction*
-+ function(Btype* fntype, const std::string& name, const std::string& asm_name,
-+ bool is_visible, bool is_declaration, bool is_inlinable,
-+ bool disable_split_stack, bool in_unique_section, Location) = 0;
- };
-
- // The backend interface has to define this function.
-@@ -517,5 +548,6 @@
- extern tree stat_to_tree(Bstatement*);
- extern tree block_to_tree(Bblock*);
- extern tree var_to_tree(Bvariable*);
-+extern tree function_to_tree(Bfunction*);
-
- #endif // !defined(GO_BACKEND_H)
-Index: gcc/go/gofrontend/types.cc
-===================================================================
---- a/src/gcc/go/gofrontend/types.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/types.cc (.../branches/gcc-4_8-branch)
-@@ -1834,7 +1834,9 @@
- bloc);
- gogo->start_block(bloc);
-
-- if (this->struct_type() != NULL)
-+ if (name != NULL && name->real_type()->named_type() != NULL)
-+ this->write_named_hash(gogo, name, hash_fntype, equal_fntype);
-+ else if (this->struct_type() != NULL)
- this->struct_type()->write_hash_function(gogo, name, hash_fntype,
- equal_fntype);
- else if (this->array_type() != NULL)
-@@ -1852,7 +1854,9 @@
- false, bloc);
- gogo->start_block(bloc);
-
-- if (this->struct_type() != NULL)
-+ if (name != NULL && name->real_type()->named_type() != NULL)
-+ this->write_named_equal(gogo, name);
-+ else if (this->struct_type() != NULL)
- this->struct_type()->write_equal_function(gogo, name);
- else if (this->array_type() != NULL)
- this->array_type()->write_equal_function(gogo, name);
-@@ -1865,6 +1869,100 @@
- gogo->finish_function(bloc);
- }
-
-+// Write a hash function that simply calls the hash function for a
-+// named type. This is used when one named type is defined as
-+// another. This ensures that this case works when the other named
-+// type is defined in another package and relies on calling hash
-+// functions defined only in that package.
-+
-+void
-+Type::write_named_hash(Gogo* gogo, Named_type* name,
-+ Function_type* hash_fntype, Function_type* equal_fntype)
-+{
-+ Location bloc = Linemap::predeclared_location();
-+
-+ Named_type* base_type = name->real_type()->named_type();
-+ go_assert(base_type != NULL);
-+
-+ // The pointer to the type we are going to hash. This is an
-+ // unsafe.Pointer.
-+ Named_object* key_arg = gogo->lookup("key", NULL);
-+ go_assert(key_arg != NULL);
-+
-+ // The size of the type we are going to hash.
-+ Named_object* keysz_arg = gogo->lookup("key_size", NULL);
-+ go_assert(keysz_arg != NULL);
-+
-+ Named_object* hash_fn;
-+ Named_object* equal_fn;
-+ name->real_type()->type_functions(gogo, base_type, hash_fntype, equal_fntype,
-+ &hash_fn, &equal_fn);
-+
-+ // Call the hash function for the base type.
-+ Expression* key_ref = Expression::make_var_reference(key_arg, bloc);
-+ Expression* keysz_ref = Expression::make_var_reference(keysz_arg, bloc);
-+ Expression_list* args = new Expression_list();
-+ args->push_back(key_ref);
-+ args->push_back(keysz_ref);
-+ Expression* func = Expression::make_func_reference(hash_fn, NULL, bloc);
-+ Expression* call = Expression::make_call(func, args, false, bloc);
-+
-+ // Return the hash of the base type.
-+ Expression_list* vals = new Expression_list();
-+ vals->push_back(call);
-+ Statement* s = Statement::make_return_statement(vals, bloc);
-+ gogo->add_statement(s);
-+}
-+
-+// Write an equality function that simply calls the equality function
-+// for a named type. This is used when one named type is defined as
-+// another. This ensures that this case works when the other named
-+// type is defined in another package and relies on calling equality
-+// functions defined only in that package.
-+
-+void
-+Type::write_named_equal(Gogo* gogo, Named_type* name)
-+{
-+ Location bloc = Linemap::predeclared_location();
-+
-+ // The pointers to the types we are going to compare. These have
-+ // type unsafe.Pointer.
-+ Named_object* key1_arg = gogo->lookup("key1", NULL);
-+ Named_object* key2_arg = gogo->lookup("key2", NULL);
-+ go_assert(key1_arg != NULL && key2_arg != NULL);
-+
-+ Named_type* base_type = name->real_type()->named_type();
-+ go_assert(base_type != NULL);
-+
-+ // Build temporaries with the base type.
-+ Type* pt = Type::make_pointer_type(base_type);
-+
-+ Expression* ref = Expression::make_var_reference(key1_arg, bloc);
-+ ref = Expression::make_cast(pt, ref, bloc);
-+ Temporary_statement* p1 = Statement::make_temporary(pt, ref, bloc);
-+ gogo->add_statement(p1);
-+
-+ ref = Expression::make_var_reference(key2_arg, bloc);
-+ ref = Expression::make_cast(pt, ref, bloc);
-+ Temporary_statement* p2 = Statement::make_temporary(pt, ref, bloc);
-+ gogo->add_statement(p2);
-+
-+ // Compare the values for equality.
-+ Expression* t1 = Expression::make_temporary_reference(p1, bloc);
-+ t1 = Expression::make_unary(OPERATOR_MULT, t1, bloc);
-+
-+ Expression* t2 = Expression::make_temporary_reference(p2, bloc);
-+ t2 = Expression::make_unary(OPERATOR_MULT, t2, bloc);
-+
-+ Expression* cond = Expression::make_binary(OPERATOR_EQEQ, t1, t2, bloc);
-+
-+ // Return the equality comparison.
-+ Expression_list* vals = new Expression_list();
-+ vals->push_back(cond);
-+ Statement* s = Statement::make_return_statement(vals, bloc);
-+ gogo->add_statement(s);
-+}
-+
- // Return a composite literal for the type descriptor for a plain type
- // of kind RUNTIME_TYPE_KIND named NAME.
-
-@@ -2164,26 +2262,9 @@
-
- ++p;
- go_assert(p->is_field_name("typ"));
-- if (!only_value_methods && m->is_value_method())
-- {
-- // This is a value method on a pointer type. Change the type of
-- // the method to use a pointer receiver. The implementation
-- // always uses a pointer receiver anyhow.
-- Type* rtype = mtype->receiver()->type();
-- Type* prtype = Type::make_pointer_type(rtype);
-- Typed_identifier* receiver =
-- new Typed_identifier(mtype->receiver()->name(), prtype,
-- mtype->receiver()->location());
-- mtype = Type::make_function_type(receiver,
-- (mtype->parameters() == NULL
-- ? NULL
-- : mtype->parameters()->copy()),
-- (mtype->results() == NULL
-- ? NULL
-- : mtype->results()->copy()),
-- mtype->location());
-- }
-- vals->push_back(Expression::make_type_descriptor(mtype, bloc));
-+ bool want_pointer_receiver = !only_value_methods && m->is_value_method();
-+ nonmethod_type = mtype->copy_with_receiver_as_param(want_pointer_receiver);
-+ vals->push_back(Expression::make_type_descriptor(nonmethod_type, bloc));
-
- ++p;
- go_assert(p->is_field_name("tfn"));
-@@ -3383,6 +3464,68 @@
- // Get the backend representation for a function type.
-
- Btype*
-+Function_type::get_backend_fntype(Gogo* gogo)
-+{
-+ if (this->fnbtype_ == NULL)
-+ {
-+ Backend::Btyped_identifier breceiver;
-+ if (this->receiver_ != NULL)
-+ {
-+ breceiver.name = Gogo::unpack_hidden_name(this->receiver_->name());
-+
-+ // We always pass the address of the receiver parameter, in
-+ // order to make interface calls work with unknown types.
-+ Type* rtype = this->receiver_->type();
-+ if (rtype->points_to() == NULL)
-+ rtype = Type::make_pointer_type(rtype);
-+ breceiver.btype = rtype->get_backend(gogo);
-+ breceiver.location = this->receiver_->location();
-+ }
-+
-+ std::vector<Backend::Btyped_identifier> bparameters;
-+ if (this->parameters_ != NULL)
-+ {
-+ bparameters.resize(this->parameters_->size());
-+ size_t i = 0;
-+ for (Typed_identifier_list::const_iterator p =
-+ this->parameters_->begin(); p != this->parameters_->end();
-+ ++p, ++i)
-+ {
-+ bparameters[i].name = Gogo::unpack_hidden_name(p->name());
-+ bparameters[i].btype = p->type()->get_backend(gogo);
-+ bparameters[i].location = p->location();
-+ }
-+ go_assert(i == bparameters.size());
-+ }
-+
-+ std::vector<Backend::Btyped_identifier> bresults;
-+ if (this->results_ != NULL)
-+ {
-+ bresults.resize(this->results_->size());
-+ size_t i = 0;
-+ for (Typed_identifier_list::const_iterator p =
-+ this->results_->begin(); p != this->results_->end();
-+ ++p, ++i)
-+ {
-+ bresults[i].name = Gogo::unpack_hidden_name(p->name());
-+ bresults[i].btype = p->type()->get_backend(gogo);
-+ bresults[i].location = p->location();
-+ }
-+ go_assert(i == bresults.size());
-+ }
-+
-+ this->fnbtype_ = gogo->backend()->function_type(breceiver, bparameters,
-+ bresults,
-+ this->location());
-+
-+ }
-+
-+ return this->fnbtype_;
-+}
-+
-+// Get the backend representation for a Go function type.
-+
-+Btype*
- Function_type::do_get_backend(Gogo* gogo)
- {
- // When we do anything with a function value other than call it, it
-@@ -3395,57 +3538,9 @@
- gogo->backend()->placeholder_struct_type("__go_descriptor", loc);
- Btype* ptr_struct_type = gogo->backend()->pointer_type(struct_type);
-
-- Backend::Btyped_identifier breceiver;
-- if (this->receiver_ != NULL)
-- {
-- breceiver.name = Gogo::unpack_hidden_name(this->receiver_->name());
--
-- // We always pass the address of the receiver parameter, in
-- // order to make interface calls work with unknown types.
-- Type* rtype = this->receiver_->type();
-- if (rtype->points_to() == NULL)
-- rtype = Type::make_pointer_type(rtype);
-- breceiver.btype = rtype->get_backend(gogo);
-- breceiver.location = this->receiver_->location();
-- }
--
-- std::vector<Backend::Btyped_identifier> bparameters;
-- if (this->parameters_ != NULL)
-- {
-- bparameters.resize(this->parameters_->size());
-- size_t i = 0;
-- for (Typed_identifier_list::const_iterator p = this->parameters_->begin();
-- p != this->parameters_->end();
-- ++p, ++i)
-- {
-- bparameters[i].name = Gogo::unpack_hidden_name(p->name());
-- bparameters[i].btype = p->type()->get_backend(gogo);
-- bparameters[i].location = p->location();
-- }
-- go_assert(i == bparameters.size());
-- }
--
-- std::vector<Backend::Btyped_identifier> bresults;
-- if (this->results_ != NULL)
-- {
-- bresults.resize(this->results_->size());
-- size_t i = 0;
-- for (Typed_identifier_list::const_iterator p = this->results_->begin();
-- p != this->results_->end();
-- ++p, ++i)
-- {
-- bresults[i].name = Gogo::unpack_hidden_name(p->name());
-- bresults[i].btype = p->type()->get_backend(gogo);
-- bresults[i].location = p->location();
-- }
-- go_assert(i == bresults.size());
-- }
--
-- Btype* fntype = gogo->backend()->function_type(breceiver, bparameters,
-- bresults, loc);
- std::vector<Backend::Btyped_identifier> fields(1);
- fields[0].name = "code";
-- fields[0].btype = fntype;
-+ fields[0].btype = this->get_backend_fntype(gogo);
- fields[0].location = loc;
- if (!gogo->backend()->set_placeholder_struct_type(struct_type, fields))
- return gogo->backend()->error_type();
-@@ -3821,6 +3916,32 @@
- return ret;
- }
-
-+// Make a copy of a function type with the receiver as the first
-+// parameter.
-+
-+Function_type*
-+Function_type::copy_with_receiver_as_param(bool want_pointer_receiver) const
-+{
-+ go_assert(this->is_method());
-+ Typed_identifier_list* new_params = new Typed_identifier_list();
-+ Type* rtype = this->receiver_->type();
-+ if (want_pointer_receiver)
-+ rtype = Type::make_pointer_type(rtype);
-+ Typed_identifier receiver(this->receiver_->name(), rtype,
-+ this->receiver_->location());
-+ new_params->push_back(receiver);
-+ const Typed_identifier_list* orig_params = this->parameters_;
-+ if (orig_params != NULL && !orig_params->empty())
-+ {
-+ for (Typed_identifier_list::const_iterator p = orig_params->begin();
-+ p != orig_params->end();
-+ ++p)
-+ new_params->push_back(*p);
-+ }
-+ return Type::make_function_type(NULL, new_params, this->results_,
-+ this->location_);
-+}
-+
- // Make a copy of a function type ignoring any receiver and adding a
- // closure parameter.
-
-@@ -4195,7 +4316,8 @@
-
- // This is a horrible hack caused by the fact that we don't pack
- // the names of builtin types. FIXME.
-- if (nt != NULL
-+ if (!this->is_imported_
-+ && nt != NULL
- && nt->is_builtin()
- && nt->name() == Gogo::unpack_hidden_name(name))
- return true;
-@@ -4204,6 +4326,36 @@
- }
- }
-
-+// Return whether this field is an unexported field named NAME.
-+
-+bool
-+Struct_field::is_unexported_field_name(Gogo* gogo,
-+ const std::string& name) const
-+{
-+ const std::string& field_name(this->field_name());
-+ if (Gogo::is_hidden_name(field_name)
-+ && name == Gogo::unpack_hidden_name(field_name)
-+ && gogo->pack_hidden_name(name, false) != field_name)
-+ return true;
-+
-+ // Check for the name of a builtin type. This is like the test in
-+ // is_field_name, only there we return false if this->is_imported_,
-+ // and here we return true.
-+ if (this->is_imported_ && this->is_anonymous())
-+ {
-+ Type* t = this->typed_identifier_.type();
-+ if (t->points_to() != NULL)
-+ t = t->points_to();
-+ Named_type* nt = t->named_type();
-+ if (nt != NULL
-+ && nt->is_builtin()
-+ && nt->name() == Gogo::unpack_hidden_name(name))
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
- // Return whether this field is an embedded built-in type.
-
- bool
-@@ -4264,13 +4416,8 @@
- ++p)
- {
- Type* t = p->type();
-- if (t->is_undefined())
-+ if (p->is_anonymous())
- {
-- error_at(p->location(), "struct field type is incomplete");
-- p->set_type(Type::make_error_type());
-- }
-- else if (p->is_anonymous())
-- {
- if (t->named_type() != NULL && t->points_to() != NULL)
- {
- error_at(p->location(), "embedded type may not be a pointer");
-@@ -4641,13 +4788,8 @@
- for (Struct_field_list::const_iterator pf = fields->begin();
- pf != fields->end();
- ++pf)
-- {
-- const std::string& field_name(pf->field_name());
-- if (Gogo::is_hidden_name(field_name)
-- && name == Gogo::unpack_hidden_name(field_name)
-- && gogo->pack_hidden_name(name, false) != field_name)
-- return true;
-- }
-+ if (pf->is_unexported_field_name(gogo, name))
-+ return true;
- }
- return false;
- }
-@@ -5250,6 +5392,7 @@
- Type* ftype = imp->read_type();
-
- Struct_field sf(Typed_identifier(name, ftype, imp->location()));
-+ sf.set_is_imported();
-
- if (imp->peek_char() == ' ')
- {
-@@ -9022,6 +9165,8 @@
- fntype->is_varargs(), location);
- gogo->finish_function(fntype->location());
-
-+ if (type->named_type() == NULL && stub->is_function())
-+ stub->func_value()->set_is_unnamed_type_stub_method();
- if (m->nointerface() && stub->is_function())
- stub->func_value()->set_nointerface();
- }
-@@ -9289,7 +9434,9 @@
- else
- {
- bool is_unexported;
-- if (!Gogo::is_hidden_name(name))
-+ // The test for 'a' and 'z' is to handle builtin names,
-+ // which are not hidden.
-+ if (!Gogo::is_hidden_name(name) && (name[0] < 'a' || name[0] > 'z'))
- is_unexported = false;
- else
- {
-Index: gcc/go/gofrontend/expressions.cc
-===================================================================
---- a/src/gcc/go/gofrontend/expressions.cc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/go/gofrontend/expressions.cc (.../branches/gcc-4_8-branch)
-@@ -1219,7 +1219,7 @@
-
- // Get the tree for the code of a function expression.
-
--tree
-+Bexpression*
- Func_expression::get_code_pointer(Gogo* gogo, Named_object* no, Location loc)
- {
- Function_type* fntype;
-@@ -1237,25 +1237,18 @@
- error_at(loc,
- "invalid use of special builtin function %qs; must be called",
- no->message_name().c_str());
-- return error_mark_node;
-+ return gogo->backend()->error_expression();
- }
-
-- tree id = no->get_id(gogo);
-- if (id == error_mark_node)
-- return error_mark_node;
--
-- tree fndecl;
-+ Bfunction* fndecl;
- if (no->is_function())
-- fndecl = no->func_value()->get_or_make_decl(gogo, no, id);
-+ fndecl = no->func_value()->get_or_make_decl(gogo, no);
- else if (no->is_function_declaration())
-- fndecl = no->func_declaration_value()->get_or_make_decl(gogo, no, id);
-+ fndecl = no->func_declaration_value()->get_or_make_decl(gogo, no);
- else
- go_unreachable();
-
-- if (fndecl == error_mark_node)
-- return error_mark_node;
--
-- return build_fold_addr_expr_loc(loc.gcc_location(), fndecl);
-+ return gogo->backend()->function_code_expression(fndecl, loc);
- }
-
- // Get the tree for a function expression. This is used when we take
-@@ -1492,8 +1485,10 @@
- tree
- Func_code_reference_expression::do_get_tree(Translate_context* context)
- {
-- return Func_expression::get_code_pointer(context->gogo(), this->function_,
-- this->location());
-+ Bexpression* ret =
-+ Func_expression::get_code_pointer(context->gogo(), this->function_,
-+ this->location());
-+ return expr_to_tree(ret);
- }
-
- // Make a reference to the code of a function.
-@@ -3055,8 +3050,7 @@
- do_lower(Gogo*, Named_object*, Statement_inserter*, int);
-
- bool
-- do_is_constant() const
-- { return this->expr_->is_constant(); }
-+ do_is_constant() const;
-
- bool
- do_numeric_constant_value(Numeric_constant*) const;
-@@ -3198,6 +3192,27 @@
- return this;
- }
-
-+// Return whether a type conversion is a constant.
-+
-+bool
-+Type_conversion_expression::do_is_constant() const
-+{
-+ if (!this->expr_->is_constant())
-+ return false;
-+
-+ // A conversion to a type that may not be used as a constant is not
-+ // a constant. For example, []byte(nil).
-+ Type* type = this->type_;
-+ if (type->integer_type() == NULL
-+ && type->float_type() == NULL
-+ && type->complex_type() == NULL
-+ && !type->is_boolean_type()
-+ && !type->is_string_type())
-+ return false;
-+
-+ return true;
-+}
-+
- // Return the constant numeric value if there is one.
-
- bool
-@@ -5586,6 +5601,15 @@
- subcontext.type = NULL;
- }
-
-+ if (this->op_ == OPERATOR_ANDAND || this->op_ == OPERATOR_OROR)
-+ {
-+ // For a logical operation, the context does not determine the
-+ // types of the operands. The operands must be some boolean
-+ // type but if the context has a boolean type they do not
-+ // inherit it. See http://golang.org/issue/3924.
-+ subcontext.type = NULL;
-+ }
-+
- // Set the context for the left hand operand.
- if (is_shift_op)
- {
-@@ -5967,6 +5991,43 @@
- right);
- }
-
-+ // For complex division Go wants slightly different results than the
-+ // GCC library provides, so we have our own runtime routine.
-+ if (this->op_ == OPERATOR_DIV && this->left_->type()->complex_type() != NULL)
-+ {
-+ const char *name;
-+ tree *pdecl;
-+ Type* ctype;
-+ static tree complex64_div_decl;
-+ static tree complex128_div_decl;
-+ switch (this->left_->type()->complex_type()->bits())
-+ {
-+ case 64:
-+ name = "__go_complex64_div";
-+ pdecl = &complex64_div_decl;
-+ ctype = Type::lookup_complex_type("complex64");
-+ break;
-+ case 128:
-+ name = "__go_complex128_div";
-+ pdecl = &complex128_div_decl;
-+ ctype = Type::lookup_complex_type("complex128");
-+ break;
-+ default:
-+ go_unreachable();
-+ }
-+ Btype* cbtype = ctype->get_backend(gogo);
-+ tree ctype_tree = type_to_tree(cbtype);
-+ return Gogo::call_builtin(pdecl,
-+ this->location(),
-+ name,
-+ 2,
-+ ctype_tree,
-+ ctype_tree,
-+ fold_convert_loc(gccloc, ctype_tree, left),
-+ type,
-+ fold_convert_loc(gccloc, ctype_tree, right));
-+ }
-+
- tree compute_type = excess_precision_type(type);
- if (compute_type != NULL_TREE)
- {
-@@ -7191,6 +7252,15 @@
- if (this->code_ == BUILTIN_OFFSETOF)
- {
- Expression* arg = this->one_arg();
-+
-+ if (arg->bound_method_expression() != NULL
-+ || arg->interface_field_reference_expression() != NULL)
-+ {
-+ this->report_error(_("invalid use of method value as argument "
-+ "of Offsetof"));
-+ return this;
-+ }
-+
- Field_reference_expression* farg = arg->field_reference_expression();
- while (farg != NULL)
- {
-@@ -7200,7 +7270,8 @@
- // it must not be reached through pointer indirections.
- if (farg->expr()->deref() != farg->expr())
- {
-- this->report_error(_("argument of Offsetof implies indirection of an embedded field"));
-+ this->report_error(_("argument of Offsetof implies "
-+ "indirection of an embedded field"));
- return this;
- }
- // Go up until we reach the original base.
-@@ -7476,7 +7547,7 @@
- switch (nc.to_unsigned_long(&v))
- {
- case Numeric_constant::NC_UL_VALID:
-- return true;
-+ break;
- case Numeric_constant::NC_UL_NOTINT:
- error_at(e->location(), "non-integer %s argument to make",
- is_length ? "len" : "cap");
-@@ -7488,8 +7559,23 @@
- case Numeric_constant::NC_UL_BIG:
- // We don't want to give a compile-time error for a 64-bit
- // value on a 32-bit target.
-- return true;
-+ break;
- }
-+
-+ mpz_t val;
-+ if (!nc.to_int(&val))
-+ go_unreachable();
-+ int bits = mpz_sizeinbase(val, 2);
-+ mpz_clear(val);
-+ Type* int_type = Type::lookup_integer_type("int");
-+ if (bits >= int_type->integer_type()->bits())
-+ {
-+ error_at(e->location(), "%s argument too large for make",
-+ is_length ? "len" : "cap");
-+ return false;
-+ }
-+
-+ return true;
- }
-
- if (e->type()->integer_type() != NULL)
-@@ -7595,6 +7681,8 @@
- bool
- Builtin_call_expression::do_is_constant() const
- {
-+ if (this->is_error_expression())
-+ return true;
- switch (this->code_)
- {
- case BUILTIN_LEN:
-@@ -9744,15 +9832,9 @@
- }
-
- tree fntype_tree = type_to_tree(fntype->get_backend(gogo));
-- if (fntype_tree == error_mark_node)
-+ tree fnfield_type = type_to_tree(fntype->get_backend_fntype(gogo));
-+ if (fntype_tree == error_mark_node || fnfield_type == error_mark_node)
- return error_mark_node;
-- go_assert(POINTER_TYPE_P(fntype_tree));
-- if (TREE_TYPE(fntype_tree) == error_mark_node)
-- return error_mark_node;
-- go_assert(TREE_CODE(TREE_TYPE(fntype_tree)) == RECORD_TYPE);
-- tree fnfield_type = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(fntype_tree)));
-- if (fnfield_type == error_mark_node)
-- return error_mark_node;
- go_assert(FUNCTION_POINTER_TYPE_P(fnfield_type));
- tree rettype = TREE_TYPE(TREE_TYPE(fnfield_type));
- if (rettype == error_mark_node)
-@@ -9763,7 +9845,7 @@
- if (func != NULL)
- {
- Named_object* no = func->named_object();
-- fn = Func_expression::get_code_pointer(gogo, no, location);
-+ fn = expr_to_tree(Func_expression::get_code_pointer(gogo, no, location));
- if (!has_closure)
- closure_tree = NULL_TREE;
- else
-@@ -10817,11 +10899,20 @@
- void
- String_index_expression::do_check_types(Gogo*)
- {
-- if (this->start_->type()->integer_type() == NULL)
-+ Numeric_constant nc;
-+ unsigned long v;
-+ if (this->start_->type()->integer_type() == NULL
-+ && !this->start_->type()->is_error()
-+ && (!this->start_->numeric_constant_value(&nc)
-+ || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT))
- this->report_error(_("index must be integer"));
- if (this->end_ != NULL
- && this->end_->type()->integer_type() == NULL
-- && !this->end_->is_nil_expression())
-+ && !this->end_->type()->is_error()
-+ && !this->end_->is_nil_expression()
-+ && !this->end_->is_error_expression()
-+ && (!this->end_->numeric_constant_value(&nc)
-+ || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT))
- this->report_error(_("slice end must be integer"));
-
- std::string sval;
-Index: gcc/opts.c
-===================================================================
---- a/src/gcc/opts.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/opts.c (.../branches/gcc-4_8-branch)
-@@ -425,8 +425,8 @@
- { OPT_LEVELS_1_PLUS, OPT_fguess_branch_probability, NULL, 1 },
- { OPT_LEVELS_1_PLUS, OPT_fcprop_registers, NULL, 1 },
- { OPT_LEVELS_1_PLUS, OPT_fforward_propagate, NULL, 1 },
-- { OPT_LEVELS_1_PLUS, OPT_fif_conversion, NULL, 1 },
-- { OPT_LEVELS_1_PLUS, OPT_fif_conversion2, NULL, 1 },
-+ { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion, NULL, 1 },
-+ { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion2, NULL, 1 },
- { OPT_LEVELS_1_PLUS, OPT_fipa_pure_const, NULL, 1 },
- { OPT_LEVELS_1_PLUS, OPT_fipa_reference, NULL, 1 },
- { OPT_LEVELS_1_PLUS, OPT_fipa_profile, NULL, 1 },
-Index: gcc/recog.c
-===================================================================
---- a/src/gcc/recog.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/recog.c (.../branches/gcc-4_8-branch)
-@@ -3061,6 +3061,9 @@
- return 1;
- }
-
-+/* Regno offset to be used in the register search. */
-+static int search_ofs;
-+
- /* Try to find a hard register of mode MODE, matching the register class in
- CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
- remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
-@@ -3076,7 +3079,6 @@
- peep2_find_free_register (int from, int to, const char *class_str,
- enum machine_mode mode, HARD_REG_SET *reg_set)
- {
-- static int search_ofs;
- enum reg_class cl;
- HARD_REG_SET live;
- df_ref *def_rec;
-@@ -3541,6 +3543,7 @@
- /* Initialize the regsets we're going to use. */
- for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
- peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack);
-+ search_ofs = 0;
- live = BITMAP_ALLOC (&reg_obstack);
-
- FOR_EACH_BB_REVERSE (bb)
-Index: gcc/ada/system-linux-s390x.ads
-===================================================================
---- a/src/gcc/ada/system-linux-s390x.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-linux-s390x.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (GNU-Linux/s390x Version) --
- -- --
---- Copyright (C) 1992-2012, Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014, Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -35,9 +35,10 @@
- ------------------------------------------------------------------------------
-
- package System is
--pragma Pure (System);
---- Note that we take advantage of the implementation permission to
---- make this unit Pure instead of Preelaborable, see RM 13.7(36)
-+ pragma Pure;
-+ -- Note that we take advantage of the implementation permission to make
-+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
-+ -- 2005, this is Pure in any case (AI-362).
-
- type Name is (SYSTEM_NAME_GNAT);
- System_Name : constant Name := SYSTEM_NAME_GNAT;
-@@ -61,6 +62,7 @@
- -- Storage-related Declarations
-
- type Address is private;
-+ pragma Preelaborable_Initialization (Address);
- Null_Address : constant Address;
-
- Storage_Unit : constant := 8;
-Index: gcc/ada/system-linux-alpha.ads
-===================================================================
---- a/src/gcc/ada/system-linux-alpha.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-linux-alpha.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (GNU-Linux/alpha Version) --
- -- --
---- Copyright (C) 1992-2012, Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014, Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -35,9 +35,10 @@
- ------------------------------------------------------------------------------
-
- package System is
--pragma Pure (System);
---- Note that we take advantage of the implementation permission to
---- make this unit Pure instead of Preelaborable, see RM 13.7(36)
-+ pragma Pure;
-+ -- Note that we take advantage of the implementation permission to make
-+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
-+ -- 2005, this is Pure in any case (AI-362).
-
- type Name is (SYSTEM_NAME_GNAT);
- System_Name : constant Name := SYSTEM_NAME_GNAT;
-@@ -61,6 +62,7 @@
- -- Storage-related Declarations
-
- type Address is private;
-+ pragma Preelaborable_Initialization (Address);
- Null_Address : constant Address;
-
- Storage_Unit : constant := 8;
-Index: gcc/ada/system-vxworks-arm.ads
-===================================================================
---- a/src/gcc/ada/system-vxworks-arm.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-vxworks-arm.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (VxWorks Version ARM) --
- -- --
---- Copyright (C) 1992-2012, Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014, Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -35,10 +35,10 @@
- ------------------------------------------------------------------------------
-
- package System is
--pragma Pure (System);
---- Note that we take advantage of the implementation permission to make this
---- unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada 2005, this is
---- Pure in any case (AI-362).
-+ pragma Pure;
-+ -- Note that we take advantage of the implementation permission to make
-+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
-+ -- 2005, this is Pure in any case (AI-362).
-
- type Name is (SYSTEM_NAME_GNAT);
- System_Name : constant Name := SYSTEM_NAME_GNAT;
-Index: gcc/ada/system-linux-s390.ads
-===================================================================
---- a/src/gcc/ada/system-linux-s390.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-linux-s390.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (GNU-Linux/s390 Version) --
- -- --
---- Copyright (C) 1992-2012, Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014, Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -35,9 +35,10 @@
- ------------------------------------------------------------------------------
-
- package System is
--pragma Pure (System);
---- Note that we take advantage of the implementation permission to
---- make this unit Pure instead of Preelaborable, see RM 13.7(36)
-+ pragma Pure;
-+ -- Note that we take advantage of the implementation permission to make
-+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
-+ -- 2005, this is Pure in any case (AI-362).
-
- type Name is (SYSTEM_NAME_GNAT);
- System_Name : constant Name := SYSTEM_NAME_GNAT;
-@@ -61,6 +62,7 @@
- -- Storage-related Declarations
-
- type Address is private;
-+ pragma Preelaborable_Initialization (Address);
- Null_Address : constant Address;
-
- Storage_Unit : constant := 8;
-Index: gcc/ada/indepsw-darwin.adb
-===================================================================
---- a/src/gcc/ada/indepsw-darwin.adb (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/indepsw-darwin.adb (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,67 @@
-+------------------------------------------------------------------------------
-+-- --
-+-- GNAT COMPILER COMPONENTS --
-+-- --
-+-- I N D E P S W --
-+-- --
-+-- B o d y --
-+-- (Darwin version) --
-+-- --
-+-- Copyright (C) 2013, Free Software Foundation, Inc. --
-+-- --
-+-- GNAT is free software; you can redistribute it and/or modify it under --
-+-- terms of the GNU General Public License as published by the Free Soft- --
-+-- ware Foundation; either version 3, or (at your option) any later ver- --
-+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
-+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-+-- or FITNESS FOR A PARTICULAR PURPOSE. --
-+-- --
-+-- As a special exception under Section 7 of GPL version 3, you are granted --
-+-- additional permissions described in the GCC Runtime Library Exception, --
-+-- version 3.1, as published by the Free Software Foundation. --
-+-- --
-+-- You should have received a copy of the GNU General Public License and --
-+-- a copy of the GCC Runtime Library Exception along with this program; --
-+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
-+-- <http://www.gnu.org/licenses/>. --
-+-- --
-+-- GNAT was originally developed by the GNAT team at New York University. --
-+-- Extensive contributions were provided by Ada Core Technologies Inc. --
-+-- --
-+------------------------------------------------------------------------------
-+
-+-- This is the Darwin version
-+
-+package body Indepsw is
-+
-+ Map_Switch : aliased constant String := "-Wl,-map,";
-+
-+ -------------
-+ -- Convert --
-+ -------------
-+
-+ procedure Convert
-+ (Switch : Switch_Kind;
-+ Argument : String;
-+ To : out String_List_Access)
-+ is
-+ begin
-+ case Switch is
-+ when Map_File =>
-+ To := new Argument_List'(1 => new String'(Map_Switch & Argument));
-+ end case;
-+ end Convert;
-+
-+ ------------------
-+ -- Is_Supported --
-+ ------------------
-+
-+ function Is_Supported (Switch : Switch_Kind) return Boolean is
-+ begin
-+ case Switch is
-+ when Map_File =>
-+ return True;
-+ end case;
-+ end Is_Supported;
-+
-+end Indepsw;
-Index: gcc/ada/system-linux-sparcv9.ads
-===================================================================
---- a/src/gcc/ada/system-linux-sparcv9.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-linux-sparcv9.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (GNU/Linux-SPARCV9 Version) --
- -- --
---- Copyright (C) 1992-2011, Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014, Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -35,9 +35,10 @@
- ------------------------------------------------------------------------------
-
- package System is
--pragma Pure (System);
---- Note that we take advantage of the implementation permission to
---- make this unit Pure instead of Preelaborable, see RM 13.7(36)
-+ pragma Pure;
-+ -- Note that we take advantage of the implementation permission to make
-+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
-+ -- 2005, this is Pure in any case (AI-362).
-
- type Name is (SYSTEM_NAME_GNAT);
- System_Name : constant Name := SYSTEM_NAME_GNAT;
-@@ -61,6 +62,7 @@
- -- Storage-related Declarations
-
- type Address is private;
-+ pragma Preelaborable_Initialization (Address);
- Null_Address : constant Address;
-
- Storage_Unit : constant := 8;
-Index: gcc/ada/ChangeLog
-===================================================================
---- a/src/gcc/ada/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,60 @@
-+2014-03-30 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR ada/60703
-+ * system-linux-alpha.ads: Adjust for Ada 2005.
-+ * system-linux-mips.ads: Likewise.
-+ * system-linux-mips64el.ads: Likewise.
-+ * system-linux-mipsel.ads: Likewise.
-+ * system-linux-s390.ads: Likewise.
-+ * system-linux-s390x.ads: Likewise.
-+ * system-linux-sparc.ads: Likewise.
-+ * system-linux-sparcv9.ads: Likewise.
-+ * system-rtems.ads: Likewise.
-+ * system-vxworks-arm.ads: Likewise.
-+
-+2014-03-13 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR ada/51483
-+ * back_end.ads (Register_Type_Proc): Add 'precision' parameter.
-+ * cstand.adb (Register_Float_Type): Add 'precision' parameter and use
-+ it to set the RM size. Use directly 'size' for the Esize.
-+ * gcc-interface/gigi.h (enumerate_modes): Add integer parameter.
-+ * gcc-interface/misc.c (enumerate_modes): Likewise. Do not register
-+ types for vector modes, pass the size in addition to the precision.
-+
-+2014-01-12 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR ada/59772
-+ * gcc-interface/cuintp.c (build_cst_from_int): Use 32-bit integer type
-+ as intermediate type.
-+ (UI_To_gnu): Likewise.
-+
-+2013-12-12 Eric Botcazou <ebotcazou@adacore.com>
-+ Iain Sandoe <iain@codesourcery.com>
-+
-+ PR ada/55946
-+ * gcc-interface/Make-lang.in (ada/doctools/xgnatugn): Use gnatmake.
-+ * gcc-interface/Makefile.in (GCC_LINK): Add LDFLAGS.
-+ (../../gnatmake): Remove LDFLAGS.
-+ (../../gnatlink): Likewise.
-+
-+2013-12-04 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ PR ada/59382
-+ * indepsw-darwin.adb: New file.
-+
-+2013-10-19 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * gcc-interface/utils.c (scale_by_factor_of): New function.
-+ (rest_of_record_type_compilation): Use scale_by_factor_of in order to
-+ scale the original offset for both rounding cases; in the second case,
-+ take into accout the addend to compute the alignment. Tidy up.
-+
-+2013-10-19 Eric Botcazou <ebotcazou@adacore.com>
-+
-+ * gcc-interface/utils.c (gnat_set_type_context): New function.
-+ (gnat_pushdecl): Use it to set the context of the type.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: gcc/ada/cstand.adb
-===================================================================
---- a/src/gcc/ada/cstand.adb (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/cstand.adb (.../branches/gcc-4_8-branch)
-@@ -151,6 +151,7 @@
- Complex : Boolean; -- True iff type has real and imaginary parts
- Count : Natural; -- Number of elements in vector, 0 otherwise
- Float_Rep : Float_Rep_Kind; -- Representation used for fpt type
-+ Precision : Positive; -- Precision of representation in bits
- Size : Positive; -- Size of representation in bits
- Alignment : Natural); -- Required alignment in bits
- pragma Convention (C, Register_Float_Type);
-@@ -2014,6 +2015,7 @@
- Complex : Boolean;
- Count : Natural;
- Float_Rep : Float_Rep_Kind;
-+ Precision : Positive;
- Size : Positive;
- Alignment : Natural)
- is
-@@ -2063,14 +2065,25 @@
-
- else
- Write_Str ("mod 2**");
-- Write_Int (Int (Size / Positive'Max (1, Count)));
-+ Write_Int (Int (Precision / Positive'Max (1, Count)));
- Write_Line (";");
- end if;
-
-- Write_Str ("for " & T & "'Size use ");
-- Write_Int (Int (Size));
-- Write_Line (";");
-+ if Precision = Size then
-+ Write_Str ("for " & T (1 .. Last) & "'Size use ");
-+ Write_Int (Int (Size));
-+ Write_Line (";");
-
-+ else
-+ Write_Str ("for " & T (1 .. Last) & "'Value_Size use ");
-+ Write_Int (Int (Precision));
-+ Write_Line (";");
-+
-+ Write_Str ("for " & T (1 .. Last) & "'Object_Size use ");
-+ Write_Int (Int (Size));
-+ Write_Line (";");
-+ end if;
-+
- Write_Str ("for " & T & "'Alignment use ");
- Write_Int (Int (Alignment / 8));
- Write_Line (";");
-@@ -2092,15 +2105,13 @@
- if Digs > 0 and then not Complex and then Count = 0 then
- declare
- Ent : constant Entity_Id := New_Standard_Entity;
-- Esize : constant Pos := Pos ((Size + Alignment - 1)
-- / Alignment * Alignment);
- begin
- Set_Defining_Identifier
- (New_Node (N_Full_Type_Declaration, Stloc), Ent);
- Make_Name (Ent, T (1 .. Last));
- Set_Scope (Ent, Standard_Standard);
-- Build_Float_Type (Ent, Esize, Float_Rep, Pos (Digs));
-- Set_RM_Size (Ent, UI_From_Int (Int (Size)));
-+ Build_Float_Type (Ent, Int (Size), Float_Rep, Pos (Digs));
-+ Set_RM_Size (Ent, UI_From_Int (Int (Precision)));
- Set_Alignment (Ent, UI_From_Int (Int (Alignment / 8)));
-
- if No (Back_End_Float_Types) then
-Index: gcc/ada/back_end.ads
-===================================================================
---- a/src/gcc/ada/back_end.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/back_end.ads (.../branches/gcc-4_8-branch)
-@@ -55,6 +55,7 @@
- Complex : Boolean; -- True iff type has real and imaginary parts
- Count : Natural; -- Number of elements in vector, 0 otherwise
- Float_Rep : Float_Rep_Kind; -- Representation used for fpt type
-+ Precision : Positive; -- Precision of representation in bits
- Size : Positive; -- Size of representation in bits
- Alignment : Natural); -- Required alignment in bits
- pragma Convention (C, Register_Type_Proc);
-Index: gcc/ada/system-linux-mipsel.ads
-===================================================================
---- a/src/gcc/ada/system-linux-mipsel.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-linux-mipsel.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (GNU-Linux/MIPSEL Version) --
- -- --
---- Copyright (C) 1992-2012, Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014, Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -62,6 +62,7 @@
- -- Storage-related Declarations
-
- type Address is private;
-+ pragma Preelaborable_Initialization (Address);
- Null_Address : constant Address;
-
- Storage_Unit : constant := 8;
-Index: gcc/ada/system-linux-mips.ads
-===================================================================
---- a/src/gcc/ada/system-linux-mips.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-linux-mips.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (GNU-Linux/MIPS Version) --
- -- --
---- Copyright (C) 1992-2012, Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014, Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -62,6 +62,7 @@
- -- Storage-related Declarations
-
- type Address is private;
-+ pragma Preelaborable_Initialization (Address);
- Null_Address : constant Address;
-
- Storage_Unit : constant := 8;
-Index: gcc/ada/system-linux-mips64el.ads
-===================================================================
---- a/src/gcc/ada/system-linux-mips64el.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-linux-mips64el.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (GNU-Linux/MIPS64EL Version) --
- -- --
---- Copyright (C) 1992-2012, Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014, Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -62,6 +62,7 @@
- -- Storage-related Declarations
-
- type Address is private;
-+ pragma Preelaborable_Initialization (Address);
- Null_Address : constant Address;
-
- Storage_Unit : constant := 8;
-Index: gcc/ada/gcc-interface/utils.c
-===================================================================
---- a/src/gcc/ada/gcc-interface/utils.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/gcc-interface/utils.c (.../branches/gcc-4_8-branch)
-@@ -232,6 +232,7 @@
- static tree split_plus (tree, tree *);
- static tree float_type_for_precision (int, enum machine_mode);
- static tree convert_to_fat_pointer (tree, tree);
-+static unsigned int scale_by_factor_of (tree, unsigned int);
- static bool potential_alignment_gap (tree, tree, tree);
- static void process_attributes (tree, struct attrib *);
-
-@@ -532,6 +533,22 @@
- free_binding_level = level;
- }
-
-+/* Set the context of TYPE and its parallel types (if any) to CONTEXT. */
-+
-+static void
-+gnat_set_type_context (tree type, tree context)
-+{
-+ tree decl = TYPE_STUB_DECL (type);
-+
-+ TYPE_CONTEXT (type) = context;
-+
-+ while (decl && DECL_PARALLEL_TYPE (decl))
-+ {
-+ TYPE_CONTEXT (DECL_PARALLEL_TYPE (decl)) = context;
-+ decl = TYPE_STUB_DECL (DECL_PARALLEL_TYPE (decl));
-+ }
-+}
-+
- /* Record DECL as belonging to the current lexical scope and use GNAT_NODE
- for location information and flag propagation. */
-
-@@ -613,7 +630,7 @@
- if (TREE_CODE (t) == POINTER_TYPE)
- TYPE_NEXT_PTR_TO (t) = tt;
- TYPE_NAME (tt) = DECL_NAME (decl);
-- TYPE_CONTEXT (tt) = DECL_CONTEXT (decl);
-+ gnat_set_type_context (tt, DECL_CONTEXT (decl));
- TYPE_STUB_DECL (tt) = TYPE_STUB_DECL (t);
- DECL_ORIGINAL_TYPE (decl) = tt;
- }
-@@ -623,7 +640,7 @@
- /* We need a variant for the placeholder machinery to work. */
- tree tt = build_variant_type_copy (t);
- TYPE_NAME (tt) = decl;
-- TYPE_CONTEXT (tt) = DECL_CONTEXT (decl);
-+ gnat_set_type_context (tt, DECL_CONTEXT (decl));
- TREE_USED (tt) = TREE_USED (t);
- TREE_TYPE (decl) = tt;
- if (DECL_ORIGINAL_TYPE (TYPE_NAME (t)))
-@@ -645,7 +662,7 @@
- if (!(TYPE_NAME (t) && TREE_CODE (TYPE_NAME (t)) == TYPE_DECL))
- {
- TYPE_NAME (t) = decl;
-- TYPE_CONTEXT (t) = DECL_CONTEXT (decl);
-+ gnat_set_type_context (t, DECL_CONTEXT (decl));
- }
- }
- }
-@@ -1692,93 +1709,74 @@
- TYPE_SIZE_UNIT (new_record_type)
- = size_int (TYPE_ALIGN (record_type) / BITS_PER_UNIT);
-
-- /* Now scan all the fields, replacing each field with a new
-- field corresponding to the new encoding. */
-+ /* Now scan all the fields, replacing each field with a new field
-+ corresponding to the new encoding. */
- for (old_field = TYPE_FIELDS (record_type); old_field;
- old_field = DECL_CHAIN (old_field))
- {
- tree field_type = TREE_TYPE (old_field);
- tree field_name = DECL_NAME (old_field);
-- tree new_field;
- tree curpos = bit_position (old_field);
-+ tree pos, new_field;
- bool var = false;
- unsigned int align = 0;
-- tree pos;
-
-+ /* We're going to do some pattern matching below so remove as many
-+ conversions as possible. */
-+ curpos = remove_conversions (curpos, true);
-+
- /* See how the position was modified from the last position.
-
-- There are two basic cases we support: a value was added
-- to the last position or the last position was rounded to
-- a boundary and they something was added. Check for the
-- first case first. If not, see if there is any evidence
-- of rounding. If so, round the last position and try
-- again.
-+ There are two basic cases we support: a value was added
-+ to the last position or the last position was rounded to
-+ a boundary and they something was added. Check for the
-+ first case first. If not, see if there is any evidence
-+ of rounding. If so, round the last position and retry.
-
-- If this is a union, the position can be taken as zero. */
--
-- /* Some computations depend on the shape of the position expression,
-- so strip conversions to make sure it's exposed. */
-- curpos = remove_conversions (curpos, true);
--
-+ If this is a union, the position can be taken as zero. */
- if (TREE_CODE (new_record_type) == UNION_TYPE)
-- pos = bitsize_zero_node, align = 0;
-+ pos = bitsize_zero_node;
- else
- pos = compute_related_constant (curpos, last_pos);
-
-- if (!pos && TREE_CODE (curpos) == MULT_EXPR
-+ if (!pos
-+ && TREE_CODE (curpos) == MULT_EXPR
- && host_integerp (TREE_OPERAND (curpos, 1), 1))
- {
- tree offset = TREE_OPERAND (curpos, 0);
- align = tree_low_cst (TREE_OPERAND (curpos, 1), 1);
--
-- /* An offset which is a bitwise AND with a mask increases the
-- alignment according to the number of trailing zeros. */
-- offset = remove_conversions (offset, true);
-- if (TREE_CODE (offset) == BIT_AND_EXPR
-- && TREE_CODE (TREE_OPERAND (offset, 1)) == INTEGER_CST)
-- {
-- unsigned HOST_WIDE_INT mask
-- = TREE_INT_CST_LOW (TREE_OPERAND (offset, 1));
-- unsigned int i;
--
-- for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
-- {
-- if (mask & 1)
-- break;
-- mask >>= 1;
-- align *= 2;
-- }
-- }
--
-- pos = compute_related_constant (curpos,
-- round_up (last_pos, align));
-+ align = scale_by_factor_of (offset, align);
-+ last_pos = round_up (last_pos, align);
-+ pos = compute_related_constant (curpos, last_pos);
- }
-- else if (!pos && TREE_CODE (curpos) == PLUS_EXPR
-- && TREE_CODE (TREE_OPERAND (curpos, 1)) == INTEGER_CST
-+ else if (!pos
-+ && TREE_CODE (curpos) == PLUS_EXPR
-+ && host_integerp (TREE_OPERAND (curpos, 1), 1)
- && TREE_CODE (TREE_OPERAND (curpos, 0)) == MULT_EXPR
-- && host_integerp (TREE_OPERAND
-- (TREE_OPERAND (curpos, 0), 1),
-- 1))
-+ && host_integerp
-+ (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1))
- {
-+ tree offset = TREE_OPERAND (TREE_OPERAND (curpos, 0), 0);
-+ unsigned HOST_WIDE_INT addend
-+ = tree_low_cst (TREE_OPERAND (curpos, 1), 1);
- align
-- = tree_low_cst
-- (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1);
-- pos = compute_related_constant (curpos,
-- round_up (last_pos, align));
-+ = tree_low_cst (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1);
-+ align = scale_by_factor_of (offset, align);
-+ align = MIN (align, addend & -addend);
-+ last_pos = round_up (last_pos, align);
-+ pos = compute_related_constant (curpos, last_pos);
- }
-- else if (potential_alignment_gap (prev_old_field, old_field,
-- pos))
-+ else if (potential_alignment_gap (prev_old_field, old_field, pos))
- {
- align = TYPE_ALIGN (field_type);
-- pos = compute_related_constant (curpos,
-- round_up (last_pos, align));
-+ last_pos = round_up (last_pos, align);
-+ pos = compute_related_constant (curpos, last_pos);
- }
-
- /* If we can't compute a position, set it to zero.
-
-- ??? We really should abort here, but it's too much work
-- to get this correct for all cases. */
--
-+ ??? We really should abort here, but it's too much work
-+ to get this correct for all cases. */
- if (!pos)
- pos = bitsize_zero_node;
-
-@@ -2553,6 +2551,32 @@
- return false;
- }
-
-+/* Return VALUE scaled by the biggest power-of-2 factor of EXPR. */
-+
-+static unsigned int
-+scale_by_factor_of (tree expr, unsigned int value)
-+{
-+ expr = remove_conversions (expr, true);
-+
-+ /* An expression which is a bitwise AND with a mask has a power-of-2 factor
-+ corresponding to the number of trailing zeros of the mask. */
-+ if (TREE_CODE (expr) == BIT_AND_EXPR
-+ && TREE_CODE (TREE_OPERAND (expr, 1)) == INTEGER_CST)
-+ {
-+ unsigned HOST_WIDE_INT mask = TREE_INT_CST_LOW (TREE_OPERAND (expr, 1));
-+ unsigned int i = 0;
-+
-+ while ((mask & 1) == 0 && i < HOST_BITS_PER_WIDE_INT)
-+ {
-+ mask >>= 1;
-+ value *= 2;
-+ i++;
-+ }
-+ }
-+
-+ return value;
-+}
-+
- /* Given two consecutive field decls PREV_FIELD and CURR_FIELD, return true
- unless we can prove these 2 fields are laid out in such a way that no gap
- exist between the end of PREV_FIELD and the beginning of CURR_FIELD. OFFSET
-Index: gcc/ada/gcc-interface/Makefile.in
-===================================================================
---- a/src/gcc/ada/gcc-interface/Makefile.in (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/gcc-interface/Makefile.in (.../branches/gcc-4_8-branch)
-@@ -2397,7 +2397,7 @@
- "GNATLINK=$(GNATLINK)" \
- "GNATBIND=$(GNATBIND)"
-
--GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES)
-+GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) $(LDFLAGS)
-
- # Build directory for the tools. Let's copy the target-dependent
- # sources using the same mechanism as for gnatlib. The other sources are
-@@ -2519,12 +2519,10 @@
-
- # Likewise for the tools
- ../../gnatmake$(exeext): $(P) b_gnatm.o link.o targext.o $(GNATMAKE_OBJS)
-- $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) \
-- $(TOOLS_LIBS)
-+ +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) $(TOOLS_LIBS)
-
- ../../gnatlink$(exeext): $(P) b_gnatl.o link.o targext.o $(GNATLINK_OBJS)
-- $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) \
-- $(TOOLS_LIBS)
-+ +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) $(TOOLS_LIBS)
-
- ../stamp-gnatlib-$(RTSDIR):
- @if [ ! -f stamp-gnatlib-$(RTSDIR) ] ; \
-Index: gcc/ada/gcc-interface/cuintp.c
-===================================================================
---- a/src/gcc/ada/gcc-interface/cuintp.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/gcc-interface/cuintp.c (.../branches/gcc-4_8-branch)
-@@ -6,7 +6,7 @@
- * *
- * C Implementation File *
- * *
-- * Copyright (C) 1992-2012, Free Software Foundation, Inc. *
-+ * Copyright (C) 1992-2014, Free Software Foundation, Inc. *
- * *
- * GNAT is free software; you can redistribute it and/or modify it under *
- * terms of the GNU General Public License as published by the Free Soft- *
-@@ -59,8 +59,8 @@
- static tree
- build_cst_from_int (tree type, HOST_WIDE_INT low)
- {
-- if (TREE_CODE (type) == REAL_TYPE)
-- return convert (type, build_int_cst (NULL_TREE, low));
-+ if (SCALAR_FLOAT_TYPE_P (type))
-+ return convert (type, build_int_cst (gnat_type_for_size (32, 0), low));
- else
- return build_int_cst_type (type, low);
- }
-@@ -99,20 +99,13 @@
- gcc_assert (Length > 0);
-
- /* The computations we perform below always require a type at least as
-- large as an integer not to overflow. REAL types are always fine, but
-+ large as an integer not to overflow. FP types are always fine, but
- INTEGER or ENUMERAL types we are handed may be too short. We use a
- base integer type node for the computations in this case and will
-- convert the final result back to the incoming type later on.
-- The base integer precision must be superior than 16. */
-+ convert the final result back to the incoming type later on. */
-+ if (!SCALAR_FLOAT_TYPE_P (comp_type) && TYPE_PRECISION (comp_type) < 32)
-+ comp_type = gnat_type_for_size (32, 0);
-
-- if (TREE_CODE (comp_type) != REAL_TYPE
-- && TYPE_PRECISION (comp_type)
-- < TYPE_PRECISION (long_integer_type_node))
-- {
-- comp_type = long_integer_type_node;
-- gcc_assert (TYPE_PRECISION (comp_type) > 16);
-- }
--
- gnu_base = build_cst_from_int (comp_type, Base);
-
- gnu_ret = build_cst_from_int (comp_type, First);
-Index: gcc/ada/gcc-interface/Make-lang.in
-===================================================================
---- a/src/gcc/ada/gcc-interface/Make-lang.in (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/gcc-interface/Make-lang.in (.../branches/gcc-4_8-branch)
-@@ -625,7 +625,7 @@
- ada/doctools/xgnatugn$(build_exeext): ada/xgnatugn.adb
- -$(MKDIR) ada/doctools
- $(CP) $^ ada/doctools
-- cd ada/doctools && $(GNATMAKE) -q xgnatugn
-+ cd ada/doctools && gnatmake -q xgnatugn
-
- # Note that doc/gnat_ugn.texi and doc/projects.texi do not depend on
- # xgnatugn being built so we can distribute a pregenerated doc/gnat_ugn.info
-Index: gcc/ada/gcc-interface/gigi.h
-===================================================================
---- a/src/gcc/ada/gcc-interface/gigi.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/gcc-interface/gigi.h (.../branches/gcc-4_8-branch)
-@@ -1014,7 +1014,7 @@
- /* This function is called by the front-end to enumerate all the supported
- modes for the machine, as well as some predefined C types. */
- extern void enumerate_modes (void (*f) (const char *, int, int, int, int, int,
-- int));
-+ int, int));
-
- #ifdef __cplusplus
- }
-Index: gcc/ada/gcc-interface/misc.c
-===================================================================
---- a/src/gcc/ada/gcc-interface/misc.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/gcc-interface/misc.c (.../branches/gcc-4_8-branch)
-@@ -648,7 +648,7 @@
- /* This function is called by the front-end to enumerate all the supported
- modes for the machine, as well as some predefined C types. F is a function
- which is called back with the parameters as listed below, first a string,
-- then six ints. The name is any arbitrary null-terminated string and has
-+ then seven ints. The name is any arbitrary null-terminated string and has
- no particular significance, except for the case of predefined C types, where
- it should be the name of the C type. For integer types, only signed types
- should be listed, unsigned versions are assumed. The order of types should
-@@ -664,11 +664,12 @@
- COMPLEX_P nonzero is this represents a complex mode
- COUNT count of number of items, nonzero for vector mode
- FLOAT_REP Float_Rep_Kind for FP, otherwise undefined
-- SIZE number of bits used to store data
-+ PRECISION number of bits used to store data
-+ SIZE number of bits occupied by the mode
- ALIGN number of bits to which mode is aligned. */
-
- void
--enumerate_modes (void (*f) (const char *, int, int, int, int, int, int))
-+enumerate_modes (void (*f) (const char *, int, int, int, int, int, int, int))
- {
- const tree c_types[]
- = { float_type_node, double_type_node, long_double_type_node };
-@@ -742,28 +743,26 @@
-
- /* First register any C types for this mode that the front end
- may need to know about, unless the mode should be skipped. */
--
-- if (!skip_p)
-+ if (!skip_p && !vector_p)
- for (nameloop = 0; nameloop < ARRAY_SIZE (c_types); nameloop++)
- {
-- tree typ = c_types[nameloop];
-- const char *nam = c_names[nameloop];
-+ tree type = c_types[nameloop];
-+ const char *name = c_names[nameloop];
-
-- if (TYPE_MODE (typ) == i)
-+ if (TYPE_MODE (type) == i)
- {
-- f (nam, digs, complex_p,
-- vector_p ? GET_MODE_NUNITS (i) : 0, float_rep,
-- TYPE_PRECISION (typ), TYPE_ALIGN (typ));
-+ f (name, digs, complex_p, 0, float_rep, TYPE_PRECISION (type),
-+ TREE_INT_CST_LOW (TYPE_SIZE (type)), TYPE_ALIGN (type));
- skip_p = true;
- }
- }
-
- /* If no predefined C types were found, register the mode itself. */
--
- if (!skip_p)
- f (GET_MODE_NAME (i), digs, complex_p,
- vector_p ? GET_MODE_NUNITS (i) : 0, float_rep,
-- GET_MODE_PRECISION (i), GET_MODE_ALIGNMENT (i));
-+ GET_MODE_PRECISION (i), GET_MODE_BITSIZE (i),
-+ GET_MODE_ALIGNMENT (i));
- }
- }
-
-Index: gcc/ada/system-linux-sparc.ads
-===================================================================
---- a/src/gcc/ada/system-linux-sparc.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-linux-sparc.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (GNU/Linux-SPARC Version) --
- -- --
---- Copyright (C) 1992-2012, Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014, Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -35,9 +35,10 @@
- ------------------------------------------------------------------------------
-
- package System is
--pragma Pure (System);
---- Note that we take advantage of the implementation permission to
---- make this unit Pure instead of Preelaborable, see RM 13.7(36)
-+ pragma Pure;
-+ -- Note that we take advantage of the implementation permission to make
-+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
-+ -- 2005, this is Pure in any case (AI-362).
-
- type Name is (SYSTEM_NAME_GNAT);
- System_Name : constant Name := SYSTEM_NAME_GNAT;
-@@ -61,6 +62,7 @@
- -- Storage-related Declarations
-
- type Address is private;
-+ pragma Preelaborable_Initialization (Address);
- Null_Address : constant Address;
-
- Storage_Unit : constant := 8;
-Index: gcc/ada/system-rtems.ads
-===================================================================
---- a/src/gcc/ada/system-rtems.ads (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ada/system-rtems.ads (.../branches/gcc-4_8-branch)
-@@ -7,7 +7,7 @@
- -- S p e c --
- -- (Compiler Version) --
- -- --
---- Copyright (C) 1992-2011 Free Software Foundation, Inc. --
-+-- Copyright (C) 1992-2014 Free Software Foundation, Inc. --
- -- --
- -- This specification is derived from the Ada Reference Manual for use with --
- -- GNAT. The copyright notice above, and the license provisions that follow --
-@@ -34,9 +34,8 @@
- -- --
- ------------------------------------------------------------------------------
-
---- This version of System is a RTEMS version that is used in building
---- the compiler. This is based as closely as possible on the generic
---- version with the following exceptions:
-+-- This version is for RTEMS. It is based as closely as possible on the
-+-- generic version with the following exceptions:
- -- + priority definitions
-
- package System is
-@@ -67,6 +66,7 @@
- -- Storage-related Declarations
-
- type Address is private;
-+ pragma Preelaborable_Initialization (Address);
- Null_Address : constant Address;
-
- Storage_Unit : constant := Standard'Storage_Unit;
-Index: gcc/dse.c
-===================================================================
---- a/src/gcc/dse.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/dse.c (.../branches/gcc-4_8-branch)
-@@ -2518,7 +2518,8 @@
- /* Cselib clears the table for this case, so we have to essentially
- do the same. */
- if (NONJUMP_INSN_P (insn)
-- && volatile_insn_p (PATTERN (insn)))
-+ && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
-+ && MEM_VOLATILE_P (PATTERN (insn)))
- {
- add_wild_read (bb_info);
- insn_info->cannot_delete = true;
-Index: gcc/gimple-ssa-strength-reduction.c
-===================================================================
---- a/src/gcc/gimple-ssa-strength-reduction.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/gimple-ssa-strength-reduction.c (.../branches/gcc-4_8-branch)
-@@ -735,15 +735,18 @@
- X = Y * c
- ============================
- X = (B + i') * (S * c) */
-- base = base_cand->base_expr;
-- index = base_cand->index;
- temp = tree_to_double_int (base_cand->stride)
- * tree_to_double_int (stride_in);
-- stride = double_int_to_tree (TREE_TYPE (stride_in), temp);
-- ctype = base_cand->cand_type;
-- if (has_single_use (base_in))
-- savings = (base_cand->dead_savings
-- + stmt_cost (base_cand->cand_stmt, speed));
-+ if (double_int_fits_to_tree_p (TREE_TYPE (stride_in), temp))
-+ {
-+ base = base_cand->base_expr;
-+ index = base_cand->index;
-+ stride = double_int_to_tree (TREE_TYPE (stride_in), temp);
-+ ctype = base_cand->cand_type;
-+ if (has_single_use (base_in))
-+ savings = (base_cand->dead_savings
-+ + stmt_cost (base_cand->cand_stmt, speed));
-+ }
- }
- else if (base_cand->kind == CAND_ADD
- && operand_equal_p (base_cand->stride, integer_one_node, 0))
-Index: gcc/tree-eh.c
-===================================================================
---- a/src/gcc/tree-eh.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-eh.c (.../branches/gcc-4_8-branch)
-@@ -1357,9 +1357,6 @@
- x = gimple_seq_last_stmt (finally);
- finally_loc = x ? gimple_location (x) : tf_loc;
-
-- /* Lower the finally block itself. */
-- lower_eh_constructs_1 (state, &finally);
--
- /* Prepare for switch statement generation. */
- nlabels = tf->dest_array.length ();
- return_index = nlabels;
-@@ -1445,6 +1442,7 @@
- x = gimple_build_label (finally_label);
- gimple_seq_add_stmt (&tf->top_p_seq, x);
-
-+ lower_eh_constructs_1 (state, &finally);
- gimple_seq_add_seq (&tf->top_p_seq, finally);
-
- /* Redirect each incoming goto edge. */
-@@ -2502,12 +2500,6 @@
- restart:
- switch (code)
- {
-- case TARGET_MEM_REF:
-- if (TREE_CODE (TMR_BASE (expr)) == ADDR_EXPR
-- && !TMR_INDEX (expr) && !TMR_INDEX2 (expr))
-- return false;
-- return !TREE_THIS_NOTRAP (expr);
--
- case COMPONENT_REF:
- case REALPART_EXPR:
- case IMAGPART_EXPR:
-@@ -2534,10 +2526,36 @@
- return false;
- return !in_array_bounds_p (expr);
-
-+ case TARGET_MEM_REF:
- case MEM_REF:
-+ if (TREE_CODE (TREE_OPERAND (expr, 0)) == ADDR_EXPR
-+ && tree_could_trap_p (TREE_OPERAND (TREE_OPERAND (expr, 0), 0)))
-+ return true;
-+ if (TREE_THIS_NOTRAP (expr))
-+ return false;
-+ /* We cannot prove that the access is in-bounds when we have
-+ variable-index TARGET_MEM_REFs. */
-+ if (code == TARGET_MEM_REF
-+ && (TMR_INDEX (expr) || TMR_INDEX2 (expr)))
-+ return true;
- if (TREE_CODE (TREE_OPERAND (expr, 0)) == ADDR_EXPR)
-- return false;
-- /* Fallthru. */
-+ {
-+ tree base = TREE_OPERAND (TREE_OPERAND (expr, 0), 0);
-+ double_int off = mem_ref_offset (expr);
-+ if (off.is_negative ())
-+ return true;
-+ if (TREE_CODE (base) == STRING_CST)
-+ return double_int::from_uhwi (TREE_STRING_LENGTH (base)).ule (off);
-+ else if (DECL_SIZE_UNIT (base) == NULL_TREE
-+ || TREE_CODE (DECL_SIZE_UNIT (base)) != INTEGER_CST
-+ || tree_to_double_int (DECL_SIZE_UNIT (base)).ule (off))
-+ return true;
-+ /* Now we are sure the first byte of the access is inside
-+ the object. */
-+ return false;
-+ }
-+ return true;
-+
- case INDIRECT_REF:
- return !TREE_THIS_NOTRAP (expr);
-
-@@ -4166,8 +4184,11 @@
- /* If the block is totally empty, look for more unsplitting cases. */
- if (gsi_end_p (gsi))
- {
-- /* For the degenerate case of an infinite loop bail out. */
-- if (infinite_empty_loop_p (e_out))
-+ /* For the degenerate case of an infinite loop bail out.
-+ If bb has no successors and is totally empty, which can happen e.g.
-+ because of incorrect noreturn attribute, bail out too. */
-+ if (e_out == NULL
-+ || infinite_empty_loop_p (e_out))
- return ret;
-
- return ret | cleanup_empty_eh_unsplit (bb, e_out, lp);
-@@ -4304,11 +4325,12 @@
- remove_unreachable_handlers ();
-
- /* Watch out for the region tree vanishing due to all unreachable. */
-- if (cfun->eh->region_tree && optimize)
-+ if (cfun->eh->region_tree)
- {
- bool changed = false;
-
-- changed |= unsplit_all_eh ();
-+ if (optimize)
-+ changed |= unsplit_all_eh ();
- changed |= cleanup_all_empty_eh ();
-
- if (changed)
-Index: gcc/fortran/interface.c
-===================================================================
---- a/src/gcc/fortran/interface.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/interface.c (.../branches/gcc-4_8-branch)
-@@ -1245,7 +1245,8 @@
- return FAILURE;
- }
-
-- if (r1->ts.u.cl->length)
-+ if (s1->ts.u.cl && s1->ts.u.cl->length
-+ && s2->ts.u.cl && s2->ts.u.cl->length)
- {
- int compval = gfc_dep_compare_expr (r1->ts.u.cl->length,
- r2->ts.u.cl->length);
-@@ -1367,8 +1368,8 @@
- if (s1->attr.function && s2->attr.function)
- {
- /* If both are functions, check result characteristics. */
-- if (check_result_characteristics (s1, s2, errmsg, err_len)
-- == FAILURE)
-+ if (check_result_characteristics (s1, s2, errmsg, err_len) == FAILURE
-+ || check_result_characteristics (s2, s1, errmsg, err_len) == FAILURE)
- return 0;
- }
-
-Index: gcc/fortran/intrinsic.c
-===================================================================
---- a/src/gcc/fortran/intrinsic.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/intrinsic.c (.../branches/gcc-4_8-branch)
-@@ -4229,7 +4229,7 @@
- c->resolved_sym->attr.elemental = isym->elemental;
- }
-
-- if (gfc_pure (NULL) && !isym->pure)
-+ if (!isym->pure && gfc_pure (NULL))
- {
- gfc_error ("Subroutine call to intrinsic '%s' at %L is not PURE", name,
- &c->loc);
-@@ -4236,6 +4236,9 @@
- return MATCH_ERROR;
- }
-
-+ if (!isym->pure)
-+ gfc_unset_implicit_pure (NULL);
-+
- c->resolved_sym->attr.noreturn = isym->noreturn;
-
- return MATCH_YES;
-Index: gcc/fortran/trans-expr.c
-===================================================================
---- a/src/gcc/fortran/trans-expr.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/trans-expr.c (.../branches/gcc-4_8-branch)
-@@ -355,7 +355,11 @@
- gfc_conv_expr_descriptor (parmse, e);
-
- if (e->rank != class_ts.u.derived->components->as->rank)
-- class_array_data_assign (&block, ctree, parmse->expr, true);
-+ {
-+ gcc_assert (class_ts.u.derived->components->as->type
-+ == AS_ASSUMED_RANK);
-+ class_array_data_assign (&block, ctree, parmse->expr, false);
-+ }
- else
- {
- if (gfc_expr_attr (e).codimension)
-@@ -670,7 +674,6 @@
- gfc_add_modify (&parmse->post, vptr,
- fold_convert (TREE_TYPE (vptr), ctree));
-
-- gcc_assert (!optional || (optional && !copyback));
- if (optional)
- {
- tree tmp2;
-@@ -6343,7 +6346,13 @@
- /* Returns a reference to the scalar evaluated outside the loop
- for this case. */
- gfc_conv_expr (se, expr);
-- se->expr = gfc_build_addr_expr (NULL_TREE, se->expr);
-+
-+ if (expr->ts.type == BT_CHARACTER
-+ && expr->expr_type != EXPR_FUNCTION)
-+ gfc_conv_string_parameter (se);
-+ else
-+ se->expr = gfc_build_addr_expr (NULL_TREE, se->expr);
-+
- return;
- }
-
-Index: gcc/fortran/trans-array.c
-===================================================================
---- a/src/gcc/fortran/trans-array.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/trans-array.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* Array translation routines
-- Copyright (C) 2002-2013 Free Software Foundation, Inc.
-+ Copyright (C) 2002-2014 Free Software Foundation, Inc.
- Contributed by Paul Brook <paul@nowt.org>
- and Steven Bosscher <s.bosscher@student.tudelft.nl>
-
-@@ -2487,6 +2487,11 @@
- a reference to the value. */
- gfc_conv_expr (&se, expr);
- }
-+
-+ /* Ensure that a pointer to the string is stored. */
-+ if (expr->ts.type == BT_CHARACTER)
-+ gfc_conv_string_parameter (&se);
-+
- gfc_add_block_to_block (&outer_loop->pre, &se.pre);
- gfc_add_block_to_block (&outer_loop->post, &se.post);
- if (gfc_is_class_scalar_expr (expr))
-@@ -7940,6 +7945,7 @@
- tree size1;
- tree size2;
- tree array1;
-+ tree cond_null;
- tree cond;
- tree tmp;
- tree tmp2;
-@@ -8015,9 +8021,9 @@
- jump_label2 = gfc_build_label_decl (NULL_TREE);
-
- /* Allocate if data is NULL. */
-- cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,
-+ cond_null = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,
- array1, build_int_cst (TREE_TYPE (array1), 0));
-- tmp = build3_v (COND_EXPR, cond,
-+ tmp = build3_v (COND_EXPR, cond_null,
- build1_v (GOTO_EXPR, jump_label1),
- build_empty_stmt (input_location));
- gfc_add_expr_to_block (&fblock, tmp);
-@@ -8069,13 +8075,25 @@
- tmp = build1_v (LABEL_EXPR, jump_label1);
- gfc_add_expr_to_block (&fblock, tmp);
-
-- size1 = gfc_conv_descriptor_size (desc, expr1->rank);
-+ /* If the lhs has not been allocated, its bounds will not have been
-+ initialized and so its size is set to zero. */
-+ size1 = gfc_create_var (gfc_array_index_type, NULL);
-+ gfc_init_block (&alloc_block);
-+ gfc_add_modify (&alloc_block, size1, gfc_index_zero_node);
-+ gfc_init_block (&realloc_block);
-+ gfc_add_modify (&realloc_block, size1,
-+ gfc_conv_descriptor_size (desc, expr1->rank));
-+ tmp = build3_v (COND_EXPR, cond_null,
-+ gfc_finish_block (&alloc_block),
-+ gfc_finish_block (&realloc_block));
-+ gfc_add_expr_to_block (&fblock, tmp);
-
-- /* Get the rhs size. Fix both sizes. */
-+ /* Get the rhs size and fix it. */
- if (expr2)
- desc2 = rss->info->data.array.descriptor;
- else
- desc2 = NULL_TREE;
-+
- size2 = gfc_index_one_node;
- for (n = 0; n < expr2->rank; n++)
- {
-@@ -8089,8 +8107,6 @@
- gfc_array_index_type,
- tmp, size2);
- }
--
-- size1 = gfc_evaluate_now (size1, &fblock);
- size2 = gfc_evaluate_now (size2, &fblock);
-
- cond = fold_build2_loc (input_location, NE_EXPR, boolean_type_node,
-Index: gcc/fortran/symbol.c
-===================================================================
---- a/src/gcc/fortran/symbol.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/symbol.c (.../branches/gcc-4_8-branch)
-@@ -1110,8 +1110,8 @@
- return FAILURE;
- }
-
-- if (s == SAVE_EXPLICIT && gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ if (s == SAVE_EXPLICIT)
-+ gfc_unset_implicit_pure (NULL);
-
- if (s == SAVE_EXPLICIT && attr->save == SAVE_EXPLICIT)
- {
-Index: gcc/fortran/class.c
-===================================================================
---- a/src/gcc/fortran/class.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/class.c (.../branches/gcc-4_8-branch)
-@@ -2486,7 +2486,7 @@
- return NULL;
-
- /* Sometimes the typespec is passed from a single call. */
-- if (ts->type == BT_DERIVED)
-+ if (ts->type == BT_DERIVED || ts->type == BT_CLASS)
- return gfc_find_derived_vtab (ts->u.derived);
-
- /* Find the top-level namespace. */
-Index: gcc/fortran/decl.c
-===================================================================
---- a/src/gcc/fortran/decl.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/decl.c (.../branches/gcc-4_8-branch)
-@@ -510,10 +510,8 @@
- free (newdata);
- return MATCH_ERROR;
- }
-+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
--
- /* Mark the variable as having appeared in a data statement. */
- if (gfc_add_data (&sym->attr, sym->name, &sym->declared_at) == FAILURE)
- {
-@@ -571,10 +569,8 @@
- gfc_error ("DATA statement at %C is not allowed in a PURE procedure");
- return MATCH_ERROR;
- }
-+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
--
- return MATCH_YES;
-
- cleanup:
-@@ -1737,6 +1733,7 @@
- "a PURE procedure");
- return MATCH_ERROR;
- }
-+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);
-
- /* Match NULL() initialization. */
- m = gfc_match_null (init);
-@@ -2045,6 +2042,10 @@
- m = MATCH_ERROR;
- }
-
-+ if (current_attr.flavor != FL_PARAMETER
-+ && gfc_state_stack->state != COMP_DERIVED)
-+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);
-+
- if (m != MATCH_YES)
- goto cleanup;
- }
-@@ -5069,7 +5070,14 @@
- if (gfc_add_proc (&c->attr, name, NULL) == FAILURE)
- return MATCH_ERROR;
-
-- c->tb = tb;
-+ if (num == 1)
-+ c->tb = tb;
-+ else
-+ {
-+ c->tb = XCNEW (gfc_typebound_proc);
-+ c->tb->where = gfc_current_locus;
-+ *c->tb = *tb;
-+ }
-
- /* Set interface. */
- if (proc_if != NULL)
-@@ -7384,6 +7392,7 @@
-
-
- /* Check a derived type that is being extended. */
-+
- static gfc_symbol*
- check_extended_derived_type (char *name)
- {
-@@ -7395,14 +7404,15 @@
- return NULL;
- }
-
-+ extended = gfc_find_dt_in_generic (extended);
-+
-+ /* F08:C428. */
- if (!extended)
- {
-- gfc_error ("No such symbol in TYPE definition at %C");
-+ gfc_error ("Symbol '%s' at %C has not been previously defined", name);
- return NULL;
- }
-
-- extended = gfc_find_dt_in_generic (extended);
--
- if (extended->attr.flavor != FL_DERIVED)
- {
- gfc_error ("'%s' in EXTENDS expression at %C is not a "
-Index: gcc/fortran/dump-parse-tree.c
-===================================================================
---- a/src/gcc/fortran/dump-parse-tree.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/dump-parse-tree.c (.../branches/gcc-4_8-branch)
-@@ -110,7 +110,8 @@
- break;
-
- case BT_CHARACTER:
-- show_expr (ts->u.cl->length);
-+ if (ts->u.cl)
-+ show_expr (ts->u.cl->length);
- fprintf(dumpfile, " %d", ts->kind);
- break;
-
-Index: gcc/fortran/cpp.c
-===================================================================
---- a/src/gcc/fortran/cpp.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/cpp.c (.../branches/gcc-4_8-branch)
-@@ -569,6 +569,7 @@
- if (gfc_option.flag_preprocessed)
- return;
-
-+ cpp_change_file (cpp_in, LC_RENAME, _("<built-in>"));
- if (!gfc_cpp_option.no_predefined)
- {
- /* Make sure all of the builtins about to be declared have
-Index: gcc/fortran/gfortran.h
-===================================================================
---- a/src/gcc/fortran/gfortran.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/gfortran.h (.../branches/gcc-4_8-branch)
-@@ -2830,6 +2830,7 @@
- int gfc_impure_variable (gfc_symbol *);
- int gfc_pure (gfc_symbol *);
- int gfc_implicit_pure (gfc_symbol *);
-+void gfc_unset_implicit_pure (gfc_symbol *);
- int gfc_elemental (gfc_symbol *);
- gfc_try gfc_resolve_iterator (gfc_iterator *, bool, bool);
- gfc_try find_forall_index (gfc_expr *, gfc_symbol *, int);
-Index: gcc/fortran/ChangeLog
-===================================================================
---- a/src/gcc/fortran/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,259 @@
-+2014-04-11 Janne Blomqvist <jb@gcc.gnu.org>
-+
-+ * intrinsic.texi (RANDOM_SEED): Improve example.
-+
-+2014-04-10 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-03-22 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR debug/60603
-+ * cpp.c (gfc_cpp_init): Restore cb_change_file call to
-+ <built-in>.
-+
-+2014-03-29 Mikael Morin <mikael@gcc.gnu.org>
-+
-+ PR fortran/60677
-+ * trans-intrinsic.c (gfc_conv_intrinsic_ichar): Enlarge argument
-+ list buffer.
-+
-+2014-03-28 Mikael Morin <mikael@gcc.gnu.org>
-+ Tobias Burnus <burnus@net-b.de>
-+
-+ PR fortran/60576
-+ * trans-expr.c (gfc_conv_derived_to_class): Avoid
-+ generation of out-of-bounds range expr.
-+
-+2014-03-28 Thomas Koenig <tkoenig@gcc.gnu.org>
-+
-+ PR fortran/60522
-+ * frontend-passes.c (cfe_code): Do not walk subtrees
-+ for WHERE.
-+
-+2014-03-20 Tobias Burnus <burnus@net-b.de>
-+
-+ PR fortran/60543
-+ PR fortran/60283
-+ * gfortran.h (gfc_unset_implicit_pure): New prototype.
-+ * resolve.c (gfc_unset_implicit_pure): New.
-+ (resolve_structure_cons, resolve_function,
-+ pure_subroutine, resolve_ordinary_assign): Use it.
-+ * decl.c (match_old_style_init, gfc_match_data,
-+ match_pointer_init, variable_decl): Ditto.
-+ * expr.c (gfc_check_pointer_assign): Ditto.
-+ * intrinsic.c (gfc_intrinsic_sub_interface): Ditto.
-+ * io.c (match_vtag, gfc_match_open, gfc_match_close,
-+ match_filepos, gfc_match_inquire, gfc_match_print,
-+ gfc_match_wait, check_io_constraints): Ditto.
-+ * match.c (gfc_match_critical, gfc_match_stopcode,
-+ lock_unlock_statement, sync_statement, gfc_match_allocate,
-+ gfc_match_deallocate): Ditto.
-+ * parse.c (decode_omp_directive): Ditto.
-+ * symbol.c (gfc_add_save): Ditto.
-+
-+2014-03-08 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/60450
-+ * simplify.c (gfc_simplify_shape): Only clear shape if it was really
-+ created successfully.
-+
-+2014-03-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-02-11 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR fortran/52370
-+ * trans-decl.c (gfc_build_dummy_array_decl): Set TREE_NO_WARNING
-+ on decl if sym->attr.optional.
-+
-+2014-03-02 Mikael Morin <mikael@gcc.gnu.org>
-+
-+ PR fortran/60341
-+ * frontend-passes.c (optimize_comparison): Guard two union accesses
-+ with the corresponding tag checks.
-+
-+2014-02-22 Mikael Morin <mikael@gcc.gnu.org>
-+
-+ PR fortran/59599
-+ * trans-intrinsic.c (gfc_conv_intrinsic_ichar): Calculate the
-+ number of arguments.
-+
-+2014-02-19 Tobias Burnus <burnus@net-b.de>
-+
-+ PR fortran/49397
-+ * expr.c (gfc_check_pointer_assign): Add check for
-+ F2008Cor2, C729.
-+ * trans-decl.c (gfc_get_symbol_decl): Correctly generate
-+ external decl in a corner case.
-+
-+2014-02-19 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backports from mainline:
-+ 2014-02-17 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/55907
-+ * resolve.c (build_default_init_expr): Don't initialize character
-+ variable if -fno-automatic is given.
-+
-+ 2014-02-18 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/60231
-+ * resolve.c (check_generic_tbp_ambiguity): Check for presence of dummy
-+ arguments to prevent ICE.
-+
-+2014-02-09 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-10-21 Tobias Burnus <burnus@net-b.de>
-+
-+ PR fortran/58803
-+ PR fortran/59395
-+ * decl.c (match_ppc_decl): Prevent later double free.
-+
-+2014-02-08 Mikael Morin <mikael@gcc.gnu.org>
-+
-+ PR fortran/57033
-+ * primary.c (gfc_convert_to_structure_constructor): Avoid null pointer
-+ dereference.
-+
-+2014-02-07 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/59906
-+ * trans-stmt.c (gfc_add_loop_ss_code): In the case of character
-+ SS_REFERENCE, use gfc_conv_string_parameter to ensure that a
-+ pointer to the string is stored.
-+ * trans-expr.c (gfc_conv_expr_reference): Likewise, use
-+ gfc_conv_string_parameter to ensure that a pointer to is passed
-+ to the elemental function.
-+
-+2014-02-01 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/59414
-+ * trans-stmt.c (gfc_trans_allocate): Before the pointer
-+ assignment to transfer the source _vptr to a class allocate
-+ expression, the final class reference should be exposed. The
-+ tail that includes the _data and array references is stored.
-+ This reduced expression is transferred to 'lhs' and the _vptr
-+ added. Then the tail is restored to the allocate expression.
-+
-+2014-01-26 Mikael Morin <mikael@gcc.gnu.org>
-+
-+ PR fortran/58007
-+ * module.c
-+ (fp2, find_pointer2): Remove.
-+ (mio_component_ref): Don't forcedfully set the containing derived type
-+ symbol for loading. Remove unused argument.
-+ (mio_ref): Update caller
-+ (skip_list): New argument nest_level. Initialize level with the new
-+ argument.
-+ (read_module): Add forced pointer components association for derived
-+ type symbols.
-+
-+2014-01-19 Paul Thomas <pault@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-12-01 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/58410
-+ * trans-array.c (gfc_alloc_allocatable_for_assignment): Do not
-+ use the array bounds of an unallocated array but set its size
-+ to zero instead.
-+
-+2014-01-19 Paul Thomas <pault@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-12-01 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/34547
-+ * resolve.c (resolve_transfer): EXPR_NULL is always in an
-+ invalid context in a transfer statement.
-+
-+2014-01-11 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-12-29 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/59612
-+ PR fortran/57042
-+ * dump-parse-tree.c (show_typespec): Check for charlen.
-+ * invoke.texi: Fix documentation of -fdump-fortran-optimized and
-+ -fdump-parse-tree.
-+
-+2014-01-04 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2014-01-02 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/59654
-+ * resolve.c (resolve_typebound_procedures): No need to create the vtab
-+ here.
-+
-+2013-12-31 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-12-30 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/58998
-+ * resolve.c (resolve_symbol): Check that symbol is not only flavorless
-+ but also untyped.
-+
-+2013-12-18 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-12-15 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/59493
-+ * class.c (gfc_find_intrinsic_vtab): Handle BT_CLASS.
-+
-+2013-11-30 Paul Thomas <pault@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-11-04 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/57445
-+ * trans-expr.c (gfc_conv_class_to_class): Remove spurious
-+ assert.
-+
-+2013-11-17 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-11-07 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/58471
-+ * primary.c (gfc_expr_attr): Check for result symbol.
-+
-+2013-11-16 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-09-20 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/58099
-+ * expr.c (gfc_check_pointer_assign): Remove second call to
-+ 'gfc_compare_interfaces' with swapped arguments.
-+ * interface.c (gfc_compare_interfaces): Symmetrize the call to
-+ 'check_result_characteristics' by calling it with swapped arguments.
-+
-+2013-11-16 Paul Thomas <pault@gcc.gnu.org>
-+
-+ PR fortran/58771
-+ * trans-io.c (transfer_expr): If the backend_decl for a derived
-+ type is missing, build it with gfc_typenode_for_spec.
-+
-+2013-11-05 Steven G. Kargl <kargl@gcc.gnu.org>
-+
-+ PR fortran/58989
-+ * check.c (gfc_check_reshape): ensure that shape is a constant
-+ expression.
-+
-+2013-11-02 Janus Weil <janus@gcc.gnu.org>
-+
-+ Backport from mainline
-+ 2013-09-23 Janus Weil <janus@gcc.gnu.org>
-+
-+ PR fortran/58355
-+ * decl.c (check_extended_derived_type): Prevent segfault, modify error
-+ message.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: gcc/fortran/trans-stmt.c
-===================================================================
---- a/src/gcc/fortran/trans-stmt.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/trans-stmt.c (.../branches/gcc-4_8-branch)
-@@ -5104,10 +5104,49 @@
- {
- gfc_expr *lhs, *rhs;
- gfc_se lse;
-+ gfc_ref *ref, *class_ref, *tail;
-
-+ /* Find the last class reference. */
-+ class_ref = NULL;
-+ for (ref = e->ref; ref; ref = ref->next)
-+ {
-+ if (ref->type == REF_COMPONENT
-+ && ref->u.c.component->ts.type == BT_CLASS)
-+ class_ref = ref;
-+
-+ if (ref->next == NULL)
-+ break;
-+ }
-+
-+ /* Remove and store all subsequent references after the
-+ CLASS reference. */
-+ if (class_ref)
-+ {
-+ tail = class_ref->next;
-+ class_ref->next = NULL;
-+ }
-+ else
-+ {
-+ tail = e->ref;
-+ e->ref = NULL;
-+ }
-+
- lhs = gfc_expr_to_initialize (e);
- gfc_add_vptr_component (lhs);
-
-+ /* Remove the _vptr component and restore the original tail
-+ references. */
-+ if (class_ref)
-+ {
-+ gfc_free_ref_list (class_ref->next);
-+ class_ref->next = tail;
-+ }
-+ else
-+ {
-+ gfc_free_ref_list (e->ref);
-+ e->ref = tail;
-+ }
-+
- if (class_expr != NULL_TREE)
- {
- /* Polymorphic SOURCE: VPTR must be determined at run time. */
-Index: gcc/fortran/expr.c
-===================================================================
---- a/src/gcc/fortran/expr.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/expr.c (.../branches/gcc-4_8-branch)
-@@ -3555,11 +3555,13 @@
- return FAILURE;
- }
-
-- if (!gfc_compare_interfaces (s2, s1, name, 0, 1,
-- err, sizeof(err), NULL, NULL))
-+ /* Check F2008Cor2, C729. */
-+ if (!s2->attr.intrinsic && s2->attr.if_source == IFSRC_UNKNOWN
-+ && !s2->attr.external && !s2->attr.subroutine && !s2->attr.function)
- {
-- gfc_error ("Interface mismatch in procedure pointer assignment "
-- "at %L: %s", &rvalue->where, err);
-+ gfc_error ("Procedure pointer target '%s' at %L must be either an "
-+ "intrinsic, host or use associated, referenced or have "
-+ "the EXTERNAL attribute", s2->name, &rvalue->where);
- return FAILURE;
- }
-
-@@ -3679,9 +3681,8 @@
- }
-
- if (is_implicit_pure && gfc_impure_variable (rvalue->symtree->n.sym))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (gfc_current_ns->proc_name);
-
--
- if (gfc_has_vector_index (rvalue))
- {
- gfc_error ("Pointer assignment with vector subscript "
-Index: gcc/fortran/module.c
-===================================================================
---- a/src/gcc/fortran/module.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/module.c (.../branches/gcc-4_8-branch)
-@@ -386,37 +386,6 @@
- }
-
-
--/* Recursive function to find a pointer within a tree by brute force. */
--
--static pointer_info *
--fp2 (pointer_info *p, const void *target)
--{
-- pointer_info *q;
--
-- if (p == NULL)
-- return NULL;
--
-- if (p->u.pointer == target)
-- return p;
--
-- q = fp2 (p->left, target);
-- if (q != NULL)
-- return q;
--
-- return fp2 (p->right, target);
--}
--
--
--/* During reading, find a pointer_info node from the pointer value.
-- This amounts to a brute-force search. */
--
--static pointer_info *
--find_pointer2 (void *p)
--{
-- return fp2 (pi_root, p);
--}
--
--
- /* Resolve any fixups using a known pointer. */
-
- static void
-@@ -2522,45 +2491,13 @@
- the namespace and is not loaded again. */
-
- static void
--mio_component_ref (gfc_component **cp, gfc_symbol *sym)
-+mio_component_ref (gfc_component **cp)
- {
-- char name[GFC_MAX_SYMBOL_LEN + 1];
-- gfc_component *q;
- pointer_info *p;
-
- p = mio_pointer_ref (cp);
- if (p->type == P_UNKNOWN)
- p->type = P_COMPONENT;
--
-- if (iomode == IO_OUTPUT)
-- mio_pool_string (&(*cp)->name);
-- else
-- {
-- mio_internal_string (name);
--
-- if (sym && sym->attr.is_class)
-- sym = sym->components->ts.u.derived;
--
-- /* It can happen that a component reference can be read before the
-- associated derived type symbol has been loaded. Return now and
-- wait for a later iteration of load_needed. */
-- if (sym == NULL)
-- return;
--
-- if (sym->components != NULL && p->u.pointer == NULL)
-- {
-- /* Symbol already loaded, so search by name. */
-- q = gfc_find_component (sym, name, true, true);
--
-- if (q)
-- associate_integer_pointer (p, q);
-- }
--
-- /* Make sure this symbol will eventually be loaded. */
-- p = find_pointer2 (sym);
-- if (p->u.rsym.state == UNUSED)
-- p->u.rsym.state = NEEDED;
-- }
- }
-
-
-@@ -2917,7 +2854,7 @@
-
- case REF_COMPONENT:
- mio_symbol_ref (&r->u.c.sym);
-- mio_component_ref (&r->u.c.component, r->u.c.sym);
-+ mio_component_ref (&r->u.c.component);
- break;
-
- case REF_SUBSTRING:
-@@ -3772,7 +3709,9 @@
-
-
- /* Unlike most other routines, the address of the symbol node is already
-- fixed on input and the name/module has already been filled in. */
-+ fixed on input and the name/module has already been filled in.
-+ If you update the symbol format here, don't forget to update read_module
-+ as well (look for "seek to the symbol's component list"). */
-
- static void
- mio_symbol (gfc_symbol *sym)
-@@ -3782,6 +3721,7 @@
- mio_lparen ();
-
- mio_symbol_attribute (&sym->attr);
-+
- mio_typespec (&sym->ts);
- if (sym->ts.type == BT_CLASS)
- sym->attr.class_ok = 1;
-@@ -3812,7 +3752,6 @@
-
- /* Note that components are always saved, even if they are supposed
- to be private. Component access is checked during searching. */
--
- mio_component_list (&sym->components, sym->attr.vtype);
-
- if (sym->components != NULL)
-@@ -3914,14 +3853,17 @@
- }
-
-
--/* Skip a list between balanced left and right parens. */
-+/* Skip a list between balanced left and right parens.
-+ By setting NEST_LEVEL one assumes that a number of NEST_LEVEL opening parens
-+ have been already parsed by hand, and the remaining of the content is to be
-+ skipped here. The default value is 0 (balanced parens). */
-
- static void
--skip_list (void)
-+skip_list (int nest_level = 0)
- {
- int level;
-
-- level = 0;
-+ level = nest_level;
- do
- {
- switch (parse_atom ())
-@@ -4555,7 +4497,6 @@
- info->u.rsym.ns = atom_int;
-
- get_module_locus (&info->u.rsym.where);
-- skip_list ();
-
- /* See if the symbol has already been loaded by a previous module.
- If so, we reference the existing symbol and prevent it from
-@@ -4566,11 +4507,57 @@
-
- if (sym == NULL
- || (sym->attr.flavor == FL_VARIABLE && info->u.rsym.ns !=1))
-- continue;
-+ {
-+ skip_list ();
-+ continue;
-+ }
-
- info->u.rsym.state = USED;
- info->u.rsym.sym = sym;
-+ /* The current symbol has already been loaded, so we can avoid loading
-+ it again. However, if it is a derived type, some of its components
-+ can be used in expressions in the module. To avoid the module loading
-+ failing, we need to associate the module's component pointer indexes
-+ with the existing symbol's component pointers. */
-+ if (sym->attr.flavor == FL_DERIVED)
-+ {
-+ gfc_component *c;
-
-+ /* First seek to the symbol's component list. */
-+ mio_lparen (); /* symbol opening. */
-+ skip_list (); /* skip symbol attribute. */
-+ skip_list (); /* typespec. */
-+ require_atom (ATOM_INTEGER); /* namespace ref. */
-+ require_atom (ATOM_INTEGER); /* common ref. */
-+ skip_list (); /* formal args. */
-+ /* no value. */
-+ skip_list (); /* array_spec. */
-+ require_atom (ATOM_INTEGER); /* result. */
-+ /* not a cray pointer. */
-+
-+ mio_lparen (); /* component list opening. */
-+ for (c = sym->components; c; c = c->next)
-+ {
-+ pointer_info *p;
-+ const char *comp_name;
-+ int n;
-+
-+ mio_lparen (); /* component opening. */
-+ mio_integer (&n);
-+ p = get_integer (n);
-+ if (p->u.pointer == NULL)
-+ associate_integer_pointer (p, c);
-+ mio_pool_string (&comp_name);
-+ gcc_assert (comp_name == c->name);
-+ skip_list (1); /* component end. */
-+ }
-+ mio_rparen (); /* component list closing. */
-+
-+ skip_list (1); /* symbol end. */
-+ }
-+ else
-+ skip_list ();
-+
- /* Some symbols do not have a namespace (eg. formal arguments),
- so the automatic "unique symtree" mechanism must be suppressed
- by marking them as referenced. */
-Index: gcc/fortran/io.c
-===================================================================
---- a/src/gcc/fortran/io.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/io.c (.../branches/gcc-4_8-branch)
-@@ -1309,7 +1309,8 @@
- return MATCH_ERROR;
- }
-
-- if (gfc_pure (NULL) && gfc_impure_variable (result->symtree->n.sym))
-+ bool impure = gfc_impure_variable (result->symtree->n.sym);
-+ if (impure && gfc_pure (NULL))
- {
- gfc_error ("Variable %s cannot be assigned in PURE procedure at %C",
- tag->name);
-@@ -1317,8 +1318,8 @@
- return MATCH_ERROR;
- }
-
-- if (gfc_implicit_pure (NULL) && gfc_impure_variable (result->symtree->n.sym))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ if (impure)
-+ gfc_unset_implicit_pure (NULL);
-
- *v = result;
- return MATCH_YES;
-@@ -1838,8 +1839,7 @@
- goto cleanup;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- warn = (open->err || open->iostat) ? true : false;
-
-@@ -2251,8 +2251,7 @@
- goto cleanup;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- warn = (close->iostat || close->err) ? true : false;
-
-@@ -2419,8 +2418,7 @@
- goto cleanup;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- new_st.op = op;
- new_st.ext.filepos = fp;
-@@ -3276,9 +3274,8 @@
- "an internal file in a PURE procedure",
- io_kind_name (k));
-
-- if (gfc_implicit_pure (NULL) && (k == M_READ || k == M_WRITE))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
--
-+ if (k == M_READ || k == M_WRITE)
-+ gfc_unset_implicit_pure (NULL);
- }
-
- if (k != M_READ)
-@@ -3809,8 +3806,7 @@
- return MATCH_ERROR;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- return MATCH_YES;
- }
-@@ -3969,8 +3965,7 @@
- return MATCH_ERROR;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- new_st.block = gfc_get_code ();
- new_st.block->op = EXEC_IOLENGTH;
-@@ -4023,8 +4018,7 @@
- goto cleanup;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- if (inquire->id != NULL && inquire->pending == NULL)
- {
-@@ -4212,8 +4206,7 @@
- goto cleanup;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- new_st.op = EXEC_WAIT;
- new_st.ext.wait = wait;
-Index: gcc/fortran/frontend-passes.c
-===================================================================
---- a/src/gcc/fortran/frontend-passes.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/frontend-passes.c (.../branches/gcc-4_8-branch)
-@@ -623,12 +623,35 @@
- to insert statements as needed. */
-
- static int
--cfe_code (gfc_code **c, int *walk_subtrees ATTRIBUTE_UNUSED,
-- void *data ATTRIBUTE_UNUSED)
-+cfe_code (gfc_code **c, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
- {
- current_code = c;
- inserted_block = NULL;
- changed_statement = NULL;
-+
-+ /* Do not do anything inside a WHERE statement; scalar assignments, BLOCKs
-+ and allocation on assigment are prohibited inside WHERE, and finally
-+ masking an expression would lead to wrong-code when replacing
-+
-+ WHERE (a>0)
-+ b = sum(foo(a) + foo(a))
-+ END WHERE
-+
-+ with
-+
-+ WHERE (a > 0)
-+ tmp = foo(a)
-+ b = sum(tmp + tmp)
-+ END WHERE
-+*/
-+
-+ if ((*c)->op == EXEC_WHERE)
-+ {
-+ *walk_subtrees = 0;
-+ return 0;
-+ }
-+
-+
- return 0;
- }
-
-@@ -1214,7 +1237,9 @@
- /* Replace A // B < A // C with B < C, and A // B < C // B
- with A < C. */
- if (op1->ts.type == BT_CHARACTER && op2->ts.type == BT_CHARACTER
-+ && op1->expr_type == EXPR_OP
- && op1->value.op.op == INTRINSIC_CONCAT
-+ && op2->expr_type == EXPR_OP
- && op2->value.op.op == INTRINSIC_CONCAT)
- {
- gfc_expr *op1_left = op1->value.op.op1;
-Index: gcc/fortran/resolve.c
-===================================================================
---- a/src/gcc/fortran/resolve.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/resolve.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* Perform type resolution on the various structures.
-- Copyright (C) 2001-2013 Free Software Foundation, Inc.
-+ Copyright (C) 2001-2014 Free Software Foundation, Inc.
- Contributed by Andy Vaught
-
- This file is part of GCC.
-@@ -1259,9 +1259,10 @@
- }
-
- /* F2003, C1272 (3). */
-- if (gfc_pure (NULL) && cons->expr->expr_type == EXPR_VARIABLE
-- && (gfc_impure_variable (cons->expr->symtree->n.sym)
-- || gfc_is_coindexed (cons->expr)))
-+ bool impure = cons->expr->expr_type == EXPR_VARIABLE
-+ && (gfc_impure_variable (cons->expr->symtree->n.sym)
-+ || gfc_is_coindexed (cons->expr));
-+ if (impure && gfc_pure (NULL))
- {
- t = FAILURE;
- gfc_error ("Invalid expression in the structure constructor for "
-@@ -1269,12 +1270,8 @@
- comp->name, &cons->expr->where);
- }
-
-- if (gfc_implicit_pure (NULL)
-- && cons->expr->expr_type == EXPR_VARIABLE
-- && (gfc_impure_variable (cons->expr->symtree->n.sym)
-- || gfc_is_coindexed (cons->expr)))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
--
-+ if (impure)
-+ gfc_unset_implicit_pure (NULL);
- }
-
- return t;
-@@ -3295,8 +3292,7 @@
- t = FAILURE;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
- }
-
- /* Functions without the RECURSIVE attribution are not allowed to
-@@ -3361,8 +3357,7 @@
- gfc_error ("Subroutine call to '%s' at %L is not PURE", sym->name,
- &c->loc);
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
- }
-
-
-@@ -8705,10 +8700,11 @@
- && exp->value.op.op == INTRINSIC_PARENTHESES)
- exp = exp->value.op.op1;
-
-- if (exp && exp->expr_type == EXPR_NULL && exp->ts.type == BT_UNKNOWN)
-+ if (exp && exp->expr_type == EXPR_NULL
-+ && code->ext.dt)
- {
-- gfc_error ("NULL intrinsic at %L in data transfer statement requires "
-- "MOLD=", &exp->where);
-+ gfc_error ("Invalid context for NULL () intrinsic at %L",
-+ &exp->where);
- return;
- }
-
-@@ -9612,7 +9608,7 @@
- if (lhs->expr_type == EXPR_VARIABLE
- && lhs->symtree->n.sym != gfc_current_ns->proc_name
- && lhs->symtree->n.sym->ns != gfc_current_ns)
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- if (lhs->ts.type == BT_DERIVED
- && lhs->expr_type == EXPR_VARIABLE
-@@ -9620,11 +9616,11 @@
- && rhs->expr_type == EXPR_VARIABLE
- && (gfc_impure_variable (rhs->symtree->n.sym)
- || gfc_is_coindexed (rhs)))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- /* Fortran 2008, C1283. */
- if (gfc_is_coindexed (lhs))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
- }
-
- /* F03:7.4.1.2. */
-@@ -11057,7 +11053,7 @@
- init_expr = NULL;
- }
- if (!init_expr && gfc_option.flag_init_character == GFC_INIT_CHARACTER_ON
-- && sym->ts.u.cl->length)
-+ && sym->ts.u.cl->length && gfc_option.flag_max_stack_var_size != 0)
- {
- gfc_actual_arglist *arg;
- init_expr = gfc_get_expr ();
-@@ -11877,6 +11873,7 @@
- {
- gfc_symbol *sym1, *sym2;
- const char *pass1, *pass2;
-+ gfc_formal_arglist *dummy_args;
-
- gcc_assert (t1->specific && t2->specific);
- gcc_assert (!t1->specific->is_generic);
-@@ -11899,19 +11896,33 @@
- return FAILURE;
- }
-
-- /* Compare the interfaces. */
-+ /* Determine PASS arguments. */
- if (t1->specific->nopass)
- pass1 = NULL;
- else if (t1->specific->pass_arg)
- pass1 = t1->specific->pass_arg;
- else
-- pass1 = gfc_sym_get_dummy_args (t1->specific->u.specific->n.sym)->sym->name;
-+ {
-+ dummy_args = gfc_sym_get_dummy_args (t1->specific->u.specific->n.sym);
-+ if (dummy_args)
-+ pass1 = dummy_args->sym->name;
-+ else
-+ pass1 = NULL;
-+ }
- if (t2->specific->nopass)
- pass2 = NULL;
- else if (t2->specific->pass_arg)
- pass2 = t2->specific->pass_arg;
- else
-- pass2 = gfc_sym_get_dummy_args (t2->specific->u.specific->n.sym)->sym->name;
-+ {
-+ dummy_args = gfc_sym_get_dummy_args (t2->specific->u.specific->n.sym);
-+ if (dummy_args)
-+ pass2 = dummy_args->sym->name;
-+ else
-+ pass2 = NULL;
-+ }
-+
-+ /* Compare the interfaces. */
- if (gfc_compare_interfaces (sym1, sym2, sym2->name, !t1->is_operator, 0,
- NULL, 0, pass1, pass2))
- {
-@@ -12425,9 +12436,6 @@
- resolve_bindings_derived = derived;
- resolve_bindings_result = SUCCESS;
-
-- /* Make sure the vtab has been generated. */
-- gfc_find_derived_vtab (derived);
--
- if (derived->f2k_derived->tb_sym_root)
- gfc_traverse_symtree (derived->f2k_derived->tb_sym_root,
- &resolve_typebound_procedure);
-@@ -13256,7 +13264,8 @@
- if (sym->attr.flavor == FL_UNKNOWN
- || (sym->attr.flavor == FL_PROCEDURE && !sym->attr.intrinsic
- && !sym->attr.generic && !sym->attr.external
-- && sym->attr.if_source == IFSRC_UNKNOWN))
-+ && sym->attr.if_source == IFSRC_UNKNOWN
-+ && sym->ts.type == BT_UNKNOWN))
- {
-
- /* If we find that a flavorless symbol is an interface in one of the
-@@ -14376,6 +14385,33 @@
- }
-
-
-+void
-+gfc_unset_implicit_pure (gfc_symbol *sym)
-+{
-+ gfc_namespace *ns;
-+
-+ if (sym == NULL)
-+ {
-+ /* Check if the current procedure is implicit_pure. Walk up
-+ the procedure list until we find a procedure. */
-+ for (ns = gfc_current_ns; ns; ns = ns->parent)
-+ {
-+ sym = ns->proc_name;
-+ if (sym == NULL)
-+ return;
-+
-+ if (sym->attr.flavor == FL_PROCEDURE)
-+ break;
-+ }
-+ }
-+
-+ if (sym->attr.flavor == FL_PROCEDURE)
-+ sym->attr.implicit_pure = 0;
-+ else
-+ sym->attr.pure = 0;
-+}
-+
-+
- /* Test whether the current procedure is elemental or not. */
-
- int
-Index: gcc/fortran/trans-io.c
-===================================================================
---- a/src/gcc/fortran/trans-io.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/trans-io.c (.../branches/gcc-4_8-branch)
-@@ -243,16 +243,16 @@
-
- /* The code to generate the error. */
- gfc_start_block (&block);
--
-+
- arg1 = gfc_build_addr_expr (NULL_TREE, var);
--
-+
- arg2 = build_int_cst (integer_type_node, error_code),
--
-+
- asprintf (&message, "%s", _(msgid));
- arg3 = gfc_build_addr_expr (pchar_type_node,
- gfc_build_localized_cstring_const (message));
- free (message);
--
-+
- tmp = build_call_expr_loc (input_location,
- gfor_fndecl_generate_error, 3, arg1, arg2, arg3);
-
-@@ -521,7 +521,7 @@
- gfc_trans_io_runtime_check (cond, var, LIBERROR_BAD_UNIT,
- "Unit number in I/O statement too small",
- &se.pre);
--
-+
- /* UNIT numbers should be less than the max. */
- val = gfc_conv_mpz_to_tree (gfc_integer_kinds[i].huge, 4);
- cond = fold_build2_loc (input_location, GT_EXPR, boolean_type_node,
-@@ -1000,7 +1000,7 @@
- if (p->convert)
- mask |= set_string (&block, &post_block, var, IOPARM_open_convert,
- p->convert);
--
-+
- if (p->newunit)
- mask |= set_parameter_ref (&block, &post_block, var, IOPARM_open_newunit,
- p->newunit);
-@@ -1234,7 +1234,7 @@
- {
- mask |= set_parameter_ref (&block, &post_block, var, IOPARM_inquire_exist,
- p->exist);
--
-+
- if (p->unit && !p->iostat)
- {
- p->iostat = create_dummy_iostat ();
-@@ -1322,7 +1322,7 @@
- if (p->pad)
- mask |= set_string (&block, &post_block, var, IOPARM_inquire_pad,
- p->pad);
--
-+
- if (p->convert)
- mask |= set_string (&block, &post_block, var, IOPARM_inquire_convert,
- p->convert);
-@@ -1547,7 +1547,7 @@
- tree dtype;
- tree dt_parm_addr;
- tree decl = NULL_TREE;
-- int n_dim;
-+ int n_dim;
- int itype;
- int rank = 0;
-
-@@ -2032,7 +2032,7 @@
- if (gfc_notification_std (GFC_STD_GNU) != SILENT)
- {
- gfc_error_now ("Derived type '%s' at %L has PRIVATE components",
-- ts->u.derived->name, code != NULL ? &(code->loc) :
-+ ts->u.derived->name, code != NULL ? &(code->loc) :
- &gfc_current_locus);
- return;
- }
-@@ -2041,7 +2041,7 @@
- ts->kind = ts->u.derived->ts.kind;
- ts->f90_type = ts->u.derived->ts.f90_type;
- }
--
-+
- kind = ts->kind;
- function = NULL;
- arg2 = NULL;
-@@ -2123,7 +2123,7 @@
- function = iocall[IOCALL_X_CHARACTER_WIDE];
- else
- function = iocall[IOCALL_X_CHARACTER_WIDE_WRITE];
--
-+
- tmp = gfc_build_addr_expr (NULL_TREE, dt_parm);
- tmp = build_call_expr_loc (input_location,
- function, 4, tmp, addr_expr, arg2, arg3);
-@@ -2158,6 +2158,12 @@
- expr = build_fold_indirect_ref_loc (input_location,
- expr);
-
-+ /* Make sure that the derived type has been built. An external
-+ function, if only referenced in an io statement requires this
-+ check (see PR58771). */
-+ if (ts->u.derived->backend_decl == NULL_TREE)
-+ tmp = gfc_typenode_for_spec (ts);
-+
- for (c = ts->u.derived->components; c; c = c->next)
- {
- field = c->backend_decl;
-Index: gcc/fortran/trans-decl.c
-===================================================================
---- a/src/gcc/fortran/trans-decl.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/trans-decl.c (.../branches/gcc-4_8-branch)
-@@ -1013,6 +1013,10 @@
- TREE_STATIC (decl) = 0;
- DECL_EXTERNAL (decl) = 0;
-
-+ /* Avoid uninitialized warnings for optional dummy arguments. */
-+ if (sym->attr.optional)
-+ TREE_NO_WARNING (decl) = 1;
-+
- /* We should never get deferred shape arrays here. We used to because of
- frontend bugs. */
- gcc_assert (sym->as->type != AS_DEFERRED);
-@@ -1358,9 +1362,10 @@
-
- if (sym->attr.flavor == FL_PROCEDURE)
- {
-- /* Catch function declarations. Only used for actual parameters,
-+ /* Catch functions. Only used for actual parameters,
- procedure pointers and procptr initialization targets. */
-- if (sym->attr.external || sym->attr.use_assoc || sym->attr.intrinsic)
-+ if (sym->attr.external || sym->attr.use_assoc || sym->attr.intrinsic
-+ || sym->attr.if_source != IFSRC_DECL)
- {
- decl = gfc_get_extern_function_decl (sym);
- gfc_set_decl_location (decl, &sym->declared_at);
-Index: gcc/fortran/match.c
-===================================================================
---- a/src/gcc/fortran/match.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/match.c (.../branches/gcc-4_8-branch)
-@@ -1753,8 +1753,7 @@
- return MATCH_ERROR;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- if (gfc_notify_std (GFC_STD_F2008, "CRITICAL statement at %C")
- == FAILURE)
-@@ -2683,8 +2682,7 @@
- goto cleanup;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- if (st == ST_STOP && gfc_find_state (COMP_CRITICAL) == SUCCESS)
- {
-@@ -2824,8 +2822,7 @@
- return MATCH_ERROR;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- if (gfc_option.coarray == GFC_FCOARRAY_NONE)
- {
-@@ -3020,8 +3017,7 @@
- return MATCH_ERROR;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- if (gfc_notify_std (GFC_STD_F2008, "SYNC statement at %C")
- == FAILURE)
-@@ -3500,15 +3496,15 @@
- if (gfc_check_do_variable (tail->expr->symtree))
- goto cleanup;
-
-- if (gfc_pure (NULL) && gfc_impure_variable (tail->expr->symtree->n.sym))
-+ bool impure = gfc_impure_variable (tail->expr->symtree->n.sym);
-+ if (impure && gfc_pure (NULL))
- {
- gfc_error ("Bad allocate-object at %C for a PURE procedure");
- goto cleanup;
- }
-
-- if (gfc_implicit_pure (NULL)
-- && gfc_impure_variable (tail->expr->symtree->n.sym))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ if (impure)
-+ gfc_unset_implicit_pure (NULL);
-
- if (tail->expr->ts.deferred)
- {
-@@ -3890,14 +3886,15 @@
-
- sym = tail->expr->symtree->n.sym;
-
-- if (gfc_pure (NULL) && gfc_impure_variable (sym))
-+ bool impure = gfc_impure_variable (sym);
-+ if (impure && gfc_pure (NULL))
- {
- gfc_error ("Illegal allocate-object at %C for a PURE procedure");
- goto cleanup;
- }
-
-- if (gfc_implicit_pure (NULL) && gfc_impure_variable (sym))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ if (impure)
-+ gfc_unset_implicit_pure (NULL);
-
- if (gfc_is_coarray (tail->expr)
- && gfc_find_state (COMP_DO_CONCURRENT) == SUCCESS)
-Index: gcc/fortran/parse.c
-===================================================================
---- a/src/gcc/fortran/parse.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/parse.c (.../branches/gcc-4_8-branch)
-@@ -550,8 +550,7 @@
- return ST_NONE;
- }
-
-- if (gfc_implicit_pure (NULL))
-- gfc_current_ns->proc_name->attr.implicit_pure = 0;
-+ gfc_unset_implicit_pure (NULL);
-
- old_locus = gfc_current_locus;
-
-Index: gcc/fortran/check.c
-===================================================================
---- a/src/gcc/fortran/check.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/check.c (.../branches/gcc-4_8-branch)
-@@ -3208,7 +3208,7 @@
- "than %d elements", &shape->where, GFC_MAX_DIMENSIONS);
- return FAILURE;
- }
-- else if (shape->expr_type == EXPR_ARRAY)
-+ else if (shape->expr_type == EXPR_ARRAY && gfc_is_constant_expr (shape))
- {
- gfc_expr *e;
- int i, extent;
-Index: gcc/fortran/primary.c
-===================================================================
---- a/src/gcc/fortran/primary.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/primary.c (.../branches/gcc-4_8-branch)
-@@ -2252,7 +2252,7 @@
- case EXPR_FUNCTION:
- gfc_clear_attr (&attr);
-
-- if (e->value.function.esym != NULL)
-+ if (e->value.function.esym && e->value.function.esym->result)
- {
- gfc_symbol *sym = e->value.function.esym->result;
- attr = sym->attr;
-@@ -2540,7 +2540,8 @@
- if (parent && !comp)
- break;
-
-- actual = actual->next;
-+ if (actual)
-+ actual = actual->next;
- }
-
- if (build_actual_constructor (&comp_head, &ctor_head, sym) == FAILURE)
-Index: gcc/fortran/trans-intrinsic.c
-===================================================================
---- a/src/gcc/fortran/trans-intrinsic.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/trans-intrinsic.c (.../branches/gcc-4_8-branch)
-@@ -4684,9 +4684,11 @@
- static void
- gfc_conv_intrinsic_ichar (gfc_se * se, gfc_expr * expr)
- {
-- tree args[2], type, pchartype;
-+ tree args[3], type, pchartype;
-+ int nargs;
-
-- gfc_conv_intrinsic_function_args (se, expr, args, 2);
-+ nargs = gfc_intrinsic_argument_list_length (expr);
-+ gfc_conv_intrinsic_function_args (se, expr, args, nargs);
- gcc_assert (POINTER_TYPE_P (TREE_TYPE (args[1])));
- pchartype = gfc_get_pchar_type (expr->value.function.actual->expr->ts.kind);
- args[1] = fold_build1_loc (input_location, NOP_EXPR, pchartype, args[1]);
-Index: gcc/fortran/simplify.c
-===================================================================
---- a/src/gcc/fortran/simplify.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/fortran/simplify.c (.../branches/gcc-4_8-branch)
-@@ -5528,7 +5528,7 @@
- if (e == &gfc_bad_expr || range_check (e, "SHAPE") == &gfc_bad_expr)
- {
- gfc_free_expr (result);
-- if (t)
-+ if (t == SUCCESS)
- gfc_clear_shape (shape, source->rank);
- return &gfc_bad_expr;
- }
-@@ -5536,7 +5536,7 @@
- gfc_constructor_append_expr (&result->value.constructor, e, NULL);
- }
-
-- if (t)
-+ if (t == SUCCESS)
- gfc_clear_shape (shape, source->rank);
-
- return result;
-Index: gcc/configure.ac
-===================================================================
---- a/src/gcc/configure.ac (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/configure.ac (.../branches/gcc-4_8-branch)
-@@ -1516,13 +1516,16 @@
- /* | [A-Za-z]:[\\/]* ) realsrcdir=${srcdir};;
- *) realsrcdir=../${srcdir};;
- esac
-- saved_CFLAGS="${CFLAGS}"
-+ # Clearing GMPINC is necessary to prevent host headers being
-+ # used by the build compiler. Defining GENERATOR_FILE stops
-+ # system.h from including gmp.h.
- CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
-- LDFLAGS="${LDFLAGS_FOR_BUILD}" \
-+ CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \
-+ LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \
-+ GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \
- ${realsrcdir}/configure \
- --enable-languages=${enable_languages-all} \
- --target=$target_alias --host=$build_alias --build=$build_alias
-- CFLAGS="${saved_CFLAGS}"
-
- # We just finished tests for the build machine, so rename
- # the file auto-build.h in the gcc directory.
-@@ -1887,6 +1890,7 @@
- if test x$build != x$host || test "x$coverage_flags" != x
- then
- BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'
-+ BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)'
- BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'
- fi
-
-@@ -3611,6 +3615,19 @@
- kasumi_fi_xor %f46, %f48, %f50, %f52],,
- [AC_DEFINE(HAVE_AS_SPARC4, 1,
- [Define if your assembler supports SPARC4 instructions.])])
-+
-+ gcc_GAS_CHECK_FEATURE([LEON instructions],
-+ gcc_cv_as_sparc_leon,,
-+ [-Aleon],
-+ [.text
-+ .register %g2, #scratch
-+ .register %g3, #scratch
-+ .align 4
-+ smac %g2, %g3, %g1
-+ umac %g2, %g3, %g1
-+ casa [[%g2]] 0xb, %g3, %g1],,
-+ [AC_DEFINE(HAVE_AS_LEON, 1,
-+ [Define if your assembler supports LEON instructions.])])
- ;;
-
- changequote(,)dnl
-@@ -3749,8 +3766,13 @@
-
- # These two are used unconditionally by i386.[ch]; it is to be defined
- # to 1 if the feature is present, 0 otherwise.
-+ as_ix86_gotoff_in_data_opt=
-+ if test x$gas = xyes; then
-+ as_ix86_gotoff_in_data_opt="--32"
-+ fi
- gcc_GAS_CHECK_FEATURE([GOTOFF in data],
-- gcc_cv_as_ix86_gotoff_in_data, [2,11,0],,
-+ gcc_cv_as_ix86_gotoff_in_data, [2,11,0],
-+ [$as_ix86_gotoff_in_data_opt],
- [ .text
- .L0:
- nop
-@@ -3772,6 +3794,12 @@
- [AC_DEFINE(HAVE_AS_IX86_REP_LOCK_PREFIX, 1,
- [Define if the assembler supports 'rep <insn>, lock <insn>'.])])
-
-+ gcc_GAS_CHECK_FEATURE([ud2 mnemonic],
-+ gcc_cv_as_ix86_ud2,,,
-+ [ud2],,
-+ [AC_DEFINE(HAVE_AS_IX86_UD2, 1,
-+ [Define if your assembler supports the 'ud2' mnemonic.])])
-+
- gcc_GAS_CHECK_FEATURE([R_386_TLS_GD_PLT reloc],
- gcc_cv_as_ix86_tlsgdplt,,,
- [call tls_gd@tlsgdplt],
-@@ -5193,15 +5221,15 @@
- AC_MSG_CHECKING([for exported symbols])
- if test "x$export_sym_check" != x; then
- echo "int main() {return 0;} int foobar() {return 0;}" > conftest.c
-- ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest > /dev/null 2>&1
-- if $export_sym_check conftest | grep foobar > /dev/null; then
-+ ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest$ac_exeext > /dev/null 2>&1
-+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then
- : # No need to use a flag
- AC_MSG_RESULT([yes])
- else
- AC_MSG_RESULT([yes])
- AC_MSG_CHECKING([for -rdynamic])
-- ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest > /dev/null 2>&1
-- if $export_sym_check conftest | grep foobar > /dev/null; then
-+ ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest$ac_exeext > /dev/null 2>&1
-+ if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then
- plugin_rdynamic=yes
- pluginlibs="-rdynamic"
- else
-Index: gcc/function.c
-===================================================================
---- a/src/gcc/function.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/function.c (.../branches/gcc-4_8-branch)
-@@ -2507,6 +2507,7 @@
- }
-
- locate_and_pad_parm (data->promoted_mode, data->passed_type, in_regs,
-+ all->reg_parm_stack_space,
- entry_parm ? data->partial : 0, current_function_decl,
- &all->stack_args_size, &data->locate);
-
-@@ -3485,11 +3486,7 @@
- /* Adjust function incoming argument size for alignment and
- minimum length. */
-
--#ifdef REG_PARM_STACK_SPACE
-- crtl->args.size = MAX (crtl->args.size,
-- REG_PARM_STACK_SPACE (fndecl));
--#endif
--
-+ crtl->args.size = MAX (crtl->args.size, all.reg_parm_stack_space);
- crtl->args.size = CEIL_ROUND (crtl->args.size,
- PARM_BOUNDARY / BITS_PER_UNIT);
-
-@@ -3693,6 +3690,9 @@
- IN_REGS is nonzero if the argument will be passed in registers. It will
- never be set if REG_PARM_STACK_SPACE is not defined.
-
-+ REG_PARM_STACK_SPACE is the number of bytes of stack space reserved
-+ for arguments which are passed in registers.
-+
- FNDECL is the function in which the argument was defined.
-
- There are two types of rounding that are done. The first, controlled by
-@@ -3713,7 +3713,8 @@
-
- void
- locate_and_pad_parm (enum machine_mode passed_mode, tree type, int in_regs,
-- int partial, tree fndecl ATTRIBUTE_UNUSED,
-+ int reg_parm_stack_space, int partial,
-+ tree fndecl ATTRIBUTE_UNUSED,
- struct args_size *initial_offset_ptr,
- struct locate_and_pad_arg_data *locate)
- {
-@@ -3720,12 +3721,8 @@
- tree sizetree;
- enum direction where_pad;
- unsigned int boundary, round_boundary;
-- int reg_parm_stack_space = 0;
- int part_size_in_regs;
-
--#ifdef REG_PARM_STACK_SPACE
-- reg_parm_stack_space = REG_PARM_STACK_SPACE (fndecl);
--
- /* If we have found a stack parm before we reach the end of the
- area reserved for registers, skip that area. */
- if (! in_regs)
-@@ -3743,7 +3740,6 @@
- initial_offset_ptr->constant = reg_parm_stack_space;
- }
- }
--#endif /* REG_PARM_STACK_SPACE */
-
- part_size_in_regs = (reg_parm_stack_space == 0 ? partial : 0);
-
-@@ -3806,11 +3802,7 @@
-
- locate->slot_offset.constant += part_size_in_regs;
-
-- if (!in_regs
--#ifdef REG_PARM_STACK_SPACE
-- || REG_PARM_STACK_SPACE (fndecl) > 0
--#endif
-- )
-+ if (!in_regs || reg_parm_stack_space > 0)
- pad_to_arg_alignment (&locate->slot_offset, boundary,
- &locate->alignment_pad);
-
-@@ -3830,11 +3822,7 @@
- pad_below (&locate->offset, passed_mode, sizetree);
-
- #else /* !ARGS_GROW_DOWNWARD */
-- if (!in_regs
--#ifdef REG_PARM_STACK_SPACE
-- || REG_PARM_STACK_SPACE (fndecl) > 0
--#endif
-- )
-+ if (!in_regs || reg_parm_stack_space > 0)
- pad_to_arg_alignment (initial_offset_ptr, boundary,
- &locate->alignment_pad);
- locate->slot_offset = *initial_offset_ptr;
-@@ -5093,6 +5081,7 @@
- amount. BLKmode results are handled using the group load/store
- machinery. */
- if (TYPE_MODE (TREE_TYPE (decl_result)) != BLKmode
-+ && REG_P (real_decl_rtl)
- && targetm.calls.return_in_msb (TREE_TYPE (decl_result)))
- {
- emit_move_insn (gen_rtx_REG (GET_MODE (decl_rtl),
-@@ -5509,22 +5498,45 @@
- except for any part that overlaps SRC (next loop). */
- bb_uses = &DF_LR_BB_INFO (bb)->use;
- bb_defs = &DF_LR_BB_INFO (bb)->def;
-- for (i = dregno; i < end_dregno; i++)
-+ if (df_live)
- {
-- if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i))
-- next_block = NULL;
-- CLEAR_REGNO_REG_SET (live_out, i);
-- CLEAR_REGNO_REG_SET (live_in, i);
-+ for (i = dregno; i < end_dregno; i++)
-+ {
-+ if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i)
-+ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i))
-+ next_block = NULL;
-+ CLEAR_REGNO_REG_SET (live_out, i);
-+ CLEAR_REGNO_REG_SET (live_in, i);
-+ }
-+
-+ /* Check whether BB clobbers SRC. We need to add INSN to BB if so.
-+ Either way, SRC is now live on entry. */
-+ for (i = sregno; i < end_sregno; i++)
-+ {
-+ if (REGNO_REG_SET_P (bb_defs, i)
-+ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i))
-+ next_block = NULL;
-+ SET_REGNO_REG_SET (live_out, i);
-+ SET_REGNO_REG_SET (live_in, i);
-+ }
- }
-+ else
-+ {
-+ /* DF_LR_BB_INFO (bb)->def does not comprise the DF_REF_PARTIAL and
-+ DF_REF_CONDITIONAL defs. So if DF_LIVE doesn't exist, i.e.
-+ at -O1, just give up searching NEXT_BLOCK. */
-+ next_block = NULL;
-+ for (i = dregno; i < end_dregno; i++)
-+ {
-+ CLEAR_REGNO_REG_SET (live_out, i);
-+ CLEAR_REGNO_REG_SET (live_in, i);
-+ }
-
-- /* Check whether BB clobbers SRC. We need to add INSN to BB if so.
-- Either way, SRC is now live on entry. */
-- for (i = sregno; i < end_sregno; i++)
-- {
-- if (REGNO_REG_SET_P (bb_defs, i))
-- next_block = NULL;
-- SET_REGNO_REG_SET (live_out, i);
-- SET_REGNO_REG_SET (live_in, i);
-+ for (i = sregno; i < end_sregno; i++)
-+ {
-+ SET_REGNO_REG_SET (live_out, i);
-+ SET_REGNO_REG_SET (live_in, i);
-+ }
- }
-
- /* If we don't need to add the move to BB, look for a single
-Index: gcc/print-rtl.c
-===================================================================
---- a/src/gcc/print-rtl.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/print-rtl.c (.../branches/gcc-4_8-branch)
-@@ -582,6 +582,8 @@
-
- if (MEM_EXPR (in_rtx))
- print_mem_expr (outfile, MEM_EXPR (in_rtx));
-+ else
-+ fputc (' ', outfile);
-
- if (MEM_OFFSET_KNOWN_P (in_rtx))
- fprintf (outfile, "+" HOST_WIDE_INT_PRINT_DEC, MEM_OFFSET (in_rtx));
-Index: gcc/tree-vectorizer.h
-===================================================================
---- a/src/gcc/tree-vectorizer.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-vectorizer.h (.../branches/gcc-4_8-branch)
-@@ -542,6 +542,10 @@
- is 1. */
- unsigned int gap;
-
-+ /* The minimum negative dependence distance this stmt participates in
-+ or zero if none. */
-+ unsigned int min_neg_dist;
-+
- /* Not all stmts in the loop need to be vectorized. e.g, the increment
- of the loop induction variable and computation of array indexes. relevant
- indicates whether the stmt needs to be vectorized. */
-@@ -593,6 +597,7 @@
- #define STMT_VINFO_GROUP_READ_WRITE_DEPENDENCE(S) (S)->read_write_dep
- #define STMT_VINFO_GROUPED_ACCESS(S) ((S)->first_element != NULL && (S)->data_ref_info)
- #define STMT_VINFO_LOOP_PHI_EVOLUTION_PART(S) (S)->loop_phi_evolution_part
-+#define STMT_VINFO_MIN_NEG_DIST(S) (S)->min_neg_dist
-
- #define GROUP_FIRST_ELEMENT(S) (S)->first_element
- #define GROUP_NEXT_ELEMENT(S) (S)->next_element
-Index: gcc/sdbout.c
-===================================================================
---- a/src/gcc/sdbout.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/sdbout.c (.../branches/gcc-4_8-branch)
-@@ -1226,7 +1226,10 @@
- sdbout_parms (tree parms)
- {
- for (; parms; parms = TREE_CHAIN (parms))
-- if (DECL_NAME (parms))
-+ if (DECL_NAME (parms)
-+ && TREE_TYPE (parms) != error_mark_node
-+ && DECL_RTL_SET_P (parms)
-+ && DECL_INCOMING_RTL (parms))
- {
- int current_sym_value = 0;
- const char *name = IDENTIFIER_POINTER (DECL_NAME (parms));
-@@ -1358,7 +1361,10 @@
- sdbout_reg_parms (tree parms)
- {
- for (; parms; parms = TREE_CHAIN (parms))
-- if (DECL_NAME (parms))
-+ if (DECL_NAME (parms)
-+ && TREE_TYPE (parms) != error_mark_node
-+ && DECL_RTL_SET_P (parms)
-+ && DECL_INCOMING_RTL (parms))
- {
- const char *name = IDENTIFIER_POINTER (DECL_NAME (parms));
-
-Index: gcc/ipa-split.c
-===================================================================
---- a/src/gcc/ipa-split.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ipa-split.c (.../branches/gcc-4_8-branch)
-@@ -136,7 +136,7 @@
- variable, check it if it is present in bitmap passed via DATA. */
-
- static bool
--test_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data)
-+test_nonssa_use (gimple, tree t, tree, void *data)
- {
- t = get_base_address (t);
-
-@@ -229,7 +229,7 @@
- }
- if (gimple_code (stmt) == GIMPLE_LABEL
- && test_nonssa_use (stmt, gimple_label_label (stmt),
-- non_ssa_vars))
-+ NULL_TREE, non_ssa_vars))
- {
- ok = false;
- goto done;
-@@ -258,7 +258,7 @@
- if (virtual_operand_p (gimple_phi_result (stmt)))
- continue;
- if (TREE_CODE (op) != SSA_NAME
-- && test_nonssa_use (stmt, op, non_ssa_vars))
-+ && test_nonssa_use (stmt, op, op, non_ssa_vars))
- {
- ok = false;
- goto done;
-@@ -670,7 +670,7 @@
- Return true when access to T prevents splitting the function. */
-
- static bool
--mark_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data)
-+mark_nonssa_use (gimple, tree t, tree, void *data)
- {
- t = get_base_address (t);
-
-@@ -830,7 +830,7 @@
- if (TREE_CODE (op) == SSA_NAME)
- bitmap_set_bit (used_ssa_names, SSA_NAME_VERSION (op));
- else
-- can_split &= !mark_nonssa_use (stmt, op, non_ssa_vars);
-+ can_split &= !mark_nonssa_use (stmt, op, op, non_ssa_vars);
- }
- }
- return can_split;
-Index: gcc/alias.c
-===================================================================
---- a/src/gcc/alias.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/alias.c (.../branches/gcc-4_8-branch)
-@@ -156,7 +156,9 @@
- static alias_set_entry get_alias_set_entry (alias_set_type);
- static bool nonoverlapping_component_refs_p (const_rtx, const_rtx);
- static tree decl_for_component_ref (tree);
--static int write_dependence_p (const_rtx, const_rtx, int);
-+static int write_dependence_p (const_rtx,
-+ const_rtx, enum machine_mode, rtx,
-+ bool, bool, bool);
-
- static void memory_modified_1 (rtx, const_rtx, void *);
-
-@@ -2558,15 +2560,24 @@
- }
-
- /* Returns nonzero if a write to X might alias a previous read from
-- (or, if WRITEP is nonzero, a write to) MEM. */
-+ (or, if WRITEP is true, a write to) MEM.
-+ If X_CANONCALIZED is true, then X_ADDR is the canonicalized address of X,
-+ and X_MODE the mode for that access.
-+ If MEM_CANONICALIZED is true, MEM is canonicalized. */
-
- static int
--write_dependence_p (const_rtx mem, const_rtx x, int writep)
-+write_dependence_p (const_rtx mem,
-+ const_rtx x, enum machine_mode x_mode, rtx x_addr,
-+ bool mem_canonicalized, bool x_canonicalized, bool writep)
- {
-- rtx x_addr, mem_addr;
-+ rtx mem_addr;
- rtx base;
- int ret;
-
-+ gcc_checking_assert (x_canonicalized
-+ ? (x_addr != NULL_RTX && x_mode != VOIDmode)
-+ : (x_addr == NULL_RTX && x_mode == VOIDmode));
-+
- if (MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
- return 1;
-
-@@ -2590,17 +2601,21 @@
- if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))
- return 1;
-
-- x_addr = XEXP (x, 0);
- mem_addr = XEXP (mem, 0);
-- if (!((GET_CODE (x_addr) == VALUE
-- && GET_CODE (mem_addr) != VALUE
-- && reg_mentioned_p (x_addr, mem_addr))
-- || (GET_CODE (x_addr) != VALUE
-- && GET_CODE (mem_addr) == VALUE
-- && reg_mentioned_p (mem_addr, x_addr))))
-+ if (!x_addr)
- {
-- x_addr = get_addr (x_addr);
-- mem_addr = get_addr (mem_addr);
-+ x_addr = XEXP (x, 0);
-+ if (!((GET_CODE (x_addr) == VALUE
-+ && GET_CODE (mem_addr) != VALUE
-+ && reg_mentioned_p (x_addr, mem_addr))
-+ || (GET_CODE (x_addr) != VALUE
-+ && GET_CODE (mem_addr) == VALUE
-+ && reg_mentioned_p (mem_addr, x_addr))))
-+ {
-+ x_addr = get_addr (x_addr);
-+ if (!mem_canonicalized)
-+ mem_addr = get_addr (mem_addr);
-+ }
- }
-
- if (! writep)
-@@ -2616,11 +2631,16 @@
- GET_MODE (mem)))
- return 0;
-
-- x_addr = canon_rtx (x_addr);
-- mem_addr = canon_rtx (mem_addr);
-+ if (!x_canonicalized)
-+ {
-+ x_addr = canon_rtx (x_addr);
-+ x_mode = GET_MODE (x);
-+ }
-+ if (!mem_canonicalized)
-+ mem_addr = canon_rtx (mem_addr);
-
- if ((ret = memrefs_conflict_p (SIZE_FOR_MODE (mem), mem_addr,
-- SIZE_FOR_MODE (x), x_addr, 0)) != -1)
-+ GET_MODE_SIZE (x_mode), x_addr, 0)) != -1)
- return ret;
-
- if (nonoverlapping_memrefs_p (x, mem, false))
-@@ -2634,15 +2654,33 @@
- int
- anti_dependence (const_rtx mem, const_rtx x)
- {
-- return write_dependence_p (mem, x, /*writep=*/0);
-+ return write_dependence_p (mem, x, VOIDmode, NULL_RTX,
-+ /*mem_canonicalized=*/false,
-+ /*x_canonicalized*/false, /*writep=*/false);
- }
-
-+/* Likewise, but we already have a canonicalized MEM, and X_ADDR for X.
-+ Also, consider X in X_MODE (which might be from an enclosing
-+ STRICT_LOW_PART / ZERO_EXTRACT).
-+ If MEM_CANONICALIZED is true, MEM is canonicalized. */
-+
-+int
-+canon_anti_dependence (const_rtx mem, bool mem_canonicalized,
-+ const_rtx x, enum machine_mode x_mode, rtx x_addr)
-+{
-+ return write_dependence_p (mem, x, x_mode, x_addr,
-+ mem_canonicalized, /*x_canonicalized=*/true,
-+ /*writep=*/false);
-+}
-+
- /* Output dependence: X is written after store in MEM takes place. */
-
- int
- output_dependence (const_rtx mem, const_rtx x)
- {
-- return write_dependence_p (mem, x, /*writep=*/1);
-+ return write_dependence_p (mem, x, VOIDmode, NULL_RTX,
-+ /*mem_canonicalized=*/false,
-+ /*x_canonicalized*/false, /*writep=*/true);
- }
-
-
-@@ -2871,17 +2909,14 @@
- /* Wipe the reg_seen array clean. */
- bitmap_clear (reg_seen);
-
-- /* Mark all hard registers which may contain an address.
-- The stack, frame and argument pointers may contain an address.
-- An argument register which can hold a Pmode value may contain
-- an address even if it is not in BASE_REGS.
-+ /* Initialize the alias information for this pass. */
-+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-+ if (static_reg_base_value[i])
-+ {
-+ new_reg_base_value[i] = static_reg_base_value[i];
-+ bitmap_set_bit (reg_seen, i);
-+ }
-
-- The address expression is VOIDmode for an argument and
-- Pmode for other registers. */
--
-- memcpy (new_reg_base_value, static_reg_base_value,
-- FIRST_PSEUDO_REGISTER * sizeof (rtx));
--
- /* Walk the insns adding values to the new_reg_base_value array. */
- for (i = 0; i < rpo_cnt; i++)
- {
-Index: gcc/tree-vect-loop.c
-===================================================================
---- a/src/gcc/tree-vect-loop.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-vect-loop.c (.../branches/gcc-4_8-branch)
-@@ -1537,7 +1537,7 @@
-
- if (!LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)
- || LOOP_VINFO_INT_NITERS (loop_vinfo) % vectorization_factor != 0
-- || LOOP_PEELING_FOR_ALIGNMENT (loop_vinfo))
-+ || LOOP_VINFO_PEELING_FOR_GAPS (loop_vinfo))
- {
- if (dump_enabled_p ())
- dump_printf_loc (MSG_NOTE, vect_location, "epilog loop required.");
-@@ -2097,6 +2097,12 @@
- || (!check_reduction && flow_loop_nested_p (vect_loop, loop)));
-
- name = PHI_RESULT (phi);
-+ /* ??? If there are no uses of the PHI result the inner loop reduction
-+ won't be detected as possibly double-reduction by vectorizable_reduction
-+ because that tries to walk the PHI arg from the preheader edge which
-+ can be constant. See PR60382. */
-+ if (has_zero_uses (name))
-+ return NULL;
- nloop_uses = 0;
- FOR_EACH_IMM_USE_FAST (use_p, imm_iter, name)
- {
-@@ -3115,7 +3121,6 @@
- stmt_vec_info stmt_vinfo = vinfo_for_stmt (iv_phi);
- loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
- struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo);
-- tree scalar_type;
- tree vectype;
- int nunits;
- edge pe = loop_preheader_edge (loop);
-@@ -3122,7 +3127,6 @@
- struct loop *iv_loop;
- basic_block new_bb;
- tree new_vec, vec_init, vec_step, t;
-- tree access_fn;
- tree new_var;
- tree new_name;
- gimple init_stmt, induction_phi, new_stmt;
-@@ -3130,7 +3134,6 @@
- tree init_expr, step_expr;
- int vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo);
- int i;
-- bool ok;
- int ncopies;
- tree expr;
- stmt_vec_info phi_info = vinfo_for_stmt (iv_phi);
-@@ -3159,16 +3162,14 @@
- latch_e = loop_latch_edge (iv_loop);
- loop_arg = PHI_ARG_DEF_FROM_EDGE (iv_phi, latch_e);
-
-- access_fn = analyze_scalar_evolution (iv_loop, PHI_RESULT (iv_phi));
-- gcc_assert (access_fn);
-- STRIP_NOPS (access_fn);
-- ok = vect_is_simple_iv_evolution (iv_loop->num, access_fn,
-- &init_expr, &step_expr);
-- gcc_assert (ok);
-+ step_expr = STMT_VINFO_LOOP_PHI_EVOLUTION_PART (phi_info);
-+ gcc_assert (step_expr != NULL_TREE);
-+
- pe = loop_preheader_edge (iv_loop);
-+ init_expr = PHI_ARG_DEF_FROM_EDGE (iv_phi,
-+ loop_preheader_edge (iv_loop));
-
-- scalar_type = TREE_TYPE (init_expr);
-- vectype = get_vectype_for_scalar_type (scalar_type);
-+ vectype = get_vectype_for_scalar_type (TREE_TYPE (init_expr));
- resvectype = get_vectype_for_scalar_type (TREE_TYPE (PHI_RESULT (iv_phi)));
- gcc_assert (vectype);
- nunits = TYPE_VECTOR_SUBPARTS (vectype);
-@@ -3177,6 +3178,16 @@
- gcc_assert (phi_info);
- gcc_assert (ncopies >= 1);
-
-+ /* Convert the step to the desired type. */
-+ step_expr = force_gimple_operand (fold_convert (TREE_TYPE (vectype),
-+ step_expr),
-+ &stmts, true, NULL_TREE);
-+ if (stmts)
-+ {
-+ new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts);
-+ gcc_assert (!new_bb);
-+ }
-+
- /* Find the first insertion point in the BB. */
- si = gsi_after_labels (bb);
-
-@@ -3186,9 +3197,7 @@
- /* iv_loop is nested in the loop to be vectorized. init_expr had already
- been created during vectorization of previous stmts. We obtain it
- from the STMT_VINFO_VEC_STMT of the defining stmt. */
-- tree iv_def = PHI_ARG_DEF_FROM_EDGE (iv_phi,
-- loop_preheader_edge (iv_loop));
-- vec_init = vect_get_vec_def_for_operand (iv_def, iv_phi, NULL);
-+ vec_init = vect_get_vec_def_for_operand (init_expr, iv_phi, NULL);
- /* If the initial value is not of proper type, convert it. */
- if (!useless_type_conversion_p (vectype, TREE_TYPE (vec_init)))
- {
-@@ -3211,8 +3220,11 @@
-
- /* iv_loop is the loop to be vectorized. Create:
- vec_init = [X, X+S, X+2*S, X+3*S] (S = step_expr, X = init_expr) */
-- new_var = vect_get_new_vect_var (scalar_type, vect_scalar_var, "var_");
-- new_name = force_gimple_operand (init_expr, &stmts, false, new_var);
-+ new_var = vect_get_new_vect_var (TREE_TYPE (vectype),
-+ vect_scalar_var, "var_");
-+ new_name = force_gimple_operand (fold_convert (TREE_TYPE (vectype),
-+ init_expr),
-+ &stmts, false, new_var);
- if (stmts)
- {
- new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts);
-@@ -3224,9 +3236,7 @@
- for (i = 1; i < nunits; i++)
- {
- /* Create: new_name_i = new_name + step_expr */
-- enum tree_code code = POINTER_TYPE_P (scalar_type)
-- ? POINTER_PLUS_EXPR : PLUS_EXPR;
-- init_stmt = gimple_build_assign_with_ops (code, new_var,
-+ init_stmt = gimple_build_assign_with_ops (PLUS_EXPR, new_var,
- new_name, step_expr);
- new_name = make_ssa_name (new_var, init_stmt);
- gimple_assign_set_lhs (init_stmt, new_name);
-@@ -3781,8 +3791,12 @@
- /* Set phi nodes arguments. */
- FOR_EACH_VEC_ELT (reduction_phis, i, phi)
- {
-- tree vec_init_def = vec_initial_defs[i];
-- tree def = vect_defs[i];
-+ tree vec_init_def, def;
-+ gimple_seq stmts;
-+ vec_init_def = force_gimple_operand (vec_initial_defs[i], &stmts,
-+ true, NULL_TREE);
-+ gsi_insert_seq_on_edge_immediate (loop_preheader_edge (loop), stmts);
-+ def = vect_defs[i];
- for (j = 0; j < ncopies; j++)
- {
- /* Set the loop-entry arg of the reduction-phi. */
-@@ -5564,8 +5578,9 @@
- && !STMT_VINFO_LIVE_P (stmt_info))
- continue;
-
-- if ((TYPE_VECTOR_SUBPARTS (STMT_VINFO_VECTYPE (stmt_info))
-- != (unsigned HOST_WIDE_INT) vectorization_factor)
-+ if (STMT_VINFO_VECTYPE (stmt_info)
-+ && (TYPE_VECTOR_SUBPARTS (STMT_VINFO_VECTYPE (stmt_info))
-+ != (unsigned HOST_WIDE_INT) vectorization_factor)
- && dump_enabled_p ())
- dump_printf_loc (MSG_NOTE, vect_location, "multiple-types.");
-
-Index: gcc/ipa.c
-===================================================================
---- a/src/gcc/ipa.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ipa.c (.../branches/gcc-4_8-branch)
-@@ -359,6 +359,8 @@
- {
- if (file)
- fprintf (file, " %s", cgraph_node_name (node));
-+ node->alias = false;
-+ node->thunk.thunk_p = false;
- cgraph_node_remove_callees (node);
- ipa_remove_all_references (&node->symbol.ref_list);
- changed = true;
-Index: gcc/lra-coalesce.c
-===================================================================
---- a/src/gcc/lra-coalesce.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/lra-coalesce.c (.../branches/gcc-4_8-branch)
-@@ -221,9 +221,12 @@
- basic_block bb;
- rtx mv, set, insn, next, *sorted_moves;
- int i, mv_num, sregno, dregno;
-+ unsigned int regno;
- int coalesced_moves;
- int max_regno = max_reg_num ();
- bitmap_head involved_insns_bitmap;
-+ bitmap_head result_pseudo_vals_bitmap;
-+ bitmap_iterator bi;
-
- timevar_push (TV_LRA_COALESCE);
-
-@@ -318,6 +321,34 @@
- }
- }
- }
-+ /* If we have situation after inheritance pass:
-+
-+ r1 <- ... insn originally setting p1
-+ i1 <- r1 setting inheritance i1 from reload r1
-+ ...
-+ ... <- ... p2 ... dead p2
-+ ..
-+ p1 <- i1
-+ r2 <- i1
-+ ...<- ... r2 ...
-+
-+ And we are coalescing p1 and p2 using p1. In this case i1 and p1
-+ should have different values, otherwise they can get the same
-+ hard reg and this is wrong for insn using p2 before coalescing.
-+ So invalidate such inheritance pseudo values. */
-+ bitmap_initialize (&result_pseudo_vals_bitmap, &reg_obstack);
-+ EXECUTE_IF_SET_IN_BITMAP (&coalesced_pseudos_bitmap, 0, regno, bi)
-+ bitmap_set_bit (&result_pseudo_vals_bitmap,
-+ lra_reg_info[first_coalesced_pseudo[regno]].val);
-+ EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
-+ if (bitmap_bit_p (&result_pseudo_vals_bitmap, lra_reg_info[regno].val))
-+ {
-+ lra_set_regno_unique_value (regno);
-+ if (lra_dump_file != NULL)
-+ fprintf (lra_dump_file,
-+ " Make unique value for inheritance r%d\n", regno);
-+ }
-+ bitmap_clear (&result_pseudo_vals_bitmap);
- bitmap_clear (&used_pseudos_bitmap);
- bitmap_clear (&involved_insns_bitmap);
- bitmap_clear (&coalesced_pseudos_bitmap);
-Index: gcc/tree-vect-data-refs.c
-===================================================================
---- a/src/gcc/tree-vect-data-refs.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-vect-data-refs.c (.../branches/gcc-4_8-branch)
-@@ -739,6 +739,13 @@
- if (dump_enabled_p ())
- dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
- "dependence distance negative.");
-+ /* Record a negative dependence distance to later limit the
-+ amount of stmt copying / unrolling we can perform.
-+ Only need to handle read-after-write dependence. */
-+ if (DR_IS_READ (drb)
-+ && (STMT_VINFO_MIN_NEG_DIST (stmtinfo_b) == 0
-+ || STMT_VINFO_MIN_NEG_DIST (stmtinfo_b) > (unsigned)dist))
-+ STMT_VINFO_MIN_NEG_DIST (stmtinfo_b) = dist;
- continue;
- }
-
-Index: gcc/gimplify.c
-===================================================================
---- a/src/gcc/gimplify.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/gimplify.c (.../branches/gcc-4_8-branch)
-@@ -2060,6 +2060,9 @@
- /* Nonlocal VLAs seen in the current function. */
- static struct pointer_set_t *nonlocal_vlas;
-
-+/* The VAR_DECLs created for nonlocal VLAs for debug info purposes. */
-+static tree nonlocal_vla_vars;
-+
- /* Gimplify a VAR_DECL or PARM_DECL. Return GS_OK if we expanded a
- DECL_VALUE_EXPR, and it's worth re-examining things. */
-
-@@ -2106,14 +2109,13 @@
- ctx = ctx->outer_context;
- if (!ctx && !pointer_set_insert (nonlocal_vlas, decl))
- {
-- tree copy = copy_node (decl), block;
-+ tree copy = copy_node (decl);
-
- lang_hooks.dup_lang_specific_decl (copy);
- SET_DECL_RTL (copy, 0);
- TREE_USED (copy) = 1;
-- block = DECL_INITIAL (current_function_decl);
-- DECL_CHAIN (copy) = BLOCK_VARS (block);
-- BLOCK_VARS (block) = copy;
-+ DECL_CHAIN (copy) = nonlocal_vla_vars;
-+ nonlocal_vla_vars = copy;
- SET_DECL_VALUE_EXPR (copy, unshare_expr (value_expr));
- DECL_HAS_VALUE_EXPR_P (copy) = 1;
- }
-@@ -4369,7 +4371,7 @@
- unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT;
- tree index = bitsize_int (indexi);
- if (offset / part_widthi
-- <= TYPE_VECTOR_SUBPARTS (TREE_TYPE (addrtype)))
-+ < TYPE_VECTOR_SUBPARTS (TREE_TYPE (addrtype)))
- return fold_build3 (BIT_FIELD_REF, type, TREE_OPERAND (addr, 0),
- part_width, index);
- }
-@@ -6131,7 +6133,7 @@
- region's REDUCTION clause. */
-
- static bool
--omp_check_private (struct gimplify_omp_ctx *ctx, tree decl)
-+omp_check_private (struct gimplify_omp_ctx *ctx, tree decl, bool copyprivate)
- {
- splay_tree_node n;
-
-@@ -6140,8 +6142,11 @@
- ctx = ctx->outer_context;
- if (ctx == NULL)
- return !(is_global_var (decl)
-- /* References might be private, but might be shared too. */
-- || lang_hooks.decls.omp_privatize_by_reference (decl));
-+ /* References might be private, but might be shared too,
-+ when checking for copyprivate, assume they might be
-+ private, otherwise assume they might be shared. */
-+ || (!copyprivate
-+ && lang_hooks.decls.omp_privatize_by_reference (decl)));
-
- n = splay_tree_lookup (ctx->variables, (splay_tree_key) decl);
- if (n != NULL)
-@@ -6267,12 +6272,36 @@
- remove = true;
- break;
- }
-+ if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_COPYPRIVATE
-+ && !remove
-+ && !omp_check_private (ctx, decl, true))
-+ {
-+ remove = true;
-+ if (is_global_var (decl))
-+ {
-+ if (DECL_THREAD_LOCAL_P (decl))
-+ remove = false;
-+ else if (DECL_HAS_VALUE_EXPR_P (decl))
-+ {
-+ tree value = get_base_address (DECL_VALUE_EXPR (decl));
-+
-+ if (value
-+ && DECL_P (value)
-+ && DECL_THREAD_LOCAL_P (value))
-+ remove = false;
-+ }
-+ }
-+ if (remove)
-+ error_at (OMP_CLAUSE_LOCATION (c),
-+ "copyprivate variable %qE is not threadprivate"
-+ " or private in outer context", DECL_NAME (decl));
-+ }
- do_notice:
- if (outer_ctx)
- omp_notice_variable (outer_ctx, decl, true);
- if (check_non_private
- && region_type == ORT_WORKSHARE
-- && omp_check_private (ctx, decl))
-+ && omp_check_private (ctx, decl, false))
- {
- error ("%s variable %qE is private in outer context",
- check_non_private, DECL_NAME (decl));
-@@ -8261,6 +8290,21 @@
-
- if (nonlocal_vlas)
- {
-+ if (nonlocal_vla_vars)
-+ {
-+ /* tree-nested.c may later on call declare_vars (..., true);
-+ which relies on BLOCK_VARS chain to be the tail of the
-+ gimple_bind_vars chain. Ensure we don't violate that
-+ assumption. */
-+ if (gimple_bind_block (outer_bind)
-+ == DECL_INITIAL (current_function_decl))
-+ declare_vars (nonlocal_vla_vars, outer_bind, true);
-+ else
-+ BLOCK_VARS (DECL_INITIAL (current_function_decl))
-+ = chainon (BLOCK_VARS (DECL_INITIAL (current_function_decl)),
-+ nonlocal_vla_vars);
-+ nonlocal_vla_vars = NULL_TREE;
-+ }
- pointer_set_destroy (nonlocal_vlas);
- nonlocal_vlas = NULL;
- }
-@@ -8588,6 +8632,8 @@
- gsi_insert_after (gsi_p, post_stmt, GSI_NEW_STMT);
-
- pop_gimplify_context (NULL);
-+
-+ update_stmt (stmt);
- }
-
- /* Expand EXPR to list of gimple statements STMTS. GIMPLE_TEST_F specifies
-Index: gcc/graphite-scop-detection.c
-===================================================================
---- a/src/gcc/graphite-scop-detection.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/graphite-scop-detection.c (.../branches/gcc-4_8-branch)
-@@ -203,7 +203,14 @@
-
- switch (TREE_CODE (scev))
- {
-+ case NEGATE_EXPR:
-+ case BIT_NOT_EXPR:
-+ CASE_CONVERT:
-+ case NON_LVALUE_EXPR:
-+ return graphite_can_represent_scev (TREE_OPERAND (scev, 0));
-+
- case PLUS_EXPR:
-+ case POINTER_PLUS_EXPR:
- case MINUS_EXPR:
- return graphite_can_represent_scev (TREE_OPERAND (scev, 0))
- && graphite_can_represent_scev (TREE_OPERAND (scev, 1));
-@@ -225,6 +232,7 @@
- if (!evolution_function_right_is_integer_cst (scev)
- || !graphite_can_represent_init (scev))
- return false;
-+ return graphite_can_represent_scev (CHREC_LEFT (scev));
-
- default:
- break;
-@@ -231,7 +239,8 @@
- }
-
- /* Only affine functions can be represented. */
-- if (!scev_is_linear_expression (scev))
-+ if (tree_contains_chrecs (scev, NULL)
-+ || !scev_is_linear_expression (scev))
- return false;
-
- return true;
-@@ -330,13 +339,10 @@
-
- case GIMPLE_COND:
- {
-- tree op;
-- ssa_op_iter op_iter;
-- enum tree_code code = gimple_cond_code (stmt);
--
- /* We can handle all binary comparisons. Inequalities are
- also supported as they can be represented with union of
- polyhedra. */
-+ enum tree_code code = gimple_cond_code (stmt);
- if (!(code == LT_EXPR
- || code == GT_EXPR
- || code == LE_EXPR
-@@ -345,11 +351,14 @@
- || code == NE_EXPR))
- return false;
-
-- FOR_EACH_SSA_TREE_OPERAND (op, stmt, op_iter, SSA_OP_ALL_USES)
-- if (!graphite_can_represent_expr (scop_entry, loop, op)
-- /* We can not handle REAL_TYPE. Failed for pr39260. */
-- || TREE_CODE (TREE_TYPE (op)) == REAL_TYPE)
-- return false;
-+ for (unsigned i = 0; i < 2; ++i)
-+ {
-+ tree op = gimple_op (stmt, i);
-+ if (!graphite_can_represent_expr (scop_entry, loop, op)
-+ /* We can not handle REAL_TYPE. Failed for pr39260. */
-+ || TREE_CODE (TREE_TYPE (op)) == REAL_TYPE)
-+ return false;
-+ }
-
- return true;
- }
-Index: gcc/lra-constraints.c
-===================================================================
---- a/src/gcc/lra-constraints.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/lra-constraints.c (.../branches/gcc-4_8-branch)
-@@ -1156,6 +1156,8 @@
- enum machine_mode mode;
- rtx reg, new_reg;
- rtx operand = *curr_id->operand_loc[nop];
-+ enum reg_class regclass;
-+ enum op_type type;
-
- before = after = NULL_RTX;
-
-@@ -1164,6 +1166,7 @@
-
- mode = GET_MODE (operand);
- reg = SUBREG_REG (operand);
-+ type = curr_static_id->operand[nop].type;
- /* If we change address for paradoxical subreg of memory, the
- address might violate the necessary alignment or the access might
- be slow. So take this into consideration. We should not worry
-@@ -1236,6 +1239,55 @@
- "Inserting subreg reload");
- return true;
- }
-+ /* Force a reload for a paradoxical subreg. For paradoxical subreg,
-+ IRA allocates hardreg to the inner pseudo reg according to its mode
-+ instead of the outermode, so the size of the hardreg may not be enough
-+ to contain the outermode operand, in that case we may need to insert
-+ reload for the reg. For the following two types of paradoxical subreg,
-+ we need to insert reload:
-+ 1. If the op_type is OP_IN, and the hardreg could not be paired with
-+ other hardreg to contain the outermode operand
-+ (checked by in_hard_reg_set_p), we need to insert the reload.
-+ 2. If the op_type is OP_OUT or OP_INOUT. */
-+ else if (REG_P (reg)
-+ && REGNO (reg) >= FIRST_PSEUDO_REGISTER
-+ && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
-+ && (hard_regno_nregs[hard_regno][GET_MODE (reg)]
-+ < hard_regno_nregs[hard_regno][mode])
-+ && (regclass = lra_get_allocno_class (REGNO (reg)))
-+ && (type != OP_IN
-+ || !in_hard_reg_set_p (reg_class_contents[regclass],
-+ mode, hard_regno)))
-+ {
-+ /* The class will be defined later in curr_insn_transform. */
-+ enum reg_class rclass
-+ = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
-+ rtx subreg;
-+
-+ new_reg = lra_create_new_reg_with_unique_value (mode, reg, rclass,
-+ "paradoxical subreg");
-+ PUT_MODE (new_reg, mode);
-+ subreg = simplify_gen_subreg (GET_MODE (reg), new_reg, mode, 0);
-+ if (type != OP_OUT)
-+ {
-+ push_to_sequence (before);
-+ lra_emit_move (subreg, reg);
-+ before = get_insns ();
-+ end_sequence ();
-+ }
-+ if (type != OP_IN)
-+ {
-+ start_sequence ();
-+ lra_emit_move (reg, subreg);
-+ emit_insn (after);
-+ after = get_insns ();
-+ end_sequence ();
-+ }
-+ SUBREG_REG (operand) = new_reg;
-+ lra_process_new_insns (curr_insn, before, after,
-+ "Inserting paradoxical subreg reload");
-+ return true;
-+ }
- return false;
- }
-
-Index: gcc/calls.c
-===================================================================
---- a/src/gcc/calls.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/calls.c (.../branches/gcc-4_8-branch)
-@@ -983,6 +983,7 @@
-
- for (i = 0; i < num_actuals; i++)
- if (args[i].reg != 0 && ! args[i].pass_on_stack
-+ && GET_CODE (args[i].reg) != PARALLEL
- && args[i].mode == BLKmode
- && MEM_P (args[i].value)
- && (MEM_ALIGN (args[i].value)
-@@ -1327,6 +1328,7 @@
- #else
- args[i].reg != 0,
- #endif
-+ reg_parm_stack_space,
- args[i].pass_on_stack ? 0 : args[i].partial,
- fndecl, args_size, &args[i].locate);
- #ifdef BLOCK_REG_PADDING
-@@ -3171,7 +3173,9 @@
- group load/store machinery below. */
- if (!structure_value_addr
- && !pcc_struct_value
-+ && TYPE_MODE (rettype) != VOIDmode
- && TYPE_MODE (rettype) != BLKmode
-+ && REG_P (valreg)
- && targetm.calls.return_in_msb (rettype))
- {
- if (shift_return_value (TYPE_MODE (rettype), false, valreg))
-@@ -3734,7 +3738,8 @@
- #else
- argvec[count].reg != 0,
- #endif
-- 0, NULL_TREE, &args_size, &argvec[count].locate);
-+ reg_parm_stack_space, 0,
-+ NULL_TREE, &args_size, &argvec[count].locate);
-
- if (argvec[count].reg == 0 || argvec[count].partial != 0
- || reg_parm_stack_space > 0)
-@@ -3821,7 +3826,7 @@
- #else
- argvec[count].reg != 0,
- #endif
-- argvec[count].partial,
-+ reg_parm_stack_space, argvec[count].partial,
- NULL_TREE, &args_size, &argvec[count].locate);
- args_size.constant += argvec[count].locate.size.constant;
- gcc_assert (!argvec[count].locate.size.var);
-Index: gcc/tree-dfa.c
-===================================================================
---- a/src/gcc/tree-dfa.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-dfa.c (.../branches/gcc-4_8-branch)
-@@ -386,7 +386,6 @@
- double_int bit_offset = double_int_zero;
- HOST_WIDE_INT hbit_offset;
- bool seen_variable_array_ref = false;
-- tree base_type;
-
- /* First get the final access size from just the outermost expression. */
- if (TREE_CODE (exp) == COMPONENT_REF)
-@@ -417,8 +416,6 @@
- and find the ultimate containing object. */
- while (1)
- {
-- base_type = TREE_TYPE (exp);
--
- switch (TREE_CODE (exp))
- {
- case BIT_FIELD_REF:
-@@ -543,7 +540,38 @@
- case VIEW_CONVERT_EXPR:
- break;
-
-+ case TARGET_MEM_REF:
-+ /* Via the variable index or index2 we can reach the
-+ whole object. Still hand back the decl here. */
-+ if (TREE_CODE (TMR_BASE (exp)) == ADDR_EXPR
-+ && (TMR_INDEX (exp) || TMR_INDEX2 (exp)))
-+ {
-+ exp = TREE_OPERAND (TMR_BASE (exp), 0);
-+ bit_offset = double_int_zero;
-+ maxsize = -1;
-+ goto done;
-+ }
-+ /* Fallthru. */
- case MEM_REF:
-+ /* We need to deal with variable arrays ending structures such as
-+ struct { int length; int a[1]; } x; x.a[d]
-+ struct { struct { int a; int b; } a[1]; } x; x.a[d].a
-+ struct { struct { int a[1]; } a[1]; } x; x.a[0][d], x.a[d][0]
-+ struct { int len; union { int a[1]; struct X x; } u; } x; x.u.a[d]
-+ where we do not know maxsize for variable index accesses to
-+ the array. The simplest way to conservatively deal with this
-+ is to punt in the case that offset + maxsize reaches the
-+ base type boundary. This needs to include possible trailing
-+ padding that is there for alignment purposes. */
-+ if (seen_variable_array_ref
-+ && maxsize != -1
-+ && (!bit_offset.fits_shwi ()
-+ || !host_integerp (TYPE_SIZE (TREE_TYPE (exp)), 1)
-+ || (bit_offset.to_shwi () + maxsize
-+ == (HOST_WIDE_INT) TREE_INT_CST_LOW
-+ (TYPE_SIZE (TREE_TYPE (exp))))))
-+ maxsize = -1;
-+
- /* Hand back the decl for MEM[&decl, off]. */
- if (TREE_CODE (TREE_OPERAND (exp, 0)) == ADDR_EXPR)
- {
-@@ -565,37 +593,6 @@
- }
- goto done;
-
-- case TARGET_MEM_REF:
-- /* Hand back the decl for MEM[&decl, off]. */
-- if (TREE_CODE (TMR_BASE (exp)) == ADDR_EXPR)
-- {
-- /* Via the variable index or index2 we can reach the
-- whole object. */
-- if (TMR_INDEX (exp) || TMR_INDEX2 (exp))
-- {
-- exp = TREE_OPERAND (TMR_BASE (exp), 0);
-- bit_offset = double_int_zero;
-- maxsize = -1;
-- goto done;
-- }
-- if (integer_zerop (TMR_OFFSET (exp)))
-- exp = TREE_OPERAND (TMR_BASE (exp), 0);
-- else
-- {
-- double_int off = mem_ref_offset (exp);
-- off = off.alshift (BITS_PER_UNIT == 8
-- ? 3 : exact_log2 (BITS_PER_UNIT),
-- HOST_BITS_PER_DOUBLE_INT);
-- off += bit_offset;
-- if (off.fits_shwi ())
-- {
-- bit_offset = off;
-- exp = TREE_OPERAND (TMR_BASE (exp), 0);
-- }
-- }
-- }
-- goto done;
--
- default:
- goto done;
- }
-@@ -602,8 +599,18 @@
-
- exp = TREE_OPERAND (exp, 0);
- }
-+
-+ /* We need to deal with variable arrays ending structures. */
-+ if (seen_variable_array_ref
-+ && maxsize != -1
-+ && (!bit_offset.fits_shwi ()
-+ || !host_integerp (TYPE_SIZE (TREE_TYPE (exp)), 1)
-+ || (bit_offset.to_shwi () + maxsize
-+ == (HOST_WIDE_INT)
-+ TREE_INT_CST_LOW (TYPE_SIZE (TREE_TYPE (exp))))))
-+ maxsize = -1;
-+
- done:
--
- if (!bit_offset.fits_shwi ())
- {
- *poffset = 0;
-@@ -615,24 +622,6 @@
-
- hbit_offset = bit_offset.to_shwi ();
-
-- /* We need to deal with variable arrays ending structures such as
-- struct { int length; int a[1]; } x; x.a[d]
-- struct { struct { int a; int b; } a[1]; } x; x.a[d].a
-- struct { struct { int a[1]; } a[1]; } x; x.a[0][d], x.a[d][0]
-- struct { int len; union { int a[1]; struct X x; } u; } x; x.u.a[d]
-- where we do not know maxsize for variable index accesses to
-- the array. The simplest way to conservatively deal with this
-- is to punt in the case that offset + maxsize reaches the
-- base type boundary. This needs to include possible trailing padding
-- that is there for alignment purposes. */
--
-- if (seen_variable_array_ref
-- && maxsize != -1
-- && (!host_integerp (TYPE_SIZE (base_type), 1)
-- || (hbit_offset + maxsize
-- == (signed) TREE_INT_CST_LOW (TYPE_SIZE (base_type)))))
-- maxsize = -1;
--
- /* In case of a decl or constant base object we can do better. */
-
- if (DECL_P (exp))
-Index: gcc/gimple-fold.c
-===================================================================
---- a/src/gcc/gimple-fold.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/gimple-fold.c (.../branches/gcc-4_8-branch)
-@@ -178,7 +178,7 @@
- /* Make sure we create a cgraph node for functions we'll reference.
- They can be non-existent if the reference comes from an entry
- of an external vtable for example. */
-- cgraph_get_create_node (base);
-+ cgraph_get_create_real_symbol_node (base);
- }
- /* Fixup types in global initializers. */
- if (TREE_TYPE (TREE_TYPE (cval)) != TREE_TYPE (TREE_OPERAND (cval, 0)))
-@@ -866,6 +866,7 @@
- break;
- case BUILT_IN_STRCPY:
- case BUILT_IN_STRNCPY:
-+ case BUILT_IN_STRCAT:
- arg_idx = 1;
- type = 0;
- break;
-@@ -941,6 +942,13 @@
- val[1]);
- break;
-
-+ case BUILT_IN_STRCAT:
-+ if (val[1] && is_gimple_val (val[1]) && nargs == 2)
-+ result = fold_builtin_strcat (loc, gimple_call_arg (stmt, 0),
-+ gimple_call_arg (stmt, 1),
-+ val[1]);
-+ break;
-+
- case BUILT_IN_FPUTS:
- if (nargs == 2)
- result = fold_builtin_fputs (loc, gimple_call_arg (stmt, 0),
-Index: gcc/cfgexpand.c
-===================================================================
---- a/src/gcc/cfgexpand.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cfgexpand.c (.../branches/gcc-4_8-branch)
-@@ -331,7 +331,7 @@
- enter its partition number into bitmap DATA. */
-
- static bool
--visit_op (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)
-+visit_op (gimple, tree op, tree, void *data)
- {
- bitmap active = (bitmap)data;
- op = get_base_address (op);
-@@ -351,7 +351,7 @@
- from bitmap DATA. */
-
- static bool
--visit_conflict (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data)
-+visit_conflict (gimple, tree op, tree, void *data)
- {
- bitmap active = (bitmap)data;
- op = get_base_address (op);
-@@ -385,7 +385,7 @@
- edge e;
- edge_iterator ei;
- gimple_stmt_iterator gsi;
-- bool (*visit)(gimple, tree, void *);
-+ walk_stmt_load_store_addr_fn visit;
-
- bitmap_clear (work);
- FOR_EACH_EDGE (e, ei, bb->preds)
-@@ -4707,14 +4707,18 @@
- if (e->insns.r)
- {
- rebuild_jump_labels_chain (e->insns.r);
-- /* Avoid putting insns before parm_birth_insn. */
-+ /* Put insns after parm birth, but before
-+ NOTE_INSNS_FUNCTION_BEG. */
- if (e->src == ENTRY_BLOCK_PTR
-- && single_succ_p (ENTRY_BLOCK_PTR)
-- && parm_birth_insn)
-+ && single_succ_p (ENTRY_BLOCK_PTR))
- {
- rtx insns = e->insns.r;
- e->insns.r = NULL_RTX;
-- emit_insn_after_noloc (insns, parm_birth_insn, e->dest);
-+ if (NOTE_P (parm_birth_insn)
-+ && NOTE_KIND (parm_birth_insn) == NOTE_INSN_FUNCTION_BEG)
-+ emit_insn_before_noloc (insns, parm_birth_insn, e->dest);
-+ else
-+ emit_insn_after_noloc (insns, parm_birth_insn, e->dest);
- }
- else
- commit_one_edge_insertion (e);
-Index: gcc/cselib.c
-===================================================================
---- a/src/gcc/cselib.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cselib.c (.../branches/gcc-4_8-branch)
-@@ -2260,8 +2260,8 @@
- continue;
- }
- if (num_mems < PARAM_VALUE (PARAM_MAX_CSELIB_MEMORY_LOCATIONS)
-- && ! canon_true_dependence (mem_rtx, GET_MODE (mem_rtx),
-- mem_addr, x, NULL_RTX))
-+ && ! canon_anti_dependence (x, false, mem_rtx,
-+ GET_MODE (mem_rtx), mem_addr))
- {
- has_mem = true;
- num_mems++;
-@@ -2623,12 +2623,13 @@
-
- cselib_current_insn = insn;
-
-- /* Forget everything at a CODE_LABEL, a volatile insn, or a setjmp. */
-+ /* Forget everything at a CODE_LABEL, a volatile asm, or a setjmp. */
- if ((LABEL_P (insn)
- || (CALL_P (insn)
- && find_reg_note (insn, REG_SETJMP, NULL))
- || (NONJUMP_INSN_P (insn)
-- && volatile_insn_p (PATTERN (insn))))
-+ && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
-+ && MEM_VOLATILE_P (PATTERN (insn))))
- && !cselib_preserve_constants)
- {
- cselib_reset_table (next_uid);
-Index: gcc/tree-cfgcleanup.c
-===================================================================
---- a/src/gcc/tree-cfgcleanup.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-cfgcleanup.c (.../branches/gcc-4_8-branch)
-@@ -539,9 +539,6 @@
- update_stmt (stmt);
- changed = true;
- }
-- /* Similarly remove VDEF if there is any. */
-- else if (gimple_vdef (stmt))
-- update_stmt (stmt);
- return changed;
- }
-
-Index: gcc/tree-ssa-pre.c
-===================================================================
---- a/src/gcc/tree-ssa-pre.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-pre.c (.../branches/gcc-4_8-branch)
-@@ -3664,6 +3664,12 @@
- if (dump_file && dump_flags & TDF_DETAILS)
- fprintf (dump_file, "Starting insert iteration %d\n", num_iterations);
- new_stuff = insert_aux (ENTRY_BLOCK_PTR);
-+
-+ /* Clear the NEW sets before the next iteration. We have already
-+ fully propagated its contents. */
-+ if (new_stuff)
-+ FOR_ALL_BB (bb)
-+ bitmap_set_free (NEW_SETS (bb));
- }
- statistics_histogram_event (cfun, "insert iterations", num_iterations);
- }
-Index: gcc/cfgcleanup.c
-===================================================================
---- a/src/gcc/cfgcleanup.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/cfgcleanup.c (.../branches/gcc-4_8-branch)
-@@ -1293,7 +1293,6 @@
- {
- rtx i1, i2, last1, last2, afterlast1, afterlast2;
- int ninsns = 0;
-- rtx p1;
- enum replace_direction dir, last_dir, afterlast_dir;
- bool follow_fallthru, did_fallthru;
-
-@@ -1321,8 +1320,9 @@
- || (returnjump_p (i2) && !side_effects_p (PATTERN (i2))))
- {
- last2 = i2;
-- /* Count everything except for unconditional jump as insn. */
-- if (!simplejump_p (i2) && !returnjump_p (i2) && last1)
-+ /* Count everything except for unconditional jump as insn.
-+ Don't count any jumps if dir_p is NULL. */
-+ if (!simplejump_p (i2) && !returnjump_p (i2) && last1 && dir_p)
- ninsns++;
- i2 = PREV_INSN (i2);
- }
-@@ -1373,8 +1373,8 @@
- last1 = i1, last2 = i2;
- afterlast_dir = last_dir;
- last_dir = dir;
-- p1 = PATTERN (i1);
-- if (!(GET_CODE (p1) == USE || GET_CODE (p1) == CLOBBER))
-+ if (GET_CODE (PATTERN (i1)) != USE
-+ && GET_CODE (PATTERN (i1)) != CLOBBER)
- ninsns++;
- }
-
-@@ -1420,7 +1420,8 @@
- /* Like flow_find_cross_jump, except start looking for a matching sequence from
- the head of the two blocks. Do not include jumps at the end.
- If STOP_AFTER is nonzero, stop after finding that many matching
-- instructions. */
-+ instructions. If STOP_AFTER is zero, count all INSN_P insns, if it is
-+ non-zero, only count active insns. */
-
- int
- flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1,
-@@ -1492,7 +1493,10 @@
-
- beforelast1 = last1, beforelast2 = last2;
- last1 = i1, last2 = i2;
-- ninsns++;
-+ if (!stop_after
-+ || (GET_CODE (PATTERN (i1)) != USE
-+ && GET_CODE (PATTERN (i1)) != CLOBBER))
-+ ninsns++;
- }
-
- if (i1 == BB_END (bb1) || i2 == BB_END (bb2)
-Index: gcc/simplify-rtx.c
-===================================================================
---- a/src/gcc/simplify-rtx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/simplify-rtx.c (.../branches/gcc-4_8-branch)
-@@ -639,11 +639,16 @@
- XEXP (op, 0), origmode);
- }
-
-- /* Simplify (truncate:SI (op:DI (x:DI) (y:DI)))
-- to (op:SI (truncate:SI (x:DI)) (truncate:SI (x:DI))). */
-- if (GET_CODE (op) == PLUS
-- || GET_CODE (op) == MINUS
-- || GET_CODE (op) == MULT)
-+ /* If the machine can perform operations in the truncated mode, distribute
-+ the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into
-+ (op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */
-+ if (1
-+#ifdef WORD_REGISTER_OPERATIONS
-+ && precision >= BITS_PER_WORD
-+#endif
-+ && (GET_CODE (op) == PLUS
-+ || GET_CODE (op) == MINUS
-+ || GET_CODE (op) == MULT))
- {
- rtx op0 = simplify_gen_unary (TRUNCATE, mode, XEXP (op, 0), op_mode);
- if (op0)
-Index: gcc/tree-ssa-live.c
-===================================================================
---- a/src/gcc/tree-ssa-live.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-live.c (.../branches/gcc-4_8-branch)
-@@ -394,7 +394,8 @@
- {
- /* When a global var becomes used for the first time also walk its
- initializer (non global ones don't have any). */
-- if (set_is_used (t) && is_global_var (t))
-+ if (set_is_used (t) && is_global_var (t)
-+ && DECL_CONTEXT (t) == current_function_decl)
- mark_all_vars_used (&DECL_INITIAL (t));
- }
- /* remove_unused_scope_block_p requires information about labels
-Index: gcc/tree-sra.c
-===================================================================
---- a/src/gcc/tree-sra.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-sra.c (.../branches/gcc-4_8-branch)
-@@ -1161,8 +1161,7 @@
- GIMPLE_ASM operands with memory constrains which cannot be scalarized. */
-
- static bool
--asm_visit_addr (gimple stmt ATTRIBUTE_UNUSED, tree op,
-- void *data ATTRIBUTE_UNUSED)
-+asm_visit_addr (gimple, tree op, tree, void *)
- {
- op = get_base_address (op);
- if (op
-@@ -2890,6 +2889,10 @@
- lacc);
- else
- drhs = NULL_TREE;
-+ if (drhs
-+ && !useless_type_conversion_p (lacc->type, TREE_TYPE (drhs)))
-+ drhs = fold_build1_loc (loc, VIEW_CONVERT_EXPR,
-+ lacc->type, drhs);
- ds = gimple_build_debug_bind (get_access_replacement (lacc),
- drhs, gsi_stmt (*old_gsi));
- gsi_insert_after (new_gsi, ds, GSI_NEW_STMT);
-@@ -4868,6 +4871,14 @@
- return false;
- }
-
-+ if (!opt_for_fn (node->symbol.decl, optimize)
-+ || !opt_for_fn (node->symbol.decl, flag_ipa_sra))
-+ {
-+ if (dump_file)
-+ fprintf (dump_file, "Function not optimized.\n");
-+ return false;
-+ }
-+
- if (DECL_VIRTUAL_P (current_function_decl))
- {
- if (dump_file)
-Index: gcc/tree-predcom.c
-===================================================================
---- a/src/gcc/tree-predcom.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-predcom.c (.../branches/gcc-4_8-branch)
-@@ -1323,90 +1323,43 @@
- gsi_insert_after (&bsi, new_stmt, GSI_NEW_STMT);
- }
-
--/* Returns the reference to the address of REF in the ITER-th iteration of
-- LOOP, or NULL if we fail to determine it (ITER may be negative). We
-- try to preserve the original shape of the reference (not rewrite it
-- as an indirect ref to the address), to make tree_could_trap_p in
-- prepare_initializers_chain return false more often. */
-+/* Returns a memory reference to DR in the ITER-th iteration of
-+ the loop it was analyzed in. Append init stmts to STMTS. */
-
--static tree
--ref_at_iteration (struct loop *loop, tree ref, int iter)
-+static tree
-+ref_at_iteration (data_reference_p dr, int iter, gimple_seq *stmts)
- {
-- tree idx, *idx_p, type, val, op0 = NULL_TREE, ret;
-- affine_iv iv;
-- bool ok;
--
-- if (handled_component_p (ref))
-+ tree off = DR_OFFSET (dr);
-+ tree coff = DR_INIT (dr);
-+ if (iter == 0)
-+ ;
-+ else if (TREE_CODE (DR_STEP (dr)) == INTEGER_CST)
-+ coff = size_binop (PLUS_EXPR, coff,
-+ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter)));
-+ else
-+ off = size_binop (PLUS_EXPR, off,
-+ size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter)));
-+ tree addr = fold_build_pointer_plus (DR_BASE_ADDRESS (dr), off);
-+ addr = force_gimple_operand_1 (addr, stmts, is_gimple_mem_ref_addr,
-+ NULL_TREE);
-+ tree alias_ptr = fold_convert (reference_alias_ptr_type (DR_REF (dr)), coff);
-+ /* While data-ref analysis punts on bit offsets it still handles
-+ bitfield accesses at byte boundaries. Cope with that. Note that
-+ we cannot simply re-apply the outer COMPONENT_REF because the
-+ byte-granular portion of it is already applied via DR_INIT and
-+ DR_OFFSET, so simply build a BIT_FIELD_REF knowing that the bits
-+ start at offset zero. */
-+ if (TREE_CODE (DR_REF (dr)) == COMPONENT_REF
-+ && DECL_BIT_FIELD (TREE_OPERAND (DR_REF (dr), 1)))
- {
-- op0 = ref_at_iteration (loop, TREE_OPERAND (ref, 0), iter);
-- if (!op0)
-- return NULL_TREE;
-+ tree field = TREE_OPERAND (DR_REF (dr), 1);
-+ return build3 (BIT_FIELD_REF, TREE_TYPE (DR_REF (dr)),
-+ build2 (MEM_REF, DECL_BIT_FIELD_TYPE (field),
-+ addr, alias_ptr),
-+ DECL_SIZE (field), bitsize_zero_node);
- }
-- else if (!INDIRECT_REF_P (ref)
-- && TREE_CODE (ref) != MEM_REF)
-- return unshare_expr (ref);
--
-- if (TREE_CODE (ref) == MEM_REF)
-- {
-- ret = unshare_expr (ref);
-- idx = TREE_OPERAND (ref, 0);
-- idx_p = &TREE_OPERAND (ret, 0);
-- }
-- else if (TREE_CODE (ref) == COMPONENT_REF)
-- {
-- /* Check that the offset is loop invariant. */
-- if (TREE_OPERAND (ref, 2)
-- && !expr_invariant_in_loop_p (loop, TREE_OPERAND (ref, 2)))
-- return NULL_TREE;
--
-- return build3 (COMPONENT_REF, TREE_TYPE (ref), op0,
-- unshare_expr (TREE_OPERAND (ref, 1)),
-- unshare_expr (TREE_OPERAND (ref, 2)));
-- }
-- else if (TREE_CODE (ref) == ARRAY_REF)
-- {
-- /* Check that the lower bound and the step are loop invariant. */
-- if (TREE_OPERAND (ref, 2)
-- && !expr_invariant_in_loop_p (loop, TREE_OPERAND (ref, 2)))
-- return NULL_TREE;
-- if (TREE_OPERAND (ref, 3)
-- && !expr_invariant_in_loop_p (loop, TREE_OPERAND (ref, 3)))
-- return NULL_TREE;
--
-- ret = build4 (ARRAY_REF, TREE_TYPE (ref), op0, NULL_TREE,
-- unshare_expr (TREE_OPERAND (ref, 2)),
-- unshare_expr (TREE_OPERAND (ref, 3)));
-- idx = TREE_OPERAND (ref, 1);
-- idx_p = &TREE_OPERAND (ret, 1);
-- }
- else
-- return NULL_TREE;
--
-- ok = simple_iv (loop, loop, idx, &iv, true);
-- if (!ok)
-- return NULL_TREE;
-- iv.base = expand_simple_operations (iv.base);
-- if (integer_zerop (iv.step))
-- *idx_p = unshare_expr (iv.base);
-- else
-- {
-- type = TREE_TYPE (iv.base);
-- if (POINTER_TYPE_P (type))
-- {
-- val = fold_build2 (MULT_EXPR, sizetype, iv.step,
-- size_int (iter));
-- val = fold_build_pointer_plus (iv.base, val);
-- }
-- else
-- {
-- val = fold_build2 (MULT_EXPR, type, iv.step,
-- build_int_cst_type (type, iter));
-- val = fold_build2 (PLUS_EXPR, type, iv.base, val);
-- }
-- *idx_p = unshare_expr (val);
-- }
--
-- return ret;
-+ return fold_build2 (MEM_REF, TREE_TYPE (DR_REF (dr)), addr, alias_ptr);
- }
-
- /* Get the initialization expression for the INDEX-th temporary variable
-@@ -2068,7 +2021,11 @@
-
- stmt = find_common_use_stmt (&name1, &name2);
-
-- if (!stmt)
-+ if (!stmt
-+ /* A simple post-dominance check - make sure the combination
-+ is executed under the same condition as the references. */
-+ || (gimple_bb (stmt) != gimple_bb (r1->stmt)
-+ && gimple_bb (stmt) != gimple_bb (r2->stmt)))
- return false;
-
- acode = gimple_assign_rhs_code (stmt);
-@@ -2365,14 +2322,10 @@
- if (chain->inits[i] != NULL_TREE)
- continue;
-
-- init = ref_at_iteration (loop, DR_REF (dr), (int) i - n);
-- if (!init)
-- return false;
--
-+ init = ref_at_iteration (dr, (int) i - n, &stmts);
- if (!chain->all_always_accessed && tree_could_trap_p (init))
- return false;
-
-- init = force_gimple_operand (init, &stmts, false, NULL_TREE);
- if (stmts)
- gsi_insert_seq_on_edge_immediate (entry, stmts);
-
-@@ -2449,6 +2402,7 @@
- if (!components)
- {
- free_data_refs (datarefs);
-+ free_affine_expand_cache (&name_expansions);
- return false;
- }
-
-Index: gcc/loop-iv.c
-===================================================================
---- a/src/gcc/loop-iv.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/loop-iv.c (.../branches/gcc-4_8-branch)
-@@ -425,7 +425,9 @@
- && !iv->first_special)
- {
- rtx val = get_iv_value (iv, const0_rtx);
-- val = lowpart_subreg (mode, val, iv->extend_mode);
-+ val = lowpart_subreg (mode, val,
-+ iv->extend == IV_UNKNOWN_EXTEND
-+ ? iv->mode : iv->extend_mode);
-
- iv->base = val;
- iv->extend = IV_UNKNOWN_EXTEND;
-@@ -465,8 +467,14 @@
- && !iv->first_special)
- {
- rtx val = get_iv_value (iv, const0_rtx);
-+ if (iv->extend_mode != iv->mode
-+ && iv->extend != IV_UNKNOWN_EXTEND
-+ && iv->extend != extend)
-+ val = lowpart_subreg (iv->mode, val, iv->extend_mode);
- val = simplify_gen_unary (iv_extend_to_rtx_code (extend), mode,
-- val, iv->extend_mode);
-+ val,
-+ iv->extend == extend
-+ ? iv->extend_mode : iv->mode);
- iv->base = val;
- iv->extend = IV_UNKNOWN_EXTEND;
- iv->mode = iv->extend_mode = mode;
-Index: gcc/ipa-prop.c
-===================================================================
---- a/src/gcc/ipa-prop.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ipa-prop.c (.../branches/gcc-4_8-branch)
-@@ -623,16 +623,22 @@
- if (parm_ainfo && parm_ainfo->parm_modified)
- return false;
-
-- gcc_checking_assert (gimple_vuse (stmt) != NULL_TREE);
-- ao_ref_init (&refd, parm_load);
-- /* We can cache visited statements only when parm_ainfo is available and when
-- we are looking at a naked load of the whole parameter. */
-- if (!parm_ainfo || TREE_CODE (parm_load) != PARM_DECL)
-- visited_stmts = NULL;
-+ if (optimize)
-+ {
-+ gcc_checking_assert (gimple_vuse (stmt) != NULL_TREE);
-+ ao_ref_init (&refd, parm_load);
-+ /* We can cache visited statements only when parm_ainfo is available and
-+ when we are looking at a naked load of the whole parameter. */
-+ if (!parm_ainfo || TREE_CODE (parm_load) != PARM_DECL)
-+ visited_stmts = NULL;
-+ else
-+ visited_stmts = &parm_ainfo->parm_visited_statements;
-+ walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified,
-+ visited_stmts);
-+ }
- else
-- visited_stmts = &parm_ainfo->parm_visited_statements;
-- walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified,
-- visited_stmts);
-+ modified = true;
-+
- if (parm_ainfo && modified)
- parm_ainfo->parm_modified = true;
- return !modified;
-@@ -740,7 +746,7 @@
- ipa_load_from_parm_agg_1 (vec<ipa_param_descriptor_t> descriptors,
- struct param_analysis_info *parms_ainfo, gimple stmt,
- tree op, int *index_p, HOST_WIDE_INT *offset_p,
-- bool *by_ref_p)
-+ HOST_WIDE_INT *size_p, bool *by_ref_p)
- {
- int index;
- HOST_WIDE_INT size, max_size;
-@@ -758,6 +764,8 @@
- {
- *index_p = index;
- *by_ref_p = false;
-+ if (size_p)
-+ *size_p = size;
- return true;
- }
- return false;
-@@ -800,6 +808,8 @@
- {
- *index_p = index;
- *by_ref_p = true;
-+ if (size_p)
-+ *size_p = size;
- return true;
- }
- return false;
-@@ -814,7 +824,7 @@
- bool *by_ref_p)
- {
- return ipa_load_from_parm_agg_1 (info->descriptors, NULL, stmt, op, index_p,
-- offset_p, by_ref_p);
-+ offset_p, NULL, by_ref_p);
- }
-
- /* Given that an actual argument is an SSA_NAME (given in NAME) and is a result
-@@ -1051,7 +1061,8 @@
- return;
- parm = TREE_OPERAND (expr, 0);
- index = ipa_get_param_decl_index (info, SSA_NAME_VAR (parm));
-- gcc_assert (index >= 0);
-+ if (index < 0)
-+ return;
-
- cond_bb = single_pred (assign_bb);
- cond = last_stmt (cond_bb);
-@@ -1462,6 +1473,9 @@
- {
- struct cgraph_edge *cs;
-
-+ if (!optimize)
-+ return;
-+
- for (cs = node->callees; cs; cs = cs->next_callee)
- {
- struct cgraph_node *callee = cgraph_function_or_thunk_node (cs->callee,
-@@ -1646,7 +1660,7 @@
- if (gimple_assign_single_p (def)
- && ipa_load_from_parm_agg_1 (info->descriptors, parms_ainfo, def,
- gimple_assign_rhs1 (def), &index, &offset,
-- &by_ref))
-+ NULL, &by_ref))
- {
- struct cgraph_edge *cs = ipa_note_param_call (node, index, call);
- cs->indirect_info->offset = offset;
-@@ -1847,8 +1861,7 @@
- passed in DATA. */
-
- static bool
--visit_ref_for_mod_analysis (gimple stmt ATTRIBUTE_UNUSED,
-- tree op, void *data)
-+visit_ref_for_mod_analysis (gimple, tree op, tree, void *data)
- {
- struct ipa_node_params *info = (struct ipa_node_params *) data;
-
-@@ -2126,7 +2139,6 @@
- we may create the first reference to the object in the unit. */
- if (!callee || callee->global.inlined_to)
- {
-- struct cgraph_node *first_clone = callee;
-
- /* We are better to ensure we can refer to it.
- In the case of static functions we are out of luck, since we already
-@@ -2142,31 +2154,7 @@
- xstrdup (cgraph_node_name (ie->callee)), ie->callee->uid);
- return NULL;
- }
--
-- /* Create symbol table node. Even if inline clone exists, we can not take
-- it as a target of non-inlined call. */
-- callee = cgraph_create_node (target);
--
-- /* OK, we previously inlined the function, then removed the offline copy and
-- now we want it back for external call. This can happen when devirtualizing
-- while inlining function called once that happens after extern inlined and
-- virtuals are already removed. In this case introduce the external node
-- and make it available for call. */
-- if (first_clone)
-- {
-- first_clone->clone_of = callee;
-- callee->clones = first_clone;
-- symtab_prevail_in_asm_name_hash ((symtab_node)callee);
-- symtab_insert_node_to_hashtable ((symtab_node)callee);
-- if (dump_file)
-- fprintf (dump_file, "ipa-prop: Introduced new external node "
-- "(%s/%i) and turned into root of the clone tree.\n",
-- xstrdup (cgraph_node_name (callee)), callee->uid);
-- }
-- else if (dump_file)
-- fprintf (dump_file, "ipa-prop: Introduced new external node "
-- "(%s/%i).\n",
-- xstrdup (cgraph_node_name (callee)), callee->uid);
-+ callee = cgraph_get_create_real_symbol_node (target);
- }
- ipa_check_create_node_params ();
-
-@@ -3902,7 +3890,7 @@
- struct ipa_agg_replacement_value *v;
- gimple stmt = gsi_stmt (gsi);
- tree rhs, val, t;
-- HOST_WIDE_INT offset;
-+ HOST_WIDE_INT offset, size;
- int index;
- bool by_ref, vce;
-
-@@ -3929,13 +3917,15 @@
- continue;
-
- if (!ipa_load_from_parm_agg_1 (descriptors, parms_ainfo, stmt,
-- rhs, &index, &offset, &by_ref))
-+ rhs, &index, &offset, &size, &by_ref))
- continue;
- for (v = aggval; v; v = v->next)
- if (v->index == index
- && v->offset == offset)
- break;
-- if (!v || v->by_ref != by_ref)
-+ if (!v
-+ || v->by_ref != by_ref
-+ || tree_low_cst (TYPE_SIZE (TREE_TYPE (v->value)), 0) != size)
- continue;
-
- gcc_checking_assert (is_gimple_ip_invariant (v->value));
-Index: gcc/tree-ssa-dce.c
-===================================================================
---- a/src/gcc/tree-ssa-dce.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-dce.c (.../branches/gcc-4_8-branch)
-@@ -1307,26 +1307,19 @@
- stats.total++;
-
- /* We can mark a call to free as not necessary if the
-- defining statement of its argument is an allocation
-- function and that is not necessary itself. */
-- if (gimple_call_builtin_p (stmt, BUILT_IN_FREE))
-+ defining statement of its argument is not necessary
-+ (and thus is getting removed). */
-+ if (gimple_plf (stmt, STMT_NECESSARY)
-+ && gimple_call_builtin_p (stmt, BUILT_IN_FREE))
- {
- tree ptr = gimple_call_arg (stmt, 0);
-- tree callee2;
-- gimple def_stmt;
-- if (TREE_CODE (ptr) != SSA_NAME)
-- continue;
-- def_stmt = SSA_NAME_DEF_STMT (ptr);
-- if (!is_gimple_call (def_stmt)
-- || gimple_plf (def_stmt, STMT_NECESSARY))
-- continue;
-- callee2 = gimple_call_fndecl (def_stmt);
-- if (callee2 == NULL_TREE
-- || DECL_BUILT_IN_CLASS (callee2) != BUILT_IN_NORMAL
-- || (DECL_FUNCTION_CODE (callee2) != BUILT_IN_MALLOC
-- && DECL_FUNCTION_CODE (callee2) != BUILT_IN_CALLOC))
-- continue;
-- gimple_set_plf (stmt, STMT_NECESSARY, false);
-+ if (TREE_CODE (ptr) == SSA_NAME)
-+ {
-+ gimple def_stmt = SSA_NAME_DEF_STMT (ptr);
-+ if (!gimple_nop_p (def_stmt)
-+ && !gimple_plf (def_stmt, STMT_NECESSARY))
-+ gimple_set_plf (stmt, STMT_NECESSARY, false);
-+ }
- }
-
- /* If GSI is not necessary then remove it. */
-Index: gcc/tree-ssa-ter.c
-===================================================================
---- a/src/gcc/tree-ssa-ter.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-ter.c (.../branches/gcc-4_8-branch)
-@@ -590,6 +590,30 @@
- }
-
-
-+/* Helper function for find_ssaname_in_stores. Called via walk_tree to
-+ find a SSA_NAME DATA somewhere in *TP. */
-+
-+static tree
-+find_ssaname (tree *tp, int *walk_subtrees, void *data)
-+{
-+ tree var = (tree) data;
-+ if (*tp == var)
-+ return var;
-+ else if (IS_TYPE_OR_DECL_P (*tp))
-+ *walk_subtrees = 0;
-+ return NULL_TREE;
-+}
-+
-+/* Helper function for find_replaceable_in_bb. Return true if SSA_NAME DATA
-+ is used somewhere in T, which is a store in the statement. Called via
-+ walk_stmt_load_store_addr_ops. */
-+
-+static bool
-+find_ssaname_in_store (gimple, tree, tree t, void *data)
-+{
-+ return walk_tree (&t, find_ssaname, data, NULL) != NULL_TREE;
-+}
-+
- /* This function processes basic block BB, and looks for variables which can
- be replaced by their expressions. Results are stored in the table TAB. */
-
-@@ -643,8 +667,7 @@
- /* If the stmt does a memory store and the replacement
- is a load aliasing it avoid creating overlapping
- assignments which we cannot expand correctly. */
-- if (gimple_vdef (stmt)
-- && gimple_assign_single_p (stmt))
-+ if (gimple_vdef (stmt))
- {
- gimple def_stmt = SSA_NAME_DEF_STMT (use);
- while (is_gimple_assign (def_stmt)
-@@ -653,9 +676,29 @@
- = SSA_NAME_DEF_STMT (gimple_assign_rhs1 (def_stmt));
- if (gimple_vuse (def_stmt)
- && gimple_assign_single_p (def_stmt)
-- && refs_may_alias_p (gimple_assign_lhs (stmt),
-- gimple_assign_rhs1 (def_stmt)))
-- same_root_var = true;
-+ && stmt_may_clobber_ref_p (stmt,
-+ gimple_assign_rhs1 (def_stmt)))
-+ {
-+ /* For calls, it is not a problem if USE is among
-+ call's arguments or say OBJ_TYPE_REF argument,
-+ all those necessarily need to be evaluated before
-+ the call that may clobber the memory. But if
-+ LHS of the call refers to USE, expansion might
-+ evaluate it after the call, prevent TER in that
-+ case.
-+ For inline asm, allow TER of loads into input
-+ arguments, but disallow TER for USEs that occur
-+ somewhere in outputs. */
-+ if (is_gimple_call (stmt)
-+ || gimple_code (stmt) == GIMPLE_ASM)
-+ {
-+ if (walk_stmt_load_store_ops (stmt, use, NULL,
-+ find_ssaname_in_store))
-+ same_root_var = true;
-+ }
-+ else
-+ same_root_var = true;
-+ }
- }
-
- /* Mark expression as replaceable unless stmt is volatile, or the
-Index: gcc/ira.c
-===================================================================
---- a/src/gcc/ira.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/ira.c (.../branches/gcc-4_8-branch)
-@@ -4742,6 +4742,18 @@
- if (need_dce && optimize)
- run_fast_dce ();
-
-+ /* Diagnose uses of the hard frame pointer when it is used as a global
-+ register. Often we can get away with letting the user appropriate
-+ the frame pointer, but we should let them know when code generation
-+ makes that impossible. */
-+ if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed)
-+ {
-+ tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM];
-+ error_at (DECL_SOURCE_LOCATION (current_function_decl),
-+ "frame pointer required, but reserved");
-+ inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl);
-+ }
-+
- timevar_pop (TV_IRA);
- }
-
-Index: gcc/rtl.h
-===================================================================
---- a/src/gcc/rtl.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/rtl.h (.../branches/gcc-4_8-branch)
-@@ -2705,6 +2705,8 @@
- const_rtx, rtx);
- extern int read_dependence (const_rtx, const_rtx);
- extern int anti_dependence (const_rtx, const_rtx);
-+extern int canon_anti_dependence (const_rtx, bool,
-+ const_rtx, enum machine_mode, rtx);
- extern int output_dependence (const_rtx, const_rtx);
- extern int may_alias_p (const_rtx, const_rtx);
- extern void init_alias_target (void);
-@@ -2789,6 +2791,8 @@
- #define fatal_insn_not_found(insn) \
- _fatal_insn_not_found (insn, __FILE__, __LINE__, __FUNCTION__)
-
-+/* reginfo.c */
-+extern tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER];
-
-
- #endif /* ! GCC_RTL_H */
-Index: gcc/tree-vect-stmts.c
-===================================================================
---- a/src/gcc/tree-vect-stmts.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-vect-stmts.c (.../branches/gcc-4_8-branch)
-@@ -4369,6 +4369,20 @@
- return false;
- }
-
-+ /* Invalidate assumptions made by dependence analysis when vectorization
-+ on the unrolled body effectively re-orders stmts. */
-+ if (ncopies > 1
-+ && STMT_VINFO_MIN_NEG_DIST (stmt_info) != 0
-+ && ((unsigned)LOOP_VINFO_VECT_FACTOR (loop_vinfo)
-+ > STMT_VINFO_MIN_NEG_DIST (stmt_info)))
-+ {
-+ if (dump_enabled_p ())
-+ dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
-+ "cannot perform implicit CSE when unrolling "
-+ "with negative dependence distance\n");
-+ return false;
-+ }
-+
- if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)
- return false;
-
-@@ -4425,6 +4439,20 @@
- else if (!vect_grouped_load_supported (vectype, group_size))
- return false;
- }
-+
-+ /* Invalidate assumptions made by dependence analysis when vectorization
-+ on the unrolled body effectively re-orders stmts. */
-+ if (!PURE_SLP_STMT (stmt_info)
-+ && STMT_VINFO_MIN_NEG_DIST (stmt_info) != 0
-+ && ((unsigned)LOOP_VINFO_VECT_FACTOR (loop_vinfo)
-+ > STMT_VINFO_MIN_NEG_DIST (stmt_info)))
-+ {
-+ if (dump_enabled_p ())
-+ dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
-+ "cannot perform implicit CSE when performing "
-+ "group loads with negative dependence distance\n");
-+ return false;
-+ }
- }
-
-
-@@ -6054,8 +6082,7 @@
- corresponding to that mode. The theory is that any use that
- would cause problems with this will disable vectorization anyway. */
- else if (!SCALAR_FLOAT_TYPE_P (scalar_type)
-- && !INTEGRAL_TYPE_P (scalar_type)
-- && !POINTER_TYPE_P (scalar_type))
-+ && !INTEGRAL_TYPE_P (scalar_type))
- scalar_type = lang_hooks.types.type_for_mode (inner_mode, 1);
-
- /* We can't build a vector type of elements with alignment bigger than
-Index: gcc/tree-inline.c
-===================================================================
---- a/src/gcc/tree-inline.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-inline.c (.../branches/gcc-4_8-branch)
-@@ -2841,7 +2841,8 @@
- {
- var = return_slot;
- gcc_assert (TREE_CODE (var) != SSA_NAME);
-- TREE_ADDRESSABLE (var) |= TREE_ADDRESSABLE (result);
-+ if (TREE_ADDRESSABLE (result))
-+ mark_addressable (var);
- }
- if ((TREE_CODE (TREE_TYPE (result)) == COMPLEX_TYPE
- || TREE_CODE (TREE_TYPE (result)) == VECTOR_TYPE)
-Index: gcc/tree-ssa-phiprop.c
-===================================================================
---- a/src/gcc/tree-ssa-phiprop.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-phiprop.c (.../branches/gcc-4_8-branch)
-@@ -307,6 +307,12 @@
- gimple def_stmt;
- tree vuse;
-
-+ /* Only replace loads in blocks that post-dominate the PHI node. That
-+ makes sure we don't end up speculating loads. */
-+ if (!dominated_by_p (CDI_POST_DOMINATORS,
-+ bb, gimple_bb (use_stmt)))
-+ continue;
-+
- /* Check whether this is a load of *ptr. */
- if (!(is_gimple_assign (use_stmt)
- && TREE_CODE (gimple_assign_lhs (use_stmt)) == SSA_NAME
-@@ -378,6 +384,7 @@
- size_t n;
-
- calculate_dominance_info (CDI_DOMINATORS);
-+ calculate_dominance_info (CDI_POST_DOMINATORS);
-
- n = num_ssa_names;
- phivn = XCNEWVEC (struct phiprop_d, n);
-@@ -395,6 +402,8 @@
- bbs.release ();
- free (phivn);
-
-+ free_dominance_info (CDI_POST_DOMINATORS);
-+
- return 0;
- }
-
-Index: gcc/tree-object-size.c
-===================================================================
---- a/src/gcc/tree-object-size.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-object-size.c (.../branches/gcc-4_8-branch)
-@@ -64,7 +64,7 @@
- the subobject (innermost array or field with address taken).
- object_sizes[2] is lower bound for number of bytes till the end of
- the object and object_sizes[3] lower bound for subobject. */
--static unsigned HOST_WIDE_INT *object_sizes[4];
-+static vec<unsigned HOST_WIDE_INT> object_sizes[4];
-
- /* Bitmaps what object sizes have been computed already. */
- static bitmap computed[4];
-@@ -493,7 +493,7 @@
-
- if (TREE_CODE (ptr) == SSA_NAME
- && POINTER_TYPE_P (TREE_TYPE (ptr))
-- && object_sizes[object_size_type] != NULL)
-+ && computed[object_size_type] != NULL)
- {
- if (!bitmap_bit_p (computed[object_size_type], SSA_NAME_VERSION (ptr)))
- {
-@@ -501,6 +501,8 @@
- bitmap_iterator bi;
- unsigned int i;
-
-+ if (num_ssa_names > object_sizes[object_size_type].length ())
-+ object_sizes[object_size_type].safe_grow (num_ssa_names);
- if (dump_file)
- {
- fprintf (dump_file, "Computing %s %sobject size for ",
-@@ -1162,12 +1164,12 @@
- {
- int object_size_type;
-
-- if (object_sizes[0])
-+ if (computed[0])
- return;
-
- for (object_size_type = 0; object_size_type <= 3; object_size_type++)
- {
-- object_sizes[object_size_type] = XNEWVEC (unsigned HOST_WIDE_INT, num_ssa_names);
-+ object_sizes[object_size_type].safe_grow (num_ssa_names);
- computed[object_size_type] = BITMAP_ALLOC (NULL);
- }
-
-@@ -1184,9 +1186,8 @@
-
- for (object_size_type = 0; object_size_type <= 3; object_size_type++)
- {
-- free (object_sizes[object_size_type]);
-+ object_sizes[object_size_type].release ();
- BITMAP_FREE (computed[object_size_type]);
-- object_sizes[object_size_type] = NULL;
- }
- }
-
-@@ -1202,18 +1203,11 @@
- gimple_stmt_iterator i;
- for (i = gsi_start_bb (bb); !gsi_end_p (i); gsi_next (&i))
- {
-- tree callee, result;
-+ tree result;
- gimple call = gsi_stmt (i);
--
-- if (gimple_code (call) != GIMPLE_CALL)
-+ if (!gimple_call_builtin_p (call, BUILT_IN_OBJECT_SIZE))
- continue;
-
-- callee = gimple_call_fndecl (call);
-- if (!callee
-- || DECL_BUILT_IN_CLASS (callee) != BUILT_IN_NORMAL
-- || DECL_FUNCTION_CODE (callee) != BUILT_IN_OBJECT_SIZE)
-- continue;
--
- init_object_sizes ();
- result = fold_call_stmt (call, false);
- if (!result)
-@@ -1240,20 +1234,32 @@
- continue;
- }
-
-+ gcc_assert (TREE_CODE (result) == INTEGER_CST);
-+
- if (dump_file && (dump_flags & TDF_DETAILS))
- {
- fprintf (dump_file, "Simplified\n ");
- print_gimple_stmt (dump_file, call, 0, dump_flags);
-+ fprintf (dump_file, " to ");
-+ print_generic_expr (dump_file, result, 0);
-+ fprintf (dump_file, "\n");
- }
-
-- if (!update_call_from_tree (&i, result))
-- gcc_unreachable ();
-+ tree lhs = gimple_call_lhs (call);
-+ if (!lhs)
-+ continue;
-
-- if (dump_file && (dump_flags & TDF_DETAILS))
-+ /* Propagate into all uses and fold those stmts. */
-+ gimple use_stmt;
-+ imm_use_iterator iter;
-+ FOR_EACH_IMM_USE_STMT (use_stmt, iter, lhs)
- {
-- fprintf (dump_file, "to\n ");
-- print_gimple_stmt (dump_file, gsi_stmt (i), 0, dump_flags);
-- fprintf (dump_file, "\n");
-+ use_operand_p use_p;
-+ FOR_EACH_IMM_USE_ON_STMT (use_p, iter)
-+ SET_USE (use_p, result);
-+ gimple_stmt_iterator gsi = gsi_for_stmt (use_stmt);
-+ fold_stmt (&gsi);
-+ update_stmt (gsi_stmt (gsi));
- }
- }
- }
-Index: gcc/combine.c
-===================================================================
---- a/src/gcc/combine.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/combine.c (.../branches/gcc-4_8-branch)
-@@ -3884,15 +3884,19 @@
-
- PATTERN (undobuf.other_insn) = other_pat;
-
-- /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
-- are still valid. Then add any non-duplicate notes added by
-- recog_for_combine. */
-+ /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
-+ ensure that they are still valid. Then add any non-duplicate
-+ notes added by recog_for_combine. */
- for (note = REG_NOTES (undobuf.other_insn); note; note = next)
- {
- next = XEXP (note, 1);
-
-- if (REG_NOTE_KIND (note) == REG_UNUSED
-- && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
-+ if ((REG_NOTE_KIND (note) == REG_DEAD
-+ && !reg_referenced_p (XEXP (note, 0),
-+ PATTERN (undobuf.other_insn)))
-+ ||(REG_NOTE_KIND (note) == REG_UNUSED
-+ && !reg_set_p (XEXP (note, 0),
-+ PATTERN (undobuf.other_insn))))
- remove_note (undobuf.other_insn, note);
- }
-
-@@ -5798,8 +5802,15 @@
- return x;
- }
-
-- /* If the code changed, return a whole new comparison. */
-- if (new_code != code)
-+ /* If the code changed, return a whole new comparison.
-+ We also need to avoid using SUBST in cases where
-+ simplify_comparison has widened a comparison with a CONST_INT,
-+ since in that case the wider CONST_INT may fail the sanity
-+ checks in do_SUBST. */
-+ if (new_code != code
-+ || (CONST_INT_P (op1)
-+ && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
-+ && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
- return gen_rtx_fmt_ee (new_code, mode, op0, op1);
-
- /* Otherwise, keep this operation, but maybe change its operands.
-@@ -7991,7 +8002,7 @@
- if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
- return x;
-
-- /* We want to perform the operation is its present mode unless we know
-+ /* We want to perform the operation in its present mode unless we know
- that the operation is valid in MODE, in which case we do the operation
- in MODE. */
- op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
-@@ -8427,9 +8438,10 @@
- GET_MODE (x), GEN_INT (mask),
- XEXP (x, 1));
- if (temp && CONST_INT_P (temp))
-- SUBST (XEXP (x, 0),
-- force_to_mode (XEXP (x, 0), GET_MODE (x),
-- INTVAL (temp), next_select));
-+ x = simplify_gen_binary (code, GET_MODE (x),
-+ force_to_mode (XEXP (x, 0), GET_MODE (x),
-+ INTVAL (temp), next_select),
-+ XEXP (x, 1));
- }
- break;
-
-@@ -8497,14 +8509,16 @@
- /* We have no way of knowing if the IF_THEN_ELSE can itself be
- written in a narrower mode. We play it safe and do not do so. */
-
-- SUBST (XEXP (x, 1),
-- gen_lowpart_or_truncate (GET_MODE (x),
-- force_to_mode (XEXP (x, 1), mode,
-- mask, next_select)));
-- SUBST (XEXP (x, 2),
-- gen_lowpart_or_truncate (GET_MODE (x),
-- force_to_mode (XEXP (x, 2), mode,
-- mask, next_select)));
-+ op0 = gen_lowpart_or_truncate (GET_MODE (x),
-+ force_to_mode (XEXP (x, 1), mode,
-+ mask, next_select));
-+ op1 = gen_lowpart_or_truncate (GET_MODE (x),
-+ force_to_mode (XEXP (x, 2), mode,
-+ mask, next_select));
-+ if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
-+ x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x),
-+ GET_MODE (XEXP (x, 0)), XEXP (x, 0),
-+ op0, op1);
- break;
-
- default:
-Index: gcc/bb-reorder.c
-===================================================================
---- a/src/gcc/bb-reorder.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/bb-reorder.c (.../branches/gcc-4_8-branch)
-@@ -1685,9 +1685,8 @@
- edge e;
- edge_iterator ei;
-
-- /* Find EDGE_CAN_FALLTHRU edge. */
- FOR_EACH_EDGE (e, ei, cur_bb->succs)
-- if (e->flags & EDGE_CAN_FALLTHRU)
-+ if (e->flags & EDGE_FALLTHRU)
- {
- fall_thru = e;
- break;
-Index: gcc/tree-vect-generic.c
-===================================================================
---- a/src/gcc/tree-vect-generic.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-vect-generic.c (.../branches/gcc-4_8-branch)
-@@ -1006,7 +1006,8 @@
-
- if (!optimize
- || !VECTOR_INTEGER_TYPE_P (type)
-- || TREE_CODE (rhs2) != VECTOR_CST)
-+ || TREE_CODE (rhs2) != VECTOR_CST
-+ || !VECTOR_MODE_P (TYPE_MODE (type)))
- break;
-
- ret = expand_vector_divmod (gsi, type, rhs1, rhs2, code);
-Index: gcc/tree-flow.h
-===================================================================
---- a/src/gcc/tree-flow.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-flow.h (.../branches/gcc-4_8-branch)
-@@ -425,6 +425,7 @@
- basic_block, tree);
- void remove_edge_and_dominated_blocks (edge);
- bool tree_node_can_be_shared (tree);
-+extern unsigned int split_critical_edges (void);
-
- /* In tree-cfgcleanup.c */
- extern bitmap cfgcleanup_altered_bbs;
-Index: gcc/config.gcc
-===================================================================
---- a/src/gcc/config.gcc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config.gcc (.../branches/gcc-4_8-branch)
-@@ -420,7 +420,7 @@
- ;;
- powerpc*-*-*)
- cpu_type=rs6000
-- extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"
-+ extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"
- need_64bit_hwint=yes
- case x$with_cpu in
- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[345678]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500)
-@@ -1761,6 +1761,14 @@
- tmake_file="${tmake_file} microblaze/t-microblaze-linux"
- ;;
- microblaze*-*-rtems*)
-+ case $target in
-+ microblazeel-*)
-+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=0"
-+ ;;
-+ microblaze-*)
-+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=4321"
-+ ;;
-+ esac
- tm_file="${tm_file} dbxelf.h"
- tm_file="${tm_file} microblaze/rtems.h rtems.h newlib-stdint.h"
- c_target_objs="${c_target_objs} microblaze-c.o"
-@@ -2073,7 +2081,7 @@
- tmake_file="rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm"
- case ${target} in
- powerpc*le-*-*)
-- tm_file="${tm_file} rs6000/sysv4le.h" ;;
-+ tm_file="${tm_file} rs6000/sysv4le.h" ;;
- esac
- maybe_biarch=yes
- case ${target} in
-@@ -2096,6 +2104,19 @@
- fi
- tm_file="rs6000/biarch64.h ${tm_file} rs6000/linux64.h glibc-stdint.h"
- tmake_file="$tmake_file rs6000/t-linux64"
-+ case ${target} in
-+ powerpc*le-*-*)
-+ tmake_file="$tmake_file rs6000/t-linux64le"
-+ case ${enable_targets} in
-+ all | *powerpc64-* | *powerpc-*)
-+ tmake_file="$tmake_file rs6000/t-linux64lebe" ;;
-+ esac ;;
-+ *)
-+ case ${enable_targets} in
-+ all | *powerpc64le-* | *powerpcle-*)
-+ tmake_file="$tmake_file rs6000/t-linux64bele" ;;
-+ esac ;;
-+ esac
- extra_options="${extra_options} rs6000/linux64.opt"
- ;;
- *)
-@@ -2963,11 +2984,18 @@
- with_cpu=8540
- fi
- ;;
-- sparc-leon*-*)
-- with_cpu=v8;
-- ;;
- sparc*-*-*)
-- with_cpu="`echo ${target} | sed 's/-.*$//'`"
-+ case ${target} in
-+ *-leon-*)
-+ with_cpu=leon
-+ ;;
-+ *-leon[3-9]*)
-+ with_cpu=leon3
-+ ;;
-+ *)
-+ with_cpu="`echo ${target} | sed 's/-.*$//'`"
-+ ;;
-+ esac
- ;;
- esac
-
-@@ -3122,6 +3150,11 @@
- ${srcdir}/config/aarch64/$def | \
- sed -e 's/^[^,]*,[ ]*//' | \
- sed -e 's/,.*$//'`
-+ # Extract the architecture flags from aarch64-arches.def
-+ ext_mask=`grep "^$pattern(\"$base_val\"," \
-+ ${srcdir}/config/aarch64/$def | \
-+ sed -e 's/)$//' | \
-+ sed -e 's/^.*,//'`
- else
- base_id=`grep "^$pattern(\"$base_val\"," \
- ${srcdir}/config/aarch64/$def | \
-@@ -3494,7 +3527,7 @@
- ;;
-
- powerpc*-*-* | rs6000-*-*)
-- supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64"
-+ supported_defaults="abi cpu cpu_32 cpu_64 float tune tune_32 tune_64"
-
- for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do
- eval "val=\$with_$which"
-@@ -3531,6 +3564,16 @@
- ;;
- esac
- done
-+
-+ case "$with_abi" in
-+ "" | elfv1 | elfv2 )
-+ #OK
-+ ;;
-+ *)
-+ echo "Unknown ABI used in --with-abi=$with_abi"
-+ exit 1
-+ ;;
-+ esac
- ;;
-
- s390*-*-*)
-@@ -3587,7 +3630,7 @@
- case ${val} in
- "" | sparc | sparcv9 | sparc64 \
- | v7 | cypress \
-- | v8 | supersparc | hypersparc | leon \
-+ | v8 | supersparc | hypersparc | leon | leon3 \
- | sparclite | f930 | f934 | sparclite86x \
- | sparclet | tsc701 \
- | v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \
-@@ -3661,10 +3704,8 @@
- target_cpu_default2=
- case ${target} in
- aarch64*-*-*)
-- if test x$target_cpu_cname = x
-+ if test x"$target_cpu_cname" != x
- then
-- target_cpu_default2=TARGET_CPU_generic
-- else
- target_cpu_default2=$target_cpu_cname
- fi
- ;;
-@@ -3745,15 +3786,6 @@
- cxx_target_objs="${cxx_target_objs} sh-c.o"
- ;;
-
-- sparc-leon*-*)
-- if test x$with_tune = x ; then
-- with_tune=leon;
-- fi
--
-- # The SPARC port checks this value at compile-time.
-- target_cpu_default2="TARGET_CPU_$with_cpu"
-- ;;
--
- sparc*-*-*)
- # Some standard aliases.
- case x$with_cpu in
-@@ -3765,6 +3797,17 @@
- ;;
- esac
-
-+ if test x$with_tune = x ; then
-+ case ${target} in
-+ *-leon-*)
-+ with_tune=leon
-+ ;;
-+ *-leon[3-9]*)
-+ with_tune=leon3
-+ ;;
-+ esac
-+ fi
-+
- # The SPARC port checks this value at compile-time.
- target_cpu_default2="TARGET_CPU_$with_cpu"
- ;;
-Index: gcc/reginfo.c
-===================================================================
---- a/src/gcc/reginfo.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/reginfo.c (.../branches/gcc-4_8-branch)
-@@ -85,7 +85,7 @@
- char global_regs[FIRST_PSEUDO_REGISTER];
-
- /* Declaration for the global register. */
--static tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER];
-+tree global_regs_decl[FIRST_PSEUDO_REGISTER];
-
- /* Same information as REGS_INVALIDATED_BY_CALL but in regset form to be used
- in dataflow more conveniently. */
-@@ -620,40 +620,35 @@
- mode = GET_MODE_WIDER_MODE (mode))
- if ((unsigned) hard_regno_nregs[regno][mode] == nregs
- && HARD_REGNO_MODE_OK (regno, mode)
-- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
-+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
-+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))
- found_mode = mode;
-
-- if (found_mode != VOIDmode)
-- return found_mode;
--
- for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
- mode != VOIDmode;
- mode = GET_MODE_WIDER_MODE (mode))
- if ((unsigned) hard_regno_nregs[regno][mode] == nregs
- && HARD_REGNO_MODE_OK (regno, mode)
-- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
-+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
-+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))
- found_mode = mode;
-
-- if (found_mode != VOIDmode)
-- return found_mode;
--
- for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);
- mode != VOIDmode;
- mode = GET_MODE_WIDER_MODE (mode))
- if ((unsigned) hard_regno_nregs[regno][mode] == nregs
- && HARD_REGNO_MODE_OK (regno, mode)
-- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
-+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
-+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))
- found_mode = mode;
-
-- if (found_mode != VOIDmode)
-- return found_mode;
--
- for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);
- mode != VOIDmode;
- mode = GET_MODE_WIDER_MODE (mode))
- if ((unsigned) hard_regno_nregs[regno][mode] == nregs
- && HARD_REGNO_MODE_OK (regno, mode)
-- && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
-+ && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
-+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))
- found_mode = mode;
-
- if (found_mode != VOIDmode)
-Index: gcc/Makefile.in
-===================================================================
---- a/src/gcc/Makefile.in (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/Makefile.in (.../branches/gcc-4_8-branch)
-@@ -747,7 +747,8 @@
-
- # Native linker and preprocessor flags. For x-fragment overrides.
- BUILD_LDFLAGS=@BUILD_LDFLAGS@
--BUILD_CPPFLAGS=$(ALL_CPPFLAGS)
-+BUILD_CPPFLAGS= -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \
-+ -I$(srcdir)/../include @INCINTL@ $(CPPINC) $(CPPFLAGS)
-
- # Actual name to use when installing a native compiler.
- GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)')
-@@ -1827,7 +1828,7 @@
- "$(MULTILIB_EXCLUSIONS)" \
- "$(MULTILIB_OSDIRNAMES)" \
- "$(MULTILIB_REQUIRED)" \
-- "$(MULTIARCH_DIRNAME)" \
-+ "$(if $(MULTILIB_OSDIRNAMES),,$(MULTIARCH_DIRNAME))" \
- "$(MULTILIB_REUSE)" \
- "@enable_multilib@" \
- > tmp-mlib.h; \
-@@ -2256,7 +2257,7 @@
- $(FUNCTION_H) $(TM_H) coretypes.h \
- $(TREE_PASS_H) $(BASIC_BLOCK_H) $(BITMAP_H) \
- $(FLAGS_H) $(HASHTAB_H) pointer-set.h \
-- $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H)
-+ $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H) $(PARAMS_H)
- tree-ssa.o : tree-ssa.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \
- $(TREE_H) $(TM_P_H) $(EXPR_H) $(DIAGNOSTIC_H) \
- toplev.h $(FUNCTION_H) $(TM_H) coretypes.h \
-@@ -3037,7 +3038,7 @@
- $(TM_H) coretypes.h $(GIMPLE_H) \
- $(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) \
- $(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H) \
-- $(GIMPLE_PRETTY_PRINT_H) langhooks.h
-+ $(GIMPLE_PRETTY_PRINT_H) langhooks.h $(OPTABS_H)
- tree-complex.o : tree-complex.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \
- $(TM_H) $(FLAGS_H) $(TREE_FLOW_H) $(GIMPLE_H) \
- tree-iterator.h $(TREE_PASS_H) tree-ssa-propagate.h
-@@ -3276,12 +3277,12 @@
- $(TM_H) $(RTL_H) $(REGS_H) insn-config.h insn-codes.h $(DF_H) \
- $(RECOG_H) output.h addresses.h $(REGS_H) hard-reg-set.h $(FLAGS_H) \
- $(FUNCTION_H) $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) \
-- ira.h rtl-error.h $(LRA_INT_H)
-+ ira.h rtl-error.h $(LRA_INT_H) $(OPTABS_H)
- lra-eliminations.o : lra-eliminations.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
- $(TM_H) $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \
- $(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \
- $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) ira.h \
-- rtl-error.h $(LRA_INT_H)
-+ rtl-error.h $(LRA_INT_H) $(OPTABS_H)
- lra-lives.o : lra-lives.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
- $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \
- $(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \
-Index: gcc/gimple.c
-===================================================================
---- a/src/gcc/gimple.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/gimple.c (.../branches/gcc-4_8-branch)
-@@ -3841,42 +3841,46 @@
-
- /* For the statement STMT call the callbacks VISIT_LOAD, VISIT_STORE and
- VISIT_ADDR if non-NULL on loads, store and address-taken operands
-- passing the STMT, the base of the operand and DATA to it. The base
-- will be either a decl, an indirect reference (including TARGET_MEM_REF)
-- or the argument of an address expression.
-+ passing the STMT, the base of the operand, the operand itself containing
-+ the base and DATA to it. The base will be either a decl, an indirect
-+ reference (including TARGET_MEM_REF) or the argument of an address
-+ expression.
- Returns the results of these callbacks or'ed. */
-
- bool
- walk_stmt_load_store_addr_ops (gimple stmt, void *data,
-- bool (*visit_load)(gimple, tree, void *),
-- bool (*visit_store)(gimple, tree, void *),
-- bool (*visit_addr)(gimple, tree, void *))
-+ walk_stmt_load_store_addr_fn visit_load,
-+ walk_stmt_load_store_addr_fn visit_store,
-+ walk_stmt_load_store_addr_fn visit_addr)
- {
- bool ret = false;
- unsigned i;
- if (gimple_assign_single_p (stmt))
- {
-- tree lhs, rhs;
-+ tree lhs, rhs, arg;
- if (visit_store)
- {
-- lhs = get_base_loadstore (gimple_assign_lhs (stmt));
-+ arg = gimple_assign_lhs (stmt);
-+ lhs = get_base_loadstore (arg);
- if (lhs)
-- ret |= visit_store (stmt, lhs, data);
-+ ret |= visit_store (stmt, lhs, arg, data);
- }
-- rhs = gimple_assign_rhs1 (stmt);
-+ arg = gimple_assign_rhs1 (stmt);
-+ rhs = arg;
- while (handled_component_p (rhs))
- rhs = TREE_OPERAND (rhs, 0);
- if (visit_addr)
- {
- if (TREE_CODE (rhs) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data);
-+ ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), arg, data);
- else if (TREE_CODE (rhs) == TARGET_MEM_REF
- && TREE_CODE (TMR_BASE (rhs)) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), data);
-+ ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), arg,
-+ data);
- else if (TREE_CODE (rhs) == OBJ_TYPE_REF
- && TREE_CODE (OBJ_TYPE_REF_OBJECT (rhs)) == ADDR_EXPR)
- ret |= visit_addr (stmt, TREE_OPERAND (OBJ_TYPE_REF_OBJECT (rhs),
-- 0), data);
-+ 0), arg, data);
- else if (TREE_CODE (rhs) == CONSTRUCTOR)
- {
- unsigned int ix;
-@@ -3884,23 +3888,23 @@
-
- FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (rhs), ix, val)
- if (TREE_CODE (val) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (val, 0), data);
-+ ret |= visit_addr (stmt, TREE_OPERAND (val, 0), arg, data);
- else if (TREE_CODE (val) == OBJ_TYPE_REF
- && TREE_CODE (OBJ_TYPE_REF_OBJECT (val)) == ADDR_EXPR)
- ret |= visit_addr (stmt,
- TREE_OPERAND (OBJ_TYPE_REF_OBJECT (val),
-- 0), data);
-+ 0), arg, data);
- }
- lhs = gimple_assign_lhs (stmt);
- if (TREE_CODE (lhs) == TARGET_MEM_REF
- && TREE_CODE (TMR_BASE (lhs)) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), data);
-+ ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), lhs, data);
- }
- if (visit_load)
- {
- rhs = get_base_loadstore (rhs);
- if (rhs)
-- ret |= visit_load (stmt, rhs, data);
-+ ret |= visit_load (stmt, rhs, arg, data);
- }
- }
- else if (visit_addr
-@@ -3913,7 +3917,7 @@
- if (op == NULL_TREE)
- ;
- else if (TREE_CODE (op) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);
-+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);
- /* COND_EXPR and VCOND_EXPR rhs1 argument is a comparison
- tree with two operands. */
- else if (i == 1 && COMPARISON_CLASS_P (op))
-@@ -3920,10 +3924,10 @@
- {
- if (TREE_CODE (TREE_OPERAND (op, 0)) == ADDR_EXPR)
- ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 0),
-- 0), data);
-+ 0), op, data);
- if (TREE_CODE (TREE_OPERAND (op, 1)) == ADDR_EXPR)
- ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 1),
-- 0), data);
-+ 0), op, data);
- }
- }
- }
-@@ -3931,26 +3935,26 @@
- {
- if (visit_store)
- {
-- tree lhs = gimple_call_lhs (stmt);
-- if (lhs)
-+ tree arg = gimple_call_lhs (stmt);
-+ if (arg)
- {
-- lhs = get_base_loadstore (lhs);
-+ tree lhs = get_base_loadstore (arg);
- if (lhs)
-- ret |= visit_store (stmt, lhs, data);
-+ ret |= visit_store (stmt, lhs, arg, data);
- }
- }
- if (visit_load || visit_addr)
- for (i = 0; i < gimple_call_num_args (stmt); ++i)
- {
-- tree rhs = gimple_call_arg (stmt, i);
-+ tree arg = gimple_call_arg (stmt, i);
- if (visit_addr
-- && TREE_CODE (rhs) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data);
-+ && TREE_CODE (arg) == ADDR_EXPR)
-+ ret |= visit_addr (stmt, TREE_OPERAND (arg, 0), arg, data);
- else if (visit_load)
- {
-- rhs = get_base_loadstore (rhs);
-+ tree rhs = get_base_loadstore (arg);
- if (rhs)
-- ret |= visit_load (stmt, rhs, data);
-+ ret |= visit_load (stmt, rhs, arg, data);
- }
- }
- if (visit_addr
-@@ -3957,12 +3961,13 @@
- && gimple_call_chain (stmt)
- && TREE_CODE (gimple_call_chain (stmt)) == ADDR_EXPR)
- ret |= visit_addr (stmt, TREE_OPERAND (gimple_call_chain (stmt), 0),
-- data);
-+ gimple_call_chain (stmt), data);
- if (visit_addr
- && gimple_call_return_slot_opt_p (stmt)
- && gimple_call_lhs (stmt) != NULL_TREE
- && TREE_ADDRESSABLE (TREE_TYPE (gimple_call_lhs (stmt))))
-- ret |= visit_addr (stmt, gimple_call_lhs (stmt), data);
-+ ret |= visit_addr (stmt, gimple_call_lhs (stmt),
-+ gimple_call_lhs (stmt), data);
- }
- else if (gimple_code (stmt) == GIMPLE_ASM)
- {
-@@ -3978,7 +3983,7 @@
- tree link = gimple_asm_output_op (stmt, i);
- tree op = get_base_loadstore (TREE_VALUE (link));
- if (op && visit_store)
-- ret |= visit_store (stmt, op, data);
-+ ret |= visit_store (stmt, op, TREE_VALUE (link), data);
- if (visit_addr)
- {
- constraint = TREE_STRING_POINTER
-@@ -3987,7 +3992,7 @@
- parse_output_constraint (&constraint, i, 0, 0, &allows_mem,
- &allows_reg, &is_inout);
- if (op && !allows_reg && allows_mem)
-- ret |= visit_addr (stmt, op, data);
-+ ret |= visit_addr (stmt, op, TREE_VALUE (link), data);
- }
- }
- if (visit_load || visit_addr)
-@@ -3997,7 +4002,7 @@
- tree op = TREE_VALUE (link);
- if (visit_addr
- && TREE_CODE (op) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);
-+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);
- else if (visit_load || visit_addr)
- {
- op = get_base_loadstore (op);
-@@ -4004,7 +4009,7 @@
- if (op)
- {
- if (visit_load)
-- ret |= visit_load (stmt, op, data);
-+ ret |= visit_load (stmt, op, TREE_VALUE (link), data);
- if (visit_addr)
- {
- constraint = TREE_STRING_POINTER
-@@ -4013,7 +4018,8 @@
- 0, oconstraints,
- &allows_mem, &allows_reg);
- if (!allows_reg && allows_mem)
-- ret |= visit_addr (stmt, op, data);
-+ ret |= visit_addr (stmt, op, TREE_VALUE (link),
-+ data);
- }
- }
- }
-@@ -4026,12 +4032,12 @@
- {
- if (visit_addr
- && TREE_CODE (op) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);
-+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);
- else if (visit_load)
- {
-- op = get_base_loadstore (op);
-- if (op)
-- ret |= visit_load (stmt, op, data);
-+ tree base = get_base_loadstore (op);
-+ if (base)
-+ ret |= visit_load (stmt, base, op, data);
- }
- }
- }
-@@ -4042,7 +4048,7 @@
- {
- tree op = PHI_ARG_DEF (stmt, i);
- if (TREE_CODE (op) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);
-+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);
- }
- }
- else if (visit_addr
-@@ -4050,7 +4056,7 @@
- {
- tree op = gimple_goto_dest (stmt);
- if (TREE_CODE (op) == ADDR_EXPR)
-- ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data);
-+ ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data);
- }
-
- return ret;
-@@ -4061,8 +4067,8 @@
-
- bool
- walk_stmt_load_store_ops (gimple stmt, void *data,
-- bool (*visit_load)(gimple, tree, void *),
-- bool (*visit_store)(gimple, tree, void *))
-+ walk_stmt_load_store_addr_fn visit_load,
-+ walk_stmt_load_store_addr_fn visit_store)
- {
- return walk_stmt_load_store_addr_ops (stmt, data,
- visit_load, visit_store, NULL);
-@@ -4071,8 +4077,7 @@
- /* Helper for gimple_ior_addresses_taken_1. */
-
- static bool
--gimple_ior_addresses_taken_1 (gimple stmt ATTRIBUTE_UNUSED,
-- tree addr, void *data)
-+gimple_ior_addresses_taken_1 (gimple, tree addr, tree, void *data)
- {
- bitmap addresses_taken = (bitmap)data;
- addr = get_base_address (addr);
-Index: gcc/tree-ssa-structalias.c
-===================================================================
---- a/src/gcc/tree-ssa-structalias.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-structalias.c (.../branches/gcc-4_8-branch)
-@@ -949,24 +949,27 @@
- bitmap_set_bit (result, i);
- else
- {
-- unsigned HOST_WIDE_INT fieldoffset = vi->offset + offset;
-+ HOST_WIDE_INT fieldoffset = vi->offset + offset;
-+ unsigned HOST_WIDE_INT size = vi->size;
-
- /* If the offset makes the pointer point to before the
- variable use offset zero for the field lookup. */
-- if (offset < 0
-- && fieldoffset > vi->offset)
-- fieldoffset = 0;
--
-- if (offset != 0)
-+ if (fieldoffset < 0)
-+ vi = lookup_vi_for_tree (vi->decl);
-+ else
- vi = first_or_preceding_vi_for_offset (vi, fieldoffset);
-
-- bitmap_set_bit (result, vi->id);
-- /* If the result is not exactly at fieldoffset include the next
-- field as well. See get_constraint_for_ptr_offset for more
-- rationale. */
-- if (vi->offset != fieldoffset
-- && vi->next != NULL)
-- bitmap_set_bit (result, vi->next->id);
-+ do
-+ {
-+ bitmap_set_bit (result, vi->id);
-+ if (!vi->next)
-+ break;
-+
-+ /* We have to include all fields that overlap the current field
-+ shifted by offset. */
-+ vi = vi->next;
-+ }
-+ while (vi->offset < fieldoffset + size);
- }
- }
-
-@@ -1607,16 +1610,21 @@
- {
- varinfo_t v = get_varinfo (j);
- HOST_WIDE_INT fieldoffset = v->offset + roffset;
-+ unsigned HOST_WIDE_INT size = v->size;
- unsigned int t;
-
- if (v->is_full_var)
-- fieldoffset = v->offset;
-+ ;
- else if (roffset != 0)
-- v = first_vi_for_offset (v, fieldoffset);
-- /* If the access is outside of the variable we can ignore it. */
-- if (!v)
-- continue;
-+ {
-+ if (fieldoffset < 0)
-+ v = lookup_vi_for_tree (v->decl);
-+ else
-+ v = first_or_preceding_vi_for_offset (v, fieldoffset);
-+ }
-
-+ /* We have to include all fields that overlap the current field
-+ shifted by roffset. */
- do
- {
- t = find (v->id);
-@@ -1633,16 +1641,13 @@
- && add_graph_edge (graph, lhs, t))
- flag |= bitmap_ior_into (sol, get_varinfo (t)->solution);
-
-- /* If the variable is not exactly at the requested offset
-- we have to include the next one. */
-- if (v->offset == (unsigned HOST_WIDE_INT)fieldoffset
-+ if (v->is_full_var
- || v->next == NULL)
- break;
-
- v = v->next;
-- fieldoffset = v->offset;
- }
-- while (1);
-+ while (v->offset < fieldoffset + size);
- }
-
- done:
-@@ -1705,15 +1710,20 @@
- varinfo_t v = get_varinfo (j);
- unsigned int t;
- HOST_WIDE_INT fieldoffset = v->offset + loff;
-+ unsigned HOST_WIDE_INT size = v->size;
-
- if (v->is_full_var)
-- fieldoffset = v->offset;
-+ ;
- else if (loff != 0)
-- v = first_vi_for_offset (v, fieldoffset);
-- /* If the access is outside of the variable we can ignore it. */
-- if (!v)
-- continue;
-+ {
-+ if (fieldoffset < 0)
-+ v = lookup_vi_for_tree (v->decl);
-+ else
-+ v = first_or_preceding_vi_for_offset (v, fieldoffset);
-+ }
-
-+ /* We have to include all fields that overlap the current field
-+ shifted by loff. */
- do
- {
- if (v->may_have_pointers)
-@@ -1739,16 +1749,13 @@
- bitmap_set_bit (changed, t);
- }
-
-- /* If the variable is not exactly at the requested offset
-- we have to include the next one. */
-- if (v->offset == (unsigned HOST_WIDE_INT)fieldoffset
-+ if (v->is_full_var
- || v->next == NULL)
- break;
-
- v = v->next;
-- fieldoffset = v->offset;
- }
-- while (1);
-+ while (v->offset < fieldoffset + size);
- }
- }
-
-@@ -2997,35 +3004,30 @@
- varinfo_t temp;
- unsigned HOST_WIDE_INT offset = curr->offset + rhsoffset;
-
-- /* Search the sub-field which overlaps with the
-- pointed-to offset. If the result is outside of the variable
-- we have to provide a conservative result, as the variable is
-- still reachable from the resulting pointer (even though it
-- technically cannot point to anything). The last and first
-- sub-fields are such conservative results.
-- ??? If we always had a sub-field for &object + 1 then
-- we could represent this in a more precise way. */
-+ /* If curr->offset + rhsoffset is less than zero adjust it. */
- if (rhsoffset < 0
- && curr->offset < offset)
- offset = 0;
-+
-+ /* We have to include all fields that overlap the current
-+ field shifted by rhsoffset. And we include at least
-+ the last or the first field of the variable to represent
-+ reachability of off-bound addresses, in particular &object + 1,
-+ conservatively correct. */
- temp = first_or_preceding_vi_for_offset (curr, offset);
--
-- /* If the found variable is not exactly at the pointed to
-- result, we have to include the next variable in the
-- solution as well. Otherwise two increments by offset / 2
-- do not result in the same or a conservative superset
-- solution. */
-- if (temp->offset != offset
-- && temp->next != NULL)
-+ c.var = temp->id;
-+ c.offset = 0;
-+ temp = temp->next;
-+ while (temp
-+ && temp->offset < offset + curr->size)
- {
- struct constraint_expr c2;
-- c2.var = temp->next->id;
-+ c2.var = temp->id;
- c2.type = ADDRESSOF;
- c2.offset = 0;
- results->safe_push (c2);
-+ temp = temp->next;
- }
-- c.var = temp->id;
-- c.offset = 0;
- }
- else
- c.offset = rhsoffset;
-Index: gcc/gimple.h
-===================================================================
---- a/src/gcc/gimple.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/gimple.h (.../branches/gcc-4_8-branch)
-@@ -176,6 +176,9 @@
- /* Nonzero if this statement contains volatile operands. */
- unsigned has_volatile_ops : 1;
-
-+ /* Padding to get subcode to 16 bit alignment. */
-+ unsigned pad : 1;
-+
- /* The SUBCODE field can be used for tuple-specific flags for tuples
- that do not require subcodes. Note that SUBCODE should be at
- least as wide as tree codes, as several tuples store tree codes
-@@ -888,13 +891,14 @@
- extern alias_set_type gimple_get_alias_set (tree);
- extern void count_uses_and_derefs (tree, gimple, unsigned *, unsigned *,
- unsigned *);
-+typedef bool (*walk_stmt_load_store_addr_fn) (gimple, tree, tree, void *);
- extern bool walk_stmt_load_store_addr_ops (gimple, void *,
-- bool (*)(gimple, tree, void *),
-- bool (*)(gimple, tree, void *),
-- bool (*)(gimple, tree, void *));
-+ walk_stmt_load_store_addr_fn,
-+ walk_stmt_load_store_addr_fn,
-+ walk_stmt_load_store_addr_fn);
- extern bool walk_stmt_load_store_ops (gimple, void *,
-- bool (*)(gimple, tree, void *),
-- bool (*)(gimple, tree, void *));
-+ walk_stmt_load_store_addr_fn,
-+ walk_stmt_load_store_addr_fn);
- extern bool gimple_ior_addresses_taken (bitmap, gimple);
- extern bool gimple_call_builtin_p (gimple, enum built_in_class);
- extern bool gimple_call_builtin_p (gimple, enum built_in_function);
-Index: gcc/tree-cfg.c
-===================================================================
---- a/src/gcc/tree-cfg.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-cfg.c (.../branches/gcc-4_8-branch)
-@@ -104,7 +104,6 @@
- static void assign_discriminator (location_t, basic_block);
- static edge gimple_redirect_edge_and_branch (edge, basic_block);
- static edge gimple_try_redirect_by_replacing_jump (edge, basic_block);
--static unsigned int split_critical_edges (void);
-
- /* Various helpers. */
- static inline bool stmt_starts_bb_p (gimple, gimple);
-@@ -1535,6 +1534,11 @@
-
- FOR_EACH_IMM_USE_STMT (stmt, imm_iter, name)
- {
-+ /* Mark the block if we change the last stmt in it. */
-+ if (cfgcleanup_altered_bbs
-+ && stmt_ends_bb_p (stmt))
-+ bitmap_set_bit (cfgcleanup_altered_bbs, gimple_bb (stmt)->index);
-+
- FOR_EACH_IMM_USE_ON_STMT (use, imm_iter)
- {
- replace_exp (use, val);
-@@ -1559,11 +1563,6 @@
- gimple orig_stmt = stmt;
- size_t i;
-
-- /* Mark the block if we changed the last stmt in it. */
-- if (cfgcleanup_altered_bbs
-- && stmt_ends_bb_p (stmt))
-- bitmap_set_bit (cfgcleanup_altered_bbs, gimple_bb (stmt)->index);
--
- /* FIXME. It shouldn't be required to keep TREE_CONSTANT
- on ADDR_EXPRs up-to-date on GIMPLE. Propagation will
- only change sth from non-invariant to invariant, and only
-@@ -3513,11 +3512,10 @@
- case PLUS_EXPR:
- case MINUS_EXPR:
- {
-- /* We use regular PLUS_EXPR and MINUS_EXPR for vectors.
-- ??? This just makes the checker happy and may not be what is
-- intended. */
-- if (TREE_CODE (lhs_type) == VECTOR_TYPE
-- && POINTER_TYPE_P (TREE_TYPE (lhs_type)))
-+ tree lhs_etype = lhs_type;
-+ tree rhs1_etype = rhs1_type;
-+ tree rhs2_etype = rhs2_type;
-+ if (TREE_CODE (lhs_type) == VECTOR_TYPE)
- {
- if (TREE_CODE (rhs1_type) != VECTOR_TYPE
- || TREE_CODE (rhs2_type) != VECTOR_TYPE)
-@@ -3525,22 +3523,13 @@
- error ("invalid non-vector operands to vector valued plus");
- return true;
- }
-- lhs_type = TREE_TYPE (lhs_type);
-- rhs1_type = TREE_TYPE (rhs1_type);
-- rhs2_type = TREE_TYPE (rhs2_type);
-- /* PLUS_EXPR is commutative, so we might end up canonicalizing
-- the pointer to 2nd place. */
-- if (POINTER_TYPE_P (rhs2_type))
-- {
-- tree tem = rhs1_type;
-- rhs1_type = rhs2_type;
-- rhs2_type = tem;
-- }
-- goto do_pointer_plus_expr_check;
-+ lhs_etype = TREE_TYPE (lhs_type);
-+ rhs1_etype = TREE_TYPE (rhs1_type);
-+ rhs2_etype = TREE_TYPE (rhs2_type);
- }
-- if (POINTER_TYPE_P (lhs_type)
-- || POINTER_TYPE_P (rhs1_type)
-- || POINTER_TYPE_P (rhs2_type))
-+ if (POINTER_TYPE_P (lhs_etype)
-+ || POINTER_TYPE_P (rhs1_etype)
-+ || POINTER_TYPE_P (rhs2_etype))
- {
- error ("invalid (pointer) operands to plus/minus");
- return true;
-@@ -3552,7 +3541,6 @@
-
- case POINTER_PLUS_EXPR:
- {
--do_pointer_plus_expr_check:
- if (!POINTER_TYPE_P (rhs1_type)
- || !useless_type_conversion_p (lhs_type, rhs1_type)
- || !ptrofftype_p (rhs2_type))
-@@ -7658,7 +7646,7 @@
-
- /* Split all critical edges. */
-
--static unsigned int
-+unsigned int
- split_critical_edges (void)
- {
- basic_block bb;
-Index: gcc/passes.c
-===================================================================
---- a/src/gcc/passes.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/passes.c (.../branches/gcc-4_8-branch)
-@@ -1398,6 +1398,7 @@
- /* After CCP we rewrite no longer addressed locals into SSA
- form if possible. */
- NEXT_PASS (pass_forwprop);
-+ NEXT_PASS (pass_object_sizes);
- /* pass_build_alias is a dummy pass that ensures that we
- execute TODO_rebuild_alias at this point. */
- NEXT_PASS (pass_build_alias);
-@@ -1435,7 +1436,6 @@
- NEXT_PASS (pass_dce);
- NEXT_PASS (pass_forwprop);
- NEXT_PASS (pass_phiopt);
-- NEXT_PASS (pass_object_sizes);
- NEXT_PASS (pass_strlen);
- NEXT_PASS (pass_ccp);
- /* After CCP we rewrite no longer addressed locals into SSA
-Index: gcc/tree-ssa-reassoc.c
-===================================================================
---- a/src/gcc/tree-ssa-reassoc.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-reassoc.c (.../branches/gcc-4_8-branch)
-@@ -785,8 +785,7 @@
- if (opcode == BIT_AND_EXPR)
- oe->op = build_zero_cst (TREE_TYPE (oe->op));
- else if (opcode == BIT_IOR_EXPR)
-- oe->op = build_low_bits_mask (TREE_TYPE (oe->op),
-- TYPE_PRECISION (TREE_TYPE (oe->op)));
-+ oe->op = build_all_ones_cst (TREE_TYPE (oe->op));
-
- reassociate_stats.ops_eliminated += ops->length () - 1;
- ops->truncate (0);
-@@ -1980,8 +1979,15 @@
-
- tem = fold_convert_loc (loc, optype, tem);
- gsi = gsi_for_stmt (stmt);
-- tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, true,
-- GSI_SAME_STMT);
-+ /* In rare cases range->exp can be equal to lhs of stmt.
-+ In that case we have to insert after the stmt rather then before
-+ it. */
-+ if (op == range->exp)
-+ tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, false,
-+ GSI_SAME_STMT);
-+ else
-+ tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, true,
-+ GSI_SAME_STMT);
-
- /* If doing inter-bb range test optimization, update the
- stmts immediately. Start with changing the first range test
-Index: gcc/config/s390/s390.c
-===================================================================
---- a/src/gcc/config/s390/s390.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/s390/s390.c (.../branches/gcc-4_8-branch)
-@@ -407,6 +407,65 @@
- bytes on a z10 (or higher) CPU. */
- #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
-
-+static const int s390_hotpatch_trampoline_halfwords_default = 12;
-+static const int s390_hotpatch_trampoline_halfwords_max = 1000000;
-+static int s390_hotpatch_trampoline_halfwords = -1;
-+
-+/* Return the argument of the given hotpatch attribute or the default value if
-+ no argument is present. */
-+
-+static inline int
-+get_hotpatch_attribute (tree hotpatch_attr)
-+{
-+ const_tree args;
-+
-+ args = TREE_VALUE (hotpatch_attr);
-+
-+ return (args) ?
-+ TREE_INT_CST_LOW (TREE_VALUE (args)):
-+ s390_hotpatch_trampoline_halfwords_default;
-+}
-+
-+/* Check whether the hotpatch attribute is applied to a function and, if it has
-+ an argument, the argument is valid. */
-+
-+static tree
-+s390_handle_hotpatch_attribute (tree *node, tree name, tree args,
-+ int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
-+{
-+ if (TREE_CODE (*node) != FUNCTION_DECL)
-+ {
-+ warning (OPT_Wattributes, "%qE attribute only applies to functions",
-+ name);
-+ *no_add_attrs = true;
-+ }
-+ else if (args)
-+ {
-+ tree expr = TREE_VALUE (args);
-+
-+ if (TREE_CODE (expr) != INTEGER_CST
-+ || !INTEGRAL_TYPE_P (TREE_TYPE (expr))
-+ || TREE_INT_CST_HIGH (expr) != 0
-+ || TREE_INT_CST_LOW (expr) > (unsigned int)
-+ s390_hotpatch_trampoline_halfwords_max)
-+ {
-+ error ("requested %qE attribute is not a non-negative integer"
-+ " constant or too large (max. %d)", name,
-+ s390_hotpatch_trampoline_halfwords_max);
-+ *no_add_attrs = true;
-+ }
-+ }
-+
-+ return NULL_TREE;
-+}
-+
-+static const struct attribute_spec s390_attribute_table[] = {
-+ { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute, false
-+ },
-+ /* End element. */
-+ { NULL, 0, 0, false, false, false, NULL, false }
-+};
-+
- /* Return the alignment for LABEL. We default to the -falign-labels
- value except for the literal pool base label. */
- int
-@@ -883,7 +942,8 @@
- {
- /* For CCRAWmode put the required cc mask into the second
- operand. */
-- if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode)
-+ if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode
-+ && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3)
- *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));
- *op0 = XVECEXP (*op0, 0, 0);
- *code = new_code;
-@@ -1594,6 +1654,46 @@
- static void
- s390_option_override (void)
- {
-+ unsigned int i;
-+ cl_deferred_option *opt;
-+ vec<cl_deferred_option> *v =
-+ (vec<cl_deferred_option> *) s390_deferred_options;
-+
-+ if (v)
-+ FOR_EACH_VEC_ELT (*v, i, opt)
-+ {
-+ switch (opt->opt_index)
-+ {
-+ case OPT_mhotpatch:
-+ s390_hotpatch_trampoline_halfwords = (opt->value) ?
-+ s390_hotpatch_trampoline_halfwords_default : -1;
-+ break;
-+ case OPT_mhotpatch_:
-+ {
-+ int val;
-+
-+ val = integral_argument (opt->arg);
-+ if (val == -1)
-+ {
-+ /* argument is not a plain number */
-+ error ("argument to %qs should be a non-negative integer",
-+ "-mhotpatch=");
-+ break;
-+ }
-+ else if (val > s390_hotpatch_trampoline_halfwords_max)
-+ {
-+ error ("argument to %qs is too large (max. %d)",
-+ "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max);
-+ break;
-+ }
-+ s390_hotpatch_trampoline_halfwords = val;
-+ break;
-+ }
-+ default:
-+ gcc_unreachable ();
-+ }
-+ }
-+
- /* Set up function hooks. */
- init_machine_status = s390_init_machine_status;
-
-@@ -3015,15 +3115,22 @@
- prefer ADDR_REGS. If 'class' is not a superset
- of ADDR_REGS, e.g. FP_REGS, reject this reload. */
- case CONST:
-- /* A larl operand with odd addend will get fixed via secondary
-- reload. So don't request it to be pushed into literal
-- pool. */
-+ /* Symrefs cannot be pushed into the literal pool with -fPIC
-+ so we *MUST NOT* return NO_REGS for these cases
-+ (s390_cannot_force_const_mem will return true).
-+
-+ On the other hand we MUST return NO_REGS for symrefs with
-+ invalid addend which might have been pushed to the literal
-+ pool (no -fPIC). Usually we would expect them to be
-+ handled via secondary reload but this does not happen if
-+ they are used as literal pool slot replacement in reload
-+ inheritance (see emit_input_reload_insns). */
- if (TARGET_CPU_ZARCH
- && GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
- && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
- {
-- if (reg_class_subset_p (ADDR_REGS, rclass))
-+ if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))
- return ADDR_REGS;
- else
- return NO_REGS;
-@@ -4683,7 +4790,7 @@
- int smode_bsize, mode_bsize;
- rtx op, clobber;
-
-- if (bitsize + bitpos > GET_MODE_SIZE (mode))
-+ if (bitsize + bitpos > GET_MODE_BITSIZE (mode))
- return false;
-
- /* Generate INSERT IMMEDIATE (IILL et al). */
-@@ -5311,6 +5418,101 @@
- gcc_unreachable ();
- }
-
-+/* Returns -1 if the function should not be made hotpatchable. Otherwise it
-+ returns a number >= 0 that is the desired size of the hotpatch trampoline
-+ in halfwords. */
-+
-+static int s390_function_num_hotpatch_trampoline_halfwords (tree decl,
-+ bool do_warn)
-+{
-+ tree attr;
-+
-+ if (DECL_DECLARED_INLINE_P (decl)
-+ || DECL_ARTIFICIAL (decl)
-+ || MAIN_NAME_P (DECL_NAME (decl)))
-+ {
-+ /* - Explicitly inlined functions cannot be hotpatched.
-+ - Artificial functions need not be hotpatched.
-+ - Making the main function hotpatchable is useless. */
-+ return -1;
-+ }
-+ attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl));
-+ if (attr || s390_hotpatch_trampoline_halfwords >= 0)
-+ {
-+ if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl)))
-+ {
-+ if (do_warn)
-+ warning (OPT_Wattributes, "function %qE with the %qs attribute"
-+ " is not hotpatchable", DECL_NAME (decl), "always_inline");
-+ return -1;
-+ }
-+ else
-+ {
-+ return (attr) ?
-+ get_hotpatch_attribute (attr) : s390_hotpatch_trampoline_halfwords;
-+ }
-+ }
-+
-+ return -1;
-+}
-+
-+/* Hook to determine if one function can safely inline another. */
-+
-+static bool
-+s390_can_inline_p (tree caller, tree callee)
-+{
-+ if (s390_function_num_hotpatch_trampoline_halfwords (callee, false) >= 0)
-+ return false;
-+
-+ return default_target_can_inline_p (caller, callee);
-+}
-+
-+/* Write the extra assembler code needed to declare a function properly. */
-+
-+void
-+s390_asm_output_function_label (FILE *asm_out_file, const char *fname,
-+ tree decl)
-+{
-+ int hotpatch_trampoline_halfwords = -1;
-+
-+ if (decl)
-+ {
-+ hotpatch_trampoline_halfwords =
-+ s390_function_num_hotpatch_trampoline_halfwords (decl, true);
-+ if (hotpatch_trampoline_halfwords >= 0
-+ && decl_function_context (decl) != NULL_TREE)
-+ {
-+ warning_at (DECL_SOURCE_LOCATION (decl), OPT_mhotpatch,
-+ "hotpatching is not compatible with nested functions");
-+ hotpatch_trampoline_halfwords = -1;
-+ }
-+ }
-+
-+ if (hotpatch_trampoline_halfwords > 0)
-+ {
-+ int i;
-+
-+ /* Add a trampoline code area before the function label and initialize it
-+ with two-byte nop instructions. This area can be overwritten with code
-+ that jumps to a patched version of the function. */
-+ for (i = 0; i < hotpatch_trampoline_halfwords; i++)
-+ asm_fprintf (asm_out_file, "\tnopr\t%%r7\n");
-+ /* Note: The function label must be aligned so that (a) the bytes of the
-+ following nop do not cross a cacheline boundary, and (b) a jump address
-+ (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
-+ stored directly before the label without crossing a cacheline
-+ boundary. All this is necessary to make sure the trampoline code can
-+ be changed atomically. */
-+ }
-+
-+ ASM_OUTPUT_LABEL (asm_out_file, fname);
-+
-+ /* Output a four-byte nop if hotpatching is enabled. This can be overwritten
-+ atomically with a relative backwards jump to the trampoline area. */
-+ if (hotpatch_trampoline_halfwords >= 0)
-+ asm_fprintf (asm_out_file, "\tnop\t0\n");
-+}
-+
- /* Output machine-dependent UNSPECs occurring in address constant X
- in assembler syntax to stdio stream FILE. Returns true if the
- constant X could be recognized, false otherwise. */
-@@ -7846,6 +8048,9 @@
- {
- bb = BASIC_BLOCK (bb_index);
-
-+ if (!bb)
-+ continue;
-+
- FOR_BB_INSNS (bb, insn)
- {
- rtx ite, cc, pat, target;
-@@ -7959,7 +8164,10 @@
- if (!result)
- return;
-
-- PATTERN (tbegin_insn) = XVECEXP (PATTERN (tbegin_insn), 0, 0);
-+ PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode,
-+ gen_rtvec (2,
-+ XVECEXP (PATTERN (tbegin_insn), 0, 0),
-+ XVECEXP (PATTERN (tbegin_insn), 0, 1)));
- INSN_CODE (tbegin_insn) = -1;
- df_insn_rescan (tbegin_insn);
-
-@@ -9568,61 +9776,47 @@
- void
- s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)
- {
-- const int CC0 = 1 << 3;
-- const int CC1 = 1 << 2;
-- const int CC3 = 1 << 0;
-- rtx abort_label = gen_label_rtx ();
-- rtx leave_label = gen_label_rtx ();
-+ rtx retry_plus_two = gen_reg_rtx (SImode);
- rtx retry_reg = gen_reg_rtx (SImode);
- rtx retry_label = NULL_RTX;
-- rtx jump;
-- rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
-
- if (retry != NULL_RTX)
- {
- emit_move_insn (retry_reg, retry);
-+ emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx));
-+ emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx));
- retry_label = gen_label_rtx ();
- emit_label (retry_label);
- }
-
- if (clobber_fprs_p)
-- emit_insn (gen_tbegin_1 (tdb,
-- gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK)));
-+ emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));
- else
-- emit_insn (gen_tbegin_nofloat_1 (tdb,
-- gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK)));
-+ emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
-+ tdb));
-
-- jump = s390_emit_jump (abort_label,
-- gen_rtx_NE (VOIDmode,
-- gen_rtx_REG (CCRAWmode, CC_REGNUM),
-- gen_rtx_CONST_INT (VOIDmode, CC0)));
--
-- JUMP_LABEL (jump) = abort_label;
-- LABEL_NUSES (abort_label) = 1;
-- add_reg_note (jump, REG_BR_PROB, very_unlikely);
--
-- /* Initialize CC return value. */
-- emit_move_insn (dest, const0_rtx);
--
-- s390_emit_jump (leave_label, NULL_RTX);
-- LABEL_NUSES (leave_label) = 1;
-- emit_barrier ();
--
-- /* Abort handler code. */
--
-- emit_label (abort_label);
-+ emit_move_insn (dest, gen_rtx_UNSPEC (SImode,
-+ gen_rtvec (1, gen_rtx_REG (CCRAWmode,
-+ CC_REGNUM)),
-+ UNSPEC_CC_TO_INT));
- if (retry != NULL_RTX)
- {
-+ const int CC0 = 1 << 3;
-+ const int CC1 = 1 << 2;
-+ const int CC3 = 1 << 0;
-+ rtx jump;
- rtx count = gen_reg_rtx (SImode);
-+ rtx leave_label = gen_label_rtx ();
-+
-+ /* Exit for success and permanent failures. */
- jump = s390_emit_jump (leave_label,
- gen_rtx_EQ (VOIDmode,
- gen_rtx_REG (CCRAWmode, CC_REGNUM),
-- gen_rtx_CONST_INT (VOIDmode, CC1 | CC3)));
-- LABEL_NUSES (leave_label) = 2;
-- add_reg_note (jump, REG_BR_PROB, very_unlikely);
-+ gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3)));
-+ LABEL_NUSES (leave_label) = 1;
-
- /* CC2 - transient failure. Perform retry with ppa. */
-- emit_move_insn (count, retry);
-+ emit_move_insn (count, retry_plus_two);
- emit_insn (gen_subsi3 (count, count, retry_reg));
- emit_insn (gen_tx_assist (count));
- jump = emit_jump_insn (gen_doloop_si64 (retry_label,
-@@ -9630,13 +9824,8 @@
- retry_reg));
- JUMP_LABEL (jump) = retry_label;
- LABEL_NUSES (retry_label) = 1;
-+ emit_label (leave_label);
- }
--
-- emit_move_insn (dest, gen_rtx_UNSPEC (SImode,
-- gen_rtvec (1, gen_rtx_REG (CCRAWmode,
-- CC_REGNUM)),
-- UNSPEC_CC_TO_INT));
-- emit_label (leave_label);
- }
-
- /* Builtins. */
-@@ -9674,6 +9863,9 @@
- s390_init_builtins (void)
- {
- tree ftype, uint64_type;
-+ tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"),
-+ NULL, NULL);
-+ tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL);
-
- /* void foo (void) */
- ftype = build_function_type_list (void_type_node, NULL_TREE);
-@@ -9684,7 +9876,7 @@
- ftype = build_function_type_list (void_type_node, integer_type_node,
- NULL_TREE);
- add_builtin_function ("__builtin_tabort", ftype,
-- S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, NULL_TREE);
-+ S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr);
- add_builtin_function ("__builtin_tx_assist", ftype,
- S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);
-
-@@ -9691,10 +9883,10 @@
- /* int foo (void *) */
- ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);
- add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,
-- BUILT_IN_MD, NULL, NULL_TREE);
-+ BUILT_IN_MD, NULL, returns_twice_attr);
- add_builtin_function ("__builtin_tbegin_nofloat", ftype,
- S390_BUILTIN_TBEGIN_NOFLOAT,
-- BUILT_IN_MD, NULL, NULL_TREE);
-+ BUILT_IN_MD, NULL, returns_twice_attr);
-
- /* int foo (void *, int) */
- ftype = build_function_type_list (integer_type_node, ptr_type_node,
-@@ -9702,11 +9894,11 @@
- add_builtin_function ("__builtin_tbegin_retry", ftype,
- S390_BUILTIN_TBEGIN_RETRY,
- BUILT_IN_MD,
-- NULL, NULL_TREE);
-+ NULL, returns_twice_attr);
- add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,
- S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
- BUILT_IN_MD,
-- NULL, NULL_TREE);
-+ NULL, returns_twice_attr);
-
- /* int foo (void) */
- ftype = build_function_type_list (integer_type_node, NULL_TREE);
-@@ -11622,6 +11814,12 @@
- #undef TARGET_CANONICALIZE_COMPARISON
- #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
-
-+#undef TARGET_ATTRIBUTE_TABLE
-+#define TARGET_ATTRIBUTE_TABLE s390_attribute_table
-+
-+#undef TARGET_CAN_INLINE_P
-+#define TARGET_CAN_INLINE_P s390_can_inline_p
-+
- struct gcc_target targetm = TARGET_INITIALIZER;
-
- #include "gt-s390.h"
-Index: gcc/config/s390/s390.h
-===================================================================
---- a/src/gcc/config/s390/s390.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/s390/s390.h (.../branches/gcc-4_8-branch)
-@@ -217,7 +217,7 @@
- #define STACK_BOUNDARY 64
-
- /* Allocation boundary (in *bits*) for the code of a function. */
--#define FUNCTION_BOUNDARY 32
-+#define FUNCTION_BOUNDARY 64
-
- /* There is no point aligning anything to a rounder boundary than this. */
- #define BIGGEST_ALIGNMENT 64
-@@ -878,6 +878,9 @@
- fputc ('\n', (FILE)); \
- } while (0)
-
-+#undef ASM_OUTPUT_FUNCTION_LABEL
-+#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
-+ s390_asm_output_function_label (FILE, NAME, DECL)
-
- /* Miscellaneous parameters. */
-
-Index: gcc/config/s390/s390.md
-===================================================================
---- a/src/gcc/config/s390/s390.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/s390/s390.md (.../branches/gcc-4_8-branch)
-@@ -147,6 +147,7 @@
-
- ; Transactional Execution support
- UNSPECV_TBEGIN
-+ UNSPECV_TBEGIN_TDB
- UNSPECV_TBEGINC
- UNSPECV_TEND
- UNSPECV_TABORT
-@@ -9896,9 +9897,10 @@
-
- (define_insn "tbegin_1"
- [(set (reg:CCRAW CC_REGNUM)
-- (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")
-- (match_operand 1 "const_int_operand" " D")]
-+ (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
- UNSPECV_TBEGIN))
-+ (set (match_operand:BLK 1 "memory_operand" "=Q")
-+ (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
- (clobber (reg:DF 16))
- (clobber (reg:DF 17))
- (clobber (reg:DF 18))
-@@ -9917,18 +9919,19 @@
- (clobber (reg:DF 31))]
- ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
- ; not supposed to be used for immediates (see genpreds.c).
-- "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"
-- "tbegin\t%0,%x1"
-+ "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
-+ "tbegin\t%1,%x0"
- [(set_attr "op_type" "SIL")])
-
- ; Same as above but without the FPR clobbers
- (define_insn "tbegin_nofloat_1"
- [(set (reg:CCRAW CC_REGNUM)
-- (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")
-- (match_operand 1 "const_int_operand" " D")]
-- UNSPECV_TBEGIN))]
-- "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"
-- "tbegin\t%0,%x1"
-+ (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
-+ UNSPECV_TBEGIN))
-+ (set (match_operand:BLK 1 "memory_operand" "=Q")
-+ (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
-+ "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
-+ "tbegin\t%1,%x0"
- [(set_attr "op_type" "SIL")])
-
-
-@@ -10012,15 +10015,12 @@
- ; Transaction perform processor assist
-
- (define_expand "tx_assist"
-- [(set (match_dup 1) (const_int 0))
-- (unspec_volatile [(match_operand:SI 0 "register_operand" "")
-- (match_dup 1)
-+ [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
-+ (reg:SI GPR0_REGNUM)
- (const_int 1)]
- UNSPECV_PPA)]
- "TARGET_HTM"
--{
-- operands[1] = gen_reg_rtx (SImode);
--})
-+ "")
-
- (define_insn "*ppa"
- [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
-@@ -10028,5 +10028,5 @@
- (match_operand 2 "const_int_operand" "I")]
- UNSPECV_PPA)]
- "TARGET_HTM && INTVAL (operands[2]) < 16"
-- "ppa\t%0,%1,1"
-+ "ppa\t%0,%1,%2"
- [(set_attr "op_type" "RRF")])
-Index: gcc/config/s390/s390.opt
-===================================================================
---- a/src/gcc/config/s390/s390.opt (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/s390/s390.opt (.../branches/gcc-4_8-branch)
-@@ -96,6 +96,14 @@
- Target Report RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT)
- Enable hardware floating point
-
-+mhotpatch
-+Target Report Var(s390_deferred_options) Defer
-+Prepend the function label with 12 two-byte Nop instructions, and add a four byte Nop instruction after the label for hotpatching.
-+
-+mhotpatch=
-+Target RejectNegative Report Joined Var(s390_deferred_options) Defer
-+Prepend the function label with the given number of two-byte Nop instructions, and add a four byte Nop instruction after the label for hotpatching.
-+
- mlong-double-128
- Target Report RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128)
- Use 128-bit long double
-Index: gcc/config/s390/htmxlintrin.h
-===================================================================
---- a/src/gcc/config/s390/htmxlintrin.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/s390/htmxlintrin.h (.../branches/gcc-4_8-branch)
-@@ -33,13 +33,20 @@
- the IBM XL compiler. For documentation please see the "z/OS XL
- C/C++ Programming Guide" publically available on the web. */
-
--extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-+/* FIXME: __TM_simple_begin and __TM_begin should be marked
-+ __always_inline__ as well but this currently produces an error
-+ since the tbegin builtins are "returns_twice" and setjmp_call_p
-+ (calls.c) therefore identifies the functions as calling setjmp.
-+ The tree inliner currently refuses to inline functions calling
-+ setjmp. */
-+
-+long
- __TM_simple_begin ()
- {
- return __builtin_tbegin_nofloat (0);
- }
-
--extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-+long
- __TM_begin (void* const tdb)
- {
- return __builtin_tbegin_nofloat (tdb);
-@@ -78,7 +85,7 @@
- if (depth != 0)
- return depth;
-
-- if (tdb->format == 0)
-+ if (tdb->format != 1)
- return 0;
- return tdb->nesting_depth;
- }
-@@ -90,7 +97,7 @@
- {
- struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;
-
-- if (tdb->format == 0)
-+ if (tdb->format != 1)
- return 0;
-
- return !!(tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE);
-@@ -101,7 +108,7 @@
- {
- struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;
-
-- if (tdb->format == 0)
-+ if (tdb->format != 1)
- return 0;
-
- if (tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE)
-@@ -117,7 +124,7 @@
- {
- struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;
-
-- return (tdb->format == 0
-+ return (tdb->format == 1
- && (tdb->abort_code == 4 /* unfiltered program interruption */
- || tdb->abort_code == 11 /* restricted instruction */));
- }
-@@ -127,7 +134,7 @@
- {
- struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;
-
-- return (tdb->format == 0
-+ return (tdb->format == 1
- && (tdb->abort_code == 7 /* fetch overflow */
- || tdb->abort_code == 8 /* store overflow */));
- }
-@@ -137,7 +144,7 @@
- {
- struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;
-
-- return tdb->format == 0 && tdb->abort_code == 13; /* depth exceeded */
-+ return tdb->format == 1 && tdb->abort_code == 13; /* depth exceeded */
- }
-
- extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-@@ -145,7 +152,7 @@
- {
- struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr;
-
-- return (tdb->format == 0
-+ return (tdb->format == 1
- && (tdb->abort_code == 9 /* fetch conflict */
- || tdb->abort_code == 10 /* store conflict */));
- }
-Index: gcc/config/s390/s390-protos.h
-===================================================================
---- a/src/gcc/config/s390/s390-protos.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/s390/s390-protos.h (.../branches/gcc-4_8-branch)
-@@ -110,5 +110,6 @@
- extern int s390_branch_condition_mask (rtx);
- extern int s390_compare_and_branch_condition_mask (rtx);
- extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT);
-+extern void s390_asm_output_function_label (FILE *, const char *, tree);
-
- #endif /* RTX_CODE */
-Index: gcc/config/sparc/t-rtems
-===================================================================
---- a/src/gcc/config/sparc/t-rtems (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/t-rtems (.../branches/gcc-4_8-branch)
-@@ -17,6 +17,6 @@
- # <http://www.gnu.org/licenses/>.
- #
-
--MULTILIB_OPTIONS = msoft-float mcpu=v8
--MULTILIB_DIRNAMES = soft v8
-+MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3
-+MULTILIB_DIRNAMES = soft v8 leon3
- MULTILIB_MATCHES = msoft-float=mno-fpu
-Index: gcc/config/sparc/sparc.md
-===================================================================
---- a/src/gcc/config/sparc/sparc.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/sparc.md (.../branches/gcc-4_8-branch)
-@@ -206,7 +206,7 @@
- ;; 'f' for all DF/TFmode values, including those that are specific to the v8.
-
- ;; Attribute for cpu type.
--;; These must match the values for enum processor_type in sparc.h.
-+;; These must match the values of the enum processor_type in sparc-opts.h.
- (define_attr "cpu"
- "v7,
- cypress,
-@@ -214,6 +214,7 @@
- supersparc,
- hypersparc,
- leon,
-+ leon3,
- sparclite,
- f930,
- f934,
-@@ -284,7 +285,8 @@
- (const_string "none"))
-
- (define_attr "pic" "false,true"
-- (symbol_ref "(flag_pic != 0 ? PIC_TRUE : PIC_FALSE)"))
-+ (symbol_ref "(flag_pic != 0
-+ ? PIC_TRUE : PIC_FALSE)"))
-
- (define_attr "calls_alloca" "false,true"
- (symbol_ref "(cfun->calls_alloca != 0
-@@ -306,6 +308,10 @@
- (symbol_ref "(TARGET_FLAT != 0
- ? FLAT_TRUE : FLAT_FALSE)"))
-
-+(define_attr "fix_ut699" "false,true"
-+ (symbol_ref "(sparc_fix_ut699 != 0
-+ ? FIX_UT699_TRUE : FIX_UT699_FALSE)"))
-+
- ;; Length (in # of insns).
- ;; Beware that setting a length greater or equal to 3 for conditional branches
- ;; has a side-effect (see output_cbranch and output_v9branch).
-@@ -412,6 +418,10 @@
- (define_attr "fptype" "single,double"
- (const_string "single"))
-
-+;; FP precision specific to the UT699.
-+(define_attr "fptype_ut699" "none,single"
-+ (const_string "none"))
-+
- ;; UltraSPARC-III integer load type.
- (define_attr "us3load_type" "2cycle,3cycle"
- (const_string "2cycle"))
-@@ -420,32 +430,18 @@
- [(set_attr "length" "2")
- (set_attr "type" "multi")])
-
--;; Attributes for instruction and branch scheduling
--(define_attr "tls_call_delay" "false,true"
-- (symbol_ref "(tls_call_delay (insn)
-- ? TLS_CALL_DELAY_TRUE : TLS_CALL_DELAY_FALSE)"))
--
-+;; Attributes for branch scheduling
- (define_attr "in_call_delay" "false,true"
-- (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
-- (const_string "false")
-- (eq_attr "type" "load,fpload,store,fpstore")
-- (if_then_else (eq_attr "length" "1")
-- (const_string "true")
-- (const_string "false"))]
-- (if_then_else (and (eq_attr "length" "1")
-- (eq_attr "tls_call_delay" "true"))
-- (const_string "true")
-- (const_string "false"))))
-+ (symbol_ref "(eligible_for_call_delay (insn)
-+ ? IN_CALL_DELAY_TRUE : IN_CALL_DELAY_FALSE)"))
-
--(define_attr "eligible_for_sibcall_delay" "false,true"
-+(define_attr "in_sibcall_delay" "false,true"
- (symbol_ref "(eligible_for_sibcall_delay (insn)
-- ? ELIGIBLE_FOR_SIBCALL_DELAY_TRUE
-- : ELIGIBLE_FOR_SIBCALL_DELAY_FALSE)"))
-+ ? IN_SIBCALL_DELAY_TRUE : IN_SIBCALL_DELAY_FALSE)"))
-
--(define_attr "eligible_for_return_delay" "false,true"
-+(define_attr "in_return_delay" "false,true"
- (symbol_ref "(eligible_for_return_delay (insn)
-- ? ELIGIBLE_FOR_RETURN_DELAY_TRUE
-- : ELIGIBLE_FOR_RETURN_DELAY_FALSE)"))
-+ ? IN_RETURN_DELAY_TRUE : IN_RETURN_DELAY_FALSE)"))
-
- ;; ??? !v9: Should implement the notion of predelay slots for floating-point
- ;; branches. This would allow us to remove the nop always inserted before
-@@ -460,41 +456,35 @@
- ;; because it prevents us from moving back the final store of inner loops.
-
- (define_attr "in_branch_delay" "false,true"
-- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
-- (eq_attr "length" "1"))
-- (const_string "true")
-- (const_string "false")))
-+ (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
-+ (const_string "false")
-+ (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload"))
-+ (const_string "false")
-+ (and (eq_attr "fix_ut699" "true")
-+ (and (eq_attr "type" "fpload,fp,fpmove,fpmul,fpdivs,fpsqrts")
-+ (ior (eq_attr "fptype" "single")
-+ (eq_attr "fptype_ut699" "single"))))
-+ (const_string "false")
-+ (eq_attr "length" "1")
-+ (const_string "true")
-+ ] (const_string "false")))
-
--(define_attr "in_uncond_branch_delay" "false,true"
-- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
-- (eq_attr "length" "1"))
-- (const_string "true")
-- (const_string "false")))
--
--(define_attr "in_annul_branch_delay" "false,true"
-- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
-- (eq_attr "length" "1"))
-- (const_string "true")
-- (const_string "false")))
--
- (define_delay (eq_attr "type" "call")
- [(eq_attr "in_call_delay" "true") (nil) (nil)])
-
- (define_delay (eq_attr "type" "sibcall")
-- [(eq_attr "eligible_for_sibcall_delay" "true") (nil) (nil)])
-+ [(eq_attr "in_sibcall_delay" "true") (nil) (nil)])
-
-+(define_delay (eq_attr "type" "return")
-+ [(eq_attr "in_return_delay" "true") (nil) (nil)])
-+
- (define_delay (eq_attr "type" "branch")
-- [(eq_attr "in_branch_delay" "true")
-- (nil) (eq_attr "in_annul_branch_delay" "true")])
-+ [(eq_attr "in_branch_delay" "true") (nil) (eq_attr "in_branch_delay" "true")])
-
- (define_delay (eq_attr "type" "uncond_branch")
-- [(eq_attr "in_uncond_branch_delay" "true")
-- (nil) (nil)])
-+ [(eq_attr "in_branch_delay" "true") (nil) (nil)])
-
--(define_delay (eq_attr "type" "return")
-- [(eq_attr "eligible_for_return_delay" "true") (nil) (nil)])
-
--
- ;; Include SPARC DFA schedulers
-
- (include "cypress.md")
-@@ -3513,7 +3503,8 @@
- "TARGET_FPU"
- "fdtos\t%1, %0"
- [(set_attr "type" "fp")
-- (set_attr "fptype" "double")])
-+ (set_attr "fptype" "double")
-+ (set_attr "fptype_ut699" "single")])
-
- (define_expand "trunctfsf2"
- [(set (match_operand:SF 0 "register_operand" "")
-@@ -3554,7 +3545,7 @@
- "TARGET_FPU"
- "fitos\t%1, %0"
- [(set_attr "type" "fp")
-- (set_attr "fptype" "double")])
-+ (set_attr "fptype" "single")])
-
- (define_insn "floatsidf2"
- [(set (match_operand:DF 0 "register_operand" "=e")
-@@ -3641,7 +3632,7 @@
- "TARGET_FPU"
- "fstoi\t%1, %0"
- [(set_attr "type" "fp")
-- (set_attr "fptype" "double")])
-+ (set_attr "fptype" "single")])
-
- (define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "=f")
-@@ -3649,7 +3640,8 @@
- "TARGET_FPU"
- "fdtoi\t%1, %0"
- [(set_attr "type" "fp")
-- (set_attr "fptype" "double")])
-+ (set_attr "fptype" "double")
-+ (set_attr "fptype_ut699" "single")])
-
- (define_expand "fix_trunctfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
-@@ -5548,7 +5540,7 @@
- [(set (match_operand:DF 0 "register_operand" "=e")
- (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
- (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
-- "(TARGET_V8 || TARGET_V9) && TARGET_FPU"
-+ "(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699"
- "fsmuld\t%1, %2, %0"
- [(set_attr "type" "fpmul")
- (set_attr "fptype" "double")])
-@@ -5575,74 +5567,90 @@
- (match_operand:TF 2 "register_operand" "e")))]
- "TARGET_FPU && TARGET_HARD_QUAD"
- "fdivq\t%1, %2, %0"
-- [(set_attr "type" "fpdivd")])
-+ [(set_attr "type" "fpdivs")])
-
--(define_insn "divdf3"
-+(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand" "=e")
- (div:DF (match_operand:DF 1 "register_operand" "e")
- (match_operand:DF 2 "register_operand" "e")))]
- "TARGET_FPU"
-+ "")
-+
-+(define_insn "*divdf3_nofix"
-+ [(set (match_operand:DF 0 "register_operand" "=e")
-+ (div:DF (match_operand:DF 1 "register_operand" "e")
-+ (match_operand:DF 2 "register_operand" "e")))]
-+ "TARGET_FPU && !sparc_fix_ut699"
- "fdivd\t%1, %2, %0"
- [(set_attr "type" "fpdivd")
- (set_attr "fptype" "double")])
-
-+(define_insn "*divdf3_fix"
-+ [(set (match_operand:DF 0 "register_operand" "=e")
-+ (div:DF (match_operand:DF 1 "register_operand" "e")
-+ (match_operand:DF 2 "register_operand" "e")))]
-+ "TARGET_FPU && sparc_fix_ut699"
-+ "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]"
-+ [(set_attr "type" "fpdivd")
-+ (set_attr "fptype" "double")
-+ (set_attr "length" "2")])
-+
- (define_insn "divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
-- "TARGET_FPU"
-+ "TARGET_FPU && !sparc_fix_ut699"
- "fdivs\t%1, %2, %0"
- [(set_attr "type" "fpdivs")])
-
- (define_expand "negtf2"
-- [(set (match_operand:TF 0 "register_operand" "=e,e")
-- (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
-+ [(set (match_operand:TF 0 "register_operand" "")
-+ (neg:TF (match_operand:TF 1 "register_operand" "")))]
- "TARGET_FPU"
- "")
-
--(define_insn_and_split "*negtf2_notv9"
-- [(set (match_operand:TF 0 "register_operand" "=e,e")
-- (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
-- ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
-- "TARGET_FPU
-- && ! TARGET_V9"
-- "@
-- fnegs\t%0, %0
-- #"
-- "&& reload_completed
-- && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-- [(set (match_dup 2) (neg:SF (match_dup 3)))
-- (set (match_dup 4) (match_dup 5))
-- (set (match_dup 6) (match_dup 7))]
-- "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
-- operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
-- operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
-- operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
-- operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
-- operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
-- [(set_attr "type" "fpmove,*")
-- (set_attr "length" "*,2")])
-+(define_insn "*negtf2_hq"
-+ [(set (match_operand:TF 0 "register_operand" "=e")
-+ (neg:TF (match_operand:TF 1 "register_operand" "e")))]
-+ "TARGET_FPU && TARGET_HARD_QUAD"
-+ "fnegq\t%1, %0"
-+ [(set_attr "type" "fpmove")])
-
--(define_insn_and_split "*negtf2_v9"
-- [(set (match_operand:TF 0 "register_operand" "=e,e")
-- (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
-- ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
-- "TARGET_FPU && TARGET_V9"
-- "@
-- fnegd\t%0, %0
-- #"
-- "&& reload_completed
-- && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-- [(set (match_dup 2) (neg:DF (match_dup 3)))
-- (set (match_dup 4) (match_dup 5))]
-- "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
-- operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
-- operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
-- operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
-- [(set_attr "type" "fpmove,*")
-- (set_attr "length" "*,2")
-- (set_attr "fptype" "double")])
-+(define_insn_and_split "*negtf2"
-+ [(set (match_operand:TF 0 "register_operand" "=e")
-+ (neg:TF (match_operand:TF 1 "register_operand" "e")))]
-+ "TARGET_FPU && !TARGET_HARD_QUAD"
-+ "#"
-+ "&& reload_completed"
-+ [(clobber (const_int 0))]
-+{
-+ rtx set_dest = operands[0];
-+ rtx set_src = operands[1];
-+ rtx dest1, dest2;
-+ rtx src1, src2;
-
-+ dest1 = gen_df_reg (set_dest, 0);
-+ dest2 = gen_df_reg (set_dest, 1);
-+ src1 = gen_df_reg (set_src, 0);
-+ src2 = gen_df_reg (set_src, 1);
-+
-+ /* Now emit using the real source and destination we found, swapping
-+ the order if we detect overlap. */
-+ if (reg_overlap_mentioned_p (dest1, src2))
-+ {
-+ emit_insn (gen_movdf (dest2, src2));
-+ emit_insn (gen_negdf2 (dest1, src1));
-+ }
-+ else
-+ {
-+ emit_insn (gen_negdf2 (dest1, src1));
-+ if (REGNO (dest2) != REGNO (src2))
-+ emit_insn (gen_movdf (dest2, src2));
-+ }
-+ DONE;
-+}
-+ [(set_attr "length" "2")])
-+
- (define_expand "negdf2"
- [(set (match_operand:DF 0 "register_operand" "")
- (neg:DF (match_operand:DF 1 "register_operand" "")))]
-@@ -5650,23 +5658,40 @@
- "")
-
- (define_insn_and_split "*negdf2_notv9"
-- [(set (match_operand:DF 0 "register_operand" "=e,e")
-- (neg:DF (match_operand:DF 1 "register_operand" "0,e")))]
-- "TARGET_FPU && ! TARGET_V9"
-- "@
-- fnegs\t%0, %0
-- #"
-- "&& reload_completed
-- && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-- [(set (match_dup 2) (neg:SF (match_dup 3)))
-- (set (match_dup 4) (match_dup 5))]
-- "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
-- operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
-- operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
-- operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
-- [(set_attr "type" "fpmove,*")
-- (set_attr "length" "*,2")])
-+ [(set (match_operand:DF 0 "register_operand" "=e")
-+ (neg:DF (match_operand:DF 1 "register_operand" "e")))]
-+ "TARGET_FPU && !TARGET_V9"
-+ "#"
-+ "&& reload_completed"
-+ [(clobber (const_int 0))]
-+{
-+ rtx set_dest = operands[0];
-+ rtx set_src = operands[1];
-+ rtx dest1, dest2;
-+ rtx src1, src2;
-
-+ dest1 = gen_highpart (SFmode, set_dest);
-+ dest2 = gen_lowpart (SFmode, set_dest);
-+ src1 = gen_highpart (SFmode, set_src);
-+ src2 = gen_lowpart (SFmode, set_src);
-+
-+ /* Now emit using the real source and destination we found, swapping
-+ the order if we detect overlap. */
-+ if (reg_overlap_mentioned_p (dest1, src2))
-+ {
-+ emit_insn (gen_movsf (dest2, src2));
-+ emit_insn (gen_negsf2 (dest1, src1));
-+ }
-+ else
-+ {
-+ emit_insn (gen_negsf2 (dest1, src1));
-+ if (REGNO (dest2) != REGNO (src2))
-+ emit_insn (gen_movsf (dest2, src2));
-+ }
-+ DONE;
-+}
-+ [(set_attr "length" "2")])
-+
- (define_insn "*negdf2_v9"
- [(set (match_operand:DF 0 "register_operand" "=e")
- (neg:DF (match_operand:DF 1 "register_operand" "e")))]
-@@ -5688,57 +5713,48 @@
- "TARGET_FPU"
- "")
-
--(define_insn_and_split "*abstf2_notv9"
-- [(set (match_operand:TF 0 "register_operand" "=e,e")
-- (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
-- ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
-- "TARGET_FPU && ! TARGET_V9"
-- "@
-- fabss\t%0, %0
-- #"
-- "&& reload_completed
-- && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-- [(set (match_dup 2) (abs:SF (match_dup 3)))
-- (set (match_dup 4) (match_dup 5))
-- (set (match_dup 6) (match_dup 7))]
-- "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
-- operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
-- operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
-- operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
-- operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
-- operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
-- [(set_attr "type" "fpmove,*")
-- (set_attr "length" "*,2")])
-+(define_insn "*abstf2_hq"
-+ [(set (match_operand:TF 0 "register_operand" "=e")
-+ (abs:TF (match_operand:TF 1 "register_operand" "e")))]
-+ "TARGET_FPU && TARGET_HARD_QUAD"
-+ "fabsq\t%1, %0"
-+ [(set_attr "type" "fpmove")])
-
--(define_insn "*abstf2_hq_v9"
-- [(set (match_operand:TF 0 "register_operand" "=e,e")
-- (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
-- "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD"
-- "@
-- fabsd\t%0, %0
-- fabsq\t%1, %0"
-- [(set_attr "type" "fpmove")
-- (set_attr "fptype" "double,*")])
-+(define_insn_and_split "*abstf2"
-+ [(set (match_operand:TF 0 "register_operand" "=e")
-+ (abs:TF (match_operand:TF 1 "register_operand" "e")))]
-+ "TARGET_FPU && !TARGET_HARD_QUAD"
-+ "#"
-+ "&& reload_completed"
-+ [(clobber (const_int 0))]
-+{
-+ rtx set_dest = operands[0];
-+ rtx set_src = operands[1];
-+ rtx dest1, dest2;
-+ rtx src1, src2;
-
--(define_insn_and_split "*abstf2_v9"
-- [(set (match_operand:TF 0 "register_operand" "=e,e")
-- (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
-- "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD"
-- "@
-- fabsd\t%0, %0
-- #"
-- "&& reload_completed
-- && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-- [(set (match_dup 2) (abs:DF (match_dup 3)))
-- (set (match_dup 4) (match_dup 5))]
-- "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
-- operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
-- operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
-- operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
-- [(set_attr "type" "fpmove,*")
-- (set_attr "length" "*,2")
-- (set_attr "fptype" "double,*")])
-+ dest1 = gen_df_reg (set_dest, 0);
-+ dest2 = gen_df_reg (set_dest, 1);
-+ src1 = gen_df_reg (set_src, 0);
-+ src2 = gen_df_reg (set_src, 1);
-
-+ /* Now emit using the real source and destination we found, swapping
-+ the order if we detect overlap. */
-+ if (reg_overlap_mentioned_p (dest1, src2))
-+ {
-+ emit_insn (gen_movdf (dest2, src2));
-+ emit_insn (gen_absdf2 (dest1, src1));
-+ }
-+ else
-+ {
-+ emit_insn (gen_absdf2 (dest1, src1));
-+ if (REGNO (dest2) != REGNO (src2))
-+ emit_insn (gen_movdf (dest2, src2));
-+ }
-+ DONE;
-+}
-+ [(set_attr "length" "2")])
-+
- (define_expand "absdf2"
- [(set (match_operand:DF 0 "register_operand" "")
- (abs:DF (match_operand:DF 1 "register_operand" "")))]
-@@ -5746,23 +5762,40 @@
- "")
-
- (define_insn_and_split "*absdf2_notv9"
-- [(set (match_operand:DF 0 "register_operand" "=e,e")
-- (abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
-- "TARGET_FPU && ! TARGET_V9"
-- "@
-- fabss\t%0, %0
-- #"
-- "&& reload_completed
-- && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-- [(set (match_dup 2) (abs:SF (match_dup 3)))
-- (set (match_dup 4) (match_dup 5))]
-- "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
-- operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
-- operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
-- operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
-- [(set_attr "type" "fpmove,*")
-- (set_attr "length" "*,2")])
-+ [(set (match_operand:DF 0 "register_operand" "=e")
-+ (abs:DF (match_operand:DF 1 "register_operand" "e")))]
-+ "TARGET_FPU && !TARGET_V9"
-+ "#"
-+ "&& reload_completed"
-+ [(clobber (const_int 0))]
-+{
-+ rtx set_dest = operands[0];
-+ rtx set_src = operands[1];
-+ rtx dest1, dest2;
-+ rtx src1, src2;
-
-+ dest1 = gen_highpart (SFmode, set_dest);
-+ dest2 = gen_lowpart (SFmode, set_dest);
-+ src1 = gen_highpart (SFmode, set_src);
-+ src2 = gen_lowpart (SFmode, set_src);
-+
-+ /* Now emit using the real source and destination we found, swapping
-+ the order if we detect overlap. */
-+ if (reg_overlap_mentioned_p (dest1, src2))
-+ {
-+ emit_insn (gen_movsf (dest2, src2));
-+ emit_insn (gen_abssf2 (dest1, src1));
-+ }
-+ else
-+ {
-+ emit_insn (gen_abssf2 (dest1, src1));
-+ if (REGNO (dest2) != REGNO (src2))
-+ emit_insn (gen_movsf (dest2, src2));
-+ }
-+ DONE;
-+}
-+ [(set_attr "length" "2")])
-+
- (define_insn "*absdf2_v9"
- [(set (match_operand:DF 0 "register_operand" "=e")
- (abs:DF (match_operand:DF 1 "register_operand" "e")))]
-@@ -5789,20 +5822,35 @@
- (sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
- "TARGET_FPU && TARGET_HARD_QUAD"
- "fsqrtq\t%1, %0"
-- [(set_attr "type" "fpsqrtd")])
-+ [(set_attr "type" "fpsqrts")])
-
--(define_insn "sqrtdf2"
-+(define_expand "sqrtdf2"
- [(set (match_operand:DF 0 "register_operand" "=e")
- (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
- "TARGET_FPU"
-+ "")
-+
-+(define_insn "*sqrtdf2_nofix"
-+ [(set (match_operand:DF 0 "register_operand" "=e")
-+ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
-+ "TARGET_FPU && !sparc_fix_ut699"
- "fsqrtd\t%1, %0"
- [(set_attr "type" "fpsqrtd")
- (set_attr "fptype" "double")])
-
-+(define_insn "*sqrtdf2_fix"
-+ [(set (match_operand:DF 0 "register_operand" "=e")
-+ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
-+ "TARGET_FPU && sparc_fix_ut699"
-+ "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]"
-+ [(set_attr "type" "fpsqrtd")
-+ (set_attr "fptype" "double")
-+ (set_attr "length" "2")])
-+
- (define_insn "sqrtsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
-- "TARGET_FPU"
-+ "TARGET_FPU && !sparc_fix_ut699"
- "fsqrts\t%1, %0"
- [(set_attr "type" "fpsqrts")])
-
-@@ -5821,19 +5869,6 @@
- }
- [(set_attr "type" "shift")])
-
--(define_insn "*ashlsi3_extend"
-- [(set (match_operand:DI 0 "register_operand" "=r")
-- (zero_extend:DI
-- (ashift:SI (match_operand:SI 1 "register_operand" "r")
-- (match_operand:SI 2 "arith_operand" "rI"))))]
-- "TARGET_ARCH64"
--{
-- if (GET_CODE (operands[2]) == CONST_INT)
-- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-- return "sll\t%1, %2, %0";
--}
-- [(set_attr "type" "shift")])
--
- (define_expand "ashldi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ashift:DI (match_operand:DI 1 "register_operand" "r")
-Index: gcc/config/sparc/t-sparc
-===================================================================
---- a/src/gcc/config/sparc/t-sparc (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/t-sparc (.../branches/gcc-4_8-branch)
-@@ -23,7 +23,7 @@
- insn-codes.h conditions.h output.h $(INSN_ATTR_H) $(FLAGS_H) \
- $(FUNCTION_H) $(EXCEPT_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H) \
- $(DIAGNOSTIC_CORE_H) $(GGC_H) $(TM_P_H) debug.h $(TARGET_H) \
-- $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) \
-+ $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) $(TREE_PASS_H) \
- langhooks.h reload.h $(PARAMS_H) $(DF_H) $(OPTS_H) \
- gt-sparc.h
-
-Index: gcc/config/sparc/sparc.opt
-===================================================================
---- a/src/gcc/config/sparc/sparc.opt (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/sparc.opt (.../branches/gcc-4_8-branch)
-@@ -113,6 +113,10 @@
- Target
- Optimize tail call instructions in assembler and linker
-
-+muser-mode
-+Target Report Mask(USER_MODE)
-+Do not generate code that can only run in supervisor mode
-+
- mcpu=
- Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
- Use features of and schedule code for given CPU
-@@ -146,6 +150,9 @@
- Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)
-
- EnumValue
-+Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
-+
-+EnumValue
- Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
-
- EnumValue
-@@ -201,9 +208,19 @@
- Enable workaround for single erratum of AT697F processor
- (corresponding to erratum #13 of AT697E processor)
-
-+mfix-ut699
-+Target Report RejectNegative Var(sparc_fix_ut699)
-+Enable workarounds for the errata of the UT699 processor
-+
- Mask(LONG_DOUBLE_128)
- ;; Use 128-bit long double
-
-+Mask(LEON)
-+;; Generate code for LEON
-+
-+Mask(LEON3)
-+;; Generate code for LEON3
-+
- Mask(SPARCLITE)
- ;; Generate code for SPARClite
-
-Index: gcc/config/sparc/sync.md
-===================================================================
---- a/src/gcc/config/sparc/sync.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/sync.md (.../branches/gcc-4_8-branch)
-@@ -161,7 +161,8 @@
- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
- (match_operand:SI 6 "const_int_operand" "") ;; mod_s
- (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
-- "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
-+ "(TARGET_V9 || TARGET_LEON3)
-+ && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
- {
- sparc_expand_compare_and_swap (operands);
- DONE;
-@@ -176,7 +177,7 @@
- [(match_operand:I48MODE 2 "register_operand" "")
- (match_operand:I48MODE 3 "register_operand" "")]
- UNSPECV_CAS))])]
-- "TARGET_V9"
-+ "TARGET_V9 || TARGET_LEON3"
- "")
-
- (define_insn "*atomic_compare_and_swap<mode>_1"
-@@ -187,10 +188,27 @@
- [(match_operand:I48MODE 2 "register_operand" "r")
- (match_operand:I48MODE 3 "register_operand" "0")]
- UNSPECV_CAS))]
-- "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
-+ "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)"
- "cas<modesuffix>\t%1, %2, %0"
- [(set_attr "type" "multi")])
-
-+(define_insn "*atomic_compare_and_swap_leon3_1"
-+ [(set (match_operand:SI 0 "register_operand" "=r")
-+ (match_operand:SI 1 "mem_noofs_operand" "+w"))
-+ (set (match_dup 1)
-+ (unspec_volatile:SI
-+ [(match_operand:SI 2 "register_operand" "r")
-+ (match_operand:SI 3 "register_operand" "0")]
-+ UNSPECV_CAS))]
-+ "TARGET_LEON3"
-+{
-+ if (TARGET_USER_MODE)
-+ return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */
-+ else
-+ return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */
-+}
-+ [(set_attr "type" "multi")])
-+
- (define_insn "*atomic_compare_and_swapdi_v8plus"
- [(set (match_operand:DI 0 "register_operand" "=h")
- (match_operand:DI 1 "mem_noofs_operand" "+w"))
-@@ -220,7 +238,7 @@
- (match_operand:SI 1 "memory_operand" "")
- (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
-- "TARGET_V8 || TARGET_V9"
-+ "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
- {
- enum memmodel model = (enum memmodel) INTVAL (operands[3]);
-
-@@ -236,7 +254,7 @@
- UNSPECV_SWAP))
- (set (match_dup 1)
- (match_operand:SI 2 "register_operand" "0"))]
-- "TARGET_V8 || TARGET_V9"
-+ "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
- "swap\t%1, %0"
- [(set_attr "type" "multi")])
-
-@@ -244,7 +262,7 @@
- [(match_operand:QI 0 "register_operand" "")
- (match_operand:QI 1 "memory_operand" "")
- (match_operand:SI 2 "const_int_operand" "")]
-- ""
-+ "!sparc_fix_ut699"
- {
- enum memmodel model = (enum memmodel) INTVAL (operands[2]);
- rtx ret;
-@@ -268,6 +286,6 @@
- (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
- UNSPECV_LDSTUB))
- (set (match_dup 1) (const_int -1))]
-- ""
-+ "!sparc_fix_ut699"
- "ldstub\t%1, %0"
- [(set_attr "type" "multi")])
-Index: gcc/config/sparc/sparc-opts.h
-===================================================================
---- a/src/gcc/config/sparc/sparc-opts.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/sparc-opts.h (.../branches/gcc-4_8-branch)
-@@ -30,6 +30,7 @@
- PROCESSOR_SUPERSPARC,
- PROCESSOR_HYPERSPARC,
- PROCESSOR_LEON,
-+ PROCESSOR_LEON3,
- PROCESSOR_SPARCLITE,
- PROCESSOR_F930,
- PROCESSOR_F934,
-Index: gcc/config/sparc/sparc-protos.h
-===================================================================
---- a/src/gcc/config/sparc/sparc-protos.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/sparc-protos.h (.../branches/gcc-4_8-branch)
-@@ -69,7 +69,6 @@
- extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx);
- extern int sparc_splitdi_legitimate (rtx, rtx);
- extern int sparc_split_regreg_legitimate (rtx, rtx);
--extern int sparc_absnegfloat_split_legitimate (rtx, rtx);
- extern const char *output_ubranch (rtx, rtx);
- extern const char *output_cbranch (rtx, rtx, int, int, int, rtx);
- extern const char *output_return (rtx);
-@@ -84,9 +83,9 @@
- extern int mems_ok_for_ldd_peep (rtx, rtx, rtx);
- extern int empty_delay_slot (rtx);
- extern int emit_cbcond_nop (rtx);
-+extern int eligible_for_call_delay (rtx);
- extern int eligible_for_return_delay (rtx);
- extern int eligible_for_sibcall_delay (rtx);
--extern int tls_call_delay (rtx);
- extern int emit_move_sequence (rtx, enum machine_mode);
- extern int fp_sethi_p (rtx);
- extern int fp_mov_p (rtx);
-Index: gcc/config/sparc/sparc.c
-===================================================================
---- a/src/gcc/config/sparc/sparc.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/sparc.c (.../branches/gcc-4_8-branch)
-@@ -52,6 +52,7 @@
- #include "params.h"
- #include "df.h"
- #include "opts.h"
-+#include "tree-pass.h"
-
- /* Processor costs */
-
-@@ -226,6 +227,30 @@
- };
-
- static const
-+struct processor_costs leon3_costs = {
-+ COSTS_N_INSNS (1), /* int load */
-+ COSTS_N_INSNS (1), /* int signed load */
-+ COSTS_N_INSNS (1), /* int zeroed load */
-+ COSTS_N_INSNS (1), /* float load */
-+ COSTS_N_INSNS (1), /* fmov, fneg, fabs */
-+ COSTS_N_INSNS (1), /* fadd, fsub */
-+ COSTS_N_INSNS (1), /* fcmp */
-+ COSTS_N_INSNS (1), /* fmov, fmovr */
-+ COSTS_N_INSNS (1), /* fmul */
-+ COSTS_N_INSNS (14), /* fdivs */
-+ COSTS_N_INSNS (15), /* fdivd */
-+ COSTS_N_INSNS (22), /* fsqrts */
-+ COSTS_N_INSNS (23), /* fsqrtd */
-+ COSTS_N_INSNS (5), /* imul */
-+ COSTS_N_INSNS (5), /* imulX */
-+ 0, /* imul bit factor */
-+ COSTS_N_INSNS (35), /* idiv */
-+ COSTS_N_INSNS (35), /* idivX */
-+ COSTS_N_INSNS (1), /* movcc/movr */
-+ 0, /* shift penalty */
-+};
-+
-+static const
- struct processor_costs sparclet_costs = {
- COSTS_N_INSNS (3), /* int load */
- COSTS_N_INSNS (3), /* int signed load */
-@@ -538,7 +563,6 @@
- HOST_WIDE_INT, tree);
- static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
- HOST_WIDE_INT, const_tree);
--static void sparc_reorg (void);
- static struct machine_function * sparc_init_machine_status (void);
- static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);
- static rtx sparc_tls_get_addr (void);
-@@ -680,9 +704,6 @@
- #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
- #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
-
--#undef TARGET_MACHINE_DEPENDENT_REORG
--#define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg
--
- #undef TARGET_RTX_COSTS
- #define TARGET_RTX_COSTS sparc_rtx_costs
- #undef TARGET_ADDRESS_COST
-@@ -804,6 +825,306 @@
-
- struct gcc_target targetm = TARGET_INITIALIZER;
-
-+/* Return the memory reference contained in X if any, zero otherwise. */
-+
-+static rtx
-+mem_ref (rtx x)
-+{
-+ if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND)
-+ x = XEXP (x, 0);
-+
-+ if (MEM_P (x))
-+ return x;
-+
-+ return NULL_RTX;
-+}
-+
-+/* We use a machine specific pass to enable workarounds for errata.
-+ We need to have the (essentially) final form of the insn stream in order
-+ to properly detect the various hazards. Therefore, this machine specific
-+ pass runs as late as possible. The pass is inserted in the pass pipeline
-+ at the end of sparc_option_override. */
-+
-+static bool
-+sparc_gate_work_around_errata (void)
-+{
-+ /* The only errata we handle are those of the AT697F and UT699. */
-+ return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;
-+}
-+
-+static unsigned int
-+sparc_do_work_around_errata (void)
-+{
-+ rtx insn, next;
-+
-+ /* Force all instructions to be split into their final form. */
-+ split_all_insns_noflow ();
-+
-+ /* Now look for specific patterns in the insn stream. */
-+ for (insn = get_insns (); insn; insn = next)
-+ {
-+ bool insert_nop = false;
-+ rtx set;
-+
-+ /* Look into the instruction in a delay slot. */
-+ if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
-+ insn = XVECEXP (PATTERN (insn), 0, 1);
-+
-+ /* Look for a single-word load into an odd-numbered FP register. */
-+ if (sparc_fix_at697f
-+ && NONJUMP_INSN_P (insn)
-+ && (set = single_set (insn)) != NULL_RTX
-+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
-+ && MEM_P (SET_SRC (set))
-+ && REG_P (SET_DEST (set))
-+ && REGNO (SET_DEST (set)) > 31
-+ && REGNO (SET_DEST (set)) % 2 != 0)
-+ {
-+ /* The wrong dependency is on the enclosing double register. */
-+ const unsigned int x = REGNO (SET_DEST (set)) - 1;
-+ unsigned int src1, src2, dest;
-+ int code;
-+
-+ next = next_active_insn (insn);
-+ if (!next)
-+ break;
-+ /* If the insn is a branch, then it cannot be problematic. */
-+ if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)
-+ continue;
-+
-+ extract_insn (next);
-+ code = INSN_CODE (next);
-+
-+ switch (code)
-+ {
-+ case CODE_FOR_adddf3:
-+ case CODE_FOR_subdf3:
-+ case CODE_FOR_muldf3:
-+ case CODE_FOR_divdf3:
-+ dest = REGNO (recog_data.operand[0]);
-+ src1 = REGNO (recog_data.operand[1]);
-+ src2 = REGNO (recog_data.operand[2]);
-+ if (src1 != src2)
-+ {
-+ /* Case [1-4]:
-+ ld [address], %fx+1
-+ FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
-+ if ((src1 == x || src2 == x)
-+ && (dest == src1 || dest == src2))
-+ insert_nop = true;
-+ }
-+ else
-+ {
-+ /* Case 5:
-+ ld [address], %fx+1
-+ FPOPd %fx, %fx, %fx */
-+ if (src1 == x
-+ && dest == src1
-+ && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
-+ insert_nop = true;
-+ }
-+ break;
-+
-+ case CODE_FOR_sqrtdf2:
-+ dest = REGNO (recog_data.operand[0]);
-+ src1 = REGNO (recog_data.operand[1]);
-+ /* Case 6:
-+ ld [address], %fx+1
-+ fsqrtd %fx, %fx */
-+ if (src1 == x && dest == src1)
-+ insert_nop = true;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+ }
-+
-+ /* Look for a single-word load into an integer register. */
-+ else if (sparc_fix_ut699
-+ && NONJUMP_INSN_P (insn)
-+ && (set = single_set (insn)) != NULL_RTX
-+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4
-+ && mem_ref (SET_SRC (set)) != NULL_RTX
-+ && REG_P (SET_DEST (set))
-+ && REGNO (SET_DEST (set)) < 32)
-+ {
-+ /* There is no problem if the second memory access has a data
-+ dependency on the first single-cycle load. */
-+ rtx x = SET_DEST (set);
-+
-+ next = next_active_insn (insn);
-+ if (!next)
-+ break;
-+ /* If the insn is a branch, then it cannot be problematic. */
-+ if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)
-+ continue;
-+
-+ /* Look for a second memory access to/from an integer register. */
-+ if ((set = single_set (next)) != NULL_RTX)
-+ {
-+ rtx src = SET_SRC (set);
-+ rtx dest = SET_DEST (set);
-+ rtx mem;
-+
-+ /* LDD is affected. */
-+ if ((mem = mem_ref (src)) != NULL_RTX
-+ && REG_P (dest)
-+ && REGNO (dest) < 32
-+ && !reg_mentioned_p (x, XEXP (mem, 0)))
-+ insert_nop = true;
-+
-+ /* STD is *not* affected. */
-+ else if (MEM_P (dest)
-+ && GET_MODE_SIZE (GET_MODE (dest)) <= 4
-+ && (src == CONST0_RTX (GET_MODE (dest))
-+ || (REG_P (src)
-+ && REGNO (src) < 32
-+ && REGNO (src) != REGNO (x)))
-+ && !reg_mentioned_p (x, XEXP (dest, 0)))
-+ insert_nop = true;
-+ }
-+ }
-+
-+ /* Look for a single-word load/operation into an FP register. */
-+ else if (sparc_fix_ut699
-+ && NONJUMP_INSN_P (insn)
-+ && (set = single_set (insn)) != NULL_RTX
-+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
-+ && REG_P (SET_DEST (set))
-+ && REGNO (SET_DEST (set)) > 31)
-+ {
-+ /* Number of instructions in the problematic window. */
-+ const int n_insns = 4;
-+ /* The problematic combination is with the sibling FP register. */
-+ const unsigned int x = REGNO (SET_DEST (set));
-+ const unsigned int y = x ^ 1;
-+ rtx after;
-+ int i;
-+
-+ next = next_active_insn (insn);
-+ if (!next)
-+ break;
-+ /* If the insn is a branch, then it cannot be problematic. */
-+ if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)
-+ continue;
-+
-+ /* Look for a second load/operation into the sibling FP register. */
-+ if (!((set = single_set (next)) != NULL_RTX
-+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
-+ && REG_P (SET_DEST (set))
-+ && REGNO (SET_DEST (set)) == y))
-+ continue;
-+
-+ /* Look for a (possible) store from the FP register in the next N
-+ instructions, but bail out if it is again modified or if there
-+ is a store from the sibling FP register before this store. */
-+ for (after = next, i = 0; i < n_insns; i++)
-+ {
-+ bool branch_p;
-+
-+ after = next_active_insn (after);
-+ if (!after)
-+ break;
-+
-+ /* This is a branch with an empty delay slot. */
-+ if (!NONJUMP_INSN_P (after))
-+ {
-+ if (++i == n_insns)
-+ break;
-+ branch_p = true;
-+ after = NULL_RTX;
-+ }
-+ /* This is a branch with a filled delay slot. */
-+ else if (GET_CODE (PATTERN (after)) == SEQUENCE)
-+ {
-+ if (++i == n_insns)
-+ break;
-+ branch_p = true;
-+ after = XVECEXP (PATTERN (after), 0, 1);
-+ }
-+ /* This is a regular instruction. */
-+ else
-+ branch_p = false;
-+
-+ if (after && (set = single_set (after)) != NULL_RTX)
-+ {
-+ const rtx src = SET_SRC (set);
-+ const rtx dest = SET_DEST (set);
-+ const unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
-+
-+ /* If the FP register is again modified before the store,
-+ then the store isn't affected. */
-+ if (REG_P (dest)
-+ && (REGNO (dest) == x
-+ || (REGNO (dest) == y && size == 8)))
-+ break;
-+
-+ if (MEM_P (dest) && REG_P (src))
-+ {
-+ /* If there is a store from the sibling FP register
-+ before the store, then the store is not affected. */
-+ if (REGNO (src) == y || (REGNO (src) == x && size == 8))
-+ break;
-+
-+ /* Otherwise, the store is affected. */
-+ if (REGNO (src) == x && size == 4)
-+ {
-+ insert_nop = true;
-+ break;
-+ }
-+ }
-+ }
-+
-+ /* If we have a branch in the first M instructions, then we
-+ cannot see the (M+2)th instruction so we play safe. */
-+ if (branch_p && i <= (n_insns - 2))
-+ {
-+ insert_nop = true;
-+ break;
-+ }
-+ }
-+ }
-+
-+ else
-+ next = NEXT_INSN (insn);
-+
-+ if (insert_nop)
-+ emit_insn_before (gen_nop (), next);
-+ }
-+
-+ return 0;
-+}
-+
-+struct rtl_opt_pass pass_work_around_errata =
-+{
-+ {
-+ RTL_PASS,
-+ "errata", /* name */
-+ OPTGROUP_NONE, /* optinfo_flags */
-+ sparc_gate_work_around_errata, /* gate */
-+ sparc_do_work_around_errata, /* execute */
-+ NULL, /* sub */
-+ NULL, /* next */
-+ 0, /* static_pass_number */
-+ TV_MACH_DEP, /* tv_id */
-+ 0, /* properties_required */
-+ 0, /* properties_provided */
-+ 0, /* properties_destroyed */
-+ 0, /* todo_flags_start */
-+ TODO_verify_rtl_sharing, /* todo_flags_finish */
-+ }
-+};
-+
-+struct register_pass_info insert_pass_work_around_errata =
-+{
-+ &pass_work_around_errata.pass, /* pass */
-+ "dbr", /* reference_pass_name */
-+ 1, /* ref_pass_instance_number */
-+ PASS_POS_INSERT_AFTER /* po_op */
-+};
-+
-+/* Helpers for TARGET_DEBUG_OPTIONS. */
- static void
- dump_target_flag_bits (const int flags)
- {
-@@ -888,6 +1209,7 @@
- { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
- { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
- { TARGET_CPU_leon, PROCESSOR_LEON },
-+ { TARGET_CPU_leon3, PROCESSOR_LEON3 },
- { TARGET_CPU_sparclite, PROCESSOR_F930 },
- { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
- { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
-@@ -902,7 +1224,7 @@
- };
- const struct cpu_default *def;
- /* Table of values for -m{cpu,tune}=. This must match the order of
-- the PROCESSOR_* enumeration. */
-+ the enum processor_type in sparc-opts.h. */
- static struct cpu_table {
- const char *const name;
- const int disable;
-@@ -914,8 +1236,8 @@
- /* TI TMS390Z55 supersparc */
- { "supersparc", MASK_ISA, MASK_V8 },
- { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
-- /* LEON */
-- { "leon", MASK_ISA, MASK_V8|MASK_FPU },
-+ { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
-+ { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
- { "sparclite", MASK_ISA, MASK_SPARCLITE },
- /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
- { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
-@@ -1075,6 +1397,9 @@
- #ifndef HAVE_AS_SPARC4
- & ~MASK_CBCOND
- #endif
-+#ifndef HAVE_AS_LEON
-+ & ~(MASK_LEON | MASK_LEON3)
-+#endif
- );
-
- /* If -mfpu or -mno-fpu was explicitly used, don't override with
-@@ -1164,6 +1489,9 @@
- case PROCESSOR_LEON:
- sparc_costs = &leon_costs;
- break;
-+ case PROCESSOR_LEON3:
-+ sparc_costs = &leon3_costs;
-+ break;
- case PROCESSOR_SPARCLET:
- case PROCESSOR_TSC701:
- sparc_costs = &sparclet_costs;
-@@ -1200,6 +1528,10 @@
- /* Choose the most relaxed model for the processor. */
- else if (TARGET_V9)
- sparc_memory_model = SMM_RMO;
-+ else if (TARGET_LEON3)
-+ sparc_memory_model = SMM_TSO;
-+ else if (TARGET_LEON)
-+ sparc_memory_model = SMM_SC;
- else if (TARGET_V8)
- sparc_memory_model = SMM_PSO;
- else
-@@ -1241,6 +1573,13 @@
- pessimizes for double floating-point registers. */
- if (!global_options_set.x_flag_ira_share_save_slots)
- flag_ira_share_save_slots = 0;
-+
-+ /* We register a machine specific pass to work around errata, if any.
-+ The pass mut be scheduled as late as possible so that we have the
-+ (essentially) final form of the insn stream to work on.
-+ Registering the pass must be done at start up. It's convenient to
-+ do it here. */
-+ register_pass (&insert_pass_work_around_errata);
- }
-
- /* Miscellaneous utilities. */
-@@ -3090,10 +3429,13 @@
- /* Return nonzero if TRIAL can go into the call delay slot. */
-
- int
--tls_call_delay (rtx trial)
-+eligible_for_call_delay (rtx trial)
- {
- rtx pat;
-
-+ if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)
-+ return 0;
-+
- /* Binutils allows
- call __tls_get_addr, %tgd_call (foo)
- add %l7, %o0, %o0, %tgd_add (foo)
-@@ -3175,11 +3517,7 @@
-
- /* If we have the 'return' instruction, anything that does not use
- local or output registers and can go into a delay slot wins. */
-- else if (return_p
-- && TARGET_V9
-- && !epilogue_renumber (&pat, 1)
-- && get_attr_in_uncond_branch_delay (trial)
-- == IN_UNCOND_BRANCH_DELAY_TRUE)
-+ else if (return_p && TARGET_V9 && !epilogue_renumber (&pat, 1))
- return 1;
-
- /* The 'restore src1,src2,dest' pattern for SImode. */
-@@ -3222,22 +3560,21 @@
- int regno;
- rtx pat;
-
-- if (GET_CODE (trial) != INSN)
-- return 0;
--
-- if (get_attr_length (trial) != 1)
-- return 0;
--
- /* If the function uses __builtin_eh_return, the eh_return machinery
- occupies the delay slot. */
- if (crtl->calls_eh_return)
- return 0;
-
-+ if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)
-+ return 0;
-+
- /* In the case of a leaf or flat function, anything can go into the slot. */
- if (sparc_leaf_function_p || TARGET_FLAT)
-- return
-- get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE;
-+ return 1;
-
-+ if (!NONJUMP_INSN_P (trial))
-+ return 0;
-+
- pat = PATTERN (trial);
- if (GET_CODE (pat) == PARALLEL)
- {
-@@ -3256,9 +3593,7 @@
- if (regno >= 8 && regno < 24)
- return 0;
- }
-- return !epilogue_renumber (&pat, 1)
-- && (get_attr_in_uncond_branch_delay (trial)
-- == IN_UNCOND_BRANCH_DELAY_TRUE);
-+ return !epilogue_renumber (&pat, 1);
- }
-
- if (GET_CODE (pat) != SET)
-@@ -3278,10 +3613,7 @@
- instruction, it can probably go in. But restore will not work
- with FP_REGS. */
- if (! SPARC_INT_REG_P (regno))
-- return (TARGET_V9
-- && !epilogue_renumber (&pat, 1)
-- && get_attr_in_uncond_branch_delay (trial)
-- == IN_UNCOND_BRANCH_DELAY_TRUE);
-+ return TARGET_V9 && !epilogue_renumber (&pat, 1);
-
- return eligible_for_restore_insn (trial, true);
- }
-@@ -3293,10 +3625,10 @@
- {
- rtx pat;
-
-- if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
-+ if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)
- return 0;
-
-- if (get_attr_length (trial) != 1)
-+ if (!NONJUMP_INSN_P (trial))
- return 0;
-
- pat = PATTERN (trial);
-@@ -3315,6 +3647,9 @@
- return 1;
- }
-
-+ if (GET_CODE (pat) != SET)
-+ return 0;
-+
- /* Otherwise, only operations which can be done in tandem with
- a `restore' insn can go into the delay slot. */
- if (GET_CODE (SET_DEST (pat)) != REG
-@@ -8134,22 +8469,6 @@
- return 0;
- }
-
--/* Return 1 if x and y are some kind of REG and they refer to
-- different hard registers. This test is guaranteed to be
-- run after reload. */
--
--int
--sparc_absnegfloat_split_legitimate (rtx x, rtx y)
--{
-- if (GET_CODE (x) != REG)
-- return 0;
-- if (GET_CODE (y) != REG)
-- return 0;
-- if (REGNO (x) == REGNO (y))
-- return 0;
-- return 1;
--}
--
- /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
- This makes them candidates for using ldd and std insns.
-
-@@ -10355,7 +10674,8 @@
- tmp = e0.add_with_sign (tmp, false, &add1_ovf);
- if (tmp.is_negative ())
- tmp = tmp.neg_with_overflow (&neg2_ovf);
--
-+ else
-+ neg2_ovf = false;
- result = result.add_with_sign (tmp, false, &add2_ovf);
- overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf;
- }
-@@ -10897,107 +11217,6 @@
- return (vcall_offset >= -32768 || ! fixed_regs[5]);
- }
-
--/* We use the machine specific reorg pass to enable workarounds for errata. */
--
--static void
--sparc_reorg (void)
--{
-- rtx insn, next;
--
-- /* The only erratum we handle for now is that of the AT697F processor. */
-- if (!sparc_fix_at697f)
-- return;
--
-- /* We need to have the (essentially) final form of the insn stream in order
-- to properly detect the various hazards. Run delay slot scheduling. */
-- if (optimize > 0 && flag_delayed_branch)
-- {
-- cleanup_barriers ();
-- dbr_schedule (get_insns ());
-- }
--
-- /* Now look for specific patterns in the insn stream. */
-- for (insn = get_insns (); insn; insn = next)
-- {
-- bool insert_nop = false;
-- rtx set;
--
-- /* Look for a single-word load into an odd-numbered FP register. */
-- if (NONJUMP_INSN_P (insn)
-- && (set = single_set (insn)) != NULL_RTX
-- && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
-- && MEM_P (SET_SRC (set))
-- && REG_P (SET_DEST (set))
-- && REGNO (SET_DEST (set)) > 31
-- && REGNO (SET_DEST (set)) % 2 != 0)
-- {
-- /* The wrong dependency is on the enclosing double register. */
-- unsigned int x = REGNO (SET_DEST (set)) - 1;
-- unsigned int src1, src2, dest;
-- int code;
--
-- /* If the insn has a delay slot, then it cannot be problematic. */
-- next = next_active_insn (insn);
-- if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
-- code = -1;
-- else
-- {
-- extract_insn (next);
-- code = INSN_CODE (next);
-- }
--
-- switch (code)
-- {
-- case CODE_FOR_adddf3:
-- case CODE_FOR_subdf3:
-- case CODE_FOR_muldf3:
-- case CODE_FOR_divdf3:
-- dest = REGNO (recog_data.operand[0]);
-- src1 = REGNO (recog_data.operand[1]);
-- src2 = REGNO (recog_data.operand[2]);
-- if (src1 != src2)
-- {
-- /* Case [1-4]:
-- ld [address], %fx+1
-- FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
-- if ((src1 == x || src2 == x)
-- && (dest == src1 || dest == src2))
-- insert_nop = true;
-- }
-- else
-- {
-- /* Case 5:
-- ld [address], %fx+1
-- FPOPd %fx, %fx, %fx */
-- if (src1 == x
-- && dest == src1
-- && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
-- insert_nop = true;
-- }
-- break;
--
-- case CODE_FOR_sqrtdf2:
-- dest = REGNO (recog_data.operand[0]);
-- src1 = REGNO (recog_data.operand[1]);
-- /* Case 6:
-- ld [address], %fx+1
-- fsqrtd %fx, %fx */
-- if (src1 == x && dest == src1)
-- insert_nop = true;
-- break;
--
-- default:
-- break;
-- }
-- }
-- else
-- next = NEXT_INSN (insn);
--
-- if (insert_nop)
-- emit_insn_after (gen_nop (), insn);
-- }
--}
--
- /* How to allocate a 'struct machine_function'. */
-
- static struct machine_function *
-Index: gcc/config/sparc/leon.md
-===================================================================
---- a/src/gcc/config/sparc/leon.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/leon.md (.../branches/gcc-4_8-branch)
-@@ -17,40 +17,48 @@
- ;; along with GCC; see the file COPYING3. If not see
- ;; <http://www.gnu.org/licenses/>.
-
-+;; Leon is a single-issue processor.
-
- (define_automaton "leon")
-
--(define_cpu_unit "leon_memory, leon_fpalu" "leon")
--(define_cpu_unit "leon_fpmds" "leon")
--(define_cpu_unit "write_buf" "leon")
-+(define_cpu_unit "leon_memory" "leon")
-
- (define_insn_reservation "leon_load" 1
-- (and (eq_attr "cpu" "leon")
-- (eq_attr "type" "load,sload,fpload"))
-+ (and (eq_attr "cpu" "leon") (eq_attr "type" "load,sload"))
- "leon_memory")
-
--(define_insn_reservation "leon_store" 1
-- (and (eq_attr "cpu" "leon")
-- (eq_attr "type" "store,fpstore"))
-- "leon_memory+write_buf")
--
--(define_insn_reservation "leon_fp_alu" 1
-- (and (eq_attr "cpu" "leon")
-- (eq_attr "type" "fp,fpmove"))
-- "leon_fpalu, nothing")
-+;; Use a double reservation to work around the load pipeline hazard on UT699.
-+(define_insn_reservation "leon3_load" 1
-+ (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload"))
-+ "leon_memory*2")
-
--(define_insn_reservation "leon_fp_mult" 1
-- (and (eq_attr "cpu" "leon")
-- (eq_attr "type" "fpmul"))
-- "leon_fpmds, nothing")
-+(define_insn_reservation "leon_store" 2
-+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store"))
-+ "leon_memory*2")
-
--(define_insn_reservation "leon_fp_div" 16
-- (and (eq_attr "cpu" "leon")
-- (eq_attr "type" "fpdivs,fpdivd"))
-- "leon_fpmds, nothing*15")
-+;; This describes Gaisler Research's FPU
-
--(define_insn_reservation "leon_fp_sqrt" 23
-- (and (eq_attr "cpu" "leon")
-- (eq_attr "type" "fpsqrts,fpsqrtd"))
-- "leon_fpmds, nothing*21")
-+(define_automaton "grfpu")
-
-+(define_cpu_unit "grfpu_alu" "grfpu")
-+(define_cpu_unit "grfpu_ds" "grfpu")
-+
-+(define_insn_reservation "leon_fp_alu" 4
-+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul"))
-+ "grfpu_alu, nothing*3")
-+
-+(define_insn_reservation "leon_fp_divs" 16
-+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs"))
-+ "grfpu_ds*14, nothing*2")
-+
-+(define_insn_reservation "leon_fp_divd" 17
-+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd"))
-+ "grfpu_ds*15, nothing*2")
-+
-+(define_insn_reservation "leon_fp_sqrts" 24
-+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts"))
-+ "grfpu_ds*22, nothing*2")
-+
-+(define_insn_reservation "leon_fp_sqrtd" 25
-+ (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd"))
-+ "grfpu_ds*23, nothing*2")
-Index: gcc/config/sparc/sparc.h
-===================================================================
---- a/src/gcc/config/sparc/sparc.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sparc/sparc.h (.../branches/gcc-4_8-branch)
-@@ -136,21 +136,22 @@
- #define TARGET_CPU_supersparc 2
- #define TARGET_CPU_hypersparc 3
- #define TARGET_CPU_leon 4
--#define TARGET_CPU_sparclite 5
--#define TARGET_CPU_f930 5 /* alias */
--#define TARGET_CPU_f934 5 /* alias */
--#define TARGET_CPU_sparclite86x 6
--#define TARGET_CPU_sparclet 7
--#define TARGET_CPU_tsc701 7 /* alias */
--#define TARGET_CPU_v9 8 /* generic v9 implementation */
--#define TARGET_CPU_sparcv9 8 /* alias */
--#define TARGET_CPU_sparc64 8 /* alias */
--#define TARGET_CPU_ultrasparc 9
--#define TARGET_CPU_ultrasparc3 10
--#define TARGET_CPU_niagara 11
--#define TARGET_CPU_niagara2 12
--#define TARGET_CPU_niagara3 13
--#define TARGET_CPU_niagara4 14
-+#define TARGET_CPU_leon3 5
-+#define TARGET_CPU_sparclite 6
-+#define TARGET_CPU_f930 6 /* alias */
-+#define TARGET_CPU_f934 6 /* alias */
-+#define TARGET_CPU_sparclite86x 7
-+#define TARGET_CPU_sparclet 8
-+#define TARGET_CPU_tsc701 8 /* alias */
-+#define TARGET_CPU_v9 9 /* generic v9 implementation */
-+#define TARGET_CPU_sparcv9 9 /* alias */
-+#define TARGET_CPU_sparc64 9 /* alias */
-+#define TARGET_CPU_ultrasparc 10
-+#define TARGET_CPU_ultrasparc3 11
-+#define TARGET_CPU_niagara 12
-+#define TARGET_CPU_niagara2 13
-+#define TARGET_CPU_niagara3 14
-+#define TARGET_CPU_niagara4 15
-
- #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
- || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
-@@ -232,9 +233,10 @@
- #define ASM_CPU32_DEFAULT_SPEC ""
- #endif
-
--#if TARGET_CPU_DEFAULT == TARGET_CPU_leon
-+#if TARGET_CPU_DEFAULT == TARGET_CPU_leon \
-+ || TARGET_CPU_DEFAULT == TARGET_CPU_leon3
- #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
--#define ASM_CPU32_DEFAULT_SPEC ""
-+#define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
- #endif
-
- #endif
-@@ -282,6 +284,7 @@
- %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
- %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
- %{mcpu=leon:-D__leon__ -D__sparc_v8__} \
-+%{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
- %{mcpu=v9:-D__sparc_v9__} \
- %{mcpu=ultrasparc:-D__sparc_v9__} \
- %{mcpu=ultrasparc3:-D__sparc_v9__} \
-@@ -329,7 +332,8 @@
- %{mcpu=v8:-Av8} \
- %{mcpu=supersparc:-Av8} \
- %{mcpu=hypersparc:-Av8} \
--%{mcpu=leon:-Av8} \
-+%{mcpu=leon:" AS_LEON_FLAG "} \
-+%{mcpu=leon3:" AS_LEON_FLAG "} \
- %{mv8plus:-Av8plus} \
- %{mcpu=v9:-Av9} \
- %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
-@@ -1754,6 +1758,12 @@
- #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG
- #endif
-
-+#ifdef HAVE_AS_LEON
-+#define AS_LEON_FLAG "-Aleon"
-+#else
-+#define AS_LEON_FLAG "-Av8"
-+#endif
-+
- /* We use gcc _mcount for profiling. */
- #define NO_PROFILE_COUNTERS 0
-
-Index: gcc/config/i386/i386.h
-===================================================================
---- a/src/gcc/config/i386/i386.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/i386/i386.h (.../branches/gcc-4_8-branch)
-@@ -197,10 +197,10 @@
-
- /* Macros used in the machine description to test the flags. */
-
--/* configure can arrange to make this 2, to force a 486. */
-+/* configure can arrange to change it. */
-
- #ifndef TARGET_CPU_DEFAULT
--#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
-+#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC32
- #endif
-
- #ifndef TARGET_FPMATH_DEFAULT
-@@ -591,43 +591,6 @@
- /* Target Pragmas. */
- #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
-
--enum target_cpu_default
--{
-- TARGET_CPU_DEFAULT_generic = 0,
--
-- TARGET_CPU_DEFAULT_i386,
-- TARGET_CPU_DEFAULT_i486,
-- TARGET_CPU_DEFAULT_pentium,
-- TARGET_CPU_DEFAULT_pentium_mmx,
-- TARGET_CPU_DEFAULT_pentiumpro,
-- TARGET_CPU_DEFAULT_pentium2,
-- TARGET_CPU_DEFAULT_pentium3,
-- TARGET_CPU_DEFAULT_pentium4,
-- TARGET_CPU_DEFAULT_pentium_m,
-- TARGET_CPU_DEFAULT_prescott,
-- TARGET_CPU_DEFAULT_nocona,
-- TARGET_CPU_DEFAULT_core2,
-- TARGET_CPU_DEFAULT_corei7,
-- TARGET_CPU_DEFAULT_haswell,
-- TARGET_CPU_DEFAULT_atom,
--
-- TARGET_CPU_DEFAULT_geode,
-- TARGET_CPU_DEFAULT_k6,
-- TARGET_CPU_DEFAULT_k6_2,
-- TARGET_CPU_DEFAULT_k6_3,
-- TARGET_CPU_DEFAULT_athlon,
-- TARGET_CPU_DEFAULT_athlon_sse,
-- TARGET_CPU_DEFAULT_k8,
-- TARGET_CPU_DEFAULT_amdfam10,
-- TARGET_CPU_DEFAULT_bdver1,
-- TARGET_CPU_DEFAULT_bdver2,
-- TARGET_CPU_DEFAULT_bdver3,
-- TARGET_CPU_DEFAULT_btver1,
-- TARGET_CPU_DEFAULT_btver2,
--
-- TARGET_CPU_DEFAULT_max
--};
--
- #ifndef CC1_SPEC
- #define CC1_SPEC "%(cc1_cpu) "
- #endif
-@@ -2089,25 +2052,27 @@
- with x86-64 medium memory model */
- #define DEFAULT_LARGE_SECTION_THRESHOLD 65536
-
--/* Which processor to tune code generation for. */
-+/* Which processor to tune code generation for. These must be in sync
-+ with processor_target_table in i386.c. */
-
- enum processor_type
- {
-- PROCESSOR_I386 = 0, /* 80386 */
-+ PROCESSOR_GENERIC32 = 0,
-+ PROCESSOR_GENERIC64,
-+ PROCESSOR_I386, /* 80386 */
- PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
- PROCESSOR_PENTIUM,
- PROCESSOR_PENTIUMPRO,
-- PROCESSOR_GEODE,
-- PROCESSOR_K6,
-- PROCESSOR_ATHLON,
- PROCESSOR_PENTIUM4,
-- PROCESSOR_K8,
- PROCESSOR_NOCONA,
- PROCESSOR_CORE2,
- PROCESSOR_COREI7,
- PROCESSOR_HASWELL,
-- PROCESSOR_GENERIC32,
-- PROCESSOR_GENERIC64,
-+ PROCESSOR_ATOM,
-+ PROCESSOR_GEODE,
-+ PROCESSOR_K6,
-+ PROCESSOR_ATHLON,
-+ PROCESSOR_K8,
- PROCESSOR_AMDFAM10,
- PROCESSOR_BDVER1,
- PROCESSOR_BDVER2,
-@@ -2114,7 +2079,6 @@
- PROCESSOR_BDVER3,
- PROCESSOR_BTVER1,
- PROCESSOR_BTVER2,
-- PROCESSOR_ATOM,
- PROCESSOR_max
- };
-
-Index: gcc/config/i386/i386.md
-===================================================================
---- a/src/gcc/config/i386/i386.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/i386/i386.md (.../branches/gcc-4_8-branch)
-@@ -363,6 +363,13 @@
- (const_string "unknown")]
- (const_string "integer")))
-
-+;; The minimum required alignment of vector mode memory operands of the SSE
-+;; (non-VEX/EVEX) instruction in bits, if it is different from
-+;; GET_MODE_ALIGNMENT of the operand, otherwise 0. If an instruction has
-+;; multiple alternatives, this should be conservative maximum of those minimum
-+;; required alignments.
-+(define_attr "ssememalign" "" (const_int 0))
-+
- ;; The (bounding maximum) length of an instruction immediate.
- (define_attr "length_immediate" ""
- (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
-@@ -1570,7 +1577,7 @@
- split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);
-
- operands[1] = gen_lowpart (DImode, operands[2]);
-- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
-+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,
- GEN_INT (4)));
- })
-
-@@ -1587,7 +1594,7 @@
- split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);
-
- operands[1] = gen_lowpart (DImode, operands[2]);
-- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
-+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,
- GEN_INT (4)));
- })
-
-@@ -2715,7 +2722,20 @@
- "reload_completed"
- [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
- (set (mem:SF (reg:P SP_REG)) (match_dup 1))]
-- "operands[2] = GEN_INT (-GET_MODE_SIZE (<P:MODE>mode));")
-+{
-+ rtx op = XEXP (operands[0], 0);
-+ if (GET_CODE (op) == PRE_DEC)
-+ {
-+ gcc_assert (!TARGET_64BIT);
-+ op = GEN_INT (-4);
-+ }
-+ else
-+ {
-+ op = XEXP (XEXP (op, 1), 1);
-+ gcc_assert (CONST_INT_P (op));
-+ }
-+ operands[2] = op;
-+})
-
- (define_split
- [(set (match_operand:SF 0 "push_operand")
-@@ -5443,6 +5463,12 @@
- mode = SImode;
-
- ix86_split_lea_for_addr (curr_insn, operands, mode);
-+
-+ /* Zero-extend return register to DImode for zero-extended addresses. */
-+ if (mode != <MODE>mode)
-+ emit_insn (gen_zero_extendsidi2
-+ (operands[0], gen_lowpart (mode, operands[0])));
-+
- DONE;
- }
- [(set_attr "type" "lea")
-@@ -6589,7 +6615,7 @@
- (set_attr "use_carry" "1")
- (set_attr "mode" "<MODE>")])
-
--;; Overflow setting add and subtract instructions
-+;; Overflow setting add instructions
-
- (define_insn "*add<mode>3_cconly_overflow"
- [(set (reg:CCC FLAGS_REG)
-@@ -6604,43 +6630,31 @@
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
--(define_insn "*sub<mode>3_cconly_overflow"
-+(define_insn "*add<mode>3_cc_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
-- (minus:SWI
-- (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
-- (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
-- (match_dup 0)))]
-- ""
-- "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
-- [(set_attr "type" "icmp")
-- (set_attr "mode" "<MODE>")])
--
--(define_insn "*<plusminus_insn><mode>3_cc_overflow"
-- [(set (reg:CCC FLAGS_REG)
-- (compare:CCC
-- (plusminus:SWI
-- (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
-+ (plus:SWI
-+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
- (match_dup 1)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
-- (plusminus:SWI (match_dup 1) (match_dup 2)))]
-- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-- "<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
-+ (plus:SWI (match_dup 1) (match_dup 2)))]
-+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
-+ "add{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
--(define_insn "*<plusminus_insn>si3_zext_cc_overflow"
-+(define_insn "*addsi3_zext_cc_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
-- (plusminus:SI
-- (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
-+ (plus:SI
-+ (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "x86_64_general_operand" "rme"))
- (match_dup 1)))
- (set (match_operand:DI 0 "register_operand" "=r")
-- (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
-- "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
-- "<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"
-+ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
-+ "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
-+ "add{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "SI")])
-
-@@ -8012,7 +8026,18 @@
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
- (and:DI (match_dup 1) (match_dup 2)))]
-- "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
-+ "TARGET_64BIT
-+ && ix86_match_ccmode
-+ (insn,
-+ /* If we are going to emit andl instead of andq, and the operands[2]
-+ constant might have the SImode sign bit set, make sure the sign
-+ flag isn't tested, because the instruction will set the sign flag
-+ based on bit 31 rather than bit 63. If it isn't CONST_INT,
-+ conservatively assume it might have bit 31 set. */
-+ (satisfies_constraint_Z (operands[2])
-+ && (!CONST_INT_P (operands[2])
-+ || val_signbit_known_set_p (SImode, INTVAL (operands[2]))))
-+ ? CCZmode : CCNOmode)
- && ix86_binary_operator_ok (AND, DImode, operands)"
- "@
- and{l}\t{%k2, %k0|%k0, %k2}
-@@ -17569,7 +17594,13 @@
- (define_insn "trap"
- [(trap_if (const_int 1) (const_int 6))]
- ""
-- { return ASM_SHORT "0x0b0f"; }
-+{
-+#ifdef HAVE_AS_IX86_UD2
-+ return "ud2";
-+#else
-+ return ASM_SHORT "0x0b0f";
-+#endif
-+}
- [(set_attr "length" "2")])
-
- (define_expand "prefetch"
-Index: gcc/config/i386/f16cintrin.h
-===================================================================
---- a/src/gcc/config/i386/f16cintrin.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/i386/f16cintrin.h (.../branches/gcc-4_8-branch)
-@@ -35,7 +35,7 @@
- extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__))
- _cvtsh_ss (unsigned short __S)
- {
-- __v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 };
-+ __v8hi __H = __extension__ (__v8hi){ (short) __S, 0, 0, 0, 0, 0, 0, 0 };
- __v4sf __A = __builtin_ia32_vcvtph2ps (__H);
- return __builtin_ia32_vec_ext_v4sf (__A, 0);
- }
-Index: gcc/config/i386/t-rtems
-===================================================================
---- a/src/gcc/config/i386/t-rtems (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/i386/t-rtems (.../branches/gcc-4_8-branch)
-@@ -17,11 +17,10 @@
- # <http://www.gnu.org/licenses/>.
- #
-
--MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro \
--msoft-float
-+MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro msoft-float
- MULTILIB_DIRNAMES= m486 mpentium mpentiumpro soft-float
--MULTILIB_MATCHES = msoft-float=mno-m80387
--MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?mathlon
-+MULTILIB_MATCHES = msoft-float=mno-80387
-+MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?athlon
- MULTILIB_EXCEPTIONS = \
- mtune=pentium/*msoft-float* \
- mtune=pentiumpro/*msoft-float*
-Index: gcc/config/i386/winnt.c
-===================================================================
---- a/src/gcc/config/i386/winnt.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/i386/winnt.c (.../branches/gcc-4_8-branch)
-@@ -547,8 +547,9 @@
- sets 'discard' characteristic, rather than telling linker
- to warn of size or content mismatch, so do the same. */
- bool discard = (flags & SECTION_CODE)
-- || lookup_attribute ("selectany",
-- DECL_ATTRIBUTES (decl));
-+ || (TREE_CODE (decl) != IDENTIFIER_NODE
-+ && lookup_attribute ("selectany",
-+ DECL_ATTRIBUTES (decl)));
- fprintf (asm_out_file, "\t.linkonce %s\n",
- (discard ? "discard" : "same_size"));
- }
-Index: gcc/config/i386/sse.md
-===================================================================
---- a/src/gcc/config/i386/sse.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/i386/sse.md (.../branches/gcc-4_8-branch)
-@@ -605,6 +605,7 @@
- }
- [(set_attr "type" "ssemov")
- (set_attr "movu" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "prefix" "maybe_vex")
- (set (attr "mode")
- (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
-@@ -634,6 +635,7 @@
- }
- [(set_attr "type" "ssemov")
- (set_attr "movu" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "prefix" "maybe_vex")
- (set (attr "mode")
- (cond [(ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
-@@ -663,6 +665,7 @@
- }
- [(set_attr "type" "ssemov")
- (set_attr "movu" "1")
-+ (set_attr "ssememalign" "8")
- (set (attr "prefix_data16")
- (if_then_else
- (match_test "TARGET_AVX")
-@@ -696,6 +699,7 @@
- }
- [(set_attr "type" "ssemov")
- (set_attr "movu" "1")
-+ (set_attr "ssememalign" "8")
- (set (attr "prefix_data16")
- (if_then_else
- (match_test "TARGET_AVX")
-@@ -721,6 +725,7 @@
- "%vlddqu\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "movu" "1")
-+ (set_attr "ssememalign" "8")
- (set (attr "prefix_data16")
- (if_then_else
- (match_test "TARGET_AVX")
-@@ -1001,6 +1006,7 @@
- vrcpss\t{%1, %2, %0|%0, %2, %1}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sse")
-+ (set_attr "ssememalign" "32")
- (set_attr "atom_sse_attr" "rcp")
- (set_attr "btver2_sse_attr" "rcp")
- (set_attr "prefix" "orig,vex")
-@@ -1089,6 +1095,7 @@
- vrsqrtss\t{%1, %2, %0|%0, %2, %1}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sse")
-+ (set_attr "ssememalign" "32")
- (set_attr "prefix" "orig,vex")
- (set_attr "mode" "SF")])
-
-@@ -2844,6 +2851,7 @@
- "%vcvtdq2pd\t{%1, %0|%0, %q1}"
- [(set_attr "type" "ssecvt")
- (set_attr "prefix" "maybe_vex")
-+ (set_attr "ssememalign" "64")
- (set_attr "mode" "V2DF")])
-
- (define_insn "avx_cvtpd2dq256"
-@@ -3572,6 +3580,7 @@
- %vmovhps\t{%2, %0|%0, %2}"
- [(set_attr "isa" "noavx,avx,noavx,avx,*")
- (set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
- (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
-
-@@ -3617,6 +3626,7 @@
- %vmovlps\t{%2, %H0|%H0, %2}"
- [(set_attr "isa" "noavx,avx,noavx,avx,*")
- (set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
- (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
-
-@@ -3941,6 +3951,7 @@
- %vmovhlps\t{%1, %d0|%d0, %1}
- %vmovlps\t{%H1, %d0|%d0, %H1}"
- [(set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "V2SF,V4SF,V2SF")])
-
-@@ -3980,6 +3991,7 @@
- %vmovlps\t{%2, %H0|%H0, %2}"
- [(set_attr "isa" "noavx,avx,noavx,avx,*")
- (set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
- (set_attr "mode" "V2SF,V2SF,V4SF,V4SF,V2SF")])
-
-@@ -4033,6 +4045,7 @@
- %vmovlps\t{%2, %0|%0, %2}"
- [(set_attr "isa" "noavx,avx,noavx,avx,*")
- (set_attr "type" "sseshuf,sseshuf,ssemov,ssemov,ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "length_immediate" "1,1,*,*,*")
- (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
- (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
-@@ -4642,7 +4655,8 @@
- vmovlpd\t{%H1, %2, %0|%0, %2, %H1}
- %vmovhpd\t{%1, %0|%0, %1}"
- [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*")
-- (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")
-+ (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix_data16" "*,*,*,1,*,1")
- (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")
- (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")])
-@@ -4744,6 +4758,7 @@
- %vmovlpd\t{%2, %H0|%H0, %2}"
- [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*")
- (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix_data16" "*,*,*,1,*,1")
- (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")
- (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")])
-@@ -4982,6 +4997,7 @@
- movhlps\t{%1, %0|%0, %1}
- movlps\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "mode" "V2SF,V4SF,V2SF")])
-
- ;; Avoid combining registers from different units in a single alternative,
-@@ -5077,6 +5093,7 @@
- #"
- [(set_attr "isa" "noavx,avx,noavx,avx,*,*,*")
- (set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,fmov,imov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix_data16" "1,*,*,*,*,*,*")
- (set_attr "prefix" "orig,vex,orig,vex,*,*,*")
- (set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")])
-@@ -5145,6 +5162,7 @@
- (const_string "imov")
- ]
- (const_string "ssemov")))
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix_data16" "*,1,*,*,*,*,1,*,*,*,*")
- (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*,*,*")
- (set_attr "prefix" "maybe_vex,orig,vex,orig,vex,orig,orig,vex,*,*,*")
-@@ -5189,6 +5207,7 @@
- (const_string "1")
- (const_string "*")))
- (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex")
- (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
-
-@@ -8736,6 +8755,7 @@
- "TARGET_SSE4_1"
- "%vpmov<extsuffix>bw\t{%1, %0|%0, %q1}"
- [(set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
-@@ -8766,6 +8786,7 @@
- "TARGET_SSE4_1"
- "%vpmov<extsuffix>bd\t{%1, %0|%0, %k1}"
- [(set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "32")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
-@@ -8791,6 +8812,7 @@
- "TARGET_SSE4_1"
- "%vpmov<extsuffix>wd\t{%1, %0|%0, %q1}"
- [(set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
-@@ -8818,6 +8840,7 @@
- "TARGET_SSE4_1"
- "%vpmov<extsuffix>bq\t{%1, %0|%0, %w1}"
- [(set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "16")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
-@@ -8845,6 +8868,7 @@
- "TARGET_SSE4_1"
- "%vpmov<extsuffix>wq\t{%1, %0|%0, %k1}"
- [(set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "32")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
-@@ -8868,6 +8892,7 @@
- "TARGET_SSE4_1"
- "%vpmov<extsuffix>dq\t{%1, %0|%0, %q1}"
- [(set_attr "type" "ssemov")
-+ (set_attr "ssememalign" "64")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
-@@ -9151,6 +9176,7 @@
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "memory" "none,load")
- (set_attr "mode" "TI")])
-@@ -9213,6 +9239,7 @@
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "memory" "load")
- (set_attr "mode" "TI")])
-@@ -9240,6 +9267,7 @@
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "maybe_vex")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "btver2_decode" "vector")
- (set_attr "memory" "none,load")
-@@ -9267,6 +9295,7 @@
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "btver2_decode" "vector")
-@@ -9293,6 +9322,7 @@
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "memory" "none,load,none,load")
- (set_attr "btver2_decode" "vector,vector,vector,vector")
-@@ -9346,6 +9376,7 @@
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "memory" "none,load")
- (set_attr "mode" "TI")])
-@@ -9399,6 +9430,7 @@
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "memory" "load")
- (set_attr "mode" "TI")])
-@@ -9421,6 +9453,7 @@
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "memory" "none,load")
-@@ -9445,6 +9478,7 @@
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "memory" "none,load")
-@@ -9469,6 +9503,7 @@
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
-+ (set_attr "ssememalign" "8")
- (set_attr "length_immediate" "1")
- (set_attr "memory" "none,load,none,load")
- (set_attr "prefix" "maybe_vex")
-@@ -10213,7 +10248,6 @@
- [(set_attr "type" "ssecvt1")
- (set_attr "mode" "<MODE>")])
-
--;; scalar insns
- (define_expand "xop_vmfrcz<mode>2"
- [(set (match_operand:VF_128 0 "register_operand")
- (vec_merge:VF_128
-@@ -10220,14 +10254,12 @@
- (unspec:VF_128
- [(match_operand:VF_128 1 "nonimmediate_operand")]
- UNSPEC_FRCZ)
-- (match_dup 3)
-+ (match_dup 2)
- (const_int 1)))]
- "TARGET_XOP"
--{
-- operands[3] = CONST0_RTX (<MODE>mode);
--})
-+ "operands[2] = CONST0_RTX (<MODE>mode);")
-
--(define_insn "*xop_vmfrcz_<mode>"
-+(define_insn "*xop_vmfrcz<mode>2"
- [(set (match_operand:VF_128 0 "register_operand" "=x")
- (vec_merge:VF_128
- (unspec:VF_128
-Index: gcc/config/i386/xopintrin.h
-===================================================================
---- a/src/gcc/config/i386/xopintrin.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/i386/xopintrin.h (.../branches/gcc-4_8-branch)
-@@ -745,13 +745,17 @@
- extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
- _mm_frcz_ss (__m128 __A, __m128 __B)
- {
-- return (__m128) __builtin_ia32_vfrczss ((__v4sf)__A, (__v4sf)__B);
-+ return (__m128) __builtin_ia32_movss ((__v4sf)__A,
-+ (__v4sf)
-+ __builtin_ia32_vfrczss ((__v4sf)__B));
- }
-
- extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
- _mm_frcz_sd (__m128d __A, __m128d __B)
- {
-- return (__m128d) __builtin_ia32_vfrczsd ((__v2df)__A, (__v2df)__B);
-+ return (__m128d) __builtin_ia32_movsd ((__v2df)__A,
-+ (__v2df)
-+ __builtin_ia32_vfrczsd ((__v2df)__B));
- }
-
- extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-Index: gcc/config/i386/driver-i386.c
-===================================================================
---- a/src/gcc/config/i386/driver-i386.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/i386/driver-i386.c (.../branches/gcc-4_8-branch)
-@@ -126,6 +126,18 @@
- case 0x0c:
- level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
- break;
-+ case 0x0d:
-+ level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
-+ break;
-+ case 0x0e:
-+ level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
-+ break;
-+ case 0x21:
-+ level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
-+ break;
-+ case 0x24:
-+ level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
-+ break;
- case 0x2c:
- level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
- break;
-@@ -162,6 +174,9 @@
- case 0x45:
- level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
- break;
-+ case 0x48:
-+ level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
-+ break;
- case 0x49:
- if (xeon_mp)
- break;
-@@ -203,6 +218,9 @@
- case 0x7f:
- level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
- break;
-+ case 0x80:
-+ level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
-+ break;
- case 0x82:
- level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
- break;
-@@ -470,6 +488,28 @@
- has_xsaveopt = eax & bit_XSAVEOPT;
- }
-
-+ /* Check cpuid level of extended features. */
-+ __cpuid (0x80000000, ext_level, ebx, ecx, edx);
-+
-+ if (ext_level > 0x80000000)
-+ {
-+ __cpuid (0x80000001, eax, ebx, ecx, edx);
-+
-+ has_lahf_lm = ecx & bit_LAHF_LM;
-+ has_sse4a = ecx & bit_SSE4a;
-+ has_abm = ecx & bit_ABM;
-+ has_lwp = ecx & bit_LWP;
-+ has_fma4 = ecx & bit_FMA4;
-+ has_xop = ecx & bit_XOP;
-+ has_tbm = ecx & bit_TBM;
-+ has_lzcnt = ecx & bit_LZCNT;
-+ has_prfchw = ecx & bit_PRFCHW;
-+
-+ has_longmode = edx & bit_LM;
-+ has_3dnowp = edx & bit_3DNOWP;
-+ has_3dnow = edx & bit_3DNOW;
-+ }
-+
- /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */
- #define XCR_XFEATURE_ENABLED_MASK 0x0
- #define XSTATE_FP 0x1
-@@ -488,33 +528,12 @@
- has_avx2 = 0;
- has_fma = 0;
- has_fma4 = 0;
-+ has_f16c = 0;
- has_xop = 0;
- has_xsave = 0;
- has_xsaveopt = 0;
- }
-
-- /* Check cpuid level of extended features. */
-- __cpuid (0x80000000, ext_level, ebx, ecx, edx);
--
-- if (ext_level > 0x80000000)
-- {
-- __cpuid (0x80000001, eax, ebx, ecx, edx);
--
-- has_lahf_lm = ecx & bit_LAHF_LM;
-- has_sse4a = ecx & bit_SSE4a;
-- has_abm = ecx & bit_ABM;
-- has_lwp = ecx & bit_LWP;
-- has_fma4 = ecx & bit_FMA4;
-- has_xop = ecx & bit_XOP;
-- has_tbm = ecx & bit_TBM;
-- has_lzcnt = ecx & bit_LZCNT;
-- has_prfchw = ecx & bit_PRFCHW;
--
-- has_longmode = edx & bit_LM;
-- has_3dnowp = edx & bit_3DNOWP;
-- has_3dnow = edx & bit_3DNOW;
-- }
--
- if (!arch)
- {
- if (vendor == signature_AMD_ebx
-Index: gcc/config/i386/i386.c
-===================================================================
---- a/src/gcc/config/i386/i386.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/i386/i386.c (.../branches/gcc-4_8-branch)
-@@ -1378,7 +1378,7 @@
- 8, /* MMX or SSE register to integer */
- 8, /* size of l1 cache. */
- 1024, /* size of l2 cache. */
-- 128, /* size of prefetch block */
-+ 64, /* size of prefetch block */
- 8, /* number of parallel prefetches */
- 1, /* Branch cost */
- COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
-@@ -1894,10 +1894,10 @@
- m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_AMDFAM10 | m_BDVER | m_GENERIC,
-
- /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
-- m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER,
-+ m_COREI7 | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER,
-
- /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
-- m_COREI7 | m_BDVER,
-+ m_COREI7 | m_HASWELL| m_BDVER,
-
- /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
- m_BDVER ,
-@@ -2409,6 +2409,7 @@
- /* Processor target table, indexed by processor number */
- struct ptt
- {
-+ const char *const name; /* processor name */
- const struct processor_costs *cost; /* Processor costs */
- const int align_loop; /* Default alignments. */
- const int align_loop_max_skip;
-@@ -2417,67 +2418,32 @@
- const int align_func;
- };
-
-+/* This table must be in sync with enum processor_type in i386.h. */
- static const struct ptt processor_target_table[PROCESSOR_max] =
- {
-- {&i386_cost, 4, 3, 4, 3, 4},
-- {&i486_cost, 16, 15, 16, 15, 16},
-- {&pentium_cost, 16, 7, 16, 7, 16},
-- {&pentiumpro_cost, 16, 15, 16, 10, 16},
-- {&geode_cost, 0, 0, 0, 0, 0},
-- {&k6_cost, 32, 7, 32, 7, 32},
-- {&athlon_cost, 16, 7, 16, 7, 16},
-- {&pentium4_cost, 0, 0, 0, 0, 0},
-- {&k8_cost, 16, 7, 16, 7, 16},
-- {&nocona_cost, 0, 0, 0, 0, 0},
-- /* Core 2 */
-- {&core_cost, 16, 10, 16, 10, 16},
-- /* Core i7 */
-- {&core_cost, 16, 10, 16, 10, 16},
-- /* Core avx2 */
-- {&core_cost, 16, 10, 16, 10, 16},
-- {&generic32_cost, 16, 7, 16, 7, 16},
-- {&generic64_cost, 16, 10, 16, 10, 16},
-- {&amdfam10_cost, 32, 24, 32, 7, 32},
-- {&bdver1_cost, 16, 10, 16, 7, 11},
-- {&bdver2_cost, 16, 10, 16, 7, 11},
-- {&bdver3_cost, 16, 10, 16, 7, 11},
-- {&btver1_cost, 16, 10, 16, 7, 11},
-- {&btver2_cost, 16, 10, 16, 7, 11},
-- {&atom_cost, 16, 15, 16, 7, 16}
-+ {"generic", &generic32_cost, 16, 7, 16, 7, 16},
-+ {"generic", &generic64_cost, 16, 10, 16, 10, 16},
-+ {"i386", &i386_cost, 4, 3, 4, 3, 4},
-+ {"i486", &i486_cost, 16, 15, 16, 15, 16},
-+ {"pentium", &pentium_cost, 16, 7, 16, 7, 16},
-+ {"pentiumpro", &pentiumpro_cost, 16, 15, 16, 10, 16},
-+ {"pentium4", &pentium4_cost, 0, 0, 0, 0, 0},
-+ {"nocona", &nocona_cost, 0, 0, 0, 0, 0},
-+ {"core2", &core_cost, 16, 10, 16, 10, 16},
-+ {"corei7", &core_cost, 16, 10, 16, 10, 16},
-+ {"core-avx2", &core_cost, 16, 10, 16, 10, 16},
-+ {"atom", &atom_cost, 16, 15, 16, 7, 16},
-+ {"geode", &geode_cost, 0, 0, 0, 0, 0},
-+ {"k6", &k6_cost, 32, 7, 32, 7, 32},
-+ {"athlon", &athlon_cost, 16, 7, 16, 7, 16},
-+ {"k8", &k8_cost, 16, 7, 16, 7, 16},
-+ {"amdfam10", &amdfam10_cost, 32, 24, 32, 7, 32},
-+ {"bdver1", &bdver1_cost, 16, 10, 16, 7, 11},
-+ {"bdver2", &bdver2_cost, 16, 10, 16, 7, 11},
-+ {"bdver3", &bdver3_cost, 16, 10, 16, 7, 11},
-+ {"btver1", &btver1_cost, 16, 10, 16, 7, 11},
-+ {"btver2", &btver2_cost, 16, 10, 16, 7, 11}
- };
--
--static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
--{
-- "generic",
-- "i386",
-- "i486",
-- "pentium",
-- "pentium-mmx",
-- "pentiumpro",
-- "pentium2",
-- "pentium3",
-- "pentium4",
-- "pentium-m",
-- "prescott",
-- "nocona",
-- "core2",
-- "corei7",
-- "core-avx2",
-- "atom",
-- "geode",
-- "k6",
-- "k6-2",
-- "k6-3",
-- "athlon",
-- "athlon-4",
-- "k8",
-- "amdfam10",
-- "bdver1",
-- "bdver2",
-- "bdver3",
-- "btver1",
-- "btver2"
--};
-
- static bool
- gate_insert_vzeroupper (void)
-@@ -2920,7 +2886,7 @@
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
- | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
- | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
-- | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
-+ | PTA_FMA | PTA_MOVBE | PTA_HLE | PTA_FXSR | PTA_XSAVE
- | PTA_XSAVEOPT},
- {"atom", PROCESSOR_ATOM, CPU_ATOM,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-@@ -2983,7 +2949,7 @@
- {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
-+ | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
- | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
- | PTA_XSAVEOPT},
-@@ -3125,7 +3091,8 @@
- ix86_tune_string = ix86_arch_string;
- if (!ix86_tune_string)
- {
-- ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
-+ ix86_tune_string
-+ = processor_target_table[TARGET_CPU_DEFAULT].name;
- ix86_tune_defaulted = 1;
- }
-
-@@ -4078,19 +4045,15 @@
- = ix86_target_string (ptr->x_ix86_isa_flags, ptr->x_target_flags,
- NULL, NULL, ptr->x_ix86_fpmath, false);
-
-+ gcc_assert (ptr->arch < PROCESSOR_max);
- fprintf (file, "%*sarch = %d (%s)\n",
- indent, "",
-- ptr->arch,
-- ((ptr->arch < TARGET_CPU_DEFAULT_max)
-- ? cpu_names[ptr->arch]
-- : "<unknown>"));
-+ ptr->arch, processor_target_table[ptr->arch].name);
-
-+ gcc_assert (ptr->tune < PROCESSOR_max);
- fprintf (file, "%*stune = %d (%s)\n",
- indent, "",
-- ptr->tune,
-- ((ptr->tune < TARGET_CPU_DEFAULT_max)
-- ? cpu_names[ptr->tune]
-- : "<unknown>"));
-+ ptr->tune, processor_target_table[ptr->tune].name);
-
- fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
-
-@@ -5213,7 +5176,12 @@
- /* Use register calling convention for local functions when possible. */
- if (decl
- && TREE_CODE (decl) == FUNCTION_DECL
-- && optimize
-+ /* Caller and callee must agree on the calling convention, so
-+ checking here just optimize means that with
-+ __attribute__((optimize (...))) caller could use regparm convention
-+ and callee not, or vice versa. Instead look at whether the callee
-+ is optimized or not. */
-+ && opt_for_fn (decl, optimize)
- && !(profile_flag && !flag_fentry))
- {
- /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
-@@ -5409,6 +5377,17 @@
- bool win;
- int j;
-
-+ /* For pre-AVX disallow unaligned loads/stores where the
-+ instructions don't support it. */
-+ if (!TARGET_AVX
-+ && VECTOR_MODE_P (GET_MODE (op))
-+ && misaligned_operand (op, GET_MODE (op)))
-+ {
-+ int min_align = get_attr_ssememalign (insn);
-+ if (min_align == 0)
-+ return false;
-+ }
-+
- /* A unary operator may be accepted by the predicate, but it
- is irrelevant for matching constraints. */
- if (UNARY_P (op))
-@@ -5747,9 +5726,9 @@
- cum->nregs = 0;
- cum->sse_nregs = 0;
- cum->mmx_nregs = 0;
-- cum->warn_avx = 0;
-- cum->warn_sse = 0;
-- cum->warn_mmx = 0;
-+ cum->warn_avx = false;
-+ cum->warn_sse = false;
-+ cum->warn_mmx = false;
- return;
- }
-
-@@ -5790,10 +5769,14 @@
-
- The midde-end can't deal with the vector types > 16 bytes. In this
- case, we return the original mode and warn ABI change if CUM isn't
-- NULL. */
-+ NULL.
-
-+ If INT_RETURN is true, warn ABI change if the vector mode isn't
-+ available for function return value. */
-+
- static enum machine_mode
--type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum)
-+type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
-+ bool in_return)
- {
- enum machine_mode mode = TYPE_MODE (type);
-
-@@ -5819,33 +5802,61 @@
- if (size == 32 && !TARGET_AVX)
- {
- static bool warnedavx;
-+ static bool warnedavx_ret;
-
-- if (cum
-- && !warnedavx
-- && cum->warn_avx)
-+ if (cum && cum->warn_avx && !warnedavx)
- {
-- warnedavx = true;
-- warning (0, "AVX vector argument without AVX "
-- "enabled changes the ABI");
-+ if (warning (OPT_Wpsabi, "AVX vector argument "
-+ "without AVX enabled changes the ABI"))
-+ warnedavx = true;
- }
-+ else if (in_return && !warnedavx_ret)
-+ {
-+ if (warning (OPT_Wpsabi, "AVX vector return "
-+ "without AVX enabled changes the ABI"))
-+ warnedavx_ret = true;
-+ }
-+
- return TYPE_MODE (type);
- }
-- else if ((size == 8 || size == 16) && !TARGET_SSE)
-+ else if (((size == 8 && TARGET_64BIT) || size == 16)
-+ && !TARGET_SSE)
- {
- static bool warnedsse;
-+ static bool warnedsse_ret;
-
-- if (cum
-- && !warnedsse
-- && cum->warn_sse)
-+ if (cum && cum->warn_sse && !warnedsse)
- {
-- warnedsse = true;
-- warning (0, "SSE vector argument without SSE "
-- "enabled changes the ABI");
-+ if (warning (OPT_Wpsabi, "SSE vector argument "
-+ "without SSE enabled changes the ABI"))
-+ warnedsse = true;
- }
-- return mode;
-+ else if (!TARGET_64BIT && in_return && !warnedsse_ret)
-+ {
-+ if (warning (OPT_Wpsabi, "SSE vector return "
-+ "without SSE enabled changes the ABI"))
-+ warnedsse_ret = true;
-+ }
- }
-- else
-- return mode;
-+ else if ((size == 8 && !TARGET_64BIT) && !TARGET_MMX)
-+ {
-+ static bool warnedmmx;
-+ static bool warnedmmx_ret;
-+
-+ if (cum && cum->warn_mmx && !warnedmmx)
-+ {
-+ if (warning (OPT_Wpsabi, "MMX vector argument "
-+ "without MMX enabled changes the ABI"))
-+ warnedmmx = true;
-+ }
-+ else if (in_return && !warnedmmx_ret)
-+ {
-+ if (warning (OPT_Wpsabi, "MMX vector return "
-+ "without MMX enabled changes the ABI"))
-+ warnedmmx_ret = true;
-+ }
-+ }
-+ return mode;
- }
-
- gcc_unreachable ();
-@@ -6190,25 +6201,28 @@
- case CHImode:
- case CQImode:
- {
-- int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
-+ int size = bit_offset + (int) GET_MODE_BITSIZE (mode);
-
-- if (size <= 32)
-+ /* Analyze last 128 bits only. */
-+ size = (size - 1) & 0x7f;
-+
-+ if (size < 32)
- {
- classes[0] = X86_64_INTEGERSI_CLASS;
- return 1;
- }
-- else if (size <= 64)
-+ else if (size < 64)
- {
- classes[0] = X86_64_INTEGER_CLASS;
- return 1;
- }
-- else if (size <= 64+32)
-+ else if (size < 64+32)
- {
- classes[0] = X86_64_INTEGER_CLASS;
- classes[1] = X86_64_INTEGERSI_CLASS;
- return 2;
- }
-- else if (size <= 64+64)
-+ else if (size < 64+64)
- {
- classes[0] = classes[1] = X86_64_INTEGER_CLASS;
- return 2;
-@@ -6475,7 +6489,7 @@
- if (n == 2
- && regclass[0] == X86_64_INTEGER_CLASS
- && regclass[1] == X86_64_INTEGER_CLASS
-- && (mode == CDImode || mode == TImode || mode == TFmode)
-+ && (mode == CDImode || mode == TImode)
- && intreg[0] + 1 == intreg[1])
- return gen_rtx_REG (mode, intreg[0]);
-
-@@ -6725,7 +6739,7 @@
- words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-
- if (type)
-- mode = type_natural_mode (type, NULL);
-+ mode = type_natural_mode (type, NULL, false);
-
- if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
- function_arg_advance_ms_64 (cum, bytes, words);
-@@ -6753,8 +6767,6 @@
- enum machine_mode orig_mode, const_tree type,
- HOST_WIDE_INT bytes, HOST_WIDE_INT words)
- {
-- static bool warnedsse, warnedmmx;
--
- /* Avoid the AL settings for the Unix64 ABI. */
- if (mode == VOIDmode)
- return constm1_rtx;
-@@ -6811,12 +6823,6 @@
- case V2DFmode:
- if (!type || !AGGREGATE_TYPE_P (type))
- {
-- if (!TARGET_SSE && !warnedsse && cum->warn_sse)
-- {
-- warnedsse = true;
-- warning (0, "SSE vector argument without SSE enabled "
-- "changes the ABI");
-- }
- if (cum->sse_nregs)
- return gen_reg_or_parallel (mode, orig_mode,
- cum->sse_regno + FIRST_SSE_REG);
-@@ -6849,12 +6855,6 @@
- case V1DImode:
- if (!type || !AGGREGATE_TYPE_P (type))
- {
-- if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
-- {
-- warnedmmx = true;
-- warning (0, "MMX vector argument without MMX enabled "
-- "changes the ABI");
-- }
- if (cum->mmx_nregs)
- return gen_reg_or_parallel (mode, orig_mode,
- cum->mmx_regno + FIRST_MMX_REG);
-@@ -6977,7 +6977,7 @@
- /* To simplify the code below, represent vector types with a vector mode
- even if MMX/SSE are not active. */
- if (type && TREE_CODE (type) == VECTOR_TYPE)
-- mode = type_natural_mode (type, cum);
-+ mode = type_natural_mode (type, cum, false);
-
- if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
- arg = function_arg_ms_64 (cum, mode, omode, named, bytes);
-@@ -7235,9 +7235,15 @@
- switch (regno)
- {
- case AX_REG:
-+ case DX_REG:
- return true;
-+ case DI_REG:
-+ case SI_REG:
-+ return TARGET_64BIT && ix86_abi != MS_ABI;
-
-- case FIRST_FLOAT_REG:
-+ /* Complex values are returned in %st(0)/%st(1) pair. */
-+ case ST0_REG:
-+ case ST1_REG:
- /* TODO: The function should depend on current function ABI but
- builtins.c would need updating then. Therefore we use the
- default ABI. */
-@@ -7245,10 +7251,12 @@
- return false;
- return TARGET_FLOAT_RETURNS_IN_80387;
-
-- case FIRST_SSE_REG:
-+ /* Complex values are returned in %xmm0/%xmm1 pair. */
-+ case XMM0_REG:
-+ case XMM1_REG:
- return TARGET_SSE;
-
-- case FIRST_MMX_REG:
-+ case MM0_REG:
- if (TARGET_MACHO || TARGET_64BIT)
- return false;
- return TARGET_MMX;
-@@ -7420,7 +7428,7 @@
- enum machine_mode mode, orig_mode;
-
- orig_mode = TYPE_MODE (valtype);
-- mode = type_natural_mode (valtype, NULL);
-+ mode = type_natural_mode (valtype, NULL, true);
- return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
- }
-
-@@ -7535,7 +7543,7 @@
- #ifdef SUBTARGET_RETURN_IN_MEMORY
- return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
- #else
-- const enum machine_mode mode = type_natural_mode (type, NULL);
-+ const enum machine_mode mode = type_natural_mode (type, NULL, true);
-
- if (TARGET_64BIT)
- {
-@@ -7549,52 +7557,6 @@
- #endif
- }
-
--/* When returning SSE vector types, we have a choice of either
-- (1) being abi incompatible with a -march switch, or
-- (2) generating an error.
-- Given no good solution, I think the safest thing is one warning.
-- The user won't be able to use -Werror, but....
--
-- Choose the STRUCT_VALUE_RTX hook because that's (at present) only
-- called in response to actually generating a caller or callee that
-- uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
-- via aggregate_value_p for general type probing from tree-ssa. */
--
--static rtx
--ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
--{
-- static bool warnedsse, warnedmmx;
--
-- if (!TARGET_64BIT && type)
-- {
-- /* Look at the return type of the function, not the function type. */
-- enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
--
-- if (!TARGET_SSE && !warnedsse)
-- {
-- if (mode == TImode
-- || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
-- {
-- warnedsse = true;
-- warning (0, "SSE vector return without SSE enabled "
-- "changes the ABI");
-- }
-- }
--
-- if (!TARGET_MMX && !warnedmmx)
-- {
-- if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
-- {
-- warnedmmx = true;
-- warning (0, "MMX vector return without MMX enabled "
-- "changes the ABI");
-- }
-- }
-- }
--
-- return NULL;
--}
--
-
- /* Create the va_list data type. */
-
-@@ -8019,7 +7981,7 @@
- size = int_size_in_bytes (type);
- rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-
-- nat_mode = type_natural_mode (type, NULL);
-+ nat_mode = type_natural_mode (type, NULL, false);
- switch (nat_mode)
- {
- case V8SFmode:
-@@ -10560,18 +10522,20 @@
- }
- m->fs.sp_offset += allocate;
-
-+ /* Use stack_pointer_rtx for relative addressing so that code
-+ works for realigned stack, too. */
- if (r10_live && eax_live)
- {
-- t = choose_baseaddr (m->fs.sp_offset - allocate);
-+ t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax);
- emit_move_insn (gen_rtx_REG (word_mode, R10_REG),
- gen_frame_mem (word_mode, t));
-- t = choose_baseaddr (m->fs.sp_offset - allocate - UNITS_PER_WORD);
-+ t = plus_constant (Pmode, t, UNITS_PER_WORD);
- emit_move_insn (gen_rtx_REG (word_mode, AX_REG),
- gen_frame_mem (word_mode, t));
- }
- else if (eax_live || r10_live)
- {
-- t = choose_baseaddr (m->fs.sp_offset - allocate);
-+ t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax);
- emit_move_insn (gen_rtx_REG (word_mode,
- (eax_live ? AX_REG : R10_REG)),
- gen_frame_mem (word_mode, t));
-@@ -11164,8 +11128,9 @@
- m->fs.cfa_offset -= UNITS_PER_WORD;
- m->fs.sp_offset -= UNITS_PER_WORD;
-
-- add_reg_note (insn, REG_CFA_ADJUST_CFA,
-- copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
-+ rtx x = plus_constant (Pmode, stack_pointer_rtx, UNITS_PER_WORD);
-+ x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
-+ add_reg_note (insn, REG_CFA_ADJUST_CFA, x);
- add_reg_note (insn, REG_CFA_REGISTER,
- gen_rtx_SET (VOIDmode, ecx, pc_rtx));
- RTX_FRAME_RELATED_P (insn) = 1;
-@@ -11561,30 +11526,6 @@
- }
- }
-
--/* Determine if op is suitable SUBREG RTX for address. */
--
--static bool
--ix86_address_subreg_operand (rtx op)
--{
-- enum machine_mode mode;
--
-- if (!REG_P (op))
-- return false;
--
-- mode = GET_MODE (op);
--
-- if (GET_MODE_CLASS (mode) != MODE_INT)
-- return false;
--
-- /* Don't allow SUBREGs that span more than a word. It can lead to spill
-- failures when the register is one word out of a two word structure. */
-- if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
-- return false;
--
-- /* Allow only SUBREGs of non-eliminable hard registers. */
-- return register_no_elim_operand (op, mode);
--}
--
- /* Extract the parts of an RTL expression that is a valid memory address
- for an instruction. Return 0 if the structure of the address is
- grossly off. Return -1 if the address contains ASHIFT, so it is not
-@@ -11641,7 +11582,7 @@
- base = addr;
- else if (GET_CODE (addr) == SUBREG)
- {
-- if (ix86_address_subreg_operand (SUBREG_REG (addr)))
-+ if (REG_P (SUBREG_REG (addr)))
- base = addr;
- else
- return 0;
-@@ -11705,7 +11646,7 @@
- break;
-
- case SUBREG:
-- if (!ix86_address_subreg_operand (SUBREG_REG (op)))
-+ if (!REG_P (SUBREG_REG (op)))
- return 0;
- /* FALLTHRU */
-
-@@ -11750,19 +11691,6 @@
- scale = 1 << scale;
- retval = -1;
- }
-- else if (CONST_INT_P (addr))
-- {
-- if (!x86_64_immediate_operand (addr, VOIDmode))
-- return 0;
--
-- /* Constant addresses are sign extended to 64bit, we have to
-- prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
-- if (TARGET_X32
-- && val_signbit_known_set_p (SImode, INTVAL (addr)))
-- return 0;
--
-- disp = addr;
-- }
- else
- disp = addr; /* displacement */
-
-@@ -11771,18 +11699,12 @@
- if (REG_P (index))
- ;
- else if (GET_CODE (index) == SUBREG
-- && ix86_address_subreg_operand (SUBREG_REG (index)))
-+ && REG_P (SUBREG_REG (index)))
- ;
- else
- return 0;
- }
-
--/* Address override works only on the (%reg) part of %fs:(%reg). */
-- if (seg != SEG_DEFAULT
-- && ((base && GET_MODE (base) != word_mode)
-- || (index && GET_MODE (index) != word_mode)))
-- return 0;
--
- /* Extract the integral value of scale. */
- if (scale_rtx)
- {
-@@ -12258,6 +12180,45 @@
- return false;
- }
-
-+/* Determine if op is suitable RTX for an address register.
-+ Return naked register if a register or a register subreg is
-+ found, otherwise return NULL_RTX. */
-+
-+static rtx
-+ix86_validate_address_register (rtx op)
-+{
-+ enum machine_mode mode = GET_MODE (op);
-+
-+ /* Only SImode or DImode registers can form the address. */
-+ if (mode != SImode && mode != DImode)
-+ return NULL_RTX;
-+
-+ if (REG_P (op))
-+ return op;
-+ else if (GET_CODE (op) == SUBREG)
-+ {
-+ rtx reg = SUBREG_REG (op);
-+
-+ if (!REG_P (reg))
-+ return NULL_RTX;
-+
-+ mode = GET_MODE (reg);
-+
-+ /* Don't allow SUBREGs that span more than a word. It can
-+ lead to spill failures when the register is one word out
-+ of a two word structure. */
-+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
-+ return NULL_RTX;
-+
-+ /* Allow only SUBREGs of non-eliminable hard registers. */
-+ if (register_no_elim_operand (reg, mode))
-+ return reg;
-+ }
-+
-+ /* Op is not a register. */
-+ return NULL_RTX;
-+}
-+
- /* Recognizes RTL expressions that are valid memory addresses for an
- instruction. The MODE argument is the machine mode for the MEM
- expression that wants to use this address.
-@@ -12273,6 +12234,7 @@
- struct ix86_address parts;
- rtx base, index, disp;
- HOST_WIDE_INT scale;
-+ enum ix86_address_seg seg;
-
- if (ix86_decompose_address (addr, &parts) <= 0)
- /* Decomposition failed. */
-@@ -12282,23 +12244,16 @@
- index = parts.index;
- disp = parts.disp;
- scale = parts.scale;
-+ seg = parts.seg;
-
- /* Validate base register. */
- if (base)
- {
-- rtx reg;
-+ rtx reg = ix86_validate_address_register (base);
-
-- if (REG_P (base))
-- reg = base;
-- else if (GET_CODE (base) == SUBREG && REG_P (SUBREG_REG (base)))
-- reg = SUBREG_REG (base);
-- else
-- /* Base is not a register. */
-+ if (reg == NULL_RTX)
- return false;
-
-- if (GET_MODE (base) != SImode && GET_MODE (base) != DImode)
-- return false;
--
- if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
- || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
- /* Base is not valid. */
-@@ -12308,19 +12263,11 @@
- /* Validate index register. */
- if (index)
- {
-- rtx reg;
-+ rtx reg = ix86_validate_address_register (index);
-
-- if (REG_P (index))
-- reg = index;
-- else if (GET_CODE (index) == SUBREG && REG_P (SUBREG_REG (index)))
-- reg = SUBREG_REG (index);
-- else
-- /* Index is not a register. */
-+ if (reg == NULL_RTX)
- return false;
-
-- if (GET_MODE (index) != SImode && GET_MODE (index) != DImode)
-- return false;
--
- if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
- || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
- /* Index is not valid. */
-@@ -12332,6 +12279,12 @@
- && GET_MODE (base) != GET_MODE (index))
- return false;
-
-+ /* Address override works only on the (%reg) part of %fs:(%reg). */
-+ if (seg != SEG_DEFAULT
-+ && ((base && GET_MODE (base) != word_mode)
-+ || (index && GET_MODE (index) != word_mode)))
-+ return false;
-+
- /* Validate scale factor. */
- if (scale != 1)
- {
-@@ -12453,6 +12406,12 @@
- && !x86_64_immediate_operand (disp, VOIDmode))
- /* Displacement is out of range. */
- return false;
-+ /* In x32 mode, constant addresses are sign extended to 64bit, so
-+ we have to prevent addresses from 0x80000000 to 0xffffffff. */
-+ else if (TARGET_X32 && !(index || base)
-+ && CONST_INT_P (disp)
-+ && val_signbit_known_set_p (SImode, INTVAL (disp)))
-+ return false;
- }
-
- /* Everything looks valid. */
-@@ -13817,8 +13776,6 @@
- Those same assemblers have the same but opposite lossage on cmov. */
- if (mode == CCmode)
- suffix = fp ? "nbe" : "a";
-- else if (mode == CCCmode)
-- suffix = "b";
- else
- gcc_unreachable ();
- break;
-@@ -13840,8 +13797,12 @@
- }
- break;
- case LTU:
-- gcc_assert (mode == CCmode || mode == CCCmode);
-- suffix = "b";
-+ if (mode == CCmode)
-+ suffix = "b";
-+ else if (mode == CCCmode)
-+ suffix = "c";
-+ else
-+ gcc_unreachable ();
- break;
- case GE:
- switch (mode)
-@@ -13861,9 +13822,12 @@
- }
- break;
- case GEU:
-- /* ??? As above. */
-- gcc_assert (mode == CCmode || mode == CCCmode);
-- suffix = fp ? "nb" : "ae";
-+ if (mode == CCmode)
-+ suffix = fp ? "nb" : "ae";
-+ else if (mode == CCCmode)
-+ suffix = "nc";
-+ else
-+ gcc_unreachable ();
- break;
- case LE:
- gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
-@@ -13870,11 +13834,8 @@
- suffix = "le";
- break;
- case LEU:
-- /* ??? As above. */
- if (mode == CCmode)
- suffix = "be";
-- else if (mode == CCCmode)
-- suffix = fp ? "nb" : "ae";
- else
- gcc_unreachable ();
- break;
-@@ -15340,7 +15301,7 @@
- rtx arg = XEXP (XEXP (link, 0), 0);
-
- if (ix86_check_avx256_register (&arg, NULL))
-- return AVX_U128_ANY;
-+ return AVX_U128_DIRTY;
- }
- }
-
-@@ -15460,8 +15421,8 @@
- {
- bool avx_reg256_found = false;
- note_stores (pat, ix86_check_avx256_stores, &avx_reg256_found);
-- if (!avx_reg256_found)
-- return AVX_U128_CLEAN;
-+
-+ return avx_reg256_found ? AVX_U128_DIRTY : AVX_U128_CLEAN;
- }
-
- /* Otherwise, return current mode. Remember that if insn
-@@ -17350,10 +17311,20 @@
- if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
- return false;
-
-- /* Check it is correct to split here. */
-- if (!ix86_ok_to_clobber_flags(insn))
-+ /* The "at least two components" test below might not catch simple
-+ move or zero extension insns if parts.base is non-NULL and parts.disp
-+ is const0_rtx as the only components in the address, e.g. if the
-+ register is %rbp or %r13. As this test is much cheaper and moves or
-+ zero extensions are the common case, do this check first. */
-+ if (REG_P (operands[1])
-+ || (SImode_address_operand (operands[1], VOIDmode)
-+ && REG_P (XEXP (operands[1], 0))))
- return false;
-
-+ /* Check if it is OK to split here. */
-+ if (!ix86_ok_to_clobber_flags (insn))
-+ return false;
-+
- ok = ix86_decompose_address (operands[1], &parts);
- gcc_assert (ok);
-
-@@ -18486,12 +18457,7 @@
- return CCmode;
- case GTU: /* CF=0 & ZF=0 */
- case LEU: /* CF=1 | ZF=1 */
-- /* Detect overflow checks. They need just the carry flag. */
-- if (GET_CODE (op0) == MINUS
-- && rtx_equal_p (op1, XEXP (op0, 0)))
-- return CCCmode;
-- else
-- return CCmode;
-+ return CCmode;
- /* Codes possibly doable only with sign flag when
- comparing against zero. */
- case GE: /* SF=OF or SF=0 */
-@@ -20500,7 +20466,7 @@
- return;
-
- case V8SFmode:
-- mask = gen_lowpart (V8SFmode, mask);
-+ mask = gen_lowpart (V8SImode, mask);
- if (one_operand_shuffle)
- emit_insn (gen_avx2_permvarv8sf (target, op0, mask));
- else
-@@ -21740,6 +21706,21 @@
- return SImode;
- }
-
-+/* Copy the address to a Pmode register. This is used for x32 to
-+ truncate DImode TLS address to a SImode register. */
-+
-+static rtx
-+ix86_copy_addr_to_reg (rtx addr)
-+{
-+ if (GET_MODE (addr) == Pmode || GET_MODE (addr) == VOIDmode)
-+ return copy_addr_to_reg (addr);
-+ else
-+ {
-+ gcc_assert (GET_MODE (addr) == DImode && Pmode == SImode);
-+ return gen_rtx_SUBREG (SImode, copy_to_mode_reg (DImode, addr), 0);
-+ }
-+}
-+
- /* When SRCPTR is non-NULL, output simple loop to move memory
- pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
- overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
-@@ -22728,8 +22709,8 @@
- gcc_assert (alg != no_stringop);
- if (!count)
- count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
-- destreg = copy_addr_to_reg (XEXP (dst, 0));
-- srcreg = copy_addr_to_reg (XEXP (src, 0));
-+ destreg = ix86_copy_addr_to_reg (XEXP (dst, 0));
-+ srcreg = ix86_copy_addr_to_reg (XEXP (src, 0));
- switch (alg)
- {
- case libcall:
-@@ -23119,7 +23100,7 @@
- gcc_assert (alg != no_stringop);
- if (!count)
- count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
-- destreg = copy_addr_to_reg (XEXP (dst, 0));
-+ destreg = ix86_copy_addr_to_reg (XEXP (dst, 0));
- switch (alg)
- {
- case libcall:
-@@ -24988,7 +24969,8 @@
- int
- ix86_data_alignment (tree type, int align)
- {
-- int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
-+ int max_align
-+ = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
-
- if (AGGREGATE_TYPE_P (type)
- && TYPE_SIZE (type)
-@@ -27984,8 +27966,8 @@
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
-
-- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
-- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
-+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
-+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
-@@ -31245,11 +31227,12 @@
-
- static rtx
- ix86_expand_special_args_builtin (const struct builtin_description *d,
-- tree exp, rtx target)
-+ tree exp, rtx target)
- {
- tree arg;
- rtx pat, op;
- unsigned int i, nargs, arg_adjust, memory;
-+ bool aligned_mem = false;
- struct
- {
- rtx op;
-@@ -31295,6 +31278,15 @@
- nargs = 1;
- klass = load;
- memory = 0;
-+ switch (icode)
-+ {
-+ case CODE_FOR_sse4_1_movntdqa:
-+ case CODE_FOR_avx2_movntdqa:
-+ aligned_mem = true;
-+ break;
-+ default:
-+ break;
-+ }
- break;
- case VOID_FTYPE_PV2SF_V4SF:
- case VOID_FTYPE_PV4DI_V4DI:
-@@ -31312,6 +31304,26 @@
- klass = store;
- /* Reserve memory operand for target. */
- memory = ARRAY_SIZE (args);
-+ switch (icode)
-+ {
-+ /* These builtins and instructions require the memory
-+ to be properly aligned. */
-+ case CODE_FOR_avx_movntv4di:
-+ case CODE_FOR_sse2_movntv2di:
-+ case CODE_FOR_avx_movntv8sf:
-+ case CODE_FOR_sse_movntv4sf:
-+ case CODE_FOR_sse4a_vmmovntv4sf:
-+ case CODE_FOR_avx_movntv4df:
-+ case CODE_FOR_sse2_movntv2df:
-+ case CODE_FOR_sse4a_vmmovntv2df:
-+ case CODE_FOR_sse2_movntidi:
-+ case CODE_FOR_sse_movntq:
-+ case CODE_FOR_sse2_movntisi:
-+ aligned_mem = true;
-+ break;
-+ default:
-+ break;
-+ }
- break;
- case V4SF_FTYPE_V4SF_PCV2SF:
- case V2DF_FTYPE_V2DF_PCDOUBLE:
-@@ -31368,6 +31380,17 @@
- {
- op = force_reg (Pmode, convert_to_mode (Pmode, op, 1));
- target = gen_rtx_MEM (tmode, op);
-+ /* target at this point has just BITS_PER_UNIT MEM_ALIGN
-+ on it. Try to improve it using get_pointer_alignment,
-+ and if the special builtin is one that requires strict
-+ mode alignment, also from it's GET_MODE_ALIGNMENT.
-+ Failure to do so could lead to ix86_legitimate_combined_insn
-+ rejecting all changes to such insns. */
-+ unsigned int align = get_pointer_alignment (arg);
-+ if (aligned_mem && align < GET_MODE_ALIGNMENT (tmode))
-+ align = GET_MODE_ALIGNMENT (tmode);
-+ if (MEM_ALIGN (target) < align)
-+ set_mem_align (target, align);
- }
- else
- target = force_reg (tmode, op);
-@@ -31413,8 +31436,17 @@
- /* This must be the memory operand. */
- op = force_reg (Pmode, convert_to_mode (Pmode, op, 1));
- op = gen_rtx_MEM (mode, op);
-- gcc_assert (GET_MODE (op) == mode
-- || GET_MODE (op) == VOIDmode);
-+ /* op at this point has just BITS_PER_UNIT MEM_ALIGN
-+ on it. Try to improve it using get_pointer_alignment,
-+ and if the special builtin is one that requires strict
-+ mode alignment, also from it's GET_MODE_ALIGNMENT.
-+ Failure to do so could lead to ix86_legitimate_combined_insn
-+ rejecting all changes to such insns. */
-+ unsigned int align = get_pointer_alignment (arg);
-+ if (aligned_mem && align < GET_MODE_ALIGNMENT (mode))
-+ align = GET_MODE_ALIGNMENT (mode);
-+ if (MEM_ALIGN (op) < align)
-+ set_mem_align (op, align);
- }
- else
- {
-@@ -32027,7 +32059,8 @@
- else
- op2 = gen_rtx_SUBREG (SImode, op0, 0);
-
-- if (target == 0)
-+ if (target == 0
-+ || !register_operand (target, SImode))
- target = gen_reg_rtx (SImode);
-
- pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG),
-@@ -32069,7 +32102,8 @@
- const0_rtx);
- emit_insn (gen_rtx_SET (VOIDmode, op2, pat));
-
-- if (target == 0)
-+ if (target == 0
-+ || !register_operand (target, SImode))
- target = gen_reg_rtx (SImode);
-
- emit_insn (gen_zero_extendqisi2 (target, op2));
-@@ -32208,7 +32242,9 @@
- mode4 = insn_data[icode].operand[5].mode;
-
- if (target == NULL_RTX
-- || GET_MODE (target) != insn_data[icode].operand[0].mode)
-+ || GET_MODE (target) != insn_data[icode].operand[0].mode
-+ || !insn_data[icode].operand[0].predicate (target,
-+ GET_MODE (target)))
- subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode);
- else
- subtarget = target;
-@@ -33879,10 +33915,10 @@
- {
- /* We implement the move patterns for all vector modes into and
- out of SSE registers, even when no operation instructions
-- are available. OImode move is available only when AVX is
-- enabled. */
-- return ((TARGET_AVX && mode == OImode)
-- || VALID_AVX256_REG_MODE (mode)
-+ are available. OImode and AVX modes are available only when
-+ AVX is enabled. */
-+ return ((TARGET_AVX
-+ && VALID_AVX256_REG_OR_OI_MODE (mode))
- || VALID_SSE_REG_MODE (mode)
- || VALID_SSE2_REG_MODE (mode)
- || VALID_MMX_REG_MODE (mode)
-@@ -35020,7 +35056,7 @@
- {
- tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOTPCREL);
- tmp = gen_rtx_CONST (Pmode, tmp);
-- fnaddr = gen_rtx_MEM (Pmode, tmp);
-+ fnaddr = gen_const_mem (Pmode, tmp);
- }
- }
- else
-@@ -35040,8 +35076,9 @@
- output_set_got (tmp, NULL_RTX);
-
- fnaddr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOT);
-- fnaddr = gen_rtx_PLUS (Pmode, fnaddr, tmp);
-- fnaddr = gen_rtx_MEM (Pmode, fnaddr);
-+ fnaddr = gen_rtx_CONST (Pmode, fnaddr);
-+ fnaddr = gen_rtx_PLUS (Pmode, tmp, fnaddr);
-+ fnaddr = gen_const_mem (Pmode, fnaddr);
- }
- }
-
-@@ -35232,7 +35269,10 @@
- The smallest offset in the page INSN can start is the case where START
- ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
- We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
-- */
-+
-+ Don't consider asm goto as jump, while it can contain a jump, it doesn't
-+ have to, control transfer to label(s) can be performed through other
-+ means, and also we estimate minimum length of all asm stmts as 0. */
- for (insn = start; insn; insn = NEXT_INSN (insn))
- {
- int min_size;
-@@ -35260,6 +35300,7 @@
- {
- start = NEXT_INSN (start);
- if ((JUMP_P (start)
-+ && asm_noperands (PATTERN (start)) < 0
- && GET_CODE (PATTERN (start)) != ADDR_VEC
- && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
- || CALL_P (start))
-@@ -35278,6 +35319,7 @@
- fprintf (dump_file, "Insn %i estimated to %i bytes\n",
- INSN_UID (insn), min_size);
- if ((JUMP_P (insn)
-+ && asm_noperands (PATTERN (insn)) < 0
- && GET_CODE (PATTERN (insn)) != ADDR_VEC
- && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
- || CALL_P (insn))
-@@ -35289,6 +35331,7 @@
- {
- start = NEXT_INSN (start);
- if ((JUMP_P (start)
-+ && asm_noperands (PATTERN (start)) < 0
- && GET_CODE (PATTERN (start)) != ADDR_VEC
- && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
- || CALL_P (start))
-@@ -39371,7 +39414,9 @@
- else
- dfinal.perm[i] = e;
- }
-- dfinal.op0 = gen_reg_rtx (dfinal.vmode);
-+
-+ if (!d->testing_p)
-+ dfinal.op0 = gen_reg_rtx (dfinal.vmode);
- dfinal.op1 = dfinal.op0;
- dfinal.one_operand_p = true;
- dremap.target = dfinal.op0;
-@@ -39806,6 +39851,9 @@
- return false;
- gcc_assert (!d->one_operand_p);
-
-+ if (d->testing_p)
-+ return true;
-+
- nelt = d->nelt;
- eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
-
-@@ -40005,6 +40053,8 @@
- switch (d->vmode)
- {
- case V4DFmode:
-+ if (d->testing_p)
-+ break;
- t1 = gen_reg_rtx (V4DFmode);
- t2 = gen_reg_rtx (V4DFmode);
-
-@@ -40024,6 +40074,8 @@
- {
- int mask = odd ? 0xdd : 0x88;
-
-+ if (d->testing_p)
-+ break;
- t1 = gen_reg_rtx (V8SFmode);
- t2 = gen_reg_rtx (V8SFmode);
- t3 = gen_reg_rtx (V8SFmode);
-@@ -40065,6 +40117,8 @@
- return expand_vec_perm_pshufb2 (d);
- else
- {
-+ if (d->testing_p)
-+ break;
- /* We need 2*log2(N)-1 operations to achieve odd/even
- with interleave. */
- t1 = gen_reg_rtx (V8HImode);
-@@ -40086,6 +40140,8 @@
- return expand_vec_perm_pshufb2 (d);
- else
- {
-+ if (d->testing_p)
-+ break;
- t1 = gen_reg_rtx (V16QImode);
- t2 = gen_reg_rtx (V16QImode);
- t3 = gen_reg_rtx (V16QImode);
-@@ -40118,6 +40174,9 @@
- return expand_vec_perm_even_odd_1 (&d_copy, odd);
- }
-
-+ if (d->testing_p)
-+ break;
-+
- t1 = gen_reg_rtx (V4DImode);
- t2 = gen_reg_rtx (V4DImode);
-
-@@ -40144,6 +40203,9 @@
- return expand_vec_perm_even_odd_1 (&d_copy, odd);
- }
-
-+ if (d->testing_p)
-+ break;
-+
- t1 = gen_reg_rtx (V8SImode);
- t2 = gen_reg_rtx (V8SImode);
-
-@@ -40236,6 +40298,8 @@
- case V16QImode:
- /* These can be implemented via interleave. We save one insn by
- stopping once we have promoted to V4SImode and then use pshufd. */
-+ if (d->testing_p)
-+ return true;
- do
- {
- rtx dest;
-@@ -42473,8 +42537,6 @@
-
- #undef TARGET_PROMOTE_PROTOTYPES
- #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
--#undef TARGET_STRUCT_VALUE_RTX
--#define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
- #undef TARGET_SETUP_INCOMING_VARARGS
- #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
- #undef TARGET_MUST_PASS_IN_STACK
-Index: gcc/config/tilegx/tilegx.md
-===================================================================
---- a/src/gcc/config/tilegx/tilegx.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/tilegx/tilegx.md (.../branches/gcc-4_8-branch)
-@@ -5076,10 +5076,8 @@
-
- ;; Network intrinsics
-
--;; Note the "pseudo" text is handled specially by the
--;; asm_output_opcode routine. If the output is an empty string, the
--;; instruction would bypass the asm_output_opcode routine, bypassing
--;; the bundle handling code.
-+;; Note the this barrier is of type "nothing," which is deleted after
-+;; the final scheduling pass so that nothing is emitted for it.
- (define_insn "tilegx_network_barrier"
- [(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)]
- ""
-Index: gcc/config/tilegx/tilegx-c.c
-===================================================================
---- a/src/gcc/config/tilegx/tilegx-c.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/tilegx/tilegx-c.c (.../branches/gcc-4_8-branch)
-@@ -47,6 +47,9 @@
- if (TARGET_32BIT)
- builtin_define ("__tilegx32__");
-
-+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
-+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
-+
- TILEGX_CPU_CPP_ENDIAN_BUILTINS ();
- GNU_USER_TARGET_OS_CPP_BUILTINS ();
- }
-Index: gcc/config/tilegx/sync.md
-===================================================================
---- a/src/gcc/config/tilegx/sync.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/tilegx/sync.md (.../branches/gcc-4_8-branch)
-@@ -150,15 +150,22 @@
- (match_operand:SI 3 "const_int_operand" "")] ;; model
- ""
- {
-+ rtx addend;
- enum memmodel model = (enum memmodel) INTVAL (operands[3]);
-
- if (operands[2] != const0_rtx)
-- emit_move_insn (operands[2], gen_rtx_NEG (<MODE>mode, operands[2]));
-+ {
-+ addend = gen_reg_rtx (<MODE>mode);
-+ emit_move_insn (addend,
-+ gen_rtx_MINUS (<MODE>mode, const0_rtx, operands[2]));
-+ }
-+ else
-+ addend = operands[2];
-
- tilegx_pre_atomic_barrier (model);
- emit_insn (gen_atomic_fetch_add_bare<mode> (operands[0],
- operands[1],
-- operands[2]));
-+ addend));
- tilegx_post_atomic_barrier (model);
- DONE;
- })
-Index: gcc/config/tilegx/tilegx.c
-===================================================================
---- a/src/gcc/config/tilegx/tilegx.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/tilegx/tilegx.c (.../branches/gcc-4_8-branch)
-@@ -702,6 +702,16 @@
- }
-
-
-+/* Implement TARGET_EXPAND_TO_RTL_HOOK. */
-+static void
-+tilegx_expand_to_rtl_hook (void)
-+{
-+ /* Exclude earlier sets of crtl->uses_pic_offset_table, because we
-+ only care about uses actually emitted. */
-+ crtl->uses_pic_offset_table = 0;
-+}
-+
-+
- /* Implement TARGET_SHIFT_TRUNCATION_MASK. DImode shifts use the mode
- matching insns and therefore guarantee that the shift count is
- modulo 64. SImode shifts sometimes use the 64 bit version so do
-@@ -3543,6 +3553,12 @@
- }
- if (!pat)
- return NULL_RTX;
-+
-+ /* If we are generating a prefetch, tell the scheduler not to move
-+ it around. */
-+ if (GET_CODE (pat) == PREFETCH)
-+ PREFETCH_SCHEDULE_BARRIER_P (pat) = true;
-+
- emit_insn (pat);
-
- if (nonvoid)
-@@ -4368,10 +4384,12 @@
- basic_block bb;
- FOR_EACH_BB (bb)
- {
-- rtx insn, next;
-+ rtx insn, next, prev;
- rtx end = NEXT_INSN (BB_END (bb));
-
-- for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)
-+ prev = NULL_RTX;
-+ for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn;
-+ prev = insn, insn = next)
- {
- next = next_insn_to_bundle (NEXT_INSN (insn), end);
-
-@@ -4396,6 +4414,18 @@
- PUT_MODE (insn, SImode);
- }
- }
-+
-+ /* Delete barrier insns, because they can mess up the
-+ emitting of bundle braces. If it is end-of-bundle, then
-+ the previous insn must be marked end-of-bundle. */
-+ if (get_attr_type (insn) == TYPE_NOTHING) {
-+ if (GET_MODE (insn) == QImode && prev != NULL
-+ && GET_MODE (prev) == SImode)
-+ {
-+ PUT_MODE (prev, QImode);
-+ }
-+ delete_insn (insn);
-+ }
- }
- }
- }
-@@ -5498,6 +5528,9 @@
- #undef TARGET_RTX_COSTS
- #define TARGET_RTX_COSTS tilegx_rtx_costs
-
-+#undef TARGET_EXPAND_TO_RTL_HOOK
-+#define TARGET_EXPAND_TO_RTL_HOOK tilegx_expand_to_rtl_hook
-+
- #undef TARGET_SHIFT_TRUNCATION_MASK
- #define TARGET_SHIFT_TRUNCATION_MASK tilegx_shift_truncation_mask
-
-Index: gcc/config/sh/predicates.md
-===================================================================
---- a/src/gcc/config/sh/predicates.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sh/predicates.md (.../branches/gcc-4_8-branch)
-@@ -389,6 +389,12 @@
- XEXP (XEXP (op, 0), 1),
- TARGET_SH2A, true)")))
-
-+;; Returns true if OP is a displacement address that can fit into a
-+;; 16 bit (non-SH2A) memory load / store insn.
-+(define_predicate "short_displacement_mem_operand"
-+ (match_test "sh_disp_addr_displacement (op)
-+ <= sh_max_mov_insn_displacement (GET_MODE (op), false)"))
-+
- ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn.
- (define_predicate "zero_extend_movu_operand"
- (and (match_operand 0 "displacement_mem_operand")
-@@ -413,6 +419,11 @@
- if (t_reg_operand (op, mode))
- return 0;
-
-+ /* Disallow PC relative QImode loads, since these is no insn to do that
-+ and an imm8 load should be used instead. */
-+ if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode)
-+ return false;
-+
- if (MEM_P (op))
- {
- rtx inside = XEXP (op, 0);
-Index: gcc/config/sh/sh-protos.h
-===================================================================
---- a/src/gcc/config/sh/sh-protos.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sh/sh-protos.h (.../branches/gcc-4_8-branch)
-@@ -159,6 +159,8 @@
- extern bool sh_cfun_trap_exit_p (void);
- extern rtx sh_find_equiv_gbr_addr (rtx cur_insn, rtx mem);
- extern int sh_eval_treg_value (rtx op);
-+extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op);
-+extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a);
-
- /* Result value of sh_find_set_of_reg. */
- struct set_of_reg
-Index: gcc/config/sh/sh.c
-===================================================================
---- a/src/gcc/config/sh/sh.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sh/sh.c (.../branches/gcc-4_8-branch)
-@@ -24,6 +24,9 @@
- malloc & co, which are poisoned by "system.h". The proper solution is
- to include <cstdlib> in "system.h" instead of <stdlib.h>. */
- #include <cstdlib>
-+#include <sstream>
-+#include <vector>
-+#include <algorithm>
-
- #include "config.h"
- #include "system.h"
-@@ -60,10 +63,6 @@
- #include "tm-constrs.h"
- #include "opts.h"
-
--#include <sstream>
--#include <vector>
--#include <algorithm>
--
- int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
-
- #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
-@@ -310,9 +309,7 @@
- static void sh_conditional_register_usage (void);
- static bool sh_legitimate_constant_p (enum machine_mode, rtx);
- static int mov_insn_size (enum machine_mode, bool);
--static int max_mov_insn_displacement (enum machine_mode, bool);
- static int mov_insn_alignment_mask (enum machine_mode, bool);
--static HOST_WIDE_INT disp_addr_displacement (rtx);
- static bool sequence_insn_p (rtx);
- static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool);
- static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&,
-@@ -3628,8 +3625,8 @@
-
- /* Determine the maximum possible displacement for a move insn for the
- specified mode. */
--static int
--max_mov_insn_displacement (enum machine_mode mode, bool consider_sh2a)
-+int
-+sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a)
- {
- /* The 4 byte displacement move insns are the same as the 2 byte
- versions but take a 12 bit displacement. All we need to do is to
-@@ -3665,8 +3662,8 @@
- }
-
- /* Return the displacement value of a displacement address. */
--static inline HOST_WIDE_INT
--disp_addr_displacement (rtx x)
-+HOST_WIDE_INT
-+sh_disp_addr_displacement (rtx x)
- {
- gcc_assert (satisfies_constraint_Sdd (x));
- return INTVAL (XEXP (XEXP (x, 0), 1));
-@@ -3703,12 +3700,12 @@
- HImode and QImode loads/stores with displacement put pressure on
- R0 which will most likely require another reg copy. Thus account
- a higher cost for that. */
-- if (offset > 0 && offset <= max_mov_insn_displacement (mode, false))
-+ if (offset > 0 && offset <= sh_max_mov_insn_displacement (mode, false))
- return (mode == HImode || mode == QImode) ? 2 : 1;
-
- /* The displacement would fit into a 4 byte move insn (SH2A). */
- if (TARGET_SH2A
-- && offset > 0 && offset <= max_mov_insn_displacement (mode, true))
-+ && offset > 0 && offset <= sh_max_mov_insn_displacement (mode, true))
- return 2;
-
- /* The displacement is probably out of range and will require extra
-@@ -10218,7 +10215,7 @@
- else
- {
- const HOST_WIDE_INT offset = INTVAL (op);
-- const int max_disp = max_mov_insn_displacement (mode, consider_sh2a);
-+ const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a);
- const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a);
-
- /* If the mode does not support any displacement always return false.
-@@ -10404,7 +10401,7 @@
- effectively disable the small displacement insns. */
- const int mode_sz = GET_MODE_SIZE (mode);
- const int mov_insn_sz = mov_insn_size (mode, false);
-- const int max_disp = max_mov_insn_displacement (mode, false);
-+ const int max_disp = sh_max_mov_insn_displacement (mode, false);
- const int max_disp_next = max_disp + mov_insn_sz;
- HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0;
- HOST_WIDE_INT offset_adjust;
-@@ -13165,7 +13162,8 @@
- the insns must have the appropriate alternatives. */
- if ((mode == QImode || mode == HImode) && rclass != R0_REGS
- && satisfies_constraint_Sdd (x)
-- && disp_addr_displacement (x) <= max_mov_insn_displacement (mode, false))
-+ && sh_disp_addr_displacement (x)
-+ <= sh_max_mov_insn_displacement (mode, false))
- return R0_REGS;
-
- /* When reload is trying to address a QImode or HImode subreg on the stack,
-Index: gcc/config/sh/constraints.md
-===================================================================
---- a/src/gcc/config/sh/constraints.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sh/constraints.md (.../branches/gcc-4_8-branch)
-@@ -221,6 +221,7 @@
- (define_constraint "Q"
- "A pc relative load operand."
- (and (match_code "mem")
-+ (match_test "GET_MODE (op) != QImode")
- (match_test "IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0))")))
-
- (define_constraint "Bsc"
-@@ -295,13 +296,15 @@
-
- (define_memory_constraint "Sdd"
- "A memory reference that uses displacement addressing."
-- (and (match_test "MEM_P (op) && GET_CODE (XEXP (op, 0)) == PLUS")
-+ (and (match_code "mem")
-+ (match_test "GET_CODE (XEXP (op, 0)) == PLUS")
- (match_test "REG_P (XEXP (XEXP (op, 0), 0))")
- (match_test "CONST_INT_P (XEXP (XEXP (op, 0), 1))")))
-
- (define_memory_constraint "Snd"
- "A memory reference that excludes displacement addressing."
-- (match_test "! satisfies_constraint_Sdd (op)"))
-+ (and (match_code "mem")
-+ (match_test "! satisfies_constraint_Sdd (op)")))
-
- (define_memory_constraint "Sbv"
- "A memory reference, as used in SH2A bclr.b, bset.b, etc."
-Index: gcc/config/sh/sh.md
-===================================================================
---- a/src/gcc/config/sh/sh.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sh/sh.md (.../branches/gcc-4_8-branch)
-@@ -2152,6 +2152,7 @@
- (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
- (clobber (reg:SI T_REG))
- (clobber (reg:SI PR_REG))
-+ (clobber (reg:SI R1_REG))
- (clobber (reg:SI R4_REG))
- (use (match_operand:SI 1 "arith_reg_operand" "r"))]
- "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
-@@ -6831,34 +6832,9 @@
- prepare_move_operands (operands, QImode);
- })
-
--;; If movqi_reg_reg is specified as an alternative of movqi, movqi will be
--;; selected to copy QImode regs. If one of them happens to be allocated
--;; on the stack, reload will stick to movqi insn and generate wrong
--;; displacement addressing because of the generic m alternatives.
--;; With the movqi_reg_reg being specified before movqi it will be initially
--;; picked to load/store regs. If the regs regs are on the stack reload
--;; try other insns and not stick to movqi_reg_reg, unless there were spilled
--;; pseudos in which case 'm' constraints pertain.
--;; The same applies to the movhi variants.
--;;
--;; Notice, that T bit is not allowed as a mov src operand here. This is to
--;; avoid things like (set (reg:QI) (subreg:QI (reg:SI T_REG) 0)), which
--;; introduces zero extensions after T bit stores and redundant reg copies.
--;;
--;; FIXME: We can't use 'arith_reg_operand' (which disallows T_REG) as a
--;; predicate for the mov src operand because reload will have trouble
--;; reloading MAC subregs otherwise. For that probably special patterns
--;; would be required.
--(define_insn "*mov<mode>_reg_reg"
-- [(set (match_operand:QIHI 0 "arith_reg_dest" "=r,m,*z")
-- (match_operand:QIHI 1 "register_operand" "r,*z,m"))]
-- "TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode)"
-- "@
-- mov %1,%0
-- mov.<bw> %1,%0
-- mov.<bw> %1,%0"
-- [(set_attr "type" "move,store,load")])
--
-+;; Specifying the displacement addressing load / store patterns separately
-+;; before the generic movqi / movhi pattern allows controlling the order
-+;; in which load / store insns are selected in a more fine grained way.
- ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
- ;; "enabled" attribute as it is done in other targets.
- (define_insn "*mov<mode>_store_mem_disp04"
-@@ -6908,38 +6884,44 @@
- [(set_attr "type" "load")
- (set_attr "length" "2,2,4")])
-
--;; The m constraints basically allow any kind of addresses to be used with any
--;; source/target register as the other operand. This is not true for
--;; displacement addressing modes on anything but SH2A. That's why the
--;; specialized load/store insns are specified above.
--(define_insn "*movqi"
-- [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,l")
-- (match_operand:QI 1 "general_movsrc_operand" "i,m,r,l,r"))]
-+;; The order of the constraint alternatives is important here.
-+;; Q/r has to come first, otherwise PC relative loads might wrongly get
-+;; placed into delay slots. Since there is no QImode PC relative load, the
-+;; Q constraint and general_movsrc_operand will reject it for QImode.
-+;; The Snd alternatives should come before Sdd in order to avoid a preference
-+;; of using r0 als the register operand for addressing modes other than
-+;; displacement addressing.
-+;; The Sdd alternatives allow only r0 as register operand, even though on
-+;; SH2A any register could be allowed by switching to a 32 bit insn.
-+;; Generally sticking to the r0 is preferrable, since it generates smaller
-+;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
-+(define_insn "*mov<mode>"
-+ [(set (match_operand:QIHI 0 "general_movdst_operand"
-+ "=r,r,r,Snd,r, Sdd,z, r,l")
-+ (match_operand:QIHI 1 "general_movsrc_operand"
-+ "Q,r,i,r, Snd,z, Sdd,l,r"))]
- "TARGET_SH1
-- && (arith_reg_operand (operands[0], QImode)
-- || arith_reg_operand (operands[1], QImode))"
-+ && (arith_reg_operand (operands[0], <MODE>mode)
-+ || arith_reg_operand (operands[1], <MODE>mode))"
- "@
-+ mov.<bw> %1,%0
- mov %1,%0
-- mov.b %1,%0
-- mov.b %1,%0
-- sts %1,%0
-- lds %1,%0"
-- [(set_attr "type" "movi8,load,store,prget,prset")])
--
--(define_insn "*movhi"
-- [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,m,r,l")
-- (match_operand:HI 1 "general_movsrc_operand" "Q,i,m,r,l,r"))]
-- "TARGET_SH1
-- && (arith_reg_operand (operands[0], HImode)
-- || arith_reg_operand (operands[1], HImode))"
-- "@
-- mov.w %1,%0
- mov %1,%0
-- mov.w %1,%0
-- mov.w %1,%0
-+ mov.<bw> %1,%0
-+ mov.<bw> %1,%0
-+ mov.<bw> %1,%0
-+ mov.<bw> %1,%0
- sts %1,%0
- lds %1,%0"
-- [(set_attr "type" "pcload,movi8,load,store,prget,prset")])
-+ [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")
-+ (set (attr "length")
-+ (cond [(and (match_operand 0 "displacement_mem_operand")
-+ (not (match_operand 0 "short_displacement_mem_operand")))
-+ (const_int 4)
-+ (and (match_operand 1 "displacement_mem_operand")
-+ (not (match_operand 1 "short_displacement_mem_operand")))
-+ (const_int 4)]
-+ (const_int 2)))])
-
- (define_insn "*movqi_media"
- [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
-@@ -8427,11 +8409,9 @@
-
- while (true)
- {
-- /* It's not safe to go beyond the current basic block after reload. */
- set_of_reg s1 = sh_find_set_of_reg (tested_reg, s0.insn,
-- reload_completed
-- ? prev_nonnote_insn_bb
-- : prev_nonnote_insn);
-+ prev_nonnote_insn);
-+
- if (s1.set_src == NULL_RTX)
- break;
-
-@@ -8449,15 +8429,25 @@
- continue;
- }
-
-- /* It's only safe to remove the testing insn if the T bit is not
-- modified between the testing insn and the insn that stores the
-- T bit. Notice that some T bit stores such as negc also modify
-- the T bit. */
-- if (modified_between_p (get_t_reg_rtx (), s1.insn, testing_insn)
-- || modified_in_p (get_t_reg_rtx (), s1.insn))
-- operands[2] = NULL_RTX;
-+ /* It's only safe to remove the testing insn if the T bit is not
-+ modified between the testing insn and the insn that stores the
-+ T bit. Notice that some T bit stores such as negc also modify
-+ the T bit. */
-+ if (modified_between_p (get_t_reg_rtx (), s1.insn, testing_insn)
-+ || modified_in_p (get_t_reg_rtx (), s1.insn)
-+ || !no_labels_between_p (s1.insn, testing_insn))
-+ operands[2] = NULL_RTX;
-+ else
-+ {
-+ /* If the insn that sets the tested reg has a REG_DEAD note on
-+ the T bit remove that note since we're extending the usage
-+ of the T bit. */
-+ rtx n = find_regno_note (s1.insn, REG_DEAD, T_REG);
-+ if (n != NULL_RTX)
-+ remove_note (s1.insn, n);
-+ }
-
-- break;
-+ break;
- }
-
- if (operands[2] == NULL_RTX)
-Index: gcc/config/sh/sh.opt
-===================================================================
---- a/src/gcc/config/sh/sh.opt (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/sh/sh.opt (.../branches/gcc-4_8-branch)
-@@ -21,7 +21,7 @@
- ;; Used for various architecture options.
- Mask(SH_E)
-
--;; Set if the default precision of th FPU is single.
-+;; Set if the default precision of the FPU is single.
- Mask(FPU_SINGLE)
-
- ;; Set if the a double-precision FPU is present but is restricted to
-Index: gcc/config/microblaze/predicates.md
-===================================================================
---- a/src/gcc/config/microblaze/predicates.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/microblaze/predicates.md (.../branches/gcc-4_8-branch)
-@@ -85,6 +85,10 @@
- (ior (match_operand 0 "const_0_operand")
- (match_operand 0 "register_operand")))
-
-+(define_predicate "reg_or_mem_operand"
-+ (ior (match_operand 0 "memory_operand")
-+ (match_operand 0 "register_operand")))
-+
- ;; Return if the operand is either the PC or a label_ref.
- (define_special_predicate "pc_or_label_operand"
- (ior (match_code "pc,label_ref")
-@@ -119,3 +123,7 @@
- ;; Test for valid PIC call operand
- (define_predicate "call_insn_plt_operand"
- (match_test "PLT_ADDR_P (op)"))
-+
-+;; Return if the code of this rtx pattern is a comparison.
-+(define_predicate "cmp_op"
-+ (match_code "gt,ge,gtu,geu,lt,le,ltu,leu"))
-Index: gcc/config/microblaze/microblaze.md
-===================================================================
---- a/src/gcc/config/microblaze/microblaze.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/microblaze/microblaze.md (.../branches/gcc-4_8-branch)
-@@ -74,7 +74,7 @@
- ;; bshift Shift operations
-
- (define_attr "type"
-- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt"
-+ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
- (const_string "unknown"))
-
- ;; Main data type used by the insn
-@@ -365,7 +365,8 @@
- [(set (match_operand:HI 0 "register_operand" "=r")
- (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
- "TARGET_REORDER"
-- "swaph %0, %1"
-+ "swapb %0, %1
-+ swaph %0, %0"
- )
-
- ;;----------------------------------------------------------------
-@@ -1118,6 +1119,18 @@
- }
- )
-
-+;;Load and store reverse
-+(define_insn "movsi4_rev"
-+ [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Q")
-+ (bswap:SI (match_operand:SF 1 "reg_or_mem_operand" "Q,r")))]
-+ "TARGET_REORDER"
-+ "@
-+ lwr\t%0,%y1,r0
-+ swr\t%1,%y0,r0"
-+ [(set_attr "type" "load,store")
-+ (set_attr "mode" "SI")
-+ (set_attr "length" "4,4")])
-+
- ;; 32-bit floating point moves
-
- (define_expand "movsf"
-@@ -1472,7 +1485,7 @@
- (set_attr "length" "124")]
- )
-
--(define_insn "*ashlri_reg"
-+(define_insn "*ashrsi_reg"
- [(set (match_operand:SI 0 "register_operand" "=&d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))]
-@@ -1561,7 +1574,7 @@
- (set_attr "length" "124")]
- )
-
--(define_insn "*lshlri_reg"
-+(define_insn "*lshrsi_reg"
- [(set (match_operand:SI 0 "register_operand" "=&d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))]
-@@ -1622,34 +1635,12 @@
- (set_attr "length" "4")]
- )
-
--(define_insn "signed_compare"
-- [(set (match_operand:SI 0 "register_operand" "=d")
-- (unspec
-- [(match_operand:SI 1 "register_operand" "d")
-- (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMP))]
-- ""
-- "cmp\t%0,%1,%2"
-- [(set_attr "type" "arith")
-- (set_attr "mode" "SI")
-- (set_attr "length" "4")])
--
--(define_insn "unsigned_compare"
-- [(set (match_operand:SI 0 "register_operand" "=d")
-- (unspec
-- [(match_operand:SI 1 "register_operand" "d")
-- (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMPU))]
-- ""
-- "cmpu\t%0,%1,%2"
-- [(set_attr "type" "arith")
-- (set_attr "mode" "SI")
-- (set_attr "length" "4")])
--
- ;;----------------------------------------------------------------
- ;; Setting a register from an floating point comparison.
- ;;----------------------------------------------------------------
- (define_insn "cstoresf4"
- [(set (match_operand:SI 0 "register_operand" "=r")
-- (match_operator 1 "comparison_operator"
-+ (match_operator:SI 1 "ordered_comparison_operator"
- [(match_operand:SF 2 "register_operand" "r")
- (match_operand:SF 3 "register_operand" "r")]))]
- "TARGET_HARD_FLOAT"
-@@ -1678,7 +1669,7 @@
-
- (define_expand "cbranchsf4"
- [(set (pc)
-- (if_then_else (match_operator 0 "comparison_operator"
-+ (if_then_else (match_operator 0 "ordered_comparison_operator"
- [(match_operand:SF 1 "register_operand")
- (match_operand:SF 2 "register_operand")])
- (label_ref (match_operand 3 ""))
-@@ -1717,6 +1708,47 @@
- (set_attr "length" "4")]
- )
-
-+(define_insn "branch_compare"
-+ [(set (pc)
-+ (if_then_else (match_operator:SI 0 "cmp_op"
-+ [(match_operand:SI 1 "register_operand" "d")
-+ (match_operand:SI 2 "register_operand" "d")
-+ ])
-+ (label_ref (match_operand 3))
-+ (pc)))
-+ (clobber(reg:SI R_TMP))]
-+ ""
-+ {
-+ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-+ enum rtx_code code = GET_CODE (operands[0]);
-+
-+ if (code == GT || code == LE)
-+ {
-+ output_asm_insn ("cmp\tr18,%z1,%z2", operands);
-+ code = swap_condition (code);
-+ }
-+ else if (code == GTU || code == LEU)
-+ {
-+ output_asm_insn ("cmpu\tr18,%z1,%z2", operands);
-+ code = swap_condition (code);
-+ }
-+ else if (code == GE || code == LT)
-+ {
-+ output_asm_insn ("cmp\tr18,%z2,%z1", operands);
-+ }
-+ else if (code == GEU || code == LTU)
-+ {
-+ output_asm_insn ("cmpu\tr18,%z2,%z1", operands);
-+ }
-+
-+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);
-+ return "b%C0i%?\tr18,%3";
-+ }
-+ [(set_attr "type" "branch")
-+ (set_attr "mode" "none")
-+ (set_attr "length" "12")]
-+)
-+
- ;;----------------------------------------------------------------
- ;; Unconditional branches
- ;;----------------------------------------------------------------
-@@ -2201,6 +2233,14 @@
- (set_attr "mode" "none")
- (set_attr "length" "4")])
-
-+;; Trap instruction pattern for __builtin_trap. Same as the glibc ABORT_INSTRUCTION
-+(define_insn "trap"
-+ [(trap_if (const_int 1) (const_int 0))]
-+ ""
-+ "brki\tr0,-1"
-+ [(set_attr "type" "trap")]
-+)
-+
- ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
- ;; between "mfs" and "addik" instructions.
- (define_insn "set_got"
-Index: gcc/config/microblaze/microblaze.c
-===================================================================
---- a/src/gcc/config/microblaze/microblaze.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/microblaze/microblaze.c (.../branches/gcc-4_8-branch)
-@@ -1609,21 +1609,28 @@
- microblaze_version_to_int (const char *version)
- {
- const char *p, *v;
-- const char *tmpl = "vX.YY.Z";
-+ const char *tmpl = "vXX.YY.Z";
- int iver = 0;
-
- p = version;
- v = tmpl;
-
-- while (*v)
-+ while (*p)
- {
- if (*v == 'X')
- { /* Looking for major */
-- if (!(*p >= '0' && *p <= '9'))
-- return -1;
-- iver += (int) (*p - '0');
-- iver *= 10;
-- }
-+ if (*p == '.')
-+ {
-+ *v++;
-+ }
-+ else
-+ {
-+ if (!(*p >= '0' && *p <= '9'))
-+ return -1;
-+ iver += (int) (*p - '0');
-+ iver *= 10;
-+ }
-+ }
- else if (*v == 'Y')
- { /* Looking for minor */
- if (!(*p >= '0' && *p <= '9'))
-@@ -3064,6 +3071,73 @@
- return result;
- }
-
-+static void
-+microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
-+ HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
-+ tree function)
-+{
-+ rtx this_rtx, insn, funexp;
-+
-+ reload_completed = 1;
-+ epilogue_completed = 1;
-+
-+ /* Mark the end of the (empty) prologue. */
-+ emit_note (NOTE_INSN_PROLOGUE_END);
-+
-+ /* Find the "this" pointer. If the function returns a structure,
-+ the structure return pointer is in MB_ABI_FIRST_ARG_REGNUM. */
-+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
-+ this_rtx = gen_rtx_REG (Pmode, (MB_ABI_FIRST_ARG_REGNUM + 1));
-+ else
-+ this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
-+
-+ /* Apply the constant offset, if required. */
-+ if (delta)
-+ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
-+
-+ /* Apply the offset from the vtable, if required. */
-+ if (vcall_offset)
-+ {
-+ rtx vcall_offset_rtx = GEN_INT (vcall_offset);
-+ rtx temp1 = gen_rtx_REG (Pmode, MB_ABI_TEMP1_REGNUM);
-+
-+ emit_move_insn (temp1, gen_rtx_MEM (Pmode, this_rtx));
-+
-+ rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);
-+ emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));
-+
-+ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
-+ }
-+
-+ /* Generate a tail call to the target function. */
-+ if (!TREE_USED (function))
-+ {
-+ assemble_external (function);
-+ TREE_USED (function) = 1;
-+ }
-+
-+ funexp = XEXP (DECL_RTL (function), 0);
-+ rtx temp2 = gen_rtx_REG (Pmode, MB_ABI_TEMP2_REGNUM);
-+
-+ if (flag_pic)
-+ emit_move_insn (temp2, expand_pic_symbol_ref (Pmode, funexp));
-+ else
-+ emit_move_insn (temp2, funexp);
-+
-+ emit_insn (gen_indirect_jump (temp2));
-+
-+ /* Run just enough of rest_of_compilation. This sequence was
-+ "borrowed" from rs6000.c. */
-+ insn = get_insns ();
-+ shorten_branches (insn);
-+ final_start_function (insn, file, 1);
-+ final (insn, file, 1);
-+ final_end_function ();
-+
-+ reload_completed = 0;
-+ epilogue_completed = 0;
-+}
-+
- bool
- microblaze_expand_move (enum machine_mode mode, rtx operands[])
- {
-@@ -3234,67 +3308,47 @@
- emit_move_insn (mem, fnaddr);
- }
-
--/* Emit instruction to perform compare.
-- cmp is (compare_op op0 op1). */
--static rtx
--microblaze_emit_compare (enum machine_mode mode, rtx cmp, enum rtx_code *cmp_code)
-+/* Generate conditional branch -- first, generate test condition,
-+ second, generate correct branch instruction. */
-+
-+void
-+microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[])
- {
-- rtx cmp_op0 = XEXP (cmp, 0);
-- rtx cmp_op1 = XEXP (cmp, 1);
-+ enum rtx_code code = GET_CODE (operands[0]);
-+ rtx cmp_op0 = operands[1];
-+ rtx cmp_op1 = operands[2];
-+ rtx label1 = operands[3];
- rtx comp_reg = gen_reg_rtx (SImode);
-- enum rtx_code code = *cmp_code;
--
-+ rtx condition;
-+
- gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
-
- /* If comparing against zero, just test source reg. */
-- if (cmp_op1 == const0_rtx)
-- return cmp_op0;
-+ if (cmp_op1 == const0_rtx)
-+ {
-+ comp_reg = cmp_op0;
-+ condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
-+ emit_jump_insn (gen_condjump (condition, label1));
-+ }
-
-- if (code == EQ || code == NE)
-+ else if (code == EQ || code == NE)
- {
- /* Use xor for equal/not-equal comparison. */
- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
-+ condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
-+ emit_jump_insn (gen_condjump (condition, label1));
- }
-- else if (code == GT || code == GTU || code == LE || code == LEU)
-+ else
- {
-- /* MicroBlaze compare is not symmetrical. */
-- /* Swap argument order. */
-+ /* Generate compare and branch in single instruction. */
- cmp_op1 = force_reg (mode, cmp_op1);
-- if (code == GT || code == LE)
-- emit_insn (gen_signed_compare (comp_reg, cmp_op0, cmp_op1));
-- else
-- emit_insn (gen_unsigned_compare (comp_reg, cmp_op0, cmp_op1));
-- /* Translate test condition. */
-- *cmp_code = swap_condition (code);
-+ condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
-+ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
- }
-- else /* if (code == GE || code == GEU || code == LT || code == LTU) */
-- {
-- cmp_op1 = force_reg (mode, cmp_op1);
-- if (code == GE || code == LT)
-- emit_insn (gen_signed_compare (comp_reg, cmp_op1, cmp_op0));
-- else
-- emit_insn (gen_unsigned_compare (comp_reg, cmp_op1, cmp_op0));
-- }
--
-- return comp_reg;
- }
-
--/* Generate conditional branch -- first, generate test condition,
-- second, generate correct branch instruction. */
-
- void
--microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[])
--{
-- enum rtx_code code = GET_CODE (operands[0]);
-- rtx comp;
-- rtx condition;
--
-- comp = microblaze_emit_compare (mode, operands[0], &code);
-- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp, const0_rtx);
-- emit_jump_insn (gen_condjump (condition, operands[3]));
--}
--
--void
- microblaze_expand_conditional_branch_sf (rtx operands[])
- {
- rtx condition;
-@@ -3501,6 +3555,12 @@
- #undef TARGET_SECONDARY_RELOAD
- #define TARGET_SECONDARY_RELOAD microblaze_secondary_reload
-
-+#undef TARGET_ASM_OUTPUT_MI_THUNK
-+#define TARGET_ASM_OUTPUT_MI_THUNK microblaze_asm_output_mi_thunk
-+
-+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
-+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
-+
- #undef TARGET_SCHED_ADJUST_COST
- #define TARGET_SCHED_ADJUST_COST microblaze_adjust_cost
-
-Index: gcc/config/microblaze/microblaze.h
-===================================================================
---- a/src/gcc/config/microblaze/microblaze.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/microblaze/microblaze.h (.../branches/gcc-4_8-branch)
-@@ -213,6 +213,12 @@
- #define STRICT_ALIGNMENT 1
- #define PCC_BITFIELD_TYPE_MATTERS 1
-
-+#undef SIZE_TYPE
-+#define SIZE_TYPE "unsigned int"
-+
-+#undef PTRDIFF_TYPE
-+#define PTRDIFF_TYPE "int"
-+
- #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
- ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
- && (ALIGN) < BITS_PER_WORD \
-@@ -407,9 +413,6 @@
- || GET_MODE (X) == VOIDmode) \
- ? (GR_REGS) : (CLASS))))
-
--#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
-- (GET_MODE_CLASS (MODE) == MODE_INT)
--
- /* Stack layout; function entry, exit and calling. */
-
- #define STACK_GROWS_DOWNWARD
-Index: gcc/config/avr/avr.md
-===================================================================
---- a/src/gcc/config/avr/avr.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/avr/avr.md (.../branches/gcc-4_8-branch)
-@@ -89,7 +89,7 @@
- (include "constraints.md")
-
- ;; Condition code settings.
--(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber,
-+(define_attr "cc" "none,set_czn,set_zn,set_vzn,set_n,compare,clobber,
- plus,ldi"
- (const_string "none"))
-
-@@ -1097,7 +1097,7 @@
- inc %0\;inc %0
- dec %0\;dec %0"
- [(set_attr "length" "1,1,1,1,2,2")
-- (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")])
-+ (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")])
-
- ;; "addhi3"
- ;; "addhq3" "adduhq3"
-@@ -1368,7 +1368,7 @@
- dec %0\;dec %0
- inc %0\;inc %0"
- [(set_attr "length" "1,1,1,1,2,2")
-- (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")])
-+ (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")])
-
- ;; "subhi3"
- ;; "subhq3" "subuhq3"
-@@ -3991,7 +3991,7 @@
- ""
- "neg %0"
- [(set_attr "length" "1")
-- (set_attr "cc" "set_zn")])
-+ (set_attr "cc" "set_vzn")])
-
- (define_insn "*negqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
-Index: gcc/config/avr/avr.c
-===================================================================
---- a/src/gcc/config/avr/avr.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/avr/avr.c (.../branches/gcc-4_8-branch)
-@@ -587,10 +587,14 @@
- const char *name;
-
- name = DECL_ASSEMBLER_NAME_SET_P (decl)
-- /* Remove the leading '*' added in set_user_assembler_name. */
-- ? 1 + IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))
-+ ? IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))
- : IDENTIFIER_POINTER (DECL_NAME (decl));
-
-+ /* Skip a leading '*' that might still prefix the assembler name,
-+ e.g. in non-LTO runs. */
-+
-+ name = default_strip_name_encoding (name);
-+
- /* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet
- using this when it switched from SIGNAL and INTERRUPT to ISR. */
-
-@@ -2339,6 +2343,12 @@
- }
- break;
-
-+ case CC_SET_VZN:
-+ /* Insn like INC, DEC, NEG that set Z,N,V. We currently don't make use
-+ of this combination, cf. also PR61055. */
-+ CC_STATUS_INIT;
-+ break;
-+
- case CC_SET_CZN:
- /* Insn sets the Z,N,C flags of CC to recog_operand[0].
- The V flag may or may not be known but that's ok because
-@@ -3977,7 +3987,7 @@
- "std Y+61,%A1" CR_TAB
- "std Y+62,%B1" CR_TAB
- "std Y+63,%C1" CR_TAB
-- "sbiw r28,%o0-60", op, plen, -5);
-+ "sbiw r28,%o0-61", op, plen, -5);
-
- return avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB
- "sbci r29,hi8(-%o0)" CR_TAB
-@@ -6274,7 +6284,7 @@
-
- if (REG_P (xop[2]))
- {
-- *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_SET_N;
-+ *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_CLOBBER;
-
- for (i = 0; i < n_bytes; i++)
- {
-@@ -6383,7 +6393,7 @@
- op, plen, 1);
-
- if (n_bytes == 2 && PLUS == code)
-- *pcc = CC_SET_ZN;
-+ *pcc = CC_SET_CZN;
- }
-
- i++;
-@@ -6406,6 +6416,7 @@
- {
- avr_asm_len ((code == PLUS) ^ (val8 == 1) ? "dec %0" : "inc %0",
- op, plen, 1);
-+ *pcc = CC_CLOBBER;
- break;
- }
-
-@@ -6806,8 +6817,8 @@
-
- /* Work out the shortest sequence. */
-
-- avr_out_plus_1 (op, &len_minus, MINUS, &cc_plus, code_sat, sign, out_label);
-- avr_out_plus_1 (op, &len_plus, PLUS, &cc_minus, code_sat, sign, out_label);
-+ avr_out_plus_1 (op, &len_minus, MINUS, &cc_minus, code_sat, sign, out_label);
-+ avr_out_plus_1 (op, &len_plus, PLUS, &cc_plus, code_sat, sign, out_label);
-
- if (plen)
- {
-Index: gcc/config/cris/cris.md
-===================================================================
---- a/src/gcc/config/cris/cris.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/cris/cris.md (.../branches/gcc-4_8-branch)
-@@ -758,7 +758,7 @@
- (match_operand:SI 1 "const_int_operand" ""))
- (match_operand:SI 2 "register_operand" ""))])
- (match_operand 3 "register_operand" ""))
-- (set (match_operand:SI 4 "register_operand" "")
-+ (set (match_operand:SI 4 "cris_nonsp_register_operand" "")
- (plus:SI (mult:SI (match_dup 0)
- (match_dup 1))
- (match_dup 2)))])]
-@@ -859,7 +859,7 @@
- (match_operand:SI 0 "cris_bdap_operand" "")
- (match_operand:SI 1 "cris_bdap_operand" ""))])
- (match_operand 2 "register_operand" ""))
-- (set (match_operand:SI 3 "register_operand" "")
-+ (set (match_operand:SI 3 "cris_nonsp_register_operand" "")
- (plus:SI (match_dup 0) (match_dup 1)))])]
- "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
- [(set (match_dup 4) (match_dup 2))
-@@ -3960,7 +3960,7 @@
- ;; up.
-
- (define_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operator
- 4 "cris_operand_extend_operator"
- [(match_operand 1 "register_operand" "")
-@@ -3990,7 +3990,7 @@
- ;; Call this op-extend-split-rx=rz
-
- (define_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operator
- 4 "cris_plus_or_bound_operator"
- [(match_operand 1 "register_operand" "")
-@@ -4018,7 +4018,7 @@
- ;; Call this op-extend-split-swapped
-
- (define_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operator
- 4 "cris_plus_or_bound_operator"
- [(match_operator
-@@ -4044,7 +4044,7 @@
- ;; bound. Call this op-extend-split-swapped-rx=rz.
-
- (define_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operator
- 4 "cris_plus_or_bound_operator"
- [(match_operator
-@@ -4075,7 +4075,7 @@
- ;; Call this op-extend.
-
- (define_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operator
- 3 "cris_orthogonal_operator"
- [(match_operand 1 "register_operand" "")
-@@ -4099,7 +4099,7 @@
- ;; Call this op-split-rx=rz
-
- (define_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operator
- 3 "cris_commutative_orth_op"
- [(match_operand 2 "memory_operand" "")
-@@ -4123,7 +4123,7 @@
- ;; Call this op-split-swapped.
-
- (define_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operator
- 3 "cris_commutative_orth_op"
- [(match_operand 1 "register_operand" "")
-@@ -4146,7 +4146,7 @@
- ;; Call this op-split-swapped-rx=rz.
-
- (define_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operator
- 3 "cris_orthogonal_operator"
- [(match_operand 2 "memory_operand" "")
-@@ -4555,10 +4555,11 @@
- ;; We're not allowed to generate copies of registers with different mode
- ;; until after reload; copying pseudos upsets reload. CVS as of
- ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
--;; cselib_invalidate_regno.
-+;; cselib_invalidate_regno. Also, don't do this for the stack-pointer,
-+;; as we don't want it set temporarily to an invalid value.
-
- (define_split ; indir_to_reg_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operand 1 "indirect_operand" ""))]
- "reload_completed
- && REG_P (operands[0])
-@@ -4574,7 +4575,7 @@
- ;; As the above, but MOVS and MOVU.
-
- (define_split
-- [(set (match_operand 0 "register_operand" "")
-+ [(set (match_operand 0 "cris_nonsp_register_operand" "")
- (match_operator
- 4 "cris_extend_operator"
- [(match_operand 1 "indirect_operand" "")]))]
-Index: gcc/config/cris/predicates.md
-===================================================================
---- a/src/gcc/config/cris/predicates.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/cris/predicates.md (.../branches/gcc-4_8-branch)
-@@ -76,6 +76,10 @@
- (match_test "cris_simple_address_operand (XEXP (op, 0),
- Pmode)"))))
-
-+(define_predicate "cris_nonsp_register_operand"
-+ (and (match_operand 0 "register_operand")
-+ (match_test "op != stack_pointer_rtx")))
-+
- ;; The caller needs to use :SI.
- (define_predicate "cris_bdap_sign_extend_operand"
- ; Disabled until <URL:http://gcc.gnu.org/ml/gcc-patches/2005-10/msg01376.html>
-Index: gcc/config/m68k/m68k.c
-===================================================================
---- a/src/gcc/config/m68k/m68k.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/m68k/m68k.c (.../branches/gcc-4_8-branch)
-@@ -3325,12 +3325,12 @@
- latehalf[1] = adjust_address (operands[1], SImode, 0);
- }
-
-- /* If insn is effectively movd N(sp),-(sp) then we will do the
-- high word first. We should use the adjusted operand 1 (which is N+4(sp))
-- for the low word as well, to compensate for the first decrement of sp. */
-+ /* If insn is effectively movd N(REG),-(REG) then we will do the high
-+ word first. We should use the adjusted operand 1 (which is N+4(REG))
-+ for the low word as well, to compensate for the first decrement of
-+ REG. */
- if (optype0 == PUSHOP
-- && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
-- && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
-+ && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1]))
- operands[1] = middlehalf[1] = latehalf[1];
-
- /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
-Index: gcc/config/aarch64/aarch64-simd.md
-===================================================================
---- a/src/gcc/config/aarch64/aarch64-simd.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/aarch64/aarch64-simd.md (.../branches/gcc-4_8-branch)
-@@ -21,7 +21,7 @@
-
- ; Main data types used by the insntructions
-
--(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,HI,QI"
-+(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI"
- (const_string "unknown"))
-
-
-@@ -1548,12 +1548,12 @@
-
- case LTU:
- case GEU:
-- emit_insn (gen_aarch64_cmhs<mode> (mask, operands[4], operands[5]));
-+ emit_insn (gen_aarch64_cmgeu<mode> (mask, operands[4], operands[5]));
- break;
-
- case LEU:
- case GTU:
-- emit_insn (gen_aarch64_cmhi<mode> (mask, operands[4], operands[5]));
-+ emit_insn (gen_aarch64_cmgtu<mode> (mask, operands[4], operands[5]));
- break;
-
- case NE:
-@@ -3034,48 +3034,181 @@
- )
-
-
--;; cm(eq|ge|le|lt|gt)
-+;; cm(eq|ge|gt|lt|le)
-+;; Note, we have constraints for Dz and Z as different expanders
-+;; have different ideas of what should be passed to this pattern.
-
--(define_insn "aarch64_cm<cmp><mode>"
-+(define_insn "aarch64_cm<optab><mode>"
- [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
-- (unspec:<V_cmp_result>
-- [(match_operand:VSDQ_I_DI 1 "register_operand" "w,w")
-- (match_operand:VSDQ_I_DI 2 "aarch64_simd_reg_or_zero" "w,Z")]
-- VCMP_S))]
-+ (neg:<V_cmp_result>
-+ (COMPARISONS:<V_cmp_result>
-+ (match_operand:VDQ 1 "register_operand" "w,w")
-+ (match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz")
-+ )))]
- "TARGET_SIMD"
- "@
-- cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>
-- cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"
-+ cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
-+ cm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"
- [(set_attr "simd_type" "simd_cmp")
- (set_attr "simd_mode" "<MODE>")]
- )
-
--;; cm(hs|hi|tst)
-+(define_insn_and_split "aarch64_cm<optab>di"
-+ [(set (match_operand:DI 0 "register_operand" "=w,w,r")
-+ (neg:DI
-+ (COMPARISONS:DI
-+ (match_operand:DI 1 "register_operand" "w,w,r")
-+ (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz,r")
-+ )))]
-+ "TARGET_SIMD"
-+ "@
-+ cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>
-+ cm<optab>\t%d0, %d1, #0
-+ #"
-+ "reload_completed
-+ /* We need to prevent the split from
-+ happening in the 'w' constraint cases. */
-+ && GP_REGNUM_P (REGNO (operands[0]))
-+ && GP_REGNUM_P (REGNO (operands[1]))"
-+ [(set (reg:CC CC_REGNUM)
-+ (compare:CC
-+ (match_dup 1)
-+ (match_dup 2)))
-+ (set (match_dup 0)
-+ (neg:DI
-+ (COMPARISONS:DI
-+ (match_operand 3 "cc_register" "")
-+ (const_int 0))))]
-+ {
-+ enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);
-+ rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
-+ rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
-+ emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
-+ DONE;
-+ }
-+ [(set_attr "simd_type" "simd_cmp")
-+ (set_attr "simd_mode" "DI")]
-+)
-
--(define_insn "aarch64_cm<cmp><mode>"
-+;; cm(hs|hi)
-+
-+(define_insn "aarch64_cm<optab><mode>"
- [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
-- (unspec:<V_cmp_result>
-- [(match_operand:VSDQ_I_DI 1 "register_operand" "w")
-- (match_operand:VSDQ_I_DI 2 "register_operand" "w")]
-- VCMP_U))]
-+ (neg:<V_cmp_result>
-+ (UCOMPARISONS:<V_cmp_result>
-+ (match_operand:VDQ 1 "register_operand" "w")
-+ (match_operand:VDQ 2 "register_operand" "w")
-+ )))]
- "TARGET_SIMD"
-- "cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
-+ "cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
- [(set_attr "simd_type" "simd_cmp")
- (set_attr "simd_mode" "<MODE>")]
- )
-
--;; fcm(eq|ge|le|lt|gt)
-+(define_insn_and_split "aarch64_cm<optab>di"
-+ [(set (match_operand:DI 0 "register_operand" "=w,r")
-+ (neg:DI
-+ (UCOMPARISONS:DI
-+ (match_operand:DI 1 "register_operand" "w,r")
-+ (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,r")
-+ )))]
-+ "TARGET_SIMD"
-+ "@
-+ cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>
-+ #"
-+ "reload_completed
-+ /* We need to prevent the split from
-+ happening in the 'w' constraint cases. */
-+ && GP_REGNUM_P (REGNO (operands[0]))
-+ && GP_REGNUM_P (REGNO (operands[1]))"
-+ [(set (reg:CC CC_REGNUM)
-+ (compare:CC
-+ (match_dup 1)
-+ (match_dup 2)))
-+ (set (match_dup 0)
-+ (neg:DI
-+ (UCOMPARISONS:DI
-+ (match_operand 3 "cc_register" "")
-+ (const_int 0))))]
-+ {
-+ enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);
-+ rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
-+ rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
-+ emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
-+ DONE;
-+ }
-+ [(set_attr "simd_type" "simd_cmp")
-+ (set_attr "simd_mode" "DI")]
-+)
-
--(define_insn "aarch64_cm<cmp><mode>"
-+;; cmtst
-+
-+(define_insn "aarch64_cmtst<mode>"
-+ [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
-+ (neg:<V_cmp_result>
-+ (ne:<V_cmp_result>
-+ (and:VDQ
-+ (match_operand:VDQ 1 "register_operand" "w")
-+ (match_operand:VDQ 2 "register_operand" "w"))
-+ (vec_duplicate:<V_cmp_result> (const_int 0)))))]
-+ "TARGET_SIMD"
-+ "cmtst\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
-+ [(set_attr "simd_type" "simd_cmp")
-+ (set_attr "simd_mode" "<MODE>")]
-+)
-+
-+(define_insn_and_split "aarch64_cmtstdi"
-+ [(set (match_operand:DI 0 "register_operand" "=w,r")
-+ (neg:DI
-+ (ne:DI
-+ (and:DI
-+ (match_operand:DI 1 "register_operand" "w,r")
-+ (match_operand:DI 2 "register_operand" "w,r"))
-+ (const_int 0))))]
-+ "TARGET_SIMD"
-+ "@
-+ cmtst\t%d0, %d1, %d2
-+ #"
-+ "reload_completed
-+ /* We need to prevent the split from
-+ happening in the 'w' constraint cases. */
-+ && GP_REGNUM_P (REGNO (operands[0]))
-+ && GP_REGNUM_P (REGNO (operands[1]))"
-+ [(set (reg:CC_NZ CC_REGNUM)
-+ (compare:CC_NZ
-+ (and:DI (match_dup 1)
-+ (match_dup 2))
-+ (const_int 0)))
-+ (set (match_dup 0)
-+ (neg:DI
-+ (ne:DI
-+ (match_operand 3 "cc_register" "")
-+ (const_int 0))))]
-+ {
-+ rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]);
-+ enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx);
-+ rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);
-+ rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx);
-+ emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
-+ DONE;
-+ }
-+ [(set_attr "simd_type" "simd_cmp")
-+ (set_attr "simd_mode" "DI")]
-+)
-+
-+;; fcm(eq|ge|gt|le|lt)
-+
-+(define_insn "aarch64_cm<optab><mode>"
- [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
-- (unspec:<V_cmp_result>
-- [(match_operand:VDQF 1 "register_operand" "w,w")
-- (match_operand:VDQF 2 "aarch64_simd_reg_or_zero" "w,Dz")]
-- VCMP_S))]
-+ (neg:<V_cmp_result>
-+ (COMPARISONS:<V_cmp_result>
-+ (match_operand:VALLF 1 "register_operand" "w,w")
-+ (match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz")
-+ )))]
- "TARGET_SIMD"
- "@
-- fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>
-- fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
-+ fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
-+ fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
- [(set_attr "simd_type" "simd_fcmp")
- (set_attr "simd_mode" "<MODE>")]
- )
-Index: gcc/config/aarch64/predicates.md
-===================================================================
---- a/src/gcc/config/aarch64/predicates.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/aarch64/predicates.md (.../branches/gcc-4_8-branch)
-@@ -31,6 +31,11 @@
- (ior (match_operand 0 "register_operand")
- (match_test "op == const0_rtx"))))
-
-+(define_predicate "aarch64_reg_or_fp_zero"
-+ (and (match_code "reg,subreg,const_double")
-+ (ior (match_operand 0 "register_operand")
-+ (match_test "aarch64_float_const_zero_rtx_p (op)"))))
-+
- (define_predicate "aarch64_reg_zero_or_m1_or_1"
- (and (match_code "reg,subreg,const_int")
- (ior (match_operand 0 "register_operand")
-Index: gcc/config/aarch64/arm_neon.h
-===================================================================
---- a/src/gcc/config/aarch64/arm_neon.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/aarch64/arm_neon.h (.../branches/gcc-4_8-branch)
-@@ -19551,7 +19551,7 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcge_u8 (uint8x8_t __a, uint8x8_t __b)
- {
-- return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __a,
-+ return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __a,
- (int8x8_t) __b);
- }
-
-@@ -19558,7 +19558,7 @@
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcge_u16 (uint16x4_t __a, uint16x4_t __b)
- {
-- return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __a,
-+ return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __a,
- (int16x4_t) __b);
- }
-
-@@ -19565,7 +19565,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcge_u32 (uint32x2_t __a, uint32x2_t __b)
- {
-- return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __a,
-+ return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __a,
- (int32x2_t) __b);
- }
-
-@@ -19572,7 +19572,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vcge_u64 (uint64x1_t __a, uint64x1_t __b)
- {
-- return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a,
-+ return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a,
- (int64x1_t) __b);
- }
-
-@@ -19603,7 +19603,7 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
-- return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __a,
-+ return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __a,
- (int8x16_t) __b);
- }
-
-@@ -19610,7 +19610,7 @@
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
-- return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __a,
-+ return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __a,
- (int16x8_t) __b);
- }
-
-@@ -19617,7 +19617,7 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
-- return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __a,
-+ return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __a,
- (int32x4_t) __b);
- }
-
-@@ -19624,7 +19624,7 @@
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgeq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
-- return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __a,
-+ return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __a,
- (int64x2_t) __b);
- }
-
-@@ -19637,7 +19637,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vcged_u64 (uint64x1_t __a, uint64x1_t __b)
- {
-- return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a,
-+ return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a,
- (int64x1_t) __b);
- }
-
-@@ -19676,7 +19676,7 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcgt_u8 (uint8x8_t __a, uint8x8_t __b)
- {
-- return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __a,
-+ return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __a,
- (int8x8_t) __b);
- }
-
-@@ -19683,7 +19683,7 @@
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcgt_u16 (uint16x4_t __a, uint16x4_t __b)
- {
-- return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __a,
-+ return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __a,
- (int16x4_t) __b);
- }
-
-@@ -19690,7 +19690,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcgt_u32 (uint32x2_t __a, uint32x2_t __b)
- {
-- return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __a,
-+ return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __a,
- (int32x2_t) __b);
- }
-
-@@ -19697,7 +19697,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vcgt_u64 (uint64x1_t __a, uint64x1_t __b)
- {
-- return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a,
-+ return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a,
- (int64x1_t) __b);
- }
-
-@@ -19728,7 +19728,7 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
-- return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __a,
-+ return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __a,
- (int8x16_t) __b);
- }
-
-@@ -19735,7 +19735,7 @@
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
-- return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __a,
-+ return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __a,
- (int16x8_t) __b);
- }
-
-@@ -19742,7 +19742,7 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
-- return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __a,
-+ return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __a,
- (int32x4_t) __b);
- }
-
-@@ -19749,7 +19749,7 @@
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgtq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
-- return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __a,
-+ return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __a,
- (int64x2_t) __b);
- }
-
-@@ -19762,7 +19762,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vcgtd_u64 (uint64x1_t __a, uint64x1_t __b)
- {
-- return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a,
-+ return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a,
- (int64x1_t) __b);
- }
-
-@@ -19801,7 +19801,7 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcle_u8 (uint8x8_t __a, uint8x8_t __b)
- {
-- return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __b,
-+ return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __b,
- (int8x8_t) __a);
- }
-
-@@ -19808,7 +19808,7 @@
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcle_u16 (uint16x4_t __a, uint16x4_t __b)
- {
-- return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __b,
-+ return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __b,
- (int16x4_t) __a);
- }
-
-@@ -19815,7 +19815,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcle_u32 (uint32x2_t __a, uint32x2_t __b)
- {
-- return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __b,
-+ return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __b,
- (int32x2_t) __a);
- }
-
-@@ -19822,7 +19822,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vcle_u64 (uint64x1_t __a, uint64x1_t __b)
- {
-- return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __b,
-+ return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __b,
- (int64x1_t) __a);
- }
-
-@@ -19853,7 +19853,7 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcleq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
-- return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __b,
-+ return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __b,
- (int8x16_t) __a);
- }
-
-@@ -19860,7 +19860,7 @@
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcleq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
-- return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __b,
-+ return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __b,
- (int16x8_t) __a);
- }
-
-@@ -19867,7 +19867,7 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcleq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
-- return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __b,
-+ return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __b,
- (int32x4_t) __a);
- }
-
-@@ -19874,7 +19874,7 @@
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcleq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
-- return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __b,
-+ return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __b,
- (int64x2_t) __a);
- }
-
-@@ -19919,7 +19919,7 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vclt_u8 (uint8x8_t __a, uint8x8_t __b)
- {
-- return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __b,
-+ return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __b,
- (int8x8_t) __a);
- }
-
-@@ -19926,7 +19926,7 @@
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vclt_u16 (uint16x4_t __a, uint16x4_t __b)
- {
-- return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __b,
-+ return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __b,
- (int16x4_t) __a);
- }
-
-@@ -19933,7 +19933,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vclt_u32 (uint32x2_t __a, uint32x2_t __b)
- {
-- return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __b,
-+ return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __b,
- (int32x2_t) __a);
- }
-
-@@ -19940,7 +19940,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vclt_u64 (uint64x1_t __a, uint64x1_t __b)
- {
-- return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __b,
-+ return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __b,
- (int64x1_t) __a);
- }
-
-@@ -19971,7 +19971,7 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcltq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
-- return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __b,
-+ return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __b,
- (int8x16_t) __a);
- }
-
-@@ -19978,7 +19978,7 @@
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcltq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
-- return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __b,
-+ return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __b,
- (int16x8_t) __a);
- }
-
-@@ -19985,7 +19985,7 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcltq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
-- return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __b,
-+ return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __b,
- (int32x4_t) __a);
- }
-
-@@ -19992,7 +19992,7 @@
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcltq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
-- return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __b,
-+ return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __b,
- (int64x2_t) __a);
- }
-
-Index: gcc/config/aarch64/aarch64.md
-===================================================================
---- a/src/gcc/config/aarch64/aarch64.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/aarch64/aarch64.md (.../branches/gcc-4_8-branch)
-@@ -2211,7 +2211,7 @@
- (set_attr "mode" "SI")]
- )
-
--(define_insn "*cstore<mode>_neg"
-+(define_insn "cstore<mode>_neg"
- [(set (match_operand:ALLI 0 "register_operand" "=r")
- (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator"
- [(match_operand 2 "cc_register" "") (const_int 0)])))]
-Index: gcc/config/aarch64/aarch64-simd-builtins.def
-===================================================================
---- a/src/gcc/config/aarch64/aarch64-simd-builtins.def (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def (.../branches/gcc-4_8-branch)
-@@ -217,8 +217,8 @@
- BUILTIN_VSDQ_I_DI (BINOP, cmle)
- BUILTIN_VSDQ_I_DI (BINOP, cmlt)
- /* Implemented by aarch64_cm<cmp><mode>. */
-- BUILTIN_VSDQ_I_DI (BINOP, cmhs)
-- BUILTIN_VSDQ_I_DI (BINOP, cmhi)
-+ BUILTIN_VSDQ_I_DI (BINOP, cmgeu)
-+ BUILTIN_VSDQ_I_DI (BINOP, cmgtu)
- BUILTIN_VSDQ_I_DI (BINOP, cmtst)
-
- /* Implemented by aarch64_<fmaxmin><mode>. */
-Index: gcc/config/aarch64/aarch64.c
-===================================================================
---- a/src/gcc/config/aarch64/aarch64.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/aarch64/aarch64.c (.../branches/gcc-4_8-branch)
-@@ -2274,7 +2274,7 @@
- if (ncount < zcount)
- {
- emit_move_insn (gen_rtx_REG (Pmode, regnum),
-- GEN_INT ((~val) & 0xffff));
-+ GEN_INT (val | ~(HOST_WIDE_INT) 0xffff));
- tval = 0xffff;
- }
- else
-@@ -4568,9 +4568,11 @@
- }
-
- static int
--aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
-- reg_class_t from, reg_class_t to)
-+aarch64_register_move_cost (enum machine_mode mode,
-+ reg_class_t from_i, reg_class_t to_i)
- {
-+ enum reg_class from = (enum reg_class) from_i;
-+ enum reg_class to = (enum reg_class) to_i;
- const struct cpu_regmove_cost *regmove_cost
- = aarch64_tune_params->regmove_cost;
-
-@@ -4586,8 +4588,7 @@
- secondary reload. A general register is used as a scratch to move
- the upper DI value and the lower DI value is moved directly,
- hence the cost is the sum of three moves. */
--
-- if (! TARGET_SIMD && GET_MODE_SIZE (from) == 128 && GET_MODE_SIZE (to) == 128)
-+ if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128)
- return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP;
-
- return regmove_cost->FP2FP;
-Index: gcc/config/aarch64/iterators.md
-===================================================================
---- a/src/gcc/config/aarch64/iterators.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/aarch64/iterators.md (.../branches/gcc-4_8-branch)
-@@ -83,6 +83,9 @@
- ;; Vector Float modes.
- (define_mode_iterator VDQF [V2SF V4SF V2DF])
-
-+;; All Float modes.
-+(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
-+
- ;; Vector Float modes with 2 elements.
- (define_mode_iterator V2F [V2SF V2DF])
-
-@@ -213,13 +216,6 @@
- UNSPEC_URSHL ; Used in aarch64-simd.md.
- UNSPEC_SQRSHL ; Used in aarch64-simd.md.
- UNSPEC_UQRSHL ; Used in aarch64-simd.md.
-- UNSPEC_CMEQ ; Used in aarch64-simd.md.
-- UNSPEC_CMLE ; Used in aarch64-simd.md.
-- UNSPEC_CMLT ; Used in aarch64-simd.md.
-- UNSPEC_CMGE ; Used in aarch64-simd.md.
-- UNSPEC_CMGT ; Used in aarch64-simd.md.
-- UNSPEC_CMHS ; Used in aarch64-simd.md.
-- UNSPEC_CMHI ; Used in aarch64-simd.md.
- UNSPEC_SSLI ; Used in aarch64-simd.md.
- UNSPEC_USLI ; Used in aarch64-simd.md.
- UNSPEC_SSRI ; Used in aarch64-simd.md.
-@@ -227,7 +223,6 @@
- UNSPEC_SSHLL ; Used in aarch64-simd.md.
- UNSPEC_USHLL ; Used in aarch64-simd.md.
- UNSPEC_ADDP ; Used in aarch64-simd.md.
-- UNSPEC_CMTST ; Used in aarch64-simd.md.
- UNSPEC_FMAX ; Used in aarch64-simd.md.
- UNSPEC_FMIN ; Used in aarch64-simd.md.
- UNSPEC_BSL ; Used in aarch64-simd.md.
-@@ -251,6 +246,7 @@
-
- ;; For scalar usage of vector/FP registers
- (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
-+ (SF "s") (DF "d")
- (V8QI "") (V16QI "")
- (V4HI "") (V8HI "")
- (V2SI "") (V4SI "")
-@@ -305,7 +301,8 @@
- (V4SF ".4s") (V2DF ".2d")
- (DI "") (SI "")
- (HI "") (QI "")
-- (TI "")])
-+ (TI "") (SF "")
-+ (DF "")])
-
- ;; Register suffix narrowed modes for VQN.
- (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
-@@ -444,7 +441,8 @@
- (V2SI "V2SI") (V4SI "V4SI")
- (DI "DI") (V2DI "V2DI")
- (V2SF "V2SI") (V4SF "V4SI")
-- (V2DF "V2DI")])
-+ (V2DF "V2DI") (DF "DI")
-+ (SF "SI")])
-
- ;; Lower case mode of results of comparison operations.
- (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
-@@ -452,7 +450,8 @@
- (V2SI "v2si") (V4SI "v4si")
- (DI "di") (V2DI "v2di")
- (V2SF "v2si") (V4SF "v4si")
-- (V2DF "v2di")])
-+ (V2DF "v2di") (DF "di")
-+ (SF "si")])
-
- ;; Vm for lane instructions is restricted to FP_LO_REGS.
- (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
-@@ -543,6 +542,12 @@
- ;; Code iterator for signed variants of vector saturating binary ops.
- (define_code_iterator SBINQOPS [ss_plus ss_minus])
-
-+;; Comparison operators for <F>CM.
-+(define_code_iterator COMPARISONS [lt le eq ge gt])
-+
-+;; Unsigned comparison operators.
-+(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
-+
- ;; -------------------------------------------------------------------
- ;; Code Attributes
- ;; -------------------------------------------------------------------
-@@ -571,8 +576,29 @@
- (eq "eq")
- (ne "ne")
- (lt "lt")
-- (ge "ge")])
-+ (ge "ge")
-+ (le "le")
-+ (gt "gt")
-+ (ltu "ltu")
-+ (leu "leu")
-+ (geu "geu")
-+ (gtu "gtu")])
-
-+;; For comparison operators we use the FCM* and CM* instructions.
-+;; As there are no CMLE or CMLT instructions which act on 3 vector
-+;; operands, we must use CMGE or CMGT and swap the order of the
-+;; source operands.
-+
-+(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
-+ (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
-+(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
-+ (ltu "2") (leu "2") (geu "1") (gtu "1")])
-+(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
-+ (ltu "1") (leu "1") (geu "2") (gtu "2")])
-+
-+(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
-+ (ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")])
-+
- ;; Optab prefix for sign/zero-extending operations
- (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
- (div "") (udiv "u")
-@@ -680,11 +706,6 @@
- UNSPEC_SQSHRN UNSPEC_UQSHRN
- UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
-
--(define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT
-- UNSPEC_CMLE UNSPEC_CMLT])
--
--(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST])
--
- (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
- UNSPEC_TRN1 UNSPEC_TRN2
- UNSPEC_UZP1 UNSPEC_UZP2])
-@@ -768,12 +789,6 @@
- (UNSPEC_RADDHN2 "add")
- (UNSPEC_RSUBHN2 "sub")])
-
--(define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt")
-- (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt")
-- (UNSPEC_CMEQ "eq")
-- (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi")
-- (UNSPEC_CMTST "tst")])
--
- (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1")
- (UNSPEC_SSRI "0") (UNSPEC_USRI "0")])
-
-Index: gcc/config/aarch64/aarch64.h
-===================================================================
---- a/src/gcc/config/aarch64/aarch64.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/aarch64/aarch64.h (.../branches/gcc-4_8-branch)
-@@ -73,9 +73,9 @@
- #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
-
- /* AdvSIMD is supported in the default configuration, unless disabled by
-- -mgeneral-regs-only. */
--#define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY
--#define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY
-+ -mgeneral-regs-only or the +nosimd extension. */
-+#define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
-+#define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
-
- #define UNITS_PER_WORD 8
-
-Index: gcc/config/rs6000/power8.md
-===================================================================
---- a/src/gcc/config/rs6000/power8.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/power8.md (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,373 @@
-+;; Scheduling description for IBM POWER8 processor.
-+;; Copyright (C) 2013 Free Software Foundation, Inc.
-+;;
-+;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
-+
-+;; This file is part of GCC.
-+;;
-+;; GCC is free software; you can redistribute it and/or modify it
-+;; under the terms of the GNU General Public License as published
-+;; by the Free Software Foundation; either version 3, or (at your
-+;; option) any later version.
-+;;
-+;; GCC is distributed in the hope that it will be useful, but WITHOUT
-+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-+;; License for more details.
-+;;
-+;; You should have received a copy of the GNU General Public License
-+;; along with GCC; see the file COPYING3. If not see
-+;; <http://www.gnu.org/licenses/>.
-+
-+(define_automaton "power8fxu,power8lsu,power8vsu,power8misc")
-+
-+(define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu")
-+(define_cpu_unit "lu0_power8,lu1_power8" "power8lsu")
-+(define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu")
-+(define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu")
-+(define_cpu_unit "bpu_power8,cru_power8" "power8misc")
-+(define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\
-+ du5_power8,du6_power8" "power8misc")
-+
-+
-+; Dispatch group reservations
-+(define_reservation "DU_any_power8"
-+ "du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\
-+ du5_power8")
-+
-+; 2-way Cracked instructions go in slots 0-1
-+; (can also have a second in slots 3-4 if insns are adjacent)
-+(define_reservation "DU_cracked_power8"
-+ "du0_power8+du1_power8")
-+
-+; Insns that are first in group
-+(define_reservation "DU_first_power8"
-+ "du0_power8")
-+
-+; Insns that are first and last in group
-+(define_reservation "DU_both_power8"
-+ "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\
-+ du5_power8+du6_power8")
-+
-+; Dispatch slots are allocated in order conforming to program order.
-+(absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\
-+ du5_power8,du6_power8")
-+(absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\
-+ du6_power8")
-+(absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8")
-+(absence_set "du3_power8" "du4_power8,du5_power8,du6_power8")
-+(absence_set "du4_power8" "du5_power8,du6_power8")
-+(absence_set "du5_power8" "du6_power8")
-+
-+
-+; Execution unit reservations
-+(define_reservation "FXU_power8"
-+ "fxu0_power8|fxu1_power8")
-+
-+(define_reservation "LU_power8"
-+ "lu0_power8|lu1_power8")
-+
-+(define_reservation "LSU_power8"
-+ "lsu0_power8|lsu1_power8")
-+
-+(define_reservation "LU_or_LSU_power8"
-+ "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8")
-+
-+(define_reservation "VSU_power8"
-+ "vsu0_power8|vsu1_power8")
-+
-+
-+; LS Unit
-+(define_insn_reservation "power8-load" 3
-+ (and (eq_attr "type" "load")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,LU_or_LSU_power8")
-+
-+(define_insn_reservation "power8-load-update" 3
-+ (and (eq_attr "type" "load_u,load_ux")
-+ (eq_attr "cpu" "power8"))
-+ "DU_cracked_power8,LU_or_LSU_power8+FXU_power8")
-+
-+(define_insn_reservation "power8-load-ext" 3
-+ (and (eq_attr "type" "load_ext")
-+ (eq_attr "cpu" "power8"))
-+ "DU_cracked_power8,LU_or_LSU_power8,FXU_power8")
-+
-+(define_insn_reservation "power8-load-ext-update" 3
-+ (and (eq_attr "type" "load_ext_u,load_ext_ux")
-+ (eq_attr "cpu" "power8"))
-+ "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")
-+
-+(define_insn_reservation "power8-fpload" 5
-+ (and (eq_attr "type" "fpload,vecload")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,LU_power8")
-+
-+(define_insn_reservation "power8-fpload-update" 5
-+ (and (eq_attr "type" "fpload_u,fpload_ux")
-+ (eq_attr "cpu" "power8"))
-+ "DU_cracked_power8,LU_power8+FXU_power8")
-+
-+(define_insn_reservation "power8-store" 5 ; store-forwarding latency
-+ (and (eq_attr "type" "store,store_u")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,LSU_power8+LU_power8")
-+
-+(define_insn_reservation "power8-store-update-indexed" 5
-+ (and (eq_attr "type" "store_ux")
-+ (eq_attr "cpu" "power8"))
-+ "DU_cracked_power8,LSU_power8+LU_power8")
-+
-+(define_insn_reservation "power8-fpstore" 5
-+ (and (eq_attr "type" "fpstore")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,LSU_power8+VSU_power8")
-+
-+(define_insn_reservation "power8-fpstore-update" 5
-+ (and (eq_attr "type" "fpstore_u,fpstore_ux")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,LSU_power8+VSU_power8")
-+
-+(define_insn_reservation "power8-vecstore" 5
-+ (and (eq_attr "type" "vecstore")
-+ (eq_attr "cpu" "power8"))
-+ "DU_cracked_power8,LSU_power8+VSU_power8")
-+
-+(define_insn_reservation "power8-larx" 3
-+ (and (eq_attr "type" "load_l")
-+ (eq_attr "cpu" "power8"))
-+ "DU_both_power8,LU_or_LSU_power8")
-+
-+(define_insn_reservation "power8-stcx" 10
-+ (and (eq_attr "type" "store_c")
-+ (eq_attr "cpu" "power8"))
-+ "DU_both_power8,LSU_power8+LU_power8")
-+
-+(define_insn_reservation "power8-sync" 1
-+ (and (eq_attr "type" "sync,isync")
-+ (eq_attr "cpu" "power8"))
-+ "DU_both_power8,LSU_power8")
-+
-+
-+; FX Unit
-+(define_insn_reservation "power8-1cyc" 1
-+ (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
-+ var_shift_rotate,exts,isel")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,FXU_power8")
-+
-+; Extra cycle to LU/LSU
-+(define_bypass 2 "power8-1cyc"
-+ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
-+ power8-vecstore,power8-larx,power8-stcx")
-+; "power8-load,power8-load-update,power8-load-ext,\
-+; power8-load-ext-update,power8-fpload,power8-fpload-update,\
-+; power8-store,power8-store-update,power8-store-update-indexed,\
-+; power8-fpstore,power8-fpstore-update,power8-vecstore,\
-+; power8-larx,power8-stcx")
-+
-+(define_insn_reservation "power8-2cyc" 2
-+ (and (eq_attr "type" "cntlz,popcnt")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,FXU_power8")
-+
-+(define_insn_reservation "power8-two" 2
-+ (and (eq_attr "type" "two")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8")
-+
-+(define_insn_reservation "power8-three" 3
-+ (and (eq_attr "type" "three")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8")
-+
-+; cmp - Normal compare insns
-+(define_insn_reservation "power8-cmp" 2
-+ (and (eq_attr "type" "cmp")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,FXU_power8")
-+
-+; fast_compare : add./and./nor./etc
-+(define_insn_reservation "power8-fast-compare" 2
-+ (and (eq_attr "type" "fast_compare")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,FXU_power8")
-+
-+; compare : rldicl./exts./etc
-+; delayed_compare : rlwinm./slwi./etc
-+; var_delayed_compare : rlwnm./slw./etc
-+(define_insn_reservation "power8-compare" 2
-+ (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
-+ (eq_attr "cpu" "power8"))
-+ "DU_cracked_power8,FXU_power8,FXU_power8")
-+
-+; Extra cycle to LU/LSU
-+(define_bypass 3 "power8-fast-compare,power8-compare"
-+ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
-+ power8-vecstore,power8-larx,power8-stcx")
-+
-+; 5 cycle CR latency
-+(define_bypass 5 "power8-fast-compare,power8-compare"
-+ "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
-+
-+(define_insn_reservation "power8-mul" 4
-+ (and (eq_attr "type" "imul,imul2,imul3,lmul")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,FXU_power8")
-+
-+(define_insn_reservation "power8-mul-compare" 4
-+ (and (eq_attr "type" "imul_compare,lmul_compare")
-+ (eq_attr "cpu" "power8"))
-+ "DU_cracked_power8,FXU_power8")
-+
-+; Extra cycle to LU/LSU
-+(define_bypass 5 "power8-mul,power8-mul-compare"
-+ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
-+ power8-vecstore,power8-larx,power8-stcx")
-+
-+; 7 cycle CR latency
-+(define_bypass 7 "power8-mul,power8-mul-compare"
-+ "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
-+
-+; FXU divides are not pipelined
-+(define_insn_reservation "power8-idiv" 37
-+ (and (eq_attr "type" "idiv")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,fxu0_power8*37|fxu1_power8*37")
-+
-+(define_insn_reservation "power8-ldiv" 68
-+ (and (eq_attr "type" "ldiv")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,fxu0_power8*68|fxu1_power8*68")
-+
-+(define_insn_reservation "power8-mtjmpr" 5
-+ (and (eq_attr "type" "mtjmpr")
-+ (eq_attr "cpu" "power8"))
-+ "DU_first_power8,FXU_power8")
-+
-+; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode
-+(define_insn_reservation "power8-mtcr" 3
-+ (and (eq_attr "type" "mtcr")
-+ (eq_attr "cpu" "power8"))
-+ "DU_both_power8,FXU_power8")
-+
-+
-+; CR Unit
-+(define_insn_reservation "power8-mfjmpr" 5
-+ (and (eq_attr "type" "mfjmpr")
-+ (eq_attr "cpu" "power8"))
-+ "DU_first_power8,cru_power8+FXU_power8")
-+
-+(define_insn_reservation "power8-crlogical" 3
-+ (and (eq_attr "type" "cr_logical,delayed_cr")
-+ (eq_attr "cpu" "power8"))
-+ "DU_first_power8,cru_power8")
-+
-+(define_insn_reservation "power8-mfcr" 5
-+ (and (eq_attr "type" "mfcr")
-+ (eq_attr "cpu" "power8"))
-+ "DU_both_power8,cru_power8")
-+
-+(define_insn_reservation "power8-mfcrf" 3
-+ (and (eq_attr "type" "mfcrf")
-+ (eq_attr "cpu" "power8"))
-+ "DU_first_power8,cru_power8")
-+
-+
-+; BR Unit
-+; Branches take dispatch slot 7, but reserve any remaining prior slots to
-+; prevent other insns from grabbing them once this is assigned.
-+(define_insn_reservation "power8-branch" 3
-+ (and (eq_attr "type" "jmpreg,branch")
-+ (eq_attr "cpu" "power8"))
-+ "(du6_power8\
-+ |du5_power8+du6_power8\
-+ |du4_power8+du5_power8+du6_power8\
-+ |du3_power8+du4_power8+du5_power8+du6_power8\
-+ |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
-+ |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
-+ |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\
-+ du6_power8),bpu_power8")
-+
-+; Branch updating LR/CTR feeding mf[lr|ctr]
-+(define_bypass 4 "power8-branch" "power8-mfjmpr")
-+
-+
-+; VS Unit (includes FP/VSX/VMX/DFP/Crypto)
-+(define_insn_reservation "power8-fp" 6
-+ (and (eq_attr "type" "fp,dmul")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+; Additional 3 cycles for any CR result
-+(define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch")
-+
-+(define_insn_reservation "power8-fpcompare" 8
-+ (and (eq_attr "type" "fpcompare")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-sdiv" 27
-+ (and (eq_attr "type" "sdiv")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-ddiv" 33
-+ (and (eq_attr "type" "ddiv")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-sqrt" 32
-+ (and (eq_attr "type" "ssqrt")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-dsqrt" 44
-+ (and (eq_attr "type" "dsqrt")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-vecsimple" 2
-+ (and (eq_attr "type" "vecperm,vecsimple,veccmp")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-vecnormal" 6
-+ (and (eq_attr "type" "vecfloat,vecdouble")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_bypass 7 "power8-vecnormal"
-+ "power8-vecsimple,power8-veccomplex,power8-fpstore*,\
-+ power8-vecstore")
-+
-+(define_insn_reservation "power8-veccomplex" 7
-+ (and (eq_attr "type" "veccomplex")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-vecfdiv" 25
-+ (and (eq_attr "type" "vecfdiv")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-vecdiv" 31
-+ (and (eq_attr "type" "vecdiv")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-mffgpr" 5
-+ (and (eq_attr "type" "mffgpr")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-mftgpr" 6
-+ (and (eq_attr "type" "mftgpr")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-+(define_insn_reservation "power8-crypto" 7
-+ (and (eq_attr "type" "crypto")
-+ (eq_attr "cpu" "power8"))
-+ "DU_any_power8,VSU_power8")
-+
-Index: gcc/config/rs6000/vector.md
-===================================================================
---- a/src/gcc/config/rs6000/vector.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/vector.md (.../branches/gcc-4_8-branch)
-@@ -24,28 +24,28 @@
-
-
- ;; Vector int modes
--(define_mode_iterator VEC_I [V16QI V8HI V4SI])
-+(define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI])
-
- ;; Vector float modes
- (define_mode_iterator VEC_F [V4SF V2DF])
-
- ;; Vector arithmetic modes
--(define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF])
-+(define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF])
-
- ;; Vector modes that need alginment via permutes
- (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
-
- ;; Vector logical modes
--(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])
-+(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI])
-
- ;; Vector modes for moves. Don't do TImode here.
--(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF])
-+(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])
-
- ;; Vector modes for types that don't need a realignment under VSX
--(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF])
-+(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF V1TI])
-
- ;; Vector comparison modes
--(define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF])
-+(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF])
-
- ;; Vector init/extract modes
- (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
-@@ -54,7 +54,8 @@
- (define_mode_iterator VEC_64 [V2DI V2DF])
-
- ;; Vector reload iterator
--(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])
-+(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
-+ SF SD SI DF DD DI TI])
-
- ;; Base type from vector mode
- (define_mode_attr VEC_base [(V16QI "QI")
-@@ -63,6 +64,7 @@
- (V2DI "DI")
- (V4SF "SF")
- (V2DF "DF")
-+ (V1TI "TI")
- (TI "TI")])
-
- ;; Same size integer type for floating point data
-@@ -88,7 +90,8 @@
- (smax "smax")])
-
-
--;; Vector move instructions.
-+;; Vector move instructions. Little-endian VSX loads and stores require
-+;; special handling to circumvent "element endianness."
- (define_expand "mov<mode>"
- [(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
- (match_operand:VEC_M 1 "any_operand" ""))]
-@@ -104,6 +107,15 @@
- && !vlogical_operand (operands[1], <MODE>mode))
- operands[1] = force_reg (<MODE>mode, operands[1]);
- }
-+ if (!BYTES_BIG_ENDIAN
-+ && VECTOR_MEM_VSX_P (<MODE>mode)
-+ && !gpr_or_gpr_p (operands[0], operands[1])
-+ && (memory_operand (operands[0], <MODE>mode)
-+ ^ memory_operand (operands[1], <MODE>mode)))
-+ {
-+ rs6000_emit_le_vsx_move (operands[0], operands[1], <MODE>mode);
-+ DONE;
-+ }
- })
-
- ;; Generic vector floating point load/store instructions. These will match
-@@ -126,7 +138,9 @@
- (match_operand:VEC_L 1 "input_operand" ""))]
- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
- && reload_completed
-- && gpr_or_gpr_p (operands[0], operands[1])"
-+ && gpr_or_gpr_p (operands[0], operands[1])
-+ && !direct_move_p (operands[0], operands[1])
-+ && !quad_load_store_p (operands[0], operands[1])"
- [(pc)]
- {
- rs6000_split_multireg_move (operands[0], operands[1]);
-@@ -249,7 +263,7 @@
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
-- "VECTOR_UNIT_VSX_P (<MODE>mode) || VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
-+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- {
- if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
- {
-@@ -395,7 +409,7 @@
- (match_operand:VEC_I 5 "vint_operand" "")])
- (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
-- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
-+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
- {
- if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
-@@ -451,7 +465,7 @@
- (match_operand:VEC_I 5 "vint_operand" "")])
- (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
-- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
-+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
- {
- if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
-@@ -505,7 +519,7 @@
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
-- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
-+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "")
-
- (define_expand "vector_geu<mode>"
-@@ -512,7 +526,7 @@
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
-- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
-+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "")
-
- (define_insn_and_split "*vector_uneq<mode>"
-@@ -595,8 +609,8 @@
- (ge:VEC_F (match_dup 2)
- (match_dup 1)))
- (set (match_dup 0)
-- (not:VEC_F (ior:VEC_F (match_dup 3)
-- (match_dup 4))))]
-+ (and:VEC_F (not:VEC_F (match_dup 3))
-+ (not:VEC_F (match_dup 4))))]
- "
- {
- operands[3] = gen_reg_rtx (<MODE>mode);
-@@ -708,48 +722,19 @@
- "")
-
-
--;; Vector logical instructions
--(define_expand "xor<mode>3"
-- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
-- (xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
-- (match_operand:VEC_L 2 "vlogical_operand" "")))]
-- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
-- "")
-+;; Vector count leading zeros
-+(define_expand "clz<mode>2"
-+ [(set (match_operand:VEC_I 0 "register_operand" "")
-+ (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
-+ "TARGET_P8_VECTOR")
-
--(define_expand "ior<mode>3"
-- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
-- (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
-- (match_operand:VEC_L 2 "vlogical_operand" "")))]
-- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
-- "")
-+;; Vector population count
-+(define_expand "popcount<mode>2"
-+ [(set (match_operand:VEC_I 0 "register_operand" "")
-+ (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
-+ "TARGET_P8_VECTOR")
-
--(define_expand "and<mode>3"
-- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
-- (and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
-- (match_operand:VEC_L 2 "vlogical_operand" "")))]
-- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
-- "")
--
--(define_expand "one_cmpl<mode>2"
-- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
-- (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]
-- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
-- "")
--
--(define_expand "nor<mode>3"
-- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
-- (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
-- (match_operand:VEC_L 2 "vlogical_operand" ""))))]
-- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
-- "")
--
--(define_expand "andc<mode>3"
-- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
-- (and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" ""))
-- (match_operand:VEC_L 1 "vlogical_operand" "")))]
-- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
-- "")
--
-+
- ;; Same size conversions
- (define_expand "float<VEC_int><mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
-@@ -889,7 +874,7 @@
- {
- rtx reg = gen_reg_rtx (V4SFmode);
-
-- rs6000_expand_interleave (reg, operands[1], operands[1], true);
-+ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
- emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
- DONE;
- })
-@@ -901,7 +886,7 @@
- {
- rtx reg = gen_reg_rtx (V4SFmode);
-
-- rs6000_expand_interleave (reg, operands[1], operands[1], false);
-+ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
- emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
- DONE;
- })
-@@ -913,7 +898,7 @@
- {
- rtx reg = gen_reg_rtx (V4SImode);
-
-- rs6000_expand_interleave (reg, operands[1], operands[1], true);
-+ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
- emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
- DONE;
- })
-@@ -925,7 +910,7 @@
- {
- rtx reg = gen_reg_rtx (V4SImode);
-
-- rs6000_expand_interleave (reg, operands[1], operands[1], false);
-+ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
- emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
- DONE;
- })
-@@ -937,7 +922,7 @@
- {
- rtx reg = gen_reg_rtx (V4SImode);
-
-- rs6000_expand_interleave (reg, operands[1], operands[1], true);
-+ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
- emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
- DONE;
- })
-@@ -949,7 +934,7 @@
- {
- rtx reg = gen_reg_rtx (V4SImode);
-
-- rs6000_expand_interleave (reg, operands[1], operands[1], false);
-+ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
- emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
- DONE;
- })
-@@ -963,8 +948,19 @@
- (match_operand:V16QI 3 "vlogical_operand" "")]
- "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- {
-- emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], operands[2],
-- operands[3]));
-+ if (BYTES_BIG_ENDIAN)
-+ emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1],
-+ operands[2], operands[3]));
-+ else
-+ {
-+ /* We have changed lvsr to lvsl, so to complete the transformation
-+ of vperm for LE, we must swap the inputs. */
-+ rtx unspec = gen_rtx_UNSPEC (<MODE>mode,
-+ gen_rtvec (3, operands[2],
-+ operands[1], operands[3]),
-+ UNSPEC_VPERM);
-+ emit_move_insn (operands[0], unspec);
-+ }
- DONE;
- })
-
-@@ -1064,7 +1060,7 @@
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "")
-
- ;; Expanders for arithmetic shift left on each vector element
-@@ -1072,7 +1068,7 @@
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "")
-
- ;; Expanders for logical shift right on each vector element
-@@ -1080,7 +1076,7 @@
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "")
-
- ;; Expanders for arithmetic shift right on each vector element
-@@ -1088,7 +1084,7 @@
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "")
-
- ;; Vector reduction expanders for VSX
-Index: gcc/config/rs6000/constraints.md
-===================================================================
---- a/src/gcc/config/rs6000/constraints.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/constraints.md (.../branches/gcc-4_8-branch)
-@@ -52,22 +52,62 @@
- "@internal")
-
- ;; Use w as a prefix to add VSX modes
--;; vector double (V2DF)
-+;; any VSX register
-+(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
-+ "Any VSX register if the -mvsx option was used or NO_REGS.")
-+
- (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"
-- "@internal")
-+ "VSX vector register to hold vector double data or NO_REGS.")
-
--;; vector float (V4SF)
- (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
-- "@internal")
-+ "VSX vector register to hold vector float data or NO_REGS.")
-
--;; scalar double (DF)
-+(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
-+ "If -mmfpgpr was used, a floating point register or NO_REGS.")
-+
-+(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
-+ "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
-+
-+(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]"
-+ "VSX register if direct move instructions are enabled, or NO_REGS.")
-+
-+;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
-+;; direct move directly, and movsf can't to move between the register sets.
-+;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode
-+(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
-+
-+(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
-+ "General purpose register if 64-bit instructions are enabled or NO_REGS.")
-+
- (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
-- "@internal")
-+ "VSX vector register to hold scalar double values or NO_REGS.")
-
--;; any VSX register
--(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
-- "@internal")
-+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
-+ "VSX vector register to hold 128 bit integer or NO_REGS.")
-
-+(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]"
-+ "Altivec register to use for float/32-bit int loads/stores or NO_REGS.")
-+
-+(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
-+ "Altivec register to use for double loads/stores or NO_REGS.")
-+
-+(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
-+ "FP or VSX register to perform float operations under -mvsx or NO_REGS.")
-+
-+(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
-+ "Floating point register if the STFIWX instruction is enabled or NO_REGS.")
-+
-+(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
-+ "VSX vector register to hold scalar float values or NO_REGS.")
-+
-+(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
-+ "Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
-+
-+;; Lq/stq validates the address for load/store quad
-+(define_memory_constraint "wQ"
-+ "Memory operand suitable for the load/store quad instructions"
-+ (match_operand 0 "quad_memory_operand"))
-+
- ;; Altivec style load/store that ignores the bottom bits of the address
- (define_memory_constraint "wZ"
- "Indexed or indirect memory operand, ignoring the bottom 4 bits"
-Index: gcc/config/rs6000/predicates.md
-===================================================================
---- a/src/gcc/config/rs6000/predicates.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/predicates.md (.../branches/gcc-4_8-branch)
-@@ -124,6 +124,11 @@
- (and (match_code "const_int")
- (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
-
-+;; Return 1 if op is a unsigned 3-bit constant integer.
-+(define_predicate "u3bit_cint_operand"
-+ (and (match_code "const_int")
-+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
-+
- ;; Return 1 if op is a unsigned 5-bit constant integer.
- (define_predicate "u5bit_cint_operand"
- (and (match_code "const_int")
-@@ -135,6 +140,11 @@
- (and (match_code "const_int")
- (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
-
-+;; Return 1 if op is a unsigned 10-bit constant integer.
-+(define_predicate "u10bit_cint_operand"
-+ (and (match_code "const_int")
-+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
-+
- ;; Return 1 if op is a constant integer that can fit in a D field.
- (define_predicate "short_cint_operand"
- (and (match_code "const_int")
-@@ -161,11 +171,21 @@
- (and (match_code "const_int")
- (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
-
-+;; Match op = 0..3.
-+(define_predicate "const_0_to_3_operand"
-+ (and (match_code "const_int")
-+ (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
-+
- ;; Match op = 2 or op = 3.
- (define_predicate "const_2_to_3_operand"
- (and (match_code "const_int")
- (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
-
-+;; Match op = 0..15
-+(define_predicate "const_0_to_15_operand"
-+ (and (match_code "const_int")
-+ (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
-+
- ;; Return 1 if op is a register that is not special.
- (define_predicate "gpc_reg_operand"
- (match_operand 0 "register_operand")
-@@ -182,9 +202,95 @@
- if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))
- return 1;
-
-+ if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
-+ return 1;
-+
- return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
- })
-
-+;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
-+;; allow floating point or vector registers.
-+(define_predicate "int_reg_operand"
-+ (match_operand 0 "register_operand")
-+{
-+ if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
-+ return 0;
-+
-+ if (GET_CODE (op) == SUBREG)
-+ op = SUBREG_REG (op);
-+
-+ if (!REG_P (op))
-+ return 0;
-+
-+ if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
-+ return 1;
-+
-+ return INT_REGNO_P (REGNO (op));
-+})
-+
-+;; Like int_reg_operand, but only return true for base registers
-+(define_predicate "base_reg_operand"
-+ (match_operand 0 "int_reg_operand")
-+{
-+ if (GET_CODE (op) == SUBREG)
-+ op = SUBREG_REG (op);
-+
-+ if (!REG_P (op))
-+ return 0;
-+
-+ return (REGNO (op) != FIRST_GPR_REGNO);
-+})
-+
-+;; Return 1 if op is a HTM specific SPR register.
-+(define_predicate "htm_spr_reg_operand"
-+ (match_operand 0 "register_operand")
-+{
-+ if (!TARGET_HTM)
-+ return 0;
-+
-+ if (GET_CODE (op) == SUBREG)
-+ op = SUBREG_REG (op);
-+
-+ if (!REG_P (op))
-+ return 0;
-+
-+ switch (REGNO (op))
-+ {
-+ case TFHAR_REGNO:
-+ case TFIAR_REGNO:
-+ case TEXASR_REGNO:
-+ return 1;
-+ default:
-+ break;
-+ }
-+
-+ /* Unknown SPR. */
-+ return 0;
-+})
-+
-+;; Return 1 if op is a general purpose register that is an even register
-+;; which suitable for a load/store quad operation
-+(define_predicate "quad_int_reg_operand"
-+ (match_operand 0 "register_operand")
-+{
-+ HOST_WIDE_INT r;
-+
-+ if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
-+ return 0;
-+
-+ if (GET_CODE (op) == SUBREG)
-+ op = SUBREG_REG (op);
-+
-+ if (!REG_P (op))
-+ return 0;
-+
-+ r = REGNO (op);
-+ if (r >= FIRST_PSEUDO_REGISTER)
-+ return 1;
-+
-+ return (INT_REGNO_P (r) && ((r & 1) == 0));
-+})
-+
- ;; Return 1 if op is a register that is a condition register field.
- (define_predicate "cc_reg_operand"
- (match_operand 0 "register_operand")
-@@ -315,6 +421,11 @@
- && CONST_DOUBLE_HIGH (op) == 0")
- (match_operand 0 "gpc_reg_operand"))))
-
-+;; Like reg_or_logical_cint_operand, but allow vsx registers
-+(define_predicate "vsx_reg_or_cint_operand"
-+ (ior (match_operand 0 "vsx_register_operand")
-+ (match_operand 0 "reg_or_logical_cint_operand")))
-+
- ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
- ;; with no more than one instruction per word.
- (define_predicate "easy_fp_constant"
-@@ -333,6 +444,11 @@
- && mode != DImode)
- return 1;
-
-+ /* The constant 0.0 is easy under VSX. */
-+ if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)
-+ && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))
-+ return 1;
-+
- if (DECIMAL_FLOAT_MODE_P (mode))
- return 0;
-
-@@ -521,6 +637,55 @@
- (and (match_operand 0 "memory_operand")
- (match_test "offsettable_nonstrict_memref_p (op)")))
-
-+;; Return 1 if the operand is suitable for load/store quad memory.
-+;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
-+(define_predicate "quad_memory_operand"
-+ (match_code "mem")
-+{
-+ rtx addr, op0, op1;
-+ int ret;
-+
-+ if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
-+ ret = 0;
-+
-+ else if (!memory_operand (op, mode))
-+ ret = 0;
-+
-+ else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
-+ ret = 0;
-+
-+ else if (MEM_ALIGN (op) < 128)
-+ ret = 0;
-+
-+ else
-+ {
-+ addr = XEXP (op, 0);
-+ if (int_reg_operand (addr, Pmode))
-+ ret = 1;
-+
-+ else if (GET_CODE (addr) != PLUS)
-+ ret = 0;
-+
-+ else
-+ {
-+ op0 = XEXP (addr, 0);
-+ op1 = XEXP (addr, 1);
-+ ret = (int_reg_operand (op0, Pmode)
-+ && GET_CODE (op1) == CONST_INT
-+ && IN_RANGE (INTVAL (op1), -32768, 32767)
-+ && (INTVAL (op1) & 15) == 0);
-+ }
-+ }
-+
-+ if (TARGET_DEBUG_ADDR)
-+ {
-+ fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");
-+ debug_rtx (op);
-+ }
-+
-+ return ret;
-+})
-+
- ;; Return 1 if the operand is an indexed or indirect memory operand.
- (define_predicate "indexed_or_indirect_operand"
- (match_code "mem")
-@@ -535,6 +700,19 @@
- return indexed_or_indirect_address (op, mode);
- })
-
-+;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
-+;; moves are supported.
-+(define_predicate "reg_or_indexed_operand"
-+ (match_code "mem,reg")
-+{
-+ if (MEM_P (op))
-+ return indexed_or_indirect_operand (op, mode);
-+ else if (TARGET_DIRECT_MOVE)
-+ return register_operand (op, mode);
-+ return
-+ 0;
-+})
-+
- ;; Return 1 if the operand is an indexed or indirect memory operand with an
- ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
- ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
-@@ -560,6 +738,28 @@
- && REG_P (XEXP (op, 1)))")
- (match_operand 0 "address_operand")))
-
-+;; Return 1 if the operand is an index-form address.
-+(define_special_predicate "indexed_address"
-+ (match_test "(GET_CODE (op) == PLUS
-+ && REG_P (XEXP (op, 0))
-+ && REG_P (XEXP (op, 1)))"))
-+
-+;; Return 1 if the operand is a MEM with an update-form address. This may
-+;; also include update-indexed form.
-+(define_special_predicate "update_address_mem"
-+ (match_test "(MEM_P (op)
-+ && (GET_CODE (XEXP (op, 0)) == PRE_INC
-+ || GET_CODE (XEXP (op, 0)) == PRE_DEC
-+ || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
-+
-+;; Return 1 if the operand is a MEM with an update-indexed-form address. Note
-+;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the
-+;; increment is based on the mode size and will therefor always be a const.
-+(define_special_predicate "update_indexed_address_mem"
-+ (match_test "(MEM_P (op)
-+ && GET_CODE (XEXP (op, 0)) == PRE_MODIFY
-+ && indexed_address (XEXP (XEXP (op, 0), 1), mode))"))
-+
- ;; Used for the destination of the fix_truncdfsi2 expander.
- ;; If stfiwx will be used, the result goes to memory; otherwise,
- ;; we're going to emit a store and a load of a subreg, so the dest is a
-@@ -883,7 +1083,8 @@
- (and (match_code "symbol_ref")
- (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
- && ((SYMBOL_REF_LOCAL_P (op)
-- && (DEFAULT_ABI != ABI_AIX
-+ && ((DEFAULT_ABI != ABI_AIX
-+ && DEFAULT_ABI != ABI_ELFv2)
- || !SYMBOL_REF_EXTERNAL_P (op)))
- || (op == XEXP (DECL_RTL (current_function_decl),
- 0)))")))
-@@ -1364,6 +1565,26 @@
- return 1;
- })
-
-+;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
-+(define_predicate "crsave_operation"
-+ (match_code "parallel")
-+{
-+ int count = XVECLEN (op, 0);
-+ int i;
-+
-+ for (i = 1; i < count; i++)
-+ {
-+ rtx exp = XVECEXP (op, 0, i);
-+
-+ if (GET_CODE (exp) != USE
-+ || GET_CODE (XEXP (exp, 0)) != REG
-+ || GET_MODE (XEXP (exp, 0)) != CCmode
-+ || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
-+ return 0;
-+ }
-+ return 1;
-+})
-+
- ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
- (define_predicate "lmw_operation"
- (match_code "parallel")
-@@ -1534,3 +1755,99 @@
-
- return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
- })
-+
-+;; Match the first insn (addis) in fusing the combination of addis and loads to
-+;; GPR registers on power8.
-+(define_predicate "fusion_gpr_addis"
-+ (match_code "const_int,high,plus")
-+{
-+ HOST_WIDE_INT value;
-+ rtx int_const;
-+
-+ if (GET_CODE (op) == HIGH)
-+ return 1;
-+
-+ if (CONST_INT_P (op))
-+ int_const = op;
-+
-+ else if (GET_CODE (op) == PLUS
-+ && base_reg_operand (XEXP (op, 0), Pmode)
-+ && CONST_INT_P (XEXP (op, 1)))
-+ int_const = XEXP (op, 1);
-+
-+ else
-+ return 0;
-+
-+ /* Power8 currently will only do the fusion if the top 11 bits of the addis
-+ value are all 1's or 0's. */
-+ value = INTVAL (int_const);
-+ if ((value & (HOST_WIDE_INT)0xffff) != 0)
-+ return 0;
-+
-+ if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
-+ return 0;
-+
-+ return (IN_RANGE (value >> 16, -32, 31));
-+})
-+
-+;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
-+;; and loads to GPR registers on power8.
-+(define_predicate "fusion_gpr_mem_load"
-+ (match_code "mem,sign_extend,zero_extend")
-+{
-+ rtx addr;
-+
-+ /* Handle sign/zero extend. */
-+ if (GET_CODE (op) == ZERO_EXTEND
-+ || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
-+ {
-+ op = XEXP (op, 0);
-+ mode = GET_MODE (op);
-+ }
-+
-+ if (!MEM_P (op))
-+ return 0;
-+
-+ switch (mode)
-+ {
-+ case QImode:
-+ case HImode:
-+ case SImode:
-+ break;
-+
-+ case DImode:
-+ if (!TARGET_POWERPC64)
-+ return 0;
-+ break;
-+
-+ default:
-+ return 0;
-+ }
-+
-+ addr = XEXP (op, 0);
-+ if (GET_CODE (addr) == PLUS)
-+ {
-+ rtx base = XEXP (addr, 0);
-+ rtx offset = XEXP (addr, 1);
-+
-+ return (base_reg_operand (base, GET_MODE (base))
-+ && satisfies_constraint_I (offset));
-+ }
-+
-+ else if (GET_CODE (addr) == LO_SUM)
-+ {
-+ rtx base = XEXP (addr, 0);
-+ rtx offset = XEXP (addr, 1);
-+
-+ if (!base_reg_operand (base, GET_MODE (base)))
-+ return 0;
-+
-+ else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
-+ return small_toc_ref (offset, GET_MODE (offset));
-+
-+ else if (TARGET_ELF && !TARGET_POWERPC64)
-+ return CONSTANT_P (offset);
-+ }
-+
-+ return 0;
-+})
-Index: gcc/config/rs6000/ppc-asm.h
-===================================================================
---- a/src/gcc/config/rs6000/ppc-asm.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/ppc-asm.h (.../branches/gcc-4_8-branch)
-@@ -256,7 +256,30 @@
- * the real function with one or two leading periods respectively.
- */
-
--#if defined (__powerpc64__)
-+#if defined(__powerpc64__) && _CALL_ELF == 2
-+
-+/* Defining "toc" above breaks @toc in assembler code. */
-+#undef toc
-+
-+#define FUNC_NAME(name) GLUE(__USER_LABEL_PREFIX__,name)
-+#define JUMP_TARGET(name) FUNC_NAME(name)
-+#define FUNC_START(name) \
-+ .type FUNC_NAME(name),@function; \
-+ .globl FUNC_NAME(name); \
-+FUNC_NAME(name): \
-+0: addis 2,12,(.TOC.-0b)@ha; \
-+ addi 2,2,(.TOC.-0b)@l; \
-+ .localentry FUNC_NAME(name),.-FUNC_NAME(name)
-+
-+#define HIDDEN_FUNC(name) \
-+ FUNC_START(name) \
-+ .hidden FUNC_NAME(name);
-+
-+#define FUNC_END(name) \
-+ .size FUNC_NAME(name),.-FUNC_NAME(name)
-+
-+#elif defined (__powerpc64__)
-+
- #define FUNC_NAME(name) GLUE(.,name)
- #define JUMP_TARGET(name) FUNC_NAME(name)
- #define FUNC_START(name) \
-Index: gcc/config/rs6000/htm.md
-===================================================================
---- a/src/gcc/config/rs6000/htm.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/htm.md (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,366 @@
-+;; Hardware Transactional Memory (HTM) patterns.
-+;; Copyright (C) 2013 Free Software Foundation, Inc.
-+;; Contributed by Peter Bergner <bergner@vnet.ibm.com>.
-+
-+;; This file is part of GCC.
-+
-+;; GCC is free software; you can redistribute it and/or modify it
-+;; under the terms of the GNU General Public License as published
-+;; by the Free Software Foundation; either version 3, or (at your
-+;; option) any later version.
-+
-+;; GCC is distributed in the hope that it will be useful, but WITHOUT
-+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-+;; License for more details.
-+
-+;; You should have received a copy of the GNU General Public License
-+;; along with GCC; see the file COPYING3. If not see
-+;; <http://www.gnu.org/licenses/>.
-+
-+(define_constants
-+ [(TFHAR_SPR 128)
-+ (TFIAR_SPR 129)
-+ (TEXASR_SPR 130)
-+ (TEXASRU_SPR 131)
-+ (MAX_HTM_OPERANDS 4)
-+ ])
-+
-+;;
-+;; UNSPEC_VOLATILE usage
-+;;
-+
-+(define_c_enum "unspecv"
-+ [UNSPECV_HTM_TABORT
-+ UNSPECV_HTM_TABORTDC
-+ UNSPECV_HTM_TABORTDCI
-+ UNSPECV_HTM_TABORTWC
-+ UNSPECV_HTM_TABORTWCI
-+ UNSPECV_HTM_TBEGIN
-+ UNSPECV_HTM_TCHECK
-+ UNSPECV_HTM_TEND
-+ UNSPECV_HTM_TRECHKPT
-+ UNSPECV_HTM_TRECLAIM
-+ UNSPECV_HTM_TSR
-+ UNSPECV_HTM_MFSPR
-+ UNSPECV_HTM_MTSPR
-+ ])
-+
-+
-+(define_expand "tabort"
-+ [(set (match_dup 2)
-+ (unspec_volatile:CC [(match_operand:SI 1 "int_reg_operand" "")]
-+ UNSPECV_HTM_TABORT))
-+ (set (match_dup 3)
-+ (eq:SI (match_dup 2)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 3)))]
-+ "TARGET_HTM"
-+{
-+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[3] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*tabort_internal"
-+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand:SI 0 "int_reg_operand" "r")]
-+ UNSPECV_HTM_TABORT))]
-+ "TARGET_HTM"
-+ "tabort. %0"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "tabortdc"
-+ [(set (match_dup 4)
-+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")
-+ (match_operand:SI 2 "gpc_reg_operand" "r")
-+ (match_operand:SI 3 "gpc_reg_operand" "r")]
-+ UNSPECV_HTM_TABORTDC))
-+ (set (match_dup 5)
-+ (eq:SI (match_dup 4)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 5)))]
-+ "TARGET_HTM"
-+{
-+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[5] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*tabortdc_internal"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
-+ (match_operand:SI 1 "gpc_reg_operand" "r")
-+ (match_operand:SI 2 "gpc_reg_operand" "r")]
-+ UNSPECV_HTM_TABORTDC))]
-+ "TARGET_HTM"
-+ "tabortdc. %0,%1,%2"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "tabortdci"
-+ [(set (match_dup 4)
-+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")
-+ (match_operand:SI 2 "gpc_reg_operand" "r")
-+ (match_operand 3 "s5bit_cint_operand" "n")]
-+ UNSPECV_HTM_TABORTDCI))
-+ (set (match_dup 5)
-+ (eq:SI (match_dup 4)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 5)))]
-+ "TARGET_HTM"
-+{
-+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[5] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*tabortdci_internal"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
-+ (match_operand:SI 1 "gpc_reg_operand" "r")
-+ (match_operand 2 "s5bit_cint_operand" "n")]
-+ UNSPECV_HTM_TABORTDCI))]
-+ "TARGET_HTM"
-+ "tabortdci. %0,%1,%2"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "tabortwc"
-+ [(set (match_dup 4)
-+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")
-+ (match_operand:SI 2 "gpc_reg_operand" "r")
-+ (match_operand:SI 3 "gpc_reg_operand" "r")]
-+ UNSPECV_HTM_TABORTWC))
-+ (set (match_dup 5)
-+ (eq:SI (match_dup 4)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 5)))]
-+ "TARGET_HTM"
-+{
-+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[5] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*tabortwc_internal"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
-+ (match_operand:SI 1 "gpc_reg_operand" "r")
-+ (match_operand:SI 2 "gpc_reg_operand" "r")]
-+ UNSPECV_HTM_TABORTWC))]
-+ "TARGET_HTM"
-+ "tabortwc. %0,%1,%2"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "tabortwci"
-+ [(set (match_dup 4)
-+ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n")
-+ (match_operand:SI 2 "gpc_reg_operand" "r")
-+ (match_operand 3 "s5bit_cint_operand" "n")]
-+ UNSPECV_HTM_TABORTWCI))
-+ (set (match_dup 5)
-+ (eq:SI (match_dup 4)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 5)))]
-+ "TARGET_HTM"
-+{
-+ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[5] = gen_reg_rtx (SImode);
-+})
-+
-+(define_expand "ttest"
-+ [(set (match_dup 1)
-+ (unspec_volatile:CC [(const_int 0)
-+ (reg:SI 0)
-+ (const_int 0)]
-+ UNSPECV_HTM_TABORTWCI))
-+ (set (subreg:CC (match_dup 2) 0) (match_dup 1))
-+ (set (match_dup 3) (lshiftrt:SI (match_dup 2) (const_int 24)))
-+ (parallel [(set (match_operand:SI 0 "int_reg_operand" "")
-+ (and:SI (match_dup 3) (const_int 15)))
-+ (clobber (scratch:CC))])]
-+ "TARGET_HTM"
-+{
-+ operands[1] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[2] = gen_reg_rtx (SImode);
-+ operands[3] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*tabortwci_internal"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
-+ (match_operand:SI 1 "gpc_reg_operand" "r")
-+ (match_operand 2 "s5bit_cint_operand" "n")]
-+ UNSPECV_HTM_TABORTWCI))]
-+ "TARGET_HTM"
-+ "tabortwci. %0,%1,%2"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "tbegin"
-+ [(set (match_dup 2)
-+ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")]
-+ UNSPECV_HTM_TBEGIN))
-+ (set (match_dup 3)
-+ (eq:SI (match_dup 2)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 3)))]
-+ "TARGET_HTM"
-+{
-+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[3] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*tbegin_internal"
-+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
-+ UNSPECV_HTM_TBEGIN))]
-+ "TARGET_HTM"
-+ "tbegin. %0"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "tcheck"
-+ [(set (match_dup 2)
-+ (unspec_volatile:CC [(match_operand 1 "u3bit_cint_operand" "n")]
-+ UNSPECV_HTM_TCHECK))
-+ (set (match_dup 3)
-+ (eq:SI (match_dup 2)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 3)))]
-+ "TARGET_HTM"
-+{
-+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[3] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*tcheck_internal"
-+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand 0 "u3bit_cint_operand" "n")]
-+ UNSPECV_HTM_TCHECK))]
-+ "TARGET_HTM"
-+ "tcheck. %0"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "tend"
-+ [(set (match_dup 2)
-+ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")]
-+ UNSPECV_HTM_TEND))
-+ (set (match_dup 3)
-+ (eq:SI (match_dup 2)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 3)))]
-+ "TARGET_HTM"
-+{
-+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[3] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*tend_internal"
-+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
-+ UNSPECV_HTM_TEND))]
-+ "TARGET_HTM"
-+ "tend. %0"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "trechkpt"
-+ [(set (match_dup 1)
-+ (unspec_volatile:CC [(const_int 0)]
-+ UNSPECV_HTM_TRECHKPT))
-+ (set (match_dup 2)
-+ (eq:SI (match_dup 1)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 2)))]
-+ "TARGET_HTM"
-+{
-+ operands[1] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[2] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*trechkpt_internal"
-+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(const_int 0)]
-+ UNSPECV_HTM_TRECHKPT))]
-+ "TARGET_HTM"
-+ "trechkpt."
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "treclaim"
-+ [(set (match_dup 2)
-+ (unspec_volatile:CC [(match_operand:SI 1 "gpc_reg_operand" "r")]
-+ UNSPECV_HTM_TRECLAIM))
-+ (set (match_dup 3)
-+ (eq:SI (match_dup 2)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 3)))]
-+ "TARGET_HTM"
-+{
-+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[3] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*treclaim_internal"
-+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
-+ UNSPECV_HTM_TRECLAIM))]
-+ "TARGET_HTM"
-+ "treclaim. %0"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_expand "tsr"
-+ [(set (match_dup 2)
-+ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")]
-+ UNSPECV_HTM_TSR))
-+ (set (match_dup 3)
-+ (eq:SI (match_dup 2)
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "int_reg_operand" "")
-+ (minus:SI (const_int 1) (match_dup 3)))]
-+ "TARGET_HTM"
-+{
-+ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO);
-+ operands[3] = gen_reg_rtx (SImode);
-+})
-+
-+(define_insn "*tsr_internal"
-+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
-+ UNSPECV_HTM_TSR))]
-+ "TARGET_HTM"
-+ "tsr. %0"
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_insn "htm_mfspr_<mode>"
-+ [(set (match_operand:P 0 "gpc_reg_operand" "=r")
-+ (unspec_volatile:P [(match_operand 1 "u10bit_cint_operand" "n")
-+ (match_operand:P 2 "htm_spr_reg_operand" "")]
-+ UNSPECV_HTM_MFSPR))]
-+ "TARGET_HTM"
-+ "mfspr %0,%1";
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-+
-+(define_insn "htm_mtspr_<mode>"
-+ [(set (match_operand:P 2 "htm_spr_reg_operand" "")
-+ (unspec_volatile:P [(match_operand:P 0 "gpc_reg_operand" "r")
-+ (match_operand 1 "u10bit_cint_operand" "n")]
-+ UNSPECV_HTM_MTSPR))]
-+ "TARGET_HTM"
-+ "mtspr %1,%0";
-+ [(set_attr "type" "htm")
-+ (set_attr "length" "4")])
-Index: gcc/config/rs6000/rs6000-modes.def
-===================================================================
---- a/src/gcc/config/rs6000/rs6000-modes.def (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000-modes.def (.../branches/gcc-4_8-branch)
-@@ -38,6 +38,12 @@
- VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
- VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
- VECTOR_MODE (INT, DI, 1);
-+VECTOR_MODE (INT, TI, 1);
- VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
- VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
- VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
-+
-+/* Replacement for TImode that only is allowed in GPRs. We also use PTImode
-+ for quad memory atomic operations to force getting an even/odd register
-+ combination. */
-+PARTIAL_INT_MODE (TI);
-Index: gcc/config/rs6000/rs6000-cpus.def
-===================================================================
---- a/src/gcc/config/rs6000/rs6000-cpus.def (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000-cpus.def (.../branches/gcc-4_8-branch)
-@@ -28,7 +28,7 @@
- ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
- fre, fsqrt, etc. were no longer documented as optional. Group masks by
- server and embedded. */
--#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \
-+#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
- | OPTION_MASK_CMPB \
- | OPTION_MASK_RECIP_PRECISION \
- | OPTION_MASK_PPC_GFXOPT \
-@@ -38,6 +38,8 @@
-
- /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
- altivec is a win so enable it. */
-+ /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
-+ PR 58587 is fixed. */
- #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
- #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
- | OPTION_MASK_POPCNTD \
-@@ -44,6 +46,16 @@
- | OPTION_MASK_ALTIVEC \
- | OPTION_MASK_VSX)
-
-+/* For now, don't provide an embedded version of ISA 2.07. */
-+#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
-+ | OPTION_MASK_P8_FUSION \
-+ | OPTION_MASK_P8_VECTOR \
-+ | OPTION_MASK_CRYPTO \
-+ | OPTION_MASK_DIRECT_MOVE \
-+ | OPTION_MASK_HTM \
-+ | OPTION_MASK_QUAD_MEMORY \
-+ | OPTION_MASK_QUAD_MEMORY_ATOMIC)
-+
- #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
-
- /* Deal with ports that do not have -mstrict-align. */
-@@ -60,23 +72,30 @@
- /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
- #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
- | OPTION_MASK_CMPB \
-+ | OPTION_MASK_CRYPTO \
- | OPTION_MASK_DFP \
-+ | OPTION_MASK_DIRECT_MOVE \
- | OPTION_MASK_DLMZB \
- | OPTION_MASK_FPRND \
-+ | OPTION_MASK_HTM \
- | OPTION_MASK_ISEL \
- | OPTION_MASK_MFCRF \
- | OPTION_MASK_MFPGPR \
- | OPTION_MASK_MULHW \
- | OPTION_MASK_NO_UPDATE \
-+ | OPTION_MASK_P8_FUSION \
-+ | OPTION_MASK_P8_VECTOR \
- | OPTION_MASK_POPCNTB \
- | OPTION_MASK_POPCNTD \
- | OPTION_MASK_POWERPC64 \
- | OPTION_MASK_PPC_GFXOPT \
- | OPTION_MASK_PPC_GPOPT \
-+ | OPTION_MASK_QUAD_MEMORY \
- | OPTION_MASK_RECIP_PRECISION \
- | OPTION_MASK_SOFT_FLOAT \
- | OPTION_MASK_STRICT_ALIGN_OPTIONAL \
-- | OPTION_MASK_VSX)
-+ | OPTION_MASK_VSX \
-+ | OPTION_MASK_VSX_TIMODE)
-
- #endif
-
-@@ -166,10 +185,7 @@
- POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
- | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
- | MASK_VSX | MASK_RECIP_PRECISION)
--RS6000_CPU ("power8", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
-- POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
-- | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
-- | MASK_VSX | MASK_RECIP_PRECISION)
-+RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
- RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
- RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
- RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
-Index: gcc/config/rs6000/t-linux64bele
-===================================================================
---- a/src/gcc/config/rs6000/t-linux64bele (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/t-linux64bele (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,7 @@
-+#rs6000/t-linux64end
-+
-+MULTILIB_OPTIONS += mlittle
-+MULTILIB_DIRNAMES += le
-+MULTILIB_OSDIRNAMES += $(subst =,.mlittle=,$(subst lible32,lib32le,$(subst lible64,lib64le,$(subst lib,lible,$(subst -linux,le-linux,$(MULTILIB_OSDIRNAMES))))))
-+MULTILIB_OSDIRNAMES += $(subst $(if $(findstring 64,$(target)),m64,m32).,,$(filter $(if $(findstring 64,$(target)),m64,m32).mlittle%,$(MULTILIB_OSDIRNAMES)))
-+MULTILIB_MATCHES := ${MULTILIB_MATCHES_ENDIAN}
-Index: gcc/config/rs6000/htmintrin.h
-===================================================================
---- a/src/gcc/config/rs6000/htmintrin.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/htmintrin.h (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,131 @@
-+/* Hardware Transactional Memory (HTM) intrinsics.
-+ Copyright (C) 2013 Free Software Foundation, Inc.
-+ Contributed by Peter Bergner <bergner@vnet.ibm.com>.
-+
-+ This file is free software; you can redistribute it and/or modify it under
-+ the terms of the GNU General Public License as published by the Free
-+ Software Foundation; either version 3 of the License, or (at your option)
-+ any later version.
-+
-+ This file is distributed in the hope that it will be useful, but WITHOUT
-+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ for more details.
-+
-+ Under Section 7 of GPL version 3, you are granted additional
-+ permissions described in the GCC Runtime Library Exception, version
-+ 3.1, as published by the Free Software Foundation.
-+
-+ You should have received a copy of the GNU General Public License and
-+ a copy of the GCC Runtime Library Exception along with this program;
-+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
-+ <http://www.gnu.org/licenses/>. */
-+
-+#ifndef __HTM__
-+# error "HTM instruction set not enabled"
-+#endif /* __HTM__ */
-+
-+#ifndef _HTMINTRIN_H
-+#define _HTMINTRIN_H
-+
-+#include <stdint.h>
-+
-+typedef uint64_t texasr_t;
-+typedef uint32_t texasru_t;
-+typedef uint32_t texasrl_t;
-+typedef uintptr_t tfiar_t;
-+typedef uintptr_t tfhar_t;
-+
-+#define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3)
-+#define _HTM_NONTRANSACTIONAL 0x0
-+#define _HTM_SUSPENDED 0x1
-+#define _HTM_TRANSACTIONAL 0x2
-+
-+/* The following macros use the IBM bit numbering for BITNUM
-+ as used in the ISA documentation. */
-+
-+#define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
-+ (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1))
-+#define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
-+ (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1))
-+
-+#define _TEXASR_FAILURE_CODE(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 7, 8)
-+#define _TEXASRU_FAILURE_CODE(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8)
-+
-+#define _TEXASR_FAILURE_PERSISTENT(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 7, 1)
-+#define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1)
-+
-+#define _TEXASR_DISALLOWED(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 8, 1)
-+#define _TEXASRU_DISALLOWED(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1)
-+
-+#define _TEXASR_NESTING_OVERFLOW(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 9, 1)
-+#define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1)
-+
-+#define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 10, 1)
-+#define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1)
-+
-+#define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 11, 1)
-+#define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1)
-+
-+#define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 12, 1)
-+#define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1)
-+
-+#define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 13, 1)
-+#define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1)
-+
-+#define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 14, 1)
-+#define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1)
-+
-+#define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 15, 1)
-+#define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1)
-+
-+#define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 16, 1)
-+#define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1)
-+
-+#define _TEXASR_ABORT(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 31, 1)
-+#define _TEXASRU_ABORT(TEXASRU) \
-+ _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1)
-+
-+
-+#define _TEXASR_SUSPENDED(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 32, 1)
-+
-+#define _TEXASR_PRIVILEGE(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 35, 2)
-+
-+#define _TEXASR_FAILURE_SUMMARY(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 36, 1)
-+
-+#define _TEXASR_TFIAR_EXACT(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 37, 1)
-+
-+#define _TEXASR_ROT(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 38, 1)
-+
-+#define _TEXASR_TRANSACTION_LEVEL(TEXASR) \
-+ _TEXASR_EXTRACT_BITS(TEXASR, 63, 12)
-+
-+#endif /* _HTMINTRIN_H */
-Index: gcc/config/rs6000/rs6000-protos.h
-===================================================================
---- a/src/gcc/config/rs6000/rs6000-protos.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000-protos.h (.../branches/gcc-4_8-branch)
-@@ -50,12 +50,19 @@
- extern rtx find_addr_reg (rtx);
- extern rtx gen_easy_altivec_constant (rtx);
- extern const char *output_vec_const_move (rtx *);
-+extern const char *rs6000_output_move_128bit (rtx *);
-+extern bool rs6000_move_128bit_ok_p (rtx []);
-+extern bool rs6000_split_128bit_ok_p (rtx []);
- extern void rs6000_expand_vector_init (rtx, rtx);
- extern void paired_expand_vector_init (rtx, rtx);
- extern void rs6000_expand_vector_set (rtx, rtx, int);
- extern void rs6000_expand_vector_extract (rtx, rtx, int);
- extern bool altivec_expand_vec_perm_const (rtx op[4]);
-+extern void altivec_expand_vec_perm_le (rtx op[4]);
- extern bool rs6000_expand_vec_perm_const (rtx op[4]);
-+extern void altivec_expand_lvx_be (rtx, rtx, enum machine_mode, unsigned);
-+extern void altivec_expand_stvx_be (rtx, rtx, enum machine_mode, unsigned);
-+extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned);
- extern void rs6000_expand_extract_even (rtx, rtx, rtx);
- extern void rs6000_expand_interleave (rtx, rtx, rtx, bool);
- extern void build_mask64_2_operands (rtx, rtx *);
-@@ -70,6 +77,11 @@
- extern int registers_ok_for_quad_peep (rtx, rtx);
- extern int mems_ok_for_quad_peep (rtx, rtx);
- extern bool gpr_or_gpr_p (rtx, rtx);
-+extern bool direct_move_p (rtx, rtx);
-+extern bool quad_load_store_p (rtx, rtx);
-+extern bool fusion_gpr_load_p (rtx *, bool);
-+extern void expand_fusion_gpr_load (rtx *);
-+extern const char *emit_fusion_gpr_load (rtx *);
- extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,
- enum reg_class);
- extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
-@@ -116,6 +128,7 @@
- extern void rs6000_fatal_bad_address (rtx);
- extern rtx create_TOC_reference (rtx, rtx);
- extern void rs6000_split_multireg_move (rtx, rtx);
-+extern void rs6000_emit_le_vsx_move (rtx, rtx, enum machine_mode);
- extern void rs6000_emit_move (rtx, rtx, enum machine_mode);
- extern rtx rs6000_secondary_memory_needed_rtx (enum machine_mode);
- extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode,
-@@ -135,9 +148,11 @@
- extern rtx rs6000_address_for_altivec (rtx);
- extern rtx rs6000_allocate_stack_temp (enum machine_mode, bool, bool);
- extern int rs6000_loop_align (rtx);
-+extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool, rtx);
- #endif /* RTX_CODE */
-
- #ifdef TREE_CODE
-+extern unsigned int rs6000_data_alignment (tree, unsigned int, enum data_align);
- extern unsigned int rs6000_special_round_type_align (tree, unsigned int,
- unsigned int);
- extern unsigned int darwin_rs6000_special_round_type_align (tree, unsigned int,
-@@ -146,6 +161,7 @@
- extern rtx rs6000_libcall_value (enum machine_mode);
- extern rtx rs6000_va_arg (tree, tree);
- extern int function_ok_for_sibcall (tree);
-+extern int rs6000_reg_parm_stack_space (tree);
- extern void rs6000_elf_declare_function_name (FILE *, const char *, tree);
- extern bool rs6000_elf_in_small_data_p (const_tree);
- #ifdef ARGS_SIZE_RTX
-@@ -170,7 +186,8 @@
- extern void rs6000_emit_epilogue (int);
- extern void rs6000_emit_eh_reg_restore (rtx, rtx);
- extern const char * output_isel (rtx *);
--extern void rs6000_call_indirect_aix (rtx, rtx, rtx);
-+extern void rs6000_call_aix (rtx, rtx, rtx, rtx);
-+extern void rs6000_sibcall_aix (rtx, rtx, rtx, rtx);
- extern void rs6000_aix_asm_output_dwarf_table_ref (char *);
- extern void get_ppc476_thunk_name (char name[32]);
- extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins);
-Index: gcc/config/rs6000/t-rs6000
-===================================================================
---- a/src/gcc/config/rs6000/t-rs6000 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/t-rs6000 (.../branches/gcc-4_8-branch)
-@@ -60,6 +60,7 @@
- $(srcdir)/config/rs6000/power5.md \
- $(srcdir)/config/rs6000/power6.md \
- $(srcdir)/config/rs6000/power7.md \
-+ $(srcdir)/config/rs6000/power8.md \
- $(srcdir)/config/rs6000/cell.md \
- $(srcdir)/config/rs6000/xfpu.md \
- $(srcdir)/config/rs6000/a2.md \
-@@ -70,6 +71,8 @@
- $(srcdir)/config/rs6000/vector.md \
- $(srcdir)/config/rs6000/vsx.md \
- $(srcdir)/config/rs6000/altivec.md \
-+ $(srcdir)/config/rs6000/crypto.md \
-+ $(srcdir)/config/rs6000/htm.md \
- $(srcdir)/config/rs6000/spe.md \
- $(srcdir)/config/rs6000/dfp.md \
- $(srcdir)/config/rs6000/paired.md
-Index: gcc/config/rs6000/htmxlintrin.h
-===================================================================
---- a/src/gcc/config/rs6000/htmxlintrin.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/htmxlintrin.h (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,213 @@
-+/* XL compiler Hardware Transactional Memory (HTM) execution intrinsics.
-+ Copyright (C) 2013 Free Software Foundation, Inc.
-+ Contributed by Peter Bergner <bergner@vnet.ibm.com>.
-+
-+ This file is free software; you can redistribute it and/or modify it under
-+ the terms of the GNU General Public License as published by the Free
-+ Software Foundation; either version 3 of the License, or (at your option)
-+ any later version.
-+
-+ This file is distributed in the hope that it will be useful, but WITHOUT
-+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ for more details.
-+
-+ Under Section 7 of GPL version 3, you are granted additional
-+ permissions described in the GCC Runtime Library Exception, version
-+ 3.1, as published by the Free Software Foundation.
-+
-+ You should have received a copy of the GNU General Public License and
-+ a copy of the GCC Runtime Library Exception along with this program;
-+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
-+ <http://www.gnu.org/licenses/>. */
-+
-+#ifndef __HTM__
-+# error "HTM instruction set not enabled"
-+#endif /* __HTM__ */
-+
-+#ifndef _HTMXLINTRIN_H
-+#define _HTMXLINTRIN_H
-+
-+#include <stdint.h>
-+#include <htmintrin.h>
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#define _TEXASR_PTR(TM_BUF) \
-+ ((texasr_t *)((TM_BUF)+0))
-+#define _TEXASRU_PTR(TM_BUF) \
-+ ((texasru_t *)((TM_BUF)+0))
-+#define _TEXASRL_PTR(TM_BUF) \
-+ ((texasrl_t *)((TM_BUF)+4))
-+#define _TFIAR_PTR(TM_BUF) \
-+ ((tfiar_t *)((TM_BUF)+8))
-+
-+typedef char TM_buff_type[16];
-+
-+/* Compatibility macro with s390. This macro can be used to determine
-+ whether a transaction was successfully started from the __TM_begin()
-+ and __TM_simple_begin() intrinsic functions below. */
-+#define _HTM_TBEGIN_STARTED 1
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_simple_begin (void)
-+{
-+ if (__builtin_expect (__builtin_tbegin (0), 1))
-+ return _HTM_TBEGIN_STARTED;
-+ return 0;
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_begin (void* const TM_buff)
-+{
-+ *_TEXASRL_PTR (TM_buff) = 0;
-+ if (__builtin_expect (__builtin_tbegin (0), 1))
-+ return _HTM_TBEGIN_STARTED;
-+#ifdef __powerpc64__
-+ *_TEXASR_PTR (TM_buff) = __builtin_get_texasr ();
-+#else
-+ *_TEXASRU_PTR (TM_buff) = __builtin_get_texasru ();
-+ *_TEXASRL_PTR (TM_buff) = __builtin_get_texasr ();
-+#endif
-+ *_TFIAR_PTR (TM_buff) = __builtin_get_tfiar ();
-+ return 0;
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_end (void)
-+{
-+ if (__builtin_expect (__builtin_tend (0), 1))
-+ return 1;
-+ return 0;
-+}
-+
-+extern __inline void
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_abort (void)
-+{
-+ __builtin_tabort (0);
-+}
-+
-+extern __inline void
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_named_abort (unsigned char const code)
-+{
-+ __builtin_tabort (code);
-+}
-+
-+extern __inline void
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_resume (void)
-+{
-+ __builtin_tresume ();
-+}
-+
-+extern __inline void
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_suspend (void)
-+{
-+ __builtin_tsuspend ();
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_is_user_abort (void* const TM_buff)
-+{
-+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);
-+ return _TEXASRU_ABORT (texasru);
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_is_named_user_abort (void* const TM_buff, unsigned char *code)
-+{
-+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);
-+
-+ *code = _TEXASRU_FAILURE_CODE (texasru);
-+ return _TEXASRU_ABORT (texasru);
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_is_illegal (void* const TM_buff)
-+{
-+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);
-+ return _TEXASRU_DISALLOWED (texasru);
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_is_footprint_exceeded (void* const TM_buff)
-+{
-+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);
-+ return _TEXASRU_FOOTPRINT_OVERFLOW (texasru);
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_nesting_depth (void* const TM_buff)
-+{
-+ texasrl_t texasrl;
-+
-+ if (_HTM_STATE (__builtin_ttest ()) == _HTM_NONTRANSACTIONAL)
-+ {
-+ texasrl = *_TEXASRL_PTR (TM_buff);
-+ if (!_TEXASR_FAILURE_SUMMARY (texasrl))
-+ texasrl = 0;
-+ }
-+ else
-+ texasrl = (texasrl_t) __builtin_get_texasr ();
-+
-+ return _TEXASR_TRANSACTION_LEVEL (texasrl);
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_is_nested_too_deep(void* const TM_buff)
-+{
-+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);
-+ return _TEXASRU_NESTING_OVERFLOW (texasru);
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_is_conflict(void* const TM_buff)
-+{
-+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);
-+ /* Return TEXASR bits 11 (Self-Induced Conflict) through
-+ 14 (Translation Invalidation Conflict). */
-+ return (_TEXASRU_EXTRACT_BITS (texasru, 14, 4)) ? 1 : 0;
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_is_failure_persistent(void* const TM_buff)
-+{
-+ texasru_t texasru = *_TEXASRU_PTR (TM_buff);
-+ return _TEXASRU_FAILURE_PERSISTENT (texasru);
-+}
-+
-+extern __inline long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_failure_address(void* const TM_buff)
-+{
-+ return *_TFIAR_PTR (TM_buff);
-+}
-+
-+extern __inline long long
-+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-+__TM_failure_code(void* const TM_buff)
-+{
-+ return *_TEXASR_PTR (TM_buff);
-+}
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _HTMXLINTRIN_H */
-Index: gcc/config/rs6000/rs6000-builtin.def
-===================================================================
---- a/src/gcc/config/rs6000/rs6000-builtin.def (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000-builtin.def (.../branches/gcc-4_8-branch)
-@@ -30,7 +30,8 @@
- RS6000_BUILTIN_A -- ABS builtins
- RS6000_BUILTIN_D -- DST builtins
- RS6000_BUILTIN_E -- SPE EVSEL builtins.
-- RS6000_BUILTIN_P -- Altivec and VSX predicate builtins
-+ RS6000_BUILTIN_H -- HTM builtins
-+ RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins
- RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins
- RS6000_BUILTIN_S -- SPE predicate builtins
- RS6000_BUILTIN_X -- special builtins
-@@ -66,6 +67,10 @@
- #error "RS6000_BUILTIN_E is not defined."
- #endif
-
-+#ifndef RS6000_BUILTIN_H
-+ #error "RS6000_BUILTIN_H is not defined."
-+#endif
-+
- #ifndef RS6000_BUILTIN_P
- #error "RS6000_BUILTIN_P is not defined."
- #endif
-@@ -301,6 +306,174 @@
- | RS6000_BTC_SPECIAL), \
- CODE_FOR_nothing) /* ICODE */
-
-+/* ISA 2.07 (power8) vector convenience macros. */
-+/* For the instructions that are encoded as altivec instructions use
-+ __builtin_altivec_ as the builtin name. */
-+#define BU_P8V_AV_1(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_altivec_" NAME, /* NAME */ \
-+ RS6000_BTM_P8_VECTOR, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_UNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_P8V_AV_2(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_2 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_altivec_" NAME, /* NAME */ \
-+ RS6000_BTM_P8_VECTOR, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_BINARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_P8V_AV_3(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_3 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_altivec_" NAME, /* NAME */ \
-+ RS6000_BTM_P8_VECTOR, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_TERNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_altivec_" NAME, /* NAME */ \
-+ RS6000_BTM_P8_VECTOR, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_PREDICATE), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+/* For the instructions encoded as VSX instructions use __builtin_vsx as the
-+ builtin name. */
-+#define BU_P8V_VSX_1(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_vsx_" NAME, /* NAME */ \
-+ RS6000_BTM_P8_VECTOR, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_UNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_P8V_OVERLOAD_1(ENUM, NAME) \
-+ RS6000_BUILTIN_1 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \
-+ "__builtin_vec_" NAME, /* NAME */ \
-+ RS6000_BTM_P8_VECTOR, /* MASK */ \
-+ (RS6000_BTC_OVERLOADED /* ATTR */ \
-+ | RS6000_BTC_UNARY), \
-+ CODE_FOR_nothing) /* ICODE */
-+
-+#define BU_P8V_OVERLOAD_2(ENUM, NAME) \
-+ RS6000_BUILTIN_2 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \
-+ "__builtin_vec_" NAME, /* NAME */ \
-+ RS6000_BTM_P8_VECTOR, /* MASK */ \
-+ (RS6000_BTC_OVERLOADED /* ATTR */ \
-+ | RS6000_BTC_BINARY), \
-+ CODE_FOR_nothing) /* ICODE */
-+
-+#define BU_P8V_OVERLOAD_3(ENUM, NAME) \
-+ RS6000_BUILTIN_3 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \
-+ "__builtin_vec_" NAME, /* NAME */ \
-+ RS6000_BTM_P8_VECTOR, /* MASK */ \
-+ (RS6000_BTC_OVERLOADED /* ATTR */ \
-+ | RS6000_BTC_TERNARY), \
-+ CODE_FOR_nothing) /* ICODE */
-+
-+/* Crypto convenience macros. */
-+#define BU_CRYPTO_1(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_crypto_" NAME, /* NAME */ \
-+ RS6000_BTM_CRYPTO, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_UNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_CRYPTO_2(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_crypto_" NAME, /* NAME */ \
-+ RS6000_BTM_CRYPTO, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_BINARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_CRYPTO_3(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_crypto_" NAME, /* NAME */ \
-+ RS6000_BTM_CRYPTO, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_TERNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_CRYPTO_OVERLOAD_1(ENUM, NAME) \
-+ RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_crypto_" NAME, /* NAME */ \
-+ RS6000_BTM_CRYPTO, /* MASK */ \
-+ (RS6000_BTC_OVERLOADED /* ATTR */ \
-+ | RS6000_BTC_UNARY), \
-+ CODE_FOR_nothing) /* ICODE */
-+
-+#define BU_CRYPTO_OVERLOAD_2(ENUM, NAME) \
-+ RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_crypto_" NAME, /* NAME */ \
-+ RS6000_BTM_CRYPTO, /* MASK */ \
-+ (RS6000_BTC_OVERLOADED /* ATTR */ \
-+ | RS6000_BTC_BINARY), \
-+ CODE_FOR_nothing) /* ICODE */
-+
-+#define BU_CRYPTO_OVERLOAD_3(ENUM, NAME) \
-+ RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_crypto_" NAME, /* NAME */ \
-+ RS6000_BTM_CRYPTO, /* MASK */ \
-+ (RS6000_BTC_OVERLOADED /* ATTR */ \
-+ | RS6000_BTC_TERNARY), \
-+ CODE_FOR_nothing) /* ICODE */
-+
-+/* HTM convenience macros. */
-+#define BU_HTM_0(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_HTM, /* MASK */ \
-+ RS6000_BTC_ ## ATTR, /* ATTR */ \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_HTM_1(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_HTM, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_UNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_HTM_2(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_HTM, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_BINARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_HTM_3(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_HTM, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_TERNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_HTM_SPR0(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_HTM, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_SPR), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_HTM_SPR1(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_HTM, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_UNARY \
-+ | RS6000_BTC_SPR \
-+ | RS6000_BTC_VOID), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
- /* SPE convenience macros. */
- #define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
-@@ -397,6 +570,75 @@
- MASK, /* MASK */ \
- (ATTR | RS6000_BTC_SPECIAL), /* ATTR */ \
- CODE_FOR_nothing) /* ICODE */
-+
-+
-+/* Decimal floating point builtins for instructions. */
-+#define BU_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_DFP, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_UNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_DFP, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_BINARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+
-+/* Miscellaneous builtins for instructions added in ISA 2.06. These
-+ instructions don't require either the DFP or VSX options, just the basic ISA
-+ 2.06 (popcntd) enablement since they operate on general purpose
-+ registers. */
-+#define BU_P7_MISC_1(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_POPCNTD, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_UNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_P7_MISC_2(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_POPCNTD, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_BINARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+
-+/* Miscellaneous builtins for instructions added in ISA 2.07. These
-+ instructions do require the ISA 2.07 vector support, but they aren't vector
-+ instructions. */
-+#define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_P8_VECTOR, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_TERNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+/* Miscellaneous builtins. */
-+#define BU_MISC_1(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_HARD_FLOAT, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_UNARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
-+#define BU_MISC_2(ENUM, NAME, ATTR, ICODE) \
-+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
-+ "__builtin_" NAME, /* NAME */ \
-+ RS6000_BTM_HARD_FLOAT, /* MASK */ \
-+ (RS6000_BTC_ ## ATTR /* ATTR */ \
-+ | RS6000_BTC_BINARY), \
-+ CODE_FOR_ ## ICODE) /* ICODE */
-+
- #endif
-
- /* Insure 0 is not a legitimate index. */
-@@ -414,6 +656,7 @@
- BU_ALTIVEC_3 (VMSUMUHS, "vmsumuhs", SAT, altivec_vmsumuhs)
- BU_ALTIVEC_3 (VMSUMSHS, "vmsumshs", SAT, altivec_vmsumshs)
- BU_ALTIVEC_3 (VNMSUBFP, "vnmsubfp", FP, nfmsv4sf4)
-+BU_ALTIVEC_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti)
- BU_ALTIVEC_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df)
- BU_ALTIVEC_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di)
- BU_ALTIVEC_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf)
-@@ -420,6 +663,7 @@
- BU_ALTIVEC_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si)
- BU_ALTIVEC_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi)
- BU_ALTIVEC_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi_uns)
-+BU_ALTIVEC_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns)
- BU_ALTIVEC_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns)
- BU_ALTIVEC_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns)
- BU_ALTIVEC_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns)
-@@ -430,10 +674,12 @@
- BU_ALTIVEC_3 (VSEL_16QI, "vsel_16qi", CONST, vector_select_v16qi)
- BU_ALTIVEC_3 (VSEL_2DF, "vsel_2df", CONST, vector_select_v2df)
- BU_ALTIVEC_3 (VSEL_2DI, "vsel_2di", CONST, vector_select_v2di)
-+BU_ALTIVEC_3 (VSEL_1TI, "vsel_1ti", CONST, vector_select_v1ti)
- BU_ALTIVEC_3 (VSEL_4SI_UNS, "vsel_4si_uns", CONST, vector_select_v4si_uns)
- BU_ALTIVEC_3 (VSEL_8HI_UNS, "vsel_8hi_uns", CONST, vector_select_v8hi_uns)
- BU_ALTIVEC_3 (VSEL_16QI_UNS, "vsel_16qi_uns", CONST, vector_select_v16qi_uns)
- BU_ALTIVEC_3 (VSEL_2DI_UNS, "vsel_2di_uns", CONST, vector_select_v2di_uns)
-+BU_ALTIVEC_3 (VSEL_1TI_UNS, "vsel_1ti_uns", CONST, vector_select_v1ti_uns)
- BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi)
- BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi)
- BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si)
-@@ -626,6 +872,8 @@
- BU_ALTIVEC_X (LD_INTERNAL_2df, "ld_internal_2df", MEM)
- BU_ALTIVEC_X (ST_INTERNAL_2di, "st_internal_2di", MEM)
- BU_ALTIVEC_X (LD_INTERNAL_2di, "ld_internal_2di", MEM)
-+BU_ALTIVEC_X (ST_INTERNAL_1ti, "st_internal_1ti", MEM)
-+BU_ALTIVEC_X (LD_INTERNAL_1ti, "ld_internal_1ti", MEM)
- BU_ALTIVEC_X (MTVSCR, "mtvscr", MISC)
- BU_ALTIVEC_X (MFVSCR, "mfvscr", MISC)
- BU_ALTIVEC_X (DSSALL, "dssall", MISC)
-@@ -636,8 +884,26 @@
- BU_ALTIVEC_X (LVEHX, "lvehx", MEM)
- BU_ALTIVEC_X (LVEWX, "lvewx", MEM)
- BU_ALTIVEC_X (LVXL, "lvxl", MEM)
-+BU_ALTIVEC_X (LVXL_V2DF, "lvxl_v2df", MEM)
-+BU_ALTIVEC_X (LVXL_V2DI, "lvxl_v2di", MEM)
-+BU_ALTIVEC_X (LVXL_V4SF, "lvxl_v4sf", MEM)
-+BU_ALTIVEC_X (LVXL_V4SI, "lvxl_v4si", MEM)
-+BU_ALTIVEC_X (LVXL_V8HI, "lvxl_v8hi", MEM)
-+BU_ALTIVEC_X (LVXL_V16QI, "lvxl_v16qi", MEM)
- BU_ALTIVEC_X (LVX, "lvx", MEM)
-+BU_ALTIVEC_X (LVX_V2DF, "lvx_v2df", MEM)
-+BU_ALTIVEC_X (LVX_V2DI, "lvx_v2di", MEM)
-+BU_ALTIVEC_X (LVX_V4SF, "lvx_v4sf", MEM)
-+BU_ALTIVEC_X (LVX_V4SI, "lvx_v4si", MEM)
-+BU_ALTIVEC_X (LVX_V8HI, "lvx_v8hi", MEM)
-+BU_ALTIVEC_X (LVX_V16QI, "lvx_v16qi", MEM)
- BU_ALTIVEC_X (STVX, "stvx", MEM)
-+BU_ALTIVEC_X (STVX_V2DF, "stvx_v2df", MEM)
-+BU_ALTIVEC_X (STVX_V2DI, "stvx_v2di", MEM)
-+BU_ALTIVEC_X (STVX_V4SF, "stvx_v4sf", MEM)
-+BU_ALTIVEC_X (STVX_V4SI, "stvx_v4si", MEM)
-+BU_ALTIVEC_X (STVX_V8HI, "stvx_v8hi", MEM)
-+BU_ALTIVEC_X (STVX_V16QI, "stvx_v16qi", MEM)
- BU_ALTIVEC_C (LVLX, "lvlx", MEM)
- BU_ALTIVEC_C (LVLXL, "lvlxl", MEM)
- BU_ALTIVEC_C (LVRX, "lvrx", MEM)
-@@ -646,6 +912,12 @@
- BU_ALTIVEC_X (STVEHX, "stvehx", MEM)
- BU_ALTIVEC_X (STVEWX, "stvewx", MEM)
- BU_ALTIVEC_X (STVXL, "stvxl", MEM)
-+BU_ALTIVEC_X (STVXL_V2DF, "stvxl_v2df", MEM)
-+BU_ALTIVEC_X (STVXL_V2DI, "stvxl_v2di", MEM)
-+BU_ALTIVEC_X (STVXL_V4SF, "stvxl_v4sf", MEM)
-+BU_ALTIVEC_X (STVXL_V4SI, "stvxl_v4si", MEM)
-+BU_ALTIVEC_X (STVXL_V8HI, "stvxl_v8hi", MEM)
-+BU_ALTIVEC_X (STVXL_V16QI, "stvxl_v16qi", MEM)
- BU_ALTIVEC_C (STVLX, "stvlx", MEM)
- BU_ALTIVEC_C (STVLXL, "stvlxl", MEM)
- BU_ALTIVEC_C (STVRX, "stvrx", MEM)
-@@ -904,6 +1176,7 @@
- BU_VSX_3 (XVNMADDDP, "xvnmadddp", CONST, nfmav2df4)
- BU_VSX_3 (XVNMSUBDP, "xvnmsubdp", CONST, nfmsv2df4)
-
-+BU_VSX_3 (XXSEL_1TI, "xxsel_1ti", CONST, vector_select_v1ti)
- BU_VSX_3 (XXSEL_2DI, "xxsel_2di", CONST, vector_select_v2di)
- BU_VSX_3 (XXSEL_2DF, "xxsel_2df", CONST, vector_select_v2df)
- BU_VSX_3 (XXSEL_4SF, "xxsel_4sf", CONST, vector_select_v4sf)
-@@ -910,11 +1183,13 @@
- BU_VSX_3 (XXSEL_4SI, "xxsel_4si", CONST, vector_select_v4si)
- BU_VSX_3 (XXSEL_8HI, "xxsel_8hi", CONST, vector_select_v8hi)
- BU_VSX_3 (XXSEL_16QI, "xxsel_16qi", CONST, vector_select_v16qi)
-+BU_VSX_3 (XXSEL_1TI_UNS, "xxsel_1ti_uns", CONST, vector_select_v1ti_uns)
- BU_VSX_3 (XXSEL_2DI_UNS, "xxsel_2di_uns", CONST, vector_select_v2di_uns)
- BU_VSX_3 (XXSEL_4SI_UNS, "xxsel_4si_uns", CONST, vector_select_v4si_uns)
- BU_VSX_3 (XXSEL_8HI_UNS, "xxsel_8hi_uns", CONST, vector_select_v8hi_uns)
- BU_VSX_3 (XXSEL_16QI_UNS, "xxsel_16qi_uns", CONST, vector_select_v16qi_uns)
-
-+BU_VSX_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti)
- BU_VSX_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di)
- BU_VSX_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df)
- BU_VSX_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf)
-@@ -921,11 +1196,13 @@
- BU_VSX_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si)
- BU_VSX_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi)
- BU_VSX_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi)
-+BU_VSX_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns)
- BU_VSX_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns)
- BU_VSX_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns)
- BU_VSX_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns)
- BU_VSX_3 (VPERM_16QI_UNS, "vperm_16qi_uns", CONST, altivec_vperm_v16qi_uns)
-
-+BU_VSX_3 (XXPERMDI_1TI, "xxpermdi_1ti", CONST, vsx_xxpermdi_v1ti)
- BU_VSX_3 (XXPERMDI_2DF, "xxpermdi_2df", CONST, vsx_xxpermdi_v2df)
- BU_VSX_3 (XXPERMDI_2DI, "xxpermdi_2di", CONST, vsx_xxpermdi_v2di)
- BU_VSX_3 (XXPERMDI_4SF, "xxpermdi_4sf", CONST, vsx_xxpermdi_v4sf)
-@@ -932,6 +1209,7 @@
- BU_VSX_3 (XXPERMDI_4SI, "xxpermdi_4si", CONST, vsx_xxpermdi_v4si)
- BU_VSX_3 (XXPERMDI_8HI, "xxpermdi_8hi", CONST, vsx_xxpermdi_v8hi)
- BU_VSX_3 (XXPERMDI_16QI, "xxpermdi_16qi", CONST, vsx_xxpermdi_v16qi)
-+BU_VSX_3 (SET_1TI, "set_1ti", CONST, vsx_set_v1ti)
- BU_VSX_3 (SET_2DF, "set_2df", CONST, vsx_set_v2df)
- BU_VSX_3 (SET_2DI, "set_2di", CONST, vsx_set_v2di)
- BU_VSX_3 (XXSLDWI_2DI, "xxsldwi_2di", CONST, vsx_xxsldwi_v2di)
-@@ -1012,7 +1290,7 @@
- BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2)
-
- BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp)
--BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvdpsp)
-+BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvspdp)
- BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp)
- BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp)
- BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe)
-@@ -1052,9 +1330,9 @@
-
- BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi)
- BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic)
--BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, vsx_floordf2)
--BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, vsx_ceildf2)
--BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, vsx_btruncdf2)
-+BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, floordf2)
-+BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, ceildf2)
-+BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, btruncdf2)
-
- /* VSX predicate functions. */
- BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p)
-@@ -1066,6 +1344,7 @@
-
- /* VSX builtins that are handled as special cases. */
- BU_VSX_X (LXSDX, "lxsdx", MEM)
-+BU_VSX_X (LXVD2X_V1TI, "lxvd2x_v1ti", MEM)
- BU_VSX_X (LXVD2X_V2DF, "lxvd2x_v2df", MEM)
- BU_VSX_X (LXVD2X_V2DI, "lxvd2x_v2di", MEM)
- BU_VSX_X (LXVDSX, "lxvdsx", MEM)
-@@ -1074,6 +1353,7 @@
- BU_VSX_X (LXVW4X_V8HI, "lxvw4x_v8hi", MEM)
- BU_VSX_X (LXVW4X_V16QI, "lxvw4x_v16qi", MEM)
- BU_VSX_X (STXSDX, "stxsdx", MEM)
-+BU_VSX_X (STXVD2X_V1TI, "stxsdx_v1ti", MEM)
- BU_VSX_X (STXVD2X_V2DF, "stxsdx_v2df", MEM)
- BU_VSX_X (STXVD2X_V2DI, "stxsdx_v2di", MEM)
- BU_VSX_X (STXVW4X_V4SF, "stxsdx_v4sf", MEM)
-@@ -1104,10 +1384,13 @@
- BU_VSX_X (XSNMSUBADP, "xsnmsubadp", FP)
- BU_VSX_X (XSNMSUBMDP, "xsnmsubmdp", FP)
- BU_VSX_X (XSSUBDP, "xssubdp", FP)
-+BU_VSX_X (VEC_INIT_V1TI, "vec_init_v1ti", CONST)
- BU_VSX_X (VEC_INIT_V2DF, "vec_init_v2df", CONST)
- BU_VSX_X (VEC_INIT_V2DI, "vec_init_v2di", CONST)
-+BU_VSX_X (VEC_SET_V1TI, "vec_set_v1ti", CONST)
- BU_VSX_X (VEC_SET_V2DF, "vec_set_v2df", CONST)
- BU_VSX_X (VEC_SET_V2DI, "vec_set_v2di", CONST)
-+BU_VSX_X (VEC_EXT_V1TI, "vec_ext_v1ti", CONST)
- BU_VSX_X (VEC_EXT_V2DF, "vec_ext_v2df", CONST)
- BU_VSX_X (VEC_EXT_V2DI, "vec_ext_v2di", CONST)
-
-@@ -1132,6 +1415,249 @@
- BU_VSX_OVERLOAD_X (LD, "ld")
- BU_VSX_OVERLOAD_X (ST, "st")
-
-+/* 1 argument VSX instructions added in ISA 2.07. */
-+BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn)
-+BU_P8V_VSX_1 (XSCVDPSPN, "xscvdpspn", CONST, vsx_xscvdpspn)
-+
-+/* 1 argument altivec instructions added in ISA 2.07. */
-+BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2)
-+BU_P8V_AV_1 (VUPKHSW, "vupkhsw", CONST, altivec_vupkhsw)
-+BU_P8V_AV_1 (VUPKLSW, "vupklsw", CONST, altivec_vupklsw)
-+BU_P8V_AV_1 (VCLZB, "vclzb", CONST, clzv16qi2)
-+BU_P8V_AV_1 (VCLZH, "vclzh", CONST, clzv8hi2)
-+BU_P8V_AV_1 (VCLZW, "vclzw", CONST, clzv4si2)
-+BU_P8V_AV_1 (VCLZD, "vclzd", CONST, clzv2di2)
-+BU_P8V_AV_1 (VPOPCNTB, "vpopcntb", CONST, popcountv16qi2)
-+BU_P8V_AV_1 (VPOPCNTH, "vpopcnth", CONST, popcountv8hi2)
-+BU_P8V_AV_1 (VPOPCNTW, "vpopcntw", CONST, popcountv4si2)
-+BU_P8V_AV_1 (VPOPCNTD, "vpopcntd", CONST, popcountv2di2)
-+BU_P8V_AV_1 (VGBBD, "vgbbd", CONST, p8v_vgbbd)
-+
-+/* 2 argument altivec instructions added in ISA 2.07. */
-+BU_P8V_AV_2 (VADDCUQ, "vaddcuq", CONST, altivec_vaddcuq)
-+BU_P8V_AV_2 (VADDUDM, "vaddudm", CONST, addv2di3)
-+BU_P8V_AV_2 (VADDUQM, "vadduqm", CONST, altivec_vadduqm)
-+BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3)
-+BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3)
-+BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3)
-+BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3)
-+BU_P8V_AV_2 (VMRGEW, "vmrgew", CONST, p8_vmrgew)
-+BU_P8V_AV_2 (VMRGOW, "vmrgow", CONST, p8_vmrgow)
-+BU_P8V_AV_2 (VBPERMQ, "vbpermq", CONST, altivec_vbpermq)
-+BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum)
-+BU_P8V_AV_2 (VPKSDSS, "vpksdss", CONST, altivec_vpksdss)
-+BU_P8V_AV_2 (VPKUDUS, "vpkudus", CONST, altivec_vpkudus)
-+BU_P8V_AV_2 (VPKSDUS, "vpksdus", CONST, altivec_vpksdus)
-+BU_P8V_AV_2 (VRLD, "vrld", CONST, vrotlv2di3)
-+BU_P8V_AV_2 (VSLD, "vsld", CONST, vashlv2di3)
-+BU_P8V_AV_2 (VSRD, "vsrd", CONST, vlshrv2di3)
-+BU_P8V_AV_2 (VSRAD, "vsrad", CONST, vashrv2di3)
-+BU_P8V_AV_2 (VSUBCUQ, "vsubcuq", CONST, altivec_vsubcuq)
-+BU_P8V_AV_2 (VSUBUDM, "vsubudm", CONST, subv2di3)
-+BU_P8V_AV_2 (VSUBUQM, "vsubuqm", CONST, altivec_vsubuqm)
-+
-+BU_P8V_AV_2 (EQV_V16QI, "eqv_v16qi", CONST, eqvv16qi3)
-+BU_P8V_AV_2 (EQV_V8HI, "eqv_v8hi", CONST, eqvv8hi3)
-+BU_P8V_AV_2 (EQV_V4SI, "eqv_v4si", CONST, eqvv4si3)
-+BU_P8V_AV_2 (EQV_V2DI, "eqv_v2di", CONST, eqvv2di3)
-+BU_P8V_AV_2 (EQV_V1TI, "eqv_v1ti", CONST, eqvv1ti3)
-+BU_P8V_AV_2 (EQV_V4SF, "eqv_v4sf", CONST, eqvv4sf3)
-+BU_P8V_AV_2 (EQV_V2DF, "eqv_v2df", CONST, eqvv2df3)
-+
-+BU_P8V_AV_2 (NAND_V16QI, "nand_v16qi", CONST, nandv16qi3)
-+BU_P8V_AV_2 (NAND_V8HI, "nand_v8hi", CONST, nandv8hi3)
-+BU_P8V_AV_2 (NAND_V4SI, "nand_v4si", CONST, nandv4si3)
-+BU_P8V_AV_2 (NAND_V2DI, "nand_v2di", CONST, nandv2di3)
-+BU_P8V_AV_2 (NAND_V1TI, "nand_v1ti", CONST, nandv1ti3)
-+BU_P8V_AV_2 (NAND_V4SF, "nand_v4sf", CONST, nandv4sf3)
-+BU_P8V_AV_2 (NAND_V2DF, "nand_v2df", CONST, nandv2df3)
-+
-+BU_P8V_AV_2 (ORC_V16QI, "orc_v16qi", CONST, orcv16qi3)
-+BU_P8V_AV_2 (ORC_V8HI, "orc_v8hi", CONST, orcv8hi3)
-+BU_P8V_AV_2 (ORC_V4SI, "orc_v4si", CONST, orcv4si3)
-+BU_P8V_AV_2 (ORC_V2DI, "orc_v2di", CONST, orcv2di3)
-+BU_P8V_AV_2 (ORC_V1TI, "orc_v1ti", CONST, orcv1ti3)
-+BU_P8V_AV_2 (ORC_V4SF, "orc_v4sf", CONST, orcv4sf3)
-+BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3)
-+
-+/* 3 argument altivec instructions added in ISA 2.07. */
-+BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm)
-+BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq)
-+BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm)
-+BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq)
-+
-+/* Vector comparison instructions added in ISA 2.07. */
-+BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di)
-+BU_P8V_AV_2 (VCMPGTSD, "vcmpgtsd", CONST, vector_gtv2di)
-+BU_P8V_AV_2 (VCMPGTUD, "vcmpgtud", CONST, vector_gtuv2di)
-+
-+/* Vector comparison predicate instructions added in ISA 2.07. */
-+BU_P8V_AV_P (VCMPEQUD_P, "vcmpequd_p", CONST, vector_eq_v2di_p)
-+BU_P8V_AV_P (VCMPGTSD_P, "vcmpgtsd_p", CONST, vector_gt_v2di_p)
-+BU_P8V_AV_P (VCMPGTUD_P, "vcmpgtud_p", CONST, vector_gtu_v2di_p)
-+
-+/* ISA 2.07 vector overloaded 1 argument functions. */
-+BU_P8V_OVERLOAD_1 (VUPKHSW, "vupkhsw")
-+BU_P8V_OVERLOAD_1 (VUPKLSW, "vupklsw")
-+BU_P8V_OVERLOAD_1 (VCLZ, "vclz")
-+BU_P8V_OVERLOAD_1 (VCLZB, "vclzb")
-+BU_P8V_OVERLOAD_1 (VCLZH, "vclzh")
-+BU_P8V_OVERLOAD_1 (VCLZW, "vclzw")
-+BU_P8V_OVERLOAD_1 (VCLZD, "vclzd")
-+BU_P8V_OVERLOAD_1 (VPOPCNT, "vpopcnt")
-+BU_P8V_OVERLOAD_1 (VPOPCNTB, "vpopcntb")
-+BU_P8V_OVERLOAD_1 (VPOPCNTH, "vpopcnth")
-+BU_P8V_OVERLOAD_1 (VPOPCNTW, "vpopcntw")
-+BU_P8V_OVERLOAD_1 (VPOPCNTD, "vpopcntd")
-+BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd")
-+
-+/* ISA 2.07 vector overloaded 2 argument functions. */
-+BU_P8V_OVERLOAD_2 (EQV, "eqv")
-+BU_P8V_OVERLOAD_2 (NAND, "nand")
-+BU_P8V_OVERLOAD_2 (ORC, "orc")
-+BU_P8V_OVERLOAD_2 (VADDCUQ, "vaddcuq")
-+BU_P8V_OVERLOAD_2 (VADDUDM, "vaddudm")
-+BU_P8V_OVERLOAD_2 (VADDUQM, "vadduqm")
-+BU_P8V_OVERLOAD_2 (VBPERMQ, "vbpermq")
-+BU_P8V_OVERLOAD_2 (VMAXSD, "vmaxsd")
-+BU_P8V_OVERLOAD_2 (VMAXUD, "vmaxud")
-+BU_P8V_OVERLOAD_2 (VMINSD, "vminsd")
-+BU_P8V_OVERLOAD_2 (VMINUD, "vminud")
-+BU_P8V_OVERLOAD_2 (VMRGEW, "vmrgew")
-+BU_P8V_OVERLOAD_2 (VMRGOW, "vmrgow")
-+BU_P8V_OVERLOAD_2 (VPKSDSS, "vpksdss")
-+BU_P8V_OVERLOAD_2 (VPKSDUS, "vpksdus")
-+BU_P8V_OVERLOAD_2 (VPKUDUM, "vpkudum")
-+BU_P8V_OVERLOAD_2 (VPKUDUS, "vpkudus")
-+BU_P8V_OVERLOAD_2 (VRLD, "vrld")
-+BU_P8V_OVERLOAD_2 (VSLD, "vsld")
-+BU_P8V_OVERLOAD_2 (VSRAD, "vsrad")
-+BU_P8V_OVERLOAD_2 (VSRD, "vsrd")
-+BU_P8V_OVERLOAD_2 (VSUBCUQ, "vsubcuq")
-+BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm")
-+BU_P8V_OVERLOAD_2 (VSUBUQM, "vsubuqm")
-+
-+/* ISA 2.07 vector overloaded 3 argument functions. */
-+BU_P8V_OVERLOAD_3 (VADDECUQ, "vaddecuq")
-+BU_P8V_OVERLOAD_3 (VADDEUQM, "vaddeuqm")
-+BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq")
-+BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm")
-+
-+
-+/* 2 argument extended divide functions added in ISA 2.06. */
-+BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si)
-+BU_P7_MISC_2 (DIVWEO, "divweo", CONST, diveo_si)
-+BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si)
-+BU_P7_MISC_2 (DIVWEUO, "divweuo", CONST, diveuo_si)
-+BU_P7_MISC_2 (DIVDE, "divde", CONST, dive_di)
-+BU_P7_MISC_2 (DIVDEO, "divdeo", CONST, diveo_di)
-+BU_P7_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di)
-+BU_P7_MISC_2 (DIVDEUO, "divdeuo", CONST, diveuo_di)
-+
-+/* 1 argument DFP (decimal floating point) functions added in ISA 2.05. */
-+BU_DFP_MISC_1 (DXEX, "dxex", CONST, dfp_dxex_dd)
-+BU_DFP_MISC_1 (DXEXQ, "dxexq", CONST, dfp_dxex_td)
-+
-+/* 2 argument DFP (decimal floating point) functions added in ISA 2.05. */
-+BU_DFP_MISC_2 (DDEDPD, "ddedpd", CONST, dfp_ddedpd_dd)
-+BU_DFP_MISC_2 (DDEDPDQ, "ddedpdq", CONST, dfp_ddedpd_td)
-+BU_DFP_MISC_2 (DENBCD, "denbcd", CONST, dfp_denbcd_dd)
-+BU_DFP_MISC_2 (DENBCDQ, "denbcdq", CONST, dfp_denbcd_td)
-+BU_DFP_MISC_2 (DIEX, "diex", CONST, dfp_diex_dd)
-+BU_DFP_MISC_2 (DIEXQ, "diexq", CONST, dfp_diex_td)
-+BU_DFP_MISC_2 (DSCLI, "dscli", CONST, dfp_dscli_dd)
-+BU_DFP_MISC_2 (DSCLIQ, "dscliq", CONST, dfp_dscli_td)
-+BU_DFP_MISC_2 (DSCRI, "dscri", CONST, dfp_dscri_dd)
-+BU_DFP_MISC_2 (DSCRIQ, "dscriq", CONST, dfp_dscri_td)
-+
-+/* 1 argument BCD functions added in ISA 2.06. */
-+BU_P7_MISC_1 (CDTBCD, "cdtbcd", CONST, cdtbcd)
-+BU_P7_MISC_1 (CBCDTD, "cbcdtd", CONST, cbcdtd)
-+
-+/* 2 argument BCD functions added in ISA 2.06. */
-+BU_P7_MISC_2 (ADDG6S, "addg6s", CONST, addg6s)
-+
-+/* 3 argument BCD functions added in ISA 2.07. */
-+BU_P8V_MISC_3 (BCDADD, "bcdadd", CONST, bcdadd)
-+BU_P8V_MISC_3 (BCDADD_LT, "bcdadd_lt", CONST, bcdadd_lt)
-+BU_P8V_MISC_3 (BCDADD_EQ, "bcdadd_eq", CONST, bcdadd_eq)
-+BU_P8V_MISC_3 (BCDADD_GT, "bcdadd_gt", CONST, bcdadd_gt)
-+BU_P8V_MISC_3 (BCDADD_OV, "bcdadd_ov", CONST, bcdadd_unordered)
-+BU_P8V_MISC_3 (BCDSUB, "bcdsub", CONST, bcdsub)
-+BU_P8V_MISC_3 (BCDSUB_LT, "bcdsub_lt", CONST, bcdsub_lt)
-+BU_P8V_MISC_3 (BCDSUB_EQ, "bcdsub_eq", CONST, bcdsub_eq)
-+BU_P8V_MISC_3 (BCDSUB_GT, "bcdsub_gt", CONST, bcdsub_gt)
-+BU_P8V_MISC_3 (BCDSUB_OV, "bcdsub_ov", CONST, bcdsub_unordered)
-+
-+/* 2 argument pack/unpack 128-bit floating point types. */
-+BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd)
-+BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd)
-+
-+BU_MISC_2 (PACK_TF, "pack_longdouble", CONST, packtf)
-+BU_MISC_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf)
-+BU_MISC_1 (UNPACK_TF_0, "longdouble_dw0", CONST, unpacktf_0)
-+BU_MISC_1 (UNPACK_TF_1, "longdouble_dw1", CONST, unpacktf_1)
-+
-+BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti)
-+BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti)
-+
-+
-+/* 1 argument crypto functions. */
-+BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox)
-+
-+/* 2 argument crypto functions. */
-+BU_CRYPTO_2 (VCIPHER, "vcipher", CONST, crypto_vcipher)
-+BU_CRYPTO_2 (VCIPHERLAST, "vcipherlast", CONST, crypto_vcipherlast)
-+BU_CRYPTO_2 (VNCIPHER, "vncipher", CONST, crypto_vncipher)
-+BU_CRYPTO_2 (VNCIPHERLAST, "vncipherlast", CONST, crypto_vncipherlast)
-+BU_CRYPTO_2 (VPMSUMB, "vpmsumb", CONST, crypto_vpmsumb)
-+BU_CRYPTO_2 (VPMSUMH, "vpmsumh", CONST, crypto_vpmsumh)
-+BU_CRYPTO_2 (VPMSUMW, "vpmsumw", CONST, crypto_vpmsumw)
-+BU_CRYPTO_2 (VPMSUMD, "vpmsumd", CONST, crypto_vpmsumd)
-+
-+/* 3 argument crypto functions. */
-+BU_CRYPTO_3 (VPERMXOR_V2DI, "vpermxor_v2di", CONST, crypto_vpermxor_v2di)
-+BU_CRYPTO_3 (VPERMXOR_V4SI, "vpermxor_v4si", CONST, crypto_vpermxor_v4si)
-+BU_CRYPTO_3 (VPERMXOR_V8HI, "vpermxor_v8hi", CONST, crypto_vpermxor_v8hi)
-+BU_CRYPTO_3 (VPERMXOR_V16QI, "vpermxor_v16qi", CONST, crypto_vpermxor_v16qi)
-+BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw)
-+BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad)
-+
-+/* 2 argument crypto overloaded functions. */
-+BU_CRYPTO_OVERLOAD_2 (VPMSUM, "vpmsum")
-+
-+/* 3 argument crypto overloaded functions. */
-+BU_CRYPTO_OVERLOAD_3 (VPERMXOR, "vpermxor")
-+BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma")
-+
-+
-+/* HTM functions. */
-+BU_HTM_1 (TABORT, "tabort", MISC, tabort)
-+BU_HTM_3 (TABORTDC, "tabortdc", MISC, tabortdc)
-+BU_HTM_3 (TABORTDCI, "tabortdci", MISC, tabortdci)
-+BU_HTM_3 (TABORTWC, "tabortwc", MISC, tabortwc)
-+BU_HTM_3 (TABORTWCI, "tabortwci", MISC, tabortwci)
-+BU_HTM_1 (TBEGIN, "tbegin", MISC, tbegin)
-+BU_HTM_1 (TCHECK, "tcheck", MISC, tcheck)
-+BU_HTM_1 (TEND, "tend", MISC, tend)
-+BU_HTM_0 (TENDALL, "tendall", MISC, tend)
-+BU_HTM_0 (TRECHKPT, "trechkpt", MISC, trechkpt)
-+BU_HTM_1 (TRECLAIM, "treclaim", MISC, treclaim)
-+BU_HTM_0 (TRESUME, "tresume", MISC, tsr)
-+BU_HTM_0 (TSUSPEND, "tsuspend", MISC, tsr)
-+BU_HTM_1 (TSR, "tsr", MISC, tsr)
-+BU_HTM_0 (TTEST, "ttest", MISC, ttest)
-+
-+BU_HTM_SPR0 (GET_TFHAR, "get_tfhar", MISC, nothing)
-+BU_HTM_SPR1 (SET_TFHAR, "set_tfhar", MISC, nothing)
-+BU_HTM_SPR0 (GET_TFIAR, "get_tfiar", MISC, nothing)
-+BU_HTM_SPR1 (SET_TFIAR, "set_tfiar", MISC, nothing)
-+BU_HTM_SPR0 (GET_TEXASR, "get_texasr", MISC, nothing)
-+BU_HTM_SPR1 (SET_TEXASR, "set_texasr", MISC, nothing)
-+BU_HTM_SPR0 (GET_TEXASRU, "get_texasru", MISC, nothing)
-+BU_HTM_SPR1 (SET_TEXASRU, "set_texasru", MISC, nothing)
-+
-+
- /* 3 argument paired floating point builtins. */
- BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4)
- BU_PAIRED_3 (MADD, "madd", FP, fmav2sf4)
-@@ -1430,10 +1956,10 @@
- RS6000_BTC_FP)
-
- BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase",
-- RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
-+ RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
-
- BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb",
-- RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
-+ RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
-
- /* Darwin CfString builtin. */
- BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
-Index: gcc/config/rs6000/rs6000-c.c
-===================================================================
---- a/src/gcc/config/rs6000/rs6000-c.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000-c.c (.../branches/gcc-4_8-branch)
-@@ -90,6 +90,8 @@
- static GTY(()) tree __bool_keyword;
- static GTY(()) tree bool_keyword;
- static GTY(()) tree _Bool_keyword;
-+static GTY(()) tree __int128_type;
-+static GTY(()) tree __uint128_type;
-
- /* Preserved across calls. */
- static tree expand_bool_pixel;
-@@ -122,9 +124,10 @@
- static void
- init_vector_keywords (void)
- {
-- /* Keywords without two leading underscores are context-sensitive,
-- and hence implemented as conditional macros, controlled by the
-- rs6000_macro_to_expand() function below. */
-+ /* Keywords without two leading underscores are context-sensitive, and hence
-+ implemented as conditional macros, controlled by the
-+ rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit
-+ support, record the __int128_t and __uint128_t types. */
-
- __vector_keyword = get_identifier ("__vector");
- C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
-@@ -146,6 +149,12 @@
-
- _Bool_keyword = get_identifier ("_Bool");
- C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
-+
-+ if (TARGET_VADDUQM)
-+ {
-+ __int128_type = get_identifier ("__int128_t");
-+ __uint128_type = get_identifier ("__uint128_t");
-+ }
- }
-
- /* Called to decide whether a conditional macro should be expanded.
-@@ -221,7 +230,8 @@
- || rid_code == RID_SHORT || rid_code == RID_SIGNED
- || rid_code == RID_INT || rid_code == RID_CHAR
- || rid_code == RID_FLOAT
-- || (rid_code == RID_DOUBLE && TARGET_VSX))
-+ || (rid_code == RID_DOUBLE && TARGET_VSX)
-+ || (rid_code == RID_INT128 && TARGET_VADDUQM))
- {
- expand_this = C_CPP_HASHNODE (__vector_keyword);
- /* If the next keyword is bool or pixel, it
-@@ -248,6 +258,13 @@
- expand_bool_pixel = __bool_keyword;
- }
- }
-+
-+ /* Support vector __int128_t, but we don't need to worry about bool
-+ or pixel on this type. */
-+ else if (TARGET_VADDUQM
-+ && (ident == C_CPP_HASHNODE (__int128_type)
-+ || ident == C_CPP_HASHNODE (__uint128_type)))
-+ expand_this = C_CPP_HASHNODE (__vector_keyword);
- }
- }
- else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))
-@@ -315,6 +332,8 @@
- rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
- if ((flags & OPTION_MASK_POPCNTD) != 0)
- rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-+ if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
-+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
- if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
- rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
- if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
-@@ -331,6 +350,16 @@
- }
- if ((flags & OPTION_MASK_VSX) != 0)
- rs6000_define_or_undefine_macro (define_p, "__VSX__");
-+ if ((flags & OPTION_MASK_HTM) != 0)
-+ rs6000_define_or_undefine_macro (define_p, "__HTM__");
-+ if ((flags & OPTION_MASK_P8_VECTOR) != 0)
-+ rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
-+ if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
-+ rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
-+ if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
-+ rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
-+ if ((flags & OPTION_MASK_CRYPTO) != 0)
-+ rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
-
- /* options from the builtin masks. */
- if ((bu_mask & RS6000_BTM_SPE) != 0)
-@@ -453,7 +482,11 @@
- case ABI_AIX:
- builtin_define ("_CALL_AIXDESC");
- builtin_define ("_CALL_AIX");
-+ builtin_define ("_CALL_ELF=1");
- break;
-+ case ABI_ELFv2:
-+ builtin_define ("_CALL_ELF=2");
-+ break;
- case ABI_DARWIN:
- builtin_define ("_CALL_DARWIN");
- break;
-@@ -465,6 +498,13 @@
- if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
- builtin_define ("__NO_FPRS__");
-
-+ /* Whether aggregates passed by value are aligned to a 16 byte boundary
-+ if their alignment is 16 bytes or larger. */
-+ if ((TARGET_MACHO && rs6000_darwin64_abi)
-+ || DEFAULT_ABI == ABI_ELFv2
-+ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
-+ builtin_define ("__STRUCT_PARM_ALIGN__=16");
-+
- /* Generate defines for Xilinx FPU. */
- if (rs6000_xilinx_fpu)
- {
-@@ -505,6 +545,8 @@
- RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
-+ { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
- RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
-@@ -577,6 +619,10 @@
- RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
- RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
-+ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
-+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
-+ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
-@@ -583,6 +629,10 @@
- RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
- RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
-+ { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
-+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
-+ { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
-@@ -601,6 +651,10 @@
- RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
- RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
-+ { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
-+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
-+ { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
-@@ -651,10 +705,27 @@
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
- RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
- RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, 0 },
- { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
- RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
-@@ -937,6 +1008,10 @@
- RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
- RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
- RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
-@@ -975,6 +1050,10 @@
- RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
- RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
- RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
-@@ -1021,6 +1100,10 @@
- RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
- RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
- RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
-@@ -1045,54 +1128,54 @@
- RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
- RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
- RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
- RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
- RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
- ~RS6000_BTI_unsigned_V2DI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
- RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
- RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
- RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
- RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
- RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
- RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
- RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
- RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
- RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
- RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
- RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
- RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
- RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
- RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
-+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
- { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
- RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
-@@ -1130,55 +1213,55 @@
- RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
- { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
- RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
- RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
- RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
- RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
- RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
- RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
- RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
- RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
- RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
- RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
- RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
- RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
- RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
- ~RS6000_BTI_unsigned_V16QI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
- RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
- RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
- RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
- ~RS6000_BTI_unsigned_V2DI, 0 },
-- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
-+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
- RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
-@@ -1418,6 +1501,18 @@
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
- RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
-@@ -1604,6 +1699,18 @@
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
- RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
-@@ -1786,6 +1893,12 @@
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
- RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
-+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
-+ RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
- RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
-@@ -1812,6 +1925,10 @@
- RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
-+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
- RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
-@@ -1824,6 +1941,8 @@
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
-@@ -1844,6 +1963,10 @@
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
-@@ -1868,6 +1991,10 @@
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
- RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
- { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
-@@ -2032,6 +2159,10 @@
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
-@@ -2056,6 +2187,10 @@
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
-@@ -2196,10 +2331,27 @@
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
- { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
- RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
- RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
-+ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, 0 },
- { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
- RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
- { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
-@@ -2730,63 +2882,63 @@
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
- { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
- RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
- RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
- RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
- ~RS6000_BTI_unsigned_V2DI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
- RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
- ~RS6000_BTI_bool_V2DI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
- RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
- RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
- RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
- RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
- RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
- RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
- RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
- RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
- RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
- RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
- RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
- RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
- RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
- RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
- RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
- RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
- RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
-- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
-+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
- RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
- { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
- RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
-@@ -2858,64 +3010,64 @@
- RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
- { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
- RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
- RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
- RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
- RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
- RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
- RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
- RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
- RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
- RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
- RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
- RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
- RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
- RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
- RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
- RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
- RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
- RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
- RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
- RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
- RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
- RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
- RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
- RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
- ~RS6000_BTI_unsigned_V2DI },
-- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
-+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
- RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
- ~RS6000_BTI_bool_V2DI },
- { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
-@@ -3327,6 +3479,20 @@
- RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
- { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
- RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
- { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
- RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
- { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
-@@ -3372,11 +3538,509 @@
- RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
- { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
- RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
-+ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
- { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
- RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
- { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
- RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
-
-+ /* Power8 vector overloaded functions. */
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
-+ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
-+ RS6000_BTI_unsigned_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_bool_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_unsigned_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
-+ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
-+ RS6000_BTI_unsigned_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-+ RS6000_BTI_bool_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-+ RS6000_BTI_unsigned_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
-+ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
-+ RS6000_BTI_unsigned_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_bool_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_unsigned_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
-+ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-+ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
-+ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-+
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
-+ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
-+ RS6000_BTI_unsigned_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_bool_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_unsigned_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
-+ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
-+ RS6000_BTI_unsigned_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-+ RS6000_BTI_bool_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-+ RS6000_BTI_unsigned_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
-+ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
-+ RS6000_BTI_unsigned_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_bool_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_unsigned_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
-+ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-+ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
-+ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-+
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
-+ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
-+ RS6000_BTI_unsigned_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_bool_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_unsigned_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
-+ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
-+ RS6000_BTI_unsigned_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-+ RS6000_BTI_bool_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-+ RS6000_BTI_unsigned_V8HI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
-+ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
-+ RS6000_BTI_unsigned_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_bool_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_unsigned_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
-+ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-+ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
-+ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-+
-+ { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
-+ { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
-+ { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
-+ RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
-+ { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_unsigned_V16QI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
-+ { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
-+
-+ { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
-+ { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
-+
-+ { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
-+ { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
-+
-+ { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
-+ { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
-+
-+ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_unsigned_V4SI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-+ { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_unsigned_V4SI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
-+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
-+ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
-+ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
-+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
-+ RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
-+ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
-+ { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
-+ RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
-+ { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
-+ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-+ RS6000_BTI_unsigned_V1TI, 0 },
-+
-+ { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
-+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
-+ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
-+ { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
-+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
-+
-+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-+ RS6000_BTI_V16QI, 0, 0, 0 },
-+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-+ RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
-+
-+ /* Crypto builtins. */
-+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
-+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
-+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
-+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
-+
-+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
-+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_unsigned_V16QI, 0 },
-+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
-+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-+ RS6000_BTI_unsigned_V8HI, 0 },
-+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_unsigned_V4SI, 0 },
-+ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_unsigned_V2DI, 0 },
-+
-+ { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
-+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI },
-+ { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
-+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-+ RS6000_BTI_INTSI, RS6000_BTI_INTSI },
-+
- { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
- };
-
-@@ -3560,6 +4224,10 @@
- unsigned_p = TYPE_UNSIGNED (type);
- switch (TYPE_MODE (type))
- {
-+ case TImode:
-+ type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
-+ size = 1;
-+ break;
- case DImode:
- type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
- size = 2;
-@@ -3591,7 +4259,7 @@
- return build_constructor (type, vec);
- }
-
-- /* For now use pointer tricks to do the extaction, unless we are on VSX
-+ /* For now use pointer tricks to do the extraction, unless we are on VSX
- extracting a double from a constant offset. */
- if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)
- {
-@@ -3619,6 +4287,17 @@
- if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
- goto bad;
-
-+ /* If we are targeting little-endian, but -maltivec=be has been
-+ specified to override the element order, adjust the element
-+ number accordingly. */
-+ if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
-+ {
-+ unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
-+ arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
-+ build_int_cstu (TREE_TYPE (arg2), last_elem),
-+ arg2);
-+ }
-+
- /* If we can use the VSX xxpermdi instruction, use that for extract. */
- mode = TYPE_MODE (arg1_type);
- if ((mode == V2DFmode || mode == V2DImode) && VECTOR_MEM_VSX_P (mode)
-@@ -3636,6 +4315,14 @@
- if (call)
- return build_call_expr (call, 2, arg1, arg2);
- }
-+ else if (mode == V1TImode && VECTOR_MEM_VSX_P (mode)
-+ && TREE_CODE (arg2) == INTEGER_CST
-+ && TREE_INT_CST_HIGH (arg2) == 0
-+ && TREE_INT_CST_LOW (arg2) == 0)
-+ {
-+ tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
-+ return build_call_expr (call, 2, arg1, arg2);
-+ }
-
- /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */
- arg1_inner_type = TREE_TYPE (arg1_type);
-@@ -3666,7 +4353,7 @@
- return stmt;
- }
-
-- /* For now use pointer tricks to do the insertation, unless we are on VSX
-+ /* For now use pointer tricks to do the insertion, unless we are on VSX
- inserting a double to a constant offset.. */
- if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)
- {
-@@ -3696,6 +4383,17 @@
- if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
- goto bad;
-
-+ /* If we are targeting little-endian, but -maltivec=be has been
-+ specified to override the element order, adjust the element
-+ number accordingly. */
-+ if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
-+ {
-+ unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
-+ arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
-+ build_int_cstu (TREE_TYPE (arg2), last_elem),
-+ arg2);
-+ }
-+
- /* If we can use the VSX xxpermdi instruction, use that for insert. */
- mode = TYPE_MODE (arg1_type);
- if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)
-@@ -3715,7 +4413,18 @@
- if (call)
- return build_call_expr (call, 3, arg1, arg0, arg2);
- }
-+ else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)
-+ && TREE_CODE (arg2) == INTEGER_CST
-+ && TREE_INT_CST_HIGH (arg2) == 0
-+ && TREE_INT_CST_LOW (arg2) == 0)
-+ {
-+ tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];
-
-+ /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
-+ reversed. */
-+ return build_call_expr (call, 3, arg1, arg0, arg2);
-+ }
-+
- /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */
- arg1_inner_type = TREE_TYPE (arg1_type);
- arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
-@@ -3824,7 +4533,8 @@
- && (desc->op2 == RS6000_BTI_NOT_OPAQUE
- || rs6000_builtin_type_compatible (types[1], desc->op2))
- && (desc->op3 == RS6000_BTI_NOT_OPAQUE
-- || rs6000_builtin_type_compatible (types[2], desc->op3)))
-+ || rs6000_builtin_type_compatible (types[2], desc->op3))
-+ && rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
- return altivec_build_resolved_builtin (args, n, desc);
-
- bad:
-Index: gcc/config/rs6000/rs6000.opt
-===================================================================
---- a/src/gcc/config/rs6000/rs6000.opt (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000.opt (.../branches/gcc-4_8-branch)
-@@ -1,6 +1,6 @@
- ; Options for the rs6000 port of the compiler
- ;
--; Copyright (C) 2005-2013 Free Software Foundation, Inc.
-+; Copyright (C) 2005-2014 Free Software Foundation, Inc.
- ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
- ;
- ; This file is part of GCC.
-@@ -137,6 +137,14 @@
- Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
- Use AltiVec instructions
-
-+maltivec=le
-+Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save
-+Generate Altivec instructions using little-endian element order
-+
-+maltivec=be
-+Target Report RejectNegative Var(rs6000_altivec_element_order, 2)
-+Generate Altivec instructions using big-endian element order
-+
- mhard-dfp
- Target Report Mask(DFP) Var(rs6000_isa_flags)
- Use decimal floating point instructions
-@@ -181,13 +189,16 @@
- Target Report Mask(VSX) Var(rs6000_isa_flags)
- Use vector/scalar (VSX) instructions
-
-+mvsx-scalar-float
-+Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1)
-+; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default)
-+
- mvsx-scalar-double
--Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)
--; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)
-+Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)
-+; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)
-
- mvsx-scalar-memory
--Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)
--; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)
-+Target Undocumented Report Alias(mupper-regs-df)
-
- mvsx-align-128
- Target Undocumented Report Var(TARGET_VSX_ALIGN_128)
-@@ -363,6 +374,14 @@
- Target RejectNegative Var(rs6000_spe_abi, 0)
- Do not use the SPE ABI extensions
-
-+mabi=elfv1
-+Target RejectNegative Var(rs6000_elf_abi, 1) Save
-+Use the ELFv1 ABI
-+
-+mabi=elfv2
-+Target RejectNegative Var(rs6000_elf_abi, 2)
-+Use the ELFv2 ABI
-+
- ; These are here for testing during development only, do not document
- ; in the manual please.
-
-@@ -443,6 +462,10 @@
- Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
- -mlong-double-<n> Specify size of long double (64 or 128 bits)
-
-+mlra
-+Target Report Var(rs6000_lra_flag) Init(0) Save
-+Use LRA instead of reload
-+
- msched-costly-dep=
- Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
- Determine which dependences between insns are considered costly
-@@ -514,3 +537,51 @@
- msave-toc-indirect
- Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save
- Control whether we save the TOC in the prologue for indirect calls or generate the save inline
-+
-+mvsx-timode
-+Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags)
-+Allow 128-bit integers in VSX registers
-+
-+mpower8-fusion
-+Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
-+Fuse certain integer operations together for better performance on power8
-+
-+mpower8-fusion-sign
-+Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
-+Allow sign extension in fusion operations
-+
-+mpower8-vector
-+Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
-+Use/do not use vector and scalar instructions added in ISA 2.07.
-+
-+mcrypto
-+Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
-+Use ISA 2.07 crypto instructions
-+
-+mdirect-move
-+Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)
-+Use ISA 2.07 direct move between GPR & VSX register instructions
-+
-+mhtm
-+Target Report Mask(HTM) Var(rs6000_isa_flags)
-+Use ISA 2.07 transactional memory (HTM) instructions
-+
-+mquad-memory
-+Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
-+Generate the quad word memory instructions (lq/stq).
-+
-+mquad-memory-atomic
-+Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
-+Generate the quad word memory atomic instructions (lqarx/stqcx).
-+
-+mcompat-align-parm
-+Target Report Var(rs6000_compat_align_parm) Init(1) Save
-+Generate aggregate parameter passing code with at most 64-bit alignment.
-+
-+mupper-regs-df
-+Target Undocumented Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
-+Allow double variables in upper registers with -mcpu=power7 or -mvsx
-+
-+mupper-regs-sf
-+Target Undocumented Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
-+Allow float variables in upper registers with -mcpu=power8 or -mp8-vector
-Index: gcc/config/rs6000/linux64.h
-===================================================================
---- a/src/gcc/config/rs6000/linux64.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/linux64.h (.../branches/gcc-4_8-branch)
-@@ -25,9 +25,6 @@
-
- #ifndef RS6000_BI_ARCH
-
--#undef DEFAULT_ABI
--#define DEFAULT_ABI ABI_AIX
--
- #undef TARGET_64BIT
- #define TARGET_64BIT 1
-
-@@ -74,7 +71,11 @@
- #undef PROCESSOR_DEFAULT
- #define PROCESSOR_DEFAULT PROCESSOR_POWER7
- #undef PROCESSOR_DEFAULT64
-+#ifdef LINUX64_DEFAULT_ABI_ELFv2
-+#define PROCESSOR_DEFAULT64 PROCESSOR_POWER8
-+#else
- #define PROCESSOR_DEFAULT64 PROCESSOR_POWER7
-+#endif
-
- /* We don't need to generate entries in .fixup, except when
- -mrelocatable or -mrelocatable-lib is given. */
-@@ -88,6 +89,12 @@
- #define INVALID_64BIT "-m%s not supported in this configuration"
- #define INVALID_32BIT INVALID_64BIT
-
-+#ifdef LINUX64_DEFAULT_ABI_ELFv2
-+#define ELFv2_ABI_CHECK (rs6000_elf_abi != 1)
-+#else
-+#define ELFv2_ABI_CHECK (rs6000_elf_abi == 2)
-+#endif
-+
- #undef SUBSUBTARGET_OVERRIDE_OPTIONS
- #define SUBSUBTARGET_OVERRIDE_OPTIONS \
- do \
-@@ -102,6 +109,12 @@
- error (INVALID_64BIT, "call"); \
- } \
- dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \
-+ if (ELFv2_ABI_CHECK) \
-+ { \
-+ rs6000_current_abi = ABI_ELFv2; \
-+ if (dot_symbols) \
-+ error ("-mcall-aixdesc incompatible with -mabi=elfv2"); \
-+ } \
- if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \
- { \
- rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \
-@@ -136,8 +149,11 @@
- SET_CMODEL (CMODEL_MEDIUM); \
- if (rs6000_current_cmodel != CMODEL_SMALL) \
- { \
-- TARGET_NO_FP_IN_TOC = 0; \
-- TARGET_NO_SUM_IN_TOC = 0; \
-+ if (!global_options_set.x_TARGET_NO_FP_IN_TOC) \
-+ TARGET_NO_FP_IN_TOC \
-+ = rs6000_current_cmodel == CMODEL_MEDIUM; \
-+ if (!global_options_set.x_TARGET_NO_SUM_IN_TOC) \
-+ TARGET_NO_SUM_IN_TOC = 0; \
- } \
- } \
- } \
-@@ -351,7 +367,11 @@
- #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
-
- #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
--#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1"
-+#ifdef LINUX64_DEFAULT_ABI_ELFv2
-+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}"
-+#else
-+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}"
-+#endif
- #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
- #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
- #if DEFAULT_LIBC == LIBC_UCLIBC
-Index: gcc/config/rs6000/darwin.h
-===================================================================
---- a/src/gcc/config/rs6000/darwin.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/darwin.h (.../branches/gcc-4_8-branch)
-@@ -205,7 +205,8 @@
- "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
- "vrsave", "vscr", \
- "spe_acc", "spefscr", \
-- "sfp" \
-+ "sfp", \
-+ "tfhar", "tfiar", "texasr" \
- }
-
- /* This outputs NAME to FILE. */
-Index: gcc/config/rs6000/rs6000.c
-===================================================================
---- a/src/gcc/config/rs6000/rs6000.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- /* Subroutines used for code generation on IBM RS/6000.
-- Copyright (C) 1991-2013 Free Software Foundation, Inc.
-+ Copyright (C) 1991-2014 Free Software Foundation, Inc.
- Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
- This file is part of GCC.
-@@ -56,6 +56,7 @@
- #include "intl.h"
- #include "params.h"
- #include "tm-constrs.h"
-+#include "ira.h"
- #include "opts.h"
- #include "tree-vectorizer.h"
- #include "dumpfile.h"
-@@ -96,6 +97,7 @@
- int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
- int varargs_save_offset; /* offset to save the varargs registers */
- int ehrd_offset; /* offset to EH return data */
-+ int ehcr_offset; /* offset to EH CR field data */
- int reg_size; /* register size (4 or 8) */
- HOST_WIDE_INT vars_size; /* variable save area size */
- int parm_size; /* outgoing parameter size */
-@@ -139,6 +141,8 @@
- 64-bits wide and is allocated early enough so that the offset
- does not overflow the 16-bit load/store offset field. */
- rtx sdmode_stack_slot;
-+ /* Flag if r2 setup is needed with ELFv2 ABI. */
-+ bool r2_setup_needed;
- } machine_function;
-
- /* Support targetm.vectorize.builtin_mask_for_load. */
-@@ -189,9 +193,6 @@
- /* Map register number to register class. */
- enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
-
--/* Reload functions based on the type and the vector unit. */
--static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];
--
- static int dbg_cost_ctrl;
-
- /* Built in types. */
-@@ -289,6 +290,105 @@
- don't link in rs6000-c.c, so we can't call it directly. */
- void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
-
-+/* Simplfy register classes into simpler classifications. We assume
-+ GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
-+ check for standard register classes (gpr/floating/altivec/vsx) and
-+ floating/vector classes (float/altivec/vsx). */
-+
-+enum rs6000_reg_type {
-+ NO_REG_TYPE,
-+ PSEUDO_REG_TYPE,
-+ GPR_REG_TYPE,
-+ VSX_REG_TYPE,
-+ ALTIVEC_REG_TYPE,
-+ FPR_REG_TYPE,
-+ SPR_REG_TYPE,
-+ CR_REG_TYPE,
-+ SPE_ACC_TYPE,
-+ SPEFSCR_REG_TYPE
-+};
-+
-+/* Map register class to register type. */
-+static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
-+
-+/* First/last register type for the 'normal' register types (i.e. general
-+ purpose, floating point, altivec, and VSX registers). */
-+#define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
-+
-+#define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
-+
-+
-+/* Register classes we care about in secondary reload or go if legitimate
-+ address. We only need to worry about GPR, FPR, and Altivec registers here,
-+ along an ANY field that is the OR of the 3 register classes. */
-+
-+enum rs6000_reload_reg_type {
-+ RELOAD_REG_GPR, /* General purpose registers. */
-+ RELOAD_REG_FPR, /* Traditional floating point regs. */
-+ RELOAD_REG_VMX, /* Altivec (VMX) registers. */
-+ RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
-+ N_RELOAD_REG
-+};
-+
-+/* For setting up register classes, loop through the 3 register classes mapping
-+ into real registers, and skip the ANY class, which is just an OR of the
-+ bits. */
-+#define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
-+#define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
-+
-+/* Map reload register type to a register in the register class. */
-+struct reload_reg_map_type {
-+ const char *name; /* Register class name. */
-+ int reg; /* Register in the register class. */
-+};
-+
-+static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
-+ { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
-+ { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
-+ { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
-+ { "Any", -1 }, /* RELOAD_REG_ANY. */
-+};
-+
-+/* Mask bits for each register class, indexed per mode. Historically the
-+ compiler has been more restrictive which types can do PRE_MODIFY instead of
-+ PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
-+typedef unsigned char addr_mask_type;
-+
-+#define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
-+#define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
-+#define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
-+#define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
-+#define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
-+#define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
-+
-+/* Register type masks based on the type, of valid addressing modes. */
-+struct rs6000_reg_addr {
-+ enum insn_code reload_load; /* INSN to reload for loading. */
-+ enum insn_code reload_store; /* INSN to reload for storing. */
-+ enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
-+ enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
-+ enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
-+ addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
-+};
-+
-+static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
-+
-+/* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
-+static inline bool
-+mode_supports_pre_incdec_p (enum machine_mode mode)
-+{
-+ return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
-+ != 0);
-+}
-+
-+/* Helper function to say whether a mode supports PRE_MODIFY. */
-+static inline bool
-+mode_supports_pre_modify_p (enum machine_mode mode)
-+{
-+ return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
-+ != 0);
-+}
-+
-
- /* Target cpu costs. */
-
-@@ -828,6 +928,25 @@
- 12, /* prefetch streams */
- };
-
-+/* Instruction costs on POWER8 processors. */
-+static const
-+struct processor_costs power8_cost = {
-+ COSTS_N_INSNS (3), /* mulsi */
-+ COSTS_N_INSNS (3), /* mulsi_const */
-+ COSTS_N_INSNS (3), /* mulsi_const9 */
-+ COSTS_N_INSNS (3), /* muldi */
-+ COSTS_N_INSNS (19), /* divsi */
-+ COSTS_N_INSNS (35), /* divdi */
-+ COSTS_N_INSNS (3), /* fp */
-+ COSTS_N_INSNS (3), /* dmul */
-+ COSTS_N_INSNS (14), /* sdiv */
-+ COSTS_N_INSNS (17), /* ddiv */
-+ 128, /* cache line size */
-+ 32, /* l1 cache */
-+ 256, /* l2 cache */
-+ 12, /* prefetch streams */
-+};
-+
- /* Instruction costs on POWER A2 processors. */
- static const
- struct processor_costs ppca2_cost = {
-@@ -855,6 +974,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -878,6 +998,9 @@
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
- { NAME, ICODE, MASK, ATTR },
-
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
-+ { NAME, ICODE, MASK, ATTR },
-+
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
- { NAME, ICODE, MASK, ATTR },
-
-@@ -908,6 +1031,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -948,6 +1072,7 @@
- static void paired_init_builtins (void);
- static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
- static void spe_init_builtins (void);
-+static void htm_init_builtins (void);
- static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
- static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
- static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
-@@ -1020,6 +1145,13 @@
- static void rs6000_print_builtin_options (FILE *, int, const char *,
- HOST_WIDE_INT);
-
-+static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
-+static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
-+ enum rs6000_reg_type,
-+ enum machine_mode,
-+ secondary_reload_info *,
-+ bool);
-+
- /* Hash table stuff for keeping track of TOC entries. */
-
- struct GTY(()) toc_hash_struct
-@@ -1068,7 +1200,9 @@
- /* SPE registers. */
- "spe_acc", "spefscr",
- /* Soft frame pointer. */
-- "sfp"
-+ "sfp",
-+ /* HTM SPR registers. */
-+ "tfhar", "tfiar", "texasr"
- };
-
- #ifdef TARGET_REGNAMES
-@@ -1094,7 +1228,9 @@
- /* SPE registers. */
- "spe_acc", "spefscr",
- /* Soft frame pointer. */
-- "sfp"
-+ "sfp",
-+ /* HTM SPR registers. */
-+ "tfhar", "tfiar", "texasr"
- };
- #endif
-
-@@ -1316,6 +1452,9 @@
- #undef TARGET_RETURN_IN_MEMORY
- #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
-
-+#undef TARGET_RETURN_IN_MSB
-+#define TARGET_RETURN_IN_MSB rs6000_return_in_msb
-+
- #undef TARGET_SETUP_INCOMING_VARARGS
- #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
-
-@@ -1425,6 +1564,9 @@
- #undef TARGET_MODE_DEPENDENT_ADDRESS_P
- #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
-
-+#undef TARGET_LRA_P
-+#define TARGET_LRA_P rs6000_lra_p
-+
- #undef TARGET_CAN_ELIMINATE
- #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
-
-@@ -1513,8 +1655,9 @@
- {
- unsigned HOST_WIDE_INT reg_size;
-
-+ /* TF/TD modes are special in that they always take 2 registers. */
- if (FP_REGNO_P (regno))
-- reg_size = (VECTOR_MEM_VSX_P (mode)
-+ reg_size = ((VECTOR_MEM_VSX_P (mode) && mode != TDmode && mode != TFmode)
- ? UNITS_PER_VSX_WORD
- : UNITS_PER_FP_WORD);
-
-@@ -1546,16 +1689,39 @@
- {
- int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
-
-+ /* PTImode can only go in GPRs. Quad word memory operations require even/odd
-+ register combinations, and use PTImode where we need to deal with quad
-+ word memory operations. Don't allow quad words in the argument or frame
-+ pointer registers, just registers 0..31. */
-+ if (mode == PTImode)
-+ return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
-+ && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
-+ && ((regno & 1) == 0));
-+
- /* VSX registers that overlap the FPR registers are larger than for non-VSX
- implementations. Don't allow an item to be split between a FP register
-- and an Altivec register. */
-- if (VECTOR_MEM_VSX_P (mode))
-+ and an Altivec register. Allow TImode in all VSX registers if the user
-+ asked for it. */
-+ if (TARGET_VSX && VSX_REGNO_P (regno)
-+ && (VECTOR_MEM_VSX_P (mode)
-+ || (TARGET_VSX_SCALAR_FLOAT && mode == SFmode)
-+ || (TARGET_VSX_SCALAR_DOUBLE && (mode == DFmode || mode == DImode))
-+ || (TARGET_VSX_TIMODE && mode == TImode)
-+ || (TARGET_VADDUQM && mode == V1TImode)))
- {
- if (FP_REGNO_P (regno))
- return FP_REGNO_P (last_regno);
-
- if (ALTIVEC_REGNO_P (regno))
-- return ALTIVEC_REGNO_P (last_regno);
-+ {
-+ if (mode == SFmode && !TARGET_UPPER_REGS_SF)
-+ return 0;
-+
-+ if ((mode == DFmode || mode == DImode) && !TARGET_UPPER_REGS_DF)
-+ return 0;
-+
-+ return ALTIVEC_REGNO_P (last_regno);
-+ }
- }
-
- /* The GPRs can hold any mode, but values bigger than one register
-@@ -1564,8 +1730,7 @@
- return INT_REGNO_P (last_regno);
-
- /* The float registers (except for VSX vector modes) can only hold floating
-- modes and DImode. This excludes the 32-bit decimal float mode for
-- now. */
-+ modes and DImode. */
- if (FP_REGNO_P (regno))
- {
- if (SCALAR_FLOAT_MODE_P (mode)
-@@ -1593,15 +1758,15 @@
-
- /* AltiVec only in AldyVec registers. */
- if (ALTIVEC_REGNO_P (regno))
-- return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);
-+ return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
-+ || mode == V1TImode);
-
- /* ...but GPRs can hold SIMD data on the SPE in one register. */
- if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
- return 1;
-
-- /* We cannot put TImode anywhere except general register and it must be able
-- to fit within the register set. In the future, allow TImode in the
-- Altivec or VSX registers. */
-+ /* We cannot put non-VSX TImode or PTImode anywhere except general register
-+ and it must be able to fit within the register set. */
-
- return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
- }
-@@ -1674,10 +1839,77 @@
- comma = "";
- }
-
-+ len += fprintf (stderr, "%sreg-class = %s", comma,
-+ reg_class_names[(int)rs6000_regno_regclass[r]]);
-+ comma = ", ";
-+
-+ if (len > 70)
-+ {
-+ fprintf (stderr, ",\n\t");
-+ comma = "";
-+ }
-+
- fprintf (stderr, "%sregno = %d\n", comma, r);
- }
- }
-
-+static const char *
-+rs6000_debug_vector_unit (enum rs6000_vector v)
-+{
-+ const char *ret;
-+
-+ switch (v)
-+ {
-+ case VECTOR_NONE: ret = "none"; break;
-+ case VECTOR_ALTIVEC: ret = "altivec"; break;
-+ case VECTOR_VSX: ret = "vsx"; break;
-+ case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
-+ case VECTOR_PAIRED: ret = "paired"; break;
-+ case VECTOR_SPE: ret = "spe"; break;
-+ case VECTOR_OTHER: ret = "other"; break;
-+ default: ret = "unknown"; break;
-+ }
-+
-+ return ret;
-+}
-+
-+/* Print the address masks in a human readble fashion. */
-+DEBUG_FUNCTION void
-+rs6000_debug_print_mode (ssize_t m)
-+{
-+ ssize_t rc;
-+
-+ fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
-+ for (rc = 0; rc < N_RELOAD_REG; rc++)
-+ {
-+ addr_mask_type mask = reg_addr[m].addr_mask[rc];
-+ fprintf (stderr,
-+ " %s: %c%c%c%c%c%c",
-+ reload_reg_map[rc].name,
-+ (mask & RELOAD_REG_VALID) != 0 ? 'v' : ' ',
-+ (mask & RELOAD_REG_MULTIPLE) != 0 ? 'm' : ' ',
-+ (mask & RELOAD_REG_INDEXED) != 0 ? 'i' : ' ',
-+ (mask & RELOAD_REG_OFFSET) != 0 ? 'o' : ' ',
-+ (mask & RELOAD_REG_PRE_INCDEC) != 0 ? '+' : ' ',
-+ (mask & RELOAD_REG_PRE_MODIFY) != 0 ? '+' : ' ');
-+ }
-+
-+ if (rs6000_vector_unit[m] != VECTOR_NONE
-+ || rs6000_vector_mem[m] != VECTOR_NONE
-+ || (reg_addr[m].reload_store != CODE_FOR_nothing)
-+ || (reg_addr[m].reload_load != CODE_FOR_nothing))
-+ {
-+ fprintf (stderr,
-+ " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",
-+ rs6000_debug_vector_unit (rs6000_vector_unit[m]),
-+ rs6000_debug_vector_unit (rs6000_vector_mem[m]),
-+ (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
-+ (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
-+ }
-+
-+ fputs ("\n", stderr);
-+}
-+
- #define DEBUG_FMT_ID "%-32s= "
- #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
- #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
-@@ -1690,6 +1922,7 @@
- static const char *const tf[2] = { "false", "true" };
- const char *nl = (const char *)0;
- int m;
-+ size_t m1, m2, v;
- char costly_num[20];
- char nop_num[20];
- char flags_buffer[40];
-@@ -1700,20 +1933,69 @@
- const char *cmodel_str;
- struct cl_target_option cl_opts;
-
-- /* Map enum rs6000_vector to string. */
-- static const char *rs6000_debug_vector_unit[] = {
-- "none",
-- "altivec",
-- "vsx",
-- "paired",
-- "spe",
-- "other"
-+ /* Modes we want tieable information on. */
-+ static const enum machine_mode print_tieable_modes[] = {
-+ QImode,
-+ HImode,
-+ SImode,
-+ DImode,
-+ TImode,
-+ PTImode,
-+ SFmode,
-+ DFmode,
-+ TFmode,
-+ SDmode,
-+ DDmode,
-+ TDmode,
-+ V8QImode,
-+ V4HImode,
-+ V2SImode,
-+ V16QImode,
-+ V8HImode,
-+ V4SImode,
-+ V2DImode,
-+ V1TImode,
-+ V32QImode,
-+ V16HImode,
-+ V8SImode,
-+ V4DImode,
-+ V2TImode,
-+ V2SFmode,
-+ V4SFmode,
-+ V2DFmode,
-+ V8SFmode,
-+ V4DFmode,
-+ CCmode,
-+ CCUNSmode,
-+ CCEQmode,
- };
-
-- fprintf (stderr, "Register information: (last virtual reg = %d)\n",
-- LAST_VIRTUAL_REGISTER);
-- rs6000_debug_reg_print (0, 31, "gr");
-- rs6000_debug_reg_print (32, 63, "fp");
-+ /* Virtual regs we are interested in. */
-+ const static struct {
-+ int regno; /* register number. */
-+ const char *name; /* register name. */
-+ } virtual_regs[] = {
-+ { STACK_POINTER_REGNUM, "stack pointer:" },
-+ { TOC_REGNUM, "toc: " },
-+ { STATIC_CHAIN_REGNUM, "static chain: " },
-+ { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
-+ { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
-+ { ARG_POINTER_REGNUM, "arg pointer: " },
-+ { FRAME_POINTER_REGNUM, "frame pointer:" },
-+ { FIRST_PSEUDO_REGISTER, "first pseudo: " },
-+ { FIRST_VIRTUAL_REGISTER, "first virtual:" },
-+ { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
-+ { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
-+ { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
-+ { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
-+ { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
-+ { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
-+ { LAST_VIRTUAL_REGISTER, "last virtual: " },
-+ };
-+
-+ fputs ("\nHard register information:\n", stderr);
-+ rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
-+ rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
- rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
- LAST_ALTIVEC_REGNO,
- "vs");
-@@ -1726,6 +2008,10 @@
- rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
- rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
-
-+ fputs ("\nVirtual/stack/frame registers:\n", stderr);
-+ for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
-+ fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
-+
- fprintf (stderr,
- "\n"
- "d reg_class = %s\n"
-@@ -1734,7 +2020,19 @@
- "wa reg_class = %s\n"
- "wd reg_class = %s\n"
- "wf reg_class = %s\n"
-- "ws reg_class = %s\n\n",
-+ "wg reg_class = %s\n"
-+ "wl reg_class = %s\n"
-+ "wm reg_class = %s\n"
-+ "wr reg_class = %s\n"
-+ "ws reg_class = %s\n"
-+ "wt reg_class = %s\n"
-+ "wu reg_class = %s\n"
-+ "wv reg_class = %s\n"
-+ "ww reg_class = %s\n"
-+ "wx reg_class = %s\n"
-+ "wy reg_class = %s\n"
-+ "wz reg_class = %s\n"
-+ "\n",
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
-@@ -1741,18 +2039,51 @@
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
-- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
-+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]]);
-
-+ nl = "\n";
- for (m = 0; m < NUM_MACHINE_MODES; ++m)
-- if (rs6000_vector_unit[m] || rs6000_vector_mem[m])
-- {
-- nl = "\n";
-- fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
-- GET_MODE_NAME (m),
-- rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],
-- rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);
-- }
-+ rs6000_debug_print_mode (m);
-
-+ fputs ("\n", stderr);
-+
-+ for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
-+ {
-+ enum machine_mode mode1 = print_tieable_modes[m1];
-+ bool first_time = true;
-+
-+ nl = (const char *)0;
-+ for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
-+ {
-+ enum machine_mode mode2 = print_tieable_modes[m2];
-+ if (mode1 != mode2 && MODES_TIEABLE_P (mode1, mode2))
-+ {
-+ if (first_time)
-+ {
-+ fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
-+ nl = "\n";
-+ first_time = false;
-+ }
-+
-+ fprintf (stderr, " %s", GET_MODE_NAME (mode2));
-+ }
-+ }
-+
-+ if (!first_time)
-+ fputs ("\n", stderr);
-+ }
-+
- if (nl)
- fputs (nl, stderr);
-
-@@ -1913,6 +2244,7 @@
- {
- case ABI_NONE: abi_str = "none"; break;
- case ABI_AIX: abi_str = "aix"; break;
-+ case ABI_ELFv2: abi_str = "ELFv2"; break;
- case ABI_V4: abi_str = "V4"; break;
- case ABI_DARWIN: abi_str = "darwin"; break;
- default: abi_str = "unknown"; break;
-@@ -1932,9 +2264,34 @@
- if (rs6000_float_gprs)
- fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
-
-+ fprintf (stderr, DEBUG_FMT_S, "fprs",
-+ (TARGET_FPRS ? "true" : "false"));
-+
-+ fprintf (stderr, DEBUG_FMT_S, "single_float",
-+ (TARGET_SINGLE_FLOAT ? "true" : "false"));
-+
-+ fprintf (stderr, DEBUG_FMT_S, "double_float",
-+ (TARGET_DOUBLE_FLOAT ? "true" : "false"));
-+
-+ fprintf (stderr, DEBUG_FMT_S, "soft_float",
-+ (TARGET_SOFT_FLOAT ? "true" : "false"));
-+
-+ fprintf (stderr, DEBUG_FMT_S, "e500_single",
-+ (TARGET_E500_SINGLE ? "true" : "false"));
-+
-+ fprintf (stderr, DEBUG_FMT_S, "e500_double",
-+ (TARGET_E500_DOUBLE ? "true" : "false"));
-+
- if (TARGET_LINK_STACK)
- fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
-
-+ if (targetm.lra_p ())
-+ fprintf (stderr, DEBUG_FMT_S, "lra", "true");
-+
-+ if (TARGET_P8_FUSION)
-+ fprintf (stderr, DEBUG_FMT_S, "p8 fusion",
-+ (TARGET_P8_FUSION_SIGN) ? "zero+sign" : "zero");
-+
- fprintf (stderr, DEBUG_FMT_S, "plt-format",
- TARGET_SECURE_PLT ? "secure" : "bss");
- fprintf (stderr, DEBUG_FMT_S, "struct-return",
-@@ -1954,11 +2311,106 @@
- (int)RS6000_BUILTIN_COUNT);
- }
-
-+
-+/* Update the addr mask bits in reg_addr to help secondary reload and go if
-+ legitimate address support to figure out the appropriate addressing to
-+ use. */
-+
-+static void
-+rs6000_setup_reg_addr_masks (void)
-+{
-+ ssize_t rc, reg, m, nregs;
-+ addr_mask_type any_addr_mask, addr_mask;
-+
-+ for (m = 0; m < NUM_MACHINE_MODES; ++m)
-+ {
-+ /* SDmode is special in that we want to access it only via REG+REG
-+ addressing on power7 and above, since we want to use the LFIWZX and
-+ STFIWZX instructions to load it. */
-+ bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
-+
-+ any_addr_mask = 0;
-+ for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
-+ {
-+ addr_mask = 0;
-+ reg = reload_reg_map[rc].reg;
-+
-+ /* Can mode values go in the GPR/FPR/Altivec registers? */
-+ if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
-+ {
-+ nregs = rs6000_hard_regno_nregs[m][reg];
-+ addr_mask |= RELOAD_REG_VALID;
-+
-+ /* Indicate if the mode takes more than 1 physical register. If
-+ it takes a single register, indicate it can do REG+REG
-+ addressing. */
-+ if (nregs > 1 || m == BLKmode)
-+ addr_mask |= RELOAD_REG_MULTIPLE;
-+ else
-+ addr_mask |= RELOAD_REG_INDEXED;
-+
-+ /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
-+ addressing. Restrict addressing on SPE for 64-bit types
-+ because of the SUBREG hackery used to address 64-bit floats in
-+ '32-bit' GPRs. To simplify secondary reload, don't allow
-+ update forms on scalar floating point types that can go in the
-+ upper registers. */
-+
-+ if (TARGET_UPDATE
-+ && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
-+ && GET_MODE_SIZE (m) <= 8
-+ && !VECTOR_MODE_P (m)
-+ && !COMPLEX_MODE_P (m)
-+ && !indexed_only_p
-+ && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8)
-+ && !(m == DFmode && TARGET_UPPER_REGS_DF)
-+ && !(m == SFmode && TARGET_UPPER_REGS_SF))
-+ {
-+ addr_mask |= RELOAD_REG_PRE_INCDEC;
-+
-+ /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
-+ we don't allow PRE_MODIFY for some multi-register
-+ operations. */
-+ switch (m)
-+ {
-+ default:
-+ addr_mask |= RELOAD_REG_PRE_MODIFY;
-+ break;
-+
-+ case DImode:
-+ if (TARGET_POWERPC64)
-+ addr_mask |= RELOAD_REG_PRE_MODIFY;
-+ break;
-+
-+ case DFmode:
-+ case DDmode:
-+ if (TARGET_DF_INSN)
-+ addr_mask |= RELOAD_REG_PRE_MODIFY;
-+ break;
-+ }
-+ }
-+ }
-+
-+ /* GPR and FPR registers can do REG+OFFSET addressing, except
-+ possibly for SDmode. */
-+ if ((addr_mask != 0) && !indexed_only_p
-+ && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR))
-+ addr_mask |= RELOAD_REG_OFFSET;
-+
-+ reg_addr[m].addr_mask[rc] = addr_mask;
-+ any_addr_mask |= addr_mask;
-+ }
-+
-+ reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
-+ }
-+}
-+
-+
- /* Initialize the various global tables that are based on register size. */
- static void
- rs6000_init_hard_regno_mode_ok (bool global_init_p)
- {
-- int r, m, c;
-+ ssize_t r, m, c;
- int align64;
- int align32;
-
-@@ -1987,21 +2439,55 @@
- rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
- rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
- rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
-+ rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
-+ rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
-+ rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
- rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
- rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
-
-- /* Precalculate vector information, this must be set up before the
-- rs6000_hard_regno_nregs_internal below. */
-- for (m = 0; m < NUM_MACHINE_MODES; ++m)
-+ /* Precalculate register class to simpler reload register class. We don't
-+ need all of the register classes that are combinations of different
-+ classes, just the simple ones that have constraint letters. */
-+ for (c = 0; c < N_REG_CLASSES; c++)
-+ reg_class_to_reg_type[c] = NO_REG_TYPE;
-+
-+ reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
-+ reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
-+ reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
-+ reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
-+ reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
-+ reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
-+ reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
-+ reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
-+ reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
-+ reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
-+ reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE;
-+ reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE;
-+
-+ if (TARGET_VSX)
- {
-- rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;
-- rs6000_vector_reload[m][0] = CODE_FOR_nothing;
-- rs6000_vector_reload[m][1] = CODE_FOR_nothing;
-+ reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
-+ reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
- }
-+ else
-+ {
-+ reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
-+ reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
-+ }
-
-- for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)
-- rs6000_constraints[c] = NO_REGS;
-+ /* Precalculate the valid memory formats as well as the vector information,
-+ this must be set up before the rs6000_hard_regno_nregs_internal calls
-+ below. */
-+ gcc_assert ((int)VECTOR_NONE == 0);
-+ memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
-+ memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
-
-+ gcc_assert ((int)CODE_FOR_nothing == 0);
-+ memset ((void *) &reg_addr[0], '\0', sizeof (reg_addr));
-+
-+ gcc_assert ((int)NO_REGS == 0);
-+ memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
-+
- /* The VSX hardware allows native alignment for vectors, but control whether the compiler
- believes it can use native alignment or still uses 128-bit alignment. */
- if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
-@@ -2062,13 +2548,19 @@
- }
- }
-
-- /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
-- Altivec doesn't have 64-bit support. */
-+ /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
-+ do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
- if (TARGET_VSX)
- {
- rs6000_vector_mem[V2DImode] = VECTOR_VSX;
-- rs6000_vector_unit[V2DImode] = VECTOR_NONE;
-+ rs6000_vector_unit[V2DImode]
-+ = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
- rs6000_vector_align[V2DImode] = align64;
-+
-+ rs6000_vector_mem[V1TImode] = VECTOR_VSX;
-+ rs6000_vector_unit[V1TImode]
-+ = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
-+ rs6000_vector_align[V1TImode] = 128;
- }
-
- /* DFmode, see if we want to use the VSX unit. */
-@@ -2076,14 +2568,48 @@
- {
- rs6000_vector_unit[DFmode] = VECTOR_VSX;
- rs6000_vector_mem[DFmode]
-- = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);
-+ = (TARGET_UPPER_REGS_DF ? VECTOR_VSX : VECTOR_NONE);
- rs6000_vector_align[DFmode] = align64;
- }
-
-+ /* Allow TImode in VSX register and set the VSX memory macros. */
-+ if (TARGET_VSX && TARGET_VSX_TIMODE)
-+ {
-+ rs6000_vector_mem[TImode] = VECTOR_VSX;
-+ rs6000_vector_align[TImode] = align64;
-+ }
-+
- /* TODO add SPE and paired floating point vector support. */
-
- /* Register class constraints for the constraints that depend on compile
-- switches. */
-+ switches. When the VSX code was added, different constraints were added
-+ based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
-+ of the VSX registers are used. The register classes for scalar floating
-+ point types is set, based on whether we allow that type into the upper
-+ (Altivec) registers. GCC has register classes to target the Altivec
-+ registers for load/store operations, to select using a VSX memory
-+ operation instead of the traditional floating point operation. The
-+ constraints are:
-+
-+ d - Register class to use with traditional DFmode instructions.
-+ f - Register class to use with traditional SFmode instructions.
-+ v - Altivec register.
-+ wa - Any VSX register.
-+ wd - Preferred register class for V2DFmode.
-+ wf - Preferred register class for V4SFmode.
-+ wg - Float register for power6x move insns.
-+ wl - Float register if we can do 32-bit signed int loads.
-+ wm - VSX register for ISA 2.07 direct move operations.
-+ wr - GPR if 64-bit mode is permitted.
-+ ws - Register class to do ISA 2.06 DF operations.
-+ wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
-+ wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
-+ wt - VSX register for TImode in VSX registers.
-+ ww - Register class to do SF conversions in with VSX operations.
-+ wx - Float register if we can do 32-bit int stores.
-+ wy - Register class to do ISA 2.07 SF operations.
-+ wz - Float register if we can do 32-bit unsigned int loads. */
-+
- if (TARGET_HARD_FLOAT && TARGET_FPRS)
- rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
-
-@@ -2092,64 +2618,164 @@
-
- if (TARGET_VSX)
- {
-- /* At present, we just use VSX_REGS, but we have different constraints
-- based on the use, in case we want to fine tune the default register
-- class used. wa = any VSX register, wf = register class to use for
-- V4SF, wd = register class to use for V2DF, and ws = register classs to
-- use for DF scalars. */
- rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
-+ rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
- rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
-- rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
-- rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY
-- ? VSX_REGS
-- : FLOAT_REGS);
-+
-+ if (TARGET_VSX_TIMODE)
-+ rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS;
-+
-+ if (TARGET_UPPER_REGS_DF)
-+ {
-+ rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS;
-+ rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS;
-+ }
-+ else
-+ rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS;
- }
-
-+ /* Add conditional constraints based on various options, to allow us to
-+ collapse multiple insn patterns. */
- if (TARGET_ALTIVEC)
- rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
-
-- /* Set up the reload helper functions. */
-+ if (TARGET_MFPGPR)
-+ rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
-+
-+ if (TARGET_LFIWAX)
-+ rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS;
-+
-+ if (TARGET_DIRECT_MOVE)
-+ rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
-+
-+ if (TARGET_POWERPC64)
-+ rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
-+
-+ if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF)
-+ {
-+ rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
-+ rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
-+ rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
-+ }
-+ else if (TARGET_P8_VECTOR)
-+ {
-+ rs6000_constraints[RS6000_CONSTRAINT_wy] = FLOAT_REGS;
-+ rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
-+ }
-+ else if (TARGET_VSX)
-+ rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
-+
-+ if (TARGET_STFIWX)
-+ rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS;
-+
-+ if (TARGET_LFIWZX)
-+ rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS;
-+
-+ /* Set up the reload helper and direct move functions. */
- if (TARGET_VSX || TARGET_ALTIVEC)
- {
- if (TARGET_64BIT)
- {
-- rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;
-- rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;
-- rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;
-- rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;
-- rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;
-- rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;
-- rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;
-- rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;
-- rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;
-- rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;
-- rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;
-- rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;
-- if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
-+ reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
-+ reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
-+ reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
-+ reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
-+ reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
-+ reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
-+ reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
-+ reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
-+ reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
-+ reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
-+ reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
-+ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
-+ reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
-+ reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
-+ if (TARGET_VSX && TARGET_UPPER_REGS_DF)
- {
-- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store;
-- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load;
-+ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
-+ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
-+ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
-+ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
- }
-+ if (TARGET_P8_VECTOR)
-+ {
-+ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
-+ reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
-+ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
-+ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
-+ }
-+ if (TARGET_VSX_TIMODE)
-+ {
-+ reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
-+ reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
-+ }
-+ if (TARGET_DIRECT_MOVE)
-+ {
-+ if (TARGET_POWERPC64)
-+ {
-+ reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
-+ reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
-+ reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
-+ reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
-+ reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
-+ reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
-+ reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
-+ reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
-+ reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
-+
-+ reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
-+ reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
-+ reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
-+ reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
-+ reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
-+ reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
-+ reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
-+ reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
-+ reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
-+ }
-+ else
-+ {
-+ reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
-+ reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
-+ reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
-+ }
-+ }
- }
- else
- {
-- rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;
-- rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;
-- rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;
-- rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;
-- rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;
-- rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;
-- rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;
-- rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;
-- rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;
-- rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;
-- rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;
-- rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;
-- if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
-+ reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
-+ reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
-+ reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
-+ reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
-+ reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
-+ reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
-+ reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
-+ reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
-+ reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
-+ reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
-+ reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
-+ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
-+ reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
-+ reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
-+ if (TARGET_VSX && TARGET_UPPER_REGS_DF)
- {
-- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store;
-- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load;
-+ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
-+ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
-+ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
-+ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
- }
-+ if (TARGET_P8_VECTOR)
-+ {
-+ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
-+ reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
-+ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
-+ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
-+ }
-+ if (TARGET_VSX_TIMODE)
-+ {
-+ reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
-+ reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
-+ }
- }
- }
-
-@@ -2267,6 +2893,11 @@
- }
- }
-
-+ /* Update the addr mask bits in reg_addr to help secondary reload and go if
-+ legitimate address support to figure out the appropriate addressing to
-+ use. */
-+ rs6000_setup_reg_addr_masks ();
-+
- if (global_init_p || TARGET_DEBUG_TARGET)
- {
- if (TARGET_DEBUG_REG)
-@@ -2369,16 +3000,21 @@
- HOST_WIDE_INT
- rs6000_builtin_mask_calculate (void)
- {
-- return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
-- | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
-- | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
-- | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
-- | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
-- | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
-- | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
-- | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
-- | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
-- | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));
-+ return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
-+ | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
-+ | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
-+ | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
-+ | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
-+ | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
-+ | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
-+ | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
-+ | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
-+ | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
-+ | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
-+ | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
-+ | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
-+ | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
-+ | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0));
- }
-
- /* Override command line options. Mostly we process the processor type and
-@@ -2415,7 +3051,8 @@
- calculation works better for RTL loop invariant motion on targets
- with enough (>= 32) registers. It is an expensive optimization.
- So it is on only for peak performance. */
-- if (optimize >= 3 && global_init_p)
-+ if (optimize >= 3 && global_init_p
-+ && !global_options_set.x_flag_ira_loop_pressure)
- flag_ira_loop_pressure = 1;
-
- /* Set the pointer size. */
-@@ -2609,6 +3246,24 @@
- }
- }
-
-+ /* If little-endian, default to -mstrict-align on older processors.
-+ Testing for htm matches power8 and later. */
-+ if (!BYTES_BIG_ENDIAN
-+ && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
-+ rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
-+
-+ /* -maltivec={le,be} implies -maltivec. */
-+ if (rs6000_altivec_element_order != 0)
-+ rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
-+
-+ /* Disallow -maltivec=le in big endian mode for now. This is not
-+ known to be useful for anyone. */
-+ if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)
-+ {
-+ warning (0, N_("-maltivec=le not allowed for big-endian targets"));
-+ rs6000_altivec_element_order = 0;
-+ }
-+
- /* Add some warnings for VSX. */
- if (TARGET_VSX)
- {
-@@ -2619,15 +3274,13 @@
- if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
- msg = N_("-mvsx requires hardware floating point");
- else
-- rs6000_isa_flags &= ~ OPTION_MASK_VSX;
-+ {
-+ rs6000_isa_flags &= ~ OPTION_MASK_VSX;
-+ rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
-+ }
- }
- else if (TARGET_PAIRED_FLOAT)
- msg = N_("-mvsx and -mpaired are incompatible");
-- /* The hardware will allow VSX and little endian, but until we make sure
-- things like vector select, etc. work don't allow VSX on little endian
-- systems at this point. */
-- else if (!BYTES_BIG_ENDIAN)
-- msg = N_("-mvsx used with little endian code");
- else if (TARGET_AVOID_XFORM > 0)
- msg = N_("-mvsx needs indexed addressing");
- else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
-@@ -2647,9 +3300,24 @@
- }
- }
-
-+ /* If hard-float/altivec/vsx were explicitly turned off then don't allow
-+ the -mcpu setting to enable options that conflict. */
-+ if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
-+ && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
-+ | OPTION_MASK_ALTIVEC
-+ | OPTION_MASK_VSX)) != 0)
-+ rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
-+ | OPTION_MASK_DIRECT_MOVE)
-+ & ~rs6000_isa_flags_explicit);
-+
-+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
-+ rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
-+
- /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno-<option> to disable the code. */
-- if (TARGET_VSX)
-+ if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
-+ rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~rs6000_isa_flags_explicit);
-+ else if (TARGET_VSX)
- rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit);
- else if (TARGET_POPCNTD)
- rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
-@@ -2664,6 +3332,99 @@
- else if (TARGET_ALTIVEC)
- rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit);
-
-+ if (TARGET_CRYPTO && !TARGET_ALTIVEC)
-+ {
-+ if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
-+ error ("-mcrypto requires -maltivec");
-+ rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
-+ }
-+
-+ if (TARGET_DIRECT_MOVE && !TARGET_VSX)
-+ {
-+ if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
-+ error ("-mdirect-move requires -mvsx");
-+ rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
-+ }
-+
-+ if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
-+ {
-+ if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
-+ error ("-mpower8-vector requires -maltivec");
-+ rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
-+ }
-+
-+ if (TARGET_P8_VECTOR && !TARGET_VSX)
-+ {
-+ if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
-+ error ("-mpower8-vector requires -mvsx");
-+ rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
-+ }
-+
-+ if (TARGET_VSX_TIMODE && !TARGET_VSX)
-+ {
-+ if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE)
-+ error ("-mvsx-timode requires -mvsx");
-+ rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE;
-+ }
-+
-+ if (TARGET_DFP && !TARGET_HARD_FLOAT)
-+ {
-+ if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
-+ error ("-mhard-dfp requires -mhard-float");
-+ rs6000_isa_flags &= ~OPTION_MASK_DFP;
-+ }
-+
-+ /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
-+ silently turn off quad memory mode. */
-+ if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
-+ {
-+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
-+ warning (0, N_("-mquad-memory requires 64-bit mode"));
-+
-+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
-+ warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
-+
-+ rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
-+ | OPTION_MASK_QUAD_MEMORY_ATOMIC);
-+ }
-+
-+ /* Non-atomic quad memory load/store are disabled for little endian, since
-+ the words are reversed, but atomic operations can still be done by
-+ swapping the words. */
-+ if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
-+ {
-+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
-+ warning (0, N_("-mquad-memory is not available in little endian mode"));
-+
-+ rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
-+ }
-+
-+ /* Assume if the user asked for normal quad memory instructions, they want
-+ the atomic versions as well, unless they explicity told us not to use quad
-+ word atomic instructions. */
-+ if (TARGET_QUAD_MEMORY
-+ && !TARGET_QUAD_MEMORY_ATOMIC
-+ && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
-+ rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
-+
-+ /* Enable power8 fusion if we are tuning for power8, even if we aren't
-+ generating power8 instructions. */
-+ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
-+ rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
-+ & OPTION_MASK_P8_FUSION);
-+
-+ /* Power8 does not fuse sign extended loads with the addis. If we are
-+ optimizing at high levels for speed, convert a sign extended load into a
-+ zero extending load, and an explicit sign extension. */
-+ if (TARGET_P8_FUSION
-+ && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
-+ && optimize_function_for_speed_p (cfun)
-+ && optimize >= 3)
-+ rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
-+
-+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
-+ rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
-+
- /* E500mc does "better" if we inline more aggressively. Respect the
- user's opinion, though. */
- if (rs6000_block_move_inline_limit == 0
-@@ -2787,9 +3548,13 @@
-
- /* Place FP constants in the constant pool instead of TOC
- if section anchors enabled. */
-- if (flag_section_anchors)
-+ if (flag_section_anchors
-+ && !global_options_set.x_TARGET_NO_FP_IN_TOC)
- TARGET_NO_FP_IN_TOC = 1;
-
-+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
-+ rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
-+
- #ifdef SUBTARGET_OVERRIDE_OPTIONS
- SUBTARGET_OVERRIDE_OPTIONS;
- #endif
-@@ -2800,6 +3565,9 @@
- SUB3TARGET_OVERRIDE_OPTIONS;
- #endif
-
-+ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
-+ rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
-+
- /* For the E500 family of cores, reset the single/double FP flags to let us
- check that they remain constant across attributes or pragmas. Also,
- clear a possible request for string instructions, not supported and which
-@@ -2849,16 +3617,19 @@
- && rs6000_cpu != PROCESSOR_POWER5
- && rs6000_cpu != PROCESSOR_POWER6
- && rs6000_cpu != PROCESSOR_POWER7
-+ && rs6000_cpu != PROCESSOR_POWER8
- && rs6000_cpu != PROCESSOR_PPCA2
- && rs6000_cpu != PROCESSOR_CELL
- && rs6000_cpu != PROCESSOR_PPC476);
- rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
- || rs6000_cpu == PROCESSOR_POWER5
-- || rs6000_cpu == PROCESSOR_POWER7);
-+ || rs6000_cpu == PROCESSOR_POWER7
-+ || rs6000_cpu == PROCESSOR_POWER8);
- rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
- || rs6000_cpu == PROCESSOR_POWER5
- || rs6000_cpu == PROCESSOR_POWER6
- || rs6000_cpu == PROCESSOR_POWER7
-+ || rs6000_cpu == PROCESSOR_POWER8
- || rs6000_cpu == PROCESSOR_PPCE500MC
- || rs6000_cpu == PROCESSOR_PPCE500MC64
- || rs6000_cpu == PROCESSOR_PPCE5500
-@@ -2988,7 +3759,7 @@
-
- /* We should always be splitting complex arguments, but we can't break
- Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
-- if (DEFAULT_ABI != ABI_AIX)
-+ if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
- targetm.calls.split_complex_arg = NULL;
- }
-
-@@ -3102,6 +3873,10 @@
- rs6000_cost = &power7_cost;
- break;
-
-+ case PROCESSOR_POWER8:
-+ rs6000_cost = &power8_cost;
-+ break;
-+
- case PROCESSOR_PPCA2:
- rs6000_cost = &ppca2_cost;
- break;
-@@ -3274,7 +4049,8 @@
- && (rs6000_cpu == PROCESSOR_POWER4
- || rs6000_cpu == PROCESSOR_POWER5
- || rs6000_cpu == PROCESSOR_POWER6
-- || rs6000_cpu == PROCESSOR_POWER7))
-+ || rs6000_cpu == PROCESSOR_POWER7
-+ || rs6000_cpu == PROCESSOR_POWER8))
- return 5;
- else
- return align_loops_log;
-@@ -3493,6 +4269,8 @@
- {
- case SFmode:
- return V4SFmode;
-+ case TImode:
-+ return V1TImode;
- case DImode:
- return V2DImode;
- case SImode:
-@@ -3813,6 +4591,22 @@
- enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
- switch (fn)
- {
-+ case BUILT_IN_CLZIMAX:
-+ case BUILT_IN_CLZLL:
-+ case BUILT_IN_CLZL:
-+ case BUILT_IN_CLZ:
-+ if (TARGET_P8_VECTOR && in_mode == out_mode && out_n == in_n)
-+ {
-+ if (out_mode == QImode && out_n == 16)
-+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZB];
-+ else if (out_mode == HImode && out_n == 8)
-+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZH];
-+ else if (out_mode == SImode && out_n == 4)
-+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZW];
-+ else if (out_mode == DImode && out_n == 2)
-+ return rs6000_builtin_decls[P8V_BUILTIN_VCLZD];
-+ }
-+ break;
- case BUILT_IN_COPYSIGN:
- if (VECTOR_UNIT_VSX_P (V2DFmode)
- && out_mode == DFmode && out_n == 2
-@@ -3828,6 +4622,22 @@
- if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
- return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
- break;
-+ case BUILT_IN_POPCOUNTIMAX:
-+ case BUILT_IN_POPCOUNTLL:
-+ case BUILT_IN_POPCOUNTL:
-+ case BUILT_IN_POPCOUNT:
-+ if (TARGET_P8_VECTOR && in_mode == out_mode && out_n == in_n)
-+ {
-+ if (out_mode == QImode && out_n == 16)
-+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTB];
-+ else if (out_mode == HImode && out_n == 8)
-+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTH];
-+ else if (out_mode == SImode && out_n == 4)
-+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTW];
-+ else if (out_mode == DImode && out_n == 2)
-+ return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTD];
-+ }
-+ break;
- case BUILT_IN_SQRT:
- if (VECTOR_UNIT_VSX_P (V2DFmode)
- && out_mode == DFmode && out_n == 2
-@@ -4043,7 +4853,11 @@
- putc ('\n', file);
- }
-
-- if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
-+ if (DEFAULT_ABI == ABI_ELFv2)
-+ fprintf (file, "\t.abiversion 2\n");
-+
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2
-+ || (TARGET_ELF && flag_pic == 2))
- {
- switch_to_section (toc_section);
- switch_to_section (text_section);
-@@ -4230,7 +5044,7 @@
- HOST_WIDE_INT splat_val;
- HOST_WIDE_INT msb_val;
-
-- if (mode == V2DImode || mode == V2DFmode)
-+ if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
- return false;
-
- nunits = GET_MODE_NUNITS (mode);
-@@ -4239,7 +5053,7 @@
-
- val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
- splat_val = val;
-- msb_val = val > 0 ? 0 : -1;
-+ msb_val = val >= 0 ? 0 : -1;
-
- /* Construct the value to be splatted, if possible. If not, return 0. */
- for (i = 2; i <= copies; i *= 2)
-@@ -4274,15 +5088,16 @@
-
- /* Check if VAL is present in every STEP-th element, and the
- other elements are filled with its most significant bit. */
-- for (i = 0; i < nunits - 1; ++i)
-+ for (i = 1; i < nunits; ++i)
- {
- HOST_WIDE_INT desired_val;
-- if (((BYTES_BIG_ENDIAN ? i + 1 : i) & (step - 1)) == 0)
-+ unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
-+ if ((i & (step - 1)) == 0)
- desired_val = val;
- else
- desired_val = msb_val;
-
-- if (desired_val != const_vector_elt_as_int (op, i))
-+ if (desired_val != const_vector_elt_as_int (op, elt))
- return false;
- }
-
-@@ -4308,7 +5123,7 @@
- if (mode == V2DFmode)
- return zero_constant (op, mode);
-
-- if (mode == V2DImode)
-+ else if (mode == V2DImode)
- {
- /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
- easy. */
-@@ -4326,6 +5141,10 @@
- return false;
- }
-
-+ /* V1TImode is a special container for TImode. Ignore for now. */
-+ else if (mode == V1TImode)
-+ return false;
-+
- /* Start with a vspltisw. */
- step = GET_MODE_NUNITS (mode) / 4;
- copies = 1;
-@@ -4407,7 +5226,7 @@
- if (zero_constant (vec, mode))
- return "xxlxor %x0,%x0,%x0";
-
-- if (mode == V2DImode
-+ if ((mode == V2DImode || mode == V1TImode)
- && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1
- && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)
- return "vspltisw %0,-1";
-@@ -4698,9 +5517,12 @@
- {
- rtx freg = gen_reg_rtx (V4SFmode);
- rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0));
-+ rtx cvt = ((TARGET_XSCVDPSPN)
-+ ? gen_vsx_xscvdpspn_scalar (freg, sreg)
-+ : gen_vsx_xscvdpsp_scalar (freg, sreg));
-
-- emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));
-- emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
-+ emit_insn (cvt);
-+ emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg, const0_rtx));
- }
- else
- {
-@@ -4790,6 +5612,13 @@
- return;
- }
-
-+ /* Simplify setting single element vectors like V1TImode. */
-+ if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
-+ {
-+ emit_move_insn (target, gen_lowpart (mode, val));
-+ return;
-+ }
-+
- /* Load single variable value. */
- mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
- emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
-@@ -4811,10 +5640,29 @@
- XVECEXP (mask, 0, elt*width + i)
- = GEN_INT (i + 0x10);
- x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
-- x = gen_rtx_UNSPEC (mode,
-- gen_rtvec (3, target, reg,
-- force_reg (V16QImode, x)),
-- UNSPEC_VPERM);
-+
-+ if (BYTES_BIG_ENDIAN)
-+ x = gen_rtx_UNSPEC (mode,
-+ gen_rtvec (3, target, reg,
-+ force_reg (V16QImode, x)),
-+ UNSPEC_VPERM);
-+ else
-+ {
-+ /* Invert selector. We prefer to generate VNAND on P8 so
-+ that future fusion opportunities can kick in, but must
-+ generate VNOR elsewhere. */
-+ rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
-+ rtx iorx = (TARGET_P8_VECTOR
-+ ? gen_rtx_IOR (V16QImode, notx, notx)
-+ : gen_rtx_AND (V16QImode, notx, notx));
-+ rtx tmp = gen_reg_rtx (V16QImode);
-+ emit_insn (gen_rtx_SET (VOIDmode, tmp, iorx));
-+
-+ /* Permute with operands reversed and adjusted selector. */
-+ x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
-+ UNSPEC_VPERM);
-+ }
-+
- emit_insn (gen_rtx_SET (VOIDmode, target, x));
- }
-
-@@ -4833,6 +5681,10 @@
- {
- default:
- break;
-+ case V1TImode:
-+ gcc_assert (elt == 0 && inner_mode == TImode);
-+ emit_move_insn (target, gen_lowpart (TImode, vec));
-+ break;
- case V2DFmode:
- emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
- return;
-@@ -4938,7 +5790,7 @@
- purpose. */
- if (GET_CODE (op) == SUBREG
- && (mode == SImode || mode == DImode || mode == TImode
-- || mode == DDmode || mode == TDmode)
-+ || mode == DDmode || mode == TDmode || mode == PTImode)
- && REG_P (SUBREG_REG (op))
- && (GET_MODE (SUBREG_REG (op)) == DFmode
- || GET_MODE (SUBREG_REG (op)) == TFmode))
-@@ -4951,6 +5803,7 @@
- && REG_P (SUBREG_REG (op))
- && (GET_MODE (SUBREG_REG (op)) == DImode
- || GET_MODE (SUBREG_REG (op)) == TImode
-+ || GET_MODE (SUBREG_REG (op)) == PTImode
- || GET_MODE (SUBREG_REG (op)) == DDmode
- || GET_MODE (SUBREG_REG (op)) == TDmode))
- return true;
-@@ -4966,6 +5819,48 @@
- return false;
- }
-
-+/* Return alignment of TYPE. Existing alignment is ALIGN. HOW
-+ selects whether the alignment is abi mandated, optional, or
-+ both abi and optional alignment. */
-+
-+unsigned int
-+rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
-+{
-+ if (how != align_opt)
-+ {
-+ if (TREE_CODE (type) == VECTOR_TYPE)
-+ {
-+ if ((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (type)))
-+ || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type))))
-+ {
-+ if (align < 64)
-+ align = 64;
-+ }
-+ else if (align < 128)
-+ align = 128;
-+ }
-+ else if (TARGET_E500_DOUBLE
-+ && TREE_CODE (type) == REAL_TYPE
-+ && TYPE_MODE (type) == DFmode)
-+ {
-+ if (align < 64)
-+ align = 64;
-+ }
-+ }
-+
-+ if (how != align_abi)
-+ {
-+ if (TREE_CODE (type) == ARRAY_TYPE
-+ && TYPE_MODE (TREE_TYPE (type)) == QImode)
-+ {
-+ if (align < BITS_PER_WORD)
-+ align = BITS_PER_WORD;
-+ }
-+ }
-+
-+ return align;
-+}
-+
- /* AIX increases natural record alignment to doubleword if the first
- field is an FP double while the FP fields remain word aligned. */
-
-@@ -5087,6 +5982,73 @@
- || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
- }
-
-+/* Return true if this is a move direct operation between GPR registers and
-+ floating point/VSX registers. */
-+
-+bool
-+direct_move_p (rtx op0, rtx op1)
-+{
-+ int regno0, regno1;
-+
-+ if (!REG_P (op0) || !REG_P (op1))
-+ return false;
-+
-+ if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
-+ return false;
-+
-+ regno0 = REGNO (op0);
-+ regno1 = REGNO (op1);
-+ if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
-+ return false;
-+
-+ if (INT_REGNO_P (regno0))
-+ return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
-+
-+ else if (INT_REGNO_P (regno1))
-+ {
-+ if (TARGET_MFPGPR && FP_REGNO_P (regno0))
-+ return true;
-+
-+ else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+/* Return true if this is a load or store quad operation. This function does
-+ not handle the atomic quad memory instructions. */
-+
-+bool
-+quad_load_store_p (rtx op0, rtx op1)
-+{
-+ bool ret;
-+
-+ if (!TARGET_QUAD_MEMORY)
-+ ret = false;
-+
-+ else if (REG_P (op0) && MEM_P (op1))
-+ ret = (quad_int_reg_operand (op0, GET_MODE (op0))
-+ && quad_memory_operand (op1, GET_MODE (op1))
-+ && !reg_overlap_mentioned_p (op0, op1));
-+
-+ else if (MEM_P (op0) && REG_P (op1))
-+ ret = (quad_memory_operand (op0, GET_MODE (op0))
-+ && quad_int_reg_operand (op1, GET_MODE (op1)));
-+
-+ else
-+ ret = false;
-+
-+ if (TARGET_DEBUG_ADDR)
-+ {
-+ fprintf (stderr, "\n========== quad_load_store, return %s\n",
-+ ret ? "true" : "false");
-+ debug_rtx (gen_rtx_SET (VOIDmode, op0, op1));
-+ }
-+
-+ return ret;
-+}
-+
- /* Given an address, return a constant offset term if one exists. */
-
- static rtx
-@@ -5170,7 +6132,12 @@
- case V4SImode:
- case V2DFmode:
- case V2DImode:
-- /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
-+ case V1TImode:
-+ case TImode:
-+ /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
-+ TImode is not a vector mode, if we want to use the VSX registers to
-+ move it around, we need to restrict ourselves to reg+reg
-+ addressing. */
- if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
- return false;
- break;
-@@ -5184,6 +6151,13 @@
- return false;
- break;
-
-+ case SDmode:
-+ /* If we can do direct load/stores of SDmode, restrict it to reg+reg
-+ addressing for the LFIWZX and STFIWX instructions. */
-+ if (TARGET_NO_SDMODE_STACK)
-+ return false;
-+ break;
-+
- default:
- break;
- }
-@@ -5211,8 +6185,8 @@
- && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
- }
-
--/* Return true if memory accesses to OP are known to never straddle
-- a 32k boundary. */
-+/* Return true if a MODE sized memory accesses to OP plus OFFSET
-+ is known to not straddle a 32k boundary. */
-
- static bool
- offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
-@@ -5219,15 +6193,16 @@
- enum machine_mode mode)
- {
- tree decl, type;
-- unsigned HOST_WIDE_INT dsize, dalign;
-+ unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
-
- if (GET_CODE (op) != SYMBOL_REF)
- return false;
-
-+ dsize = GET_MODE_SIZE (mode);
- decl = SYMBOL_REF_DECL (op);
- if (!decl)
- {
-- if (GET_MODE_SIZE (mode) == 0)
-+ if (dsize == 0)
- return false;
-
- /* -fsection-anchors loses the original SYMBOL_REF_DECL when
-@@ -5234,68 +6209,78 @@
- replacing memory addresses with an anchor plus offset. We
- could find the decl by rummaging around in the block->objects
- VEC for the given offset but that seems like too much work. */
-- dalign = 1;
-+ dalign = BITS_PER_UNIT;
- if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
- && SYMBOL_REF_ANCHOR_P (op)
- && SYMBOL_REF_BLOCK (op) != NULL)
- {
- struct object_block *block = SYMBOL_REF_BLOCK (op);
-- HOST_WIDE_INT lsb, mask;
-
-- /* Given the alignment of the block.. */
- dalign = block->alignment;
-- mask = dalign / BITS_PER_UNIT - 1;
--
-- /* ..and the combined offset of the anchor and any offset
-- to this block object.. */
- offset += SYMBOL_REF_BLOCK_OFFSET (op);
-- lsb = offset & -offset;
-+ }
-+ else if (CONSTANT_POOL_ADDRESS_P (op))
-+ {
-+ /* It would be nice to have get_pool_align().. */
-+ enum machine_mode cmode = get_pool_mode (op);
-
-- /* ..find how many bits of the alignment we know for the
-- object. */
-- mask &= lsb - 1;
-- dalign = mask + 1;
-+ dalign = GET_MODE_ALIGNMENT (cmode);
- }
-- return dalign >= GET_MODE_SIZE (mode);
- }
--
-- if (DECL_P (decl))
-+ else if (DECL_P (decl))
- {
-- if (TREE_CODE (decl) == FUNCTION_DECL)
-- return true;
-+ dalign = DECL_ALIGN (decl);
-
-- if (!DECL_SIZE_UNIT (decl))
-- return false;
-+ if (dsize == 0)
-+ {
-+ /* Allow BLKmode when the entire object is known to not
-+ cross a 32k boundary. */
-+ if (!DECL_SIZE_UNIT (decl))
-+ return false;
-
-- if (!host_integerp (DECL_SIZE_UNIT (decl), 1))
-- return false;
-+ if (!host_integerp (DECL_SIZE_UNIT (decl), 1))
-+ return false;
-
-- dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);
-- if (dsize > 32768)
-- return false;
-+ dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);
-+ if (dsize > 32768)
-+ return false;
-
-- dalign = DECL_ALIGN_UNIT (decl);
-- return dalign >= dsize;
-+ return dalign / BITS_PER_UNIT >= dsize;
-+ }
- }
-+ else
-+ {
-+ type = TREE_TYPE (decl);
-
-- type = TREE_TYPE (decl);
-+ dalign = TYPE_ALIGN (type);
-+ if (CONSTANT_CLASS_P (decl))
-+ dalign = CONSTANT_ALIGNMENT (decl, dalign);
-+ else
-+ dalign = DATA_ALIGNMENT (decl, dalign);
-
-- if (TREE_CODE (decl) == STRING_CST)
-- dsize = TREE_STRING_LENGTH (decl);
-- else if (TYPE_SIZE_UNIT (type)
-- && host_integerp (TYPE_SIZE_UNIT (type), 1))
-- dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
-- else
-- return false;
-- if (dsize > 32768)
-- return false;
-+ if (dsize == 0)
-+ {
-+ /* BLKmode, check the entire object. */
-+ if (TREE_CODE (decl) == STRING_CST)
-+ dsize = TREE_STRING_LENGTH (decl);
-+ else if (TYPE_SIZE_UNIT (type)
-+ && host_integerp (TYPE_SIZE_UNIT (type), 1))
-+ dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
-+ else
-+ return false;
-+ if (dsize > 32768)
-+ return false;
-
-- dalign = TYPE_ALIGN (type);
-- if (CONSTANT_CLASS_P (decl))
-- dalign = CONSTANT_ALIGNMENT (decl, dalign);
-- else
-- dalign = DATA_ALIGNMENT (decl, dalign);
-- dalign /= BITS_PER_UNIT;
-+ return dalign / BITS_PER_UNIT >= dsize;
-+ }
-+ }
-+
-+ /* Find how many bits of the alignment we know for this access. */
-+ mask = dalign / BITS_PER_UNIT - 1;
-+ lsb = offset & -offset;
-+ mask &= lsb - 1;
-+ dalign = mask + 1;
-+
- return dalign >= dsize;
- }
-
-@@ -5387,7 +6372,7 @@
- return false;
- if (!reg_offset_addressing_ok_p (mode))
- return virtual_stack_registers_memory_p (x);
-- if (legitimate_constant_pool_address_p (x, mode, strict))
-+ if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
- return true;
- if (GET_CODE (XEXP (x, 1)) != CONST_INT)
- return false;
-@@ -5416,7 +6401,7 @@
-
- /* If we are using VSX scalar loads, restrict ourselves to reg+reg
- addressing. */
-- if (mode == DFmode && VECTOR_MEM_VSX_P (DFmode))
-+ if (VECTOR_MEM_VSX_P (mode))
- return false;
-
- if (!worst_case)
-@@ -5428,12 +6413,14 @@
- break;
-
- case TFmode:
-- case TDmode:
-- case TImode:
- if (TARGET_E500_DOUBLE)
- return (SPE_CONST_OFFSET_OK (offset)
- && SPE_CONST_OFFSET_OK (offset + 8));
-+ /* fall through */
-
-+ case TDmode:
-+ case TImode:
-+ case PTImode:
- extra = 8;
- if (!worst_case)
- break;
-@@ -5526,9 +6513,21 @@
-
- if (TARGET_ELF || TARGET_MACHO)
- {
-- if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
-+ bool large_toc_ok;
-+
-+ if (DEFAULT_ABI == ABI_V4 && flag_pic)
- return false;
-- if (TARGET_TOC)
-+ /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
-+ push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
-+ recognizes some LO_SUM addresses as valid although this
-+ function says opposite. In most cases, LRA through different
-+ transformations can generate correct code for address reloads.
-+ It can not manage only some LO_SUM cases. So we need to add
-+ code analogous to one in rs6000_legitimize_reload_address for
-+ LOW_SUM here saying that some addresses are still valid. */
-+ large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
-+ && small_toc_ref (x, VOIDmode));
-+ if (TARGET_TOC && ! large_toc_ok)
- return false;
- if (GET_MODE_NUNITS (mode) != 1)
- return false;
-@@ -5538,7 +6537,7 @@
- && (mode == DFmode || mode == DDmode)))
- return false;
-
-- return CONSTANT_P (x);
-+ return CONSTANT_P (x) || large_toc_ok;
- }
-
- return false;
-@@ -5582,8 +6581,11 @@
- if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
- return force_reg (Pmode, XEXP (x, 0));
-
-+ /* For TImode with load/store quad, restrict addresses to just a single
-+ pointer, so it works with both GPRs and VSX registers. */
- /* Make sure both operands are registers. */
-- else if (GET_CODE (x) == PLUS)
-+ else if (GET_CODE (x) == PLUS
-+ && (mode != TImode || !TARGET_QUAD_MEMORY))
- return gen_rtx_PLUS (Pmode,
- force_reg (Pmode, XEXP (x, 0)),
- force_reg (Pmode, XEXP (x, 1)));
-@@ -5603,11 +6605,12 @@
- case TFmode:
- case TDmode:
- case TImode:
-+ case PTImode:
- /* As in legitimate_offset_address_p we do not assume
- worst-case. The mode here is just a hint as to the registers
- used. A TImode is usually in gprs, but may actually be in
- fprs. Leave worst-case scenario for reload to handle via
-- insn constraints. */
-+ insn constraints. PTImode is only GPRs. */
- extra = 8;
- break;
- default:
-@@ -6099,10 +7102,13 @@
- 1, const0_rtx, Pmode);
-
- r3 = gen_rtx_REG (Pmode, 3);
-- if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
-- insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
-- else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
-- insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ {
-+ if (TARGET_64BIT)
-+ insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
-+ else
-+ insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
-+ }
- else if (DEFAULT_ABI == ABI_V4)
- insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
- else
-@@ -6121,10 +7127,13 @@
- 1, const0_rtx, Pmode);
-
- r3 = gen_rtx_REG (Pmode, 3);
-- if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
-- insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
-- else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
-- insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ {
-+ if (TARGET_64BIT)
-+ insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
-+ else
-+ insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
-+ }
- else if (DEFAULT_ABI == ABI_V4)
- insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
- else
-@@ -6239,7 +7248,6 @@
- && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
- get_pool_mode (sym)))
- || (TARGET_CMODEL == CMODEL_MEDIUM
-- && !CONSTANT_POOL_ADDRESS_P (sym)
- && SYMBOL_REF_LOCAL_P (sym)));
- }
-
-@@ -6338,7 +7346,7 @@
- && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
- || mode == DDmode || mode == TDmode
- || mode == DImode))
-- && VECTOR_MEM_NONE_P (mode))
-+ && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
- {
- HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
- HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
-@@ -6369,7 +7377,7 @@
-
- if (GET_CODE (x) == SYMBOL_REF
- && reg_offset_p
-- && VECTOR_MEM_NONE_P (mode)
-+ && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
- && !SPE_VECTOR_MODE (mode)
- #if TARGET_MACHO
- && DEFAULT_ABI == ABI_DARWIN
-@@ -6395,6 +7403,8 @@
- mem is sufficiently aligned. */
- && mode != TFmode
- && mode != TDmode
-+ && (mode != TImode || !TARGET_VSX_TIMODE)
-+ && mode != PTImode
- && (mode != DImode || TARGET_POWERPC64)
- && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
- || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
-@@ -6515,15 +7525,9 @@
- return 0;
- if (legitimate_indirect_address_p (x, reg_ok_strict))
- return 1;
-- if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
-- && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
-- && !SPE_VECTOR_MODE (mode)
-- && mode != TFmode
-- && mode != TDmode
-- /* Restrict addressing for DI because of our SUBREG hackery. */
-- && !(TARGET_E500_DOUBLE
-- && (mode == DFmode || mode == DDmode || mode == DImode))
-- && TARGET_UPDATE
-+ if (TARGET_UPDATE
-+ && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
-+ && mode_supports_pre_incdec_p (mode)
- && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
- return 1;
- if (virtual_stack_registers_memory_p (x))
-@@ -6531,8 +7535,16 @@
- if (reg_offset_p && legitimate_small_data_p (mode, x))
- return 1;
- if (reg_offset_p
-- && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))
-+ && legitimate_constant_pool_address_p (x, mode,
-+ reg_ok_strict || lra_in_progress))
- return 1;
-+ /* For TImode, if we have load/store quad and TImode in VSX registers, only
-+ allow register indirect addresses. This will allow the values to go in
-+ either GPRs or VSX registers without reloading. The vector types would
-+ tend to go into VSX registers, so we allow REG+REG, while TImode seems
-+ somewhat split, in that some uses are GPR based, and some VSX based. */
-+ if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE)
-+ return 0;
- /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
- if (! reg_ok_strict
- && reg_offset_p
-@@ -6544,8 +7556,7 @@
- return 1;
- if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
- return 1;
-- if (mode != TImode
-- && mode != TFmode
-+ if (mode != TFmode
- && mode != TDmode
- && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
- || TARGET_POWERPC64
-@@ -6552,23 +7563,13 @@
- || (mode != DFmode && mode != DDmode)
- || (TARGET_E500_DOUBLE && mode != DDmode))
- && (TARGET_POWERPC64 || mode != DImode)
-+ && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
-+ && mode != PTImode
- && !avoiding_indexed_address_p (mode)
- && legitimate_indexed_address_p (x, reg_ok_strict))
- return 1;
-- if (GET_CODE (x) == PRE_MODIFY
-- && mode != TImode
-- && mode != TFmode
-- && mode != TDmode
-- && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
-- || TARGET_POWERPC64
-- || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
-- && (TARGET_POWERPC64 || mode != DImode)
-- && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
-- && !SPE_VECTOR_MODE (mode)
-- /* Restrict addressing for DI because of our SUBREG hackery. */
-- && !(TARGET_E500_DOUBLE
-- && (mode == DFmode || mode == DDmode || mode == DImode))
-- && TARGET_UPDATE
-+ if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
-+ && mode_supports_pre_modify_p (mode)
- && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
- && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
- reg_ok_strict, false)
-@@ -6589,10 +7590,13 @@
- bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
- fprintf (stderr,
- "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
-- "strict = %d, code = %s\n",
-+ "strict = %d, reload = %s, code = %s\n",
- ret ? "true" : "false",
- GET_MODE_NAME (mode),
- reg_ok_strict,
-+ (reload_completed
-+ ? "after"
-+ : (reload_in_progress ? "progress" : "before")),
- GET_RTX_NAME (GET_CODE (x)));
- debug_rtx (x);
-
-@@ -6758,7 +7762,7 @@
-
- /* The TOC register is not killed across calls in a way that is
- visible to the compiler. */
-- if (DEFAULT_ABI == ABI_AIX)
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- call_really_used_regs[2] = 0;
-
- if (DEFAULT_ABI == ABI_V4
-@@ -6818,6 +7822,7 @@
- fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
- }
- }
-+
-
- /* Try to output insns to set TARGET equal to the constant C if it can
- be done in less than N insns. Do all computations in MODE.
-@@ -7006,7 +8011,7 @@
- }
-
- /* Helper for the following. Get rid of [r+r] memory refs
-- in cases where it won't work (TImode, TFmode, TDmode). */
-+ in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
-
- static void
- rs6000_eliminate_indexed_memrefs (rtx operands[2])
-@@ -7031,6 +8036,131 @@
- copy_addr_to_reg (XEXP (operands[1], 0)));
- }
-
-+/* Generate a vector of constants to permute MODE for a little-endian
-+ storage operation by swapping the two halves of a vector. */
-+static rtvec
-+rs6000_const_vec (enum machine_mode mode)
-+{
-+ int i, subparts;
-+ rtvec v;
-+
-+ switch (mode)
-+ {
-+ case V1TImode:
-+ subparts = 1;
-+ break;
-+ case V2DFmode:
-+ case V2DImode:
-+ subparts = 2;
-+ break;
-+ case V4SFmode:
-+ case V4SImode:
-+ subparts = 4;
-+ break;
-+ case V8HImode:
-+ subparts = 8;
-+ break;
-+ case V16QImode:
-+ subparts = 16;
-+ break;
-+ default:
-+ gcc_unreachable();
-+ }
-+
-+ v = rtvec_alloc (subparts);
-+
-+ for (i = 0; i < subparts / 2; ++i)
-+ RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
-+ for (i = subparts / 2; i < subparts; ++i)
-+ RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
-+
-+ return v;
-+}
-+
-+/* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
-+ for a VSX load or store operation. */
-+rtx
-+rs6000_gen_le_vsx_permute (rtx source, enum machine_mode mode)
-+{
-+ rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
-+ return gen_rtx_VEC_SELECT (mode, source, par);
-+}
-+
-+/* Emit a little-endian load from vector memory location SOURCE to VSX
-+ register DEST in mode MODE. The load is done with two permuting
-+ insn's that represent an lxvd2x and xxpermdi. */
-+void
-+rs6000_emit_le_vsx_load (rtx dest, rtx source, enum machine_mode mode)
-+{
-+ rtx tmp, permute_mem, permute_reg;
-+
-+ /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
-+ V1TImode). */
-+ if (mode == TImode || mode == V1TImode)
-+ {
-+ mode = V2DImode;
-+ dest = gen_lowpart (V2DImode, dest);
-+ source = adjust_address (source, V2DImode, 0);
-+ }
-+
-+ tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
-+ permute_mem = rs6000_gen_le_vsx_permute (source, mode);
-+ permute_reg = rs6000_gen_le_vsx_permute (tmp, mode);
-+ emit_insn (gen_rtx_SET (VOIDmode, tmp, permute_mem));
-+ emit_insn (gen_rtx_SET (VOIDmode, dest, permute_reg));
-+}
-+
-+/* Emit a little-endian store to vector memory location DEST from VSX
-+ register SOURCE in mode MODE. The store is done with two permuting
-+ insn's that represent an xxpermdi and an stxvd2x. */
-+void
-+rs6000_emit_le_vsx_store (rtx dest, rtx source, enum machine_mode mode)
-+{
-+ rtx tmp, permute_src, permute_tmp;
-+
-+ /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
-+ V1TImode). */
-+ if (mode == TImode || mode == V1TImode)
-+ {
-+ mode = V2DImode;
-+ dest = adjust_address (dest, V2DImode, 0);
-+ source = gen_lowpart (V2DImode, source);
-+ }
-+
-+ tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
-+ permute_src = rs6000_gen_le_vsx_permute (source, mode);
-+ permute_tmp = rs6000_gen_le_vsx_permute (tmp, mode);
-+ emit_insn (gen_rtx_SET (VOIDmode, tmp, permute_src));
-+ emit_insn (gen_rtx_SET (VOIDmode, dest, permute_tmp));
-+}
-+
-+/* Emit a sequence representing a little-endian VSX load or store,
-+ moving data from SOURCE to DEST in mode MODE. This is done
-+ separately from rs6000_emit_move to ensure it is called only
-+ during expand. LE VSX loads and stores introduced later are
-+ handled with a split. The expand-time RTL generation allows
-+ us to optimize away redundant pairs of register-permutes. */
-+void
-+rs6000_emit_le_vsx_move (rtx dest, rtx source, enum machine_mode mode)
-+{
-+ gcc_assert (!BYTES_BIG_ENDIAN
-+ && VECTOR_MEM_VSX_P (mode)
-+ && !gpr_or_gpr_p (dest, source)
-+ && (MEM_P (source) ^ MEM_P (dest)));
-+
-+ if (MEM_P (source))
-+ {
-+ gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
-+ rs6000_emit_le_vsx_load (dest, source, mode);
-+ }
-+ else
-+ {
-+ if (!REG_P (source))
-+ source = force_reg (mode, source);
-+ rs6000_emit_le_vsx_store (dest, source, mode);
-+ }
-+}
-+
- /* Emit a move from SOURCE to DEST in mode MODE. */
- void
- rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
-@@ -7149,8 +8279,71 @@
- cfun->machine->sdmode_stack_slot =
- eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
-
-+
-+ if (lra_in_progress
-+ && mode == SDmode
-+ && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
-+ && reg_preferred_class (REGNO (operands[0])) == NO_REGS
-+ && (REG_P (operands[1])
-+ || (GET_CODE (operands[1]) == SUBREG
-+ && REG_P (SUBREG_REG (operands[1])))))
-+ {
-+ int regno = REGNO (GET_CODE (operands[1]) == SUBREG
-+ ? SUBREG_REG (operands[1]) : operands[1]);
-+ enum reg_class cl;
-+
-+ if (regno >= FIRST_PSEUDO_REGISTER)
-+ {
-+ cl = reg_preferred_class (regno);
-+ gcc_assert (cl != NO_REGS);
-+ regno = ira_class_hard_regs[cl][0];
-+ }
-+ if (FP_REGNO_P (regno))
-+ {
-+ if (GET_MODE (operands[0]) != DDmode)
-+ operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
-+ emit_insn (gen_movsd_store (operands[0], operands[1]));
-+ }
-+ else if (INT_REGNO_P (regno))
-+ emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
-+ else
-+ gcc_unreachable();
-+ return;
-+ }
-+ if (lra_in_progress
-+ && mode == SDmode
-+ && (REG_P (operands[0])
-+ || (GET_CODE (operands[0]) == SUBREG
-+ && REG_P (SUBREG_REG (operands[0]))))
-+ && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
-+ && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
-+ {
-+ int regno = REGNO (GET_CODE (operands[0]) == SUBREG
-+ ? SUBREG_REG (operands[0]) : operands[0]);
-+ enum reg_class cl;
-+
-+ if (regno >= FIRST_PSEUDO_REGISTER)
-+ {
-+ cl = reg_preferred_class (regno);
-+ gcc_assert (cl != NO_REGS);
-+ regno = ira_class_hard_regs[cl][0];
-+ }
-+ if (FP_REGNO_P (regno))
-+ {
-+ if (GET_MODE (operands[1]) != DDmode)
-+ operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
-+ emit_insn (gen_movsd_load (operands[0], operands[1]));
-+ }
-+ else if (INT_REGNO_P (regno))
-+ emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
-+ else
-+ gcc_unreachable();
-+ return;
-+ }
-+
- if (reload_in_progress
- && mode == SDmode
-+ && cfun->machine->sdmode_stack_slot != NULL_RTX
- && MEM_P (operands[0])
- && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
- && REG_P (operands[1]))
-@@ -7163,7 +8356,9 @@
- }
- else if (INT_REGNO_P (REGNO (operands[1])))
- {
-- rtx mem = adjust_address_nv (operands[0], mode, 4);
-+ rtx mem = operands[0];
-+ if (BYTES_BIG_ENDIAN)
-+ mem = adjust_address_nv (mem, mode, 4);
- mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
- emit_insn (gen_movsd_hardfloat (mem, operands[1]));
- }
-@@ -7175,6 +8370,7 @@
- && mode == SDmode
- && REG_P (operands[0])
- && MEM_P (operands[1])
-+ && cfun->machine->sdmode_stack_slot != NULL_RTX
- && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
- {
- if (FP_REGNO_P (REGNO (operands[0])))
-@@ -7185,7 +8381,9 @@
- }
- else if (INT_REGNO_P (REGNO (operands[0])))
- {
-- rtx mem = adjust_address_nv (operands[1], mode, 4);
-+ rtx mem = operands[1];
-+ if (BYTES_BIG_ENDIAN)
-+ mem = adjust_address_nv (mem, mode, 4);
- mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
- emit_insn (gen_movsd_hardfloat (operands[0], mem));
- }
-@@ -7230,6 +8428,7 @@
- case V1DImode:
- case V2DFmode:
- case V2DImode:
-+ case V1TImode:
- if (CONSTANT_P (operands[1])
- && !easy_vector_constant (operands[1], mode))
- operands[1] = force_const_mem (mode, operands[1]);
-@@ -7388,6 +8587,11 @@
- break;
-
- case TImode:
-+ if (!VECTOR_MEM_VSX_P (TImode))
-+ rs6000_eliminate_indexed_memrefs (operands);
-+ break;
-+
-+ case PTImode:
- rs6000_eliminate_indexed_memrefs (operands);
- break;
-
-@@ -7426,18 +8630,231 @@
- }
-
- /* Nonzero if we can use a floating-point register to pass this arg. */
--#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
-+#define USE_FP_FOR_ARG_P(CUM,MODE) \
- (SCALAR_FLOAT_MODE_P (MODE) \
- && (CUM)->fregno <= FP_ARG_MAX_REG \
- && TARGET_HARD_FLOAT && TARGET_FPRS)
-
- /* Nonzero if we can use an AltiVec register to pass this arg. */
--#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
-+#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
- (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
- && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
- && TARGET_ALTIVEC_ABI \
- && (NAMED))
-
-+/* Walk down the type tree of TYPE counting consecutive base elements.
-+ If *MODEP is VOIDmode, then set it to the first valid floating point
-+ or vector type. If a non-floating point or vector type is found, or
-+ if a floating point or vector type that doesn't match a non-VOIDmode
-+ *MODEP is found, then return -1, otherwise return the count in the
-+ sub-tree. */
-+
-+static int
-+rs6000_aggregate_candidate (const_tree type, enum machine_mode *modep)
-+{
-+ enum machine_mode mode;
-+ HOST_WIDE_INT size;
-+
-+ switch (TREE_CODE (type))
-+ {
-+ case REAL_TYPE:
-+ mode = TYPE_MODE (type);
-+ if (!SCALAR_FLOAT_MODE_P (mode))
-+ return -1;
-+
-+ if (*modep == VOIDmode)
-+ *modep = mode;
-+
-+ if (*modep == mode)
-+ return 1;
-+
-+ break;
-+
-+ case COMPLEX_TYPE:
-+ mode = TYPE_MODE (TREE_TYPE (type));
-+ if (!SCALAR_FLOAT_MODE_P (mode))
-+ return -1;
-+
-+ if (*modep == VOIDmode)
-+ *modep = mode;
-+
-+ if (*modep == mode)
-+ return 2;
-+
-+ break;
-+
-+ case VECTOR_TYPE:
-+ if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
-+ return -1;
-+
-+ /* Use V4SImode as representative of all 128-bit vector types. */
-+ size = int_size_in_bytes (type);
-+ switch (size)
-+ {
-+ case 16:
-+ mode = V4SImode;
-+ break;
-+ default:
-+ return -1;
-+ }
-+
-+ if (*modep == VOIDmode)
-+ *modep = mode;
-+
-+ /* Vector modes are considered to be opaque: two vectors are
-+ equivalent for the purposes of being homogeneous aggregates
-+ if they are the same size. */
-+ if (*modep == mode)
-+ return 1;
-+
-+ break;
-+
-+ case ARRAY_TYPE:
-+ {
-+ int count;
-+ tree index = TYPE_DOMAIN (type);
-+
-+ /* Can't handle incomplete types. */
-+ if (!COMPLETE_TYPE_P (type))
-+ return -1;
-+
-+ count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
-+ if (count == -1
-+ || !index
-+ || !TYPE_MAX_VALUE (index)
-+ || !host_integerp (TYPE_MAX_VALUE (index), 1)
-+ || !TYPE_MIN_VALUE (index)
-+ || !host_integerp (TYPE_MIN_VALUE (index), 1)
-+ || count < 0)
-+ return -1;
-+
-+ count *= (1 + tree_low_cst (TYPE_MAX_VALUE (index), 1)
-+ - tree_low_cst (TYPE_MIN_VALUE (index), 1));
-+
-+ /* There must be no padding. */
-+ if (!host_integerp (TYPE_SIZE (type), 1)
-+ || (tree_low_cst (TYPE_SIZE (type), 1)
-+ != count * GET_MODE_BITSIZE (*modep)))
-+ return -1;
-+
-+ return count;
-+ }
-+
-+ case RECORD_TYPE:
-+ {
-+ int count = 0;
-+ int sub_count;
-+ tree field;
-+
-+ /* Can't handle incomplete types. */
-+ if (!COMPLETE_TYPE_P (type))
-+ return -1;
-+
-+ for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
-+ {
-+ if (TREE_CODE (field) != FIELD_DECL)
-+ continue;
-+
-+ sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
-+ if (sub_count < 0)
-+ return -1;
-+ count += sub_count;
-+ }
-+
-+ /* There must be no padding. */
-+ if (!host_integerp (TYPE_SIZE (type), 1)
-+ || (tree_low_cst (TYPE_SIZE (type), 1)
-+ != count * GET_MODE_BITSIZE (*modep)))
-+ return -1;
-+
-+ return count;
-+ }
-+
-+ case UNION_TYPE:
-+ case QUAL_UNION_TYPE:
-+ {
-+ /* These aren't very interesting except in a degenerate case. */
-+ int count = 0;
-+ int sub_count;
-+ tree field;
-+
-+ /* Can't handle incomplete types. */
-+ if (!COMPLETE_TYPE_P (type))
-+ return -1;
-+
-+ for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
-+ {
-+ if (TREE_CODE (field) != FIELD_DECL)
-+ continue;
-+
-+ sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
-+ if (sub_count < 0)
-+ return -1;
-+ count = count > sub_count ? count : sub_count;
-+ }
-+
-+ /* There must be no padding. */
-+ if (!host_integerp (TYPE_SIZE (type), 1)
-+ || (tree_low_cst (TYPE_SIZE (type), 1)
-+ != count * GET_MODE_BITSIZE (*modep)))
-+ return -1;
-+
-+ return count;
-+ }
-+
-+ default:
-+ break;
-+ }
-+
-+ return -1;
-+}
-+
-+/* If an argument, whose type is described by TYPE and MODE, is a homogeneous
-+ float or vector aggregate that shall be passed in FP/vector registers
-+ according to the ELFv2 ABI, return the homogeneous element mode in
-+ *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
-+
-+ Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
-+
-+static bool
-+rs6000_discover_homogeneous_aggregate (enum machine_mode mode, const_tree type,
-+ enum machine_mode *elt_mode,
-+ int *n_elts)
-+{
-+ /* Note that we do not accept complex types at the top level as
-+ homogeneous aggregates; these types are handled via the
-+ targetm.calls.split_complex_arg mechanism. Complex types
-+ can be elements of homogeneous aggregates, however. */
-+ if (DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P (type))
-+ {
-+ enum machine_mode field_mode = VOIDmode;
-+ int field_count = rs6000_aggregate_candidate (type, &field_mode);
-+
-+ if (field_count > 0)
-+ {
-+ int n_regs = (SCALAR_FLOAT_MODE_P (field_mode)?
-+ (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
-+
-+ /* The ELFv2 ABI allows homogeneous aggregates to occupy
-+ up to AGGR_ARG_NUM_REG registers. */
-+ if (field_count * n_regs <= AGGR_ARG_NUM_REG)
-+ {
-+ if (elt_mode)
-+ *elt_mode = field_mode;
-+ if (n_elts)
-+ *n_elts = field_count;
-+ return true;
-+ }
-+ }
-+ }
-+
-+ if (elt_mode)
-+ *elt_mode = mode;
-+ if (n_elts)
-+ *n_elts = 1;
-+ return false;
-+}
-+
- /* Return a nonzero value to say to return the function value in
- memory, just as large structures are always returned. TYPE will be
- the data type of the value, and FNTYPE will be the type of the
-@@ -7490,6 +8907,16 @@
- /* Otherwise fall through to more conventional ABI rules. */
- }
-
-+ /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
-+ if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
-+ NULL, NULL))
-+ return false;
-+
-+ /* The ELFv2 ABI returns aggregates up to 16B in registers */
-+ if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
-+ && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
-+ return false;
-+
- if (AGGREGATE_TYPE_P (type)
- && (aix_struct_return
- || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
-@@ -7521,6 +8948,19 @@
- return false;
- }
-
-+/* Specify whether values returned in registers should be at the most
-+ significant end of a register. We want aggregates returned by
-+ value to match the way aggregates are passed to functions. */
-+
-+static bool
-+rs6000_return_in_msb (const_tree valtype)
-+{
-+ return (DEFAULT_ABI == ABI_ELFv2
-+ && BYTES_BIG_ENDIAN
-+ && AGGREGATE_TYPE_P (valtype)
-+ && FUNCTION_ARG_PADDING (TYPE_MODE (valtype), valtype) == upward);
-+}
-+
- #ifdef HAVE_AS_GNU_ATTRIBUTE
- /* Return TRUE if a call to function FNDECL may be one that
- potentially affects the function calling ABI of the object file. */
-@@ -7657,7 +9097,7 @@
- static bool
- rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
- {
-- if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
- return must_pass_in_stack_var_size (mode, type);
- else
- return must_pass_in_stack_var_size_or_pad (mode, type);
-@@ -7738,6 +9178,11 @@
- static unsigned int
- rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)
- {
-+ enum machine_mode elt_mode;
-+ int n_elts;
-+
-+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
-+
- if (DEFAULT_ABI == ABI_V4
- && (GET_MODE_SIZE (mode) == 8
- || (TARGET_HARD_FLOAT
-@@ -7749,12 +9194,13 @@
- && int_size_in_bytes (type) >= 8
- && int_size_in_bytes (type) < 16))
- return 64;
-- else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
-+ else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
- || (type && TREE_CODE (type) == VECTOR_TYPE
- && int_size_in_bytes (type) >= 16))
- return 128;
-- else if (TARGET_MACHO
-- && rs6000_darwin64_abi
-+ else if (((TARGET_MACHO && rs6000_darwin64_abi)
-+ || DEFAULT_ABI == ABI_ELFv2
-+ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
- && mode == BLKmode
- && type && TYPE_ALIGN (type) > 64)
- return 128;
-@@ -7762,6 +9208,16 @@
- return PARM_BOUNDARY;
- }
-
-+/* The offset in words to the start of the parameter save area. */
-+
-+static unsigned int
-+rs6000_parm_offset (void)
-+{
-+ return (DEFAULT_ABI == ABI_V4 ? 2
-+ : DEFAULT_ABI == ABI_ELFv2 ? 4
-+ : 6);
-+}
-+
- /* For a function parm of MODE and TYPE, return the starting word in
- the parameter area. NWORDS of the parameter area are already used. */
-
-@@ -7770,11 +9226,9 @@
- unsigned int nwords)
- {
- unsigned int align;
-- unsigned int parm_offset;
-
- align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
-- parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
-- return nwords + (-(parm_offset + nwords) & align);
-+ return nwords + (-(rs6000_parm_offset () + nwords) & align);
- }
-
- /* Compute the size (in words) of a function argument. */
-@@ -7881,7 +9335,7 @@
-
- if (TREE_CODE (ftype) == RECORD_TYPE)
- rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
-- else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
-+ else if (USE_FP_FOR_ARG_P (cum, mode))
- {
- unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
- rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
-@@ -7922,7 +9376,7 @@
- else
- cum->words += n_fpregs;
- }
-- else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
-+ else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
- {
- rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
- cum->vregno++;
-@@ -7959,6 +9413,11 @@
- rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
- const_tree type, bool named, int depth)
- {
-+ enum machine_mode elt_mode;
-+ int n_elts;
-+
-+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
-+
- /* Only tick off an argument if we're not recursing. */
- if (depth == 0)
- cum->nargs_prototype--;
-@@ -7979,15 +9438,16 @@
- #endif
-
- if (TARGET_ALTIVEC_ABI
-- && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
-+ && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
- || (type && TREE_CODE (type) == VECTOR_TYPE
- && int_size_in_bytes (type) == 16)))
- {
- bool stack = false;
-
-- if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
-+ if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
- {
-- cum->vregno++;
-+ cum->vregno += n_elts;
-+
- if (!TARGET_ALTIVEC)
- error ("cannot pass argument in vector register because"
- " altivec instructions are disabled, use -maltivec"
-@@ -7996,7 +9456,8 @@
- /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
- even if it is going to be passed in a vector register.
- Darwin does the same for variable-argument functions. */
-- if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
-+ if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ && TARGET_64BIT)
- || (cum->stdarg && DEFAULT_ABI != ABI_V4))
- stack = true;
- }
-@@ -8007,15 +9468,13 @@
- {
- int align;
-
-- /* Vector parameters must be 16-byte aligned. This places
-- them at 2 mod 4 in terms of words in 32-bit mode, since
-- the parameter save area starts at offset 24 from the
-- stack. In 64-bit mode, they just have to start on an
-- even word, since the parameter save area is 16-byte
-- aligned. Space for GPRs is reserved even if the argument
-- will be passed in memory. */
-+ /* Vector parameters must be 16-byte aligned. In 32-bit
-+ mode this means we need to take into account the offset
-+ to the parameter save area. In 64-bit mode, they just
-+ have to start on an even word, since the parameter save
-+ area is 16-byte aligned. */
- if (TARGET_32BIT)
-- align = (2 - cum->words) & 3;
-+ align = -(rs6000_parm_offset () + cum->words) & 3;
- else
- align = cum->words & 1;
- cum->words += align + rs6000_arg_size (mode, type);
-@@ -8140,15 +9599,15 @@
-
- cum->words = align_words + n_words;
-
-- if (SCALAR_FLOAT_MODE_P (mode)
-+ if (SCALAR_FLOAT_MODE_P (elt_mode)
- && TARGET_HARD_FLOAT && TARGET_FPRS)
- {
- /* _Decimal128 must be passed in an even/odd float register pair.
- This assumes that the register number is odd when fregno is
- odd. */
-- if (mode == TDmode && (cum->fregno % 2) == 1)
-+ if (elt_mode == TDmode && (cum->fregno % 2) == 1)
- cum->fregno++;
-- cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
-+ cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
- }
-
- if (TARGET_DEBUG_ARG)
-@@ -8358,7 +9817,7 @@
-
- if (TREE_CODE (ftype) == RECORD_TYPE)
- rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
-- else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
-+ else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
- {
- unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
- #if 0
-@@ -8386,7 +9845,7 @@
- if (mode == TFmode || mode == TDmode)
- cum->fregno++;
- }
-- else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
-+ else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
- {
- rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
- rvec[(*k)++]
-@@ -8503,6 +9962,84 @@
- return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
- }
-
-+/* We have an argument of MODE and TYPE that goes into FPRs or VRs,
-+ but must also be copied into the parameter save area starting at
-+ offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
-+ to the GPRs and/or memory. Return the number of elements used. */
-+
-+static int
-+rs6000_psave_function_arg (enum machine_mode mode, const_tree type,
-+ int align_words, rtx *rvec)
-+{
-+ int k = 0;
-+
-+ if (align_words < GP_ARG_NUM_REG)
-+ {
-+ int n_words = rs6000_arg_size (mode, type);
-+
-+ if (align_words + n_words > GP_ARG_NUM_REG
-+ || mode == BLKmode
-+ || (TARGET_32BIT && TARGET_POWERPC64))
-+ {
-+ /* If this is partially on the stack, then we only
-+ include the portion actually in registers here. */
-+ enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
-+ int i = 0;
-+
-+ if (align_words + n_words > GP_ARG_NUM_REG)
-+ {
-+ /* Not all of the arg fits in gprs. Say that it goes in memory
-+ too, using a magic NULL_RTX component. Also see comment in
-+ rs6000_mixed_function_arg for why the normal
-+ function_arg_partial_nregs scheme doesn't work in this case. */
-+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
-+ }
-+
-+ do
-+ {
-+ rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
-+ rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
-+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
-+ }
-+ while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
-+ }
-+ else
-+ {
-+ /* The whole arg fits in gprs. */
-+ rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
-+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
-+ }
-+ }
-+ else
-+ {
-+ /* It's entirely in memory. */
-+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
-+ }
-+
-+ return k;
-+}
-+
-+/* RVEC is a vector of K components of an argument of mode MODE.
-+ Construct the final function_arg return value from it. */
-+
-+static rtx
-+rs6000_finish_function_arg (enum machine_mode mode, rtx *rvec, int k)
-+{
-+ gcc_assert (k >= 1);
-+
-+ /* Avoid returning a PARALLEL in the trivial cases. */
-+ if (k == 1)
-+ {
-+ if (XEXP (rvec[0], 0) == NULL_RTX)
-+ return NULL_RTX;
-+
-+ if (GET_MODE (XEXP (rvec[0], 0)) == mode)
-+ return XEXP (rvec[0], 0);
-+ }
-+
-+ return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
-+}
-+
- /* Determine where to put an argument to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-@@ -8537,6 +10074,8 @@
- {
- CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
- enum rs6000_abi abi = DEFAULT_ABI;
-+ enum machine_mode elt_mode;
-+ int n_elts;
-
- /* Return a marker to indicate whether CR1 needs to set or clear the
- bit that V.4 uses to say fp args were passed in registers.
-@@ -8563,6 +10102,8 @@
- return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
- }
-
-+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
-+
- if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
- {
- rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
-@@ -8571,33 +10112,30 @@
- /* Else fall through to usual handling. */
- }
-
-- if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
-- if (TARGET_64BIT && ! cum->prototype)
-- {
-- /* Vector parameters get passed in vector register
-- and also in GPRs or memory, in absence of prototype. */
-- int align_words;
-- rtx slot;
-- align_words = (cum->words + 1) & ~1;
-+ if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
-+ {
-+ rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
-+ rtx r, off;
-+ int i, k = 0;
-
-- if (align_words >= GP_ARG_NUM_REG)
-- {
-- slot = NULL_RTX;
-- }
-- else
-- {
-- slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
-- }
-- return gen_rtx_PARALLEL (mode,
-- gen_rtvec (2,
-- gen_rtx_EXPR_LIST (VOIDmode,
-- slot, const0_rtx),
-- gen_rtx_EXPR_LIST (VOIDmode,
-- gen_rtx_REG (mode, cum->vregno),
-- const0_rtx)));
-- }
-- else
-- return gen_rtx_REG (mode, cum->vregno);
-+ /* Do we also need to pass this argument in the parameter
-+ save area? */
-+ if (TARGET_64BIT && ! cum->prototype)
-+ {
-+ int align_words = (cum->words + 1) & ~1;
-+ k = rs6000_psave_function_arg (mode, type, align_words, rvec);
-+ }
-+
-+ /* Describe where this argument goes in the vector registers. */
-+ for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
-+ {
-+ r = gen_rtx_REG (elt_mode, cum->vregno + i);
-+ off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
-+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
-+ }
-+
-+ return rs6000_finish_function_arg (mode, rvec, k);
-+ }
- else if (TARGET_ALTIVEC_ABI
- && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
- || (type && TREE_CODE (type) == VECTOR_TYPE
-@@ -8612,13 +10150,13 @@
- int align, align_words, n_words;
- enum machine_mode part_mode;
-
-- /* Vector parameters must be 16-byte aligned. This places them at
-- 2 mod 4 in terms of words in 32-bit mode, since the parameter
-- save area starts at offset 24 from the stack. In 64-bit mode,
-- they just have to start on an even word, since the parameter
-- save area is 16-byte aligned. */
-+ /* Vector parameters must be 16-byte aligned. In 32-bit
-+ mode this means we need to take into account the offset
-+ to the parameter save area. In 64-bit mode, they just
-+ have to start on an even word, since the parameter save
-+ area is 16-byte aligned. */
- if (TARGET_32BIT)
-- align = (2 - cum->words) & 3;
-+ align = -(rs6000_parm_offset () + cum->words) & 3;
- else
- align = cum->words & 1;
- align_words = cum->words + align;
-@@ -8696,92 +10234,44 @@
-
- /* _Decimal128 must be passed in an even/odd float register pair.
- This assumes that the register number is odd when fregno is odd. */
-- if (mode == TDmode && (cum->fregno % 2) == 1)
-+ if (elt_mode == TDmode && (cum->fregno % 2) == 1)
- cum->fregno++;
-
-- if (USE_FP_FOR_ARG_P (cum, mode, type))
-+ if (USE_FP_FOR_ARG_P (cum, elt_mode))
- {
-- rtx rvec[GP_ARG_NUM_REG + 1];
-- rtx r;
-- int k;
-- bool needs_psave;
-- enum machine_mode fmode = mode;
-- unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
-+ rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
-+ rtx r, off;
-+ int i, k = 0;
-+ unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
-
-- if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
-- {
-- /* Currently, we only ever need one reg here because complex
-- doubles are split. */
-- gcc_assert (cum->fregno == FP_ARG_MAX_REG
-- && (fmode == TFmode || fmode == TDmode));
-+ /* Do we also need to pass this argument in the parameter
-+ save area? */
-+ if (type && (cum->nargs_prototype <= 0
-+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ && TARGET_XL_COMPAT
-+ && align_words >= GP_ARG_NUM_REG)))
-+ k = rs6000_psave_function_arg (mode, type, align_words, rvec);
-
-- /* Long double or _Decimal128 split over regs and memory. */
-- fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
-- }
--
-- /* Do we also need to pass this arg in the parameter save
-- area? */
-- needs_psave = (type
-- && (cum->nargs_prototype <= 0
-- || (DEFAULT_ABI == ABI_AIX
-- && TARGET_XL_COMPAT
-- && align_words >= GP_ARG_NUM_REG)));
--
-- if (!needs_psave && mode == fmode)
-- return gen_rtx_REG (fmode, cum->fregno);
--
-- k = 0;
-- if (needs_psave)
-+ /* Describe where this argument goes in the fprs. */
-+ for (i = 0; i < n_elts
-+ && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
- {
-- /* Describe the part that goes in gprs or the stack.
-- This piece must come first, before the fprs. */
-- if (align_words < GP_ARG_NUM_REG)
-+ /* Check if the argument is split over registers and memory.
-+ This can only ever happen for long double or _Decimal128;
-+ complex types are handled via split_complex_arg. */
-+ enum machine_mode fmode = elt_mode;
-+ if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
- {
-- unsigned long n_words = rs6000_arg_size (mode, type);
-+ gcc_assert (fmode == TFmode || fmode == TDmode);
-+ fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
-+ }
-
-- if (align_words + n_words > GP_ARG_NUM_REG
-- || (TARGET_32BIT && TARGET_POWERPC64))
-- {
-- /* If this is partially on the stack, then we only
-- include the portion actually in registers here. */
-- enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
-- rtx off;
-- int i = 0;
-- if (align_words + n_words > GP_ARG_NUM_REG)
-- /* Not all of the arg fits in gprs. Say that it
-- goes in memory too, using a magic NULL_RTX
-- component. Also see comment in
-- rs6000_mixed_function_arg for why the normal
-- function_arg_partial_nregs scheme doesn't work
-- in this case. */
-- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
-- const0_rtx);
-- do
-- {
-- r = gen_rtx_REG (rmode,
-- GP_ARG_MIN_REG + align_words);
-- off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
-- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
-- }
-- while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
-- }
-- else
-- {
-- /* The whole arg fits in gprs. */
-- r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
-- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
-- }
-- }
-- else
-- /* It's entirely in memory. */
-- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
-+ r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
-+ off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
-+ rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
- }
-
-- /* Describe where this piece goes in the fprs. */
-- r = gen_rtx_REG (fmode, cum->fregno);
-- rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
--
-- return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
-+ return rs6000_finish_function_arg (mode, rvec, k);
- }
- else if (align_words < GP_ARG_NUM_REG)
- {
-@@ -8788,9 +10278,6 @@
- if (TARGET_32BIT && TARGET_POWERPC64)
- return rs6000_mixed_function_arg (mode, type, align_words);
-
-- if (mode == BLKmode)
-- mode = Pmode;
--
- return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
- }
- else
-@@ -8809,16 +10296,32 @@
- tree type, bool named)
- {
- CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
-+ bool passed_in_gprs = true;
- int ret = 0;
- int align_words;
-+ enum machine_mode elt_mode;
-+ int n_elts;
-
-+ rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
-+
- if (DEFAULT_ABI == ABI_V4)
- return 0;
-
-- if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
-- && cum->nargs_prototype >= 0)
-- return 0;
-+ if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
-+ {
-+ /* If we are passing this arg in the fixed parameter save area
-+ (gprs or memory) as well as VRs, we do not use the partial
-+ bytes mechanism; instead, rs6000_function_arg will return a
-+ PARALLEL including a memory element as necessary. */
-+ if (TARGET_64BIT && ! cum->prototype)
-+ return 0;
-
-+ /* Otherwise, we pass in VRs only. Check for partial copies. */
-+ passed_in_gprs = false;
-+ if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
-+ ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
-+ }
-+
- /* In this complicated case we just disable the partial_nregs code. */
- if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
- return 0;
-@@ -8825,26 +10328,30 @@
-
- align_words = rs6000_parm_start (mode, type, cum->words);
-
-- if (USE_FP_FOR_ARG_P (cum, mode, type))
-+ if (USE_FP_FOR_ARG_P (cum, elt_mode))
- {
-+ unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
-+
- /* If we are passing this arg in the fixed parameter save area
-- (gprs or memory) as well as fprs, then this function should
-- return the number of partial bytes passed in the parameter
-- save area rather than partial bytes passed in fprs. */
-+ (gprs or memory) as well as FPRs, we do not use the partial
-+ bytes mechanism; instead, rs6000_function_arg will return a
-+ PARALLEL including a memory element as necessary. */
- if (type
- && (cum->nargs_prototype <= 0
-- || (DEFAULT_ABI == ABI_AIX
-+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- && TARGET_XL_COMPAT
- && align_words >= GP_ARG_NUM_REG)))
- return 0;
-- else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
-- > FP_ARG_MAX_REG + 1)
-- ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
-- else if (cum->nargs_prototype >= 0)
-- return 0;
-+
-+ /* Otherwise, we pass in FPRs only. Check for partial copies. */
-+ passed_in_gprs = false;
-+ if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
-+ ret = ((FP_ARG_MAX_REG + 1 - cum->fregno)
-+ * MIN (8, GET_MODE_SIZE (elt_mode)));
- }
-
-- if (align_words < GP_ARG_NUM_REG
-+ if (passed_in_gprs
-+ && align_words < GP_ARG_NUM_REG
- && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
- ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
-
-@@ -8925,6 +10432,139 @@
- return 0;
- }
-
-+/* Process parameter of type TYPE after ARGS_SO_FAR parameters were
-+ already processes. Return true if the parameter must be passed
-+ (fully or partially) on the stack. */
-+
-+static bool
-+rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
-+{
-+ enum machine_mode mode;
-+ int unsignedp;
-+ rtx entry_parm;
-+
-+ /* Catch errors. */
-+ if (type == NULL || type == error_mark_node)
-+ return true;
-+
-+ /* Handle types with no storage requirement. */
-+ if (TYPE_MODE (type) == VOIDmode)
-+ return false;
-+
-+ /* Handle complex types. */
-+ if (TREE_CODE (type) == COMPLEX_TYPE)
-+ return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
-+ || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
-+
-+ /* Handle transparent aggregates. */
-+ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
-+ && TYPE_TRANSPARENT_AGGR (type))
-+ type = TREE_TYPE (first_field (type));
-+
-+ /* See if this arg was passed by invisible reference. */
-+ if (pass_by_reference (get_cumulative_args (args_so_far),
-+ TYPE_MODE (type), type, true))
-+ type = build_pointer_type (type);
-+
-+ /* Find mode as it is passed by the ABI. */
-+ unsignedp = TYPE_UNSIGNED (type);
-+ mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
-+
-+ /* If we must pass in stack, we need a stack. */
-+ if (rs6000_must_pass_in_stack (mode, type))
-+ return true;
-+
-+ /* If there is no incoming register, we need a stack. */
-+ entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
-+ if (entry_parm == NULL)
-+ return true;
-+
-+ /* Likewise if we need to pass both in registers and on the stack. */
-+ if (GET_CODE (entry_parm) == PARALLEL
-+ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
-+ return true;
-+
-+ /* Also true if we're partially in registers and partially not. */
-+ if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
-+ return true;
-+
-+ /* Update info on where next arg arrives in registers. */
-+ rs6000_function_arg_advance (args_so_far, mode, type, true);
-+ return false;
-+}
-+
-+/* Return true if FUN has no prototype, has a variable argument
-+ list, or passes any parameter in memory. */
-+
-+static bool
-+rs6000_function_parms_need_stack (tree fun)
-+{
-+ function_args_iterator args_iter;
-+ tree arg_type;
-+ CUMULATIVE_ARGS args_so_far_v;
-+ cumulative_args_t args_so_far;
-+
-+ if (!fun)
-+ /* Must be a libcall, all of which only use reg parms. */
-+ return false;
-+ if (!TYPE_P (fun))
-+ fun = TREE_TYPE (fun);
-+
-+ /* Varargs functions need the parameter save area. */
-+ if (!prototype_p (fun) || stdarg_p (fun))
-+ return true;
-+
-+ INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fun, NULL_RTX);
-+ args_so_far = pack_cumulative_args (&args_so_far_v);
-+
-+ if (aggregate_value_p (TREE_TYPE (fun), fun))
-+ {
-+ tree type = build_pointer_type (TREE_TYPE (fun));
-+ rs6000_parm_needs_stack (args_so_far, type);
-+ }
-+
-+ FOREACH_FUNCTION_ARGS (fun, arg_type, args_iter)
-+ if (rs6000_parm_needs_stack (args_so_far, arg_type))
-+ return true;
-+
-+ return false;
-+}
-+
-+/* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
-+ usually a constant depending on the ABI. However, in the ELFv2 ABI
-+ the register parameter area is optional when calling a function that
-+ has a prototype is scope, has no variable argument list, and passes
-+ all parameters in registers. */
-+
-+int
-+rs6000_reg_parm_stack_space (tree fun)
-+{
-+ int reg_parm_stack_space;
-+
-+ switch (DEFAULT_ABI)
-+ {
-+ default:
-+ reg_parm_stack_space = 0;
-+ break;
-+
-+ case ABI_AIX:
-+ case ABI_DARWIN:
-+ reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
-+ break;
-+
-+ case ABI_ELFv2:
-+ /* ??? Recomputing this every time is a bit expensive. Is there
-+ a place to cache this information? */
-+ if (rs6000_function_parms_need_stack (fun))
-+ reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
-+ else
-+ reg_parm_stack_space = 0;
-+ break;
-+ }
-+
-+ return reg_parm_stack_space;
-+}
-+
- static void
- rs6000_move_block_from_reg (int regno, rtx x, int nregs)
- {
-@@ -9306,8 +10946,10 @@
- We don't need to check for pass-by-reference because of the test above.
- We can return a simplifed answer, since we know there's no offset to add. */
-
-- if (TARGET_MACHO
-- && rs6000_darwin64_abi
-+ if (((TARGET_MACHO
-+ && rs6000_darwin64_abi)
-+ || DEFAULT_ABI == ABI_ELFv2
-+ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
- && integer_zerop (TYPE_SIZE (type)))
- {
- unsigned HOST_WIDE_INT align, boundary;
-@@ -9602,6 +11244,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -9615,6 +11258,7 @@
- #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -9633,6 +11277,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -9646,6 +11291,7 @@
- { MASK, ICODE, NAME, ENUM },
-
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -9664,6 +11310,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -9677,6 +11324,7 @@
- #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -9693,6 +11341,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -9704,6 +11353,7 @@
- #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
- { MASK, ICODE, NAME, ENUM },
-
-@@ -9725,6 +11375,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -9736,6 +11387,7 @@
- #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
-@@ -9755,6 +11407,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -9768,6 +11421,7 @@
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
- { MASK, ICODE, NAME, ENUM },
-
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -9785,6 +11439,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -9796,6 +11451,7 @@
- #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
- { MASK, ICODE, NAME, ENUM },
-@@ -9816,6 +11472,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -9829,6 +11486,7 @@
-
- #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -9846,8 +11504,9 @@
- #undef RS6000_BUILTIN_2
- #undef RS6000_BUILTIN_3
- #undef RS6000_BUILTIN_A
-+#undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
--#undef RS6000_BUILTIN_D
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -9861,6 +11520,7 @@
- #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
- #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -9871,6 +11531,7 @@
- #include "rs6000-builtin.def"
- };
-
-+/* HTM builtins. */
- #undef RS6000_BUILTIN_1
- #undef RS6000_BUILTIN_2
- #undef RS6000_BUILTIN_3
-@@ -9877,11 +11538,42 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
- #undef RS6000_BUILTIN_X
-
-+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
-+ { MASK, ICODE, NAME, ENUM },
-+
-+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
-+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
-+
-+static const struct builtin_description bdesc_htm[] =
-+{
-+#include "rs6000-builtin.def"
-+};
-+
-+#undef RS6000_BUILTIN_1
-+#undef RS6000_BUILTIN_2
-+#undef RS6000_BUILTIN_3
-+#undef RS6000_BUILTIN_A
-+#undef RS6000_BUILTIN_D
-+#undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
-+#undef RS6000_BUILTIN_P
-+#undef RS6000_BUILTIN_Q
-+#undef RS6000_BUILTIN_S
-+
- /* Return true if a builtin function is overloaded. */
- bool
- rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
-@@ -10189,7 +11881,101 @@
- return target;
- }
-
-+/* Return a constant vector for use as a little-endian permute control vector
-+ to reverse the order of elements of the given vector mode. */
- static rtx
-+swap_selector_for_mode (enum machine_mode mode)
-+{
-+ /* These are little endian vectors, so their elements are reversed
-+ from what you would normally expect for a permute control vector. */
-+ unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
-+ unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
-+ unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
-+ unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-+ unsigned int *swaparray, i;
-+ rtx perm[16];
-+
-+ switch (mode)
-+ {
-+ case V2DFmode:
-+ case V2DImode:
-+ swaparray = swap2;
-+ break;
-+ case V4SFmode:
-+ case V4SImode:
-+ swaparray = swap4;
-+ break;
-+ case V8HImode:
-+ swaparray = swap8;
-+ break;
-+ case V16QImode:
-+ swaparray = swap16;
-+ break;
-+ default:
-+ gcc_unreachable ();
-+ }
-+
-+ for (i = 0; i < 16; ++i)
-+ perm[i] = GEN_INT (swaparray[i]);
-+
-+ return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
-+}
-+
-+/* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
-+ with -maltivec=be specified. Issue the load followed by an element-reversing
-+ permute. */
-+void
-+altivec_expand_lvx_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)
-+{
-+ rtx tmp = gen_reg_rtx (mode);
-+ rtx load = gen_rtx_SET (VOIDmode, tmp, op1);
-+ rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
-+ rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));
-+ rtx sel = swap_selector_for_mode (mode);
-+ rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);
-+
-+ gcc_assert (REG_P (op0));
-+ emit_insn (par);
-+ emit_insn (gen_rtx_SET (VOIDmode, op0, vperm));
-+}
-+
-+/* Generate code for a "stvx" or "stvxl" built-in for a little endian target
-+ with -maltivec=be specified. Issue the store preceded by an element-reversing
-+ permute. */
-+void
-+altivec_expand_stvx_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)
-+{
-+ rtx tmp = gen_reg_rtx (mode);
-+ rtx store = gen_rtx_SET (VOIDmode, op0, tmp);
-+ rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
-+ rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));
-+ rtx sel = swap_selector_for_mode (mode);
-+ rtx vperm;
-+
-+ gcc_assert (REG_P (op1));
-+ vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
-+ emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));
-+ emit_insn (par);
-+}
-+
-+/* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
-+ specified. Issue the store preceded by an element-reversing permute. */
-+void
-+altivec_expand_stvex_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)
-+{
-+ enum machine_mode inner_mode = GET_MODE_INNER (mode);
-+ rtx tmp = gen_reg_rtx (mode);
-+ rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);
-+ rtx sel = swap_selector_for_mode (mode);
-+ rtx vperm;
-+
-+ gcc_assert (REG_P (op1));
-+ vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
-+ emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));
-+ emit_insn (gen_rtx_SET (VOIDmode, op0, stvx));
-+}
-+
-+static rtx
- altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
- {
- rtx pat, addr;
-@@ -10351,7 +12137,198 @@
- return NULL_RTX;
- }
-
-+/* Return the appropriate SPR number associated with the given builtin. */
-+static inline HOST_WIDE_INT
-+htm_spr_num (enum rs6000_builtins code)
-+{
-+ if (code == HTM_BUILTIN_GET_TFHAR
-+ || code == HTM_BUILTIN_SET_TFHAR)
-+ return TFHAR_SPR;
-+ else if (code == HTM_BUILTIN_GET_TFIAR
-+ || code == HTM_BUILTIN_SET_TFIAR)
-+ return TFIAR_SPR;
-+ else if (code == HTM_BUILTIN_GET_TEXASR
-+ || code == HTM_BUILTIN_SET_TEXASR)
-+ return TEXASR_SPR;
-+ gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
-+ || code == HTM_BUILTIN_SET_TEXASRU);
-+ return TEXASRU_SPR;
-+}
-+
-+/* Return the appropriate SPR regno associated with the given builtin. */
-+static inline HOST_WIDE_INT
-+htm_spr_regno (enum rs6000_builtins code)
-+{
-+ if (code == HTM_BUILTIN_GET_TFHAR
-+ || code == HTM_BUILTIN_SET_TFHAR)
-+ return TFHAR_REGNO;
-+ else if (code == HTM_BUILTIN_GET_TFIAR
-+ || code == HTM_BUILTIN_SET_TFIAR)
-+ return TFIAR_REGNO;
-+ gcc_assert (code == HTM_BUILTIN_GET_TEXASR
-+ || code == HTM_BUILTIN_SET_TEXASR
-+ || code == HTM_BUILTIN_GET_TEXASRU
-+ || code == HTM_BUILTIN_SET_TEXASRU);
-+ return TEXASR_REGNO;
-+}
-+
-+/* Return the correct ICODE value depending on whether we are
-+ setting or reading the HTM SPRs. */
-+static inline enum insn_code
-+rs6000_htm_spr_icode (bool nonvoid)
-+{
-+ if (nonvoid)
-+ return (TARGET_64BIT) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
-+ else
-+ return (TARGET_64BIT) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
-+}
-+
-+/* Expand the HTM builtin in EXP and store the result in TARGET.
-+ Store true in *EXPANDEDP if we found a builtin to expand. */
- static rtx
-+htm_expand_builtin (tree exp, rtx target, bool * expandedp)
-+{
-+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
-+ bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
-+ enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
-+ const struct builtin_description *d;
-+ size_t i;
-+
-+ *expandedp = false;
-+
-+ /* Expand the HTM builtins. */
-+ d = bdesc_htm;
-+ for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
-+ if (d->code == fcode)
-+ {
-+ rtx op[MAX_HTM_OPERANDS], pat;
-+ int nopnds = 0;
-+ tree arg;
-+ call_expr_arg_iterator iter;
-+ unsigned attr = rs6000_builtin_info[fcode].attr;
-+ enum insn_code icode = d->icode;
-+
-+ if (attr & RS6000_BTC_SPR)
-+ icode = rs6000_htm_spr_icode (nonvoid);
-+
-+ if (nonvoid)
-+ {
-+ enum machine_mode tmode = insn_data[icode].operand[0].mode;
-+ if (!target
-+ || GET_MODE (target) != tmode
-+ || !(*insn_data[icode].operand[0].predicate) (target, tmode))
-+ target = gen_reg_rtx (tmode);
-+ op[nopnds++] = target;
-+ }
-+
-+ FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
-+ {
-+ const struct insn_operand_data *insn_op;
-+
-+ if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
-+ return NULL_RTX;
-+
-+ insn_op = &insn_data[icode].operand[nopnds];
-+
-+ op[nopnds] = expand_normal (arg);
-+
-+ if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
-+ {
-+ if (!strcmp (insn_op->constraint, "n"))
-+ {
-+ int arg_num = (nonvoid) ? nopnds : nopnds + 1;
-+ if (!CONST_INT_P (op[nopnds]))
-+ error ("argument %d must be an unsigned literal", arg_num);
-+ else
-+ error ("argument %d is an unsigned literal that is "
-+ "out of range", arg_num);
-+ return const0_rtx;
-+ }
-+ op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
-+ }
-+
-+ nopnds++;
-+ }
-+
-+ /* Handle the builtins for extended mnemonics. These accept
-+ no arguments, but map to builtins that take arguments. */
-+ switch (fcode)
-+ {
-+ case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
-+ case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
-+ op[nopnds++] = GEN_INT (1);
-+#ifdef ENABLE_CHECKING
-+ attr |= RS6000_BTC_UNARY;
-+#endif
-+ break;
-+ case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
-+ op[nopnds++] = GEN_INT (0);
-+#ifdef ENABLE_CHECKING
-+ attr |= RS6000_BTC_UNARY;
-+#endif
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ /* If this builtin accesses SPRs, then pass in the appropriate
-+ SPR number and SPR regno as the last two operands. */
-+ if (attr & RS6000_BTC_SPR)
-+ {
-+ op[nopnds++] = gen_rtx_CONST_INT (Pmode, htm_spr_num (fcode));
-+ op[nopnds++] = gen_rtx_REG (Pmode, htm_spr_regno (fcode));
-+ }
-+
-+#ifdef ENABLE_CHECKING
-+ int expected_nopnds = 0;
-+ if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
-+ expected_nopnds = 1;
-+ else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
-+ expected_nopnds = 2;
-+ else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
-+ expected_nopnds = 3;
-+ if (!(attr & RS6000_BTC_VOID))
-+ expected_nopnds += 1;
-+ if (attr & RS6000_BTC_SPR)
-+ expected_nopnds += 2;
-+
-+ gcc_assert (nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS);
-+#endif
-+
-+ switch (nopnds)
-+ {
-+ case 0:
-+ pat = GEN_FCN (icode) (NULL_RTX);
-+ break;
-+ case 1:
-+ pat = GEN_FCN (icode) (op[0]);
-+ break;
-+ case 2:
-+ pat = GEN_FCN (icode) (op[0], op[1]);
-+ break;
-+ case 3:
-+ pat = GEN_FCN (icode) (op[0], op[1], op[2]);
-+ break;
-+ case 4:
-+ pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
-+ break;
-+ default:
-+ gcc_unreachable ();
-+ }
-+ if (!pat)
-+ return NULL_RTX;
-+ emit_insn (pat);
-+
-+ *expandedp = true;
-+ if (nonvoid)
-+ return target;
-+ return const0_rtx;
-+ }
-+
-+ return NULL_RTX;
-+}
-+
-+static rtx
- rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
- {
- rtx pat;
-@@ -10416,7 +12393,15 @@
- }
- }
- else if (icode == CODE_FOR_vsx_set_v2df
-- || icode == CODE_FOR_vsx_set_v2di)
-+ || icode == CODE_FOR_vsx_set_v2di
-+ || icode == CODE_FOR_bcdadd
-+ || icode == CODE_FOR_bcdadd_lt
-+ || icode == CODE_FOR_bcdadd_eq
-+ || icode == CODE_FOR_bcdadd_gt
-+ || icode == CODE_FOR_bcdsub
-+ || icode == CODE_FOR_bcdsub_lt
-+ || icode == CODE_FOR_bcdsub_eq
-+ || icode == CODE_FOR_bcdsub_gt)
- {
- /* Only allow 1-bit unsigned literals. */
- STRIP_NOPS (arg2);
-@@ -10427,7 +12412,66 @@
- return const0_rtx;
- }
- }
-+ else if (icode == CODE_FOR_dfp_ddedpd_dd
-+ || icode == CODE_FOR_dfp_ddedpd_td)
-+ {
-+ /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
-+ STRIP_NOPS (arg0);
-+ if (TREE_CODE (arg0) != INTEGER_CST
-+ || TREE_INT_CST_LOW (arg2) & ~0x3)
-+ {
-+ error ("argument 1 must be 0 or 2");
-+ return const0_rtx;
-+ }
-+ }
-+ else if (icode == CODE_FOR_dfp_denbcd_dd
-+ || icode == CODE_FOR_dfp_denbcd_td)
-+ {
-+ /* Only allow 1-bit unsigned literals. */
-+ STRIP_NOPS (arg0);
-+ if (TREE_CODE (arg0) != INTEGER_CST
-+ || TREE_INT_CST_LOW (arg0) & ~0x1)
-+ {
-+ error ("argument 1 must be a 1-bit unsigned literal");
-+ return const0_rtx;
-+ }
-+ }
-+ else if (icode == CODE_FOR_dfp_dscli_dd
-+ || icode == CODE_FOR_dfp_dscli_td
-+ || icode == CODE_FOR_dfp_dscri_dd
-+ || icode == CODE_FOR_dfp_dscri_td)
-+ {
-+ /* Only allow 6-bit unsigned literals. */
-+ STRIP_NOPS (arg1);
-+ if (TREE_CODE (arg1) != INTEGER_CST
-+ || TREE_INT_CST_LOW (arg1) & ~0x3f)
-+ {
-+ error ("argument 2 must be a 6-bit unsigned literal");
-+ return const0_rtx;
-+ }
-+ }
-+ else if (icode == CODE_FOR_crypto_vshasigmaw
-+ || icode == CODE_FOR_crypto_vshasigmad)
-+ {
-+ /* Check whether the 2nd and 3rd arguments are integer constants and in
-+ range and prepare arguments. */
-+ STRIP_NOPS (arg1);
-+ if (TREE_CODE (arg1) != INTEGER_CST
-+ || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
-+ {
-+ error ("argument 2 must be 0 or 1");
-+ return const0_rtx;
-+ }
-
-+ STRIP_NOPS (arg2);
-+ if (TREE_CODE (arg2) != INTEGER_CST
-+ || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 15))
-+ {
-+ error ("argument 3 must be in the range 0..15");
-+ return const0_rtx;
-+ }
-+ }
-+
- if (target == 0
- || GET_MODE (target) != tmode
- || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
-@@ -10481,6 +12525,8 @@
- break;
- case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
- icode = CODE_FOR_vector_altivec_load_v2di;
-+ case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:
-+ icode = CODE_FOR_vector_altivec_load_v1ti;
- break;
- default:
- *expandedp = false;
-@@ -10540,6 +12586,8 @@
- break;
- case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
- icode = CODE_FOR_vector_altivec_store_v2di;
-+ case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:
-+ icode = CODE_FOR_vector_altivec_store_v1ti;
- break;
- default:
- *expandedp = false;
-@@ -10632,21 +12680,33 @@
- enum machine_mode tmode = TYPE_MODE (type);
- enum machine_mode inner_mode = GET_MODE_INNER (tmode);
- int i, n_elt = GET_MODE_NUNITS (tmode);
-- rtvec v = rtvec_alloc (n_elt);
-
- gcc_assert (VECTOR_MODE_P (tmode));
- gcc_assert (n_elt == call_expr_nargs (exp));
-
-- for (i = 0; i < n_elt; ++i)
-+ if (!target || !register_operand (target, tmode))
-+ target = gen_reg_rtx (tmode);
-+
-+ /* If we have a vector compromised of a single element, such as V1TImode, do
-+ the initialization directly. */
-+ if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
- {
-- rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
-- RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
-+ rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
-+ emit_move_insn (target, gen_lowpart (tmode, x));
- }
-+ else
-+ {
-+ rtvec v = rtvec_alloc (n_elt);
-
-- if (!target || !register_operand (target, tmode))
-- target = gen_reg_rtx (tmode);
-+ for (i = 0; i < n_elt; ++i)
-+ {
-+ rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
-+ RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
-+ }
-
-- rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
-+ rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
-+ }
-+
- return target;
- }
-
-@@ -10769,8 +12829,19 @@
-
- switch (fcode)
- {
-+ case ALTIVEC_BUILTIN_STVX_V2DF:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
-+ case ALTIVEC_BUILTIN_STVX_V2DI:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
-+ case ALTIVEC_BUILTIN_STVX_V4SF:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
- case ALTIVEC_BUILTIN_STVX:
-+ case ALTIVEC_BUILTIN_STVX_V4SI:
- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
-+ case ALTIVEC_BUILTIN_STVX_V8HI:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
-+ case ALTIVEC_BUILTIN_STVX_V16QI:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
- case ALTIVEC_BUILTIN_STVEBX:
- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
- case ALTIVEC_BUILTIN_STVEHX:
-@@ -10777,8 +12848,19 @@
- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
- case ALTIVEC_BUILTIN_STVEWX:
- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
-+ case ALTIVEC_BUILTIN_STVXL_V2DF:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
-+ case ALTIVEC_BUILTIN_STVXL_V2DI:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
-+ case ALTIVEC_BUILTIN_STVXL_V4SF:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
- case ALTIVEC_BUILTIN_STVXL:
-- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
-+ case ALTIVEC_BUILTIN_STVXL_V4SI:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
-+ case ALTIVEC_BUILTIN_STVXL_V8HI:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
-+ case ALTIVEC_BUILTIN_STVXL_V16QI:
-+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
-
- case ALTIVEC_BUILTIN_STVLX:
- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
-@@ -10789,6 +12871,8 @@
- case ALTIVEC_BUILTIN_STVRXL:
- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
-
-+ case VSX_BUILTIN_STXVD2X_V1TI:
-+ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
- case VSX_BUILTIN_STXVD2X_V2DF:
- return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
- case VSX_BUILTIN_STXVD2X_V2DI:
-@@ -10869,6 +12953,7 @@
- case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
- case VSX_BUILTIN_VEC_INIT_V2DF:
- case VSX_BUILTIN_VEC_INIT_V2DI:
-+ case VSX_BUILTIN_VEC_INIT_V1TI:
- return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
-
- case ALTIVEC_BUILTIN_VEC_SET_V4SI:
-@@ -10877,6 +12962,7 @@
- case ALTIVEC_BUILTIN_VEC_SET_V4SF:
- case VSX_BUILTIN_VEC_SET_V2DF:
- case VSX_BUILTIN_VEC_SET_V2DI:
-+ case VSX_BUILTIN_VEC_SET_V1TI:
- return altivec_expand_vec_set_builtin (exp);
-
- case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
-@@ -10885,6 +12971,7 @@
- case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
- case VSX_BUILTIN_VEC_EXT_V2DF:
- case VSX_BUILTIN_VEC_EXT_V2DI:
-+ case VSX_BUILTIN_VEC_EXT_V1TI:
- return altivec_expand_vec_ext_builtin (exp, target);
-
- default:
-@@ -10922,12 +13009,44 @@
- case ALTIVEC_BUILTIN_LVEWX:
- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
- exp, target, false);
-+ case ALTIVEC_BUILTIN_LVXL_V2DF:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
-+ exp, target, false);
-+ case ALTIVEC_BUILTIN_LVXL_V2DI:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
-+ exp, target, false);
-+ case ALTIVEC_BUILTIN_LVXL_V4SF:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
-+ exp, target, false);
- case ALTIVEC_BUILTIN_LVXL:
-- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
-+ case ALTIVEC_BUILTIN_LVXL_V4SI:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
- exp, target, false);
-+ case ALTIVEC_BUILTIN_LVXL_V8HI:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
-+ exp, target, false);
-+ case ALTIVEC_BUILTIN_LVXL_V16QI:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
-+ exp, target, false);
-+ case ALTIVEC_BUILTIN_LVX_V2DF:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
-+ exp, target, false);
-+ case ALTIVEC_BUILTIN_LVX_V2DI:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
-+ exp, target, false);
-+ case ALTIVEC_BUILTIN_LVX_V4SF:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
-+ exp, target, false);
- case ALTIVEC_BUILTIN_LVX:
-+ case ALTIVEC_BUILTIN_LVX_V4SI:
- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
- exp, target, false);
-+ case ALTIVEC_BUILTIN_LVX_V8HI:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
-+ exp, target, false);
-+ case ALTIVEC_BUILTIN_LVX_V16QI:
-+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
-+ exp, target, false);
- case ALTIVEC_BUILTIN_LVLX:
- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
- exp, target, true);
-@@ -10940,6 +13059,9 @@
- case ALTIVEC_BUILTIN_LVRXL:
- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
- exp, target, true);
-+ case VSX_BUILTIN_LXVD2X_V1TI:
-+ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
-+ exp, target, false);
- case VSX_BUILTIN_LXVD2X_V2DF:
- return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
- exp, target, false);
-@@ -11411,6 +13533,8 @@
- error ("Builtin function %s is only valid for the cell processor", name);
- else if ((fnmask & RS6000_BTM_VSX) != 0)
- error ("Builtin function %s requires the -mvsx option", name);
-+ else if ((fnmask & RS6000_BTM_HTM) != 0)
-+ error ("Builtin function %s requires the -mhtm option", name);
- else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
- error ("Builtin function %s requires the -maltivec option", name);
- else if ((fnmask & RS6000_BTM_PAIRED) != 0)
-@@ -11417,6 +13541,16 @@
- error ("Builtin function %s requires the -mpaired option", name);
- else if ((fnmask & RS6000_BTM_SPE) != 0)
- error ("Builtin function %s requires the -mspe option", name);
-+ else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
-+ == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
-+ error ("Builtin function %s requires the -mhard-dfp and"
-+ "-mpower8-vector options", name);
-+ else if ((fnmask & RS6000_BTM_DFP) != 0)
-+ error ("Builtin function %s requires the -mhard-dfp option", name);
-+ else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
-+ error ("Builtin function %s requires the -mpower8-vector option", name);
-+ else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
-+ error ("Builtin function %s requires the -mhard-float option", name);
- else
- error ("Builtin function %s is not supported with the current options",
- name);
-@@ -11515,7 +13649,8 @@
- case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
- case ALTIVEC_BUILTIN_MASK_FOR_STORE:
- {
-- int icode = (int) CODE_FOR_altivec_lvsr;
-+ int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr
-+ : (int) CODE_FOR_altivec_lvsl);
- enum machine_mode tmode = insn_data[icode].operand[0].mode;
- enum machine_mode mode = insn_data[icode].operand[1].mode;
- tree arg;
-@@ -11590,9 +13725,19 @@
- if (success)
- return ret;
- }
-+ if (TARGET_HTM)
-+ {
-+ ret = htm_expand_builtin (exp, target, &success);
-
-- gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
-+ if (success)
-+ return ret;
-+ }
-
-+ unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
-+ gcc_assert (attr == RS6000_BTC_UNARY
-+ || attr == RS6000_BTC_BINARY
-+ || attr == RS6000_BTC_TERNARY);
-+
- /* Handle simple unary operations. */
- d = bdesc_1arg;
- for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
-@@ -11648,6 +13793,14 @@
- opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
- opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
-
-+ /* We use V1TI mode as a special container to hold __int128_t items that
-+ must live in VSX registers. */
-+ if (intTI_type_node)
-+ {
-+ V1TI_type_node = build_vector_type (intTI_type_node, 1);
-+ unsigned_V1TI_type_node = build_vector_type (unsigned_intTI_type_node, 1);
-+ }
-+
- /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
- types, especially in C++ land. Similarly, 'vector pixel' is distinct from
- 'vector unsigned short'. */
-@@ -11670,8 +13823,13 @@
- uintSI_type_internal_node = unsigned_intSI_type_node;
- intDI_type_internal_node = intDI_type_node;
- uintDI_type_internal_node = unsigned_intDI_type_node;
-+ intTI_type_internal_node = intTI_type_node;
-+ uintTI_type_internal_node = unsigned_intTI_type_node;
- float_type_internal_node = float_type_node;
- double_type_internal_node = double_type_node;
-+ long_double_type_internal_node = long_double_type_node;
-+ dfloat64_type_internal_node = dfloat64_type_node;
-+ dfloat128_type_internal_node = dfloat128_type_node;
- void_type_internal_node = void_type_node;
-
- /* Initialize the modes for builtin_function_type, mapping a machine mode to
-@@ -11682,8 +13840,15 @@
- builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
- builtin_mode_to_type[DImode][0] = intDI_type_node;
- builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
-+ builtin_mode_to_type[TImode][0] = intTI_type_node;
-+ builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
- builtin_mode_to_type[SFmode][0] = float_type_node;
- builtin_mode_to_type[DFmode][0] = double_type_node;
-+ builtin_mode_to_type[TFmode][0] = long_double_type_node;
-+ builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
-+ builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
-+ builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
-+ builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
- builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
- builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
- builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
-@@ -11752,15 +13917,42 @@
- tdecl = add_builtin_type ("__vector double", V2DF_type_node);
- TYPE_NAME (V2DF_type_node) = tdecl;
-
-- tdecl = add_builtin_type ("__vector long", V2DI_type_node);
-- TYPE_NAME (V2DI_type_node) = tdecl;
-+ if (TARGET_POWERPC64)
-+ {
-+ tdecl = add_builtin_type ("__vector long", V2DI_type_node);
-+ TYPE_NAME (V2DI_type_node) = tdecl;
-
-- tdecl = add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node);
-- TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
-+ tdecl = add_builtin_type ("__vector unsigned long",
-+ unsigned_V2DI_type_node);
-+ TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
-
-- tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);
-- TYPE_NAME (bool_V2DI_type_node) = tdecl;
-+ tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);
-+ TYPE_NAME (bool_V2DI_type_node) = tdecl;
-+ }
-+ else
-+ {
-+ tdecl = add_builtin_type ("__vector long long", V2DI_type_node);
-+ TYPE_NAME (V2DI_type_node) = tdecl;
-
-+ tdecl = add_builtin_type ("__vector unsigned long long",
-+ unsigned_V2DI_type_node);
-+ TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
-+
-+ tdecl = add_builtin_type ("__vector __bool long long",
-+ bool_V2DI_type_node);
-+ TYPE_NAME (bool_V2DI_type_node) = tdecl;
-+ }
-+
-+ if (V1TI_type_node)
-+ {
-+ tdecl = add_builtin_type ("__vector __int128", V1TI_type_node);
-+ TYPE_NAME (V1TI_type_node) = tdecl;
-+
-+ tdecl = add_builtin_type ("__vector unsigned __int128",
-+ unsigned_V1TI_type_node);
-+ TYPE_NAME (unsigned_V1TI_type_node) = tdecl;
-+ }
-+
- /* Paired and SPE builtins are only available if you build a compiler with
- the appropriate options, so only create those builtins with the
- appropriate compiler option. Create Altivec and VSX builtins on machines
-@@ -11772,6 +13964,9 @@
- spe_init_builtins ();
- if (TARGET_EXTRA_BUILTINS)
- altivec_init_builtins ();
-+ if (TARGET_HTM)
-+ htm_init_builtins ();
-+
- if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
- rs6000_common_init_builtins ();
-
-@@ -12117,6 +14312,10 @@
- = build_function_type_list (integer_type_node,
- integer_type_node, V4SI_type_node,
- V4SI_type_node, NULL_TREE);
-+ tree int_ftype_int_v2di_v2di
-+ = build_function_type_list (integer_type_node,
-+ integer_type_node, V2DI_type_node,
-+ V2DI_type_node, NULL_TREE);
- tree void_ftype_v4si
- = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
- tree v8hi_ftype_void
-@@ -12199,6 +14398,8 @@
- = build_function_type_list (integer_type_node,
- integer_type_node, V2DF_type_node,
- V2DF_type_node, NULL_TREE);
-+ tree v2di_ftype_v2di
-+ = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
- tree v4si_ftype_v4si
- = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
- tree v8hi_ftype_v8hi
-@@ -12224,10 +14425,58 @@
- def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
- def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
- def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
-+ def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVXL_V2DF);
-+ def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVXL_V2DI);
-+ def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVXL_V4SF);
-+ def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVXL_V4SI);
-+ def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVXL_V8HI);
-+ def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVXL_V16QI);
- def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
-+ def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVX_V2DF);
-+ def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVX_V2DI);
-+ def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVX_V4SF);
-+ def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVX_V4SI);
-+ def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVX_V8HI);
-+ def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
-+ ALTIVEC_BUILTIN_LVX_V16QI);
- def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
-+ def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
-+ ALTIVEC_BUILTIN_STVX_V2DF);
-+ def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
-+ ALTIVEC_BUILTIN_STVX_V2DI);
-+ def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
-+ ALTIVEC_BUILTIN_STVX_V4SF);
-+ def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
-+ ALTIVEC_BUILTIN_STVX_V4SI);
-+ def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
-+ ALTIVEC_BUILTIN_STVX_V8HI);
-+ def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
-+ ALTIVEC_BUILTIN_STVX_V16QI);
- def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
- def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
-+ def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
-+ ALTIVEC_BUILTIN_STVXL_V2DF);
-+ def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
-+ ALTIVEC_BUILTIN_STVXL_V2DI);
-+ def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
-+ ALTIVEC_BUILTIN_STVXL_V4SF);
-+ def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
-+ ALTIVEC_BUILTIN_STVXL_V4SI);
-+ def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
-+ ALTIVEC_BUILTIN_STVXL_V8HI);
-+ def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
-+ ALTIVEC_BUILTIN_STVXL_V16QI);
- def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
- def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
- def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
-@@ -12334,6 +14583,9 @@
- case VOIDmode:
- type = int_ftype_int_opaque_opaque;
- break;
-+ case V2DImode:
-+ type = int_ftype_int_v2di_v2di;
-+ break;
- case V4SImode:
- type = int_ftype_int_v4si_v4si;
- break;
-@@ -12367,6 +14619,9 @@
-
- switch (mode0)
- {
-+ case V2DImode:
-+ type = v2di_ftype_v2di;
-+ break;
- case V4SImode:
- type = v4si_ftype_v4si;
- break;
-@@ -12497,8 +14752,109 @@
- ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
- integer_type_node, NULL_TREE);
- def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
-+
-+
-+ if (V1TI_type_node)
-+ {
-+ tree v1ti_ftype_long_pcvoid
-+ = build_function_type_list (V1TI_type_node,
-+ long_integer_type_node, pcvoid_type_node,
-+ NULL_TREE);
-+ tree void_ftype_v1ti_long_pvoid
-+ = build_function_type_list (void_type_node,
-+ V1TI_type_node, long_integer_type_node,
-+ pvoid_type_node, NULL_TREE);
-+ def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
-+ VSX_BUILTIN_LXVD2X_V1TI);
-+ def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
-+ VSX_BUILTIN_STXVD2X_V1TI);
-+ ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
-+ NULL_TREE, NULL_TREE);
-+ def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
-+ ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
-+ intTI_type_node,
-+ integer_type_node, NULL_TREE);
-+ def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
-+ ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
-+ integer_type_node, NULL_TREE);
-+ def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
-+ }
-+
- }
-
-+static void
-+htm_init_builtins (void)
-+{
-+ HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
-+ const struct builtin_description *d;
-+ size_t i;
-+
-+ d = bdesc_htm;
-+ for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
-+ {
-+ tree op[MAX_HTM_OPERANDS], type;
-+ HOST_WIDE_INT mask = d->mask;
-+ unsigned attr = rs6000_builtin_info[d->code].attr;
-+ bool void_func = (attr & RS6000_BTC_VOID);
-+ int attr_args = (attr & RS6000_BTC_TYPE_MASK);
-+ int nopnds = 0;
-+ tree argtype = (attr & RS6000_BTC_SPR) ? long_unsigned_type_node
-+ : unsigned_type_node;
-+
-+ if ((mask & builtin_mask) != mask)
-+ {
-+ if (TARGET_DEBUG_BUILTIN)
-+ fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
-+ continue;
-+ }
-+
-+ if (d->name == 0)
-+ {
-+ if (TARGET_DEBUG_BUILTIN)
-+ fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
-+ (long unsigned) i);
-+ continue;
-+ }
-+
-+ op[nopnds++] = (void_func) ? void_type_node : argtype;
-+
-+ if (attr_args == RS6000_BTC_UNARY)
-+ op[nopnds++] = argtype;
-+ else if (attr_args == RS6000_BTC_BINARY)
-+ {
-+ op[nopnds++] = argtype;
-+ op[nopnds++] = argtype;
-+ }
-+ else if (attr_args == RS6000_BTC_TERNARY)
-+ {
-+ op[nopnds++] = argtype;
-+ op[nopnds++] = argtype;
-+ op[nopnds++] = argtype;
-+ }
-+
-+ switch (nopnds)
-+ {
-+ case 1:
-+ type = build_function_type_list (op[0], NULL_TREE);
-+ break;
-+ case 2:
-+ type = build_function_type_list (op[0], op[1], NULL_TREE);
-+ break;
-+ case 3:
-+ type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
-+ break;
-+ case 4:
-+ type = build_function_type_list (op[0], op[1], op[2], op[3],
-+ NULL_TREE);
-+ break;
-+ default:
-+ gcc_unreachable ();
-+ }
-+
-+ def_builtin (d->name, type, d->code);
-+ }
-+}
-+
- /* Hash function for builtin functions with up to 3 arguments and a return
- type. */
- static unsigned
-@@ -12572,11 +14928,34 @@
- are type correct. */
- switch (builtin)
- {
-+ /* unsigned 1 argument functions. */
-+ case CRYPTO_BUILTIN_VSBOX:
-+ case P8V_BUILTIN_VGBBD:
-+ case MISC_BUILTIN_CDTBCD:
-+ case MISC_BUILTIN_CBCDTD:
-+ h.uns_p[0] = 1;
-+ h.uns_p[1] = 1;
-+ break;
-+
- /* unsigned 2 argument functions. */
- case ALTIVEC_BUILTIN_VMULEUB_UNS:
- case ALTIVEC_BUILTIN_VMULEUH_UNS:
- case ALTIVEC_BUILTIN_VMULOUB_UNS:
- case ALTIVEC_BUILTIN_VMULOUH_UNS:
-+ case CRYPTO_BUILTIN_VCIPHER:
-+ case CRYPTO_BUILTIN_VCIPHERLAST:
-+ case CRYPTO_BUILTIN_VNCIPHER:
-+ case CRYPTO_BUILTIN_VNCIPHERLAST:
-+ case CRYPTO_BUILTIN_VPMSUMB:
-+ case CRYPTO_BUILTIN_VPMSUMH:
-+ case CRYPTO_BUILTIN_VPMSUMW:
-+ case CRYPTO_BUILTIN_VPMSUMD:
-+ case CRYPTO_BUILTIN_VPMSUM:
-+ case MISC_BUILTIN_ADDG6S:
-+ case MISC_BUILTIN_DIVWEU:
-+ case MISC_BUILTIN_DIVWEUO:
-+ case MISC_BUILTIN_DIVDEU:
-+ case MISC_BUILTIN_DIVDEUO:
- h.uns_p[0] = 1;
- h.uns_p[1] = 1;
- h.uns_p[2] = 1;
-@@ -12599,6 +14978,14 @@
- case VSX_BUILTIN_XXSEL_8HI_UNS:
- case VSX_BUILTIN_XXSEL_4SI_UNS:
- case VSX_BUILTIN_XXSEL_2DI_UNS:
-+ case CRYPTO_BUILTIN_VPERMXOR:
-+ case CRYPTO_BUILTIN_VPERMXOR_V2DI:
-+ case CRYPTO_BUILTIN_VPERMXOR_V4SI:
-+ case CRYPTO_BUILTIN_VPERMXOR_V8HI:
-+ case CRYPTO_BUILTIN_VPERMXOR_V16QI:
-+ case CRYPTO_BUILTIN_VSHASIGMAW:
-+ case CRYPTO_BUILTIN_VSHASIGMAD:
-+ case CRYPTO_BUILTIN_VSHASIGMA:
- h.uns_p[0] = 1;
- h.uns_p[1] = 1;
- h.uns_p[2] = 1;
-@@ -12630,9 +15017,18 @@
- /* signed args, unsigned return. */
- case VSX_BUILTIN_XVCVDPUXDS_UNS:
- case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
-+ case MISC_BUILTIN_UNPACK_TD:
-+ case MISC_BUILTIN_UNPACK_V1TI:
- h.uns_p[0] = 1;
- break;
-
-+ /* unsigned arguments for 128-bit pack instructions. */
-+ case MISC_BUILTIN_PACK_TD:
-+ case MISC_BUILTIN_PACK_V1TI:
-+ h.uns_p[1] = 1;
-+ h.uns_p[2] = 1;
-+ break;
-+
- default:
- break;
- }
-@@ -12740,9 +15136,24 @@
- else
- {
- enum insn_code icode = d->icode;
-- if (d->name == 0 || icode == CODE_FOR_nothing)
-- continue;
-+ if (d->name == 0)
-+ {
-+ if (TARGET_DEBUG_BUILTIN)
-+ fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
-+ (long unsigned)i);
-
-+ continue;
-+ }
-+
-+ if (icode == CODE_FOR_nothing)
-+ {
-+ if (TARGET_DEBUG_BUILTIN)
-+ fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
-+ d->name);
-+
-+ continue;
-+ }
-+
- type = builtin_function_type (insn_data[icode].operand[0].mode,
- insn_data[icode].operand[1].mode,
- insn_data[icode].operand[2].mode,
-@@ -12780,9 +15191,24 @@
- else
- {
- enum insn_code icode = d->icode;
-- if (d->name == 0 || icode == CODE_FOR_nothing)
-- continue;
-+ if (d->name == 0)
-+ {
-+ if (TARGET_DEBUG_BUILTIN)
-+ fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
-+ (long unsigned)i);
-
-+ continue;
-+ }
-+
-+ if (icode == CODE_FOR_nothing)
-+ {
-+ if (TARGET_DEBUG_BUILTIN)
-+ fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
-+ d->name);
-+
-+ continue;
-+ }
-+
- mode0 = insn_data[icode].operand[0].mode;
- mode1 = insn_data[icode].operand[1].mode;
- mode2 = insn_data[icode].operand[2].mode;
-@@ -12842,9 +15268,24 @@
- else
- {
- enum insn_code icode = d->icode;
-- if (d->name == 0 || icode == CODE_FOR_nothing)
-- continue;
-+ if (d->name == 0)
-+ {
-+ if (TARGET_DEBUG_BUILTIN)
-+ fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
-+ (long unsigned)i);
-
-+ continue;
-+ }
-+
-+ if (icode == CODE_FOR_nothing)
-+ {
-+ if (TARGET_DEBUG_BUILTIN)
-+ fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
-+ d->name);
-+
-+ continue;
-+ }
-+
- mode0 = insn_data[icode].operand[0].mode;
- mode1 = insn_data[icode].operand[1].mode;
-
-@@ -13631,7 +16072,7 @@
- static bool eliminated = false;
- rtx ret;
-
-- if (mode != SDmode)
-+ if (mode != SDmode || TARGET_NO_SDMODE_STACK)
- ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
- else
- {
-@@ -13660,6 +16101,17 @@
- return ret;
- }
-
-+/* Return the mode to be used for memory when a secondary memory
-+ location is needed. For SDmode values we need to use DDmode, in
-+ all other cases we can use the same mode. */
-+enum machine_mode
-+rs6000_secondary_memory_needed_mode (enum machine_mode mode)
-+{
-+ if (mode == SDmode)
-+ return DDmode;
-+ return mode;
-+}
-+
- static tree
- rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
- {
-@@ -13690,31 +16142,228 @@
- return NULL_TREE;
- }
-
--enum reload_reg_type {
-- GPR_REGISTER_TYPE,
-- VECTOR_REGISTER_TYPE,
-- OTHER_REGISTER_TYPE
--};
-+/* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
-+ on traditional floating point registers, and the VMRGOW/VMRGEW instructions
-+ only work on the traditional altivec registers, note if an altivec register
-+ was chosen. */
-
--static enum reload_reg_type
--rs6000_reload_register_type (enum reg_class rclass)
-+static enum rs6000_reg_type
-+register_to_reg_type (rtx reg, bool *is_altivec)
- {
-- switch (rclass)
-+ HOST_WIDE_INT regno;
-+ enum reg_class rclass;
-+
-+ if (GET_CODE (reg) == SUBREG)
-+ reg = SUBREG_REG (reg);
-+
-+ if (!REG_P (reg))
-+ return NO_REG_TYPE;
-+
-+ regno = REGNO (reg);
-+ if (regno >= FIRST_PSEUDO_REGISTER)
- {
-- case GENERAL_REGS:
-- case BASE_REGS:
-- return GPR_REGISTER_TYPE;
-+ if (!lra_in_progress && !reload_in_progress && !reload_completed)
-+ return PSEUDO_REG_TYPE;
-
-- case FLOAT_REGS:
-- case ALTIVEC_REGS:
-- case VSX_REGS:
-- return VECTOR_REGISTER_TYPE;
-+ regno = true_regnum (reg);
-+ if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
-+ return PSEUDO_REG_TYPE;
-+ }
-
-- default:
-- return OTHER_REGISTER_TYPE;
-+ gcc_assert (regno >= 0);
-+
-+ if (is_altivec && ALTIVEC_REGNO_P (regno))
-+ *is_altivec = true;
-+
-+ rclass = rs6000_regno_regclass[regno];
-+ return reg_class_to_reg_type[(int)rclass];
-+}
-+
-+/* Helper function for rs6000_secondary_reload to return true if a move to a
-+ different register classe is really a simple move. */
-+
-+static bool
-+rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
-+ enum rs6000_reg_type from_type,
-+ enum machine_mode mode)
-+{
-+ int size;
-+
-+ /* Add support for various direct moves available. In this function, we only
-+ look at cases where we don't need any extra registers, and one or more
-+ simple move insns are issued. At present, 32-bit integers are not allowed
-+ in FPR/VSX registers. Single precision binary floating is not a simple
-+ move because we need to convert to the single precision memory layout.
-+ The 4-byte SDmode can be moved. */
-+ size = GET_MODE_SIZE (mode);
-+ if (TARGET_DIRECT_MOVE
-+ && ((mode == SDmode) || (TARGET_POWERPC64 && size == 8))
-+ && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
-+ || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
-+ return true;
-+
-+ else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
-+ && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
-+ || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
-+ return true;
-+
-+ else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
-+ && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
-+ || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
-+ return true;
-+
-+ return false;
-+}
-+
-+/* Power8 helper function for rs6000_secondary_reload, handle all of the
-+ special direct moves that involve allocating an extra register, return the
-+ insn code of the helper function if there is such a function or
-+ CODE_FOR_nothing if not. */
-+
-+static bool
-+rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
-+ enum rs6000_reg_type from_type,
-+ enum machine_mode mode,
-+ secondary_reload_info *sri,
-+ bool altivec_p)
-+{
-+ bool ret = false;
-+ enum insn_code icode = CODE_FOR_nothing;
-+ int cost = 0;
-+ int size = GET_MODE_SIZE (mode);
-+
-+ if (TARGET_POWERPC64)
-+ {
-+ if (size == 16)
-+ {
-+ /* Handle moving 128-bit values from GPRs to VSX point registers on
-+ power8 when running in 64-bit mode using XXPERMDI to glue the two
-+ 64-bit values back together. */
-+ if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
-+ {
-+ cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
-+ icode = reg_addr[mode].reload_vsx_gpr;
-+ }
-+
-+ /* Handle moving 128-bit values from VSX point registers to GPRs on
-+ power8 when running in 64-bit mode using XXPERMDI to get access to the
-+ bottom 64-bit value. */
-+ else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
-+ {
-+ cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
-+ icode = reg_addr[mode].reload_gpr_vsx;
-+ }
-+ }
-+
-+ else if (mode == SFmode)
-+ {
-+ if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
-+ {
-+ cost = 3; /* xscvdpspn, mfvsrd, and. */
-+ icode = reg_addr[mode].reload_gpr_vsx;
-+ }
-+
-+ else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
-+ {
-+ cost = 2; /* mtvsrz, xscvspdpn. */
-+ icode = reg_addr[mode].reload_vsx_gpr;
-+ }
-+ }
- }
-+
-+ if (TARGET_POWERPC64 && size == 16)
-+ {
-+ /* Handle moving 128-bit values from GPRs to VSX point registers on
-+ power8 when running in 64-bit mode using XXPERMDI to glue the two
-+ 64-bit values back together. */
-+ if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
-+ {
-+ cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
-+ icode = reg_addr[mode].reload_vsx_gpr;
-+ }
-+
-+ /* Handle moving 128-bit values from VSX point registers to GPRs on
-+ power8 when running in 64-bit mode using XXPERMDI to get access to the
-+ bottom 64-bit value. */
-+ else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
-+ {
-+ cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
-+ icode = reg_addr[mode].reload_gpr_vsx;
-+ }
-+ }
-+
-+ else if (!TARGET_POWERPC64 && size == 8)
-+ {
-+ /* Handle moving 64-bit values from GPRs to floating point registers on
-+ power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
-+ values back together. Altivec register classes must be handled
-+ specially since a different instruction is used, and the secondary
-+ reload support requires a single instruction class in the scratch
-+ register constraint. However, right now TFmode is not allowed in
-+ Altivec registers, so the pattern will never match. */
-+ if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
-+ {
-+ cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
-+ icode = reg_addr[mode].reload_fpr_gpr;
-+ }
-+ }
-+
-+ if (icode != CODE_FOR_nothing)
-+ {
-+ ret = true;
-+ if (sri)
-+ {
-+ sri->icode = icode;
-+ sri->extra_cost = cost;
-+ }
-+ }
-+
-+ return ret;
- }
-
-+/* Return whether a move between two register classes can be done either
-+ directly (simple move) or via a pattern that uses a single extra temporary
-+ (using power8's direct move in this case. */
-+
-+static bool
-+rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
-+ enum rs6000_reg_type from_type,
-+ enum machine_mode mode,
-+ secondary_reload_info *sri,
-+ bool altivec_p)
-+{
-+ /* Fall back to load/store reloads if either type is not a register. */
-+ if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
-+ return false;
-+
-+ /* If we haven't allocated registers yet, assume the move can be done for the
-+ standard register types. */
-+ if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
-+ || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
-+ || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
-+ return true;
-+
-+ /* Moves to the same set of registers is a simple move for non-specialized
-+ registers. */
-+ if (to_type == from_type && IS_STD_REG_TYPE (to_type))
-+ return true;
-+
-+ /* Check whether a simple move can be done directly. */
-+ if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
-+ {
-+ if (sri)
-+ {
-+ sri->icode = CODE_FOR_nothing;
-+ sri->extra_cost = 0;
-+ }
-+ return true;
-+ }
-+
-+ /* Now check if we can do it in a few steps. */
-+ return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
-+ altivec_p);
-+}
-+
- /* Inform reload about cases where moving X with a mode MODE to a register in
- RCLASS requires an extra scratch or immediate register. Return the class
- needed for the immediate register.
-@@ -13738,12 +16387,36 @@
- bool default_p = false;
-
- sri->icode = CODE_FOR_nothing;
-+ icode = ((in_p)
-+ ? reg_addr[mode].reload_load
-+ : reg_addr[mode].reload_store);
-
-- /* Convert vector loads and stores into gprs to use an additional base
-- register. */
-- icode = rs6000_vector_reload[mode][in_p != false];
-- if (icode != CODE_FOR_nothing)
-+ if (REG_P (x) || register_operand (x, mode))
- {
-+ enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
-+ bool altivec_p = (rclass == ALTIVEC_REGS);
-+ enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
-+
-+ if (!in_p)
-+ {
-+ enum rs6000_reg_type exchange = to_type;
-+ to_type = from_type;
-+ from_type = exchange;
-+ }
-+
-+ /* Can we do a direct move of some sort? */
-+ if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
-+ altivec_p))
-+ {
-+ icode = (enum insn_code)sri->icode;
-+ default_p = false;
-+ ret = NO_REGS;
-+ }
-+ }
-+
-+ /* Handle vector moves with reload helper functions. */
-+ if (ret == ALL_REGS && icode != CODE_FOR_nothing)
-+ {
- ret = NO_REGS;
- sri->icode = CODE_FOR_nothing;
- sri->extra_cost = 0;
-@@ -13754,14 +16427,23 @@
-
- /* Loads to and stores from gprs can do reg+offset, and wouldn't need
- an extra register in that case, but it would need an extra
-- register if the addressing is reg+reg or (reg+reg)&(-16). */
-+ register if the addressing is reg+reg or (reg+reg)&(-16). Special
-+ case load/store quad. */
- if (rclass == GENERAL_REGS || rclass == BASE_REGS)
- {
-- if (!legitimate_indirect_address_p (addr, false)
-- && !rs6000_legitimate_offset_address_p (TImode, addr,
-- false, true))
-+ if (TARGET_POWERPC64 && TARGET_QUAD_MEMORY
-+ && GET_MODE_SIZE (mode) == 16
-+ && quad_memory_operand (x, mode))
- {
- sri->icode = icode;
-+ sri->extra_cost = 2;
-+ }
-+
-+ else if (!legitimate_indirect_address_p (addr, false)
-+ && !rs6000_legitimate_offset_address_p (PTImode, addr,
-+ false, true))
-+ {
-+ sri->icode = icode;
- /* account for splitting the loads, and converting the
- address from reg+reg to reg. */
- sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)
-@@ -13768,8 +16450,20 @@
- + ((GET_CODE (addr) == AND) ? 1 : 0));
- }
- }
-- /* Loads to and stores from vector registers can only do reg+reg
-- addressing. Altivec registers can also do (reg+reg)&(-16). */
-+ /* Allow scalar loads to/from the traditional floating point
-+ registers, even if VSX memory is set. */
-+ else if ((rclass == FLOAT_REGS || rclass == NO_REGS)
-+ && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
-+ && (legitimate_indirect_address_p (addr, false)
-+ || legitimate_indirect_address_p (addr, false)
-+ || rs6000_legitimate_offset_address_p (mode, addr,
-+ false, true)))
-+
-+ ;
-+ /* Loads to and stores from vector registers can only do reg+reg
-+ addressing. Altivec registers can also do (reg+reg)&(-16). Allow
-+ scalar modes loading up the traditional floating point registers
-+ to use offset addresses. */
- else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS
- || rclass == FLOAT_REGS || rclass == NO_REGS)
- {
-@@ -13813,12 +16507,12 @@
- else
- {
- enum reg_class xclass = REGNO_REG_CLASS (regno);
-- enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);
-- enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);
-+ enum rs6000_reg_type rtype1 = reg_class_to_reg_type[(int)rclass];
-+ enum rs6000_reg_type rtype2 = reg_class_to_reg_type[(int)xclass];
-
- /* If memory is needed, use default_secondary_reload to create the
- stack slot. */
-- if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)
-+ if (rtype1 != rtype2 || !IS_STD_REG_TYPE (rtype1))
- default_p = true;
- else
- ret = NO_REGS;
-@@ -13828,7 +16522,7 @@
- default_p = true;
- }
- else if (TARGET_POWERPC64
-- && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
-+ && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
- && MEM_P (x)
- && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
- {
-@@ -13867,7 +16561,7 @@
- default_p = true;
- }
- else if (!TARGET_POWERPC64
-- && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
-+ && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
- && MEM_P (x)
- && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
- {
-@@ -13945,6 +16639,36 @@
- return ret;
- }
-
-+/* Better tracing for rs6000_secondary_reload_inner. */
-+
-+static void
-+rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
-+ bool store_p)
-+{
-+ rtx set, clobber;
-+
-+ gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
-+
-+ fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
-+ store_p ? "store" : "load");
-+
-+ if (store_p)
-+ set = gen_rtx_SET (VOIDmode, mem, reg);
-+ else
-+ set = gen_rtx_SET (VOIDmode, reg, mem);
-+
-+ clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
-+ debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
-+}
-+
-+static void
-+rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
-+ bool store_p)
-+{
-+ rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
-+ gcc_unreachable ();
-+}
-+
- /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
- to SP+reg addressing. */
-
-@@ -13963,21 +16687,16 @@
- rtx cc_clobber;
-
- if (TARGET_DEBUG_ADDR)
-- {
-- fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",
-- store_p ? "store" : "load");
-- fprintf (stderr, "reg:\n");
-- debug_rtx (reg);
-- fprintf (stderr, "mem:\n");
-- debug_rtx (mem);
-- fprintf (stderr, "scratch:\n");
-- debug_rtx (scratch);
-- }
-+ rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
-
-- gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
-- gcc_assert (GET_CODE (mem) == MEM);
-+ if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
-+
-+ if (GET_CODE (mem) != MEM)
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
-+
- rclass = REGNO_REG_CLASS (regno);
-- addr = XEXP (mem, 0);
-+ addr = find_replacement (&XEXP (mem, 0));
-
- switch (rclass)
- {
-@@ -13988,25 +16707,31 @@
- if (GET_CODE (addr) == AND)
- {
- and_op2 = XEXP (addr, 1);
-- addr = XEXP (addr, 0);
-+ addr = find_replacement (&XEXP (addr, 0));
- }
-
- if (GET_CODE (addr) == PRE_MODIFY)
- {
-- scratch_or_premodify = XEXP (addr, 0);
-- gcc_assert (REG_P (scratch_or_premodify));
-- gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
-- addr = XEXP (addr, 1);
-+ scratch_or_premodify = find_replacement (&XEXP (addr, 0));
-+ if (!REG_P (scratch_or_premodify))
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
-+
-+ addr = find_replacement (&XEXP (addr, 1));
-+ if (GET_CODE (addr) != PLUS)
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
- }
-
- if (GET_CODE (addr) == PLUS
- && (and_op2 != NULL_RTX
-- || !rs6000_legitimate_offset_address_p (TImode, addr,
-+ || !rs6000_legitimate_offset_address_p (PTImode, addr,
- false, true)))
- {
-+ /* find_replacement already recurses into both operands of
-+ PLUS so we don't need to call it here. */
- addr_op1 = XEXP (addr, 0);
- addr_op2 = XEXP (addr, 1);
-- gcc_assert (legitimate_indirect_address_p (addr_op1, false));
-+ if (!legitimate_indirect_address_p (addr_op1, false))
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
-
- if (!REG_P (addr_op2)
- && (GET_CODE (addr_op2) != CONST_INT
-@@ -14034,7 +16759,7 @@
- scratch_or_premodify = scratch;
- }
- else if (!legitimate_indirect_address_p (addr, false)
-- && !rs6000_legitimate_offset_address_p (TImode, addr,
-+ && !rs6000_legitimate_offset_address_p (PTImode, addr,
- false, true))
- {
- if (TARGET_DEBUG_ADDR)
-@@ -14050,9 +16775,21 @@
- }
- break;
-
-- /* Float/Altivec registers can only handle reg+reg addressing. Move
-- other addresses into a scratch register. */
-+ /* Float registers can do offset+reg addressing for scalar types. */
- case FLOAT_REGS:
-+ if (legitimate_indirect_address_p (addr, false) /* reg */
-+ || legitimate_indexed_address_p (addr, false) /* reg+reg */
-+ || ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
-+ && and_op2 == NULL_RTX
-+ && scratch_or_premodify == scratch
-+ && rs6000_legitimate_offset_address_p (mode, addr, false, false)))
-+ break;
-+
-+ /* If this isn't a legacy floating point load/store, fall through to the
-+ VSX defaults. */
-+
-+ /* VSX/Altivec registers can only handle reg+reg addressing. Move other
-+ addresses into a scratch register. */
- case VSX_REGS:
- case ALTIVEC_REGS:
-
-@@ -14066,35 +16803,35 @@
- || !VECTOR_MEM_ALTIVEC_P (mode)))
- {
- and_op2 = XEXP (addr, 1);
-- addr = XEXP (addr, 0);
-+ addr = find_replacement (&XEXP (addr, 0));
- }
-
- /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
- as the address later. */
- if (GET_CODE (addr) == PRE_MODIFY
-- && (!VECTOR_MEM_VSX_P (mode)
-+ && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode)
-+ && (rclass != FLOAT_REGS
-+ || (GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)))
- || and_op2 != NULL_RTX
- || !legitimate_indexed_address_p (XEXP (addr, 1), false)))
- {
-- scratch_or_premodify = XEXP (addr, 0);
-- gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,
-- false));
-- gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
-- addr = XEXP (addr, 1);
-+ scratch_or_premodify = find_replacement (&XEXP (addr, 0));
-+ if (!legitimate_indirect_address_p (scratch_or_premodify, false))
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
-+
-+ addr = find_replacement (&XEXP (addr, 1));
-+ if (GET_CODE (addr) != PLUS)
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
- }
-
- if (legitimate_indirect_address_p (addr, false) /* reg */
- || legitimate_indexed_address_p (addr, false) /* reg+reg */
-- || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */
- || (GET_CODE (addr) == AND /* Altivec memory */
-+ && rclass == ALTIVEC_REGS
- && GET_CODE (XEXP (addr, 1)) == CONST_INT
- && INTVAL (XEXP (addr, 1)) == -16
-- && VECTOR_MEM_ALTIVEC_P (mode))
-- || (rclass == FLOAT_REGS /* legacy float mem */
-- && GET_MODE_SIZE (mode) == 8
-- && and_op2 == NULL_RTX
-- && scratch_or_premodify == scratch
-- && rs6000_legitimate_offset_address_p (mode, addr, false, false)))
-+ && (legitimate_indirect_address_p (XEXP (addr, 0), false)
-+ || legitimate_indexed_address_p (XEXP (addr, 0), false))))
- ;
-
- else if (GET_CODE (addr) == PLUS)
-@@ -14101,7 +16838,8 @@
- {
- addr_op1 = XEXP (addr, 0);
- addr_op2 = XEXP (addr, 1);
-- gcc_assert (REG_P (addr_op1));
-+ if (!REG_P (addr_op1))
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
-
- if (TARGET_DEBUG_ADDR)
- {
-@@ -14120,7 +16858,8 @@
- }
-
- else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
-- || GET_CODE (addr) == CONST_INT || REG_P (addr))
-+ || GET_CODE (addr) == CONST_INT || GET_CODE (addr) == LO_SUM
-+ || REG_P (addr))
- {
- if (TARGET_DEBUG_ADDR)
- {
-@@ -14136,12 +16875,12 @@
- }
-
- else
-- gcc_unreachable ();
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
-
- break;
-
- default:
-- gcc_unreachable ();
-+ rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
- }
-
- /* If the original address involved a pre-modify that we couldn't use the VSX
-@@ -14188,7 +16927,7 @@
- /* Adjust the address if it changed. */
- if (addr != XEXP (mem, 0))
- {
-- mem = change_address (mem, mode, addr);
-+ mem = replace_equiv_address_nv (mem, addr);
- if (TARGET_DEBUG_ADDR)
- fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
- }
-@@ -14253,8 +16992,10 @@
- return;
- }
-
--/* Allocate a 64-bit stack slot to be used for copying SDmode
-- values through if this function has any SDmode references. */
-+/* Allocate a 64-bit stack slot to be used for copying SDmode values through if
-+ this function has any SDmode references. If we are on a power7 or later, we
-+ don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
-+ can load/store the value. */
-
- static void
- rs6000_alloc_sdmode_stack_slot (void)
-@@ -14264,7 +17005,14 @@
- gimple_stmt_iterator gsi;
-
- gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
-+ /* We use a different approach for dealing with the secondary
-+ memory in LRA. */
-+ if (ira_use_lra_p)
-+ return;
-
-+ if (TARGET_NO_SDMODE_STACK)
-+ return;
-+
- FOR_EACH_BB (bb)
- for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
- {
-@@ -14325,8 +17073,7 @@
- {
- enum machine_mode mode = GET_MODE (x);
-
-- if (VECTOR_UNIT_VSX_P (mode)
-- && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
-+ if (TARGET_VSX && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
- return rclass;
-
- if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
-@@ -14334,8 +17081,14 @@
- && easy_vector_constant (x, mode))
- return ALTIVEC_REGS;
-
-- if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))
-- return NO_REGS;
-+ if ((CONSTANT_P (x) || GET_CODE (x) == PLUS))
-+ {
-+ if (reg_class_subset_p (GENERAL_REGS, rclass))
-+ return GENERAL_REGS;
-+ if (reg_class_subset_p (BASE_REGS, rclass))
-+ return BASE_REGS;
-+ return NO_REGS;
-+ }
-
- if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
- return GENERAL_REGS;
-@@ -14349,7 +17102,8 @@
- if (GET_MODE_SIZE (mode) <= 8)
- return FLOAT_REGS;
-
-- if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))
-+ if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
-+ || mode == V1TImode)
- return ALTIVEC_REGS;
-
- return rclass;
-@@ -14381,60 +17135,45 @@
- set and vice versa. */
-
- static bool
--rs6000_secondary_memory_needed (enum reg_class class1,
-- enum reg_class class2,
-+rs6000_secondary_memory_needed (enum reg_class from_class,
-+ enum reg_class to_class,
- enum machine_mode mode)
- {
-- if (class1 == class2)
-- return false;
-+ enum rs6000_reg_type from_type, to_type;
-+ bool altivec_p = ((from_class == ALTIVEC_REGS)
-+ || (to_class == ALTIVEC_REGS));
-
-- /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
-- ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
-- between these classes. But we need memory for other things that can go in
-- FLOAT_REGS like SFmode. */
-- if (TARGET_VSX
-- && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))
-- && (class1 == VSX_REGS || class1 == ALTIVEC_REGS
-- || class1 == FLOAT_REGS))
-- return (class2 != VSX_REGS && class2 != ALTIVEC_REGS
-- && class2 != FLOAT_REGS);
-+ /* If a simple/direct move is available, we don't need secondary memory */
-+ from_type = reg_class_to_reg_type[(int)from_class];
-+ to_type = reg_class_to_reg_type[(int)to_class];
-
-- if (class1 == VSX_REGS || class2 == VSX_REGS)
-- return true;
-+ if (rs6000_secondary_reload_move (to_type, from_type, mode,
-+ (secondary_reload_info *)0, altivec_p))
-+ return false;
-
-- if (class1 == FLOAT_REGS
-- && (!TARGET_MFPGPR || !TARGET_POWERPC64
-- || ((mode != DFmode)
-- && (mode != DDmode)
-- && (mode != DImode))))
-+ /* If we have a floating point or vector register class, we need to use
-+ memory to transfer the data. */
-+ if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
- return true;
-
-- if (class2 == FLOAT_REGS
-- && (!TARGET_MFPGPR || !TARGET_POWERPC64
-- || ((mode != DFmode)
-- && (mode != DDmode)
-- && (mode != DImode))))
-- return true;
--
-- if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)
-- return true;
--
- return false;
- }
-
- /* Debug version of rs6000_secondary_memory_needed. */
- static bool
--rs6000_debug_secondary_memory_needed (enum reg_class class1,
-- enum reg_class class2,
-+rs6000_debug_secondary_memory_needed (enum reg_class from_class,
-+ enum reg_class to_class,
- enum machine_mode mode)
- {
-- bool ret = rs6000_secondary_memory_needed (class1, class2, mode);
-+ bool ret = rs6000_secondary_memory_needed (from_class, to_class, mode);
-
- fprintf (stderr,
-- "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
-- "class2 = %s, mode = %s\n",
-- ret ? "true" : "false", reg_class_names[class1],
-- reg_class_names[class2], GET_MODE_NAME (mode));
-+ "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
-+ "to_class = %s, mode = %s\n",
-+ ret ? "true" : "false",
-+ reg_class_names[from_class],
-+ reg_class_names[to_class],
-+ GET_MODE_NAME (mode));
-
- return ret;
- }
-@@ -14498,15 +17237,21 @@
- /* Constants, memory, and FP registers can go into FP registers. */
- if ((regno == -1 || FP_REGNO_P (regno))
- && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
-- return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
-+ return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
-
- /* Memory, and FP/altivec registers can go into fp/altivec registers under
-- VSX. */
-+ VSX. However, for scalar variables, use the traditional floating point
-+ registers so that we can use offset+register addressing. */
- if (TARGET_VSX
- && (regno == -1 || VSX_REGNO_P (regno))
- && VSX_REG_CLASS_P (rclass))
-- return NO_REGS;
-+ {
-+ if (GET_MODE_SIZE (mode) < 16)
-+ return FLOAT_REGS;
-
-+ return NO_REGS;
-+ }
-+
- /* Memory, and AltiVec registers can go into AltiVec registers. */
- if ((regno == -1 || ALTIVEC_REGNO_P (regno))
- && rclass == ALTIVEC_REGS)
-@@ -14550,8 +17295,42 @@
- if (from_size != to_size)
- {
- enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
-- return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)
-- && reg_classes_intersect_p (xclass, rclass));
-+
-+ if (reg_classes_intersect_p (xclass, rclass))
-+ {
-+ unsigned to_nregs = hard_regno_nregs[FIRST_FPR_REGNO][to];
-+ unsigned from_nregs = hard_regno_nregs[FIRST_FPR_REGNO][from];
-+
-+ /* Don't allow 64-bit types to overlap with 128-bit types that take a
-+ single register under VSX because the scalar part of the register
-+ is in the upper 64-bits, and not the lower 64-bits. Types like
-+ TFmode/TDmode that take 2 scalar register can overlap. 128-bit
-+ IEEE floating point can't overlap, and neither can small
-+ values. */
-+
-+ if (TARGET_IEEEQUAD && (to == TFmode || from == TFmode))
-+ return true;
-+
-+ /* TDmode in floating-mode registers must always go into a register
-+ pair with the most significant word in the even-numbered register
-+ to match ISA requirements. In little-endian mode, this does not
-+ match subreg numbering, so we cannot allow subregs. */
-+ if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
-+ return true;
-+
-+ if (from_size < 8 || to_size < 8)
-+ return true;
-+
-+ if (from_size == 8 && (8 * to_nregs) != to_size)
-+ return true;
-+
-+ if (to_size == 8 && (8 * from_nregs) != from_size)
-+ return true;
-+
-+ return false;
-+ }
-+ else
-+ return false;
- }
-
- if (TARGET_E500_DOUBLE
-@@ -14565,10 +17344,19 @@
- /* Since the VSX register set includes traditional floating point registers
- and altivec registers, just check for the size being different instead of
- trying to check whether the modes are vector modes. Otherwise it won't
-- allow say DF and DI to change classes. */
-+ allow say DF and DI to change classes. For types like TFmode and TDmode
-+ that take 2 64-bit registers, rather than a single 128-bit register, don't
-+ allow subregs of those types to other 128 bit types. */
- if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
-- return (from_size != 8 && from_size != 16);
-+ {
-+ unsigned num_regs = (from_size + 15) / 16;
-+ if (hard_regno_nregs[FIRST_FPR_REGNO][to] > num_regs
-+ || hard_regno_nregs[FIRST_FPR_REGNO][from] > num_regs)
-+ return true;
-
-+ return (from_size != 8 && from_size != 16);
-+ }
-+
- if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
- && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
- return true;
-@@ -14598,6 +17386,186 @@
- return ret;
- }
-
-+/* Return a string to do a move operation of 128 bits of data. */
-+
-+const char *
-+rs6000_output_move_128bit (rtx operands[])
-+{
-+ rtx dest = operands[0];
-+ rtx src = operands[1];
-+ enum machine_mode mode = GET_MODE (dest);
-+ int dest_regno;
-+ int src_regno;
-+ bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
-+ bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
-+
-+ if (REG_P (dest))
-+ {
-+ dest_regno = REGNO (dest);
-+ dest_gpr_p = INT_REGNO_P (dest_regno);
-+ dest_fp_p = FP_REGNO_P (dest_regno);
-+ dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
-+ dest_vsx_p = dest_fp_p | dest_vmx_p;
-+ }
-+ else
-+ {
-+ dest_regno = -1;
-+ dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
-+ }
-+
-+ if (REG_P (src))
-+ {
-+ src_regno = REGNO (src);
-+ src_gpr_p = INT_REGNO_P (src_regno);
-+ src_fp_p = FP_REGNO_P (src_regno);
-+ src_vmx_p = ALTIVEC_REGNO_P (src_regno);
-+ src_vsx_p = src_fp_p | src_vmx_p;
-+ }
-+ else
-+ {
-+ src_regno = -1;
-+ src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
-+ }
-+
-+ /* Register moves. */
-+ if (dest_regno >= 0 && src_regno >= 0)
-+ {
-+ if (dest_gpr_p)
-+ {
-+ if (src_gpr_p)
-+ return "#";
-+
-+ else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
-+ return "#";
-+ }
-+
-+ else if (TARGET_VSX && dest_vsx_p)
-+ {
-+ if (src_vsx_p)
-+ return "xxlor %x0,%x1,%x1";
-+
-+ else if (TARGET_DIRECT_MOVE && src_gpr_p)
-+ return "#";
-+ }
-+
-+ else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
-+ return "vor %0,%1,%1";
-+
-+ else if (dest_fp_p && src_fp_p)
-+ return "#";
-+ }
-+
-+ /* Loads. */
-+ else if (dest_regno >= 0 && MEM_P (src))
-+ {
-+ if (dest_gpr_p)
-+ {
-+ if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
-+ return "lq %0,%1";
-+ else
-+ return "#";
-+ }
-+
-+ else if (TARGET_ALTIVEC && dest_vmx_p
-+ && altivec_indexed_or_indirect_operand (src, mode))
-+ return "lvx %0,%y1";
-+
-+ else if (TARGET_VSX && dest_vsx_p)
-+ {
-+ if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
-+ return "lxvw4x %x0,%y1";
-+ else
-+ return "lxvd2x %x0,%y1";
-+ }
-+
-+ else if (TARGET_ALTIVEC && dest_vmx_p)
-+ return "lvx %0,%y1";
-+
-+ else if (dest_fp_p)
-+ return "#";
-+ }
-+
-+ /* Stores. */
-+ else if (src_regno >= 0 && MEM_P (dest))
-+ {
-+ if (src_gpr_p)
-+ {
-+ if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
-+ return "stq %1,%0";
-+ else
-+ return "#";
-+ }
-+
-+ else if (TARGET_ALTIVEC && src_vmx_p
-+ && altivec_indexed_or_indirect_operand (src, mode))
-+ return "stvx %1,%y0";
-+
-+ else if (TARGET_VSX && src_vsx_p)
-+ {
-+ if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
-+ return "stxvw4x %x1,%y0";
-+ else
-+ return "stxvd2x %x1,%y0";
-+ }
-+
-+ else if (TARGET_ALTIVEC && src_vmx_p)
-+ return "stvx %1,%y0";
-+
-+ else if (src_fp_p)
-+ return "#";
-+ }
-+
-+ /* Constants. */
-+ else if (dest_regno >= 0
-+ && (GET_CODE (src) == CONST_INT
-+ || GET_CODE (src) == CONST_DOUBLE
-+ || GET_CODE (src) == CONST_VECTOR))
-+ {
-+ if (dest_gpr_p)
-+ return "#";
-+
-+ else if (TARGET_VSX && dest_vsx_p && zero_constant (src, mode))
-+ return "xxlxor %x0,%x0,%x0";
-+
-+ else if (TARGET_ALTIVEC && dest_vmx_p)
-+ return output_vec_const_move (operands);
-+ }
-+
-+ if (TARGET_DEBUG_ADDR)
-+ {
-+ fprintf (stderr, "\n===== Bad 128 bit move:\n");
-+ debug_rtx (gen_rtx_SET (VOIDmode, dest, src));
-+ }
-+
-+ gcc_unreachable ();
-+}
-+
-+/* Validate a 128-bit move. */
-+bool
-+rs6000_move_128bit_ok_p (rtx operands[])
-+{
-+ enum machine_mode mode = GET_MODE (operands[0]);
-+ return (gpc_reg_operand (operands[0], mode)
-+ || gpc_reg_operand (operands[1], mode));
-+}
-+
-+/* Return true if a 128-bit move needs to be split. */
-+bool
-+rs6000_split_128bit_ok_p (rtx operands[])
-+{
-+ if (!reload_completed)
-+ return false;
-+
-+ if (!gpr_or_gpr_p (operands[0], operands[1]))
-+ return false;
-+
-+ if (quad_load_store_p (operands[0], operands[1]))
-+ return false;
-+
-+ return true;
-+}
-+
-+
- /* Given a comparison operation, return the bit number in CCR to test. We
- know this is a valid comparison.
-
-@@ -14823,6 +17791,7 @@
- ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
- break;
-
-+ case ABI_ELFv2:
- case ABI_V4:
- case ABI_DARWIN:
- break;
-@@ -15302,7 +18271,7 @@
- return;
-
- case 'Y':
-- /* Like 'L', for third word of TImode */
-+ /* Like 'L', for third word of TImode/PTImode */
- if (REG_P (x))
- fputs (reg_names[REGNO (x) + 2], file);
- else if (MEM_P (x))
-@@ -15352,7 +18321,7 @@
- return;
-
- case 'Z':
-- /* Like 'L', for last word of TImode. */
-+ /* Like 'L', for last word of TImode/PTImode. */
- if (REG_P (x))
- fputs (reg_names[REGNO (x) + 3], file);
- else if (MEM_P (x))
-@@ -15383,7 +18352,8 @@
- if ((TARGET_SPE || TARGET_E500_DOUBLE)
- && (GET_MODE_SIZE (GET_MODE (x)) == 8
- || GET_MODE (x) == TFmode
-- || GET_MODE (x) == TImode))
-+ || GET_MODE (x) == TImode
-+ || GET_MODE (x) == PTImode))
- {
- /* Handle [reg]. */
- if (REG_P (tmp))
-@@ -16766,7 +19736,8 @@
- }
-
- /* A subroutine of the atomic operation splitters. Emit a load-locked
-- instruction in MODE. */
-+ instruction in MODE. For QI/HImode, possibly use a pattern than includes
-+ the zero_extend operation. */
-
- static void
- emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
-@@ -16775,12 +19746,26 @@
-
- switch (mode)
- {
-+ case QImode:
-+ fn = gen_load_lockedqi;
-+ break;
-+ case HImode:
-+ fn = gen_load_lockedhi;
-+ break;
- case SImode:
-- fn = gen_load_lockedsi;
-+ if (GET_MODE (mem) == QImode)
-+ fn = gen_load_lockedqi_si;
-+ else if (GET_MODE (mem) == HImode)
-+ fn = gen_load_lockedhi_si;
-+ else
-+ fn = gen_load_lockedsi;
- break;
- case DImode:
- fn = gen_load_lockeddi;
- break;
-+ case TImode:
-+ fn = gen_load_lockedti;
-+ break;
- default:
- gcc_unreachable ();
- }
-@@ -16797,6 +19782,12 @@
-
- switch (mode)
- {
-+ case QImode:
-+ fn = gen_store_conditionalqi;
-+ break;
-+ case HImode:
-+ fn = gen_store_conditionalhi;
-+ break;
- case SImode:
- fn = gen_store_conditionalsi;
- break;
-@@ -16803,6 +19794,9 @@
- case DImode:
- fn = gen_store_conditionaldi;
- break;
-+ case TImode:
-+ fn = gen_store_conditionalti;
-+ break;
- default:
- gcc_unreachable ();
- }
-@@ -16949,7 +19943,7 @@
- {
- rtx boolval, retval, mem, oldval, newval, cond;
- rtx label1, label2, x, mask, shift;
-- enum machine_mode mode;
-+ enum machine_mode mode, orig_mode;
- enum memmodel mod_s, mod_f;
- bool is_weak;
-
-@@ -16961,23 +19955,30 @@
- is_weak = (INTVAL (operands[5]) != 0);
- mod_s = (enum memmodel) INTVAL (operands[6]);
- mod_f = (enum memmodel) INTVAL (operands[7]);
-- mode = GET_MODE (mem);
-+ orig_mode = mode = GET_MODE (mem);
-
- mask = shift = NULL_RTX;
- if (mode == QImode || mode == HImode)
- {
-- mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
--
-- /* Shift and mask OLDVAL into position with the word. */
-+ /* Before power8, we didn't have access to lbarx/lharx, so generate a
-+ lwarx and shift/mask operations. With power8, we need to do the
-+ comparison in SImode, but the store is still done in QI/HImode. */
- oldval = convert_modes (SImode, mode, oldval, 1);
-- oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
-- NULL_RTX, 1, OPTAB_LIB_WIDEN);
-
-- /* Shift and mask NEWVAL into position within the word. */
-- newval = convert_modes (SImode, mode, newval, 1);
-- newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
-- NULL_RTX, 1, OPTAB_LIB_WIDEN);
-+ if (!TARGET_SYNC_HI_QI)
-+ {
-+ mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
-
-+ /* Shift and mask OLDVAL into position with the word. */
-+ oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
-+ NULL_RTX, 1, OPTAB_LIB_WIDEN);
-+
-+ /* Shift and mask NEWVAL into position within the word. */
-+ newval = convert_modes (SImode, mode, newval, 1);
-+ newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
-+ NULL_RTX, 1, OPTAB_LIB_WIDEN);
-+ }
-+
- /* Prepare to adjust the return value. */
- retval = gen_reg_rtx (SImode);
- mode = SImode;
-@@ -17005,7 +20006,25 @@
- }
-
- cond = gen_reg_rtx (CCmode);
-- x = gen_rtx_COMPARE (CCmode, x, oldval);
-+ /* If we have TImode, synthesize a comparison. */
-+ if (mode != TImode)
-+ x = gen_rtx_COMPARE (CCmode, x, oldval);
-+ else
-+ {
-+ rtx xor1_result = gen_reg_rtx (DImode);
-+ rtx xor2_result = gen_reg_rtx (DImode);
-+ rtx or_result = gen_reg_rtx (DImode);
-+ rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
-+ rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
-+ rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
-+ rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
-+
-+ emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
-+ emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
-+ emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
-+ x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
-+ }
-+
- emit_insn (gen_rtx_SET (VOIDmode, cond, x));
-
- x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
-@@ -17015,7 +20034,7 @@
- if (mask)
- x = rs6000_mask_atomic_subword (retval, newval, mask);
-
-- emit_store_conditional (mode, cond, mem, x);
-+ emit_store_conditional (orig_mode, cond, mem, x);
-
- if (!is_weak)
- {
-@@ -17033,6 +20052,8 @@
-
- if (shift)
- rs6000_finish_atomic_subword (operands[1], retval, shift);
-+ else if (mode != GET_MODE (operands[1]))
-+ convert_move (operands[1], retval, 1);
-
- /* In all cases, CR0 contains EQ on success, and NE on failure. */
- x = gen_rtx_EQ (SImode, cond, const0_rtx);
-@@ -17056,7 +20077,7 @@
- mode = GET_MODE (mem);
-
- mask = shift = NULL_RTX;
-- if (mode == QImode || mode == HImode)
-+ if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
- {
- mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
-
-@@ -17105,53 +20126,70 @@
- {
- enum memmodel model = (enum memmodel) INTVAL (model_rtx);
- enum machine_mode mode = GET_MODE (mem);
-+ enum machine_mode store_mode = mode;
- rtx label, x, cond, mask, shift;
- rtx before = orig_before, after = orig_after;
-
- mask = shift = NULL_RTX;
-+ /* On power8, we want to use SImode for the operation. On previous systems,
-+ use the operation in a subword and shift/mask to get the proper byte or
-+ halfword. */
- if (mode == QImode || mode == HImode)
- {
-- mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
-+ if (TARGET_SYNC_HI_QI)
-+ {
-+ val = convert_modes (SImode, mode, val, 1);
-
-- /* Shift and mask VAL into position with the word. */
-- val = convert_modes (SImode, mode, val, 1);
-- val = expand_simple_binop (SImode, ASHIFT, val, shift,
-- NULL_RTX, 1, OPTAB_LIB_WIDEN);
--
-- switch (code)
-+ /* Prepare to adjust the return value. */
-+ before = gen_reg_rtx (SImode);
-+ if (after)
-+ after = gen_reg_rtx (SImode);
-+ mode = SImode;
-+ }
-+ else
- {
-- case IOR:
-- case XOR:
-- /* We've already zero-extended VAL. That is sufficient to
-- make certain that it does not affect other bits. */
-- mask = NULL;
-- break;
-+ mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
-
-- case AND:
-- /* If we make certain that all of the other bits in VAL are
-- set, that will be sufficient to not affect other bits. */
-- x = gen_rtx_NOT (SImode, mask);
-- x = gen_rtx_IOR (SImode, x, val);
-- emit_insn (gen_rtx_SET (VOIDmode, val, x));
-- mask = NULL;
-- break;
-+ /* Shift and mask VAL into position with the word. */
-+ val = convert_modes (SImode, mode, val, 1);
-+ val = expand_simple_binop (SImode, ASHIFT, val, shift,
-+ NULL_RTX, 1, OPTAB_LIB_WIDEN);
-
-- case NOT:
-- case PLUS:
-- case MINUS:
-- /* These will all affect bits outside the field and need
-- adjustment via MASK within the loop. */
-- break;
-+ switch (code)
-+ {
-+ case IOR:
-+ case XOR:
-+ /* We've already zero-extended VAL. That is sufficient to
-+ make certain that it does not affect other bits. */
-+ mask = NULL;
-+ break;
-
-- default:
-- gcc_unreachable ();
-+ case AND:
-+ /* If we make certain that all of the other bits in VAL are
-+ set, that will be sufficient to not affect other bits. */
-+ x = gen_rtx_NOT (SImode, mask);
-+ x = gen_rtx_IOR (SImode, x, val);
-+ emit_insn (gen_rtx_SET (VOIDmode, val, x));
-+ mask = NULL;
-+ break;
-+
-+ case NOT:
-+ case PLUS:
-+ case MINUS:
-+ /* These will all affect bits outside the field and need
-+ adjustment via MASK within the loop. */
-+ break;
-+
-+ default:
-+ gcc_unreachable ();
-+ }
-+
-+ /* Prepare to adjust the return value. */
-+ before = gen_reg_rtx (SImode);
-+ if (after)
-+ after = gen_reg_rtx (SImode);
-+ store_mode = mode = SImode;
- }
--
-- /* Prepare to adjust the return value. */
-- before = gen_reg_rtx (SImode);
-- if (after)
-- after = gen_reg_rtx (SImode);
-- mode = SImode;
- }
-
- mem = rs6000_pre_atomic_barrier (mem, model);
-@@ -17184,9 +20222,11 @@
- NULL_RTX, 1, OPTAB_LIB_WIDEN);
- x = rs6000_mask_atomic_subword (before, x, mask);
- }
-+ else if (store_mode != mode)
-+ x = convert_modes (store_mode, mode, x, 1);
-
- cond = gen_reg_rtx (CCmode);
-- emit_store_conditional (mode, cond, mem, x);
-+ emit_store_conditional (store_mode, cond, mem, x);
-
- x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
- emit_unlikely_jump (x, label);
-@@ -17195,11 +20235,22 @@
-
- if (shift)
- {
-+ /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
-+ then do the calcuations in a SImode register. */
- if (orig_before)
- rs6000_finish_atomic_subword (orig_before, before, shift);
- if (orig_after)
- rs6000_finish_atomic_subword (orig_after, after, shift);
- }
-+ else if (store_mode != mode)
-+ {
-+ /* QImode/HImode on machines with lbarx/lharx where we do the native
-+ operation and then do the calcuations in a SImode register. */
-+ if (orig_before)
-+ convert_move (orig_before, before, 1);
-+ if (orig_after)
-+ convert_move (orig_after, after, 1);
-+ }
- else if (orig_after && after != orig_after)
- emit_move_insn (orig_after, after);
- }
-@@ -17239,6 +20290,39 @@
-
- gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
-
-+ /* TDmode residing in FP registers is special, since the ISA requires that
-+ the lower-numbered word of a register pair is always the most significant
-+ word, even in little-endian mode. This does not match the usual subreg
-+ semantics, so we cannnot use simplify_gen_subreg in those cases. Access
-+ the appropriate constituent registers "by hand" in little-endian mode.
-+
-+ Note we do not need to check for destructive overlap here since TDmode
-+ can only reside in even/odd register pairs. */
-+ if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
-+ {
-+ rtx p_src, p_dst;
-+ int i;
-+
-+ for (i = 0; i < nregs; i++)
-+ {
-+ if (REG_P (src) && FP_REGNO_P (REGNO (src)))
-+ p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
-+ else
-+ p_src = simplify_gen_subreg (reg_mode, src, mode,
-+ i * reg_mode_size);
-+
-+ if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
-+ p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
-+ else
-+ p_dst = simplify_gen_subreg (reg_mode, dst, mode,
-+ i * reg_mode_size);
-+
-+ emit_insn (gen_rtx_SET (VOIDmode, p_dst, p_src));
-+ }
-+
-+ return;
-+ }
-+
- if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
- {
- /* Move register range backwards, if we might have destructive
-@@ -17693,7 +20777,7 @@
- }
- else
- {
-- gcc_checking_assert (DEFAULT_ABI == ABI_AIX);
-+ gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
- if (info->first_fp_reg_save > 61)
- strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
- strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
-@@ -17704,7 +20788,8 @@
- by the static chain. It would require too much fiddling and the
- static chain is rarely used anyway. FPRs are saved w.r.t the stack
- pointer on Darwin, and AIX uses r1 or r12. */
-- if (using_static_chain_p && DEFAULT_ABI != ABI_AIX)
-+ if (using_static_chain_p
-+ && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
- strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
- | SAVE_INLINE_GPRS
- | SAVE_INLINE_VRS | REST_INLINE_VRS);
-@@ -17837,7 +20922,35 @@
- The required alignment for AIX configurations is two words (i.e., 8
- or 16 bytes).
-
-+ The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
-
-+ SP----> +---------------------------------------+
-+ | Back chain to caller | 0
-+ +---------------------------------------+
-+ | Save area for CR | 8
-+ +---------------------------------------+
-+ | Saved LR | 16
-+ +---------------------------------------+
-+ | Saved TOC pointer | 24
-+ +---------------------------------------+
-+ | Parameter save area (P) | 32
-+ +---------------------------------------+
-+ | Alloca space (A) | 32+P
-+ +---------------------------------------+
-+ | Local variable space (L) | 32+P+A
-+ +---------------------------------------+
-+ | Save area for AltiVec registers (W) | 32+P+A+L
-+ +---------------------------------------+
-+ | AltiVec alignment padding (Y) | 32+P+A+L+W
-+ +---------------------------------------+
-+ | Save area for GP registers (G) | 32+P+A+L+W+Y
-+ +---------------------------------------+
-+ | Save area for FP registers (F) | 32+P+A+L+W+Y+G
-+ +---------------------------------------+
-+ old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
-+ +---------------------------------------+
-+
-+
- V.4 stack frames look like:
-
- SP----> +---------------------------------------+
-@@ -17897,6 +21010,7 @@
- rs6000_stack_t *info_ptr = &stack_info;
- int reg_size = TARGET_32BIT ? 4 : 8;
- int ehrd_size;
-+ int ehcr_size;
- int save_align;
- int first_gp;
- HOST_WIDE_INT non_fixed_size;
-@@ -17990,6 +21104,18 @@
- else
- ehrd_size = 0;
-
-+ /* In the ELFv2 ABI, we also need to allocate space for separate
-+ CR field save areas if the function calls __builtin_eh_return. */
-+ if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
-+ {
-+ /* This hard-codes that we have three call-saved CR fields. */
-+ ehcr_size = 3 * reg_size;
-+ /* We do *not* use the regular CR save mechanism. */
-+ info_ptr->cr_save_p = 0;
-+ }
-+ else
-+ ehcr_size = 0;
-+
- /* Determine various sizes. */
- info_ptr->reg_size = reg_size;
- info_ptr->fixed_size = RS6000_SAVE_AREA;
-@@ -18029,6 +21155,7 @@
- gcc_unreachable ();
-
- case ABI_AIX:
-+ case ABI_ELFv2:
- case ABI_DARWIN:
- info_ptr->fp_save_offset = - info_ptr->fp_size;
- info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
-@@ -18058,6 +21185,8 @@
- }
- else
- info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
-+
-+ info_ptr->ehcr_offset = info_ptr->ehrd_offset - ehcr_size;
- info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
- info_ptr->lr_save_offset = 2*reg_size;
- break;
-@@ -18120,6 +21249,7 @@
- + info_ptr->spe_gp_size
- + info_ptr->spe_padding_size
- + ehrd_size
-+ + ehcr_size
- + info_ptr->cr_size
- + info_ptr->vrsave_size,
- save_align);
-@@ -18133,7 +21263,7 @@
-
- /* Determine if we need to save the link register. */
- if (info_ptr->calls_p
-- || (DEFAULT_ABI == ABI_AIX
-+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- && crtl->profile
- && !TARGET_PROFILE_KERNEL)
- || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
-@@ -18279,6 +21409,7 @@
- default: abi_string = "Unknown"; break;
- case ABI_NONE: abi_string = "NONE"; break;
- case ABI_AIX: abi_string = "AIX"; break;
-+ case ABI_ELFv2: abi_string = "ELFv2"; break;
- case ABI_DARWIN: abi_string = "Darwin"; break;
- case ABI_V4: abi_string = "V.4"; break;
- }
-@@ -18400,7 +21531,8 @@
- /* Currently we don't optimize very well between prolog and body
- code and for PIC code the code can be actually quite bad, so
- don't try to be too clever here. */
-- if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
-+ if (count != 0
-+ || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
- {
- cfun->machine->ra_needs_full_frame = 1;
-
-@@ -18459,13 +21591,13 @@
- return false;
- }
-
-- /* Under the AIX ABI we can't allow calls to non-local functions,
-- because the callee may have a different TOC pointer to the
-- caller and there's no way to ensure we restore the TOC when we
-- return. With the secure-plt SYSV ABI we can't make non-local
-+ /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
-+ functions, because the callee may have a different TOC pointer to
-+ the caller and there's no way to ensure we restore the TOC when
-+ we return. With the secure-plt SYSV ABI we can't make non-local
- calls when -fpic/PIC because the plt call stubs use r30. */
- if (DEFAULT_ABI == ABI_DARWIN
-- || (DEFAULT_ABI == ABI_AIX
-+ || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- && decl
- && !DECL_EXTERNAL (decl)
- && (*targetm.binds_local_p) (decl))
-@@ -18566,7 +21698,7 @@
- rtx dest;
- dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
-
-- if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
-+ if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
- {
- char buf[30];
- rtx lab, tmp1, tmp2, got;
-@@ -18594,7 +21726,7 @@
- emit_insn (gen_load_toc_v4_pic_si ());
- emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
- }
-- else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
-+ else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
- {
- char buf[30];
- rtx temp0 = (fromprolog
-@@ -18642,7 +21774,7 @@
- }
- else
- {
-- gcc_assert (DEFAULT_ABI == ABI_AIX);
-+ gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
-
- if (TARGET_32BIT)
- emit_insn (gen_load_toc_aix_si (dest));
-@@ -19047,7 +22179,7 @@
-
- static rtx
- rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
-- rtx reg2, rtx rreg)
-+ rtx reg2, rtx rreg, rtx split_reg)
- {
- rtx real, temp;
-
-@@ -19138,6 +22270,11 @@
- }
- }
-
-+ /* If a store insn has been split into multiple insns, the
-+ true source register is given by split_reg. */
-+ if (split_reg != NULL_RTX)
-+ real = gen_rtx_SET (VOIDmode, SET_DEST (real), split_reg);
-+
- RTX_FRAME_RELATED_P (insn) = 1;
- add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
-
-@@ -19245,7 +22382,7 @@
- reg = gen_rtx_REG (mode, regno);
- insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
- return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
-- NULL_RTX, NULL_RTX);
-+ NULL_RTX, NULL_RTX, NULL_RTX);
- }
-
- /* Emit an offset memory reference suitable for a frame store, while
-@@ -19361,7 +22498,7 @@
- if ((sel & SAVRES_LR))
- suffix = "_x";
- }
-- else if (DEFAULT_ABI == ABI_AIX)
-+ else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- {
- #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
- /* No out-of-line save/restore routines for GPRs on AIX. */
-@@ -19502,7 +22639,7 @@
- static inline unsigned
- ptr_regno_for_savres (int sel)
- {
-- if (DEFAULT_ABI == ABI_AIX)
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
- return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
- }
-@@ -19587,6 +22724,43 @@
- return insn;
- }
-
-+/* Emit code to store CR fields that need to be saved into REG. */
-+
-+static void
-+rs6000_emit_move_from_cr (rtx reg)
-+{
-+ /* Only the ELFv2 ABI allows storing only selected fields. */
-+ if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
-+ {
-+ int i, cr_reg[8], count = 0;
-+
-+ /* Collect CR fields that must be saved. */
-+ for (i = 0; i < 8; i++)
-+ if (save_reg_p (CR0_REGNO + i))
-+ cr_reg[count++] = i;
-+
-+ /* If it's just a single one, use mfcrf. */
-+ if (count == 1)
-+ {
-+ rtvec p = rtvec_alloc (1);
-+ rtvec r = rtvec_alloc (2);
-+ RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
-+ RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
-+ RTVEC_ELT (p, 0)
-+ = gen_rtx_SET (VOIDmode, reg,
-+ gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
-+
-+ emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
-+ return;
-+ }
-+
-+ /* ??? It might be better to handle count == 2 / 3 cases here
-+ as well, using logical operations to combine the values. */
-+ }
-+
-+ emit_insn (gen_movesi_from_cr (reg));
-+}
-+
- /* Determine whether the gp REG is really used. */
-
- static bool
-@@ -19652,6 +22826,17 @@
- #define NOT_INUSE(R) do {} while (0)
- #endif
-
-+ if (DEFAULT_ABI == ABI_ELFv2)
-+ {
-+ cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
-+
-+ /* With -mminimal-toc we may generate an extra use of r2 below. */
-+ if (!TARGET_SINGLE_PIC_BASE
-+ && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
-+ cfun->machine->r2_setup_needed = true;
-+ }
-+
-+
- if (flag_stack_usage_info)
- current_function_static_stack_size = info->total_size;
-
-@@ -19766,7 +22951,7 @@
-
- insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
- rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
-- treg, GEN_INT (-info->total_size));
-+ treg, GEN_INT (-info->total_size), NULL_RTX);
- sp_off = frame_off = info->total_size;
- }
-
-@@ -19851,7 +23036,7 @@
-
- insn = emit_move_insn (mem, reg);
- rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
-- NULL_RTX, NULL_RTX);
-+ NULL_RTX, NULL_RTX, NULL_RTX);
- END_USE (0);
- }
- }
-@@ -19858,7 +23043,7 @@
-
- /* If we need to save CR, put it into r12 or r11. Choose r12 except when
- r12 will be needed by out-of-line gpr restore. */
-- cr_save_regno = (DEFAULT_ABI == ABI_AIX
-+ cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- && !(strategy & (SAVE_INLINE_GPRS
- | SAVE_NOINLINE_GPRS_SAVES_LR))
- ? 11 : 12);
-@@ -19867,21 +23052,9 @@
- && REGNO (frame_reg_rtx) != cr_save_regno
- && !(using_static_chain_p && cr_save_regno == 11))
- {
-- rtx set;
--
- cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
- START_USE (cr_save_regno);
-- insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
-- RTX_FRAME_RELATED_P (insn) = 1;
-- /* Now, there's no way that dwarf2out_frame_debug_expr is going
-- to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
-- But that's OK. All we have to do is specify that _one_ condition
-- code register is saved in this stack slot. The thrower's epilogue
-- will then restore all the call-saved registers.
-- We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
-- set = gen_rtx_SET (VOIDmode, cr_save_rtx,
-- gen_rtx_REG (SImode, CR2_REGNO));
-- add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
-+ rs6000_emit_move_from_cr (cr_save_rtx);
- }
-
- /* Do any required saving of fpr's. If only one or two to save, do
-@@ -19919,7 +23092,7 @@
- info->lr_save_offset,
- DFmode, sel);
- rs6000_frame_related (insn, ptr_reg, sp_off,
-- NULL_RTX, NULL_RTX);
-+ NULL_RTX, NULL_RTX, NULL_RTX);
- if (lr)
- END_USE (0);
- }
-@@ -19998,7 +23171,7 @@
- SAVRES_SAVE | SAVRES_GPR);
-
- rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,
-- NULL_RTX, NULL_RTX);
-+ NULL_RTX, NULL_RTX, NULL_RTX);
- }
-
- /* Move the static chain pointer back. */
-@@ -20048,7 +23221,7 @@
- info->lr_save_offset + ptr_off,
- reg_mode, sel);
- rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
-- NULL_RTX, NULL_RTX);
-+ NULL_RTX, NULL_RTX, NULL_RTX);
- if (lr)
- END_USE (0);
- }
-@@ -20064,7 +23237,7 @@
- info->gp_save_offset + frame_off + reg_size * i);
- insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
- rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
-- NULL_RTX, NULL_RTX);
-+ NULL_RTX, NULL_RTX, NULL_RTX);
- }
- else if (!WORLD_SAVE_P (info))
- {
-@@ -20133,7 +23306,8 @@
- be updated if we arrived at this function via a plt call or
- toc adjusting stub. */
- emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
-- toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;
-+ toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
-+ + RS6000_TOC_SAVE_SLOT);
- hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
- emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
- compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
-@@ -20152,7 +23326,7 @@
- LABEL_NUSES (toc_save_done) += 1;
-
- save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
-- TOC_REGNUM, frame_off + 5 * reg_size,
-+ TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
- sp_off - frame_off);
-
- emit_label (toc_save_done);
-@@ -20192,28 +23366,123 @@
- rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
- GEN_INT (info->cr_save_offset + frame_off));
- rtx mem = gen_frame_mem (SImode, addr);
-- /* See the large comment above about why CR2_REGNO is used. */
-- rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
-
- /* If we didn't copy cr before, do so now using r0. */
- if (cr_save_rtx == NULL_RTX)
- {
-- rtx set;
--
- START_USE (0);
- cr_save_rtx = gen_rtx_REG (SImode, 0);
-- insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
-- RTX_FRAME_RELATED_P (insn) = 1;
-- set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
-- add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
-+ rs6000_emit_move_from_cr (cr_save_rtx);
- }
-- insn = emit_move_insn (mem, cr_save_rtx);
-+
-+ /* Saving CR requires a two-instruction sequence: one instruction
-+ to move the CR to a general-purpose register, and a second
-+ instruction that stores the GPR to memory.
-+
-+ We do not emit any DWARF CFI records for the first of these,
-+ because we cannot properly represent the fact that CR is saved in
-+ a register. One reason is that we cannot express that multiple
-+ CR fields are saved; another reason is that on 64-bit, the size
-+ of the CR register in DWARF (4 bytes) differs from the size of
-+ a general-purpose register.
-+
-+ This means if any intervening instruction were to clobber one of
-+ the call-saved CR fields, we'd have incorrect CFI. To prevent
-+ this from happening, we mark the store to memory as a use of
-+ those CR fields, which prevents any such instruction from being
-+ scheduled in between the two instructions. */
-+ rtx crsave_v[9];
-+ int n_crsave = 0;
-+ int i;
-+
-+ crsave_v[n_crsave++] = gen_rtx_SET (VOIDmode, mem, cr_save_rtx);
-+ for (i = 0; i < 8; i++)
-+ if (save_reg_p (CR0_REGNO + i))
-+ crsave_v[n_crsave++]
-+ = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
-+
-+ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
-+ gen_rtvec_v (n_crsave, crsave_v)));
- END_USE (REGNO (cr_save_rtx));
-
-- rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
-- NULL_RTX, NULL_RTX);
-+ /* Now, there's no way that dwarf2out_frame_debug_expr is going to
-+ understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
-+ so we need to construct a frame expression manually. */
-+ RTX_FRAME_RELATED_P (insn) = 1;
-+
-+ /* Update address to be stack-pointer relative, like
-+ rs6000_frame_related would do. */
-+ addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
-+ GEN_INT (info->cr_save_offset + sp_off));
-+ mem = gen_frame_mem (SImode, addr);
-+
-+ if (DEFAULT_ABI == ABI_ELFv2)
-+ {
-+ /* In the ELFv2 ABI we generate separate CFI records for each
-+ CR field that was actually saved. They all point to the
-+ same 32-bit stack slot. */
-+ rtx crframe[8];
-+ int n_crframe = 0;
-+
-+ for (i = 0; i < 8; i++)
-+ if (save_reg_p (CR0_REGNO + i))
-+ {
-+ crframe[n_crframe]
-+ = gen_rtx_SET (VOIDmode, mem,
-+ gen_rtx_REG (SImode, CR0_REGNO + i));
-+
-+ RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
-+ n_crframe++;
-+ }
-+
-+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,
-+ gen_rtx_PARALLEL (VOIDmode,
-+ gen_rtvec_v (n_crframe, crframe)));
-+ }
-+ else
-+ {
-+ /* In other ABIs, by convention, we use a single CR regnum to
-+ represent the fact that all call-saved CR fields are saved.
-+ We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
-+ rtx set = gen_rtx_SET (VOIDmode, mem,
-+ gen_rtx_REG (SImode, CR2_REGNO));
-+ add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
-+ }
- }
-
-+ /* In the ELFv2 ABI we need to save all call-saved CR fields into
-+ *separate* slots if the routine calls __builtin_eh_return, so
-+ that they can be independently restored by the unwinder. */
-+ if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
-+ {
-+ int i, cr_off = info->ehcr_offset;
-+ rtx crsave;
-+
-+ /* ??? We might get better performance by using multiple mfocrf
-+ instructions. */
-+ crsave = gen_rtx_REG (SImode, 0);
-+ emit_insn (gen_movesi_from_cr (crsave));
-+
-+ for (i = 0; i < 8; i++)
-+ if (!call_used_regs[CR0_REGNO + i])
-+ {
-+ rtvec p = rtvec_alloc (2);
-+ RTVEC_ELT (p, 0)
-+ = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
-+ RTVEC_ELT (p, 1)
-+ = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
-+
-+ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
-+
-+ RTX_FRAME_RELATED_P (insn) = 1;
-+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,
-+ gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
-+ sp_reg_rtx, cr_off + sp_off));
-+
-+ cr_off += reg_size;
-+ }
-+ }
-+
- /* Update stack and set back pointer unless this is V.4,
- for which it was done previously. */
- if (!WORLD_SAVE_P (info) && info->push_p
-@@ -20291,7 +23560,7 @@
- info->altivec_save_offset + ptr_off,
- 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
- rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
-- NULL_RTX, NULL_RTX);
-+ NULL_RTX, NULL_RTX, NULL_RTX);
- if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
- {
- /* The oddity mentioned above clobbered our frame reg. */
-@@ -20307,7 +23576,7 @@
- for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
- if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
- {
-- rtx areg, savereg, mem;
-+ rtx areg, savereg, mem, split_reg;
- int offset;
-
- offset = (info->altivec_save_offset + frame_off
-@@ -20325,8 +23594,18 @@
-
- insn = emit_move_insn (mem, savereg);
-
-+ /* When we split a VSX store into two insns, we need to make
-+ sure the DWARF info knows which register we are storing.
-+ Pass it in to be used on the appropriate note. */
-+ if (!BYTES_BIG_ENDIAN
-+ && GET_CODE (PATTERN (insn)) == SET
-+ && GET_CODE (SET_SRC (PATTERN (insn))) == VEC_SELECT)
-+ split_reg = savereg;
-+ else
-+ split_reg = NULL_RTX;
-+
- rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
-- areg, GEN_INT (offset));
-+ areg, GEN_INT (offset), split_reg);
- }
- }
-
-@@ -20350,7 +23629,8 @@
- be using r12 as frame_reg_rtx and r11 as the static chain
- pointer for nested functions. */
- save_regno = 12;
-- if (DEFAULT_ABI == ABI_AIX && !using_static_chain_p)
-+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ && !using_static_chain_p)
- save_regno = 11;
- else if (REGNO (frame_reg_rtx) == 12)
- {
-@@ -20389,7 +23669,7 @@
- can use register 0. This allows us to use a plain 'blr' to return
- from the procedure more often. */
- int save_LR_around_toc_setup = (TARGET_ELF
-- && DEFAULT_ABI != ABI_AIX
-+ && DEFAULT_ABI == ABI_V4
- && flag_pic
- && ! info->lr_save_p
- && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
-@@ -20451,7 +23731,7 @@
- if (rs6000_save_toc_in_prologue_p ())
- {
- rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
-- emit_insn (gen_frame_store (reg, sp_reg_rtx, 5 * reg_size));
-+ emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
- }
- }
-
-@@ -20492,6 +23772,49 @@
- }
- }
-
-+ /* ELFv2 ABI r2 setup code and local entry point. This must follow
-+ immediately after the global entry point label. */
-+ if (DEFAULT_ABI == ABI_ELFv2 && cfun->machine->r2_setup_needed)
-+ {
-+ const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
-+
-+ fprintf (file, "0:\taddis 2,12,.TOC.-0b@ha\n");
-+ fprintf (file, "\taddi 2,2,.TOC.-0b@l\n");
-+
-+ fputs ("\t.localentry\t", file);
-+ assemble_name (file, name);
-+ fputs (",.-", file);
-+ assemble_name (file, name);
-+ fputs ("\n", file);
-+ }
-+
-+ /* Output -mprofile-kernel code. This needs to be done here instead of
-+ in output_function_profile since it must go after the ELFv2 ABI
-+ local entry point. */
-+ if (TARGET_PROFILE_KERNEL)
-+ {
-+ gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
-+ gcc_assert (!TARGET_32BIT);
-+
-+ asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
-+ asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
-+
-+ /* In the ELFv2 ABI we have no compiler stack word. It must be
-+ the resposibility of _mcount to preserve the static chain
-+ register if required. */
-+ if (DEFAULT_ABI != ABI_ELFv2
-+ && cfun->static_chain_decl != NULL)
-+ {
-+ asm_fprintf (file, "\tstd %s,24(%s)\n",
-+ reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
-+ fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
-+ asm_fprintf (file, "\tld %s,24(%s)\n",
-+ reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
-+ }
-+ else
-+ fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
-+ }
-+
- rs6000_pic_labelno++;
- }
-
-@@ -20544,6 +23867,7 @@
-
- if (using_mfcr_multiple && count > 1)
- {
-+ rtx insn;
- rtvec p;
- int ndx;
-
-@@ -20561,16 +23885,43 @@
- gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
- ndx++;
- }
-- emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
-+ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
- gcc_assert (ndx == count);
-+
-+ /* For the ELFv2 ABI we generate a CFA_RESTORE for each
-+ CR field separately. */
-+ if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
-+ {
-+ for (i = 0; i < 8; i++)
-+ if (save_reg_p (CR0_REGNO + i))
-+ add_reg_note (insn, REG_CFA_RESTORE,
-+ gen_rtx_REG (SImode, CR0_REGNO + i));
-+
-+ RTX_FRAME_RELATED_P (insn) = 1;
-+ }
- }
- else
- for (i = 0; i < 8; i++)
- if (save_reg_p (CR0_REGNO + i))
-- emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, CR0_REGNO + i),
-- reg));
-+ {
-+ rtx insn = emit_insn (gen_movsi_to_cr_one
-+ (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
-
-- if (!exit_func && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
-+ /* For the ELFv2 ABI we generate a CFA_RESTORE for each
-+ CR field separately, attached to the insn that in fact
-+ restores this particular CR field. */
-+ if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
-+ {
-+ add_reg_note (insn, REG_CFA_RESTORE,
-+ gen_rtx_REG (SImode, CR0_REGNO + i));
-+
-+ RTX_FRAME_RELATED_P (insn) = 1;
-+ }
-+ }
-+
-+ /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
-+ if (!exit_func && DEFAULT_ABI != ABI_ELFv2
-+ && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
- {
- rtx insn = get_last_insn ();
- rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
-@@ -20611,10 +23962,22 @@
- static rtx
- add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
- {
-- if (info->cr_save_p)
-+ if (DEFAULT_ABI == ABI_ELFv2)
-+ {
-+ int i;
-+ for (i = 0; i < 8; i++)
-+ if (save_reg_p (CR0_REGNO + i))
-+ {
-+ rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
-+ cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
-+ cfa_restores);
-+ }
-+ }
-+ else if (info->cr_save_p)
- cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
- gen_rtx_REG (SImode, CR2_REGNO),
- cfa_restores);
-+
- if (info->lr_save_p)
- cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
- gen_rtx_REG (Pmode, LR_REGNO),
-@@ -21112,6 +24475,35 @@
- || (!restoring_GPRs_inline
- && info->first_fp_reg_save == 64));
-
-+ /* In the ELFv2 ABI we need to restore all call-saved CR fields from
-+ *separate* slots if the routine calls __builtin_eh_return, so
-+ that they can be independently restored by the unwinder. */
-+ if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
-+ {
-+ int i, cr_off = info->ehcr_offset;
-+
-+ for (i = 0; i < 8; i++)
-+ if (!call_used_regs[CR0_REGNO + i])
-+ {
-+ rtx reg = gen_rtx_REG (SImode, 0);
-+ emit_insn (gen_frame_load (reg, frame_reg_rtx,
-+ cr_off + frame_off));
-+
-+ insn = emit_insn (gen_movsi_to_cr_one
-+ (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
-+
-+ if (!exit_func && flag_shrink_wrap)
-+ {
-+ add_reg_note (insn, REG_CFA_RESTORE,
-+ gen_rtx_REG (SImode, CR0_REGNO + i));
-+
-+ RTX_FRAME_RELATED_P (insn) = 1;
-+ }
-+
-+ cr_off += reg_size;
-+ }
-+ }
-+
- /* Get the old lr if we saved it. If we are restoring registers
- out-of-line, then the out-of-line routines can do this for us. */
- if (restore_lr && restoring_GPRs_inline)
-@@ -21155,7 +24547,7 @@
- {
- rtx reg = gen_rtx_REG (reg_mode, 2);
- emit_insn (gen_frame_load (reg, frame_reg_rtx,
-- frame_off + 5 * reg_size));
-+ frame_off + RS6000_TOC_SAVE_SLOT));
- }
-
- for (i = 0; ; ++i)
-@@ -21441,6 +24833,7 @@
- if (! restoring_FPRs_inline)
- {
- int i;
-+ int reg;
- rtx sym;
-
- if (flag_shrink_wrap)
-@@ -21449,10 +24842,9 @@
- sym = rs6000_savres_routine_sym (info,
- SAVRES_FPR | (lr ? SAVRES_LR : 0));
- RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
-- RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
-- gen_rtx_REG (Pmode,
-- DEFAULT_ABI == ABI_AIX
-- ? 1 : 11));
-+ reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
-+ RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
-+
- for (i = 0; i < 64 - info->first_fp_reg_save; i++)
- {
- rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
-@@ -21530,7 +24922,8 @@
-
- System V.4 Powerpc's (and the embedded ABI derived from it) use a
- different traceback table. */
-- if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
-+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ && ! flag_inhibit_size_directive
- && rs6000_traceback != traceback_none && !cfun->is_thunk)
- {
- const char *fname = NULL;
-@@ -21858,6 +25251,12 @@
- SIBLING_CALL_P (insn) = 1;
- emit_barrier ();
-
-+ /* Ensure we have a global entry point for the thunk. ??? We could
-+ avoid that if the target routine doesn't need a global entry point,
-+ but we do not know whether this is the case at this point. */
-+ if (DEFAULT_ABI == ABI_ELFv2)
-+ cfun->machine->r2_setup_needed = true;
-+
- /* Run just enough of rest_of_compilation to get the insns emitted.
- There's not really enough bulk here to make other passes such as
- instruction scheduling worth while. Note that use_thunk calls
-@@ -22554,7 +25953,7 @@
- if (TARGET_PROFILE_KERNEL)
- return;
-
-- if (DEFAULT_ABI == ABI_AIX)
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- {
- #ifndef NO_PROFILE_COUNTERS
- # define NO_PROFILE_COUNTERS 0
-@@ -22698,29 +26097,9 @@
- break;
-
- case ABI_AIX:
-+ case ABI_ELFv2:
- case ABI_DARWIN:
-- if (!TARGET_PROFILE_KERNEL)
-- {
-- /* Don't do anything, done in output_profile_hook (). */
-- }
-- else
-- {
-- gcc_assert (!TARGET_32BIT);
--
-- asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
-- asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
--
-- if (cfun->static_chain_decl != NULL)
-- {
-- asm_fprintf (file, "\tstd %s,24(%s)\n",
-- reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
-- fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
-- asm_fprintf (file, "\tld %s,24(%s)\n",
-- reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
-- }
-- else
-- fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
-- }
-+ /* Don't do anything, done in output_profile_hook (). */
- break;
- }
- }
-@@ -22846,6 +26225,7 @@
- || rs6000_cpu_attr == CPU_POWER4
- || rs6000_cpu_attr == CPU_POWER5
- || rs6000_cpu_attr == CPU_POWER7
-+ || rs6000_cpu_attr == CPU_POWER8
- || rs6000_cpu_attr == CPU_CELL)
- && recog_memoized (dep_insn)
- && (INSN_CODE (dep_insn) >= 0))
-@@ -23128,7 +26508,8 @@
- if (rs6000_cpu_attr == CPU_CELL)
- return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
-
-- if (rs6000_sched_groups)
-+ if (rs6000_sched_groups
-+ && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
- {
- enum attr_type type = get_attr_type (insn);
- if (type == TYPE_LOAD_EXT_U
-@@ -23153,7 +26534,8 @@
- || GET_CODE (PATTERN (insn)) == CLOBBER)
- return false;
-
-- if (rs6000_sched_groups)
-+ if (rs6000_sched_groups
-+ && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
- {
- enum attr_type type = get_attr_type (insn);
- if (type == TYPE_LOAD_U || type == TYPE_STORE_U
-@@ -23432,6 +26814,8 @@
- case CPU_POWER6:
- case CPU_POWER7:
- return 5;
-+ case CPU_POWER8:
-+ return 7;
- default:
- return 1;
- }
-@@ -24059,6 +27443,39 @@
- break;
- }
- break;
-+ case PROCESSOR_POWER8:
-+ type = get_attr_type (insn);
-+
-+ switch (type)
-+ {
-+ case TYPE_CR_LOGICAL:
-+ case TYPE_DELAYED_CR:
-+ case TYPE_MFCR:
-+ case TYPE_MFCRF:
-+ case TYPE_MTCR:
-+ case TYPE_COMPARE:
-+ case TYPE_DELAYED_COMPARE:
-+ case TYPE_VAR_DELAYED_COMPARE:
-+ case TYPE_IMUL_COMPARE:
-+ case TYPE_LMUL_COMPARE:
-+ case TYPE_SYNC:
-+ case TYPE_ISYNC:
-+ case TYPE_LOAD_L:
-+ case TYPE_STORE_C:
-+ case TYPE_LOAD_U:
-+ case TYPE_LOAD_UX:
-+ case TYPE_LOAD_EXT:
-+ case TYPE_LOAD_EXT_U:
-+ case TYPE_LOAD_EXT_UX:
-+ case TYPE_STORE_UX:
-+ case TYPE_VECSTORE:
-+ case TYPE_MFJMPR:
-+ case TYPE_MTJMPR:
-+ return true;
-+ default:
-+ break;
-+ }
-+ break;
- default:
- break;
- }
-@@ -24137,6 +27554,25 @@
- break;
- }
- break;
-+ case PROCESSOR_POWER8:
-+ type = get_attr_type (insn);
-+
-+ switch (type)
-+ {
-+ case TYPE_MFCR:
-+ case TYPE_MTCR:
-+ case TYPE_ISYNC:
-+ case TYPE_SYNC:
-+ case TYPE_LOAD_L:
-+ case TYPE_STORE_C:
-+ case TYPE_LOAD_EXT_U:
-+ case TYPE_LOAD_EXT_UX:
-+ case TYPE_STORE_UX:
-+ return true;
-+ default:
-+ break;
-+ }
-+ break;
- default:
- break;
- }
-@@ -24226,8 +27662,9 @@
- if (can_issue_more && !is_branch_slot_insn (next_insn))
- can_issue_more--;
-
-- /* Power6 and Power7 have special group ending nop. */
-- if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7)
-+ /* Do we have a special group ending nop? */
-+ if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7
-+ || rs6000_cpu_attr == CPU_POWER8)
- {
- nop = gen_group_ending_nop ();
- emit_insn_before (nop, next_insn);
-@@ -24598,6 +28035,11 @@
- ret = (TARGET_32BIT) ? 12 : 24;
- break;
-
-+ case ABI_ELFv2:
-+ gcc_assert (!TARGET_32BIT);
-+ ret = 32;
-+ break;
-+
- case ABI_DARWIN:
- case ABI_V4:
- ret = (TARGET_32BIT) ? 40 : 48;
-@@ -24653,6 +28095,7 @@
- break;
-
- /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
-+ case ABI_ELFv2:
- case ABI_DARWIN:
- case ABI_V4:
- emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
-@@ -24743,6 +28186,9 @@
- unsigned_p = TYPE_UNSIGNED (type);
- switch (mode)
- {
-+ case TImode:
-+ result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
-+ break;
- case DImode:
- result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
- break;
-@@ -24947,7 +28393,7 @@
- static void
- rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
- {
-- if (DEFAULT_ABI == ABI_AIX
-+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- && TARGET_MINIMAL_TOC
- && !TARGET_RELOCATABLE)
- {
-@@ -24968,7 +28414,8 @@
- else
- fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
- }
-- else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
-+ else if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ && !TARGET_RELOCATABLE)
- fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
- else
- {
-@@ -25518,7 +28965,7 @@
- {
- if (flag_pic)
- return 3;
-- else if (DEFAULT_ABI == ABI_AIX)
-+ else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- return 2;
- else
- return 0;
-@@ -25594,7 +29041,7 @@
- void
- rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
- {
-- if (TARGET_64BIT)
-+ if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
- {
- fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
- ASM_OUTPUT_LABEL (file, name);
-@@ -25660,8 +29107,7 @@
- fprintf (file, "%s:\n", desc_name);
- fprintf (file, "\t.long %s\n", orig_name);
- fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
-- if (DEFAULT_ABI == ABI_AIX)
-- fputs ("\t.long 0\n", file);
-+ fputs ("\t.long 0\n", file);
- fprintf (file, "\t.previous\n");
- }
- ASM_OUTPUT_LABEL (file, name);
-@@ -25690,7 +29136,7 @@
- }
- #endif
- #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
-- if (TARGET_32BIT)
-+ if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
- file_end_indicate_exec_stack ();
- #endif
- }
-@@ -25829,10 +29275,23 @@
- name, suffix[smclass], flags & SECTION_ENTSIZE);
- }
-
-+#define IN_NAMED_SECTION(DECL) \
-+ ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
-+ && DECL_SECTION_NAME (DECL) != NULL_TREE)
-+
- static section *
- rs6000_xcoff_select_section (tree decl, int reloc,
-- unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
-+ unsigned HOST_WIDE_INT align)
- {
-+ /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
-+ named section. */
-+ if (align > BIGGEST_ALIGNMENT)
-+ {
-+ resolve_unique_section (decl, reloc, true);
-+ if (IN_NAMED_SECTION (decl))
-+ return get_named_section (decl, NULL, reloc);
-+ }
-+
- if (decl_readonly_section (decl, reloc))
- {
- if (TREE_PUBLIC (decl))
-@@ -25870,10 +29329,12 @@
- {
- const char *name;
-
-- /* Use select_section for private and uninitialized data. */
-+ /* Use select_section for private data and uninitialized data with
-+ alignment <= BIGGEST_ALIGNMENT. */
- if (!TREE_PUBLIC (decl)
- || DECL_COMMON (decl)
-- || DECL_INITIAL (decl) == NULL_TREE
-+ || (DECL_INITIAL (decl) == NULL_TREE
-+ && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
- || DECL_INITIAL (decl) == error_mark_node
- || (flag_zero_initialized_in_bss
- && initializer_zerop (DECL_INITIAL (decl))))
-@@ -26430,7 +29891,8 @@
- /* For those processors that have slow LR/CTR moves, make them more
- expensive than memory in order to bias spills to memory .*/
- else if ((rs6000_cpu == PROCESSOR_POWER6
-- || rs6000_cpu == PROCESSOR_POWER7)
-+ || rs6000_cpu == PROCESSOR_POWER7
-+ || rs6000_cpu == PROCESSOR_POWER8)
- && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
- ret = 6 * hard_regno_nregs[0][mode];
-
-@@ -26440,7 +29902,7 @@
- }
-
- /* If we have VSX, we can easily move between FPR or Altivec registers. */
-- else if (VECTOR_UNIT_VSX_P (mode)
-+ else if (VECTOR_MEM_VSX_P (mode)
- && reg_classes_intersect_p (to, VSX_REGS)
- && reg_classes_intersect_p (from, VSX_REGS))
- ret = 2 * hard_regno_nregs[32][mode];
-@@ -26481,7 +29943,8 @@
-
- if (reg_classes_intersect_p (rclass, GENERAL_REGS))
- ret = 4 * hard_regno_nregs[0][mode];
-- else if (reg_classes_intersect_p (rclass, FLOAT_REGS))
-+ else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
-+ || reg_classes_intersect_p (rclass, VSX_REGS)))
- ret = 4 * hard_regno_nregs[32][mode];
- else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
- ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
-@@ -26643,54 +30106,26 @@
- emit_insn (gen_rtx_SET (VOIDmode, dst, r));
- }
-
--/* Newton-Raphson approximation of floating point divide with just 2 passes
-- (either single precision floating point, or newer machines with higher
-- accuracy estimates). Support both scalar and vector divide. Assumes no
-- trapping math and finite arguments. */
-+/* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
-+ add a reg_note saying that this was a division. Support both scalar and
-+ vector divide. Assumes no trapping math and finite arguments. */
-
--static void
--rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)
-+void
-+rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
- {
- enum machine_mode mode = GET_MODE (dst);
-- rtx x0, e0, e1, y1, u0, v0;
-- enum insn_code code = optab_handler (smul_optab, mode);
-- insn_gen_fn gen_mul = GEN_FCN (code);
-- rtx one = rs6000_load_constant_and_splat (mode, dconst1);
-+ rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
-+ int i;
-
-- gcc_assert (code != CODE_FOR_nothing);
-+ /* Low precision estimates guarantee 5 bits of accuracy. High
-+ precision estimates guarantee 14 bits of accuracy. SFmode
-+ requires 23 bits of accuracy. DFmode requires 52 bits of
-+ accuracy. Each pass at least doubles the accuracy, leading
-+ to the following. */
-+ int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
-+ if (mode == DFmode || mode == V2DFmode)
-+ passes++;
-
-- /* x0 = 1./d estimate */
-- x0 = gen_reg_rtx (mode);
-- emit_insn (gen_rtx_SET (VOIDmode, x0,
-- gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
-- UNSPEC_FRES)));
--
-- e0 = gen_reg_rtx (mode);
-- rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */
--
-- e1 = gen_reg_rtx (mode);
-- rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */
--
-- y1 = gen_reg_rtx (mode);
-- rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */
--
-- u0 = gen_reg_rtx (mode);
-- emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */
--
-- v0 = gen_reg_rtx (mode);
-- rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */
--
-- rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */
--}
--
--/* Newton-Raphson approximation of floating point divide that has a low
-- precision estimate. Assumes no trapping math and finite arguments. */
--
--static void
--rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)
--{
-- enum machine_mode mode = GET_MODE (dst);
-- rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
- enum insn_code code = optab_handler (smul_optab, mode);
- insn_gen_fn gen_mul = GEN_FCN (code);
-
-@@ -26704,47 +30139,45 @@
- gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
- UNSPEC_FRES)));
-
-- e0 = gen_reg_rtx (mode);
-- rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */
-+ /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
-+ if (passes > 1) {
-
-- y1 = gen_reg_rtx (mode);
-- rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */
-+ /* e0 = 1. - d * x0 */
-+ e0 = gen_reg_rtx (mode);
-+ rs6000_emit_nmsub (e0, d, x0, one);
-
-- e1 = gen_reg_rtx (mode);
-- emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */
-+ /* x1 = x0 + e0 * x0 */
-+ x1 = gen_reg_rtx (mode);
-+ rs6000_emit_madd (x1, e0, x0, x0);
-
-- y2 = gen_reg_rtx (mode);
-- rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */
-+ for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
-+ ++i, xprev = xnext, eprev = enext) {
-+
-+ /* enext = eprev * eprev */
-+ enext = gen_reg_rtx (mode);
-+ emit_insn (gen_mul (enext, eprev, eprev));
-
-- e2 = gen_reg_rtx (mode);
-- emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */
-+ /* xnext = xprev + enext * xprev */
-+ xnext = gen_reg_rtx (mode);
-+ rs6000_emit_madd (xnext, enext, xprev, xprev);
-+ }
-
-- y3 = gen_reg_rtx (mode);
-- rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */
-+ } else
-+ xprev = x0;
-
-- u0 = gen_reg_rtx (mode);
-- emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */
-+ /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
-
-- v0 = gen_reg_rtx (mode);
-- rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */
-+ /* u = n * xprev */
-+ u = gen_reg_rtx (mode);
-+ emit_insn (gen_mul (u, n, xprev));
-
-- rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */
--}
-+ /* v = n - (d * u) */
-+ v = gen_reg_rtx (mode);
-+ rs6000_emit_nmsub (v, d, u, n);
-
--/* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
-- add a reg_note saying that this was a division. Support both scalar and
-- vector divide. Assumes no trapping math and finite arguments. */
-+ /* dst = (v * xprev) + u */
-+ rs6000_emit_madd (dst, v, xprev, u);
-
--void
--rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
--{
-- enum machine_mode mode = GET_MODE (dst);
--
-- if (RS6000_RECIP_HIGH_PRECISION_P (mode))
-- rs6000_emit_swdiv_high_precision (dst, n, d);
-- else
-- rs6000_emit_swdiv_low_precision (dst, n, d);
--
- if (note_p)
- add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
- }
-@@ -26758,7 +30191,16 @@
- enum machine_mode mode = GET_MODE (src);
- rtx x0 = gen_reg_rtx (mode);
- rtx y = gen_reg_rtx (mode);
-- int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;
-+
-+ /* Low precision estimates guarantee 5 bits of accuracy. High
-+ precision estimates guarantee 14 bits of accuracy. SFmode
-+ requires 23 bits of accuracy. DFmode requires 52 bits of
-+ accuracy. Each pass at least doubles the accuracy, leading
-+ to the following. */
-+ int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
-+ if (mode == DFmode || mode == V2DFmode)
-+ passes++;
-+
- REAL_VALUE_TYPE dconst3_2;
- int i;
- rtx halfthree;
-@@ -26920,6 +30362,136 @@
- }
- }
-
-+/* Expand an Altivec constant permutation for little endian mode.
-+ There are two issues: First, the two input operands must be
-+ swapped so that together they form a double-wide array in LE
-+ order. Second, the vperm instruction has surprising behavior
-+ in LE mode: it interprets the elements of the source vectors
-+ in BE mode ("left to right") and interprets the elements of
-+ the destination vector in LE mode ("right to left"). To
-+ correct for this, we must subtract each element of the permute
-+ control vector from 31.
-+
-+ For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
-+ with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
-+ We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
-+ serve as the permute control vector. Then, in BE mode,
-+
-+ vperm 9,10,11,12
-+
-+ places the desired result in vr9. However, in LE mode the
-+ vector contents will be
-+
-+ vr10 = 00000003 00000002 00000001 00000000
-+ vr11 = 00000007 00000006 00000005 00000004
-+
-+ The result of the vperm using the same permute control vector is
-+
-+ vr9 = 05000000 07000000 01000000 03000000
-+
-+ That is, the leftmost 4 bytes of vr10 are interpreted as the
-+ source for the rightmost 4 bytes of vr9, and so on.
-+
-+ If we change the permute control vector to
-+
-+ vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
-+
-+ and issue
-+
-+ vperm 9,11,10,12
-+
-+ we get the desired
-+
-+ vr9 = 00000006 00000004 00000002 00000000. */
-+
-+void
-+altivec_expand_vec_perm_const_le (rtx operands[4])
-+{
-+ unsigned int i;
-+ rtx perm[16];
-+ rtx constv, unspec;
-+ rtx target = operands[0];
-+ rtx op0 = operands[1];
-+ rtx op1 = operands[2];
-+ rtx sel = operands[3];
-+
-+ /* Unpack and adjust the constant selector. */
-+ for (i = 0; i < 16; ++i)
-+ {
-+ rtx e = XVECEXP (sel, 0, i);
-+ unsigned int elt = 31 - (INTVAL (e) & 31);
-+ perm[i] = GEN_INT (elt);
-+ }
-+
-+ /* Expand to a permute, swapping the inputs and using the
-+ adjusted selector. */
-+ if (!REG_P (op0))
-+ op0 = force_reg (V16QImode, op0);
-+ if (!REG_P (op1))
-+ op1 = force_reg (V16QImode, op1);
-+
-+ constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
-+ constv = force_reg (V16QImode, constv);
-+ unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
-+ UNSPEC_VPERM);
-+ if (!REG_P (target))
-+ {
-+ rtx tmp = gen_reg_rtx (V16QImode);
-+ emit_move_insn (tmp, unspec);
-+ unspec = tmp;
-+ }
-+
-+ emit_move_insn (target, unspec);
-+}
-+
-+/* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
-+ permute control vector. But here it's not a constant, so we must
-+ generate a vector NAND or NOR to do the adjustment. */
-+
-+void
-+altivec_expand_vec_perm_le (rtx operands[4])
-+{
-+ rtx notx, iorx, unspec;
-+ rtx target = operands[0];
-+ rtx op0 = operands[1];
-+ rtx op1 = operands[2];
-+ rtx sel = operands[3];
-+ rtx tmp = target;
-+ rtx norreg = gen_reg_rtx (V16QImode);
-+ enum machine_mode mode = GET_MODE (target);
-+
-+ /* Get everything in regs so the pattern matches. */
-+ if (!REG_P (op0))
-+ op0 = force_reg (mode, op0);
-+ if (!REG_P (op1))
-+ op1 = force_reg (mode, op1);
-+ if (!REG_P (sel))
-+ sel = force_reg (V16QImode, sel);
-+ if (!REG_P (target))
-+ tmp = gen_reg_rtx (mode);
-+
-+ /* Invert the selector with a VNAND if available, else a VNOR.
-+ The VNAND is preferred for future fusion opportunities. */
-+ notx = gen_rtx_NOT (V16QImode, sel);
-+ iorx = (TARGET_P8_VECTOR
-+ ? gen_rtx_IOR (V16QImode, notx, notx)
-+ : gen_rtx_AND (V16QImode, notx, notx));
-+ emit_insn (gen_rtx_SET (VOIDmode, norreg, iorx));
-+
-+ /* Permute with operands reversed and adjusted selector. */
-+ unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
-+ UNSPEC_VPERM);
-+
-+ /* Copy into target, possibly by way of a register. */
-+ if (!REG_P (target))
-+ {
-+ emit_move_insn (tmp, unspec);
-+ unspec = tmp;
-+ }
-+
-+ emit_move_insn (target, unspec);
-+}
-+
- /* Expand an Altivec constant permutation. Return true if we match
- an efficient implementation; false to fall back to VPERM. */
-
-@@ -26927,26 +30499,43 @@
- altivec_expand_vec_perm_const (rtx operands[4])
- {
- struct altivec_perm_insn {
-+ HOST_WIDE_INT mask;
- enum insn_code impl;
- unsigned char perm[16];
- };
- static const struct altivec_perm_insn patterns[] = {
-- { CODE_FOR_altivec_vpkuhum,
-+ { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
- { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
-- { CODE_FOR_altivec_vpkuwum,
-+ { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
- { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
-- { CODE_FOR_altivec_vmrghb,
-+ { OPTION_MASK_ALTIVEC,
-+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
-+ : CODE_FOR_altivec_vmrglb_direct),
- { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
-- { CODE_FOR_altivec_vmrghh,
-+ { OPTION_MASK_ALTIVEC,
-+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
-+ : CODE_FOR_altivec_vmrglh_direct),
- { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
-- { CODE_FOR_altivec_vmrghw,
-+ { OPTION_MASK_ALTIVEC,
-+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
-+ : CODE_FOR_altivec_vmrglw_direct),
- { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
-- { CODE_FOR_altivec_vmrglb,
-+ { OPTION_MASK_ALTIVEC,
-+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
-+ : CODE_FOR_altivec_vmrghb_direct),
- { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
-- { CODE_FOR_altivec_vmrglh,
-+ { OPTION_MASK_ALTIVEC,
-+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
-+ : CODE_FOR_altivec_vmrghh_direct),
- { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
-- { CODE_FOR_altivec_vmrglw,
-- { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
-+ { OPTION_MASK_ALTIVEC,
-+ (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
-+ : CODE_FOR_altivec_vmrghw_direct),
-+ { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
-+ { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgew,
-+ { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
-+ { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgow,
-+ { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
- };
-
- unsigned int i, j, elt, which;
-@@ -27003,7 +30592,9 @@
- break;
- if (i == 16)
- {
-- emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));
-+ if (!BYTES_BIG_ENDIAN)
-+ elt = 15 - elt;
-+ emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
- return true;
- }
-
-@@ -27014,9 +30605,10 @@
- break;
- if (i == 16)
- {
-+ int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
- x = gen_reg_rtx (V8HImode);
-- emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),
-- GEN_INT (elt / 2)));
-+ emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
-+ GEN_INT (field)));
- emit_move_insn (target, gen_lowpart (V16QImode, x));
- return true;
- }
-@@ -27032,9 +30624,10 @@
- break;
- if (i == 16)
- {
-+ int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
- x = gen_reg_rtx (V4SImode);
-- emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),
-- GEN_INT (elt / 4)));
-+ emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
-+ GEN_INT (field)));
- emit_move_insn (target, gen_lowpart (V16QImode, x));
- return true;
- }
-@@ -27046,6 +30639,9 @@
- {
- bool swapped;
-
-+ if ((patterns[j].mask & rs6000_isa_flags) == 0)
-+ continue;
-+
- elt = patterns[j].perm[0];
- if (perm[0] == elt)
- swapped = false;
-@@ -27069,7 +30665,30 @@
- enum machine_mode omode = insn_data[icode].operand[0].mode;
- enum machine_mode imode = insn_data[icode].operand[1].mode;
-
-- if (swapped)
-+ /* For little-endian, don't use vpkuwum and vpkuhum if the
-+ underlying vector type is not V4SI and V8HI, respectively.
-+ For example, using vpkuwum with a V8HI picks up the even
-+ halfwords (BE numbering) when the even halfwords (LE
-+ numbering) are what we need. */
-+ if (!BYTES_BIG_ENDIAN
-+ && icode == CODE_FOR_altivec_vpkuwum_direct
-+ && ((GET_CODE (op0) == REG
-+ && GET_MODE (op0) != V4SImode)
-+ || (GET_CODE (op0) == SUBREG
-+ && GET_MODE (XEXP (op0, 0)) != V4SImode)))
-+ continue;
-+ if (!BYTES_BIG_ENDIAN
-+ && icode == CODE_FOR_altivec_vpkuhum_direct
-+ && ((GET_CODE (op0) == REG
-+ && GET_MODE (op0) != V8HImode)
-+ || (GET_CODE (op0) == SUBREG
-+ && GET_MODE (XEXP (op0, 0)) != V8HImode)))
-+ continue;
-+
-+ /* For little-endian, the two input operands must be swapped
-+ (or swapped back) to ensure proper right-to-left numbering
-+ from 0 to 2N-1. */
-+ if (swapped ^ !BYTES_BIG_ENDIAN)
- x = op0, op0 = op1, op1 = x;
- if (imode != V16QImode)
- {
-@@ -27087,6 +30706,12 @@
- }
- }
-
-+ if (!BYTES_BIG_ENDIAN)
-+ {
-+ altivec_expand_vec_perm_const_le (operands);
-+ return true;
-+ }
-+
- return false;
- }
-
-@@ -27135,7 +30760,6 @@
- vmode = GET_MODE (target);
- gcc_assert (GET_MODE_NUNITS (vmode) == 2);
- dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);
--
- x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
- v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
- x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
-@@ -27231,7 +30855,7 @@
- unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
- rtx perm[16];
-
-- high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2);
-+ high = (highp ? 0 : nelt / 2);
- for (i = 0; i < nelt / 2; i++)
- {
- perm[i * 2] = GEN_INT (i + high);
-@@ -27286,6 +30910,8 @@
- {
- enum machine_mode mode;
- unsigned int regno;
-+ enum machine_mode elt_mode;
-+ int n_elts;
-
- /* Special handling for structs in darwin64. */
- if (TARGET_MACHO
-@@ -27305,6 +30931,36 @@
- /* Otherwise fall through to standard ABI rules. */
- }
-
-+ /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
-+ if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype), valtype,
-+ &elt_mode, &n_elts))
-+ {
-+ int first_reg, n_regs, i;
-+ rtx par;
-+
-+ if (SCALAR_FLOAT_MODE_P (elt_mode))
-+ {
-+ /* _Decimal128 must use even/odd register pairs. */
-+ first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
-+ n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
-+ }
-+ else
-+ {
-+ first_reg = ALTIVEC_ARG_RETURN;
-+ n_regs = 1;
-+ }
-+
-+ par = gen_rtx_PARALLEL (TYPE_MODE (valtype), rtvec_alloc (n_elts));
-+ for (i = 0; i < n_elts; i++)
-+ {
-+ rtx r = gen_rtx_REG (elt_mode, first_reg + i * n_regs);
-+ rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
-+ XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
-+ }
-+
-+ return par;
-+ }
-+
- if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
- {
- /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
-@@ -27417,6 +31073,13 @@
- }
-
-
-+/* Return true if we use LRA instead of reload pass. */
-+static bool
-+rs6000_lra_p (void)
-+{
-+ return rs6000_lra_flag;
-+}
-+
- /* Given FROM and TO register numbers, say whether this elimination is allowed.
- Frame pointer elimination is automatically handled.
-
-@@ -27679,22 +31342,33 @@
- {
- { "altivec", OPTION_MASK_ALTIVEC, false, true },
- { "cmpb", OPTION_MASK_CMPB, false, true },
-+ { "crypto", OPTION_MASK_CRYPTO, false, true },
-+ { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
- { "dlmzb", OPTION_MASK_DLMZB, false, true },
- { "fprnd", OPTION_MASK_FPRND, false, true },
- { "hard-dfp", OPTION_MASK_DFP, false, true },
-+ { "htm", OPTION_MASK_HTM, false, true },
- { "isel", OPTION_MASK_ISEL, false, true },
- { "mfcrf", OPTION_MASK_MFCRF, false, true },
- { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
- { "mulhw", OPTION_MASK_MULHW, false, true },
- { "multiple", OPTION_MASK_MULTIPLE, false, true },
-- { "update", OPTION_MASK_NO_UPDATE, true , true },
- { "popcntb", OPTION_MASK_POPCNTB, false, true },
- { "popcntd", OPTION_MASK_POPCNTD, false, true },
-+ { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
-+ { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
-+ { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
- { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
- { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
-+ { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
-+ { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
- { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
- { "string", OPTION_MASK_STRING, false, true },
-+ { "update", OPTION_MASK_NO_UPDATE, true , true },
-+ { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, false },
-+ { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, false },
- { "vsx", OPTION_MASK_VSX, false, true },
-+ { "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
- #ifdef OPTION_MASK_64BIT
- #if TARGET_AIX_OS
- { "aix64", OPTION_MASK_64BIT, false, false },
-@@ -27734,6 +31408,11 @@
- { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
- { "popcntd", RS6000_BTM_POPCNTD, false, false },
- { "cell", RS6000_BTM_CELL, false, false },
-+ { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
-+ { "crypto", RS6000_BTM_CRYPTO, false, false },
-+ { "htm", RS6000_BTM_HTM, false, false },
-+ { "hard-dfp", RS6000_BTM_DFP, false, false },
-+ { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
- };
-
- /* Option variables that we want to support inside attribute((target)) and
-@@ -28250,7 +31929,6 @@
- size_t cur_column;
- size_t max_column = 76;
- const char *comma = "";
-- const char *nl = "\n";
-
- if (indent)
- start_column += fprintf (file, "%*s", indent, "");
-@@ -28281,7 +31959,6 @@
- fprintf (stderr, ", \\\n%*s", (int)start_column, "");
- cur_column = start_column + len;
- comma = "";
-- nl = "\n\n";
- }
-
- fprintf (file, "%s%s%s%s", comma, prefix, no_str,
-@@ -28291,7 +31968,7 @@
- }
- }
-
-- fputs (nl, file);
-+ fputs ("\n", file);
- }
-
- /* Helper function to print the current isa options on a line. */
-@@ -28467,118 +32144,149 @@
- }
-
-
--/* A function pointer under AIX is a pointer to a data area whose first word
-- contains the actual address of the function, whose second word contains a
-- pointer to its TOC, and whose third word contains a value to place in the
-- static chain register (r11). Note that if we load the static chain, our
-- "trampoline" need not have any executable code. */
-
-+/* Expand code to perform a call under the AIX or ELFv2 ABI. */
-+
- void
--rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)
-+rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
- {
-+ rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
-+ rtx toc_load = NULL_RTX;
-+ rtx toc_restore = NULL_RTX;
- rtx func_addr;
-- rtx toc_reg;
-- rtx sc_reg;
-- rtx stack_ptr;
-- rtx stack_toc_offset;
-- rtx stack_toc_mem;
-- rtx func_toc_offset;
-- rtx func_toc_mem;
-- rtx func_sc_offset;
-- rtx func_sc_mem;
-+ rtx abi_reg = NULL_RTX;
-+ rtx call[4];
-+ int n_call;
- rtx insn;
-- rtx (*call_func) (rtx, rtx, rtx, rtx);
-- rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);
-
-- stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
-- toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
-+ /* Handle longcall attributes. */
-+ if (INTVAL (cookie) & CALL_LONG)
-+ func_desc = rs6000_longcall_ref (func_desc);
-
-- /* Load up address of the actual function. */
-- func_desc = force_reg (Pmode, func_desc);
-- func_addr = gen_reg_rtx (Pmode);
-- emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
--
-- if (TARGET_32BIT)
-+ /* Handle indirect calls. */
-+ if (GET_CODE (func_desc) != SYMBOL_REF
-+ || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
- {
-+ /* Save the TOC into its reserved slot before the call,
-+ and prepare to restore it after the call. */
-+ rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
-+ rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
-+ rtx stack_toc_mem = gen_frame_mem (Pmode,
-+ gen_rtx_PLUS (Pmode, stack_ptr,
-+ stack_toc_offset));
-+ toc_restore = gen_rtx_SET (VOIDmode, toc_reg, stack_toc_mem);
-
-- stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);
-- func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);
-- func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);
-- if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
-- {
-- call_func = gen_call_indirect_aix32bit;
-- call_value_func = gen_call_value_indirect_aix32bit;
-- }
-+ /* Can we optimize saving the TOC in the prologue or
-+ do we need to do it at every call? */
-+ if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
-+ cfun->machine->save_toc_in_prologue = true;
- else
- {
-- call_func = gen_call_indirect_aix32bit_nor11;
-- call_value_func = gen_call_value_indirect_aix32bit_nor11;
-+ MEM_VOLATILE_P (stack_toc_mem) = 1;
-+ emit_move_insn (stack_toc_mem, toc_reg);
- }
-- }
-- else
-- {
-- stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);
-- func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);
-- func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);
-- if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
-+
-+ if (DEFAULT_ABI == ABI_ELFv2)
- {
-- call_func = gen_call_indirect_aix64bit;
-- call_value_func = gen_call_value_indirect_aix64bit;
-+ /* A function pointer in the ELFv2 ABI is just a plain address, but
-+ the ABI requires it to be loaded into r12 before the call. */
-+ func_addr = gen_rtx_REG (Pmode, 12);
-+ emit_move_insn (func_addr, func_desc);
-+ abi_reg = func_addr;
- }
- else
- {
-- call_func = gen_call_indirect_aix64bit_nor11;
-- call_value_func = gen_call_value_indirect_aix64bit_nor11;
-- }
-- }
-+ /* A function pointer under AIX is a pointer to a data area whose
-+ first word contains the actual address of the function, whose
-+ second word contains a pointer to its TOC, and whose third word
-+ contains a value to place in the static chain register (r11).
-+ Note that if we load the static chain, our "trampoline" need
-+ not have any executable code. */
-
-- /* Reserved spot to store the TOC. */
-- stack_toc_mem = gen_frame_mem (Pmode,
-- gen_rtx_PLUS (Pmode,
-- stack_ptr,
-- stack_toc_offset));
-+ /* Load up address of the actual function. */
-+ func_desc = force_reg (Pmode, func_desc);
-+ func_addr = gen_reg_rtx (Pmode);
-+ emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
-
-- gcc_assert (cfun);
-- gcc_assert (cfun->machine);
-+ /* Prepare to load the TOC of the called function. Note that the
-+ TOC load must happen immediately before the actual call so
-+ that unwinding the TOC registers works correctly. See the
-+ comment in frob_update_context. */
-+ rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
-+ rtx func_toc_mem = gen_rtx_MEM (Pmode,
-+ gen_rtx_PLUS (Pmode, func_desc,
-+ func_toc_offset));
-+ toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
-
-- /* Can we optimize saving the TOC in the prologue or do we need to do it at
-- every call? */
-- if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
-- cfun->machine->save_toc_in_prologue = true;
--
-+ /* If we have a static chain, load it up. */
-+ if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
-+ {
-+ rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
-+ rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
-+ rtx func_sc_mem = gen_rtx_MEM (Pmode,
-+ gen_rtx_PLUS (Pmode, func_desc,
-+ func_sc_offset));
-+ emit_move_insn (sc_reg, func_sc_mem);
-+ abi_reg = sc_reg;
-+ }
-+ }
-+ }
- else
- {
-- MEM_VOLATILE_P (stack_toc_mem) = 1;
-- emit_move_insn (stack_toc_mem, toc_reg);
-+ /* Direct calls use the TOC: for local calls, the callee will
-+ assume the TOC register is set; for non-local calls, the
-+ PLT stub needs the TOC register. */
-+ abi_reg = toc_reg;
-+ func_addr = func_desc;
- }
-
-- /* Calculate the address to load the TOC of the called function. We don't
-- actually load this until the split after reload. */
-- func_toc_mem = gen_rtx_MEM (Pmode,
-- gen_rtx_PLUS (Pmode,
-- func_desc,
-- func_toc_offset));
-+ /* Create the call. */
-+ call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
-+ if (value != NULL_RTX)
-+ call[0] = gen_rtx_SET (VOIDmode, value, call[0]);
-+ n_call = 1;
-
-- /* If we have a static chain, load it up. */
-- if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
-- {
-- func_sc_mem = gen_rtx_MEM (Pmode,
-- gen_rtx_PLUS (Pmode,
-- func_desc,
-- func_sc_offset));
-+ if (toc_load)
-+ call[n_call++] = toc_load;
-+ if (toc_restore)
-+ call[n_call++] = toc_restore;
-
-- sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
-- emit_move_insn (sc_reg, func_sc_mem);
-- }
-+ call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
-
-+ insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
-+ insn = emit_call_insn (insn);
-+
-+ /* Mention all registers defined by the ABI to hold information
-+ as uses in CALL_INSN_FUNCTION_USAGE. */
-+ if (abi_reg)
-+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
-+}
-+
-+/* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
-+
-+void
-+rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
-+{
-+ rtx call[2];
-+ rtx insn;
-+
-+ gcc_assert (INTVAL (cookie) == 0);
-+
- /* Create the call. */
-- if (value)
-- insn = call_value_func (value, func_addr, flag, func_toc_mem,
-- stack_toc_mem);
-- else
-- insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);
-+ call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
-+ if (value != NULL_RTX)
-+ call[0] = gen_rtx_SET (VOIDmode, value, call[0]);
-
-- emit_call_insn (insn);
-+ call[1] = simple_return_rtx;
-+
-+ insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
-+ insn = emit_call_insn (insn);
-+
-+ /* Note use of the TOC register. */
-+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
-+ /* We need to also mark a use of the link register since the function we
-+ sibling-call to will use it to return to our caller. */
-+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, LR_REGNO));
- }
-
- /* Return whether we need to always update the saved TOC pointer when we update
-@@ -28679,6 +32387,661 @@
- add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
- }
-
-+
-+/* Helper function for rs6000_split_logical to emit a logical instruction after
-+ spliting the operation to single GPR registers.
-+
-+ DEST is the destination register.
-+ OP1 and OP2 are the input source registers.
-+ CODE is the base operation (AND, IOR, XOR, NOT).
-+ MODE is the machine mode.
-+ If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
-+ If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
-+ If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
-+ CLOBBER_REG is either NULL or a scratch register of type CC to allow
-+ formation of the AND instructions. */
-+
-+static void
-+rs6000_split_logical_inner (rtx dest,
-+ rtx op1,
-+ rtx op2,
-+ enum rtx_code code,
-+ enum machine_mode mode,
-+ bool complement_final_p,
-+ bool complement_op1_p,
-+ bool complement_op2_p,
-+ rtx clobber_reg)
-+{
-+ rtx bool_rtx;
-+ rtx set_rtx;
-+
-+ /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
-+ if (op2 && GET_CODE (op2) == CONST_INT
-+ && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
-+ && !complement_final_p && !complement_op1_p && !complement_op2_p)
-+ {
-+ HOST_WIDE_INT mask = GET_MODE_MASK (mode);
-+ HOST_WIDE_INT value = INTVAL (op2) & mask;
-+
-+ /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
-+ if (code == AND)
-+ {
-+ if (value == 0)
-+ {
-+ emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
-+ return;
-+ }
-+
-+ else if (value == mask)
-+ {
-+ if (!rtx_equal_p (dest, op1))
-+ emit_insn (gen_rtx_SET (VOIDmode, dest, op1));
-+ return;
-+ }
-+ }
-+
-+ /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
-+ into separate ORI/ORIS or XORI/XORIS instrucitons. */
-+ else if (code == IOR || code == XOR)
-+ {
-+ if (value == 0)
-+ {
-+ if (!rtx_equal_p (dest, op1))
-+ emit_insn (gen_rtx_SET (VOIDmode, dest, op1));
-+ return;
-+ }
-+ }
-+ }
-+
-+ if (complement_op1_p)
-+ op1 = gen_rtx_NOT (mode, op1);
-+
-+ if (complement_op2_p)
-+ op2 = gen_rtx_NOT (mode, op2);
-+
-+ bool_rtx = ((code == NOT)
-+ ? gen_rtx_NOT (mode, op1)
-+ : gen_rtx_fmt_ee (code, mode, op1, op2));
-+
-+ if (complement_final_p)
-+ bool_rtx = gen_rtx_NOT (mode, bool_rtx);
-+
-+ set_rtx = gen_rtx_SET (VOIDmode, dest, bool_rtx);
-+
-+ /* Is this AND with an explicit clobber? */
-+ if (clobber_reg)
-+ {
-+ rtx clobber = gen_rtx_CLOBBER (VOIDmode, clobber_reg);
-+ set_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set_rtx, clobber));
-+ }
-+
-+ emit_insn (set_rtx);
-+ return;
-+}
-+
-+/* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
-+ operations are split immediately during RTL generation to allow for more
-+ optimizations of the AND/IOR/XOR.
-+
-+ OPERANDS is an array containing the destination and two input operands.
-+ CODE is the base operation (AND, IOR, XOR, NOT).
-+ MODE is the machine mode.
-+ If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
-+ If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
-+ If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
-+ CLOBBER_REG is either NULL or a scratch register of type CC to allow
-+ formation of the AND instructions. */
-+
-+static void
-+rs6000_split_logical_di (rtx operands[3],
-+ enum rtx_code code,
-+ bool complement_final_p,
-+ bool complement_op1_p,
-+ bool complement_op2_p,
-+ rtx clobber_reg)
-+{
-+ const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
-+ const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
-+ const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
-+ enum hi_lo { hi = 0, lo = 1 };
-+ rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
-+ size_t i;
-+
-+ op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
-+ op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
-+ op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
-+ op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
-+
-+ if (code == NOT)
-+ op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
-+ else
-+ {
-+ if (GET_CODE (operands[2]) != CONST_INT)
-+ {
-+ op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
-+ op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
-+ }
-+ else
-+ {
-+ HOST_WIDE_INT value = INTVAL (operands[2]);
-+ HOST_WIDE_INT value_hi_lo[2];
-+
-+ gcc_assert (!complement_final_p);
-+ gcc_assert (!complement_op1_p);
-+ gcc_assert (!complement_op2_p);
-+
-+ value_hi_lo[hi] = value >> 32;
-+ value_hi_lo[lo] = value & lower_32bits;
-+
-+ for (i = 0; i < 2; i++)
-+ {
-+ HOST_WIDE_INT sub_value = value_hi_lo[i];
-+
-+ if (sub_value & sign_bit)
-+ sub_value |= upper_32bits;
-+
-+ op2_hi_lo[i] = GEN_INT (sub_value);
-+
-+ /* If this is an AND instruction, check to see if we need to load
-+ the value in a register. */
-+ if (code == AND && sub_value != -1 && sub_value != 0
-+ && !and_operand (op2_hi_lo[i], SImode))
-+ op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
-+ }
-+ }
-+ }
-+
-+ for (i = 0; i < 2; i++)
-+ {
-+ /* Split large IOR/XOR operations. */
-+ if ((code == IOR || code == XOR)
-+ && GET_CODE (op2_hi_lo[i]) == CONST_INT
-+ && !complement_final_p
-+ && !complement_op1_p
-+ && !complement_op2_p
-+ && clobber_reg == NULL_RTX
-+ && !logical_const_operand (op2_hi_lo[i], SImode))
-+ {
-+ HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
-+ HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
-+ HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
-+ rtx tmp = gen_reg_rtx (SImode);
-+
-+ /* Make sure the constant is sign extended. */
-+ if ((hi_16bits & sign_bit) != 0)
-+ hi_16bits |= upper_32bits;
-+
-+ rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
-+ code, SImode, false, false, false,
-+ NULL_RTX);
-+
-+ rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
-+ code, SImode, false, false, false,
-+ NULL_RTX);
-+ }
-+ else
-+ rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
-+ code, SImode, complement_final_p,
-+ complement_op1_p, complement_op2_p,
-+ clobber_reg);
-+ }
-+
-+ return;
-+}
-+
-+/* Split the insns that make up boolean operations operating on multiple GPR
-+ registers. The boolean MD patterns ensure that the inputs either are
-+ exactly the same as the output registers, or there is no overlap.
-+
-+ OPERANDS is an array containing the destination and two input operands.
-+ CODE is the base operation (AND, IOR, XOR, NOT).
-+ MODE is the machine mode.
-+ If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
-+ If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
-+ If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
-+ CLOBBER_REG is either NULL or a scratch register of type CC to allow
-+ formation of the AND instructions. */
-+
-+void
-+rs6000_split_logical (rtx operands[3],
-+ enum rtx_code code,
-+ bool complement_final_p,
-+ bool complement_op1_p,
-+ bool complement_op2_p,
-+ rtx clobber_reg)
-+{
-+ enum machine_mode mode = GET_MODE (operands[0]);
-+ enum machine_mode sub_mode;
-+ rtx op0, op1, op2;
-+ int sub_size, regno0, regno1, nregs, i;
-+
-+ /* If this is DImode, use the specialized version that can run before
-+ register allocation. */
-+ if (mode == DImode && !TARGET_POWERPC64)
-+ {
-+ rs6000_split_logical_di (operands, code, complement_final_p,
-+ complement_op1_p, complement_op2_p,
-+ clobber_reg);
-+ return;
-+ }
-+
-+ op0 = operands[0];
-+ op1 = operands[1];
-+ op2 = (code == NOT) ? NULL_RTX : operands[2];
-+ sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
-+ sub_size = GET_MODE_SIZE (sub_mode);
-+ regno0 = REGNO (op0);
-+ regno1 = REGNO (op1);
-+
-+ gcc_assert (reload_completed);
-+ gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
-+ gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
-+
-+ nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
-+ gcc_assert (nregs > 1);
-+
-+ if (op2 && REG_P (op2))
-+ gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
-+
-+ for (i = 0; i < nregs; i++)
-+ {
-+ int offset = i * sub_size;
-+ rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
-+ rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
-+ rtx sub_op2 = ((code == NOT)
-+ ? NULL_RTX
-+ : simplify_subreg (sub_mode, op2, mode, offset));
-+
-+ rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
-+ complement_final_p, complement_op1_p,
-+ complement_op2_p, clobber_reg);
-+ }
-+
-+ return;
-+}
-+
-+
-+/* Return true if the peephole2 can combine a load involving a combination of
-+ an addis instruction and a load with an offset that can be fused together on
-+ a power8.
-+
-+ The operands are:
-+ operands[0] register set with addis
-+ operands[1] value set via addis
-+ operands[2] target register being loaded
-+ operands[3] D-form memory reference using operands[0].
-+
-+ In addition, we are passed a boolean that is true if this is a peephole2,
-+ and we can use see if the addis_reg is dead after the insn and can be
-+ replaced by the target register. */
-+
-+bool
-+fusion_gpr_load_p (rtx *operands, bool peep2_p)
-+{
-+ rtx addis_reg = operands[0];
-+ rtx addis_value = operands[1];
-+ rtx target = operands[2];
-+ rtx mem = operands[3];
-+ rtx addr;
-+ rtx base_reg;
-+
-+ /* Validate arguments. */
-+ if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
-+ return false;
-+
-+ if (!base_reg_operand (target, GET_MODE (target)))
-+ return false;
-+
-+ if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
-+ return false;
-+
-+ if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
-+ return false;
-+
-+ /* Allow sign/zero extension. */
-+ if (GET_CODE (mem) == ZERO_EXTEND
-+ || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
-+ mem = XEXP (mem, 0);
-+
-+ if (!MEM_P (mem))
-+ return false;
-+
-+ addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
-+ if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
-+ return false;
-+
-+ /* Validate that the register used to load the high value is either the
-+ register being loaded, or we can safely replace its use in a peephole2.
-+
-+ If this is a peephole2, we assume that there are 2 instructions in the
-+ peephole (addis and load), so we want to check if the target register was
-+ not used in the memory address and the register to hold the addis result
-+ is dead after the peephole. */
-+ if (REGNO (addis_reg) != REGNO (target))
-+ {
-+ if (!peep2_p)
-+ return false;
-+
-+ if (reg_mentioned_p (target, mem))
-+ return false;
-+
-+ if (!peep2_reg_dead_p (2, addis_reg))
-+ return false;
-+
-+ /* If the target register being loaded is the stack pointer, we must
-+ avoid loading any other value into it, even temporarily. */
-+ if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
-+ return false;
-+ }
-+
-+ base_reg = XEXP (addr, 0);
-+ return REGNO (addis_reg) == REGNO (base_reg);
-+}
-+
-+/* During the peephole2 pass, adjust and expand the insns for a load fusion
-+ sequence. We adjust the addis register to use the target register. If the
-+ load sign extends, we adjust the code to do the zero extending load, and an
-+ explicit sign extension later since the fusion only covers zero extending
-+ loads.
-+
-+ The operands are:
-+ operands[0] register set with addis (to be replaced with target)
-+ operands[1] value set via addis
-+ operands[2] target register being loaded
-+ operands[3] D-form memory reference using operands[0]. */
-+
-+void
-+expand_fusion_gpr_load (rtx *operands)
-+{
-+ rtx addis_value = operands[1];
-+ rtx target = operands[2];
-+ rtx orig_mem = operands[3];
-+ rtx new_addr, new_mem, orig_addr, offset;
-+ enum rtx_code plus_or_lo_sum;
-+ enum machine_mode target_mode = GET_MODE (target);
-+ enum machine_mode extend_mode = target_mode;
-+ enum machine_mode ptr_mode = Pmode;
-+ enum rtx_code extend = UNKNOWN;
-+ rtx addis_reg = ((ptr_mode == target_mode)
-+ ? target
-+ : simplify_subreg (ptr_mode, target, target_mode, 0));
-+
-+ if (GET_CODE (orig_mem) == ZERO_EXTEND
-+ || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
-+ {
-+ extend = GET_CODE (orig_mem);
-+ orig_mem = XEXP (orig_mem, 0);
-+ target_mode = GET_MODE (orig_mem);
-+ }
-+
-+ gcc_assert (MEM_P (orig_mem));
-+
-+ orig_addr = XEXP (orig_mem, 0);
-+ plus_or_lo_sum = GET_CODE (orig_addr);
-+ gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
-+
-+ offset = XEXP (orig_addr, 1);
-+ new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_reg, offset);
-+ new_mem = change_address (orig_mem, target_mode, new_addr);
-+
-+ if (extend != UNKNOWN)
-+ new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
-+
-+ emit_insn (gen_rtx_SET (VOIDmode, addis_reg, addis_value));
-+ emit_insn (gen_rtx_SET (VOIDmode, target, new_mem));
-+
-+ if (extend == SIGN_EXTEND)
-+ {
-+ int sub_off = ((BYTES_BIG_ENDIAN)
-+ ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
-+ : 0);
-+ rtx sign_reg
-+ = simplify_subreg (target_mode, target, extend_mode, sub_off);
-+
-+ emit_insn (gen_rtx_SET (VOIDmode, target,
-+ gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
-+ }
-+
-+ return;
-+}
-+
-+/* Return a string to fuse an addis instruction with a gpr load to the same
-+ register that we loaded up the addis instruction. The code is complicated,
-+ so we call output_asm_insn directly, and just return "".
-+
-+ The operands are:
-+ operands[0] register set with addis (must be same reg as target).
-+ operands[1] value set via addis
-+ operands[2] target register being loaded
-+ operands[3] D-form memory reference using operands[0]. */
-+
-+const char *
-+emit_fusion_gpr_load (rtx *operands)
-+{
-+ rtx addis_reg = operands[0];
-+ rtx addis_value = operands[1];
-+ rtx target = operands[2];
-+ rtx mem = operands[3];
-+ rtx fuse_ops[10];
-+ rtx addr;
-+ rtx load_offset;
-+ const char *addis_str = NULL;
-+ const char *load_str = NULL;
-+ const char *extend_insn = NULL;
-+ const char *mode_name = NULL;
-+ char insn_template[80];
-+ enum machine_mode mode;
-+ const char *comment_str = ASM_COMMENT_START;
-+ bool sign_p = false;
-+
-+ gcc_assert (REG_P (addis_reg) && REG_P (target));
-+ gcc_assert (REGNO (addis_reg) == REGNO (target));
-+
-+ if (*comment_str == ' ')
-+ comment_str++;
-+
-+ /* Allow sign/zero extension. */
-+ if (GET_CODE (mem) == ZERO_EXTEND)
-+ mem = XEXP (mem, 0);
-+
-+ else if (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN)
-+ {
-+ sign_p = true;
-+ mem = XEXP (mem, 0);
-+ }
-+
-+ gcc_assert (MEM_P (mem));
-+ addr = XEXP (mem, 0);
-+ if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
-+ gcc_unreachable ();
-+
-+ load_offset = XEXP (addr, 1);
-+
-+ /* Now emit the load instruction to the same register. */
-+ mode = GET_MODE (mem);
-+ switch (mode)
-+ {
-+ case QImode:
-+ mode_name = "char";
-+ load_str = "lbz";
-+ extend_insn = "extsb %0,%0";
-+ break;
-+
-+ case HImode:
-+ mode_name = "short";
-+ load_str = "lhz";
-+ extend_insn = "extsh %0,%0";
-+ break;
-+
-+ case SImode:
-+ mode_name = "int";
-+ load_str = "lwz";
-+ extend_insn = "extsw %0,%0";
-+ break;
-+
-+ case DImode:
-+ if (TARGET_POWERPC64)
-+ {
-+ mode_name = "long";
-+ load_str = "ld";
-+ }
-+ else
-+ gcc_unreachable ();
-+ break;
-+
-+ default:
-+ gcc_unreachable ();
-+ }
-+
-+ /* Emit the addis instruction. */
-+ fuse_ops[0] = target;
-+ if (satisfies_constraint_L (addis_value))
-+ {
-+ fuse_ops[1] = addis_value;
-+ addis_str = "lis %0,%v1";
-+ }
-+
-+ else if (GET_CODE (addis_value) == PLUS)
-+ {
-+ rtx op0 = XEXP (addis_value, 0);
-+ rtx op1 = XEXP (addis_value, 1);
-+
-+ if (REG_P (op0) && CONST_INT_P (op1)
-+ && satisfies_constraint_L (op1))
-+ {
-+ fuse_ops[1] = op0;
-+ fuse_ops[2] = op1;
-+ addis_str = "addis %0,%1,%v2";
-+ }
-+ }
-+
-+ else if (GET_CODE (addis_value) == HIGH)
-+ {
-+ rtx value = XEXP (addis_value, 0);
-+ if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
-+ {
-+ fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
-+ fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
-+ if (TARGET_ELF)
-+ addis_str = "addis %0,%2,%1@toc@ha";
-+
-+ else if (TARGET_XCOFF)
-+ addis_str = "addis %0,%1@u(%2)";
-+
-+ else
-+ gcc_unreachable ();
-+ }
-+
-+ else if (GET_CODE (value) == PLUS)
-+ {
-+ rtx op0 = XEXP (value, 0);
-+ rtx op1 = XEXP (value, 1);
-+
-+ if (GET_CODE (op0) == UNSPEC
-+ && XINT (op0, 1) == UNSPEC_TOCREL
-+ && CONST_INT_P (op1))
-+ {
-+ fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
-+ fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
-+ fuse_ops[3] = op1;
-+ if (TARGET_ELF)
-+ addis_str = "addis %0,%2,%1+%3@toc@ha";
-+
-+ else if (TARGET_XCOFF)
-+ addis_str = "addis %0,%1+%3@u(%2)";
-+
-+ else
-+ gcc_unreachable ();
-+ }
-+ }
-+
-+ else if (satisfies_constraint_L (value))
-+ {
-+ fuse_ops[1] = value;
-+ addis_str = "lis %0,%v1";
-+ }
-+
-+ else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
-+ {
-+ fuse_ops[1] = value;
-+ addis_str = "lis %0,%1@ha";
-+ }
-+ }
-+
-+ if (!addis_str)
-+ fatal_insn ("Could not generate addis value for fusion", addis_value);
-+
-+ sprintf (insn_template, "%s\t\t%s gpr load fusion, type %s", addis_str,
-+ comment_str, mode_name);
-+ output_asm_insn (insn_template, fuse_ops);
-+
-+ /* Emit the D-form load instruction. */
-+ if (CONST_INT_P (load_offset) && satisfies_constraint_I (load_offset))
-+ {
-+ sprintf (insn_template, "%s %%0,%%1(%%0)", load_str);
-+ fuse_ops[1] = load_offset;
-+ output_asm_insn (insn_template, fuse_ops);
-+ }
-+
-+ else if (GET_CODE (load_offset) == UNSPEC
-+ && XINT (load_offset, 1) == UNSPEC_TOCREL)
-+ {
-+ if (TARGET_ELF)
-+ sprintf (insn_template, "%s %%0,%%1@toc@l(%%0)", load_str);
-+
-+ else if (TARGET_XCOFF)
-+ sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str);
-+
-+ else
-+ gcc_unreachable ();
-+
-+ fuse_ops[1] = XVECEXP (load_offset, 0, 0);
-+ output_asm_insn (insn_template, fuse_ops);
-+ }
-+
-+ else if (GET_CODE (load_offset) == PLUS
-+ && GET_CODE (XEXP (load_offset, 0)) == UNSPEC
-+ && XINT (XEXP (load_offset, 0), 1) == UNSPEC_TOCREL
-+ && CONST_INT_P (XEXP (load_offset, 1)))
-+ {
-+ rtx tocrel_unspec = XEXP (load_offset, 0);
-+ if (TARGET_ELF)
-+ sprintf (insn_template, "%s %%0,%%1+%%2@toc@l(%%0)", load_str);
-+
-+ else if (TARGET_XCOFF)
-+ sprintf (insn_template, "%s %%0,%%1+%%2@l(%%0)", load_str);
-+
-+ else
-+ gcc_unreachable ();
-+
-+ fuse_ops[1] = XVECEXP (tocrel_unspec, 0, 0);
-+ fuse_ops[2] = XEXP (load_offset, 1);
-+ output_asm_insn (insn_template, fuse_ops);
-+ }
-+
-+ else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (load_offset))
-+ {
-+ sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str);
-+
-+ fuse_ops[1] = load_offset;
-+ output_asm_insn (insn_template, fuse_ops);
-+ }
-+
-+ else
-+ fatal_insn ("Unable to generate load offset for fusion", load_offset);
-+
-+ /* Handle sign extension. The peephole2 pass generates this as a separate
-+ insn, but we handle it just in case it got reattached. */
-+ if (sign_p)
-+ {
-+ gcc_assert (extend_insn != NULL);
-+ output_asm_insn (extend_insn, fuse_ops);
-+ }
-+
-+ return "";
-+}
-+
-+
- struct gcc_target targetm = TARGET_INITIALIZER;
-
- #include "gt-rs6000.h"
-Index: gcc/config/rs6000/vsx.md
-===================================================================
---- a/src/gcc/config/rs6000/vsx.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/vsx.md (.../branches/gcc-4_8-branch)
-@@ -34,12 +34,21 @@
- (define_mode_iterator VSX_F [V4SF V2DF])
-
- ;; Iterator for logical types supported by VSX
--(define_mode_iterator VSX_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])
-+(define_mode_iterator VSX_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI])
-
- ;; Iterator for memory move. Handle TImode specially to allow
- ;; it to use gprs as well as vsx registers.
--(define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF])
-+(define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])
-
-+(define_mode_iterator VSX_M2 [V16QI
-+ V8HI
-+ V4SI
-+ V2DI
-+ V4SF
-+ V2DF
-+ V1TI
-+ (TI "TARGET_VSX_TIMODE")])
-+
- ;; Map into the appropriate load/store name based on the type
- (define_mode_attr VSm [(V16QI "vw4")
- (V8HI "vw4")
-@@ -48,7 +57,8 @@
- (V2DF "vd2")
- (V2DI "vd2")
- (DF "d")
-- (TI "vw4")])
-+ (V1TI "vd2")
-+ (TI "vd2")])
-
- ;; Map into the appropriate suffix based on the type
- (define_mode_attr VSs [(V16QI "sp")
-@@ -59,7 +69,8 @@
- (V2DI "dp")
- (DF "dp")
- (SF "sp")
-- (TI "sp")])
-+ (V1TI "dp")
-+ (TI "dp")])
-
- ;; Map the register class used
- (define_mode_attr VSr [(V16QI "v")
-@@ -70,7 +81,8 @@
- (V2DF "wd")
- (DF "ws")
- (SF "d")
-- (TI "wd")])
-+ (V1TI "v")
-+ (TI "wt")])
-
- ;; Map the register class used for float<->int conversions
- (define_mode_attr VSr2 [(V2DF "wd")
-@@ -115,7 +127,7 @@
- (V4SF "v")
- (V2DI "v")
- (V2DF "v")
-- (TI "v")
-+ (V1TI "v")
- (DF "s")])
-
- ;; Appropriate type for add ops (and other simple FP ops)
-@@ -173,7 +185,8 @@
- (V2DF "vecdouble")])
-
- ;; Map the scalar mode for a vector type
--(define_mode_attr VS_scalar [(V2DF "DF")
-+(define_mode_attr VS_scalar [(V1TI "TI")
-+ (V2DF "DF")
- (V2DI "DI")
- (V4SF "SF")
- (V4SI "SI")
-@@ -184,7 +197,8 @@
- (define_mode_attr VS_double [(V4SI "V8SI")
- (V4SF "V8SF")
- (V2DI "V4DI")
-- (V2DF "V4DF")])
-+ (V2DF "V4DF")
-+ (V1TI "V2TI")])
-
- ;; Constants for creating unspecs
- (define_c_enum "unspec"
-@@ -192,6 +206,8 @@
- UNSPEC_VSX_CVDPSXWS
- UNSPEC_VSX_CVDPUXWS
- UNSPEC_VSX_CVSPDP
-+ UNSPEC_VSX_CVSPDPN
-+ UNSPEC_VSX_CVDPSPN
- UNSPEC_VSX_CVSXWDP
- UNSPEC_VSX_CVUXWDP
- UNSPEC_VSX_CVSXDSP
-@@ -204,80 +220,397 @@
- UNSPEC_VSX_ROUND_I
- UNSPEC_VSX_ROUND_IC
- UNSPEC_VSX_SLDWI
-+ UNSPEC_VSX_XXSPLTW
- ])
-
- ;; VSX moves
--(define_insn "*vsx_mov<mode>"
-- [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,*Y,*r,*r,<VSr>,?wa,*r,v,wZ,v")
-- (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,Y,r,j,j,j,W,v,wZ"))]
-- "VECTOR_MEM_VSX_P (<MODE>mode)
-- && (register_operand (operands[0], <MODE>mode)
-- || register_operand (operands[1], <MODE>mode))"
-+
-+;; The patterns for LE permuted loads and stores come before the general
-+;; VSX moves so they match first.
-+(define_insn_and_split "*vsx_le_perm_load_<mode>"
-+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
-+ (match_operand:VSX_D 1 "memory_operand" "Z"))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ "#"
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ [(set (match_dup 2)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 1) (const_int 0)])))
-+ (set (match_dup 0)
-+ (vec_select:<MODE>
-+ (match_dup 2)
-+ (parallel [(const_int 1) (const_int 0)])))]
-+ "
- {
-- switch (which_alternative)
-- {
-- case 0:
-- case 3:
-- gcc_assert (MEM_P (operands[0])
-- && GET_CODE (XEXP (operands[0], 0)) != PRE_INC
-- && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC
-- && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY);
-- return "stx<VSm>x %x1,%y0";
-+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
-+ : operands[0];
-+}
-+ "
-+ [(set_attr "type" "vecload")
-+ (set_attr "length" "8")])
-
-- case 1:
-- case 4:
-- gcc_assert (MEM_P (operands[1])
-- && GET_CODE (XEXP (operands[1], 0)) != PRE_INC
-- && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC
-- && GET_CODE (XEXP (operands[1], 0)) != PRE_MODIFY);
-- return "lx<VSm>x %x0,%y1";
-+(define_insn_and_split "*vsx_le_perm_load_<mode>"
-+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
-+ (match_operand:VSX_W 1 "memory_operand" "Z"))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ "#"
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ [(set (match_dup 2)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))
-+ (set (match_dup 0)
-+ (vec_select:<MODE>
-+ (match_dup 2)
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))]
-+ "
-+{
-+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
-+ : operands[0];
-+}
-+ "
-+ [(set_attr "type" "vecload")
-+ (set_attr "length" "8")])
-
-- case 2:
-- case 5:
-- return "xxlor %x0,%x1,%x1";
-+(define_insn_and_split "*vsx_le_perm_load_v8hi"
-+ [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")
-+ (match_operand:V8HI 1 "memory_operand" "Z"))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ "#"
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ [(set (match_dup 2)
-+ (vec_select:V8HI
-+ (match_dup 1)
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))
-+ (set (match_dup 0)
-+ (vec_select:V8HI
-+ (match_dup 2)
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))]
-+ "
-+{
-+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
-+ : operands[0];
-+}
-+ "
-+ [(set_attr "type" "vecload")
-+ (set_attr "length" "8")])
-
-- case 6:
-- case 7:
-- case 8:
-- case 11:
-- return "#";
-+(define_insn_and_split "*vsx_le_perm_load_v16qi"
-+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
-+ (match_operand:V16QI 1 "memory_operand" "Z"))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ "#"
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ [(set (match_dup 2)
-+ (vec_select:V16QI
-+ (match_dup 1)
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))
-+ (set (match_dup 0)
-+ (vec_select:V16QI
-+ (match_dup 2)
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))]
-+ "
-+{
-+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
-+ : operands[0];
-+}
-+ "
-+ [(set_attr "type" "vecload")
-+ (set_attr "length" "8")])
-
-- case 9:
-- case 10:
-- return "xxlxor %x0,%x0,%x0";
-+(define_insn "*vsx_le_perm_store_<mode>"
-+ [(set (match_operand:VSX_D 0 "memory_operand" "=Z")
-+ (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ "#"
-+ [(set_attr "type" "vecstore")
-+ (set_attr "length" "12")])
-
-- case 12:
-- return output_vec_const_move (operands);
-+(define_split
-+ [(set (match_operand:VSX_D 0 "memory_operand" "")
-+ (match_operand:VSX_D 1 "vsx_register_operand" ""))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"
-+ [(set (match_dup 2)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 1) (const_int 0)])))
-+ (set (match_dup 0)
-+ (vec_select:<MODE>
-+ (match_dup 2)
-+ (parallel [(const_int 1) (const_int 0)])))]
-+{
-+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])
-+ : operands[1];
-+})
-
-- case 13:
-- gcc_assert (MEM_P (operands[0])
-- && GET_CODE (XEXP (operands[0], 0)) != PRE_INC
-- && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC
-- && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY);
-- return "stvx %1,%y0";
-+;; The post-reload split requires that we re-permute the source
-+;; register in case it is still live.
-+(define_split
-+ [(set (match_operand:VSX_D 0 "memory_operand" "")
-+ (match_operand:VSX_D 1 "vsx_register_operand" ""))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"
-+ [(set (match_dup 1)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 1) (const_int 0)])))
-+ (set (match_dup 0)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 1) (const_int 0)])))
-+ (set (match_dup 1)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 1) (const_int 0)])))]
-+ "")
-
-- case 14:
-- gcc_assert (MEM_P (operands[0])
-- && GET_CODE (XEXP (operands[0], 0)) != PRE_INC
-- && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC
-- && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY);
-- return "lvx %0,%y1";
-+(define_insn "*vsx_le_perm_store_<mode>"
-+ [(set (match_operand:VSX_W 0 "memory_operand" "=Z")
-+ (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ "#"
-+ [(set_attr "type" "vecstore")
-+ (set_attr "length" "12")])
-
-- default:
-- gcc_unreachable ();
-- }
-+(define_split
-+ [(set (match_operand:VSX_W 0 "memory_operand" "")
-+ (match_operand:VSX_W 1 "vsx_register_operand" ""))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"
-+ [(set (match_dup 2)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))
-+ (set (match_dup 0)
-+ (vec_select:<MODE>
-+ (match_dup 2)
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))]
-+{
-+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])
-+ : operands[1];
-+})
-+
-+;; The post-reload split requires that we re-permute the source
-+;; register in case it is still live.
-+(define_split
-+ [(set (match_operand:VSX_W 0 "memory_operand" "")
-+ (match_operand:VSX_W 1 "vsx_register_operand" ""))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"
-+ [(set (match_dup 1)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))
-+ (set (match_dup 0)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))
-+ (set (match_dup 1)
-+ (vec_select:<MODE>
-+ (match_dup 1)
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))]
-+ "")
-+
-+(define_insn "*vsx_le_perm_store_v8hi"
-+ [(set (match_operand:V8HI 0 "memory_operand" "=Z")
-+ (match_operand:V8HI 1 "vsx_register_operand" "+wa"))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ "#"
-+ [(set_attr "type" "vecstore")
-+ (set_attr "length" "12")])
-+
-+(define_split
-+ [(set (match_operand:V8HI 0 "memory_operand" "")
-+ (match_operand:V8HI 1 "vsx_register_operand" ""))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"
-+ [(set (match_dup 2)
-+ (vec_select:V8HI
-+ (match_dup 1)
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))
-+ (set (match_dup 0)
-+ (vec_select:V8HI
-+ (match_dup 2)
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))]
-+{
-+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])
-+ : operands[1];
-+})
-+
-+;; The post-reload split requires that we re-permute the source
-+;; register in case it is still live.
-+(define_split
-+ [(set (match_operand:V8HI 0 "memory_operand" "")
-+ (match_operand:V8HI 1 "vsx_register_operand" ""))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"
-+ [(set (match_dup 1)
-+ (vec_select:V8HI
-+ (match_dup 1)
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))
-+ (set (match_dup 0)
-+ (vec_select:V8HI
-+ (match_dup 1)
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))
-+ (set (match_dup 1)
-+ (vec_select:V8HI
-+ (match_dup 1)
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))]
-+ "")
-+
-+(define_insn "*vsx_le_perm_store_v16qi"
-+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
-+ (match_operand:V16QI 1 "vsx_register_operand" "+wa"))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX"
-+ "#"
-+ [(set_attr "type" "vecstore")
-+ (set_attr "length" "12")])
-+
-+(define_split
-+ [(set (match_operand:V16QI 0 "memory_operand" "")
-+ (match_operand:V16QI 1 "vsx_register_operand" ""))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"
-+ [(set (match_dup 2)
-+ (vec_select:V16QI
-+ (match_dup 1)
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))
-+ (set (match_dup 0)
-+ (vec_select:V16QI
-+ (match_dup 2)
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))]
-+{
-+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1])
-+ : operands[1];
-+})
-+
-+;; The post-reload split requires that we re-permute the source
-+;; register in case it is still live.
-+(define_split
-+ [(set (match_operand:V16QI 0 "memory_operand" "")
-+ (match_operand:V16QI 1 "vsx_register_operand" ""))]
-+ "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"
-+ [(set (match_dup 1)
-+ (vec_select:V16QI
-+ (match_dup 1)
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))
-+ (set (match_dup 0)
-+ (vec_select:V16QI
-+ (match_dup 1)
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))
-+ (set (match_dup 1)
-+ (vec_select:V16QI
-+ (match_dup 1)
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))]
-+ "")
-+
-+
-+(define_insn "*vsx_mov<mode>"
-+ [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,<VSr>,?wa,*r,v,wZ, v")
-+ (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]
-+ "VECTOR_MEM_VSX_P (<MODE>mode)
-+ && (register_operand (operands[0], <MODE>mode)
-+ || register_operand (operands[1], <MODE>mode))"
-+{
-+ return rs6000_output_move_128bit (operands);
- }
-- [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,*,*,*,vecsimple,vecsimple,*,*,vecstore,vecload")])
-+ [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,load,store,store,load, *,vecsimple,vecsimple,*, *,vecstore,vecload")
-+ (set_attr "length" "4,4,4,4,4,4,12,12,12,12,16,4,4,*,16,4,4")])
-
--;; Unlike other VSX moves, allow the GPRs, since a normal use of TImode is for
--;; unions. However for plain data movement, slightly favor the vector loads
--(define_insn "*vsx_movti"
-- [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,?Y,?r,?r,wa,v,v,wZ")
-- (match_operand:TI 1 "input_operand" "wa,Z,wa,r,Y,r,j,W,wZ,v"))]
-- "VECTOR_MEM_VSX_P (TImode)
-+;; Unlike other VSX moves, allow the GPRs even for reloading, since a normal
-+;; use of TImode is for unions. However for plain data movement, slightly
-+;; favor the vector loads
-+(define_insn "*vsx_movti_64bit"
-+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v,v,wZ,wQ,&r,Y,r,r,?r")
-+ (match_operand:TI 1 "input_operand" "wa,Z,wa,O,W,wZ,v,r,wQ,r,Y,r,n"))]
-+ "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode)
- && (register_operand (operands[0], TImode)
- || register_operand (operands[1], TImode))"
- {
-+ return rs6000_output_move_128bit (operands);
-+}
-+ [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store,load,store,load,*,*")
-+ (set_attr "length" "4,4,4,4,16,4,4,8,8,8,8,8,8")])
-+
-+(define_insn "*vsx_movti_32bit"
-+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v, v,wZ,Q,Y,????r,????r,????r,r")
-+ (match_operand:TI 1 "input_operand" "wa, Z,wa, O,W,wZ, v,r,r, Q, Y, r,n"))]
-+ "! TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode)
-+ && (register_operand (operands[0], TImode)
-+ || register_operand (operands[1], TImode))"
-+{
- switch (which_alternative)
- {
- case 0:
-@@ -290,27 +623,45 @@
- return "xxlor %x0,%x1,%x1";
-
- case 3:
-+ return "xxlxor %x0,%x0,%x0";
-+
- case 4:
-+ return output_vec_const_move (operands);
-+
- case 5:
-- return "#";
-+ return "stvx %1,%y0";
-
- case 6:
-- return "xxlxor %x0,%x0,%x0";
-+ return "lvx %0,%y1";
-
- case 7:
-- return output_vec_const_move (operands);
-+ if (TARGET_STRING)
-+ return \"stswi %1,%P0,16\";
-
- case 8:
-- return "stvx %1,%y0";
-+ return \"#\";
-
- case 9:
-- return "lvx %0,%y1";
-+ /* If the address is not used in the output, we can use lsi. Otherwise,
-+ fall through to generating four loads. */
-+ if (TARGET_STRING
-+ && ! reg_overlap_mentioned_p (operands[0], operands[1]))
-+ return \"lswi %0,%P1,16\";
-+ /* ... fall through ... */
-
-+ case 10:
-+ case 11:
-+ case 12:
-+ return \"#\";
- default:
- gcc_unreachable ();
- }
- }
-- [(set_attr "type" "vecstore,vecload,vecsimple,*,*,*,vecsimple,*,vecstore,vecload")])
-+ [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store_ux,store_ux,load_ux,load_ux, *, *")
-+ (set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16")
-+ (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
-+ (const_string "always")
-+ (const_string "conditional")))])
-
- ;; Explicit load/store expanders for the builtin functions
- (define_expand "vsx_load_<mode>"
-@@ -320,46 +671,48 @@
- "")
-
- (define_expand "vsx_store_<mode>"
-- [(set (match_operand:VEC_M 0 "memory_operand" "")
-- (match_operand:VEC_M 1 "vsx_register_operand" ""))]
-+ [(set (match_operand:VSX_M 0 "memory_operand" "")
-+ (match_operand:VSX_M 1 "vsx_register_operand" ""))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- "")
-
-
--;; VSX scalar and vector floating point arithmetic instructions
-+;; VSX vector floating point arithmetic instructions. The VSX scalar
-+;; instructions are now combined with the insn for the traditional floating
-+;; point unit.
- (define_insn "*vsx_add<mode>3"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (plus:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
-- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
-+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>add<VSs> %x0,%x1,%x2"
-+ "xvadd<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "*vsx_sub<mode>3"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (minus:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
-- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
-+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>sub<VSs> %x0,%x1,%x2"
-+ "xvsub<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "*vsx_mul<mode>3"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (mult:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
-- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
-+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>mul<VSs> %x0,%x1,%x2"
-- [(set_attr "type" "<VStype_mul>")
-+ "xvmul<VSs> %x0,%x1,%x2"
-+ [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_mul>")])
-
- (define_insn "*vsx_div<mode>3"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (div:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
-- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
-+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>div<VSs> %x0,%x1,%x2"
-+ "xvdiv<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_div>")
- (set_attr "fp_type" "<VSfptype_div>")])
-
-@@ -402,94 +755,72 @@
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "vsx_fre<mode>2"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
- UNSPEC_FRES))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>re<VSs> %x0,%x1"
-+ "xvre<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "*vsx_neg<mode>2"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (neg:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>neg<VSs> %x0,%x1"
-+ "xvneg<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "*vsx_abs<mode>2"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (abs:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>abs<VSs> %x0,%x1"
-+ "xvabs<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "vsx_nabs<mode>2"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (neg:VSX_B
-- (abs:VSX_B
-- (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa"))))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (neg:VSX_F
-+ (abs:VSX_F
-+ (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa"))))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>nabs<VSs> %x0,%x1"
-+ "xvnabs<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "vsx_smax<mode>3"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (smax:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
-- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
-+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>max<VSs> %x0,%x1,%x2"
-+ "xvmax<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "*vsx_smin<mode>3"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (smin:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
-- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
-+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>min<VSs> %x0,%x1,%x2"
-+ "xvmin<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
--;; Special VSX version of smin/smax for single precision floating point. Since
--;; both numbers are rounded to single precision, we can just use the DP version
--;; of the instruction.
--
--(define_insn "*vsx_smaxsf3"
-- [(set (match_operand:SF 0 "vsx_register_operand" "=f")
-- (smax:SF (match_operand:SF 1 "vsx_register_operand" "f")
-- (match_operand:SF 2 "vsx_register_operand" "f")))]
-- "VECTOR_UNIT_VSX_P (DFmode)"
-- "xsmaxdp %x0,%x1,%x2"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_addsub_d")])
--
--(define_insn "*vsx_sminsf3"
-- [(set (match_operand:SF 0 "vsx_register_operand" "=f")
-- (smin:SF (match_operand:SF 1 "vsx_register_operand" "f")
-- (match_operand:SF 2 "vsx_register_operand" "f")))]
-- "VECTOR_UNIT_VSX_P (DFmode)"
-- "xsmindp %x0,%x1,%x2"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_addsub_d")])
--
- (define_insn "*vsx_sqrt<mode>2"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (sqrt:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>sqrt<VSs> %x0,%x1"
-+ "xvsqrt<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_sqrt>")
- (set_attr "fp_type" "<VSfptype_sqrt>")])
-
- (define_insn "*vsx_rsqrte<mode>2"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
- UNSPEC_RSQRT))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>rsqrte<VSs> %x0,%x1"
-+ "xvrsqrte<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
-@@ -528,27 +859,11 @@
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
--;; Fused vector multiply/add instructions Support the classical DF versions of
--;; fma, which allows the target to be a separate register from the 3 inputs.
--;; Under VSX, the target must be either the addend or the first multiply.
--;; Where we can, also do the same for the Altivec V4SF fmas.
-+;; Fused vector multiply/add instructions. Support the classical Altivec
-+;; versions of fma, which allows the target to be a separate register from the
-+;; 3 inputs. Under VSX, the target must be either the addend or the first
-+;; multiply.
-
--(define_insn "*vsx_fmadf4"
-- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")
-- (fma:DF
-- (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d")
-- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")
-- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d")))]
-- "VECTOR_UNIT_VSX_P (DFmode)"
-- "@
-- xsmaddadp %x0,%x1,%x2
-- xsmaddmdp %x0,%x1,%x3
-- xsmaddadp %x0,%x1,%x2
-- xsmaddmdp %x0,%x1,%x3
-- fmadd %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_d")])
--
- (define_insn "*vsx_fmav4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,v")
- (fma:V4SF
-@@ -578,23 +893,6 @@
- xvmaddmdp %x0,%x1,%x3"
- [(set_attr "type" "vecdouble")])
-
--(define_insn "*vsx_fmsdf4"
-- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")
-- (fma:DF
-- (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d")
-- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")
-- (neg:DF
-- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d"))))]
-- "VECTOR_UNIT_VSX_P (DFmode)"
-- "@
-- xsmsubadp %x0,%x1,%x2
-- xsmsubmdp %x0,%x1,%x3
-- xsmsubadp %x0,%x1,%x2
-- xsmsubmdp %x0,%x1,%x3
-- fmsub %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_d")])
--
- (define_insn "*vsx_fms<mode>4"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")
- (fma:VSX_F
-@@ -604,29 +902,12 @@
- (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
- "@
-- x<VSv>msuba<VSs> %x0,%x1,%x2
-- x<VSv>msubm<VSs> %x0,%x1,%x3
-- x<VSv>msuba<VSs> %x0,%x1,%x2
-- x<VSv>msubm<VSs> %x0,%x1,%x3"
-+ xvmsuba<VSs> %x0,%x1,%x2
-+ xvmsubm<VSs> %x0,%x1,%x3
-+ xvmsuba<VSs> %x0,%x1,%x2
-+ xvmsubm<VSs> %x0,%x1,%x3"
- [(set_attr "type" "<VStype_mul>")])
-
--(define_insn "*vsx_nfmadf4"
-- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")
-- (neg:DF
-- (fma:DF
-- (match_operand:DF 1 "vsx_register_operand" "ws,ws,wa,wa,d")
-- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")
-- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d"))))]
-- "VECTOR_UNIT_VSX_P (DFmode)"
-- "@
-- xsnmaddadp %x0,%x1,%x2
-- xsnmaddmdp %x0,%x1,%x3
-- xsnmaddadp %x0,%x1,%x2
-- xsnmaddmdp %x0,%x1,%x3
-- fnmadd %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_d")])
--
- (define_insn "*vsx_nfma<mode>4"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")
- (neg:VSX_F
-@@ -636,31 +917,13 @@
- (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
- "@
-- x<VSv>nmadda<VSs> %x0,%x1,%x2
-- x<VSv>nmaddm<VSs> %x0,%x1,%x3
-- x<VSv>nmadda<VSs> %x0,%x1,%x2
-- x<VSv>nmaddm<VSs> %x0,%x1,%x3"
-+ xvnmadda<VSs> %x0,%x1,%x2
-+ xvnmaddm<VSs> %x0,%x1,%x3
-+ xvnmadda<VSs> %x0,%x1,%x2
-+ xvnmaddm<VSs> %x0,%x1,%x3"
- [(set_attr "type" "<VStype_mul>")
- (set_attr "fp_type" "<VSfptype_mul>")])
-
--(define_insn "*vsx_nfmsdf4"
-- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d")
-- (neg:DF
-- (fma:DF
-- (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d")
-- (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d")
-- (neg:DF
-- (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d")))))]
-- "VECTOR_UNIT_VSX_P (DFmode)"
-- "@
-- xsnmsubadp %x0,%x1,%x2
-- xsnmsubmdp %x0,%x1,%x3
-- xsnmsubadp %x0,%x1,%x2
-- xsnmsubmdp %x0,%x1,%x3
-- fnmsub %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_d")])
--
- (define_insn "*vsx_nfmsv4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v")
- (neg:V4SF
-@@ -722,16 +985,6 @@
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
--;; Floating point scalar compare
--(define_insn "*vsx_cmpdf_internal1"
-- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,?y")
-- (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "ws,wa")
-- (match_operand:DF 2 "gpc_reg_operand" "ws,wa")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && VECTOR_UNIT_VSX_P (DFmode)"
-- "xscmpudp %0,%x1,%x2"
-- [(set_attr "type" "fpcompare")])
--
- ;; Compare vectors producing a vector result and a predicate, setting CR6 to
- ;; indicate a combined status
- (define_insn "*vsx_eq_<mode>_p"
-@@ -798,13 +1051,13 @@
-
- ;; Copy sign
- (define_insn "vsx_copysign<mode>3"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (unspec:VSX_B
-- [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
-- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (unspec:VSX_F
-+ [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
-+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")]
- UNSPEC_COPYSIGN))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>cpsgn<VSs> %x0,%x2,%x1"
-+ "xvcpsgn<VSs> %x0,%x2,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
-@@ -865,10 +1118,10 @@
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "vsx_btrunc<mode>2"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (fix:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>r<VSs>iz %x0,%x1"
-+ "xvr<VSs>iz %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
-@@ -882,20 +1135,20 @@
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "vsx_floor<mode>2"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
- UNSPEC_FRIM))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>r<VSs>im %x0,%x1"
-+ "xvr<VSs>im %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
- (define_insn "vsx_ceil<mode>2"
-- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
-+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
- UNSPEC_FRIP))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "x<VSv>r<VSs>ip %x0,%x1"
-+ "xvr<VSs>ip %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
-
-@@ -942,6 +1195,40 @@
- "xscvspdp %x0,%x1"
- [(set_attr "type" "fp")])
-
-+;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs
-+(define_insn "vsx_xscvdpspn"
-+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,?wa")
-+ (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")]
-+ UNSPEC_VSX_CVDPSPN))]
-+ "TARGET_XSCVDPSPN"
-+ "xscvdpspn %x0,%x1"
-+ [(set_attr "type" "fp")])
-+
-+(define_insn "vsx_xscvspdpn"
-+ [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa")
-+ (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
-+ UNSPEC_VSX_CVSPDPN))]
-+ "TARGET_XSCVSPDPN"
-+ "xscvspdpn %x0,%x1"
-+ [(set_attr "type" "fp")])
-+
-+(define_insn "vsx_xscvdpspn_scalar"
-+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
-+ (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")]
-+ UNSPEC_VSX_CVDPSPN))]
-+ "TARGET_XSCVDPSPN"
-+ "xscvdpspn %x0,%x1"
-+ [(set_attr "type" "fp")])
-+
-+;; Used by direct move to move a SFmode value from GPR to VSX register
-+(define_insn "vsx_xscvspdpn_directmove"
-+ [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
-+ (unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
-+ UNSPEC_VSX_CVSPDPN))]
-+ "TARGET_XSCVSPDPN"
-+ "xscvspdpn %x0,%x1"
-+ [(set_attr "type" "fp")])
-+
- ;; Convert from 64-bit to 32-bit types
- ;; Note, favor the Altivec registers since the usual use of these instructions
- ;; is in vector converts and we need to use the Altivec vperm instruction.
-@@ -1027,73 +1314,21 @@
- (set_attr "fp_type" "<VSfptype_simple>")])
-
-
--;; Logical and permute operations
--(define_insn "*vsx_and<mode>3"
-- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
-- (and:VSX_L
-- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")
-- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa")))]
-- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "xxland %x0,%x1,%x2"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*vsx_ior<mode>3"
-- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
-- (ior:VSX_L (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")
-- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa")))]
-- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "xxlor %x0,%x1,%x2"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*vsx_xor<mode>3"
-- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
-- (xor:VSX_L
-- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")
-- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa")))]
-- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "xxlxor %x0,%x1,%x2"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*vsx_one_cmpl<mode>2"
-- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
-- (not:VSX_L
-- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")))]
-- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "xxlnor %x0,%x1,%x1"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*vsx_nor<mode>3"
-- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
-- (not:VSX_L
-- (ior:VSX_L
-- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")
-- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa"))))]
-- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "xxlnor %x0,%x1,%x2"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*vsx_andc<mode>3"
-- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
-- (and:VSX_L
-- (not:VSX_L
-- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,?wa"))
-- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,?wa")))]
-- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "xxlandc %x0,%x1,%x2"
-- [(set_attr "type" "vecsimple")])
--
--
- ;; Permute operations
-
- ;; Build a V2DF/V2DI vector from two scalars
- (define_insn "vsx_concat_<mode>"
-- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa")
-- (unspec:VSX_D
-- [(match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa")
-- (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")]
-- UNSPEC_VSX_CONCAT))]
-+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?wa")
-+ (vec_concat:VSX_D
-+ (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa")
-+ (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "xxpermdi %x0,%x1,%x2,0"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "xxpermdi %x0,%x1,%x2,0";
-+ else
-+ return "xxpermdi %x0,%x2,%x1,0";
-+}
- [(set_attr "type" "vecperm")])
-
- ;; Special purpose concat using xxpermdi to glue two single precision values
-@@ -1106,9 +1341,176 @@
- (match_operand:SF 2 "vsx_register_operand" "f,f")]
- UNSPEC_VSX_CONCAT))]
- "VECTOR_MEM_VSX_P (V2DFmode)"
-- "xxpermdi %x0,%x1,%x2,0"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "xxpermdi %x0,%x1,%x2,0";
-+ else
-+ return "xxpermdi %x0,%x2,%x1,0";
-+}
- [(set_attr "type" "vecperm")])
-
-+;; xxpermdi for little endian loads and stores. We need several of
-+;; these since the form of the PARALLEL differs by mode.
-+(define_insn "*vsx_xxpermdi2_le_<mode>"
-+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
-+ (vec_select:VSX_D
-+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")
-+ (parallel [(const_int 1) (const_int 0)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
-+ "xxpermdi %x0,%x1,%x1,2"
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "*vsx_xxpermdi4_le_<mode>"
-+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
-+ (vec_select:VSX_W
-+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
-+ "xxpermdi %x0,%x1,%x1,2"
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "*vsx_xxpermdi8_le_V8HI"
-+ [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")
-+ (vec_select:V8HI
-+ (match_operand:V8HI 1 "vsx_register_operand" "wa")
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)"
-+ "xxpermdi %x0,%x1,%x1,2"
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "*vsx_xxpermdi16_le_V16QI"
-+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
-+ (vec_select:V16QI
-+ (match_operand:V16QI 1 "vsx_register_operand" "wa")
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)"
-+ "xxpermdi %x0,%x1,%x1,2"
-+ [(set_attr "type" "vecperm")])
-+
-+;; lxvd2x for little endian loads. We need several of
-+;; these since the form of the PARALLEL differs by mode.
-+(define_insn "*vsx_lxvd2x2_le_<mode>"
-+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
-+ (vec_select:VSX_D
-+ (match_operand:VSX_D 1 "memory_operand" "Z")
-+ (parallel [(const_int 1) (const_int 0)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
-+ "lxvd2x %x0,%y1"
-+ [(set_attr "type" "vecload")])
-+
-+(define_insn "*vsx_lxvd2x4_le_<mode>"
-+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
-+ (vec_select:VSX_W
-+ (match_operand:VSX_W 1 "memory_operand" "Z")
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
-+ "lxvd2x %x0,%y1"
-+ [(set_attr "type" "vecload")])
-+
-+(define_insn "*vsx_lxvd2x8_le_V8HI"
-+ [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")
-+ (vec_select:V8HI
-+ (match_operand:V8HI 1 "memory_operand" "Z")
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)"
-+ "lxvd2x %x0,%y1"
-+ [(set_attr "type" "vecload")])
-+
-+(define_insn "*vsx_lxvd2x16_le_V16QI"
-+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
-+ (vec_select:V16QI
-+ (match_operand:V16QI 1 "memory_operand" "Z")
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)"
-+ "lxvd2x %x0,%y1"
-+ [(set_attr "type" "vecload")])
-+
-+;; stxvd2x for little endian stores. We need several of
-+;; these since the form of the PARALLEL differs by mode.
-+(define_insn "*vsx_stxvd2x2_le_<mode>"
-+ [(set (match_operand:VSX_D 0 "memory_operand" "=Z")
-+ (vec_select:VSX_D
-+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")
-+ (parallel [(const_int 1) (const_int 0)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
-+ "stxvd2x %x1,%y0"
-+ [(set_attr "type" "vecstore")])
-+
-+(define_insn "*vsx_stxvd2x4_le_<mode>"
-+ [(set (match_operand:VSX_W 0 "memory_operand" "=Z")
-+ (vec_select:VSX_W
-+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")
-+ (parallel [(const_int 2) (const_int 3)
-+ (const_int 0) (const_int 1)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
-+ "stxvd2x %x1,%y0"
-+ [(set_attr "type" "vecstore")])
-+
-+(define_insn "*vsx_stxvd2x8_le_V8HI"
-+ [(set (match_operand:V8HI 0 "memory_operand" "=Z")
-+ (vec_select:V8HI
-+ (match_operand:V8HI 1 "vsx_register_operand" "wa")
-+ (parallel [(const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)"
-+ "stxvd2x %x1,%y0"
-+ [(set_attr "type" "vecstore")])
-+
-+(define_insn "*vsx_stxvd2x16_le_V16QI"
-+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
-+ (vec_select:V16QI
-+ (match_operand:V16QI 1 "vsx_register_operand" "wa")
-+ (parallel [(const_int 8) (const_int 9)
-+ (const_int 10) (const_int 11)
-+ (const_int 12) (const_int 13)
-+ (const_int 14) (const_int 15)
-+ (const_int 0) (const_int 1)
-+ (const_int 2) (const_int 3)
-+ (const_int 4) (const_int 5)
-+ (const_int 6) (const_int 7)])))]
-+ "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)"
-+ "stxvd2x %x1,%y0"
-+ [(set_attr "type" "vecstore")])
-+
-+;; Convert a TImode value into V1TImode
-+(define_expand "vsx_set_v1ti"
-+ [(match_operand:V1TI 0 "nonimmediate_operand" "")
-+ (match_operand:V1TI 1 "nonimmediate_operand" "")
-+ (match_operand:TI 2 "input_operand" "")
-+ (match_operand:QI 3 "u5bit_cint_operand" "")]
-+ "VECTOR_MEM_VSX_P (V1TImode)"
-+{
-+ if (operands[3] != const0_rtx)
-+ gcc_unreachable ();
-+
-+ emit_move_insn (operands[0], gen_lowpart (V1TImode, operands[1]));
-+ DONE;
-+})
-+
- ;; Set the element of a V2DI/VD2F mode
- (define_insn "vsx_set_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa")
-@@ -1118,9 +1520,10 @@
- UNSPEC_VSX_SET))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- {
-- if (INTVAL (operands[3]) == 0)
-+ int idx_first = BYTES_BIG_ENDIAN ? 0 : 1;
-+ if (INTVAL (operands[3]) == idx_first)
- return \"xxpermdi %x0,%x2,%x1,1\";
-- else if (INTVAL (operands[3]) == 1)
-+ else if (INTVAL (operands[3]) == 1 - idx_first)
- return \"xxpermdi %x0,%x1,%x2,0\";
- else
- gcc_unreachable ();
-@@ -1135,8 +1538,12 @@
- [(match_operand:QI 2 "u5bit_cint_operand" "i,i,i")])))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- {
-+ int fldDM;
- gcc_assert (UINTVAL (operands[2]) <= 1);
-- operands[3] = GEN_INT (INTVAL (operands[2]) << 1);
-+ fldDM = INTVAL (operands[2]) << 1;
-+ if (!BYTES_BIG_ENDIAN)
-+ fldDM = 3 - fldDM;
-+ operands[3] = GEN_INT (fldDM);
- return \"xxpermdi %x0,%x1,%x1,%3\";
- }
- [(set_attr "type" "vecperm")])
-@@ -1149,9 +1556,28 @@
- (parallel [(const_int 0)])))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && WORDS_BIG_ENDIAN"
- "lxsd%U1x %x0,%y1"
-- [(set_attr "type" "fpload")
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (const_string "fpload")))
- (set_attr "length" "4")])
-
-+;; Optimize extracting element 1 from memory for little endian
-+(define_insn "*vsx_extract_<mode>_one_le"
-+ [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=ws,d,?wa")
-+ (vec_select:<VS_scalar>
-+ (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z,Z,Z")
-+ (parallel [(const_int 1)])))]
-+ "VECTOR_MEM_VSX_P (<MODE>mode) && !WORDS_BIG_ENDIAN"
-+ "lxsd%U1x %x0,%y1"
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (const_string "fpload")))
-+ (set_attr "length" "4")])
-+
- ;; Extract a SF element from V4SF
- (define_insn_and_split "vsx_extract_v4sf"
- [(set (match_operand:SF 0 "vsx_register_operand" "=f,f")
-@@ -1172,7 +1598,7 @@
- rtx op2 = operands[2];
- rtx op3 = operands[3];
- rtx tmp;
-- HOST_WIDE_INT ele = INTVAL (op2);
-+ HOST_WIDE_INT ele = BYTES_BIG_ENDIAN ? INTVAL (op2) : 3 - INTVAL (op2);
-
- if (ele == 0)
- tmp = op1;
-@@ -1213,11 +1639,22 @@
- if (<MODE>mode != V2DImode)
- {
- target = gen_lowpart (V2DImode, target);
-- op0 = gen_lowpart (V2DImode, target);
-- op1 = gen_lowpart (V2DImode, target);
-+ op0 = gen_lowpart (V2DImode, op0);
-+ op1 = gen_lowpart (V2DImode, op1);
- }
- }
-- emit_insn (gen (target, op0, op1, perm0, perm1));
-+ /* In little endian mode, vsx_xxpermdi2_<mode>_1 will perform a
-+ transformation we don't want; it is necessary for
-+ rs6000_expand_vec_perm_const_1 but not for this use. So we
-+ prepare for that by reversing the transformation here. */
-+ if (BYTES_BIG_ENDIAN)
-+ emit_insn (gen (target, op0, op1, perm0, perm1));
-+ else
-+ {
-+ rtx p0 = GEN_INT (3 - INTVAL (perm1));
-+ rtx p1 = GEN_INT (3 - INTVAL (perm0));
-+ emit_insn (gen (target, op1, op0, p0, p1));
-+ }
- DONE;
- })
-
-@@ -1231,9 +1668,32 @@
- (match_operand 4 "const_2_to_3_operand" "")])))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- {
-- int mask = (INTVAL (operands[3]) << 1) | (INTVAL (operands[4]) - 2);
-+ int op3, op4, mask;
-+
-+ /* For little endian, swap operands and invert/swap selectors
-+ to get the correct xxpermdi. The operand swap sets up the
-+ inputs as a little endian array. The selectors are swapped
-+ because they are defined to use big endian ordering. The
-+ selectors are inverted to get the correct doublewords for
-+ little endian ordering. */
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ op3 = INTVAL (operands[3]);
-+ op4 = INTVAL (operands[4]);
-+ }
-+ else
-+ {
-+ op3 = 3 - INTVAL (operands[4]);
-+ op4 = 3 - INTVAL (operands[3]);
-+ }
-+
-+ mask = (op3 << 1) | (op4 - 2);
- operands[3] = GEN_INT (mask);
-- return "xxpermdi %x0,%x1,%x2,%3";
-+
-+ if (BYTES_BIG_ENDIAN)
-+ return "xxpermdi %x0,%x1,%x2,%3";
-+ else
-+ return "xxpermdi %x0,%x2,%x1,%3";
- }
- [(set_attr "type" "vecperm")])
-
-@@ -1252,25 +1712,57 @@
-
- ;; Expanders for builtins
- (define_expand "vsx_mergel_<mode>"
-- [(set (match_operand:VSX_D 0 "vsx_register_operand" "")
-- (vec_select:VSX_D
-- (vec_concat:<VS_double>
-- (match_operand:VSX_D 1 "vsx_register_operand" "")
-- (match_operand:VSX_D 2 "vsx_register_operand" ""))
-- (parallel [(const_int 1) (const_int 3)])))]
-+ [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
-+ (use (match_operand:VSX_D 1 "vsx_register_operand" ""))
-+ (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "")
-+{
-+ rtvec v;
-+ rtx x;
-
-+ /* Special handling for LE with -maltivec=be. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ v = gen_rtvec (2, GEN_INT (0), GEN_INT (2));
-+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[2], operands[1]);
-+ }
-+ else
-+ {
-+ v = gen_rtvec (2, GEN_INT (1), GEN_INT (3));
-+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[1], operands[2]);
-+ }
-+
-+ x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
- (define_expand "vsx_mergeh_<mode>"
-- [(set (match_operand:VSX_D 0 "vsx_register_operand" "")
-- (vec_select:VSX_D
-- (vec_concat:<VS_double>
-- (match_operand:VSX_D 1 "vsx_register_operand" "")
-- (match_operand:VSX_D 2 "vsx_register_operand" ""))
-- (parallel [(const_int 0) (const_int 2)])))]
-+ [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
-+ (use (match_operand:VSX_D 1 "vsx_register_operand" ""))
-+ (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "")
-+{
-+ rtvec v;
-+ rtx x;
-
-+ /* Special handling for LE with -maltivec=be. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ v = gen_rtvec (2, GEN_INT (1), GEN_INT (3));
-+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[2], operands[1]);
-+ }
-+ else
-+ {
-+ v = gen_rtvec (2, GEN_INT (0), GEN_INT (2));
-+ x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[1], operands[2]);
-+ }
-+
-+ x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
- ;; V2DF/V2DI splat
- (define_insn "vsx_splat_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?wa,?wa,?wa")
-@@ -1295,6 +1787,20 @@
- (parallel
- [(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
-+{
-+ if (!BYTES_BIG_ENDIAN)
-+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));
-+
-+ return "xxspltw %x0,%x1,%2";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "vsx_xxspltw_<mode>_direct"
-+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
-+ (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
-+ (match_operand:QI 2 "u5bit_cint_operand" "i,i")]
-+ UNSPEC_VSX_XXSPLTW))]
-+ "VECTOR_MEM_VSX_P (<MODE>mode)"
- "xxspltw %x0,%x1,%2"
- [(set_attr "type" "vecperm")])
-
-@@ -1308,7 +1814,12 @@
- (parallel [(const_int 0) (const_int 4)
- (const_int 1) (const_int 5)])))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "xxmrghw %x0,%x1,%x2"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "xxmrghw %x0,%x1,%x2";
-+ else
-+ return "xxmrglw %x0,%x2,%x1";
-+}
- [(set_attr "type" "vecperm")])
-
- (define_insn "vsx_xxmrglw_<mode>"
-@@ -1320,7 +1831,12 @@
- (parallel [(const_int 2) (const_int 6)
- (const_int 3) (const_int 7)])))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
-- "xxmrglw %x0,%x1,%x2"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "xxmrglw %x0,%x1,%x2";
-+ else
-+ return "xxmrghw %x0,%x2,%x1";
-+}
- [(set_attr "type" "vecperm")])
-
- ;; Shift left double by word immediate
-@@ -1483,3 +1999,27 @@
- }"
- [(set_attr "length" "20")
- (set_attr "type" "veccomplex")])
-+
-+
-+;; Power8 Vector fusion. The fused ops must be physically adjacent.
-+(define_peephole
-+ [(set (match_operand:P 0 "base_reg_operand" "")
-+ (match_operand:P 1 "short_cint_operand" ""))
-+ (set (match_operand:VSX_M2 2 "vsx_register_operand" "")
-+ (mem:VSX_M2 (plus:P (match_dup 0)
-+ (match_operand:P 3 "int_reg_operand" ""))))]
-+ "TARGET_VSX && TARGET_P8_FUSION"
-+ "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3"
-+ [(set_attr "length" "8")
-+ (set_attr "type" "vecload")])
-+
-+(define_peephole
-+ [(set (match_operand:P 0 "base_reg_operand" "")
-+ (match_operand:P 1 "short_cint_operand" ""))
-+ (set (match_operand:VSX_M2 2 "vsx_register_operand" "")
-+ (mem:VSX_M2 (plus:P (match_operand:P 3 "int_reg_operand" "")
-+ (match_dup 0))))]
-+ "TARGET_VSX && TARGET_P8_FUSION"
-+ "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3"
-+ [(set_attr "length" "8")
-+ (set_attr "type" "vecload")])
-Index: gcc/config/rs6000/rs6000.h
-===================================================================
---- a/src/gcc/config/rs6000/rs6000.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000.h (.../branches/gcc-4_8-branch)
-@@ -92,7 +92,7 @@
- #ifdef HAVE_AS_POWER8
- #define ASM_CPU_POWER8_SPEC "-mpower8"
- #else
--#define ASM_CPU_POWER8_SPEC "-mpower4 -maltivec"
-+#define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC
- #endif
-
- #ifdef HAVE_AS_DCI
-@@ -164,6 +164,7 @@
- %{mcpu=e6500: -me6500} \
- %{maltivec: -maltivec} \
- %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
-+%{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
- -many"
-
- #define CPP_DEFAULT_SPEC ""
-@@ -277,6 +278,21 @@
- #define TARGET_POPCNTD 0
- #endif
-
-+/* Define the ISA 2.07 flags as 0 if the target assembler does not support the
-+ waitasecond instruction. Allow -mpower8-fusion, since it does not add new
-+ instructions. */
-+
-+#ifndef HAVE_AS_POWER8
-+#undef TARGET_DIRECT_MOVE
-+#undef TARGET_CRYPTO
-+#undef TARGET_HTM
-+#undef TARGET_P8_VECTOR
-+#define TARGET_DIRECT_MOVE 0
-+#define TARGET_CRYPTO 0
-+#define TARGET_HTM 0
-+#define TARGET_P8_VECTOR 0
-+#endif
-+
- /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
- not, generate the lwsync code as an integer constant. */
- #ifdef HAVE_AS_LWSYNC
-@@ -386,6 +402,7 @@
- #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
- #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
-
-+/* Describe the vector unit used for arithmetic operations. */
- extern enum rs6000_vector rs6000_vector_unit[];
-
- #define VECTOR_UNIT_NONE_P(MODE) \
-@@ -394,12 +411,25 @@
- #define VECTOR_UNIT_VSX_P(MODE) \
- (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
-
-+#define VECTOR_UNIT_P8_VECTOR_P(MODE) \
-+ (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
-+
- #define VECTOR_UNIT_ALTIVEC_P(MODE) \
- (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
-
-+#define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
-+ (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
-+ (int)VECTOR_VSX, \
-+ (int)VECTOR_P8_VECTOR))
-+
-+/* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
-+ altivec (VMX) or VSX vector instructions. P8 vector support is upwards
-+ compatible, so allow it as well, rather than changing all of the uses of the
-+ macro. */
- #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
-- (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \
-- || rs6000_vector_unit[(MODE)] == VECTOR_VSX)
-+ (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
-+ (int)VECTOR_ALTIVEC, \
-+ (int)VECTOR_P8_VECTOR))
-
- /* Describe whether to use VSX loads or Altivec loads. For now, just use the
- same unit as the vector unit we are using, but we may want to migrate to
-@@ -412,12 +442,21 @@
- #define VECTOR_MEM_VSX_P(MODE) \
- (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
-
-+#define VECTOR_MEM_P8_VECTOR_P(MODE) \
-+ (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
-+
- #define VECTOR_MEM_ALTIVEC_P(MODE) \
- (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
-
-+#define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
-+ (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
-+ (int)VECTOR_VSX, \
-+ (int)VECTOR_P8_VECTOR))
-+
- #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
-- (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \
-- || rs6000_vector_mem[(MODE)] == VECTOR_VSX)
-+ (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
-+ (int)VECTOR_ALTIVEC, \
-+ (int)VECTOR_P8_VECTOR))
-
- /* Return the alignment of a given vector type, which is set based on the
- vector unit use. VSX for instance can load 32 or 64 bit aligned words
-@@ -429,6 +468,15 @@
- ? rs6000_vector_align[(MODE)] \
- : (int)GET_MODE_BITSIZE ((MODE)))
-
-+/* Determine the element order to use for vector instructions. By
-+ default we use big-endian element order when targeting big-endian,
-+ and little-endian element order when targeting little-endian. For
-+ programs being ported from BE Power to LE Power, it can sometimes
-+ be useful to use big-endian element order when targeting little-endian.
-+ This is set via -maltivec=be, for example. */
-+#define VECTOR_ELT_ORDER_BIG \
-+ (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
-+
- /* Alignment options for fields in structures for sub-targets following
- AIX-like ABI.
- ALIGN_POWER word-aligns FP doubles (default AIX ABI).
-@@ -479,16 +527,38 @@
- #define TARGET_FCTIDUZ TARGET_POPCNTD
- #define TARGET_FCTIWUZ TARGET_POPCNTD
-
-+#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
-+#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
-+#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
-+
-+/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
-+ in power7, so conditionalize them on p8 features. TImode syncs need quad
-+ memory support. */
-+#define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
-+ || TARGET_QUAD_MEMORY_ATOMIC \
-+ || TARGET_DIRECT_MOVE)
-+
-+#define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
-+
-+/* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
-+ to allocate the SDmode stack slot to get the value into the proper location
-+ in the register. */
-+#define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
-+
- /* In switching from using target_flags to using rs6000_isa_flags, the options
- machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
- OPTION_MASK_<xxx> back into MASK_<xxx>. */
- #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
- #define MASK_CMPB OPTION_MASK_CMPB
-+#define MASK_CRYPTO OPTION_MASK_CRYPTO
- #define MASK_DFP OPTION_MASK_DFP
-+#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
- #define MASK_DLMZB OPTION_MASK_DLMZB
- #define MASK_EABI OPTION_MASK_EABI
- #define MASK_FPRND OPTION_MASK_FPRND
-+#define MASK_P8_FUSION OPTION_MASK_P8_FUSION
- #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
-+#define MASK_HTM OPTION_MASK_HTM
- #define MASK_ISEL OPTION_MASK_ISEL
- #define MASK_MFCRF OPTION_MASK_MFCRF
- #define MASK_MFPGPR OPTION_MASK_MFPGPR
-@@ -495,6 +565,7 @@
- #define MASK_MULHW OPTION_MASK_MULHW
- #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
- #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
-+#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
- #define MASK_POPCNTB OPTION_MASK_POPCNTB
- #define MASK_POPCNTD OPTION_MASK_POPCNTD
- #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
-@@ -505,6 +576,7 @@
- #define MASK_STRING OPTION_MASK_STRING
- #define MASK_UPDATE OPTION_MASK_UPDATE
- #define MASK_VSX OPTION_MASK_VSX
-+#define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE
-
- #ifndef IN_LIBGCC2
- #define MASK_POWERPC64 OPTION_MASK_POWERPC64
-@@ -551,7 +623,8 @@
- || TARGET_CMPB /* ISA 2.05 */ \
- || TARGET_POPCNTD /* ISA 2.06 */ \
- || TARGET_ALTIVEC \
-- || TARGET_VSX)))
-+ || TARGET_VSX \
-+ || TARGET_HARD_FLOAT)))
-
- /* E500 cores only support plain "sync", not lwsync. */
- #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
-@@ -558,6 +631,25 @@
- || rs6000_cpu == PROCESSOR_PPC8548)
-
-
-+/* Whether SF/DF operations are supported on the E500. */
-+#define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \
-+ && !TARGET_FPRS)
-+
-+#define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
-+ && !TARGET_FPRS && TARGET_E500_DOUBLE)
-+
-+/* Whether SF/DF operations are supported by by the normal floating point unit
-+ (or the vector/scalar unit). */
-+#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
-+ && TARGET_SINGLE_FLOAT)
-+
-+#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
-+ && TARGET_DOUBLE_FLOAT)
-+
-+/* Whether SF/DF operations are supported by any hardware. */
-+#define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE)
-+#define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE)
-+
- /* Which machine supports the various reciprocal estimate instructions. */
- #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
- && TARGET_FPRS && TARGET_SINGLE_FLOAT)
-@@ -595,9 +687,6 @@
- #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
- (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
-
--#define RS6000_RECIP_HIGH_PRECISION_P(MODE) \
-- ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION)
--
- /* The default CPU for TARGET_OPTION_OVERRIDE. */
- #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
-
-@@ -760,12 +849,6 @@
- /* No data type wants to be aligned rounder than this. */
- #define BIGGEST_ALIGNMENT 128
-
--/* A C expression to compute the alignment for a variables in the
-- local store. TYPE is the data type, and ALIGN is the alignment
-- that the object would ordinarily have. */
--#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
-- DATA_ALIGNMENT (TYPE, ALIGN)
--
- /* Alignment of field after `int : 0' in a structure. */
- #define EMPTY_FIELD_BOUNDARY 32
-
-@@ -775,8 +858,15 @@
- /* A bit-field declared as `int' forces `int' alignment for the struct. */
- #define PCC_BITFIELD_TYPE_MATTERS 1
-
--/* Make strings word-aligned so strcpy from constants will be faster.
-- Make vector constants quadword aligned. */
-+enum data_align { align_abi, align_opt, align_both };
-+
-+/* A C expression to compute the alignment for a variables in the
-+ local store. TYPE is the data type, and ALIGN is the alignment
-+ that the object would ordinarily have. */
-+#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
-+ rs6000_data_alignment (TYPE, ALIGN, align_both)
-+
-+/* Make strings word-aligned so strcpy from constants will be faster. */
- #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
- (TREE_CODE (EXP) == STRING_CST \
- && (STRICT_ALIGNMENT || !optimize_size) \
-@@ -784,21 +874,14 @@
- ? BITS_PER_WORD \
- : (ALIGN))
-
--/* Make arrays of chars word-aligned for the same reasons.
-- Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
-+/* Make arrays of chars word-aligned for the same reasons. */
-+#define DATA_ALIGNMENT(TYPE, ALIGN) \
-+ rs6000_data_alignment (TYPE, ALIGN, align_opt)
-+
-+/* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
- 64 bits. */
--#define DATA_ALIGNMENT(TYPE, ALIGN) \
-- (TREE_CODE (TYPE) == VECTOR_TYPE \
-- ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \
-- || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \
-- ? 64 : 128) \
-- : ((TARGET_E500_DOUBLE \
-- && TREE_CODE (TYPE) == REAL_TYPE \
-- && TYPE_MODE (TYPE) == DFmode) \
-- ? 64 \
-- : (TREE_CODE (TYPE) == ARRAY_TYPE \
-- && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
-- && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)))
-+#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
-+ rs6000_data_alignment (TYPE, ALIGN, align_abi)
-
- /* Nonzero if move instructions will actually fail to work
- when given unaligned data. */
-@@ -842,15 +925,17 @@
- in inline functions.
-
- Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
-- pointer, which is eventually eliminated in favor of SP or FP. */
-+ pointer, which is eventually eliminated in favor of SP or FP.
-
--#define FIRST_PSEUDO_REGISTER 114
-+ The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
-
-+#define FIRST_PSEUDO_REGISTER 117
-+
- /* This must be included for pre gcc 3.0 glibc compatibility. */
- #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
-
- /* Add 32 dwarf columns for synthetic SPE registers. */
--#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
-+#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32)
-
- /* The SPE has an additional 32 synthetic registers, with DWARF debug
- info numbering for these registers starting at 1200. While eh_frame
-@@ -866,7 +951,7 @@
- We must map them here to avoid huge unwinder tables mostly consisting
- of unused space. */
- #define DWARF_REG_TO_UNWIND_COLUMN(r) \
-- ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
-+ ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
-
- /* Use standard DWARF numbering for DWARF debugging information. */
- #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
-@@ -906,7 +991,7 @@
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 1, 1 \
-- , 1, 1, 1 \
-+ , 1, 1, 1, 1, 1, 1 \
- }
-
- /* 1 for registers not available across function calls.
-@@ -926,7 +1011,7 @@
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 1, 1 \
-- , 1, 1, 1 \
-+ , 1, 1, 1, 1, 1, 1 \
- }
-
- /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
-@@ -945,7 +1030,7 @@
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0 \
-- , 0, 0, 0 \
-+ , 0, 0, 0, 0, 0, 0 \
- }
-
- #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
-@@ -984,6 +1069,9 @@
- vrsave, vscr (fixed)
- spe_acc, spefscr (fixed)
- sfp (fixed)
-+ tfhar (fixed)
-+ tfiar (fixed)
-+ texasr (fixed)
- */
-
- #if FIXED_R2 == 1
-@@ -1004,7 +1092,9 @@
-
- #define REG_ALLOC_ORDER \
- {32, \
-- 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
-+ /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
-+ /* not use fr14 which is a saved register. */ \
-+ 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
- 33, \
- 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
- 50, 49, 48, 47, 46, \
-@@ -1023,7 +1113,7 @@
- 96, 95, 94, 93, 92, 91, \
- 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
- 109, 110, \
-- 111, 112, 113 \
-+ 111, 112, 113, 114, 115, 116 \
- }
-
- /* True if register is floating-point. */
-@@ -1064,8 +1154,11 @@
- #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
-
- /* Alternate name for any vector register supporting logical operations, no
-- matter which instruction set(s) are available. */
--#define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)
-+ matter which instruction set(s) are available. Allow GPRs as well as the
-+ vector registers. */
-+#define VLOGICAL_REGNO_P(N) \
-+ (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
-+ || (TARGET_VSX && FP_REGNO_P (N))) \
-
- /* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE. */
-@@ -1106,7 +1199,7 @@
-
- #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
- (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
-- || (MODE) == V2DImode)
-+ || (MODE) == V2DImode || (MODE) == V1TImode)
-
- #define SPE_VECTOR_MODE(MODE) \
- ((MODE) == V4HImode \
-@@ -1125,28 +1218,32 @@
- /* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-- for any hard reg, then this must be 0 for correct output. */
--#define MODES_TIEABLE_P(MODE1, MODE2) \
-- (SCALAR_FLOAT_MODE_P (MODE1) \
-+ for any hard reg, then this must be 0 for correct output.
-+
-+ PTImode cannot tie with other modes because PTImode is restricted to even
-+ GPR registers, and TImode can go in any GPR as well as VSX registers (PR
-+ 57744). */
-+#define MODES_TIEABLE_P(MODE1, MODE2) \
-+ ((MODE1) == PTImode \
-+ ? (MODE2) == PTImode \
-+ : (MODE2) == PTImode \
-+ ? 0 \
-+ : SCALAR_FLOAT_MODE_P (MODE1) \
- ? SCALAR_FLOAT_MODE_P (MODE2) \
- : SCALAR_FLOAT_MODE_P (MODE2) \
-- ? SCALAR_FLOAT_MODE_P (MODE1) \
-+ ? 0 \
- : GET_MODE_CLASS (MODE1) == MODE_CC \
- ? GET_MODE_CLASS (MODE2) == MODE_CC \
- : GET_MODE_CLASS (MODE2) == MODE_CC \
-- ? GET_MODE_CLASS (MODE1) == MODE_CC \
-+ ? 0 \
- : SPE_VECTOR_MODE (MODE1) \
- ? SPE_VECTOR_MODE (MODE2) \
- : SPE_VECTOR_MODE (MODE2) \
-- ? SPE_VECTOR_MODE (MODE1) \
-- : ALTIVEC_VECTOR_MODE (MODE1) \
-- ? ALTIVEC_VECTOR_MODE (MODE2) \
-- : ALTIVEC_VECTOR_MODE (MODE2) \
-- ? ALTIVEC_VECTOR_MODE (MODE1) \
-+ ? 0 \
- : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
- ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
- : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
-- ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
-+ ? 0 \
- : 1)
-
- /* Post-reload, we can't use any new AltiVec registers, as we already
-@@ -1240,6 +1337,7 @@
- VSCR_REGS,
- SPE_ACC_REGS,
- SPEFSCR_REGS,
-+ SPR_REGS,
- NON_SPECIAL_REGS,
- LINK_REGS,
- CTR_REGS,
-@@ -1270,6 +1368,7 @@
- "VSCR_REGS", \
- "SPE_ACC_REGS", \
- "SPEFSCR_REGS", \
-+ "SPR_REGS", \
- "NON_SPECIAL_REGS", \
- "LINK_REGS", \
- "CTR_REGS", \
-@@ -1299,6 +1398,7 @@
- { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
-+ { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \
- { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
- { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
- { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
-@@ -1309,7 +1409,7 @@
- { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
- { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \
- { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
-- { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0003ffff } /* ALL_REGS */ \
-+ { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \
- }
-
- /* The same information, inverted:
-@@ -1337,7 +1437,18 @@
- RS6000_CONSTRAINT_wa, /* Any VSX register */
- RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
- RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
-+ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
-+ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
-+ RS6000_CONSTRAINT_wm, /* VSX register for direct move */
-+ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
- RS6000_CONSTRAINT_ws, /* VSX register for DF */
-+ RS6000_CONSTRAINT_wt, /* VSX register for TImode */
-+ RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */
-+ RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */
-+ RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
-+ RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
-+ RS6000_CONSTRAINT_wy, /* VSX register for SF */
-+ RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */
- RS6000_CONSTRAINT_MAX
- };
-
-@@ -1425,21 +1536,14 @@
- arguments. */
- #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 || flag_asan != 0)
-
--/* Size of the outgoing register save area */
--#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
-- || DEFAULT_ABI == ABI_DARWIN) \
-- ? (TARGET_64BIT ? 64 : 32) \
-- : 0)
--
- /* Size of the fixed area on the stack */
- #define RS6000_SAVE_AREA \
-- (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
-+ ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
- << (TARGET_64BIT ? 1 : 0))
-
--/* MEM representing address to save the TOC register */
--#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
-- plus_constant (Pmode, stack_pointer_rtx, \
-- (TARGET_32BIT ? 20 : 40)))
-+/* Stack offset for toc save slot. */
-+#define RS6000_TOC_SAVE_SLOT \
-+ ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
-
- /* Align an address */
- #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
-@@ -1489,7 +1593,7 @@
- /* Define this if stack space is still allocated for a parameter passed
- in a register. The value is the number of bytes allocated to this
- area. */
--#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
-+#define REG_PARM_STACK_SPACE(FNDECL) rs6000_reg_parm_stack_space((FNDECL))
-
- /* Define this if the above stack space is to be considered part of the
- space allocated by the caller. */
-@@ -1522,7 +1626,7 @@
- NONLOCAL needs twice Pmode to maintain both backchain and SP. */
- #define STACK_SAVEAREA_MODE(LEVEL) \
- (LEVEL == SAVE_FUNCTION ? VOIDmode \
-- : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
-+ : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
-
- /* Minimum and maximum general purpose registers used to hold arguments. */
- #define GP_ARG_MIN_REG 3
-@@ -1533,9 +1637,8 @@
- #define FP_ARG_MIN_REG 33
- #define FP_ARG_AIX_MAX_REG 45
- #define FP_ARG_V4_MAX_REG 40
--#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
-- || DEFAULT_ABI == ABI_DARWIN) \
-- ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
-+#define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
-+ ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
- #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
-
- /* Minimum and maximum AltiVec registers used to hold arguments. */
-@@ -1543,10 +1646,17 @@
- #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
- #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
-
-+/* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
-+#define AGGR_ARG_NUM_REG 8
-+
- /* Return registers */
- #define GP_ARG_RETURN GP_ARG_MIN_REG
- #define FP_ARG_RETURN FP_ARG_MIN_REG
- #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
-+#define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
-+ : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
-+#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \
-+ : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
-
- /* Flags for the call/call_value rtl operations set up by function_arg */
- #define CALL_NORMAL 0x00000000 /* no special processing */
-@@ -1566,8 +1676,10 @@
- On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
- #define FUNCTION_VALUE_REGNO_P(N) \
- ((N) == GP_ARG_RETURN \
-- || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
-- || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
-+ || ((N) >= FP_ARG_RETURN && (N) <= FP_ARG_MAX_RETURN \
-+ && TARGET_HARD_FLOAT && TARGET_FPRS) \
-+ || ((N) >= ALTIVEC_ARG_RETURN && (N) <= ALTIVEC_ARG_MAX_RETURN \
-+ && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
-
- /* 1 if N is a possible register number for function argument passing.
- On RS/6000, these are r3-r10 and fp1-fp13.
-@@ -1691,11 +1803,8 @@
- /* Number of bytes into the frame return addresses can be found. See
- rs6000_stack_info in rs6000.c for more information on how the different
- abi's store the return address. */
--#define RETURN_ADDRESS_OFFSET \
-- ((DEFAULT_ABI == ABI_AIX \
-- || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
-- (DEFAULT_ABI == ABI_V4) ? 4 : \
-- (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
-+#define RETURN_ADDRESS_OFFSET \
-+ ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
-
- /* The current return address is in link register (65). The return address
- of anything farther back is accessed normally at an offset of 8 from the
-@@ -2215,6 +2324,9 @@
- &rs6000_reg_names[111][0], /* spe_acc */ \
- &rs6000_reg_names[112][0], /* spefscr */ \
- &rs6000_reg_names[113][0], /* sfp */ \
-+ &rs6000_reg_names[114][0], /* tfhar */ \
-+ &rs6000_reg_names[115][0], /* tfiar */ \
-+ &rs6000_reg_names[116][0], /* texasr */ \
- }
-
- /* Table of additional register names to use in user input. */
-@@ -2268,7 +2380,9 @@
- {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
- {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
- {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
-- {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }
-+ {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
-+ /* Transactional Memory Facility (HTM) Registers. */ \
-+ {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} }
-
- /* This is how to output an element of a case-vector that is relative. */
-
-@@ -2357,7 +2471,12 @@
- #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
-
- /* Miscellaneous information. */
--#define RS6000_BTC_OVERLOADED 0x4000000 /* function is overloaded. */
-+#define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */
-+#define RS6000_BTC_VOID 0x02000000 /* function has no return value. */
-+#define RS6000_BTC_OVERLOADED 0x04000000 /* function is overloaded. */
-+#define RS6000_BTC_32BIT 0x08000000 /* function references SPRs. */
-+#define RS6000_BTC_64BIT 0x10000000 /* function references SPRs. */
-+#define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */
-
- /* Convenience macros to document the instruction type. */
- #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
-@@ -2369,6 +2488,9 @@
- #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
- #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
- #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
-+#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
-+#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
-+#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
- #define RS6000_BTM_SPE MASK_STRING /* E500 */
- #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
- #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
-@@ -2377,15 +2499,22 @@
- #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
- #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
- #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
-+#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
-+#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
-
- #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
- | RS6000_BTM_VSX \
-+ | RS6000_BTM_P8_VECTOR \
-+ | RS6000_BTM_CRYPTO \
- | RS6000_BTM_FRE \
- | RS6000_BTM_FRES \
- | RS6000_BTM_FRSQRTE \
- | RS6000_BTM_FRSQRTES \
-+ | RS6000_BTM_HTM \
- | RS6000_BTM_POPCNTD \
-- | RS6000_BTM_CELL)
-+ | RS6000_BTM_CELL \
-+ | RS6000_BTM_DFP \
-+ | RS6000_BTM_HARD_FLOAT)
-
- /* Define builtin enum index. */
-
-@@ -2395,6 +2524,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -2406,6 +2536,7 @@
- #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
- #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-+#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
- #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
- #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
- #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-@@ -2424,6 +2555,7 @@
- #undef RS6000_BUILTIN_A
- #undef RS6000_BUILTIN_D
- #undef RS6000_BUILTIN_E
-+#undef RS6000_BUILTIN_H
- #undef RS6000_BUILTIN_P
- #undef RS6000_BUILTIN_Q
- #undef RS6000_BUILTIN_S
-@@ -2437,6 +2569,7 @@
- RS6000_BTI_opaque_p_V2SI,
- RS6000_BTI_opaque_V4SI,
- RS6000_BTI_V16QI,
-+ RS6000_BTI_V1TI,
- RS6000_BTI_V2SI,
- RS6000_BTI_V2SF,
- RS6000_BTI_V2DI,
-@@ -2446,6 +2579,7 @@
- RS6000_BTI_V4SF,
- RS6000_BTI_V8HI,
- RS6000_BTI_unsigned_V16QI,
-+ RS6000_BTI_unsigned_V1TI,
- RS6000_BTI_unsigned_V8HI,
- RS6000_BTI_unsigned_V4SI,
- RS6000_BTI_unsigned_V2DI,
-@@ -2471,8 +2605,13 @@
- RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
- RS6000_BTI_INTDI, /* intDI_type_node */
- RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
-+ RS6000_BTI_INTTI, /* intTI_type_node */
-+ RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */
- RS6000_BTI_float, /* float_type_node */
- RS6000_BTI_double, /* double_type_node */
-+ RS6000_BTI_long_double, /* long_double_type_node */
-+ RS6000_BTI_dfloat64, /* dfloat64_type_node */
-+ RS6000_BTI_dfloat128, /* dfloat128_type_node */
- RS6000_BTI_void, /* void_type_node */
- RS6000_BTI_MAX
- };
-@@ -2483,6 +2622,7 @@
- #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
- #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
- #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
-+#define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
- #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
- #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
- #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
-@@ -2492,6 +2632,7 @@
- #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
- #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
- #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
-+#define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
- #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
- #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
- #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
-@@ -2518,8 +2659,13 @@
- #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
- #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
- #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
-+#define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
-+#define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
- #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
- #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
-+#define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
-+#define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
-+#define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
- #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
-
- extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
-Index: gcc/config/rs6000/altivec.md
-===================================================================
---- a/src/gcc/config/rs6000/altivec.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/altivec.md (.../branches/gcc-4_8-branch)
-@@ -41,15 +41,12 @@
- UNSPEC_VMULOSB
- UNSPEC_VMULOUH
- UNSPEC_VMULOSH
-- UNSPEC_VPKUHUM
-- UNSPEC_VPKUWUM
- UNSPEC_VPKPX
-- UNSPEC_VPKSHSS
-- UNSPEC_VPKSWSS
-- UNSPEC_VPKUHUS
-- UNSPEC_VPKSHUS
-- UNSPEC_VPKUWUS
-- UNSPEC_VPKSWUS
-+ UNSPEC_VPACK_SIGN_SIGN_SAT
-+ UNSPEC_VPACK_SIGN_UNS_SAT
-+ UNSPEC_VPACK_UNS_UNS_SAT
-+ UNSPEC_VPACK_UNS_UNS_MOD
-+ UNSPEC_VPACK_UNS_UNS_MOD_DIRECT
- UNSPEC_VSLV4SI
- UNSPEC_VSLO
- UNSPEC_VSR
-@@ -71,12 +68,12 @@
- UNSPEC_VLOGEFP
- UNSPEC_VEXPTEFP
- UNSPEC_VLSDOI
-- UNSPEC_VUPKHSB
-+ UNSPEC_VUNPACK_HI_SIGN
-+ UNSPEC_VUNPACK_LO_SIGN
-+ UNSPEC_VUNPACK_HI_SIGN_DIRECT
-+ UNSPEC_VUNPACK_LO_SIGN_DIRECT
- UNSPEC_VUPKHPX
-- UNSPEC_VUPKHSH
-- UNSPEC_VUPKLSB
- UNSPEC_VUPKLPX
-- UNSPEC_VUPKLSH
- UNSPEC_DST
- UNSPEC_DSTT
- UNSPEC_DSTST
-@@ -134,6 +131,21 @@
- UNSPEC_VUPKLS_V4SF
- UNSPEC_VUPKHU_V4SF
- UNSPEC_VUPKLU_V4SF
-+ UNSPEC_VGBBD
-+ UNSPEC_VMRGH_DIRECT
-+ UNSPEC_VMRGL_DIRECT
-+ UNSPEC_VSPLT_DIRECT
-+ UNSPEC_VSUMSWS_DIRECT
-+ UNSPEC_VADDCUQ
-+ UNSPEC_VADDEUQM
-+ UNSPEC_VADDECUQ
-+ UNSPEC_VSUBCUQ
-+ UNSPEC_VSUBEUQM
-+ UNSPEC_VSUBECUQ
-+ UNSPEC_VBPERMQ
-+ UNSPEC_BCDADD
-+ UNSPEC_BCDSUB
-+ UNSPEC_BCD_OVERFLOW
- ])
-
- (define_c_enum "unspecv"
-@@ -146,6 +158,8 @@
-
- ;; Vec int modes
- (define_mode_iterator VI [V4SI V8HI V16QI])
-+;; Like VI, but add ISA 2.07 integer vector ops
-+(define_mode_iterator VI2 [V4SI V8HI V16QI V2DI])
- ;; Short vec in modes
- (define_mode_iterator VIshort [V8HI V16QI])
- ;; Vec float modes
-@@ -154,14 +168,25 @@
- (define_mode_iterator V [V4SI V8HI V16QI V4SF])
- ;; Vec modes for move/logical/permute ops, include vector types for move not
- ;; otherwise handled by altivec (v2df, v2di, ti)
--(define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI TI])
-+(define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI V1TI TI])
-
- ;; Like VM, except don't do TImode
--(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI])
-+(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI V1TI])
-
--(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
--(define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")])
-+(define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")])
-+(define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")])
-+(define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)")
-+ (V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)")
-+ (V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)")
-+ (V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)")
-+ (V1TI "VECTOR_UNIT_ALTIVEC_P (V1TImode)")])
-
-+;; Vector pack/unpack
-+(define_mode_iterator VP [V2DI V4SI V8HI])
-+(define_mode_attr VP_small [(V2DI "V4SI") (V4SI "V8HI") (V8HI "V16QI")])
-+(define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")])
-+(define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")])
-+
- ;; Vector move instructions.
- (define_insn "*altivec_mov<mode>"
- [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v")
-@@ -378,10 +403,10 @@
-
- ;; add
- (define_insn "add<mode>3"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (plus:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (plus:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vaddu<VI_char>m %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -398,7 +423,7 @@
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VADDCUW))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_P (V4SImode)"
- "vaddcuw %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -405,10 +430,10 @@
- (define_insn "altivec_vaddu<VI_char>s"
- [(set (match_operand:VI 0 "register_operand" "=v")
- (unspec:VI [(match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")]
-+ (match_operand:VI 2 "register_operand" "v")]
- UNSPEC_VADDU))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-+ "<VI_unit>"
- "vaddu<VI_char>s %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -418,16 +443,16 @@
- (match_operand:VI 2 "register_operand" "v")]
- UNSPEC_VADDS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
- "vadds<VI_char>s %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- ;; sub
- (define_insn "sub<mode>3"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (minus:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (minus:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vsubu<VI_char>m %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -444,7 +469,7 @@
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VSUBCUW))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_P (V4SImode)"
- "vsubcuw %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -454,7 +479,7 @@
- (match_operand:VI 2 "register_operand" "v")]
- UNSPEC_VSUBU))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
- "vsubu<VI_char>s %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -464,7 +489,7 @@
- (match_operand:VI 2 "register_operand" "v")]
- UNSPEC_VSUBS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
- "vsubs<VI_char>s %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -483,7 +508,7 @@
- (unspec:VI [(match_operand:VI 1 "register_operand" "v")
- (match_operand:VI 2 "register_operand" "v")]
- UNSPEC_VAVGS))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
- "vavgs<VI_char> %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -492,31 +517,31 @@
- (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
- (match_operand:V4SF 2 "register_operand" "v")]
- UNSPEC_VCMPBFP))]
-- "TARGET_ALTIVEC"
-+ "VECTOR_UNIT_ALTIVEC_P (V4SImode)"
- "vcmpbfp %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
- (define_insn "*altivec_eq<mode>"
-- [(set (match_operand:VI 0 "altivec_register_operand" "=v")
-- (eq:VI (match_operand:VI 1 "altivec_register_operand" "v")
-- (match_operand:VI 2 "altivec_register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "altivec_register_operand" "=v")
-+ (eq:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")
-+ (match_operand:VI2 2 "altivec_register_operand" "v")))]
-+ "<VI_unit>"
- "vcmpequ<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
- (define_insn "*altivec_gt<mode>"
-- [(set (match_operand:VI 0 "altivec_register_operand" "=v")
-- (gt:VI (match_operand:VI 1 "altivec_register_operand" "v")
-- (match_operand:VI 2 "altivec_register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "altivec_register_operand" "=v")
-+ (gt:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")
-+ (match_operand:VI2 2 "altivec_register_operand" "v")))]
-+ "<VI_unit>"
- "vcmpgts<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
- (define_insn "*altivec_gtu<mode>"
-- [(set (match_operand:VI 0 "altivec_register_operand" "=v")
-- (gtu:VI (match_operand:VI 1 "altivec_register_operand" "v")
-- (match_operand:VI 2 "altivec_register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "altivec_register_operand" "=v")
-+ (gtu:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")
-+ (match_operand:VI2 2 "altivec_register_operand" "v")))]
-+ "<VI_unit>"
- "vcmpgtu<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-@@ -642,7 +667,7 @@
- convert_move (small_swap, swap, 0);
-
- low_product = gen_reg_rtx (V4SImode);
-- emit_insn (gen_vec_widen_umult_odd_v8hi (low_product, one, two));
-+ emit_insn (gen_altivec_vmulouh (low_product, one, two));
-
- high_product = gen_reg_rtx (V4SImode);
- emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
-@@ -666,14 +691,23 @@
- rtx high = gen_reg_rtx (V4SImode);
- rtx low = gen_reg_rtx (V4SImode);
-
-- emit_insn (gen_vec_widen_smult_even_v8hi (even, operands[1], operands[2]));
-- emit_insn (gen_vec_widen_smult_odd_v8hi (odd, operands[1], operands[2]));
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghw_direct (high, even, odd));
-+ emit_insn (gen_altivec_vmrglw_direct (low, even, odd));
-+ emit_insn (gen_altivec_vpkuwum_direct (operands[0], high, low));
-+ }
-+ else
-+ {
-+ emit_insn (gen_altivec_vmulosh (even, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulesh (odd, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghw_direct (high, odd, even));
-+ emit_insn (gen_altivec_vmrglw_direct (low, odd, even));
-+ emit_insn (gen_altivec_vpkuwum_direct (operands[0], low, high));
-+ }
-
-- emit_insn (gen_altivec_vmrghw (high, even, odd));
-- emit_insn (gen_altivec_vmrglw (low, even, odd));
--
-- emit_insn (gen_altivec_vpkuwum (operands[0], high, low));
--
- DONE;
- }")
-
-@@ -744,18 +778,18 @@
- ;; max
-
- (define_insn "umax<mode>3"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (umax:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (umax:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vmaxu<VI_char> %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "smax<mode>3"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (smax:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (smax:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vmaxs<VI_char> %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -768,18 +802,18 @@
- [(set_attr "type" "veccmp")])
-
- (define_insn "umin<mode>3"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (umin:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (umin:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vminu<VI_char> %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "smin<mode>3"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (smin:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (smin:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vmins<VI_char> %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -823,9 +857,41 @@
- "vmladduhm %0,%1,%2,%3"
- [(set_attr "type" "veccomplex")])
-
--(define_insn "altivec_vmrghb"
-+(define_expand "altivec_vmrghb"
-+ [(use (match_operand:V16QI 0 "register_operand" ""))
-+ (use (match_operand:V16QI 1 "register_operand" ""))
-+ (use (match_operand:V16QI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25),
-+ GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27),
-+ GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29),
-+ GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31));
-+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]);
-+ }
-+ else
-+ {
-+ v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17),
-+ GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19),
-+ GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21),
-+ GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23));
-+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]);
-+ }
-+
-+ x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vmrghb_internal"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
-- (vec_select:V16QI
-+ (vec_select:V16QI
- (vec_concat:V32QI
- (match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v"))
-@@ -838,12 +904,54 @@
- (const_int 6) (const_int 22)
- (const_int 7) (const_int 23)])))]
- "TARGET_ALTIVEC"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrghb %0,%1,%2";
-+ else
-+ return "vmrglb %0,%2,%1";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "altivec_vmrghb_direct"
-+ [(set (match_operand:V16QI 0 "register_operand" "=v")
-+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
-+ (match_operand:V16QI 2 "register_operand" "v")]
-+ UNSPEC_VMRGH_DIRECT))]
-+ "TARGET_ALTIVEC"
- "vmrghb %0,%1,%2"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vmrghh"
-+(define_expand "altivec_vmrghh"
-+ [(use (match_operand:V8HI 0 "register_operand" ""))
-+ (use (match_operand:V8HI 1 "register_operand" ""))
-+ (use (match_operand:V8HI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13),
-+ GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15));
-+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]);
-+ }
-+ else
-+ {
-+ v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9),
-+ GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11));
-+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]);
-+ }
-+
-+ x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vmrghh_internal"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (vec_select:V8HI
-+ (vec_select:V8HI
- (vec_concat:V16HI
- (match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v"))
-@@ -852,10 +960,50 @@
- (const_int 2) (const_int 10)
- (const_int 3) (const_int 11)])))]
- "TARGET_ALTIVEC"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrghh %0,%1,%2";
-+ else
-+ return "vmrglh %0,%2,%1";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "altivec_vmrghh_direct"
-+ [(set (match_operand:V8HI 0 "register_operand" "=v")
-+ (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
-+ (match_operand:V8HI 2 "register_operand" "v")]
-+ UNSPEC_VMRGH_DIRECT))]
-+ "TARGET_ALTIVEC"
- "vmrghh %0,%1,%2"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vmrghw"
-+(define_expand "altivec_vmrghw"
-+ [(use (match_operand:V4SI 0 "register_operand" ""))
-+ (use (match_operand:V4SI 1 "register_operand" ""))
-+ (use (match_operand:V4SI 2 "register_operand" ""))]
-+ "VECTOR_MEM_ALTIVEC_P (V4SImode)"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7));
-+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]);
-+ }
-+ else
-+ {
-+ v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5));
-+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]);
-+ }
-+
-+ x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vmrghw_internal"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (vec_select:V4SI
- (vec_concat:V8SI
-@@ -864,6 +1012,20 @@
- (parallel [(const_int 0) (const_int 4)
- (const_int 1) (const_int 5)])))]
- "VECTOR_MEM_ALTIVEC_P (V4SImode)"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrghw %0,%1,%2";
-+ else
-+ return "vmrglw %0,%2,%1";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "altivec_vmrghw_direct"
-+ [(set (match_operand:V4SI 0 "register_operand" "=v")
-+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-+ (match_operand:V4SI 2 "register_operand" "v")]
-+ UNSPEC_VMRGH_DIRECT))]
-+ "TARGET_ALTIVEC"
- "vmrghw %0,%1,%2"
- [(set_attr "type" "vecperm")])
-
-@@ -876,10 +1038,47 @@
- (parallel [(const_int 0) (const_int 4)
- (const_int 1) (const_int 5)])))]
- "VECTOR_MEM_ALTIVEC_P (V4SFmode)"
-- "vmrghw %0,%1,%2"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrghw %0,%1,%2";
-+ else
-+ return "vmrglw %0,%2,%1";
-+}
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vmrglb"
-+(define_expand "altivec_vmrglb"
-+ [(use (match_operand:V16QI 0 "register_operand" ""))
-+ (use (match_operand:V16QI 1 "register_operand" ""))
-+ (use (match_operand:V16QI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17),
-+ GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19),
-+ GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21),
-+ GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23));
-+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]);
-+ }
-+ else
-+ {
-+ v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25),
-+ GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27),
-+ GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29),
-+ GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31));
-+ x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]);
-+ }
-+
-+ x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vmrglb_internal"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (vec_select:V16QI
- (vec_concat:V32QI
-@@ -894,10 +1093,52 @@
- (const_int 14) (const_int 30)
- (const_int 15) (const_int 31)])))]
- "TARGET_ALTIVEC"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrglb %0,%1,%2";
-+ else
-+ return "vmrghb %0,%2,%1";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "altivec_vmrglb_direct"
-+ [(set (match_operand:V16QI 0 "register_operand" "=v")
-+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
-+ (match_operand:V16QI 2 "register_operand" "v")]
-+ UNSPEC_VMRGL_DIRECT))]
-+ "TARGET_ALTIVEC"
- "vmrglb %0,%1,%2"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vmrglh"
-+(define_expand "altivec_vmrglh"
-+ [(use (match_operand:V8HI 0 "register_operand" ""))
-+ (use (match_operand:V8HI 1 "register_operand" ""))
-+ (use (match_operand:V8HI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9),
-+ GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11));
-+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]);
-+ }
-+ else
-+ {
-+ v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13),
-+ GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15));
-+ x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]);
-+ }
-+
-+ x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vmrglh_internal"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (vec_select:V8HI
- (vec_concat:V16HI
-@@ -908,10 +1149,50 @@
- (const_int 6) (const_int 14)
- (const_int 7) (const_int 15)])))]
- "TARGET_ALTIVEC"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrglh %0,%1,%2";
-+ else
-+ return "vmrghh %0,%2,%1";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "altivec_vmrglh_direct"
-+ [(set (match_operand:V8HI 0 "register_operand" "=v")
-+ (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
-+ (match_operand:V8HI 2 "register_operand" "v")]
-+ UNSPEC_VMRGL_DIRECT))]
-+ "TARGET_ALTIVEC"
- "vmrglh %0,%1,%2"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vmrglw"
-+(define_expand "altivec_vmrglw"
-+ [(use (match_operand:V4SI 0 "register_operand" ""))
-+ (use (match_operand:V4SI 1 "register_operand" ""))
-+ (use (match_operand:V4SI 2 "register_operand" ""))]
-+ "VECTOR_MEM_ALTIVEC_P (V4SImode)"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5));
-+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]);
-+ }
-+ else
-+ {
-+ v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7));
-+ x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]);
-+ }
-+
-+ x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vmrglw_internal"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (vec_select:V4SI
- (vec_concat:V8SI
-@@ -920,6 +1201,20 @@
- (parallel [(const_int 2) (const_int 6)
- (const_int 3) (const_int 7)])))]
- "VECTOR_MEM_ALTIVEC_P (V4SImode)"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrglw %0,%1,%2";
-+ else
-+ return "vmrghw %0,%2,%1";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "altivec_vmrglw_direct"
-+ [(set (match_operand:V4SI 0 "register_operand" "=v")
-+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-+ (match_operand:V4SI 2 "register_operand" "v")]
-+ UNSPEC_VMRGL_DIRECT))]
-+ "TARGET_ALTIVEC"
- "vmrglw %0,%1,%2"
- [(set_attr "type" "vecperm")])
-
-@@ -932,10 +1227,154 @@
- (parallel [(const_int 2) (const_int 6)
- (const_int 3) (const_int 7)])))]
- "VECTOR_MEM_ALTIVEC_P (V4SFmode)"
-- "vmrglw %0,%1,%2"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrglw %0,%1,%2";
-+ else
-+ return "vmrghw %0,%2,%1";
-+}
- [(set_attr "type" "vecperm")])
-
--(define_insn "vec_widen_umult_even_v16qi"
-+;; Power8 vector merge even/odd
-+(define_insn "p8_vmrgew"
-+ [(set (match_operand:V4SI 0 "register_operand" "=v")
-+ (vec_select:V4SI
-+ (vec_concat:V8SI
-+ (match_operand:V4SI 1 "register_operand" "v")
-+ (match_operand:V4SI 2 "register_operand" "v"))
-+ (parallel [(const_int 0) (const_int 4)
-+ (const_int 2) (const_int 6)])))]
-+ "TARGET_P8_VECTOR"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrgew %0,%1,%2";
-+ else
-+ return "vmrgow %0,%2,%1";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "p8_vmrgow"
-+ [(set (match_operand:V4SI 0 "register_operand" "=v")
-+ (vec_select:V4SI
-+ (vec_concat:V8SI
-+ (match_operand:V4SI 1 "register_operand" "v")
-+ (match_operand:V4SI 2 "register_operand" "v"))
-+ (parallel [(const_int 1) (const_int 5)
-+ (const_int 3) (const_int 7)])))]
-+ "TARGET_P8_VECTOR"
-+{
-+ if (BYTES_BIG_ENDIAN)
-+ return "vmrgow %0,%1,%2";
-+ else
-+ return "vmrgew %0,%2,%1";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_expand "vec_widen_umult_even_v16qi"
-+ [(use (match_operand:V8HI 0 "register_operand" ""))
-+ (use (match_operand:V16QI 1 "register_operand" ""))
-+ (use (match_operand:V16QI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2]));
-+ else
-+ emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2]));
-+ DONE;
-+})
-+
-+(define_expand "vec_widen_smult_even_v16qi"
-+ [(use (match_operand:V8HI 0 "register_operand" ""))
-+ (use (match_operand:V16QI 1 "register_operand" ""))
-+ (use (match_operand:V16QI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2]));
-+ else
-+ emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2]));
-+ DONE;
-+})
-+
-+(define_expand "vec_widen_umult_even_v8hi"
-+ [(use (match_operand:V4SI 0 "register_operand" ""))
-+ (use (match_operand:V8HI 1 "register_operand" ""))
-+ (use (match_operand:V8HI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2]));
-+ else
-+ emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2]));
-+ DONE;
-+})
-+
-+(define_expand "vec_widen_smult_even_v8hi"
-+ [(use (match_operand:V4SI 0 "register_operand" ""))
-+ (use (match_operand:V8HI 1 "register_operand" ""))
-+ (use (match_operand:V8HI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2]));
-+ else
-+ emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2]));
-+ DONE;
-+})
-+
-+(define_expand "vec_widen_umult_odd_v16qi"
-+ [(use (match_operand:V8HI 0 "register_operand" ""))
-+ (use (match_operand:V16QI 1 "register_operand" ""))
-+ (use (match_operand:V16QI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2]));
-+ else
-+ emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2]));
-+ DONE;
-+})
-+
-+(define_expand "vec_widen_smult_odd_v16qi"
-+ [(use (match_operand:V8HI 0 "register_operand" ""))
-+ (use (match_operand:V16QI 1 "register_operand" ""))
-+ (use (match_operand:V16QI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2]));
-+ else
-+ emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2]));
-+ DONE;
-+})
-+
-+(define_expand "vec_widen_umult_odd_v8hi"
-+ [(use (match_operand:V4SI 0 "register_operand" ""))
-+ (use (match_operand:V8HI 1 "register_operand" ""))
-+ (use (match_operand:V8HI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2]));
-+ else
-+ emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2]));
-+ DONE;
-+})
-+
-+(define_expand "vec_widen_smult_odd_v8hi"
-+ [(use (match_operand:V4SI 0 "register_operand" ""))
-+ (use (match_operand:V8HI 1 "register_operand" ""))
-+ (use (match_operand:V8HI 2 "register_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2]));
-+ else
-+ emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2]));
-+ DONE;
-+})
-+
-+(define_insn "altivec_vmuleub"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
-@@ -944,43 +1383,25 @@
- "vmuleub %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
--(define_insn "vec_widen_smult_even_v16qi"
-+(define_insn "altivec_vmuloub"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
-- UNSPEC_VMULESB))]
-+ UNSPEC_VMULOUB))]
- "TARGET_ALTIVEC"
-- "vmulesb %0,%1,%2"
-+ "vmuloub %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
--(define_insn "vec_widen_umult_even_v8hi"
-- [(set (match_operand:V4SI 0 "register_operand" "=v")
-- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
-- (match_operand:V8HI 2 "register_operand" "v")]
-- UNSPEC_VMULEUH))]
-- "TARGET_ALTIVEC"
-- "vmuleuh %0,%1,%2"
-- [(set_attr "type" "veccomplex")])
--
--(define_insn "vec_widen_smult_even_v8hi"
-- [(set (match_operand:V4SI 0 "register_operand" "=v")
-- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
-- (match_operand:V8HI 2 "register_operand" "v")]
-- UNSPEC_VMULESH))]
-- "TARGET_ALTIVEC"
-- "vmulesh %0,%1,%2"
-- [(set_attr "type" "veccomplex")])
--
--(define_insn "vec_widen_umult_odd_v16qi"
-+(define_insn "altivec_vmulesb"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
-- UNSPEC_VMULOUB))]
-+ UNSPEC_VMULESB))]
- "TARGET_ALTIVEC"
-- "vmuloub %0,%1,%2"
-+ "vmulesb %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
--(define_insn "vec_widen_smult_odd_v16qi"
-+(define_insn "altivec_vmulosb"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
-@@ -989,19 +1410,37 @@
- "vmulosb %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
--(define_insn "vec_widen_umult_odd_v8hi"
-+(define_insn "altivec_vmuleuh"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")]
-+ UNSPEC_VMULEUH))]
-+ "TARGET_ALTIVEC"
-+ "vmuleuh %0,%1,%2"
-+ [(set_attr "type" "veccomplex")])
-+
-+(define_insn "altivec_vmulouh"
-+ [(set (match_operand:V4SI 0 "register_operand" "=v")
-+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
-+ (match_operand:V8HI 2 "register_operand" "v")]
- UNSPEC_VMULOUH))]
- "TARGET_ALTIVEC"
- "vmulouh %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
--(define_insn "vec_widen_smult_odd_v8hi"
-+(define_insn "altivec_vmulesh"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")]
-+ UNSPEC_VMULESH))]
-+ "TARGET_ALTIVEC"
-+ "vmulesh %0,%1,%2"
-+ [(set_attr "type" "veccomplex")])
-+
-+(define_insn "altivec_vmulosh"
-+ [(set (match_operand:V4SI 0 "register_operand" "=v")
-+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
-+ (match_operand:V8HI 2 "register_operand" "v")]
- UNSPEC_VMULOSH))]
- "TARGET_ALTIVEC"
- "vmulosh %0,%1,%2"
-@@ -1008,74 +1447,7 @@
- [(set_attr "type" "veccomplex")])
-
-
--;; logical ops. Have the logical ops follow the memory ops in
--;; terms of whether to prefer VSX or Altivec
--
--(define_insn "*altivec_and<mode>3"
-- [(set (match_operand:VM 0 "register_operand" "=v")
-- (and:VM (match_operand:VM 1 "register_operand" "v")
-- (match_operand:VM 2 "register_operand" "v")))]
-- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
-- "vand %0,%1,%2"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*altivec_ior<mode>3"
-- [(set (match_operand:VM 0 "register_operand" "=v")
-- (ior:VM (match_operand:VM 1 "register_operand" "v")
-- (match_operand:VM 2 "register_operand" "v")))]
-- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
-- "vor %0,%1,%2"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*altivec_xor<mode>3"
-- [(set (match_operand:VM 0 "register_operand" "=v")
-- (xor:VM (match_operand:VM 1 "register_operand" "v")
-- (match_operand:VM 2 "register_operand" "v")))]
-- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
-- "vxor %0,%1,%2"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*altivec_one_cmpl<mode>2"
-- [(set (match_operand:VM 0 "register_operand" "=v")
-- (not:VM (match_operand:VM 1 "register_operand" "v")))]
-- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
-- "vnor %0,%1,%1"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*altivec_nor<mode>3"
-- [(set (match_operand:VM 0 "register_operand" "=v")
-- (not:VM (ior:VM (match_operand:VM 1 "register_operand" "v")
-- (match_operand:VM 2 "register_operand" "v"))))]
-- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
-- "vnor %0,%1,%2"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "*altivec_andc<mode>3"
-- [(set (match_operand:VM 0 "register_operand" "=v")
-- (and:VM (not:VM (match_operand:VM 2 "register_operand" "v"))
-- (match_operand:VM 1 "register_operand" "v")))]
-- "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
-- "vandc %0,%1,%2"
-- [(set_attr "type" "vecsimple")])
--
--(define_insn "altivec_vpkuhum"
-- [(set (match_operand:V16QI 0 "register_operand" "=v")
-- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-- (match_operand:V8HI 2 "register_operand" "v")]
-- UNSPEC_VPKUHUM))]
-- "TARGET_ALTIVEC"
-- "vpkuhum %0,%1,%2"
-- [(set_attr "type" "vecperm")])
--
--(define_insn "altivec_vpkuwum"
-- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-- (match_operand:V4SI 2 "register_operand" "v")]
-- UNSPEC_VPKUWUM))]
-- "TARGET_ALTIVEC"
-- "vpkuwum %0,%1,%2"
-- [(set_attr "type" "vecperm")])
--
-+;; Vector pack/unpack
- (define_insn "altivec_vpkpx"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-@@ -1082,74 +1454,95 @@
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VPKPX))]
- "TARGET_ALTIVEC"
-- "vpkpx %0,%1,%2"
-+ "*
-+ {
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return \"vpkpx %0,%1,%2\";
-+ else
-+ return \"vpkpx %0,%2,%1\";
-+ }"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vpkshss"
-- [(set (match_operand:V16QI 0 "register_operand" "=v")
-- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-- (match_operand:V8HI 2 "register_operand" "v")]
-- UNSPEC_VPKSHSS))
-- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-- "vpkshss %0,%1,%2"
-+(define_insn "altivec_vpks<VI_char>ss"
-+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")
-+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")
-+ (match_operand:VP 2 "register_operand" "v")]
-+ UNSPEC_VPACK_SIGN_SIGN_SAT))]
-+ "<VI_unit>"
-+ "*
-+ {
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return \"vpks<VI_char>ss %0,%1,%2\";
-+ else
-+ return \"vpks<VI_char>ss %0,%2,%1\";
-+ }"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vpkswss"
-- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-- (match_operand:V4SI 2 "register_operand" "v")]
-- UNSPEC_VPKSWSS))
-- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-- "vpkswss %0,%1,%2"
-+(define_insn "altivec_vpks<VI_char>us"
-+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")
-+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")
-+ (match_operand:VP 2 "register_operand" "v")]
-+ UNSPEC_VPACK_SIGN_UNS_SAT))]
-+ "<VI_unit>"
-+ "*
-+ {
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return \"vpks<VI_char>us %0,%1,%2\";
-+ else
-+ return \"vpks<VI_char>us %0,%2,%1\";
-+ }"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vpkuhus"
-- [(set (match_operand:V16QI 0 "register_operand" "=v")
-- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-- (match_operand:V8HI 2 "register_operand" "v")]
-- UNSPEC_VPKUHUS))
-- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-- "vpkuhus %0,%1,%2"
-+(define_insn "altivec_vpku<VI_char>us"
-+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")
-+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")
-+ (match_operand:VP 2 "register_operand" "v")]
-+ UNSPEC_VPACK_UNS_UNS_SAT))]
-+ "<VI_unit>"
-+ "*
-+ {
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return \"vpku<VI_char>us %0,%1,%2\";
-+ else
-+ return \"vpku<VI_char>us %0,%2,%1\";
-+ }"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vpkshus"
-- [(set (match_operand:V16QI 0 "register_operand" "=v")
-- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-- (match_operand:V8HI 2 "register_operand" "v")]
-- UNSPEC_VPKSHUS))
-- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-- "vpkshus %0,%1,%2"
-+(define_insn "altivec_vpku<VI_char>um"
-+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")
-+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")
-+ (match_operand:VP 2 "register_operand" "v")]
-+ UNSPEC_VPACK_UNS_UNS_MOD))]
-+ "<VI_unit>"
-+ "*
-+ {
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return \"vpku<VI_char>um %0,%1,%2\";
-+ else
-+ return \"vpku<VI_char>um %0,%2,%1\";
-+ }"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vpkuwus"
-- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-- (match_operand:V4SI 2 "register_operand" "v")]
-- UNSPEC_VPKUWUS))
-- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-- "vpkuwus %0,%1,%2"
-+(define_insn "altivec_vpku<VI_char>um_direct"
-+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")
-+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")
-+ (match_operand:VP 2 "register_operand" "v")]
-+ UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))]
-+ "<VI_unit>"
-+ "*
-+ {
-+ if (BYTES_BIG_ENDIAN)
-+ return \"vpku<VI_char>um %0,%1,%2\";
-+ else
-+ return \"vpku<VI_char>um %0,%2,%1\";
-+ }"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vpkswus"
-- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-- (match_operand:V4SI 2 "register_operand" "v")]
-- UNSPEC_VPKSWUS))
-- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-- "TARGET_ALTIVEC"
-- "vpkswus %0,%1,%2"
-- [(set_attr "type" "vecperm")])
--
- (define_insn "*altivec_vrl<VI_char>"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (rotate:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vrl<VI_char> %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -1172,26 +1565,26 @@
- [(set_attr "type" "vecperm")])
-
- (define_insn "*altivec_vsl<VI_char>"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (ashift:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (ashift:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vsl<VI_char> %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "*altivec_vsr<VI_char>"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (lshiftrt:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vsr<VI_char> %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "*altivec_vsra<VI_char>"
-- [(set (match_operand:VI 0 "register_operand" "=v")
-- (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v")))]
-- "TARGET_ALTIVEC"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (ashiftrt:VI2 (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v")))]
-+ "<VI_unit>"
- "vsra<VI_char> %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
-@@ -1233,15 +1626,29 @@
- "vsum4s<VI_char>s %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-+;; FIXME: For the following two patterns, the scratch should only be
-+;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should
-+;; be emitted separately.
- (define_insn "altivec_vsum2sws"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VSUM2SWS))
-- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-+ (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
-+ (clobber (match_scratch:V4SI 3 "=v"))]
- "TARGET_ALTIVEC"
-- "vsum2sws %0,%1,%2"
-- [(set_attr "type" "veccomplex")])
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return "vsum2sws %0,%1,%2";
-+ else
-+ return "vsldoi %3,%2,%2,12\n\tvsum2sws %3,%1,%3\n\tvsldoi %0,%3,%3,4";
-+}
-+ [(set_attr "type" "veccomplex")
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "VECTOR_ELT_ORDER_BIG")
-+ (const_string "4")
-+ (const_string "12")))])
-
- (define_insn "altivec_vsumsws"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
-@@ -1248,12 +1655,54 @@
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VSUMSWS))
-+ (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
-+ (clobber (match_scratch:V4SI 3 "=v"))]
-+ "TARGET_ALTIVEC"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return "vsumsws %0,%1,%2";
-+ else
-+ return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvsldoi %0,%3,%3,12";
-+}
-+ [(set_attr "type" "veccomplex")
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "(VECTOR_ELT_ORDER_BIG)")
-+ (const_string "4")
-+ (const_string "12")))])
-+
-+(define_insn "altivec_vsumsws_direct"
-+ [(set (match_operand:V4SI 0 "register_operand" "=v")
-+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-+ (match_operand:V4SI 2 "register_operand" "v")]
-+ UNSPEC_VSUMSWS_DIRECT))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vsumsws %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
--(define_insn "altivec_vspltb"
-+(define_expand "altivec_vspltb"
-+ [(use (match_operand:V16QI 0 "register_operand" ""))
-+ (use (match_operand:V16QI 1 "register_operand" ""))
-+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. We have to reflect
-+ the actual selected index for the splat in the RTL. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ operands[2] = GEN_INT (15 - INTVAL (operands[2]));
-+
-+ v = gen_rtvec (1, operands[2]);
-+ x = gen_rtx_VEC_SELECT (QImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));
-+ x = gen_rtx_VEC_DUPLICATE (V16QImode, x);
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vspltb_internal"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (vec_duplicate:V16QI
- (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
-@@ -1260,10 +1709,48 @@
- (parallel
- [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
- "TARGET_ALTIVEC"
-+{
-+ /* For true LE, this adjusts the selected index. For LE with
-+ -maltivec=be, this reverses what was done in the define_expand
-+ because the instruction already has big-endian bias. */
-+ if (!BYTES_BIG_ENDIAN)
-+ operands[2] = GEN_INT (15 - INTVAL (operands[2]));
-+
-+ return "vspltb %0,%1,%2";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "altivec_vspltb_direct"
-+ [(set (match_operand:V16QI 0 "register_operand" "=v")
-+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
-+ (match_operand:QI 2 "u5bit_cint_operand" "i")]
-+ UNSPEC_VSPLT_DIRECT))]
-+ "TARGET_ALTIVEC"
- "vspltb %0,%1,%2"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vsplth"
-+(define_expand "altivec_vsplth"
-+ [(use (match_operand:V8HI 0 "register_operand" ""))
-+ (use (match_operand:V8HI 1 "register_operand" ""))
-+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. We have to reflect
-+ the actual selected index for the splat in the RTL. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ operands[2] = GEN_INT (7 - INTVAL (operands[2]));
-+
-+ v = gen_rtvec (1, operands[2]);
-+ x = gen_rtx_VEC_SELECT (HImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));
-+ x = gen_rtx_VEC_DUPLICATE (V8HImode, x);
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vsplth_internal"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (vec_duplicate:V8HI
- (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
-@@ -1270,10 +1757,48 @@
- (parallel
- [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
- "TARGET_ALTIVEC"
-+{
-+ /* For true LE, this adjusts the selected index. For LE with
-+ -maltivec=be, this reverses what was done in the define_expand
-+ because the instruction already has big-endian bias. */
-+ if (!BYTES_BIG_ENDIAN)
-+ operands[2] = GEN_INT (7 - INTVAL (operands[2]));
-+
-+ return "vsplth %0,%1,%2";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "altivec_vsplth_direct"
-+ [(set (match_operand:V8HI 0 "register_operand" "=v")
-+ (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
-+ (match_operand:QI 2 "u5bit_cint_operand" "i")]
-+ UNSPEC_VSPLT_DIRECT))]
-+ "TARGET_ALTIVEC"
- "vsplth %0,%1,%2"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vspltw"
-+(define_expand "altivec_vspltw"
-+ [(use (match_operand:V4SI 0 "register_operand" ""))
-+ (use (match_operand:V4SI 1 "register_operand" ""))
-+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. We have to reflect
-+ the actual selected index for the splat in the RTL. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));
-+
-+ v = gen_rtvec (1, operands[2]);
-+ x = gen_rtx_VEC_SELECT (SImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));
-+ x = gen_rtx_VEC_DUPLICATE (V4SImode, x);
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vspltw_internal"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (vec_duplicate:V4SI
- (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
-@@ -1280,10 +1805,48 @@
- (parallel
- [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
- "TARGET_ALTIVEC"
-+{
-+ /* For true LE, this adjusts the selected index. For LE with
-+ -maltivec=be, this reverses what was done in the define_expand
-+ because the instruction already has big-endian bias. */
-+ if (!BYTES_BIG_ENDIAN)
-+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));
-+
-+ return "vspltw %0,%1,%2";
-+}
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "altivec_vspltw_direct"
-+ [(set (match_operand:V4SI 0 "register_operand" "=v")
-+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-+ (match_operand:QI 2 "u5bit_cint_operand" "i")]
-+ UNSPEC_VSPLT_DIRECT))]
-+ "TARGET_ALTIVEC"
- "vspltw %0,%1,%2"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vspltsf"
-+(define_expand "altivec_vspltsf"
-+ [(use (match_operand:V4SF 0 "register_operand" ""))
-+ (use (match_operand:V4SF 1 "register_operand" ""))
-+ (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
-+ "TARGET_ALTIVEC"
-+{
-+ rtvec v;
-+ rtx x;
-+
-+ /* Special handling for LE with -maltivec=be. We have to reflect
-+ the actual selected index for the splat in the RTL. */
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));
-+
-+ v = gen_rtvec (1, operands[2]);
-+ x = gen_rtx_VEC_SELECT (SFmode, operands[1], gen_rtx_PARALLEL (VOIDmode, v));
-+ x = gen_rtx_VEC_DUPLICATE (V4SFmode, x);
-+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
-+ DONE;
-+})
-+
-+(define_insn "*altivec_vspltsf_internal"
- [(set (match_operand:V4SF 0 "register_operand" "=v")
- (vec_duplicate:V4SF
- (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
-@@ -1290,7 +1853,15 @@
- (parallel
- [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
- "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
-- "vspltw %0,%1,%2"
-+{
-+ /* For true LE, this adjusts the selected index. For LE with
-+ -maltivec=be, this reverses what was done in the define_expand
-+ because the instruction already has big-endian bias. */
-+ if (!BYTES_BIG_ENDIAN)
-+ operands[2] = GEN_INT (3 - INTVAL (operands[2]));
-+
-+ return "vspltw %0,%1,%2";
-+}
- [(set_attr "type" "vecperm")])
-
- (define_insn "altivec_vspltis<VI_char>"
-@@ -1308,7 +1879,7 @@
- "vrfiz %0,%1"
- [(set_attr "type" "vecfloat")])
-
--(define_insn "altivec_vperm_<mode>"
-+(define_expand "altivec_vperm_<mode>"
- [(set (match_operand:VM 0 "register_operand" "=v")
- (unspec:VM [(match_operand:VM 1 "register_operand" "v")
- (match_operand:VM 2 "register_operand" "v")
-@@ -1315,10 +1886,25 @@
- (match_operand:V16QI 3 "register_operand" "v")]
- UNSPEC_VPERM))]
- "TARGET_ALTIVEC"
-+{
-+ if (!VECTOR_ELT_ORDER_BIG)
-+ {
-+ altivec_expand_vec_perm_le (operands);
-+ DONE;
-+ }
-+})
-+
-+(define_insn "*altivec_vperm_<mode>_internal"
-+ [(set (match_operand:VM 0 "register_operand" "=v")
-+ (unspec:VM [(match_operand:VM 1 "register_operand" "v")
-+ (match_operand:VM 2 "register_operand" "v")
-+ (match_operand:V16QI 3 "register_operand" "v")]
-+ UNSPEC_VPERM))]
-+ "TARGET_ALTIVEC"
- "vperm %0,%1,%2,%3"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vperm_<mode>_uns"
-+(define_expand "altivec_vperm_<mode>_uns"
- [(set (match_operand:VM 0 "register_operand" "=v")
- (unspec:VM [(match_operand:VM 1 "register_operand" "v")
- (match_operand:VM 2 "register_operand" "v")
-@@ -1325,6 +1911,21 @@
- (match_operand:V16QI 3 "register_operand" "v")]
- UNSPEC_VPERM_UNS))]
- "TARGET_ALTIVEC"
-+{
-+ if (!VECTOR_ELT_ORDER_BIG)
-+ {
-+ altivec_expand_vec_perm_le (operands);
-+ DONE;
-+ }
-+})
-+
-+(define_insn "*altivec_vperm_<mode>_uns_internal"
-+ [(set (match_operand:VM 0 "register_operand" "=v")
-+ (unspec:VM [(match_operand:VM 1 "register_operand" "v")
-+ (match_operand:VM 2 "register_operand" "v")
-+ (match_operand:V16QI 3 "register_operand" "v")]
-+ UNSPEC_VPERM_UNS))]
-+ "TARGET_ALTIVEC"
- "vperm %0,%1,%2,%3"
- [(set_attr "type" "vecperm")])
-
-@@ -1335,7 +1936,12 @@
- (match_operand:V16QI 3 "register_operand" "")]
- UNSPEC_VPERM))]
- "TARGET_ALTIVEC"
-- "")
-+{
-+ if (!BYTES_BIG_ENDIAN) {
-+ altivec_expand_vec_perm_le (operands);
-+ DONE;
-+ }
-+})
-
- (define_expand "vec_perm_constv16qi"
- [(match_operand:V16QI 0 "register_operand" "")
-@@ -1476,52 +2082,72 @@
- "vsldoi %0,%1,%2,%3"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vupkhsb"
-- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
-- UNSPEC_VUPKHSB))]
-- "TARGET_ALTIVEC"
-- "vupkhsb %0,%1"
-+(define_insn "altivec_vupkhs<VU_char>"
-+ [(set (match_operand:VP 0 "register_operand" "=v")
-+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]
-+ UNSPEC_VUNPACK_HI_SIGN))]
-+ "<VI_unit>"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return "vupkhs<VU_char> %0,%1";
-+ else
-+ return "vupkls<VU_char> %0,%1";
-+}
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vupkhpx"
-- [(set (match_operand:V4SI 0 "register_operand" "=v")
-- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
-- UNSPEC_VUPKHPX))]
-- "TARGET_ALTIVEC"
-- "vupkhpx %0,%1"
-+(define_insn "*altivec_vupkhs<VU_char>_direct"
-+ [(set (match_operand:VP 0 "register_operand" "=v")
-+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]
-+ UNSPEC_VUNPACK_HI_SIGN_DIRECT))]
-+ "<VI_unit>"
-+ "vupkhs<VU_char> %0,%1"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vupkhsh"
-- [(set (match_operand:V4SI 0 "register_operand" "=v")
-- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
-- UNSPEC_VUPKHSH))]
-- "TARGET_ALTIVEC"
-- "vupkhsh %0,%1"
-+(define_insn "altivec_vupkls<VU_char>"
-+ [(set (match_operand:VP 0 "register_operand" "=v")
-+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]
-+ UNSPEC_VUNPACK_LO_SIGN))]
-+ "<VI_unit>"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return "vupkls<VU_char> %0,%1";
-+ else
-+ return "vupkhs<VU_char> %0,%1";
-+}
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vupklsb"
-- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
-- UNSPEC_VUPKLSB))]
-- "TARGET_ALTIVEC"
-- "vupklsb %0,%1"
-+(define_insn "*altivec_vupkls<VU_char>_direct"
-+ [(set (match_operand:VP 0 "register_operand" "=v")
-+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]
-+ UNSPEC_VUNPACK_LO_SIGN_DIRECT))]
-+ "<VI_unit>"
-+ "vupkls<VU_char> %0,%1"
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vupklpx"
-+(define_insn "altivec_vupkhpx"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
-- UNSPEC_VUPKLPX))]
-+ UNSPEC_VUPKHPX))]
- "TARGET_ALTIVEC"
-- "vupklpx %0,%1"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return "vupkhpx %0,%1";
-+ else
-+ return "vupklpx %0,%1";
-+}
- [(set_attr "type" "vecperm")])
-
--(define_insn "altivec_vupklsh"
-+(define_insn "altivec_vupklpx"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
-- UNSPEC_VUPKLSH))]
-+ UNSPEC_VUPKLPX))]
- "TARGET_ALTIVEC"
-- "vupklsh %0,%1"
-+{
-+ if (VECTOR_ELT_ORDER_BIG)
-+ return "vupklpx %0,%1";
-+ else
-+ return "vupkhpx %0,%1";
-+}
- [(set_attr "type" "vecperm")])
-
- ;; Compare vectors producing a vector result and a predicate, setting CR6 to
-@@ -1528,37 +2154,37 @@
- ;; indicate a combined status
- (define_insn "*altivec_vcmpequ<VI_char>_p"
- [(set (reg:CC 74)
-- (unspec:CC [(eq:CC (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v"))]
-+ (unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v"))]
- UNSPEC_PREDICATE))
-- (set (match_operand:VI 0 "register_operand" "=v")
-- (eq:VI (match_dup 1)
-- (match_dup 2)))]
-- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
-+ (set (match_operand:VI2 0 "register_operand" "=v")
-+ (eq:VI2 (match_dup 1)
-+ (match_dup 2)))]
-+ "<VI_unit>"
- "vcmpequ<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
- (define_insn "*altivec_vcmpgts<VI_char>_p"
- [(set (reg:CC 74)
-- (unspec:CC [(gt:CC (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v"))]
-+ (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v"))]
- UNSPEC_PREDICATE))
-- (set (match_operand:VI 0 "register_operand" "=v")
-- (gt:VI (match_dup 1)
-- (match_dup 2)))]
-- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
-+ (set (match_operand:VI2 0 "register_operand" "=v")
-+ (gt:VI2 (match_dup 1)
-+ (match_dup 2)))]
-+ "<VI_unit>"
- "vcmpgts<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
- (define_insn "*altivec_vcmpgtu<VI_char>_p"
- [(set (reg:CC 74)
-- (unspec:CC [(gtu:CC (match_operand:VI 1 "register_operand" "v")
-- (match_operand:VI 2 "register_operand" "v"))]
-+ (unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v")
-+ (match_operand:VI2 2 "register_operand" "v"))]
- UNSPEC_PREDICATE))
-- (set (match_operand:VI 0 "register_operand" "=v")
-- (gtu:VI (match_dup 1)
-- (match_dup 2)))]
-- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
-+ (set (match_operand:VI2 0 "register_operand" "=v")
-+ (gtu:VI2 (match_dup 1)
-+ (match_dup 2)))]
-+ "<VI_unit>"
- "vcmpgtu<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-@@ -1710,12 +2336,26 @@
- ;; Parallel some of the LVE* and STV*'s with unspecs because some have
- ;; identical rtl but different instructions-- and gcc gets confused.
-
--(define_insn "altivec_lve<VI_char>x"
-+(define_expand "altivec_lve<VI_char>x"
- [(parallel
- [(set (match_operand:VI 0 "register_operand" "=v")
- (match_operand:VI 1 "memory_operand" "Z"))
- (unspec [(const_int 0)] UNSPEC_LVE)])]
- "TARGET_ALTIVEC"
-+{
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_LVE);
-+ DONE;
-+ }
-+})
-+
-+(define_insn "*altivec_lve<VI_char>x_internal"
-+ [(parallel
-+ [(set (match_operand:VI 0 "register_operand" "=v")
-+ (match_operand:VI 1 "memory_operand" "Z"))
-+ (unspec [(const_int 0)] UNSPEC_LVE)])]
-+ "TARGET_ALTIVEC"
- "lve<VI_char>x %0,%y1"
- [(set_attr "type" "vecload")])
-
-@@ -1728,46 +2368,114 @@
- "lvewx %0,%y1"
- [(set_attr "type" "vecload")])
-
--(define_insn "altivec_lvxl"
-+(define_expand "altivec_lvxl_<mode>"
- [(parallel
-- [(set (match_operand:V4SI 0 "register_operand" "=v")
-- (match_operand:V4SI 1 "memory_operand" "Z"))
-+ [(set (match_operand:VM2 0 "register_operand" "=v")
-+ (match_operand:VM2 1 "memory_operand" "Z"))
- (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
- "TARGET_ALTIVEC"
-- "lvxl %0,%y1"
-+{
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_SET_VSCR);
-+ DONE;
-+ }
-+})
-+
-+(define_insn "*altivec_lvxl_<mode>_internal"
-+ [(parallel
-+ [(set (match_operand:VM2 0 "register_operand" "=v")
-+ (match_operand:VM2 1 "memory_operand" "Z"))
-+ (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
-+ "TARGET_ALTIVEC"
-+ "lvx %0,%y1"
- [(set_attr "type" "vecload")])
-
--(define_insn "altivec_lvx_<mode>"
-+(define_expand "altivec_lvx_<mode>"
- [(parallel
- [(set (match_operand:VM2 0 "register_operand" "=v")
- (match_operand:VM2 1 "memory_operand" "Z"))
- (unspec [(const_int 0)] UNSPEC_LVX)])]
- "TARGET_ALTIVEC"
-+{
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_LVX);
-+ DONE;
-+ }
-+})
-+
-+(define_insn "*altivec_lvx_<mode>_internal"
-+ [(parallel
-+ [(set (match_operand:VM2 0 "register_operand" "=v")
-+ (match_operand:VM2 1 "memory_operand" "Z"))
-+ (unspec [(const_int 0)] UNSPEC_LVX)])]
-+ "TARGET_ALTIVEC"
- "lvx %0,%y1"
- [(set_attr "type" "vecload")])
-
--(define_insn "altivec_stvx_<mode>"
-+(define_expand "altivec_stvx_<mode>"
- [(parallel
- [(set (match_operand:VM2 0 "memory_operand" "=Z")
- (match_operand:VM2 1 "register_operand" "v"))
- (unspec [(const_int 0)] UNSPEC_STVX)])]
- "TARGET_ALTIVEC"
-+{
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ altivec_expand_stvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVX);
-+ DONE;
-+ }
-+})
-+
-+(define_insn "*altivec_stvx_<mode>_internal"
-+ [(parallel
-+ [(set (match_operand:VM2 0 "memory_operand" "=Z")
-+ (match_operand:VM2 1 "register_operand" "v"))
-+ (unspec [(const_int 0)] UNSPEC_STVX)])]
-+ "TARGET_ALTIVEC"
- "stvx %1,%y0"
- [(set_attr "type" "vecstore")])
-
--(define_insn "altivec_stvxl"
-+(define_expand "altivec_stvxl_<mode>"
- [(parallel
-- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
-- (match_operand:V4SI 1 "register_operand" "v"))
-+ [(set (match_operand:VM2 0 "memory_operand" "=Z")
-+ (match_operand:VM2 1 "register_operand" "v"))
- (unspec [(const_int 0)] UNSPEC_STVXL)])]
- "TARGET_ALTIVEC"
-+{
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ altivec_expand_stvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVXL);
-+ DONE;
-+ }
-+})
-+
-+(define_insn "*altivec_stvxl_<mode>_internal"
-+ [(parallel
-+ [(set (match_operand:VM2 0 "memory_operand" "=Z")
-+ (match_operand:VM2 1 "register_operand" "v"))
-+ (unspec [(const_int 0)] UNSPEC_STVXL)])]
-+ "TARGET_ALTIVEC"
- "stvxl %1,%y0"
- [(set_attr "type" "vecstore")])
-
--(define_insn "altivec_stve<VI_char>x"
-+(define_expand "altivec_stve<VI_char>x"
- [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")
- (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]
- "TARGET_ALTIVEC"
-+{
-+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-+ {
-+ altivec_expand_stvex_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVE);
-+ DONE;
-+ }
-+})
-+
-+(define_insn "*altivec_stve<VI_char>x_internal"
-+ [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")
-+ (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]
-+ "TARGET_ALTIVEC"
- "stve<VI_char>x %1,%y0"
- [(set_attr "type" "vecstore")])
-
-@@ -1779,20 +2487,28 @@
- [(set_attr "type" "vecstore")])
-
- ;; Generate
--;; vspltis? SCRATCH0,0
-+;; xxlxor/vxor SCRATCH0,SCRATCH0,SCRATCH0
- ;; vsubu?m SCRATCH2,SCRATCH1,%1
- ;; vmaxs? %0,%1,SCRATCH2"
- (define_expand "abs<mode>2"
-- [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
-- (set (match_dup 3)
-- (minus:VI (match_dup 2)
-- (match_operand:VI 1 "register_operand" "v")))
-- (set (match_operand:VI 0 "register_operand" "=v")
-- (smax:VI (match_dup 1) (match_dup 3)))]
-- "TARGET_ALTIVEC"
-+ [(set (match_dup 2) (match_dup 3))
-+ (set (match_dup 4)
-+ (minus:VI2 (match_dup 2)
-+ (match_operand:VI2 1 "register_operand" "v")))
-+ (set (match_operand:VI2 0 "register_operand" "=v")
-+ (smax:VI2 (match_dup 1) (match_dup 4)))]
-+ "<VI_unit>"
- {
-- operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
-- operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
-+ int i, n_elt = GET_MODE_NUNITS (<MODE>mode);
-+ rtvec v = rtvec_alloc (n_elt);
-+
-+ /* Create an all 0 constant. */
-+ for (i = 0; i < n_elt; ++i)
-+ RTVEC_ELT (v, i) = const0_rtx;
-+
-+ operands[2] = gen_reg_rtx (<MODE>mode);
-+ operands[3] = gen_rtx_CONST_VECTOR (<MODE>mode, v);
-+ operands[4] = gen_reg_rtx (<MODE>mode);
- })
-
- ;; Generate
-@@ -1844,7 +2560,7 @@
-
- emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
- emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
-- emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));
-+ emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));
- DONE;
- })
-
-@@ -1860,7 +2576,7 @@
-
- emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
- emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
-- emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));
-+ emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));
- DONE;
- })
-
-@@ -1950,50 +2666,20 @@
- DONE;
- }")
-
--(define_expand "vec_unpacks_hi_v16qi"
-- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
-- UNSPEC_VUPKHSB))]
-- "TARGET_ALTIVEC"
-- "
--{
-- emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));
-- DONE;
--}")
-+(define_expand "vec_unpacks_hi_<VP_small_lc>"
-+ [(set (match_operand:VP 0 "register_operand" "=v")
-+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]
-+ UNSPEC_VUNPACK_HI_SIGN_DIRECT))]
-+ "<VI_unit>"
-+ "")
-
--(define_expand "vec_unpacks_hi_v8hi"
-- [(set (match_operand:V4SI 0 "register_operand" "=v")
-- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
-- UNSPEC_VUPKHSH))]
-- "TARGET_ALTIVEC"
-- "
--{
-- emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));
-- DONE;
--}")
-+(define_expand "vec_unpacks_lo_<VP_small_lc>"
-+ [(set (match_operand:VP 0 "register_operand" "=v")
-+ (unspec:VP [(match_operand:<VP_small> 1 "register_operand" "v")]
-+ UNSPEC_VUNPACK_LO_SIGN_DIRECT))]
-+ "<VI_unit>"
-+ "")
-
--(define_expand "vec_unpacks_lo_v16qi"
-- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
-- UNSPEC_VUPKLSB))]
-- "TARGET_ALTIVEC"
-- "
--{
-- emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));
-- DONE;
--}")
--
--(define_expand "vec_unpacks_lo_v8hi"
-- [(set (match_operand:V4SI 0 "register_operand" "=v")
-- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
-- UNSPEC_VUPKLSH))]
-- "TARGET_ALTIVEC"
-- "
--{
-- emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));
-- DONE;
--}")
--
- (define_insn "vperm_v8hiv4si"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
-@@ -2025,25 +2711,26 @@
- rtx vzero = gen_reg_rtx (V8HImode);
- rtx mask = gen_reg_rtx (V16QImode);
- rtvec v = rtvec_alloc (16);
-+ bool be = BYTES_BIG_ENDIAN;
-
- emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
-
-- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);
-- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
-- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);
-- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
-- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);
-- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
-- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);
-- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
-+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7);
-+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 0 : 16);
-+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 6);
-+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16);
-+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5);
-+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 2 : 16);
-+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 4);
-+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16);
-+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3);
-+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 4 : 16);
-+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 2);
-+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16);
-+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1);
-+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 6 : 16);
-+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 0);
-+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16);
-
- emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
- emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
-@@ -2060,25 +2747,26 @@
- rtx vzero = gen_reg_rtx (V4SImode);
- rtx mask = gen_reg_rtx (V16QImode);
- rtvec v = rtvec_alloc (16);
-+ bool be = BYTES_BIG_ENDIAN;
-
- emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
-
-- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
-- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);
-- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
-- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
-- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);
-- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
-- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
-- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);
-- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
-- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
-- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);
-- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
-+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7);
-+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 6);
-+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 0 : 17);
-+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16);
-+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5);
-+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 4);
-+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 2 : 17);
-+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16);
-+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3);
-+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 2);
-+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 4 : 17);
-+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16);
-+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1);
-+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 0);
-+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 6 : 17);
-+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16);
-
- emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
- emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
-@@ -2095,25 +2783,26 @@
- rtx vzero = gen_reg_rtx (V8HImode);
- rtx mask = gen_reg_rtx (V16QImode);
- rtvec v = rtvec_alloc (16);
-+ bool be = BYTES_BIG_ENDIAN;
-
- emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
-
-- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);
-- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
-- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
-- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
-- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);
-- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
-- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);
-- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
-+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15);
-+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 8 : 16);
-+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 14);
-+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16);
-+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13);
-+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 10 : 16);
-+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 12);
-+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16);
-+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11);
-+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 12 : 16);
-+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 10);
-+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16);
-+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9);
-+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 14 : 16);
-+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 8);
-+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16);
-
- emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
- emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
-@@ -2130,25 +2819,26 @@
- rtx vzero = gen_reg_rtx (V4SImode);
- rtx mask = gen_reg_rtx (V16QImode);
- rtvec v = rtvec_alloc (16);
-+ bool be = BYTES_BIG_ENDIAN;
-
- emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
-
-- RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
-- RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);
-- RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
-- RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
-- RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
-- RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
-- RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
-- RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);
-- RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
-- RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
-- RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
-- RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);
-- RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
-+ RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15);
-+ RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 14);
-+ RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 8 : 17);
-+ RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16);
-+ RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13);
-+ RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 12);
-+ RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 10 : 17);
-+ RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16);
-+ RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11);
-+ RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 10);
-+ RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 12 : 17);
-+ RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16);
-+ RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9);
-+ RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 8);
-+ RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 14 : 17);
-+ RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16);
-
- emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
- emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
-@@ -2166,9 +2856,18 @@
- rtx ve = gen_reg_rtx (V8HImode);
- rtx vo = gen_reg_rtx (V8HImode);
-
-- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));
-- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));
-- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
-+ }
-+ else
-+ {
-+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
-+ }
- DONE;
- }")
-
-@@ -2183,9 +2882,18 @@
- rtx ve = gen_reg_rtx (V8HImode);
- rtx vo = gen_reg_rtx (V8HImode);
-
-- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));
-- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));
-- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
-+ }
-+ else
-+ {
-+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
-+ }
- DONE;
- }")
-
-@@ -2200,9 +2908,18 @@
- rtx ve = gen_reg_rtx (V8HImode);
- rtx vo = gen_reg_rtx (V8HImode);
-
-- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));
-- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));
-- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
-+ }
-+ else
-+ {
-+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
-+ }
- DONE;
- }")
-
-@@ -2217,9 +2934,18 @@
- rtx ve = gen_reg_rtx (V8HImode);
- rtx vo = gen_reg_rtx (V8HImode);
-
-- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));
-- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));
-- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
-+ }
-+ else
-+ {
-+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
-+ }
- DONE;
- }")
-
-@@ -2234,9 +2960,18 @@
- rtx ve = gen_reg_rtx (V4SImode);
- rtx vo = gen_reg_rtx (V4SImode);
-
-- emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));
-- emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));
-- emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo));
-+ }
-+ else
-+ {
-+ emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
-+ }
- DONE;
- }")
-
-@@ -2251,9 +2986,18 @@
- rtx ve = gen_reg_rtx (V4SImode);
- rtx vo = gen_reg_rtx (V4SImode);
-
-- emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));
-- emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));
-- emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo));
-+ }
-+ else
-+ {
-+ emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
-+ }
- DONE;
- }")
-
-@@ -2268,9 +3012,18 @@
- rtx ve = gen_reg_rtx (V4SImode);
- rtx vo = gen_reg_rtx (V4SImode);
-
-- emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));
-- emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));
-- emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo));
-+ }
-+ else
-+ {
-+ emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
-+ }
- DONE;
- }")
-
-@@ -2285,35 +3038,28 @@
- rtx ve = gen_reg_rtx (V4SImode);
- rtx vo = gen_reg_rtx (V4SImode);
-
-- emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));
-- emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));
-- emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
-+ if (BYTES_BIG_ENDIAN)
-+ {
-+ emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo));
-+ }
-+ else
-+ {
-+ emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2]));
-+ emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
-+ }
- DONE;
- }")
-
--(define_expand "vec_pack_trunc_v8hi"
-- [(set (match_operand:V16QI 0 "register_operand" "=v")
-- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-- (match_operand:V8HI 2 "register_operand" "v")]
-- UNSPEC_VPKUHUM))]
-- "TARGET_ALTIVEC"
-- "
--{
-- emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));
-- DONE;
--}")
--
--(define_expand "vec_pack_trunc_v4si"
-- [(set (match_operand:V8HI 0 "register_operand" "=v")
-- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-- (match_operand:V4SI 2 "register_operand" "v")]
-- UNSPEC_VPKUWUM))]
-- "TARGET_ALTIVEC"
-- "
--{
-- emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));
-- DONE;
--}")
-+(define_expand "vec_pack_trunc_<mode>"
-+ [(set (match_operand:<VP_small> 0 "register_operand" "=v")
-+ (unspec:<VP_small> [(match_operand:VP 1 "register_operand" "v")
-+ (match_operand:VP 2 "register_operand" "v")]
-+ UNSPEC_VPACK_UNS_UNS_MOD))]
-+ "<VI_unit>"
-+ "")
-
- (define_expand "altivec_negv4sf2"
- [(use (match_operand:V4SF 0 "register_operand" ""))
-@@ -2460,3 +3206,243 @@
- emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
- DONE;
- }")
-+
-+
-+;; Power8 vector instructions encoded as Altivec instructions
-+
-+;; Vector count leading zeros
-+(define_insn "*p8v_clz<mode>2"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (clz:VI2 (match_operand:VI2 1 "register_operand" "v")))]
-+ "TARGET_P8_VECTOR"
-+ "vclz<wd> %0,%1"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+;; Vector population count
-+(define_insn "*p8v_popcount<mode>2"
-+ [(set (match_operand:VI2 0 "register_operand" "=v")
-+ (popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))]
-+ "TARGET_P8_VECTOR"
-+ "vpopcnt<wd> %0,%1"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+;; Vector Gather Bits by Bytes by Doubleword
-+(define_insn "p8v_vgbbd"
-+ [(set (match_operand:V16QI 0 "register_operand" "=v")
-+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
-+ UNSPEC_VGBBD))]
-+ "TARGET_P8_VECTOR"
-+ "vgbbd %0,%1"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+
-+;; 128-bit binary integer arithmetic
-+;; We have a special container type (V1TImode) to allow operations using the
-+;; ISA 2.07 128-bit binary support to target the VMX/altivec registers without
-+;; having to worry about the register allocator deciding GPRs are better.
-+
-+(define_insn "altivec_vadduqm"
-+ [(set (match_operand:V1TI 0 "register_operand" "=v")
-+ (plus:V1TI (match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")))]
-+ "TARGET_VADDUQM"
-+ "vadduqm %0,%1,%2"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+(define_insn "altivec_vaddcuq"
-+ [(set (match_operand:V1TI 0 "register_operand" "=v")
-+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")]
-+ UNSPEC_VADDCUQ))]
-+ "TARGET_VADDUQM"
-+ "vaddcuq %0,%1,%2"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+(define_insn "altivec_vsubuqm"
-+ [(set (match_operand:V1TI 0 "register_operand" "=v")
-+ (minus:V1TI (match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")))]
-+ "TARGET_VADDUQM"
-+ "vsubuqm %0,%1,%2"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+(define_insn "altivec_vsubcuq"
-+ [(set (match_operand:V1TI 0 "register_operand" "=v")
-+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")]
-+ UNSPEC_VSUBCUQ))]
-+ "TARGET_VADDUQM"
-+ "vsubcuq %0,%1,%2"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+(define_insn "altivec_vaddeuqm"
-+ [(set (match_operand:V1TI 0 "register_operand" "=v")
-+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")
-+ (match_operand:V1TI 3 "register_operand" "v")]
-+ UNSPEC_VADDEUQM))]
-+ "TARGET_VADDUQM"
-+ "vaddeuqm %0,%1,%2,%3"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+(define_insn "altivec_vaddecuq"
-+ [(set (match_operand:V1TI 0 "register_operand" "=v")
-+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")
-+ (match_operand:V1TI 3 "register_operand" "v")]
-+ UNSPEC_VADDECUQ))]
-+ "TARGET_VADDUQM"
-+ "vaddecuq %0,%1,%2,%3"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+(define_insn "altivec_vsubeuqm"
-+ [(set (match_operand:V1TI 0 "register_operand" "=v")
-+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")
-+ (match_operand:V1TI 3 "register_operand" "v")]
-+ UNSPEC_VSUBEUQM))]
-+ "TARGET_VADDUQM"
-+ "vsubeuqm %0,%1,%2,%3"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+(define_insn "altivec_vsubecuq"
-+ [(set (match_operand:V1TI 0 "register_operand" "=v")
-+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")
-+ (match_operand:V1TI 3 "register_operand" "v")]
-+ UNSPEC_VSUBECUQ))]
-+ "TARGET_VADDUQM"
-+ "vsubecuq %0,%1,%2,%3"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+;; We use V2DI as the output type to simplify converting the permute
-+;; bits into an integer
-+(define_insn "altivec_vbpermq"
-+ [(set (match_operand:V2DI 0 "register_operand" "=v")
-+ (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "v")
-+ (match_operand:V16QI 2 "register_operand" "v")]
-+ UNSPEC_VBPERMQ))]
-+ "TARGET_P8_VECTOR"
-+ "vbpermq %0,%1,%2"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+;; Decimal Integer operations
-+(define_int_iterator UNSPEC_BCD_ADD_SUB [UNSPEC_BCDADD UNSPEC_BCDSUB])
-+
-+(define_int_attr bcd_add_sub [(UNSPEC_BCDADD "add")
-+ (UNSPEC_BCDSUB "sub")])
-+
-+(define_code_iterator BCD_TEST [eq lt gt unordered])
-+
-+(define_insn "bcd<bcd_add_sub>"
-+ [(set (match_operand:V1TI 0 "register_operand" "")
-+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")
-+ (match_operand:V1TI 2 "register_operand" "")
-+ (match_operand:QI 3 "const_0_to_1_operand" "")]
-+ UNSPEC_BCD_ADD_SUB))
-+ (clobber (reg:CCFP 74))]
-+ "TARGET_P8_VECTOR"
-+ "bcd<bcd_add_sub>. %0,%1,%2,%3"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we
-+;; can use the unordered test for BCD nans and add/subtracts that overflow. An
-+;; UNORDERED test on an integer type (like V1TImode) is not defined. The type
-+;; probably should be one that can go in the VMX (Altivec) registers, so we
-+;; can't use DDmode or DFmode.
-+(define_insn "*bcd<bcd_add_sub>_test"
-+ [(set (reg:CCFP 74)
-+ (compare:CCFP
-+ (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")
-+ (match_operand:QI 3 "const_0_to_1_operand" "i")]
-+ UNSPEC_BCD_ADD_SUB)
-+ (match_operand:V2DF 4 "zero_constant" "j")))
-+ (clobber (match_scratch:V1TI 0 "=v"))]
-+ "TARGET_P8_VECTOR"
-+ "bcd<bcd_add_sub>. %0,%1,%2,%3"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+(define_insn "*bcd<bcd_add_sub>_test2"
-+ [(set (match_operand:V1TI 0 "register_operand" "=v")
-+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")
-+ (match_operand:V1TI 2 "register_operand" "v")
-+ (match_operand:QI 3 "const_0_to_1_operand" "i")]
-+ UNSPEC_BCD_ADD_SUB))
-+ (set (reg:CCFP 74)
-+ (compare:CCFP
-+ (unspec:V2DF [(match_dup 1)
-+ (match_dup 2)
-+ (match_dup 3)]
-+ UNSPEC_BCD_ADD_SUB)
-+ (match_operand:V2DF 4 "zero_constant" "j")))]
-+ "TARGET_P8_VECTOR"
-+ "bcd<bcd_add_sub>. %0,%1,%2,%3"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "vecsimple")])
-+
-+(define_expand "bcd<bcd_add_sub>_<code>"
-+ [(parallel [(set (reg:CCFP 74)
-+ (compare:CCFP
-+ (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")
-+ (match_operand:V1TI 2 "register_operand" "")
-+ (match_operand:QI 3 "const_0_to_1_operand" "")]
-+ UNSPEC_BCD_ADD_SUB)
-+ (match_dup 4)))
-+ (clobber (match_scratch:V1TI 5 ""))])
-+ (set (match_operand:SI 0 "register_operand" "")
-+ (BCD_TEST:SI (reg:CCFP 74)
-+ (const_int 0)))]
-+ "TARGET_P8_VECTOR"
-+{
-+ operands[4] = CONST0_RTX (V2DFmode);
-+})
-+
-+;; Peephole2 pattern to combine a bcdadd/bcdsub that calculates the value and
-+;; the bcdadd/bcdsub that tests the value. The combiner won't work since
-+;; CR6 is a hard coded register. Unfortunately, all of the Altivec predicate
-+;; support is hard coded to use the fixed register CR6 instead of creating
-+;; a register class for CR6.
-+
-+(define_peephole2
-+ [(parallel [(set (match_operand:V1TI 0 "register_operand" "")
-+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")
-+ (match_operand:V1TI 2 "register_operand" "")
-+ (match_operand:QI 3 "const_0_to_1_operand" "")]
-+ UNSPEC_BCD_ADD_SUB))
-+ (clobber (reg:CCFP 74))])
-+ (parallel [(set (reg:CCFP 74)
-+ (compare:CCFP
-+ (unspec:V2DF [(match_dup 1)
-+ (match_dup 2)
-+ (match_dup 3)]
-+ UNSPEC_BCD_ADD_SUB)
-+ (match_operand:V2DF 4 "zero_constant" "")))
-+ (clobber (match_operand:V1TI 5 "register_operand" ""))])]
-+ "TARGET_P8_VECTOR"
-+ [(parallel [(set (match_dup 0)
-+ (unspec:V1TI [(match_dup 1)
-+ (match_dup 2)
-+ (match_dup 3)]
-+ UNSPEC_BCD_ADD_SUB))
-+ (set (reg:CCFP 74)
-+ (compare:CCFP
-+ (unspec:V2DF [(match_dup 1)
-+ (match_dup 2)
-+ (match_dup 3)]
-+ UNSPEC_BCD_ADD_SUB)
-+ (match_dup 4)))])])
-Index: gcc/config/rs6000/sysv4le.h
-===================================================================
---- a/src/gcc/config/rs6000/sysv4le.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/sysv4le.h (.../branches/gcc-4_8-branch)
-@@ -22,9 +22,6 @@
- #undef TARGET_DEFAULT
- #define TARGET_DEFAULT MASK_LITTLE_ENDIAN
-
--#undef CC1_ENDIAN_DEFAULT_SPEC
--#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)"
--
- #undef DEFAULT_ASM_ENDIAN
- #define DEFAULT_ASM_ENDIAN " -mlittle"
-
-@@ -34,3 +31,7 @@
-
- #undef MULTILIB_DEFAULTS
- #define MULTILIB_DEFAULTS { "mlittle", "mcall-sysv" }
-+
-+/* Little-endian PowerPC64 Linux uses the ELF v2 ABI by default. */
-+#define LINUX64_DEFAULT_ABI_ELFv2
-+
-Index: gcc/config/rs6000/dfp.md
-===================================================================
---- a/src/gcc/config/rs6000/dfp.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/dfp.md (.../branches/gcc-4_8-branch)
-@@ -29,77 +29,6 @@
- ])
-
-
--(define_expand "movsd"
-- [(set (match_operand:SD 0 "nonimmediate_operand" "")
-- (match_operand:SD 1 "any_operand" ""))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS"
-- "{ rs6000_emit_move (operands[0], operands[1], SDmode); DONE; }")
--
--(define_split
-- [(set (match_operand:SD 0 "gpc_reg_operand" "")
-- (match_operand:SD 1 "const_double_operand" ""))]
-- "reload_completed
-- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-- || (GET_CODE (operands[0]) == SUBREG
-- && GET_CODE (SUBREG_REG (operands[0])) == REG
-- && REGNO (SUBREG_REG (operands[0])) <= 31))"
-- [(set (match_dup 2) (match_dup 3))]
-- "
--{
-- long l;
-- REAL_VALUE_TYPE rv;
--
-- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-- REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
--
-- if (! TARGET_POWERPC64)
-- operands[2] = operand_subword (operands[0], 0, 0, SDmode);
-- else
-- operands[2] = gen_lowpart (SImode, operands[0]);
--
-- operands[3] = gen_int_mode (l, SImode);
--}")
--
--(define_insn "movsd_hardfloat"
-- [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,!r,*h,!r,!r")
-- (match_operand:SD 1 "input_operand" "r,m,r,f,r,h,0,G,Fn"))]
-- "(gpc_reg_operand (operands[0], SDmode)
-- || gpc_reg_operand (operands[1], SDmode))
-- && (TARGET_HARD_FLOAT && TARGET_FPRS)"
-- "@
-- mr %0,%1
-- lwz%U1%X1 %0,%1
-- stw%U0%X0 %1,%0
-- fmr %0,%1
-- mt%0 %1
-- mf%1 %0
-- nop
-- #
-- #"
-- [(set_attr "type" "*,load,store,fp,mtjmpr,mfjmpr,*,*,*")
-- (set_attr "length" "4,4,4,4,4,4,4,4,8")])
--
--(define_insn "movsd_softfloat"
-- [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,r,*h")
-- (match_operand:SD 1 "input_operand" "r,r,h,m,r,I,L,R,G,Fn,0"))]
-- "(gpc_reg_operand (operands[0], SDmode)
-- || gpc_reg_operand (operands[1], SDmode))
-- && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
-- "@
-- mr %0,%1
-- mt%0 %1
-- mf%1 %0
-- lwz%U1%X1 %0,%1
-- stw%U0%X0 %1,%0
-- li %0,%1
-- lis %0,%v1
-- la %0,%a1
-- #
-- #
-- nop"
-- [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*,*")
-- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")])
--
- (define_insn "movsd_store"
- [(set (match_operand:DD 0 "nonimmediate_operand" "=m")
- (unspec:DD [(match_operand:SD 1 "input_operand" "d")]
-@@ -108,7 +37,14 @@
- || gpc_reg_operand (operands[1], SDmode))
- && TARGET_HARD_FLOAT && TARGET_FPRS"
- "stfd%U0%X0 %1,%0"
-- [(set_attr "type" "fpstore")
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_u")
-+ (const_string "fpstore"))))
- (set_attr "length" "4")])
-
- (define_insn "movsd_load"
-@@ -119,7 +55,14 @@
- || gpc_reg_operand (operands[1], DDmode))
- && TARGET_HARD_FLOAT && TARGET_FPRS"
- "lfd%U1%X1 %0,%1"
-- [(set_attr "type" "fpload")
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_u")
-+ (const_string "fpload"))))
- (set_attr "length" "4")])
-
- ;; Hardware support for decimal floating point operations.
-@@ -182,211 +125,6 @@
- "fnabs %0,%1"
- [(set_attr "type" "fp")])
-
--(define_expand "movdd"
-- [(set (match_operand:DD 0 "nonimmediate_operand" "")
-- (match_operand:DD 1 "any_operand" ""))]
-- ""
-- "{ rs6000_emit_move (operands[0], operands[1], DDmode); DONE; }")
--
--(define_split
-- [(set (match_operand:DD 0 "gpc_reg_operand" "")
-- (match_operand:DD 1 "const_int_operand" ""))]
-- "! TARGET_POWERPC64 && reload_completed
-- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-- || (GET_CODE (operands[0]) == SUBREG
-- && GET_CODE (SUBREG_REG (operands[0])) == REG
-- && REGNO (SUBREG_REG (operands[0])) <= 31))"
-- [(set (match_dup 2) (match_dup 4))
-- (set (match_dup 3) (match_dup 1))]
-- "
--{
-- int endian = (WORDS_BIG_ENDIAN == 0);
-- HOST_WIDE_INT value = INTVAL (operands[1]);
--
-- operands[2] = operand_subword (operands[0], endian, 0, DDmode);
-- operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);
--#if HOST_BITS_PER_WIDE_INT == 32
-- operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
--#else
-- operands[4] = GEN_INT (value >> 32);
-- operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
--#endif
--}")
--
--(define_split
-- [(set (match_operand:DD 0 "gpc_reg_operand" "")
-- (match_operand:DD 1 "const_double_operand" ""))]
-- "! TARGET_POWERPC64 && reload_completed
-- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-- || (GET_CODE (operands[0]) == SUBREG
-- && GET_CODE (SUBREG_REG (operands[0])) == REG
-- && REGNO (SUBREG_REG (operands[0])) <= 31))"
-- [(set (match_dup 2) (match_dup 4))
-- (set (match_dup 3) (match_dup 5))]
-- "
--{
-- int endian = (WORDS_BIG_ENDIAN == 0);
-- long l[2];
-- REAL_VALUE_TYPE rv;
--
-- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-- REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
--
-- operands[2] = operand_subword (operands[0], endian, 0, DDmode);
-- operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);
-- operands[4] = gen_int_mode (l[endian], SImode);
-- operands[5] = gen_int_mode (l[1 - endian], SImode);
--}")
--
--(define_split
-- [(set (match_operand:DD 0 "gpc_reg_operand" "")
-- (match_operand:DD 1 "const_double_operand" ""))]
-- "TARGET_POWERPC64 && reload_completed
-- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-- || (GET_CODE (operands[0]) == SUBREG
-- && GET_CODE (SUBREG_REG (operands[0])) == REG
-- && REGNO (SUBREG_REG (operands[0])) <= 31))"
-- [(set (match_dup 2) (match_dup 3))]
-- "
--{
-- int endian = (WORDS_BIG_ENDIAN == 0);
-- long l[2];
-- REAL_VALUE_TYPE rv;
--#if HOST_BITS_PER_WIDE_INT >= 64
-- HOST_WIDE_INT val;
--#endif
--
-- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-- REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
--
-- operands[2] = gen_lowpart (DImode, operands[0]);
-- /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
--#if HOST_BITS_PER_WIDE_INT >= 64
-- val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
-- | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
--
-- operands[3] = gen_int_mode (val, DImode);
--#else
-- operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
--#endif
--}")
--
--;; Don't have reload use general registers to load a constant. First,
--;; it might not work if the output operand is the equivalent of
--;; a non-offsettable memref, but also it is less efficient than loading
--;; the constant into an FP register, since it will probably be used there.
--;; The "??" is a kludge until we can figure out a more reasonable way
--;; of handling these non-offsettable values.
--(define_insn "*movdd_hardfloat32"
-- [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")
-- (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]
-- "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
-- && (gpc_reg_operand (operands[0], DDmode)
-- || gpc_reg_operand (operands[1], DDmode))"
-- "*
--{
-- switch (which_alternative)
-- {
-- default:
-- gcc_unreachable ();
-- case 0:
-- case 1:
-- case 2:
-- return \"#\";
-- case 3:
-- return \"fmr %0,%1\";
-- case 4:
-- return \"lfd%U1%X1 %0,%1\";
-- case 5:
-- return \"stfd%U0%X0 %1,%0\";
-- case 6:
-- case 7:
-- case 8:
-- return \"#\";
-- }
--}"
-- [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
-- (set_attr "length" "8,16,16,4,4,4,8,12,16")])
--
--(define_insn "*movdd_softfloat32"
-- [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r")
-- (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))]
-- "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
-- && (gpc_reg_operand (operands[0], DDmode)
-- || gpc_reg_operand (operands[1], DDmode))"
-- "#"
-- [(set_attr "type" "two,load,store,*,*,*")
-- (set_attr "length" "8,8,8,8,12,16")])
--
--; ld/std require word-aligned displacements -> 'Y' constraint.
--; List Y->r and r->Y before r->r for reload.
--(define_insn "*movdd_hardfloat64_mfpgpr"
-- [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
-- (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
-- "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
-- && (gpc_reg_operand (operands[0], DDmode)
-- || gpc_reg_operand (operands[1], DDmode))"
-- "@
-- std%U0%X0 %1,%0
-- ld%U1%X1 %0,%1
-- mr %0,%1
-- fmr %0,%1
-- lfd%U1%X1 %0,%1
-- stfd%U0%X0 %1,%0
-- mt%0 %1
-- mf%1 %0
-- nop
-- #
-- #
-- #
-- mftgpr %0,%1
-- mffgpr %0,%1"
-- [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
-- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
--
--; ld/std require word-aligned displacements -> 'Y' constraint.
--; List Y->r and r->Y before r->r for reload.
--(define_insn "*movdd_hardfloat64"
-- [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
-- (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
-- "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
-- && (gpc_reg_operand (operands[0], DDmode)
-- || gpc_reg_operand (operands[1], DDmode))"
-- "@
-- std%U0%X0 %1,%0
-- ld%U1%X1 %0,%1
-- mr %0,%1
-- fmr %0,%1
-- lfd%U1%X1 %0,%1
-- stfd%U0%X0 %1,%0
-- mt%0 %1
-- mf%1 %0
-- nop
-- #
-- #
-- #"
-- [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
-- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
--
--(define_insn "*movdd_softfloat64"
-- [(set (match_operand:DD 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
-- (match_operand:DD 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
-- "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
-- && (gpc_reg_operand (operands[0], DDmode)
-- || gpc_reg_operand (operands[1], DDmode))"
-- "@
-- ld%U1%X1 %0,%1
-- std%U0%X0 %1,%0
-- mr %0,%1
-- mt%0 %1
-- mf%1 %0
-- #
-- #
-- #
-- nop"
-- [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
-- (set_attr "length" "4,4,4,4,4,8,12,16,4")])
--
- (define_expand "negtd2"
- [(set (match_operand:TD 0 "gpc_reg_operand" "")
- (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
-@@ -410,40 +148,25 @@
- "")
-
- (define_insn "*abstd2_fpr"
-- [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
-- (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
-+ [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
-+ (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
-- "fabs %0,%1"
-- [(set_attr "type" "fp")])
-+ "@
-+ fabs %0,%1
-+ fabs %0,%1\;fmr %L0,%L1"
-+ [(set_attr "type" "fp")
-+ (set_attr "length" "4,8")])
-
- (define_insn "*nabstd2_fpr"
-- [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
-- (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))]
-+ [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
-+ (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
-- "fnabs %0,%1"
-- [(set_attr "type" "fp")])
-+ "@
-+ fnabs %0,%1
-+ fnabs %0,%1\;fmr %L0,%L1"
-+ [(set_attr "type" "fp")
-+ (set_attr "length" "4,8")])
-
--(define_expand "movtd"
-- [(set (match_operand:TD 0 "general_operand" "")
-- (match_operand:TD 1 "any_operand" ""))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS"
-- "{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }")
--
--; It's important to list the Y->r and r->Y moves before r->r because
--; otherwise reload, given m->r, will try to pick r->r and reload it,
--; which doesn't make progress.
--(define_insn_and_split "*movtd_internal"
-- [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
-- (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS
-- && (gpc_reg_operand (operands[0], TDmode)
-- || gpc_reg_operand (operands[1], TDmode))"
-- "#"
-- "&& reload_completed"
-- [(pc)]
--{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
-- [(set_attr "length" "8,8,8,20,20,16")])
--
- ;; Hardware support for decimal floating point operations.
-
- (define_insn "extendddtd2"
-@@ -599,3 +322,72 @@
- "TARGET_DFP"
- "dctfixq %0,%1"
- [(set_attr "type" "fp")])
-+
-+
-+;; Decimal builtin support
-+
-+(define_c_enum "unspec"
-+ [UNSPEC_DDEDPD
-+ UNSPEC_DENBCD
-+ UNSPEC_DXEX
-+ UNSPEC_DIEX
-+ UNSPEC_DSCLI
-+ UNSPEC_DSCRI])
-+
-+(define_mode_iterator D64_D128 [DD TD])
-+
-+(define_mode_attr dfp_suffix [(DD "")
-+ (TD "q")])
-+
-+(define_insn "dfp_ddedpd_<mode>"
-+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-+ (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")
-+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
-+ UNSPEC_DDEDPD))]
-+ "TARGET_DFP"
-+ "ddedpd<dfp_suffix> %1,%0,%2"
-+ [(set_attr "type" "fp")])
-+
-+(define_insn "dfp_denbcd_<mode>"
-+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-+ (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")
-+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
-+ UNSPEC_DENBCD))]
-+ "TARGET_DFP"
-+ "denbcd<dfp_suffix> %1,%0,%2"
-+ [(set_attr "type" "fp")])
-+
-+(define_insn "dfp_dxex_<mode>"
-+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]
-+ UNSPEC_DXEX))]
-+ "TARGET_DFP"
-+ "dxex<dfp_suffix> %0,%1"
-+ [(set_attr "type" "fp")])
-+
-+(define_insn "dfp_diex_<mode>"
-+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
-+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
-+ UNSPEC_DXEX))]
-+ "TARGET_DFP"
-+ "diex<dfp_suffix> %0,%1,%2"
-+ [(set_attr "type" "fp")])
-+
-+(define_insn "dfp_dscli_<mode>"
-+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
-+ (match_operand:QI 2 "immediate_operand" "i")]
-+ UNSPEC_DSCLI))]
-+ "TARGET_DFP"
-+ "dscli<dfp_suffix> %0,%1,%2"
-+ [(set_attr "type" "fp")])
-+
-+(define_insn "dfp_dscri_<mode>"
-+ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-+ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
-+ (match_operand:QI 2 "immediate_operand" "i")]
-+ UNSPEC_DSCRI))]
-+ "TARGET_DFP"
-+ "dscri<dfp_suffix> %0,%1,%2"
-+ [(set_attr "type" "fp")])
-Index: gcc/config/rs6000/t-linux64
-===================================================================
---- a/src/gcc/config/rs6000/t-linux64 (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/t-linux64 (.../branches/gcc-4_8-branch)
-@@ -25,8 +25,8 @@
- # it doesn't tell anything about the 32bit libraries on those systems. Set
- # MULTILIB_OSDIRNAMES according to what is found on the target.
-
--MULTILIB_OPTIONS = m64/m32
--MULTILIB_DIRNAMES = 64 32
--MULTILIB_EXTRA_OPTS = fPIC
--MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:powerpc64-linux-gnu)
--MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)
-+MULTILIB_OPTIONS := m64/m32
-+MULTILIB_DIRNAMES := 64 32
-+MULTILIB_EXTRA_OPTS :=
-+MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu)
-+MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)
-Index: gcc/config/rs6000/sync.md
-===================================================================
---- a/src/gcc/config/rs6000/sync.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/sync.md (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,5 @@
- ;; Machine description for PowerPC synchronization instructions.
--;; Copyright (C) 2005-2013 Free Software Foundation, Inc.
-+;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
- ;; Contributed by Geoffrey Keating.
-
- ;; This file is part of GCC.
-@@ -18,14 +18,23 @@
- ;; along with GCC; see the file COPYING3. If not see
- ;; <http://www.gnu.org/licenses/>.
-
--(define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
--(define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
-+(define_mode_attr larx [(QI "lbarx")
-+ (HI "lharx")
-+ (SI "lwarx")
-+ (DI "ldarx")
-+ (TI "lqarx")])
-
-+(define_mode_attr stcx [(QI "stbcx.")
-+ (HI "sthcx.")
-+ (SI "stwcx.")
-+ (DI "stdcx.")
-+ (TI "stqcx.")])
-+
- (define_code_iterator FETCHOP [plus minus ior xor and])
- (define_code_attr fetchop_name
- [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
- (define_code_attr fetchop_pred
-- [(plus "add_operand") (minus "gpc_reg_operand")
-+ [(plus "add_operand") (minus "int_reg_operand")
- (ior "logical_operand") (xor "logical_operand") (and "and_operand")])
-
- (define_expand "mem_thread_fence"
-@@ -98,10 +107,17 @@
- "isync"
- [(set_attr "type" "isync")])
-
-+;; Types that we should provide atomic instructions for.
-+(define_mode_iterator AINT [QI
-+ HI
-+ SI
-+ (DI "TARGET_POWERPC64")
-+ (TI "TARGET_SYNC_TI")])
-+
- ;; The control dependency used for load dependency described
- ;; in B.2.3 of the Power ISA 2.06B.
- (define_insn "loadsync_<mode>"
-- [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")]
-+ [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")]
- UNSPECV_ISYNC)
- (clobber (match_scratch:CC 1 "=y"))]
- ""
-@@ -109,19 +125,74 @@
- [(set_attr "type" "isync")
- (set_attr "length" "12")])
-
-+(define_insn "load_quadpti"
-+ [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
-+ (unspec:PTI
-+ [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))]
-+ "TARGET_SYNC_TI
-+ && !reg_mentioned_p (operands[0], operands[1])"
-+ "lq %0,%1"
-+ [(set_attr "type" "load")
-+ (set_attr "length" "4")])
-+
- (define_expand "atomic_load<mode>"
-- [(set (match_operand:INT1 0 "register_operand" "") ;; output
-- (match_operand:INT1 1 "memory_operand" "")) ;; memory
-+ [(set (match_operand:AINT 0 "register_operand" "") ;; output
-+ (match_operand:AINT 1 "memory_operand" "")) ;; memory
- (use (match_operand:SI 2 "const_int_operand" ""))] ;; model
- ""
- {
-+ if (<MODE>mode == TImode && !TARGET_SYNC_TI)
-+ FAIL;
-+
- enum memmodel model = (enum memmodel) INTVAL (operands[2]);
-
- if (model == MEMMODEL_SEQ_CST)
- emit_insn (gen_hwsync ());
-
-- emit_move_insn (operands[0], operands[1]);
-+ if (<MODE>mode != TImode)
-+ emit_move_insn (operands[0], operands[1]);
-+ else
-+ {
-+ rtx op0 = operands[0];
-+ rtx op1 = operands[1];
-+ rtx pti_reg = gen_reg_rtx (PTImode);
-
-+ // Can't have indexed address for 'lq'
-+ if (indexed_address (XEXP (op1, 0), TImode))
-+ {
-+ rtx old_addr = XEXP (op1, 0);
-+ rtx new_addr = force_reg (Pmode, old_addr);
-+ operands[1] = op1 = replace_equiv_address (op1, new_addr);
-+ }
-+
-+ emit_insn (gen_load_quadpti (pti_reg, op1));
-+
-+ /* For 4.8 we need to do explicit dword copies, even in big endian mode,
-+ unless we are using the LRA register allocator. The 4.9 register
-+ allocator is smart enough to assign an even/odd pair. */
-+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)
-+ emit_move_insn (op0, gen_lowpart (TImode, pti_reg));
-+ else
-+ {
-+ rtx op0_lo = gen_lowpart (DImode, op0);
-+ rtx op0_hi = gen_highpart (DImode, op0);
-+ rtx pti_lo = gen_lowpart (DImode, pti_reg);
-+ rtx pti_hi = gen_highpart (DImode, pti_reg);
-+
-+ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
-+ if (WORDS_BIG_ENDIAN)
-+ {
-+ emit_move_insn (op0_hi, pti_hi);
-+ emit_move_insn (op0_lo, pti_lo);
-+ }
-+ else
-+ {
-+ emit_move_insn (op0_hi, pti_lo);
-+ emit_move_insn (op0_lo, pti_hi);
-+ }
-+ }
-+ }
-+
- switch (model)
- {
- case MEMMODEL_RELAXED:
-@@ -129,16 +200,7 @@
- case MEMMODEL_CONSUME:
- case MEMMODEL_ACQUIRE:
- case MEMMODEL_SEQ_CST:
-- if (GET_MODE (operands[0]) == QImode)
-- emit_insn (gen_loadsync_qi (operands[0]));
-- else if (GET_MODE (operands[0]) == HImode)
-- emit_insn (gen_loadsync_hi (operands[0]));
-- else if (GET_MODE (operands[0]) == SImode)
-- emit_insn (gen_loadsync_si (operands[0]));
-- else if (GET_MODE (operands[0]) == DImode)
-- emit_insn (gen_loadsync_di (operands[0]));
-- else
-- gcc_unreachable ();
-+ emit_insn (gen_loadsync_<mode> (operands[0]));
- break;
- default:
- gcc_unreachable ();
-@@ -146,12 +208,24 @@
- DONE;
- })
-
-+(define_insn "store_quadpti"
-+ [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ")
-+ (unspec:PTI
-+ [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))]
-+ "TARGET_SYNC_TI"
-+ "stq %1,%0"
-+ [(set_attr "type" "store")
-+ (set_attr "length" "4")])
-+
- (define_expand "atomic_store<mode>"
-- [(set (match_operand:INT1 0 "memory_operand" "") ;; memory
-- (match_operand:INT1 1 "register_operand" "")) ;; input
-+ [(set (match_operand:AINT 0 "memory_operand" "") ;; memory
-+ (match_operand:AINT 1 "register_operand" "")) ;; input
- (use (match_operand:SI 2 "const_int_operand" ""))] ;; model
- ""
- {
-+ if (<MODE>mode == TImode && !TARGET_SYNC_TI)
-+ FAIL;
-+
- enum memmodel model = (enum memmodel) INTVAL (operands[2]);
- switch (model)
- {
-@@ -166,18 +240,65 @@
- default:
- gcc_unreachable ();
- }
-- emit_move_insn (operands[0], operands[1]);
-+ if (<MODE>mode != TImode)
-+ emit_move_insn (operands[0], operands[1]);
-+ else
-+ {
-+ rtx op0 = operands[0];
-+ rtx op1 = operands[1];
-+ rtx pti_reg = gen_reg_rtx (PTImode);
-+
-+ // Can't have indexed address for 'stq'
-+ if (indexed_address (XEXP (op0, 0), TImode))
-+ {
-+ rtx old_addr = XEXP (op0, 0);
-+ rtx new_addr = force_reg (Pmode, old_addr);
-+ operands[0] = op0 = replace_equiv_address (op0, new_addr);
-+ }
-+
-+ /* For 4.8 we need to do explicit dword copies, even in big endian mode,
-+ unless we are using the LRA register allocator. The 4.9 register
-+ allocator is smart enough to assign an even/odd pair. */
-+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)
-+ emit_move_insn (pti_reg, gen_lowpart (PTImode, op1));
-+ else
-+ {
-+ rtx op1_lo = gen_lowpart (DImode, op1);
-+ rtx op1_hi = gen_highpart (DImode, op1);
-+ rtx pti_lo = gen_lowpart (DImode, pti_reg);
-+ rtx pti_hi = gen_highpart (DImode, pti_reg);
-+
-+ emit_insn (gen_rtx_CLOBBER (VOIDmode, pti_reg));
-+ if (WORDS_BIG_ENDIAN)
-+ {
-+ emit_move_insn (pti_hi, op1_hi);
-+ emit_move_insn (pti_lo, op1_lo);
-+ }
-+ else
-+ {
-+ emit_move_insn (pti_hi, op1_lo);
-+ emit_move_insn (pti_lo, op1_hi);
-+ }
-+ }
-+
-+ emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg));
-+ }
-+
- DONE;
- })
-
--;; ??? Power ISA 2.06B says that there *is* a load-{byte,half}-and-reserve
--;; opcode that is "phased-in". Not implemented as of Power7, so not yet used,
--;; but let's prepare the macros anyway.
-+;; Any supported integer mode that has atomic l<x>arx/st<x>cx. instrucitons
-+;; other than the quad memory operations, which have special restrictions.
-+;; Byte/halfword atomic instructions were added in ISA 2.06B, but were phased
-+;; in and did not show up until power8. TImode atomic lqarx/stqcx. require
-+;; special handling due to even/odd register requirements.
-+(define_mode_iterator ATOMIC [(QI "TARGET_SYNC_HI_QI")
-+ (HI "TARGET_SYNC_HI_QI")
-+ SI
-+ (DI "TARGET_POWERPC64")])
-
--(define_mode_iterator ATOMIC [SI (DI "TARGET_POWERPC64")])
--
- (define_insn "load_locked<mode>"
-- [(set (match_operand:ATOMIC 0 "gpc_reg_operand" "=r")
-+ [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")
- (unspec_volatile:ATOMIC
- [(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))]
- ""
-@@ -184,21 +305,159 @@
- "<larx> %0,%y1"
- [(set_attr "type" "load_l")])
-
-+(define_insn "load_locked<QHI:mode>_si"
-+ [(set (match_operand:SI 0 "int_reg_operand" "=r")
-+ (unspec_volatile:SI
-+ [(match_operand:QHI 1 "memory_operand" "Z")] UNSPECV_LL))]
-+ "TARGET_SYNC_HI_QI"
-+ "<QHI:larx> %0,%y1"
-+ [(set_attr "type" "load_l")])
-+
-+;; Use PTImode to get even/odd register pairs.
-+
-+;; Use a temporary register to force getting an even register for the
-+;; lqarx/stqcrx. instructions. Under AT 7.0, we need use an explicit copy,
-+;; even in big endian mode, unless we are using the LRA register allocator. In
-+;; GCC 4.9, the register allocator is smart enough to assign a even/odd
-+;; register pair.
-+
-+;; On little endian systems where non-atomic quad word load/store instructions
-+;; are not used, the address can be register+offset, so make sure the address
-+;; is indexed or indirect before register allocation.
-+
-+(define_expand "load_lockedti"
-+ [(use (match_operand:TI 0 "quad_int_reg_operand" ""))
-+ (use (match_operand:TI 1 "memory_operand" ""))]
-+ "TARGET_SYNC_TI"
-+{
-+ rtx op0 = operands[0];
-+ rtx op1 = operands[1];
-+ rtx pti = gen_reg_rtx (PTImode);
-+
-+ if (!indexed_or_indirect_operand (op1, TImode))
-+ {
-+ rtx old_addr = XEXP (op1, 0);
-+ rtx new_addr = force_reg (Pmode, old_addr);
-+ operands[1] = op1 = change_address (op1, TImode, new_addr);
-+ }
-+
-+ emit_insn (gen_load_lockedpti (pti, op1));
-+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)
-+ emit_move_insn (op0, gen_lowpart (TImode, pti));
-+ else
-+ {
-+ rtx op0_lo = gen_lowpart (DImode, op0);
-+ rtx op0_hi = gen_highpart (DImode, op0);
-+ rtx pti_lo = gen_lowpart (DImode, pti);
-+ rtx pti_hi = gen_highpart (DImode, pti);
-+
-+ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
-+ if (WORDS_BIG_ENDIAN)
-+ {
-+ emit_move_insn (op0_hi, pti_hi);
-+ emit_move_insn (op0_lo, pti_lo);
-+ }
-+ else
-+ {
-+ emit_move_insn (op0_hi, pti_lo);
-+ emit_move_insn (op0_lo, pti_hi);
-+ }
-+ }
-+ DONE;
-+})
-+
-+(define_insn "load_lockedpti"
-+ [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
-+ (unspec_volatile:PTI
-+ [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")] UNSPECV_LL))]
-+ "TARGET_SYNC_TI
-+ && !reg_mentioned_p (operands[0], operands[1])
-+ && quad_int_reg_operand (operands[0], PTImode)"
-+ "lqarx %0,%y1"
-+ [(set_attr "type" "load_l")])
-+
- (define_insn "store_conditional<mode>"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
- (set (match_operand:ATOMIC 1 "memory_operand" "=Z")
-- (match_operand:ATOMIC 2 "gpc_reg_operand" "r"))]
-+ (match_operand:ATOMIC 2 "int_reg_operand" "r"))]
- ""
- "<stcx> %2,%y1"
- [(set_attr "type" "store_c")])
-
-+;; Use a temporary register to force getting an even register for the
-+;; lqarx/stqcrx. instructions. Under AT 7.0, we need use an explicit copy,
-+;; even in big endian mode. In GCC 4.9, the register allocator is smart enough
-+;; to assign a even/odd register pair.
-+
-+;; On little endian systems where non-atomic quad word load/store instructions
-+;; are not used, the address can be register+offset, so make sure the address
-+;; is indexed or indirect before register allocation.
-+
-+(define_expand "store_conditionalti"
-+ [(use (match_operand:CC 0 "cc_reg_operand" ""))
-+ (use (match_operand:TI 1 "memory_operand" ""))
-+ (use (match_operand:TI 2 "quad_int_reg_operand" ""))]
-+ "TARGET_SYNC_TI"
-+{
-+ rtx op0 = operands[0];
-+ rtx op1 = operands[1];
-+ rtx op2 = operands[2];
-+ rtx addr = XEXP (op1, 0);
-+ rtx pti_mem;
-+ rtx pti_reg;
-+
-+ if (!indexed_or_indirect_operand (op1, TImode))
-+ {
-+ rtx new_addr = force_reg (Pmode, addr);
-+ operands[1] = op1 = change_address (op1, TImode, new_addr);
-+ addr = new_addr;
-+ }
-+
-+ pti_mem = change_address (op1, PTImode, addr);
-+ pti_reg = gen_reg_rtx (PTImode);
-+
-+ if (WORDS_BIG_ENDIAN && rs6000_lra_flag)
-+ emit_move_insn (pti_reg, gen_lowpart (PTImode, op2));
-+ else
-+ {
-+ rtx op2_lo = gen_lowpart (DImode, op2);
-+ rtx op2_hi = gen_highpart (DImode, op2);
-+ rtx pti_lo = gen_lowpart (DImode, pti_reg);
-+ rtx pti_hi = gen_highpart (DImode, pti_reg);
-+
-+ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
-+ if (WORDS_BIG_ENDIAN)
-+ {
-+ emit_move_insn (pti_hi, op2_hi);
-+ emit_move_insn (pti_lo, op2_lo);
-+ }
-+ else
-+ {
-+ emit_move_insn (pti_hi, op2_lo);
-+ emit_move_insn (pti_lo, op2_hi);
-+ }
-+ }
-+
-+ emit_insn (gen_store_conditionalpti (op0, pti_mem, pti_reg));
-+ DONE;
-+})
-+
-+(define_insn "store_conditionalpti"
-+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-+ (unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
-+ (set (match_operand:PTI 1 "indexed_or_indirect_operand" "=Z")
-+ (match_operand:PTI 2 "quad_int_reg_operand" "r"))]
-+ "TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)"
-+ "stqcx. %2,%y1"
-+ [(set_attr "type" "store_c")])
-+
- (define_expand "atomic_compare_and_swap<mode>"
-- [(match_operand:SI 0 "gpc_reg_operand" "") ;; bool out
-- (match_operand:INT1 1 "gpc_reg_operand" "") ;; val out
-- (match_operand:INT1 2 "memory_operand" "") ;; memory
-- (match_operand:INT1 3 "reg_or_short_operand" "") ;; expected
-- (match_operand:INT1 4 "gpc_reg_operand" "") ;; desired
-+ [(match_operand:SI 0 "int_reg_operand" "") ;; bool out
-+ (match_operand:AINT 1 "int_reg_operand" "") ;; val out
-+ (match_operand:AINT 2 "memory_operand" "") ;; memory
-+ (match_operand:AINT 3 "reg_or_short_operand" "") ;; expected
-+ (match_operand:AINT 4 "int_reg_operand" "") ;; desired
- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
- (match_operand:SI 6 "const_int_operand" "") ;; model succ
- (match_operand:SI 7 "const_int_operand" "")] ;; model fail
-@@ -209,9 +468,9 @@
- })
-
- (define_expand "atomic_exchange<mode>"
-- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output
-- (match_operand:INT1 1 "memory_operand" "") ;; memory
-- (match_operand:INT1 2 "gpc_reg_operand" "") ;; input
-+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output
-+ (match_operand:AINT 1 "memory_operand" "") ;; memory
-+ (match_operand:AINT 2 "int_reg_operand" "") ;; input
- (match_operand:SI 3 "const_int_operand" "")] ;; model
- ""
- {
-@@ -220,9 +479,9 @@
- })
-
- (define_expand "atomic_<fetchop_name><mode>"
-- [(match_operand:INT1 0 "memory_operand" "") ;; memory
-- (FETCHOP:INT1 (match_dup 0)
-- (match_operand:INT1 1 "<fetchop_pred>" "")) ;; operand
-+ [(match_operand:AINT 0 "memory_operand" "") ;; memory
-+ (FETCHOP:AINT (match_dup 0)
-+ (match_operand:AINT 1 "<fetchop_pred>" "")) ;; operand
- (match_operand:SI 2 "const_int_operand" "")] ;; model
- ""
- {
-@@ -232,8 +491,8 @@
- })
-
- (define_expand "atomic_nand<mode>"
-- [(match_operand:INT1 0 "memory_operand" "") ;; memory
-- (match_operand:INT1 1 "gpc_reg_operand" "") ;; operand
-+ [(match_operand:AINT 0 "memory_operand" "") ;; memory
-+ (match_operand:AINT 1 "int_reg_operand" "") ;; operand
- (match_operand:SI 2 "const_int_operand" "")] ;; model
- ""
- {
-@@ -243,10 +502,10 @@
- })
-
- (define_expand "atomic_fetch_<fetchop_name><mode>"
-- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output
-- (match_operand:INT1 1 "memory_operand" "") ;; memory
-- (FETCHOP:INT1 (match_dup 1)
-- (match_operand:INT1 2 "<fetchop_pred>" "")) ;; operand
-+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output
-+ (match_operand:AINT 1 "memory_operand" "") ;; memory
-+ (FETCHOP:AINT (match_dup 1)
-+ (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
- ""
- {
-@@ -256,9 +515,9 @@
- })
-
- (define_expand "atomic_fetch_nand<mode>"
-- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output
-- (match_operand:INT1 1 "memory_operand" "") ;; memory
-- (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand
-+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output
-+ (match_operand:AINT 1 "memory_operand" "") ;; memory
-+ (match_operand:AINT 2 "int_reg_operand" "") ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
- ""
- {
-@@ -268,10 +527,10 @@
- })
-
- (define_expand "atomic_<fetchop_name>_fetch<mode>"
-- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output
-- (match_operand:INT1 1 "memory_operand" "") ;; memory
-- (FETCHOP:INT1 (match_dup 1)
-- (match_operand:INT1 2 "<fetchop_pred>" "")) ;; operand
-+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output
-+ (match_operand:AINT 1 "memory_operand" "") ;; memory
-+ (FETCHOP:AINT (match_dup 1)
-+ (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
- ""
- {
-@@ -281,9 +540,9 @@
- })
-
- (define_expand "atomic_nand_fetch<mode>"
-- [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output
-- (match_operand:INT1 1 "memory_operand" "") ;; memory
-- (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand
-+ [(match_operand:AINT 0 "int_reg_operand" "") ;; output
-+ (match_operand:AINT 1 "memory_operand" "") ;; memory
-+ (match_operand:AINT 2 "int_reg_operand" "") ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
- ""
- {
-Index: gcc/config/rs6000/crypto.md
-===================================================================
---- a/src/gcc/config/rs6000/crypto.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/crypto.md (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,101 @@
-+;; Cryptographic instructions added in ISA 2.07
-+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
-+;; Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)
-+
-+;; This file is part of GCC.
-+
-+;; GCC is free software; you can redistribute it and/or modify it
-+;; under the terms of the GNU General Public License as published
-+;; by the Free Software Foundation; either version 3, or (at your
-+;; option) any later version.
-+
-+;; GCC is distributed in the hope that it will be useful, but WITHOUT
-+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-+;; License for more details.
-+
-+;; You should have received a copy of the GNU General Public License
-+;; along with GCC; see the file COPYING3. If not see
-+;; <http://www.gnu.org/licenses/>.
-+
-+(define_c_enum "unspec"
-+ [UNSPEC_VCIPHER
-+ UNSPEC_VNCIPHER
-+ UNSPEC_VCIPHERLAST
-+ UNSPEC_VNCIPHERLAST
-+ UNSPEC_VSBOX
-+ UNSPEC_VSHASIGMA
-+ UNSPEC_VPERMXOR
-+ UNSPEC_VPMSUM])
-+
-+;; Iterator for VPMSUM/VPERMXOR
-+(define_mode_iterator CR_mode [V16QI V8HI V4SI V2DI])
-+
-+(define_mode_attr CR_char [(V16QI "b")
-+ (V8HI "h")
-+ (V4SI "w")
-+ (V2DI "d")])
-+
-+;; Iterator for VSHASIGMAD/VSHASIGMAW
-+(define_mode_iterator CR_hash [V4SI V2DI])
-+
-+;; Iterator for the other crypto functions
-+(define_int_iterator CR_code [UNSPEC_VCIPHER
-+ UNSPEC_VNCIPHER
-+ UNSPEC_VCIPHERLAST
-+ UNSPEC_VNCIPHERLAST])
-+
-+(define_int_attr CR_insn [(UNSPEC_VCIPHER "vcipher")
-+ (UNSPEC_VNCIPHER "vncipher")
-+ (UNSPEC_VCIPHERLAST "vcipherlast")
-+ (UNSPEC_VNCIPHERLAST "vncipherlast")])
-+
-+;; 2 operand crypto instructions
-+(define_insn "crypto_<CR_insn>"
-+ [(set (match_operand:V2DI 0 "register_operand" "=v")
-+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
-+ (match_operand:V2DI 2 "register_operand" "v")]
-+ CR_code))]
-+ "TARGET_CRYPTO"
-+ "<CR_insn> %0,%1,%2"
-+ [(set_attr "type" "crypto")])
-+
-+(define_insn "crypto_vpmsum<CR_char>"
-+ [(set (match_operand:CR_mode 0 "register_operand" "=v")
-+ (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")
-+ (match_operand:CR_mode 2 "register_operand" "v")]
-+ UNSPEC_VPMSUM))]
-+ "TARGET_CRYPTO"
-+ "vpmsum<CR_char> %0,%1,%2"
-+ [(set_attr "type" "crypto")])
-+
-+;; 3 operand crypto instructions
-+(define_insn "crypto_vpermxor_<mode>"
-+ [(set (match_operand:CR_mode 0 "register_operand" "=v")
-+ (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")
-+ (match_operand:CR_mode 2 "register_operand" "v")
-+ (match_operand:CR_mode 3 "register_operand" "v")]
-+ UNSPEC_VPERMXOR))]
-+ "TARGET_CRYPTO"
-+ "vpermxor %0,%1,%2,%3"
-+ [(set_attr "type" "crypto")])
-+
-+;; 1 operand crypto instruction
-+(define_insn "crypto_vsbox"
-+ [(set (match_operand:V2DI 0 "register_operand" "=v")
-+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")]
-+ UNSPEC_VSBOX))]
-+ "TARGET_CRYPTO"
-+ "vsbox %0,%1"
-+ [(set_attr "type" "crypto")])
-+
-+;; Hash crypto instructions
-+(define_insn "crypto_vshasigma<CR_char>"
-+ [(set (match_operand:CR_hash 0 "register_operand" "=v")
-+ (unspec:CR_hash [(match_operand:CR_hash 1 "register_operand" "v")
-+ (match_operand:SI 2 "const_0_to_1_operand" "n")
-+ (match_operand:SI 3 "const_0_to_15_operand" "n")]
-+ UNSPEC_VSHASIGMA))]
-+ "TARGET_CRYPTO"
-+ "vshasigma<CR_char> %0,%1,%2,%3"
-+ [(set_attr "type" "crypto")])
-Index: gcc/config/rs6000/rs6000.md
-===================================================================
---- a/src/gcc/config/rs6000/rs6000.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000.md (.../branches/gcc-4_8-branch)
-@@ -25,10 +25,14 @@
- ;;
-
- (define_constants
-- [(STACK_POINTER_REGNUM 1)
-+ [(FIRST_GPR_REGNO 0)
-+ (STACK_POINTER_REGNUM 1)
- (TOC_REGNUM 2)
- (STATIC_CHAIN_REGNUM 11)
- (HARD_FRAME_POINTER_REGNUM 31)
-+ (LAST_GPR_REGNO 31)
-+ (FIRST_FPR_REGNO 32)
-+ (LAST_FPR_REGNO 63)
- (LR_REGNO 65)
- (CTR_REGNO 66)
- (ARG_POINTER_REGNUM 67)
-@@ -49,18 +53,9 @@
- (SPE_ACC_REGNO 111)
- (SPEFSCR_REGNO 112)
- (FRAME_POINTER_REGNUM 113)
--
-- ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
-- (TOC_SAVE_OFFSET_32BIT 20)
-- (TOC_SAVE_OFFSET_64BIT 40)
--
-- ; Function TOC offset in the AIX function descriptor.
-- (AIX_FUNC_DESC_TOC_32BIT 4)
-- (AIX_FUNC_DESC_TOC_64BIT 8)
--
-- ; Static chain offset in the AIX function descriptor.
-- (AIX_FUNC_DESC_SC_32BIT 8)
-- (AIX_FUNC_DESC_SC_64BIT 16)
-+ (TFHAR_REGNO 114)
-+ (TFIAR_REGNO 115)
-+ (TEXASR_REGNO 116)
- ])
-
- ;;
-@@ -123,6 +118,22 @@
- UNSPEC_LFIWZX
- UNSPEC_FCTIWUZ
- UNSPEC_GRP_END_NOP
-+ UNSPEC_P8V_FMRGOW
-+ UNSPEC_P8V_MTVSRWZ
-+ UNSPEC_P8V_RELOAD_FROM_GPR
-+ UNSPEC_P8V_MTVSRD
-+ UNSPEC_P8V_XXPERMDI
-+ UNSPEC_P8V_RELOAD_FROM_VSX
-+ UNSPEC_ADDG6S
-+ UNSPEC_CDTBCD
-+ UNSPEC_CBCDTD
-+ UNSPEC_DIVE
-+ UNSPEC_DIVEO
-+ UNSPEC_DIVEU
-+ UNSPEC_DIVEUO
-+ UNSPEC_UNPACK_128BIT
-+ UNSPEC_PACK_128BIT
-+ UNSPEC_LSQ
- ])
-
- ;;
-@@ -142,7 +153,7 @@
-
- ;; Define an insn type attribute. This is used in function unit delay
- ;; computations.
--(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
-+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"
- (const_string "integer"))
-
- ;; Define floating point instruction sub-types for use with Xfpu.md
-@@ -164,7 +175,7 @@
- ;; Processor type -- this attribute must exactly match the processor_type
- ;; enumeration in rs6000.h.
-
--(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
-+(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan,power8"
- (const (symbol_ref "rs6000_cpu_attr")))
-
-
-@@ -197,6 +208,7 @@
- (include "power5.md")
- (include "power6.md")
- (include "power7.md")
-+(include "power8.md")
- (include "cell.md")
- (include "xfpu.md")
- (include "a2.md")
-@@ -215,7 +227,7 @@
- (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
-
- ; Any supported integer mode.
--(define_mode_iterator INT [QI HI SI DI TI])
-+(define_mode_iterator INT [QI HI SI DI TI PTI])
-
- ; Any supported integer mode that fits in one register.
- (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
-@@ -223,6 +235,12 @@
- ; extend modes for DImode
- (define_mode_iterator QHSI [QI HI SI])
-
-+; QImode or HImode for small atomic ops
-+(define_mode_iterator QHI [QI HI])
-+
-+; HImode or SImode for sign extended fusion ops
-+(define_mode_iterator HSI [HI SI])
-+
- ; SImode or DImode, even if DImode doesn't fit in GPRs.
- (define_mode_iterator SDI [SI DI])
-
-@@ -230,6 +248,10 @@
- ; (one with a '.') will compare; and the size used for arithmetic carries.
- (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
-
-+; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
-+; PTImode is GPR only)
-+(define_mode_iterator TI2 [TI PTI])
-+
- ; Any hardware-supported floating-point mode
- (define_mode_iterator FP [
- (SF "TARGET_HARD_FLOAT
-@@ -253,6 +275,50 @@
- (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
- ])
-
-+; Floating point move iterators to combine binary and decimal moves
-+(define_mode_iterator FMOVE32 [SF SD])
-+(define_mode_iterator FMOVE64 [DF DD])
-+(define_mode_iterator FMOVE64X [DI DF DD])
-+(define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
-+ (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
-+
-+; Iterators for 128 bit types for direct move
-+(define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
-+ (V16QI "")
-+ (V8HI "")
-+ (V4SI "")
-+ (V4SF "")
-+ (V2DI "")
-+ (V2DF "")
-+ (V1TI "")])
-+
-+; Whether a floating point move is ok, don't allow SD without hardware FP
-+(define_mode_attr fmove_ok [(SF "")
-+ (DF "")
-+ (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
-+ (DD "")])
-+
-+; Convert REAL_VALUE to the appropriate bits
-+(define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
-+ (DF "REAL_VALUE_TO_TARGET_DOUBLE")
-+ (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
-+ (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
-+
-+; Definitions for load to 32-bit fpr register
-+(define_mode_attr f32_lr [(SF "f") (SD "wz")])
-+(define_mode_attr f32_lm [(SF "m") (SD "Z")])
-+(define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
-+(define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
-+
-+; Definitions for store from 32-bit fpr register
-+(define_mode_attr f32_sr [(SF "f") (SD "wx")])
-+(define_mode_attr f32_sm [(SF "m") (SD "Z")])
-+(define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
-+(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
-+
-+; Definitions for 32-bit fpr direct move
-+(define_mode_attr f32_dm [(SF "wn") (SD "wm")])
-+
- ; These modes do not fit in integer registers in 32-bit mode.
- ; but on e500v2, the gpr are 64 bit registers
- (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
-@@ -263,6 +329,25 @@
- ; Iterator for just SF/DF
- (define_mode_iterator SFDF [SF DF])
-
-+; SF/DF suffix for traditional floating instructions
-+(define_mode_attr Ftrad [(SF "s") (DF "")])
-+
-+; SF/DF suffix for VSX instructions
-+(define_mode_attr Fvsx [(SF "sp") (DF "dp")])
-+
-+; SF/DF constraint for arithmetic on traditional floating point registers
-+(define_mode_attr Ff [(SF "f") (DF "d")])
-+
-+; SF/DF constraint for arithmetic on VSX registers
-+(define_mode_attr Fv [(SF "wy") (DF "ws")])
-+
-+; s/d suffix for things like fp_addsub_s/fp_addsub_d
-+(define_mode_attr Fs [(SF "s") (DF "d")])
-+
-+; FRE/FRES support
-+(define_mode_attr Ffre [(SF "fres") (DF "fre")])
-+(define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
-+
- ; Conditional returns.
- (define_code_iterator any_return [return simple_return])
- (define_code_attr return_pred [(return "direct_return ()")
-@@ -271,7 +356,14 @@
-
- ; Various instructions that come in SI and DI forms.
- ; A generic w/d attribute, for things like cmpw/cmpd.
--(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
-+(define_mode_attr wd [(QI "b")
-+ (HI "h")
-+ (SI "w")
-+ (DI "d")
-+ (V16QI "b")
-+ (V8HI "h")
-+ (V4SI "w")
-+ (V2DI "d")])
-
- ; DImode bits
- (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
-@@ -297,6 +389,8 @@
-
- (define_mode_attr rreg [(SF "f")
- (DF "ws")
-+ (TF "f")
-+ (TD "f")
- (V4SF "wf")
- (V2DF "wd")])
-
-@@ -311,6 +405,87 @@
-
- (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
- (DF "TARGET_DOUBLE_FLOAT")])
-+
-+;; Mode iterator for logical operations on 128-bit types
-+(define_mode_iterator BOOL_128 [TI
-+ PTI
-+ (V16QI "TARGET_ALTIVEC")
-+ (V8HI "TARGET_ALTIVEC")
-+ (V4SI "TARGET_ALTIVEC")
-+ (V4SF "TARGET_ALTIVEC")
-+ (V2DI "TARGET_ALTIVEC")
-+ (V2DF "TARGET_ALTIVEC")
-+ (V1TI "TARGET_ALTIVEC")])
-+
-+;; For the GPRs we use 3 constraints for register outputs, two that are the
-+;; same as the output register, and a third where the output register is an
-+;; early clobber, so we don't have to deal with register overlaps. For the
-+;; vector types, we prefer to use the vector registers. For TI mode, allow
-+;; either.
-+
-+;; Mode attribute for boolean operation register constraints for output
-+(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
-+ (PTI "&r,r,r")
-+ (V16QI "wa,v,&?r,?r,?r")
-+ (V8HI "wa,v,&?r,?r,?r")
-+ (V4SI "wa,v,&?r,?r,?r")
-+ (V4SF "wa,v,&?r,?r,?r")
-+ (V2DI "wa,v,&?r,?r,?r")
-+ (V2DF "wa,v,&?r,?r,?r")
-+ (V1TI "wa,v,&?r,?r,?r")])
-+
-+;; Mode attribute for boolean operation register constraints for operand1
-+(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
-+ (PTI "r,0,r")
-+ (V16QI "wa,v,r,0,r")
-+ (V8HI "wa,v,r,0,r")
-+ (V4SI "wa,v,r,0,r")
-+ (V4SF "wa,v,r,0,r")
-+ (V2DI "wa,v,r,0,r")
-+ (V2DF "wa,v,r,0,r")
-+ (V1TI "wa,v,r,0,r")])
-+
-+;; Mode attribute for boolean operation register constraints for operand2
-+(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
-+ (PTI "r,r,0")
-+ (V16QI "wa,v,r,r,0")
-+ (V8HI "wa,v,r,r,0")
-+ (V4SI "wa,v,r,r,0")
-+ (V4SF "wa,v,r,r,0")
-+ (V2DI "wa,v,r,r,0")
-+ (V2DF "wa,v,r,r,0")
-+ (V1TI "wa,v,r,r,0")])
-+
-+;; Mode attribute for boolean operation register constraints for operand1
-+;; for one_cmpl. To simplify things, we repeat the constraint where 0
-+;; is used for operand1 or operand2
-+(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
-+ (PTI "r,0,0")
-+ (V16QI "wa,v,r,0,0")
-+ (V8HI "wa,v,r,0,0")
-+ (V4SI "wa,v,r,0,0")
-+ (V4SF "wa,v,r,0,0")
-+ (V2DI "wa,v,r,0,0")
-+ (V2DF "wa,v,r,0,0")
-+ (V1TI "wa,v,r,0,0")])
-+
-+;; Mode attribute for the clobber of CC0 for AND expansion.
-+;; For the 128-bit types, we never do AND immediate, but we need to
-+;; get the correct number of X's for the number of operands.
-+(define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
-+ (PTI "X,X,X")
-+ (V16QI "X,X,X,X,X")
-+ (V8HI "X,X,X,X,X")
-+ (V4SI "X,X,X,X,X")
-+ (V4SF "X,X,X,X,X")
-+ (V2DI "X,X,X,X,X")
-+ (V2DF "X,X,X,X,X")
-+ (V1TI "X,X,X,X,X")])
-+
-+;; Mode attribute to give the correct type for integer divides
-+(define_mode_attr idiv_ldiv [(SI "idiv")
-+ (DI "ldiv")])
-+
-
- ;; Start with fixed-point load and store insns. Here we put only the more
- ;; complex forms. Basic data transfer is done later.
-@@ -324,11 +499,19 @@
- (define_insn "*zero_extend<mode>di2_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
-- "TARGET_POWERPC64"
-+ "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
- "@
- l<wd>z%U1%X1 %0,%1
- rldicl %0,%1,0,<dbits>"
-- [(set_attr "type" "load,*")])
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (const_string "*")])])
-
- (define_insn "*zero_extend<mode>di2_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-@@ -382,6 +565,29 @@
- (const_int 0)))]
- "")
-
-+(define_insn "*zero_extendsidi2_lfiwzx"
-+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
-+ (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
-+ "TARGET_POWERPC64 && TARGET_LFIWZX"
-+ "@
-+ lwz%U1%X1 %0,%1
-+ rldicl %0,%1,0,32
-+ mtvsrwz %x0,%1
-+ lfiwzx %0,%y1
-+ lxsiwzx %x0,%y1"
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (const_string "*")
-+ (const_string "mffgpr")
-+ (const_string "fpload")
-+ (const_string "fpload")])])
-+
- (define_insn "extendqidi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
-@@ -454,7 +660,15 @@
- "@
- lha%U1%X1 %0,%1
- extsh %0,%1"
-- [(set_attr "type" "load_ext,exts")])
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ext_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ext_u")
-+ (const_string "load_ext")))
-+ (const_string "exts")])])
-
- (define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-@@ -521,16 +735,47 @@
- "TARGET_POWERPC64"
- "")
-
--(define_insn ""
-+(define_insn "*extendsidi2_lfiwax"
-+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
-+ (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))]
-+ "TARGET_POWERPC64 && TARGET_LFIWAX"
-+ "@
-+ lwa%U1%X1 %0,%1
-+ extsw %0,%1
-+ mtvsrwa %x0,%1
-+ lfiwax %0,%y1
-+ lxsiwax %x0,%y1"
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ext_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ext_u")
-+ (const_string "load_ext")))
-+ (const_string "exts")
-+ (const_string "mffgpr")
-+ (const_string "fpload")
-+ (const_string "fpload")])])
-+
-+(define_insn "*extendsidi2_nocell"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
-- "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
-+ "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
- "@
- lwa%U1%X1 %0,%1
- extsw %0,%1"
-- [(set_attr "type" "load_ext,exts")])
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ext_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ext_u")
-+ (const_string "load_ext")))
-+ (const_string "exts")])])
-
--(define_insn ""
-+(define_insn "*extendsidi2_nocell"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
-@@ -602,7 +847,15 @@
- "@
- lbz%U1%X1 %0,%1
- rlwinm %0,%1,0,0xff"
-- [(set_attr "type" "load,*")])
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (const_string "*")])])
-
- (define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-@@ -722,7 +975,15 @@
- "@
- lbz%U1%X1 %0,%1
- rlwinm %0,%1,0,0xff"
-- [(set_attr "type" "load,*")])
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (const_string "*")])])
-
- (define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-@@ -848,7 +1109,15 @@
- "@
- lhz%U1%X1 %0,%1
- rlwinm %0,%1,0,0xffff"
-- [(set_attr "type" "load,*")])
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (const_string "*")])])
-
- (define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-@@ -915,7 +1184,15 @@
- "@
- lha%U1%X1 %0,%1
- extsh %0,%1"
-- [(set_attr "type" "load_ext,exts")])
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ext_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ext_u")
-+ (const_string "load_ext")))
-+ (const_string "exts")])])
-
- (define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-@@ -1658,7 +1935,19 @@
- FAIL;
- })
-
--(define_insn "one_cmpl<mode>2"
-+(define_expand "one_cmpl<mode>2"
-+ [(set (match_operand:SDI 0 "gpc_reg_operand" "")
-+ (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
-+ ""
-+{
-+ if (<MODE>mode == DImode && !TARGET_POWERPC64)
-+ {
-+ rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
-+ DONE;
-+ }
-+})
-+
-+(define_insn "*one_cmpl<mode>2"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
- ""
-@@ -1935,7 +2224,9 @@
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
- "TARGET_CMPB && TARGET_POPCNTB"
-- "prty<wd> %0,%1")
-+ "prty<wd> %0,%1"
-+ [(set_attr "length" "4")
-+ (set_attr "type" "popcnt")])
-
- (define_expand "parity<mode>2"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
-@@ -2412,7 +2703,7 @@
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
-- ""
-+ "TARGET_32BIT"
- "@
- mullw. %3,%1,%2
- #"
-@@ -2425,7 +2716,7 @@
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
-- "reload_completed"
-+ "TARGET_32BIT && reload_completed"
- [(set (match_dup 3)
- (mult:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
-@@ -2440,7 +2731,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (mult:SI (match_dup 1) (match_dup 2)))]
-- ""
-+ "TARGET_32BIT"
- "@
- mullw. %0,%1,%2
- #"
-@@ -2454,7 +2745,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (mult:SI (match_dup 1) (match_dup 2)))]
-- "reload_completed"
-+ "TARGET_32BIT && reload_completed"
- [(set (match_dup 0)
- (mult:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
-@@ -2469,10 +2760,7 @@
- (match_operand:GPR 2 "gpc_reg_operand" "r")))]
- ""
- "div<wd>u %0,%1,%2"
-- [(set (attr "type")
-- (cond [(match_operand:SI 0 "" "")
-- (const_string "idiv")]
-- (const_string "ldiv")))])
-+ [(set_attr "type" "<idiv_ldiv>")])
-
-
- ;; For powers of two we can do srai/aze for divide and then adjust for
-@@ -2496,10 +2784,7 @@
- (match_operand:GPR 2 "gpc_reg_operand" "r")))]
- ""
- "div<wd> %0,%1,%2"
-- [(set (attr "type")
-- (cond [(match_operand:SI 0 "" "")
-- (const_string "idiv")]
-- (const_string "ldiv")))])
-+ [(set_attr "type" "<idiv_ldiv>")])
-
- (define_expand "mod<mode>3"
- [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
-@@ -3698,13 +3983,13 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotlsi3_internal7"
-+(define_insn "*rotlsi3_internal7le"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
-- ""
-+ "!BYTES_BIG_ENDIAN"
- "rlw%I2nm %0,%1,%h2,0xff"
- [(set (attr "cell_micro")
- (if_then_else (match_operand:SI 2 "const_int_operand" "")
-@@ -3711,7 +3996,20 @@
- (const_string "not")
- (const_string "always")))])
-
--(define_insn "*rotlsi3_internal8"
-+(define_insn "*rotlsi3_internal7be"
-+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-+ (zero_extend:SI
-+ (subreg:QI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-+ (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
-+ "BYTES_BIG_ENDIAN"
-+ "rlw%I2nm %0,%1,%h2,0xff"
-+ [(set (attr "cell_micro")
-+ (if_then_else (match_operand:SI 2 "const_int_operand" "")
-+ (const_string "not")
-+ (const_string "always")))])
-+
-+(define_insn "*rotlsi3_internal8le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:SI
- (subreg:QI
-@@ -3719,7 +4017,7 @@
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-- ""
-+ "!BYTES_BIG_ENDIAN"
- "@
- rlwnm. %3,%1,%2,0xff
- rlwinm. %3,%1,%h2,0xff
-@@ -3728,6 +4026,23 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotlsi3_internal8be"
-+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:SI
-+ (subreg:QI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
-+ (const_int 0)))
-+ (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-+ "BYTES_BIG_ENDIAN"
-+ "@
-+ rlwnm. %3,%1,%2,0xff
-+ rlwinm. %3,%1,%h2,0xff
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
-@@ -3736,7 +4051,7 @@
- (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
-- "reload_completed"
-+ "!BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:QI
- (rotate:SI (match_dup 1)
-@@ -3746,7 +4061,25 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotlsi3_internal9"
-+(define_split
-+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:SI
-+ (subreg:QI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-+ (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
-+ (const_int 0)))
-+ (clobber (match_scratch:SI 3 ""))]
-+ "BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 3)
-+ (zero_extend:SI (subreg:QI
-+ (rotate:SI (match_dup 1)
-+ (match_dup 2)) 3)))
-+ (set (match_dup 0)
-+ (compare:CC (match_dup 3)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*rotlsi3_internal9le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:SI
- (subreg:QI
-@@ -3755,7 +4088,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-- ""
-+ "!BYTES_BIG_ENDIAN"
- "@
- rlwnm. %0,%1,%2,0xff
- rlwinm. %0,%1,%h2,0xff
-@@ -3764,6 +4097,24 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotlsi3_internal9be"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:SI
-+ (subreg:QI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-+ (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
-+ "BYTES_BIG_ENDIAN"
-+ "@
-+ rlwnm. %0,%1,%2,0xff
-+ rlwinm. %0,%1,%h2,0xff
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
-@@ -3773,7 +4124,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-- "reload_completed"
-+ "!BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
-@@ -3781,20 +4132,48 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotlsi3_internal10"
-+(define_split
-+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:SI
-+ (subreg:QI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-+ (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "gpc_reg_operand" "")
-+ (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
-+ "BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 0)
-+ (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
-+ (set (match_dup 3)
-+ (compare:CC (match_dup 0)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*rotlsi3_internal10le"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
-- ""
-+ "!BYTES_BIG_ENDIAN"
- "@
- rlwnm %0,%1,%2,0xffff
- rlwinm %0,%1,%h2,0xffff"
- [(set_attr "type" "var_shift_rotate,integer")])
-
-+(define_insn "*rotlsi3_internal10be"
-+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-+ (zero_extend:SI
-+ (subreg:HI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-+ (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]
-+ "BYTES_BIG_ENDIAN"
-+ "@
-+ rlwnm %0,%1,%2,0xffff
-+ rlwinm %0,%1,%h2,0xffff"
-+ [(set_attr "type" "var_shift_rotate,integer")])
-
--(define_insn "*rotlsi3_internal11"
-+(define_insn "*rotlsi3_internal11le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:SI
- (subreg:HI
-@@ -3802,7 +4181,7 @@
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-- ""
-+ "!BYTES_BIG_ENDIAN"
- "@
- rlwnm. %3,%1,%2,0xffff
- rlwinm. %3,%1,%h2,0xffff
-@@ -3811,6 +4190,23 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotlsi3_internal11be"
-+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:SI
-+ (subreg:HI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
-+ (const_int 0)))
-+ (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-+ "BYTES_BIG_ENDIAN"
-+ "@
-+ rlwnm. %3,%1,%2,0xffff
-+ rlwinm. %3,%1,%h2,0xffff
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
-@@ -3819,7 +4215,7 @@
- (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
-- "reload_completed"
-+ "!BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:HI
- (rotate:SI (match_dup 1)
-@@ -3829,7 +4225,25 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotlsi3_internal12"
-+(define_split
-+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:SI
-+ (subreg:HI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-+ (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
-+ (const_int 0)))
-+ (clobber (match_scratch:SI 3 ""))]
-+ "BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 3)
-+ (zero_extend:SI (subreg:HI
-+ (rotate:SI (match_dup 1)
-+ (match_dup 2)) 2)))
-+ (set (match_dup 0)
-+ (compare:CC (match_dup 3)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*rotlsi3_internal12le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:SI
- (subreg:HI
-@@ -3838,7 +4252,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-- ""
-+ "!BYTES_BIG_ENDIAN"
- "@
- rlwnm. %0,%1,%2,0xffff
- rlwinm. %0,%1,%h2,0xffff
-@@ -3847,6 +4261,24 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotlsi3_internal12be"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:SI
-+ (subreg:HI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-+ (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
-+ "BYTES_BIG_ENDIAN"
-+ "@
-+ rlwnm. %0,%1,%2,0xffff
-+ rlwinm. %0,%1,%h2,0xffff
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
-@@ -3856,7 +4288,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-- "reload_completed"
-+ "!BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
-@@ -3864,6 +4296,23 @@
- (const_int 0)))]
- "")
-
-+(define_split
-+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:SI
-+ (subreg:HI
-+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-+ (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "gpc_reg_operand" "")
-+ (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
-+ "BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 0)
-+ (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
-+ (set (match_dup 3)
-+ (compare:CC (match_dup 0)
-+ (const_int 0)))]
-+ "")
-+
- (define_insn "ashlsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-@@ -4054,7 +4503,7 @@
- #
- #
- #"
-- [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,4,8,8,8")])
-
- (define_split
-@@ -4086,7 +4535,7 @@
- #
- #
- #"
-- [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,4,8,8,8")])
-
- (define_split
-@@ -4177,16 +4626,25 @@
- (const_int 0)))]
- "")
-
--(define_insn ""
-+(define_insn "*lshiftrt_internal1le"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "const_int_operand" "i")) 0)))]
-- "includes_rshift_p (operands[2], GEN_INT (255))"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "rlwinm %0,%1,%s2,0xff")
-
--(define_insn ""
-+(define_insn "*lshiftrt_internal1be"
-+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-+ (zero_extend:SI
-+ (subreg:QI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-+ (match_operand:SI 2 "const_int_operand" "i")) 3)))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
-+ "rlwinm %0,%1,%s2,0xff")
-+
-+(define_insn "*lshiftrt_internal2le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
-@@ -4195,7 +4653,7 @@
- (match_operand:SI 2 "const_int_operand" "i,i")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
-- "includes_rshift_p (operands[2], GEN_INT (255))"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "@
- rlwinm. %3,%1,%s2,0xff
- #"
-@@ -4202,6 +4660,22 @@
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,8")])
-
-+(define_insn "*lshiftrt_internal2be"
-+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-+ (compare:CC
-+ (zero_extend:SI
-+ (subreg:QI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-+ (match_operand:SI 2 "const_int_operand" "i,i")) 3))
-+ (const_int 0)))
-+ (clobber (match_scratch:SI 3 "=r,r"))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
-+ "@
-+ rlwinm. %3,%1,%s2,0xff
-+ #"
-+ [(set_attr "type" "delayed_compare")
-+ (set_attr "length" "4,8")])
-+
- (define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
-@@ -4211,7 +4685,7 @@
- (match_operand:SI 2 "const_int_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
-- "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:QI
- (lshiftrt:SI (match_dup 1)
-@@ -4221,7 +4695,26 @@
- (const_int 0)))]
- "")
-
--(define_insn ""
-+(define_split
-+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC
-+ (zero_extend:SI
-+ (subreg:QI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-+ (match_operand:SI 2 "const_int_operand" "")) 3))
-+ (const_int 0)))
-+ (clobber (match_scratch:SI 3 ""))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
-+ [(set (match_dup 3)
-+ (zero_extend:SI (subreg:QI
-+ (lshiftrt:SI (match_dup 1)
-+ (match_dup 2)) 3)))
-+ (set (match_dup 0)
-+ (compare:CC (match_dup 3)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*lshiftrt_internal3le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
-@@ -4231,7 +4724,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-- "includes_rshift_p (operands[2], GEN_INT (255))"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "@
- rlwinm. %0,%1,%s2,0xff
- #"
-@@ -4238,6 +4731,23 @@
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,8")])
-
-+(define_insn "*lshiftrt_internal3be"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-+ (compare:CC
-+ (zero_extend:SI
-+ (subreg:QI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-+ (match_operand:SI 2 "const_int_operand" "i,i")) 3))
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-+ (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
-+ "@
-+ rlwinm. %0,%1,%s2,0xff
-+ #"
-+ [(set_attr "type" "delayed_compare")
-+ (set_attr "length" "4,8")])
-+
- (define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
-@@ -4248,7 +4758,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-- "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
-@@ -4256,16 +4766,43 @@
- (const_int 0)))]
- "")
-
--(define_insn ""
-+(define_split
-+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC
-+ (zero_extend:SI
-+ (subreg:QI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-+ (match_operand:SI 2 "const_int_operand" "")) 3))
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "gpc_reg_operand" "")
-+ (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
-+ [(set (match_dup 0)
-+ (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
-+ (set (match_dup 3)
-+ (compare:CC (match_dup 0)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*lshiftrt_internal4le"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "const_int_operand" "i")) 0)))]
-- "includes_rshift_p (operands[2], GEN_INT (65535))"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "rlwinm %0,%1,%s2,0xffff")
-
--(define_insn ""
-+(define_insn "*lshiftrt_internal4be"
-+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-+ (zero_extend:SI
-+ (subreg:HI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-+ (match_operand:SI 2 "const_int_operand" "i")) 2)))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
-+ "rlwinm %0,%1,%s2,0xffff")
-+
-+(define_insn "*lshiftrt_internal5le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
-@@ -4274,7 +4811,7 @@
- (match_operand:SI 2 "const_int_operand" "i,i")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
-- "includes_rshift_p (operands[2], GEN_INT (65535))"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "@
- rlwinm. %3,%1,%s2,0xffff
- #"
-@@ -4281,6 +4818,22 @@
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,8")])
-
-+(define_insn "*lshiftrt_internal5be"
-+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-+ (compare:CC
-+ (zero_extend:SI
-+ (subreg:HI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-+ (match_operand:SI 2 "const_int_operand" "i,i")) 2))
-+ (const_int 0)))
-+ (clobber (match_scratch:SI 3 "=r,r"))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
-+ "@
-+ rlwinm. %3,%1,%s2,0xffff
-+ #"
-+ [(set_attr "type" "delayed_compare")
-+ (set_attr "length" "4,8")])
-+
- (define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
-@@ -4290,7 +4843,7 @@
- (match_operand:SI 2 "const_int_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
-- "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:HI
- (lshiftrt:SI (match_dup 1)
-@@ -4300,7 +4853,26 @@
- (const_int 0)))]
- "")
-
--(define_insn ""
-+(define_split
-+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC
-+ (zero_extend:SI
-+ (subreg:HI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-+ (match_operand:SI 2 "const_int_operand" "")) 2))
-+ (const_int 0)))
-+ (clobber (match_scratch:SI 3 ""))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
-+ [(set (match_dup 3)
-+ (zero_extend:SI (subreg:HI
-+ (lshiftrt:SI (match_dup 1)
-+ (match_dup 2)) 2)))
-+ (set (match_dup 0)
-+ (compare:CC (match_dup 3)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*lshiftrt_internal5le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
-@@ -4310,7 +4882,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-- "includes_rshift_p (operands[2], GEN_INT (65535))"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "@
- rlwinm. %0,%1,%s2,0xffff
- #"
-@@ -4317,6 +4889,23 @@
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,8")])
-
-+(define_insn "*lshiftrt_internal5be"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-+ (compare:CC
-+ (zero_extend:SI
-+ (subreg:HI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-+ (match_operand:SI 2 "const_int_operand" "i,i")) 2))
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-+ (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
-+ "@
-+ rlwinm. %0,%1,%s2,0xffff
-+ #"
-+ [(set_attr "type" "delayed_compare")
-+ (set_attr "length" "4,8")])
-+
- (define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
-@@ -4327,7 +4916,7 @@
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-- "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
-+ "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
-@@ -4335,6 +4924,24 @@
- (const_int 0)))]
- "")
-
-+(define_split
-+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC
-+ (zero_extend:SI
-+ (subreg:HI
-+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-+ (match_operand:SI 2 "const_int_operand" "")) 2))
-+ (const_int 0)))
-+ (set (match_operand:SI 0 "gpc_reg_operand" "")
-+ (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
-+ "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
-+ [(set (match_dup 0)
-+ (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
-+ (set (match_dup 3)
-+ (compare:CC (match_dup 0)
-+ (const_int 0)))]
-+ "")
-+
- (define_insn "ashrsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-@@ -4455,224 +5062,226 @@
- (const_int 0)))]
- "")
-
--;; Floating-point insns, excluding normal data motion.
--;;
--;; PowerPC has a full set of single-precision floating point instructions.
--;;
--;; For the POWER architecture, we pretend that we have both SFmode and
--;; DFmode insns, while, in fact, all fp insns are actually done in double.
--;; The only conversions we will do will be when storing to memory. In that
--;; case, we will use the "frsp" instruction before storing.
--;;
--;; Note that when we store into a single-precision memory location, we need to
--;; use the frsp insn first. If the register being stored isn't dead, we
--;; need a scratch register for the frsp. But this is difficult when the store
--;; is done by reload. It is not incorrect to do the frsp on the register in
--;; this case, we just lose precision that we would have otherwise gotten but
--;; is not guaranteed. Perhaps this should be tightened up at some point.
-+
-+;; Floating-point insns, excluding normal data motion. We combine the SF/DF
-+;; modes here, and also add in conditional vsx/power8-vector support to access
-+;; values in the traditional Altivec registers if the appropriate
-+;; -mupper-regs-{df,sf} option is enabled.
-
--(define_expand "extendsfdf2"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
-- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
-+(define_expand "abs<mode>2"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
-+ "TARGET_<MODE>_INSN"
- "")
-
--(define_insn_and_split "*extendsfdf2_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
-- (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
-+(define_insn "*abs<mode>2_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR"
- "@
-- #
-- fmr %0,%1
-- lfs%U1%X1 %0,%1"
-- "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
-- [(const_int 0)]
--{
-- emit_note (NOTE_INSN_DELETED);
-- DONE;
--}
-- [(set_attr "type" "fp,fp,fpload")])
-+ fabs %0,%1
-+ xsabsdp %x0,%x1"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_addsub_<Fs>")])
-
--(define_expand "truncdfsf2"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
-- "")
-+(define_insn "*nabs<mode>2_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (neg:SFDF
-+ (abs:SFDF
-+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fnabs %0,%1
-+ xsnabsdp %x0,%x1"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_addsub_<Fs>")])
-
--(define_insn "*truncdfsf2_fpr"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
-- "frsp %0,%1"
-- [(set_attr "type" "fp")])
--
--(define_expand "negsf2"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
-+(define_expand "neg<mode>2"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
-+ "TARGET_<MODE>_INSN"
- "")
-
--(define_insn "*negsf2"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fneg %0,%1"
-- [(set_attr "type" "fp")])
-+(define_insn "*neg<mode>2_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fneg %0,%1
-+ xsnegdp %x0,%x1"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_addsub_<Fs>")])
-
--(define_expand "abssf2"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
-+(define_expand "add<mode>3"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]
-+ "TARGET_<MODE>_INSN"
- "")
-
--(define_insn "*abssf2"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fabs %0,%1"
-- [(set_attr "type" "fp")])
-+(define_insn "*add<mode>3_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fadd<Ftrad> %0,%1,%2
-+ xsadd<Fvsx> %x0,%x1,%x2"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_addsub_<Fs>")])
-
--(define_insn ""
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fnabs %0,%1"
-- [(set_attr "type" "fp")])
--
--(define_expand "addsf3"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
-- (match_operand:SF 2 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
-+(define_expand "sub<mode>3"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]
-+ "TARGET_<MODE>_INSN"
- "")
-
--(define_insn ""
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-- (match_operand:SF 2 "gpc_reg_operand" "f")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fadds %0,%1,%2"
-+(define_insn "*sub<mode>3_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fsub<Ftrad> %0,%1,%2
-+ xssub<Fvsx> %x0,%x1,%x2"
- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_addsub_s")])
-+ (set_attr "fp_type" "fp_addsub_<Fs>")])
-
--(define_expand "subsf3"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
-- (match_operand:SF 2 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
-+(define_expand "mul<mode>3"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]
-+ "TARGET_<MODE>_INSN"
- "")
-
--(define_insn ""
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-- (match_operand:SF 2 "gpc_reg_operand" "f")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fsubs %0,%1,%2"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_addsub_s")])
-+(define_insn "*mul<mode>3_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fmul<Ftrad> %0,%1,%2
-+ xsmul<Fvsx> %x0,%x1,%x2"
-+ [(set_attr "type" "dmul")
-+ (set_attr "fp_type" "fp_mul_<Fs>")])
-
--(define_expand "mulsf3"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
-- (match_operand:SF 2 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
-+(define_expand "div<mode>3"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "")))]
-+ "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
- "")
-
--(define_insn ""
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-- (match_operand:SF 2 "gpc_reg_operand" "f")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fmuls %0,%1,%2"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_mul_s")])
-+(define_insn "*div<mode>3_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
-+ "@
-+ fdiv<Ftrad> %0,%1,%2
-+ xsdiv<Fvsx> %x0,%x1,%x2"
-+ [(set_attr "type" "<Fs>div")
-+ (set_attr "fp_type" "fp_div_<Fs>")])
-
--(define_expand "divsf3"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
-- (match_operand:SF 2 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
-- "")
-+(define_insn "sqrt<mode>2"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
-+ && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
-+ "@
-+ fsqrt<Ftrad> %0,%1
-+ xssqrt<Fvsx> %x0,%x1"
-+ [(set_attr "type" "<Fs>sqrt")
-+ (set_attr "fp_type" "fp_sqrt_<Fs>")])
-
--(define_insn ""
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-- (match_operand:SF 2 "gpc_reg_operand" "f")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS
-- && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
-- "fdivs %0,%1,%2"
-- [(set_attr "type" "sdiv")])
-+;; Floating point reciprocal approximation
-+(define_insn "fre<Fs>"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
-+ UNSPEC_FRES))]
-+ "TARGET_<FFRE>"
-+ "@
-+ fre<Ftrad> %0,%1
-+ xsre<Fvsx> %x0,%x1"
-+ [(set_attr "type" "fp")])
-
--(define_insn "fres"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
-- "TARGET_FRES"
-- "fres %0,%1"
-+(define_insn "*rsqrt<mode>2"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
-+ UNSPEC_RSQRT))]
-+ "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
-+ "@
-+ frsqrte<Ftrad> %0,%1
-+ xsrsqrte<Fvsx> %x0,%x1"
- [(set_attr "type" "fp")])
-
--; builtin fmaf support
--(define_insn "*fmasf4_fpr"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-- (match_operand:SF 2 "gpc_reg_operand" "f")
-- (match_operand:SF 3 "gpc_reg_operand" "f")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fmadds %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_s")])
-+;; Floating point comparisons
-+(define_insn "*cmp<mode>_fpr"
-+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
-+ (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fcmpu %0,%1,%2
-+ xscmpudp %0,%x1,%x2"
-+ [(set_attr "type" "fpcompare")])
-
--(define_insn "*fmssf4_fpr"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-- (match_operand:SF 2 "gpc_reg_operand" "f")
-- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fmsubs %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_s")])
-+;; Floating point conversions
-+(define_expand "extendsfdf2"
-+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
-+ (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
-+ "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
-+ "")
-
--(define_insn "*nfmasf4_fpr"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-- (match_operand:SF 2 "gpc_reg_operand" "f")
-- (match_operand:SF 3 "gpc_reg_operand" "f"))))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fnmadds %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_s")])
-+(define_insn_and_split "*extendsfdf2_fpr"
-+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
-+ (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
-+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
-+ "@
-+ #
-+ fmr %0,%1
-+ lfs%U1%X1 %0,%1
-+ #
-+ xxlor %x0,%x1,%x1
-+ lxsspx %x0,%y1"
-+ "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
-+ [(const_int 0)]
-+{
-+ emit_note (NOTE_INSN_DELETED);
-+ DONE;
-+}
-+ [(set_attr_alternative "type"
-+ [(const_string "fp")
-+ (const_string "fp")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_u")
-+ (const_string "fpload")))
-+ (const_string "fp")
-+ (const_string "vecsimple")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_u")
-+ (const_string "fpload")))])])
-
--(define_insn "*nfmssf4_fpr"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-- (match_operand:SF 2 "gpc_reg_operand" "f")
-- (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fnmsubs %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_s")])
--
--(define_expand "sqrtsf2"
-+(define_expand "truncdfsf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
-- "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
-- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
-- && !TARGET_SIMPLE_FPU"
-+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
-+ "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
- "")
-
--(define_insn ""
-+(define_insn "*truncdfsf2_fpr"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-- "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
-- && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
-- "fsqrts %0,%1"
-- [(set_attr "type" "ssqrt")])
--
--(define_insn "*rsqrtsf_internal1"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-- (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
-- UNSPEC_RSQRT))]
-- "TARGET_FRSQRTES"
-- "frsqrtes %0,%1"
-+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
-+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
-+ "frsp %0,%1"
- [(set_attr "type" "fp")])
-
- ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
-@@ -4742,12 +5351,14 @@
- ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
- ;; compiler from optimizing -0.0
- (define_insn "copysign<mode>3_fcpsgn"
-- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
-- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
-- (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
- UNSPEC_COPYSIGN))]
-- "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "fcpsgn %0,%2,%1"
-+ "TARGET_<MODE>_FPR && TARGET_CMPB"
-+ "@
-+ fcpsgn %0,%2,%1
-+ xscpsgn<Fvsx> %x0,%x2,%x1"
- [(set_attr "type" "fp")])
-
- ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
-@@ -4754,27 +5365,70 @@
- ;; fsel instruction and some auxiliary computations. Then we just have a
- ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
- ;; combine.
--(define_expand "smaxsf3"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
-- (match_operand:SF 2 "gpc_reg_operand" ""))
-- (match_dup 1)
-- (match_dup 2)))]
-- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
-- && TARGET_SINGLE_FLOAT && !flag_trapping_math"
-- "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
-+;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
-+;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
-+;; computations. Then we just have a single DEFINE_INSN for fsel and the
-+;; define_splits to make them if made by combine. On VSX machines we have the
-+;; min/max instructions.
-+;;
-+;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
-+;; to allow either DF/SF to use only traditional registers.
-
--(define_expand "sminsf3"
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
-- (match_operand:SF 2 "gpc_reg_operand" ""))
-- (match_dup 2)
-- (match_dup 1)))]
-- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
-- && TARGET_SINGLE_FLOAT && !flag_trapping_math"
-- "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
-+(define_expand "smax<mode>3"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-+ (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
-+ (match_operand:SFDF 2 "gpc_reg_operand" ""))
-+ (match_dup 1)
-+ (match_dup 2)))]
-+ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
-+{
-+ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
-+ DONE;
-+})
-
-+(define_insn "*smax<mode>3_vsx"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR && TARGET_VSX"
-+ "xsmaxdp %x0,%x1,%x2"
-+ [(set_attr "type" "fp")])
-+
-+(define_expand "smin<mode>3"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-+ (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
-+ (match_operand:SFDF 2 "gpc_reg_operand" ""))
-+ (match_dup 2)
-+ (match_dup 1)))]
-+ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
-+{
-+ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
-+ DONE;
-+})
-+
-+(define_insn "*smin<mode>3_vsx"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
-+ "TARGET_<MODE>_FPR && TARGET_VSX"
-+ "xsmindp %x0,%x1,%x2"
-+ [(set_attr "type" "fp")])
-+
- (define_split
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-+ (match_operator:SFDF 3 "min_max_operator"
-+ [(match_operand:SFDF 1 "gpc_reg_operand" "")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
-+ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
-+ && !TARGET_VSX"
-+ [(const_int 0)]
-+{
-+ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
-+ operands[2]);
-+ DONE;
-+})
-+
-+(define_split
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (match_operator:SF 3 "min_max_operator"
- [(match_operand:SF 1 "gpc_reg_operand" "")
-@@ -4904,208 +5558,9 @@
- "fsel %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
--(define_expand "negdf2"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
-- "")
--
--(define_insn "*negdf2_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
-- (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fneg %0,%1"
-- [(set_attr "type" "fp")])
--
--(define_expand "absdf2"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
-- "")
--
--(define_insn "*absdf2_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
-- (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fabs %0,%1"
-- [(set_attr "type" "fp")])
--
--(define_insn "*nabsdf2_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
-- (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fnabs %0,%1"
-- [(set_attr "type" "fp")])
--
--(define_expand "adddf3"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
-- (match_operand:DF 2 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
-- "")
--
--(define_insn "*adddf3_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
-- (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
-- (match_operand:DF 2 "gpc_reg_operand" "d")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fadd %0,%1,%2"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_addsub_d")])
--
--(define_expand "subdf3"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
-- (match_operand:DF 2 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
-- "")
--
--(define_insn "*subdf3_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
-- (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
-- (match_operand:DF 2 "gpc_reg_operand" "d")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fsub %0,%1,%2"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_addsub_d")])
--
--(define_expand "muldf3"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
-- (match_operand:DF 2 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
-- "")
--
--(define_insn "*muldf3_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
-- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
-- (match_operand:DF 2 "gpc_reg_operand" "d")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fmul %0,%1,%2"
-- [(set_attr "type" "dmul")
-- (set_attr "fp_type" "fp_mul_d")])
--
--(define_expand "divdf3"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
-- (match_operand:DF 2 "gpc_reg_operand" "")))]
-- "TARGET_HARD_FLOAT
-- && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
-- && !TARGET_SIMPLE_FPU"
-- "")
--
--(define_insn "*divdf3_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
-- (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
-- (match_operand:DF 2 "gpc_reg_operand" "d")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
-- && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fdiv %0,%1,%2"
-- [(set_attr "type" "ddiv")])
--
--(define_insn "*fred_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
-- "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fre %0,%1"
-- [(set_attr "type" "fp")])
--
--(define_insn "*rsqrtdf_internal1"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
-- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
-- UNSPEC_RSQRT))]
-- "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
-- "frsqrte %0,%1"
-- [(set_attr "type" "fp")])
--
--; builtin fma support
--(define_insn "*fmadf4_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-- (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
-- (match_operand:DF 2 "gpc_reg_operand" "f")
-- (match_operand:DF 3 "gpc_reg_operand" "f")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && VECTOR_UNIT_NONE_P (DFmode)"
-- "fmadd %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_d")])
--
--(define_insn "*fmsdf4_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-- (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
-- (match_operand:DF 2 "gpc_reg_operand" "f")
-- (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && VECTOR_UNIT_NONE_P (DFmode)"
-- "fmsub %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_d")])
--
--(define_insn "*nfmadf4_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-- (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
-- (match_operand:DF 2 "gpc_reg_operand" "f")
-- (match_operand:DF 3 "gpc_reg_operand" "f"))))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && VECTOR_UNIT_NONE_P (DFmode)"
-- "fnmadd %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_d")])
--
--(define_insn "*nfmsdf4_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-- (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
-- (match_operand:DF 2 "gpc_reg_operand" "f")
-- (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && VECTOR_UNIT_NONE_P (DFmode)"
-- "fnmsub %0,%1,%2,%3"
-- [(set_attr "type" "fp")
-- (set_attr "fp_type" "fp_maddsub_d")])
--
--(define_expand "sqrtdf2"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
-- "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
-- "")
--
--(define_insn "*sqrtdf2_fpr"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
-- (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
-- "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fsqrt %0,%1"
-- [(set_attr "type" "dsqrt")])
--
- ;; The conditional move instructions allow us to perform max and min
- ;; operations even when
-
--(define_expand "smaxdf3"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
-- (match_operand:DF 2 "gpc_reg_operand" ""))
-- (match_dup 1)
-- (match_dup 2)))]
-- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !flag_trapping_math"
-- "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
--
--(define_expand "smindf3"
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
-- (match_operand:DF 2 "gpc_reg_operand" ""))
-- (match_dup 2)
-- (match_dup 1)))]
-- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !flag_trapping_math"
-- "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
--
- (define_split
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (match_operator:DF 3 "min_max_operator"
-@@ -5159,12 +5614,15 @@
- ; We don't define lfiwax/lfiwzx with the normal definition, because we
- ; don't want to support putting SImode in FPR registers.
- (define_insn "lfiwax"
-- [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
-- (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
-+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
-+ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
- UNSPEC_LFIWAX))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
-- "lfiwax %0,%y1"
-- [(set_attr "type" "fpload")])
-+ "@
-+ lfiwax %0,%y1
-+ lxsiwax %x0,%y1
-+ mtvsrwa %x0,%1"
-+ [(set_attr "type" "fpload,fpload,mffgpr")])
-
- ; This split must be run before register allocation because it allocates the
- ; memory slot that is needed to move values to/from the FPR. We don't allocate
-@@ -5186,7 +5644,8 @@
- rtx src = operands[1];
- rtx tmp;
-
-- if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
-+ if (!MEM_P (src) && TARGET_POWERPC64
-+ && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
- tmp = convert_to_mode (DImode, src, false);
- else
- {
-@@ -5235,12 +5694,15 @@
- (set_attr "type" "fpload")])
-
- (define_insn "lfiwzx"
-- [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
-- (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
-+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
-+ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
- UNSPEC_LFIWZX))]
- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
-- "lfiwzx %0,%y1"
-- [(set_attr "type" "fpload")])
-+ "@
-+ lfiwzx %0,%y1
-+ lxsiwzx %x0,%y1
-+ mtvsrwz %x0,%1"
-+ [(set_attr "type" "fpload,fpload,mftgpr")])
-
- (define_insn_and_split "floatunssi<mode>2_lfiwzx"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
-@@ -5257,7 +5719,8 @@
- rtx src = operands[1];
- rtx tmp;
-
-- if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
-+ if (!MEM_P (src) && TARGET_POWERPC64
-+ && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
- tmp = convert_to_mode (DImode, src, true);
- else
- {
-@@ -5548,7 +6011,7 @@
- emit_insn (gen_stfiwx (dest, tmp));
- DONE;
- }
-- else if (TARGET_MFPGPR && TARGET_POWERPC64)
-+ else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
- {
- dest = gen_lowpart (DImode, dest);
- emit_move_insn (dest, tmp);
-@@ -5642,7 +6105,7 @@
- emit_insn (gen_stfiwx (dest, tmp));
- DONE;
- }
-- else if (TARGET_MFPGPR && TARGET_POWERPC64)
-+ else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
- {
- dest = gen_lowpart (DImode, dest);
- emit_move_insn (dest, tmp);
-@@ -5781,66 +6244,52 @@
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
- (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
- UNSPEC_FCTID))]
-- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
-+ "TARGET_<MODE>_FPR && TARGET_FPRND"
- "fctid %0,%1"
- [(set_attr "type" "fp")])
-
--(define_expand "btrunc<mode>2"
-- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
-+(define_insn "btrunc<mode>2"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
- UNSPEC_FRIZ))]
-- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
-- "")
-+ "TARGET_<MODE>_FPR && TARGET_FPRND"
-+ "@
-+ friz %0,%1
-+ xsrdpiz %x0,%x1"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_addsub_<Fs>")])
-
--(define_insn "*btrunc<mode>2_fpr"
-- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
-- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
-- UNSPEC_FRIZ))]
-- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
-- && !VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "friz %0,%1"
-- [(set_attr "type" "fp")])
--
--(define_expand "ceil<mode>2"
-- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
-+(define_insn "ceil<mode>2"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
- UNSPEC_FRIP))]
-- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
-- "")
-+ "TARGET_<MODE>_FPR && TARGET_FPRND"
-+ "@
-+ frip %0,%1
-+ xsrdpip %x0,%x1"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_addsub_<Fs>")])
-
--(define_insn "*ceil<mode>2_fpr"
-- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
-- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
-- UNSPEC_FRIP))]
-- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
-- && !VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "frip %0,%1"
-- [(set_attr "type" "fp")])
--
--(define_expand "floor<mode>2"
-- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
-- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
-+(define_insn "floor<mode>2"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
- UNSPEC_FRIM))]
-- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
-- "")
-+ "TARGET_<MODE>_FPR && TARGET_FPRND"
-+ "@
-+ frim %0,%1
-+ xsrdpim %x0,%x1"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_addsub_<Fs>")])
-
--(define_insn "*floor<mode>2_fpr"
-- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
-- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
-- UNSPEC_FRIM))]
-- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
-- && !VECTOR_UNIT_VSX_P (<MODE>mode)"
-- "frim %0,%1"
-- [(set_attr "type" "fp")])
--
- ;; No VSX equivalent to frin
- (define_insn "round<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
- UNSPEC_FRIN))]
-- "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
-+ "TARGET_<MODE>_FPR && TARGET_FPRND"
- "frin %0,%1"
-- [(set_attr "type" "fp")])
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_addsub_<Fs>")])
-
- ; An UNSPEC is used so we don't have to support SImode in FP registers.
- (define_insn "stfiwx"
-@@ -6084,6 +6533,49 @@
- [(set_attr "length" "8")
- (set_attr "type" "fpload")])
-
-+;; Define the TImode operations that can be done in a small number
-+;; of instructions. The & constraints are to prevent the register
-+;; allocator from allocating registers that overlap with the inputs
-+;; (for example, having an input in 7,8 and an output in 6,7). We
-+;; also allow for the output being the same as one of the inputs.
-+
-+(define_insn "addti3"
-+ [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
-+ (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
-+ (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
-+ "TARGET_64BIT"
-+{
-+ if (WORDS_BIG_ENDIAN)
-+ return (GET_CODE (operands[2])) != CONST_INT
-+ ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
-+ : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
-+ else
-+ return (GET_CODE (operands[2])) != CONST_INT
-+ ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
-+ : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
-+}
-+ [(set_attr "type" "two")
-+ (set_attr "length" "8")])
-+
-+(define_insn "subti3"
-+ [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
-+ (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
-+ (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
-+ "TARGET_64BIT"
-+{
-+ if (WORDS_BIG_ENDIAN)
-+ return (GET_CODE (operands[1]) != CONST_INT)
-+ ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
-+ : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
-+ else
-+ return (GET_CODE (operands[1]) != CONST_INT)
-+ ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
-+ : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
-+}
-+ [(set_attr "type" "two")
-+ (set_attr "length" "8")])
-+
-+
- ;; Define the DImode operations that can be done in a small number
- ;; of instructions. The & constraints are to prevent the register
- ;; allocator from allocating registers that overlap with the inputs
-@@ -6260,11 +6752,11 @@
- [(set_attr "type" "two,three")
- (set_attr "length" "8,12")])
-
--(define_insn "*ashrdisi3_noppc64"
-+(define_insn "*ashrdisi3_noppc64be"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (const_int 32)) 4))]
-- "TARGET_32BIT && !TARGET_POWERPC64"
-+ "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
- "*
- {
- if (REGNO (operands[0]) == REGNO (operands[1]))
-@@ -6551,19 +7043,31 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotldi3_internal7"
-+(define_insn "*rotldi3_internal7le"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
-- "TARGET_POWERPC64"
-+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
- "@
- rldcl %0,%1,%2,56
- rldicl %0,%1,%H2,56"
- [(set_attr "type" "var_shift_rotate,integer")])
-
--(define_insn "*rotldi3_internal8"
-+(define_insn "*rotldi3_internal7be"
-+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-+ (zero_extend:DI
-+ (subreg:QI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-+ (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]
-+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
-+ "@
-+ rldcl %0,%1,%2,56
-+ rldicl %0,%1,%H2,56"
-+ [(set_attr "type" "var_shift_rotate,integer")])
-+
-+(define_insn "*rotldi3_internal8le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
-@@ -6571,7 +7075,7 @@
- (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-- "TARGET_64BIT"
-+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rldcl. %3,%1,%2,56
- rldicl. %3,%1,%H2,56
-@@ -6580,6 +7084,23 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotldi3_internal8be"
-+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:DI
-+ (subreg:QI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
-+ (const_int 0)))
-+ (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
-+ "@
-+ rldcl. %3,%1,%2,56
-+ rldicl. %3,%1,%H2,56
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
-@@ -6588,7 +7109,7 @@
- (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
-- "TARGET_POWERPC64 && reload_completed"
-+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:QI
- (rotate:DI (match_dup 1)
-@@ -6598,7 +7119,25 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotldi3_internal9"
-+(define_split
-+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:DI
-+ (subreg:QI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-+ (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
-+ (const_int 0)))
-+ (clobber (match_scratch:DI 3 ""))]
-+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 3)
-+ (zero_extend:DI (subreg:QI
-+ (rotate:DI (match_dup 1)
-+ (match_dup 2)) 7)))
-+ (set (match_dup 0)
-+ (compare:CC (match_dup 3)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*rotldi3_internal9le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
-@@ -6607,7 +7146,7 @@
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-- "TARGET_64BIT"
-+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rldcl. %0,%1,%2,56
- rldicl. %0,%1,%H2,56
-@@ -6616,6 +7155,24 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotldi3_internal9be"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:DI
-+ (subreg:QI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
-+ (const_int 0)))
-+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
-+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
-+ "@
-+ rldcl. %0,%1,%2,56
-+ rldicl. %0,%1,%H2,56
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
-@@ -6625,7 +7182,7 @@
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-- "TARGET_POWERPC64 && reload_completed"
-+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
-@@ -6633,19 +7190,48 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotldi3_internal10"
-+(define_split
-+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:DI
-+ (subreg:QI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-+ (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
-+ (const_int 0)))
-+ (set (match_operand:DI 0 "gpc_reg_operand" "")
-+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
-+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 0)
-+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
-+ (set (match_dup 3)
-+ (compare:CC (match_dup 0)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*rotldi3_internal10le"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
-- "TARGET_POWERPC64"
-+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
- "@
- rldcl %0,%1,%2,48
- rldicl %0,%1,%H2,48"
- [(set_attr "type" "var_shift_rotate,integer")])
-
--(define_insn "*rotldi3_internal11"
-+(define_insn "*rotldi3_internal10be"
-+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-+ (zero_extend:DI
-+ (subreg:HI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-+ (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]
-+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
-+ "@
-+ rldcl %0,%1,%2,48
-+ rldicl %0,%1,%H2,48"
-+ [(set_attr "type" "var_shift_rotate,integer")])
-+
-+(define_insn "*rotldi3_internal11le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
-@@ -6653,7 +7239,7 @@
- (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-- "TARGET_64BIT"
-+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rldcl. %3,%1,%2,48
- rldicl. %3,%1,%H2,48
-@@ -6662,6 +7248,23 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotldi3_internal11be"
-+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:DI
-+ (subreg:HI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
-+ (const_int 0)))
-+ (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
-+ "@
-+ rldcl. %3,%1,%2,48
-+ rldicl. %3,%1,%H2,48
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
-@@ -6670,7 +7273,7 @@
- (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
-- "TARGET_POWERPC64 && reload_completed"
-+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:HI
- (rotate:DI (match_dup 1)
-@@ -6680,7 +7283,25 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotldi3_internal12"
-+(define_split
-+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:DI
-+ (subreg:HI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-+ (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
-+ (const_int 0)))
-+ (clobber (match_scratch:DI 3 ""))]
-+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 3)
-+ (zero_extend:DI (subreg:HI
-+ (rotate:DI (match_dup 1)
-+ (match_dup 2)) 6)))
-+ (set (match_dup 0)
-+ (compare:CC (match_dup 3)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*rotldi3_internal12le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
-@@ -6689,7 +7310,7 @@
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-- "TARGET_64BIT"
-+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rldcl. %0,%1,%2,48
- rldicl. %0,%1,%H2,48
-@@ -6698,6 +7319,24 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotldi3_internal12be"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:DI
-+ (subreg:HI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
-+ (const_int 0)))
-+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
-+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
-+ "@
-+ rldcl. %0,%1,%2,48
-+ rldicl. %0,%1,%H2,48
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
-@@ -6707,7 +7346,7 @@
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-- "TARGET_POWERPC64 && reload_completed"
-+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
-@@ -6715,19 +7354,48 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotldi3_internal13"
-+(define_split
-+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:DI
-+ (subreg:HI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-+ (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
-+ (const_int 0)))
-+ (set (match_operand:DI 0 "gpc_reg_operand" "")
-+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
-+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 0)
-+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
-+ (set (match_dup 3)
-+ (compare:CC (match_dup 0)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*rotldi3_internal13le"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
-- "TARGET_POWERPC64"
-+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
- "@
- rldcl %0,%1,%2,32
- rldicl %0,%1,%H2,32"
- [(set_attr "type" "var_shift_rotate,integer")])
-
--(define_insn "*rotldi3_internal14"
-+(define_insn "*rotldi3_internal13be"
-+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-+ (zero_extend:DI
-+ (subreg:SI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-+ (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]
-+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
-+ "@
-+ rldcl %0,%1,%2,32
-+ rldicl %0,%1,%H2,32"
-+ [(set_attr "type" "var_shift_rotate,integer")])
-+
-+(define_insn "*rotldi3_internal14le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:DI
- (subreg:SI
-@@ -6735,7 +7403,7 @@
- (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-- "TARGET_64BIT"
-+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rldcl. %3,%1,%2,32
- rldicl. %3,%1,%H2,32
-@@ -6744,6 +7412,23 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotldi3_internal14be"
-+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:DI
-+ (subreg:SI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
-+ (const_int 0)))
-+ (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
-+ "@
-+ rldcl. %3,%1,%2,32
-+ rldicl. %3,%1,%H2,32
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
-@@ -6752,7 +7437,7 @@
- (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
-- "TARGET_POWERPC64 && reload_completed"
-+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:SI
- (rotate:DI (match_dup 1)
-@@ -6762,7 +7447,25 @@
- (const_int 0)))]
- "")
-
--(define_insn "*rotldi3_internal15"
-+(define_split
-+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:DI
-+ (subreg:SI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-+ (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
-+ (const_int 0)))
-+ (clobber (match_scratch:DI 3 ""))]
-+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 3)
-+ (zero_extend:DI (subreg:SI
-+ (rotate:DI (match_dup 1)
-+ (match_dup 2)) 4)))
-+ (set (match_dup 0)
-+ (compare:CC (match_dup 3)
-+ (const_int 0)))]
-+ "")
-+
-+(define_insn "*rotldi3_internal15le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (zero_extend:DI
- (subreg:SI
-@@ -6771,7 +7474,7 @@
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-- "TARGET_64BIT"
-+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rldcl. %0,%1,%2,32
- rldicl. %0,%1,%H2,32
-@@ -6780,6 +7483,24 @@
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-+(define_insn "*rotldi3_internal15be"
-+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-+ (compare:CC (zero_extend:DI
-+ (subreg:SI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-+ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
-+ (const_int 0)))
-+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
-+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
-+ "@
-+ rldcl. %0,%1,%2,32
-+ rldicl. %0,%1,%H2,32
-+ #
-+ #"
-+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-+ (set_attr "length" "4,4,8,8")])
-+
- (define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
-@@ -6789,7 +7510,7 @@
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-- "TARGET_POWERPC64 && reload_completed"
-+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
-@@ -6797,6 +7518,23 @@
- (const_int 0)))]
- "")
-
-+(define_split
-+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-+ (compare:CC (zero_extend:DI
-+ (subreg:SI
-+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-+ (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
-+ (const_int 0)))
-+ (set (match_operand:DI 0 "gpc_reg_operand" "")
-+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
-+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
-+ [(set (match_dup 0)
-+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
-+ (set (match_dup 3)
-+ (compare:CC (match_dup 0)
-+ (const_int 0)))]
-+ "")
-+
- (define_expand "ashldi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
-@@ -7195,10 +7933,19 @@
- [(parallel
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
-- (match_operand:DI 2 "and64_2_operand" "")))
-+ (match_operand:DI 2 "reg_or_cint_operand" "")))
- (clobber (match_scratch:CC 3 ""))])]
-- "TARGET_POWERPC64"
-- "")
-+ ""
-+{
-+ if (!TARGET_POWERPC64)
-+ {
-+ rtx cc = gen_rtx_SCRATCH (CCmode);
-+ rs6000_split_logical (operands, AND, false, false, false, cc);
-+ DONE;
-+ }
-+ else if (!and64_2_operand (operands[2], DImode))
-+ operands[2] = force_reg (DImode, operands[2]);
-+})
-
- (define_insn "anddi3_mc"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
-@@ -7379,12 +8126,18 @@
- (define_expand "iordi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
-- (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
-- "TARGET_POWERPC64"
-- "
-+ (match_operand:DI 2 "reg_or_cint_operand" "")))]
-+ ""
- {
-- if (non_logical_cint_operand (operands[2], DImode))
-+ if (!TARGET_POWERPC64)
- {
-+ rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
-+ DONE;
-+ }
-+ else if (!reg_or_logical_cint_operand (operands[2], DImode))
-+ operands[2] = force_reg (DImode, operands[2]);
-+ else if (non_logical_cint_operand (operands[2], DImode))
-+ {
- HOST_WIDE_INT value;
- rtx tmp = ((!can_create_pseudo_p ()
- || rtx_equal_p (operands[0], operands[1]))
-@@ -7408,15 +8161,21 @@
- emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
- DONE;
- }
--}")
-+})
-
- (define_expand "xordi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
-- (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
-- "TARGET_POWERPC64"
-- "
-+ (match_operand:DI 2 "reg_or_cint_operand" "")))]
-+ ""
- {
-+ if (!TARGET_POWERPC64)
-+ {
-+ rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
-+ DONE;
-+ }
-+ else if (!reg_or_logical_cint_operand (operands[2], DImode))
-+ operands[2] = force_reg (DImode, operands[2]);
- if (non_logical_cint_operand (operands[2], DImode))
- {
- HOST_WIDE_INT value;
-@@ -7442,7 +8201,7 @@
- emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
- DONE;
- }
--}")
-+})
-
- (define_insn "*booldi3_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
-@@ -7678,7 +8437,385 @@
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-+
-+;; Eqv operation.
-+(define_insn "*eqv<mode>3"
-+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-+ (not:GPR
-+ (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-+ (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
-+ ""
-+ "eqv %0,%1,%2"
-+ [(set_attr "type" "integer")
-+ (set_attr "length" "4")])
-+
-
-+;; 128-bit logical operations expanders
-+
-+(define_expand "and<mode>3"
-+ [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
-+ (and:BOOL_128
-+ (match_operand:BOOL_128 1 "vlogical_operand" "")
-+ (match_operand:BOOL_128 2 "vlogical_operand" "")))
-+ (clobber (match_scratch:CC 3 ""))])]
-+ ""
-+ "")
-+
-+(define_expand "ior<mode>3"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
-+ (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
-+ (match_operand:BOOL_128 2 "vlogical_operand" "")))]
-+ ""
-+ "")
-+
-+(define_expand "xor<mode>3"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
-+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
-+ (match_operand:BOOL_128 2 "vlogical_operand" "")))]
-+ ""
-+ "")
-+
-+(define_expand "one_cmpl<mode>2"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
-+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
-+ ""
-+ "")
-+
-+(define_expand "nor<mode>3"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
-+ (and:BOOL_128
-+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
-+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
-+ ""
-+ "")
-+
-+(define_expand "andc<mode>3"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
-+ (and:BOOL_128
-+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
-+ (match_operand:BOOL_128 1 "vlogical_operand" "")))]
-+ ""
-+ "")
-+
-+;; Power8 vector logical instructions.
-+(define_expand "eqv<mode>3"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
-+ (not:BOOL_128
-+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
-+ (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
-+ "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
-+ "")
-+
-+;; Rewrite nand into canonical form
-+(define_expand "nand<mode>3"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
-+ (ior:BOOL_128
-+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
-+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
-+ "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
-+ "")
-+
-+;; The canonical form is to have the negated element first, so we need to
-+;; reverse arguments.
-+(define_expand "orc<mode>3"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
-+ (ior:BOOL_128
-+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
-+ (match_operand:BOOL_128 1 "vlogical_operand" "")))]
-+ "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
-+ "")
-+
-+;; 128-bit logical operations insns and split operations
-+(define_insn_and_split "*and<mode>3_internal"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
-+ (and:BOOL_128
-+ (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
-+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))
-+ (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]
-+ ""
-+{
-+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
-+ return "xxland %x0,%x1,%x2";
-+
-+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
-+ return "vand %0,%1,%2";
-+
-+ return "#";
-+}
-+ "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
-+ [(const_int 0)]
-+{
-+ rs6000_split_logical (operands, AND, false, false, false, operands[3]);
-+ DONE;
-+}
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "vecsimple")
-+ (const_string "integer")))
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "4")
-+ (if_then_else
-+ (match_test "TARGET_POWERPC64")
-+ (const_string "8")
-+ (const_string "16"))))])
-+
-+;; 128-bit IOR/XOR
-+(define_insn_and_split "*bool<mode>3_internal"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
-+ (match_operator:BOOL_128 3 "boolean_or_operator"
-+ [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
-+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
-+ ""
-+{
-+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
-+ return "xxl%q3 %x0,%x1,%x2";
-+
-+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
-+ return "v%q3 %0,%1,%2";
-+
-+ return "#";
-+}
-+ "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
-+ [(const_int 0)]
-+{
-+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,
-+ NULL_RTX);
-+ DONE;
-+}
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "vecsimple")
-+ (const_string "integer")))
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "4")
-+ (if_then_else
-+ (match_test "TARGET_POWERPC64")
-+ (const_string "8")
-+ (const_string "16"))))])
-+
-+;; 128-bit ANDC/ORC
-+(define_insn_and_split "*boolc<mode>3_internal1"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
-+ (match_operator:BOOL_128 3 "boolean_operator"
-+ [(not:BOOL_128
-+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
-+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
-+ "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
-+{
-+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
-+ return "xxl%q3 %x0,%x1,%x2";
-+
-+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
-+ return "v%q3 %0,%1,%2";
-+
-+ return "#";
-+}
-+ "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
-+ && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
-+ [(const_int 0)]
-+{
-+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
-+ NULL_RTX);
-+ DONE;
-+}
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "vecsimple")
-+ (const_string "integer")))
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "4")
-+ (if_then_else
-+ (match_test "TARGET_POWERPC64")
-+ (const_string "8")
-+ (const_string "16"))))])
-+
-+(define_insn_and_split "*boolc<mode>3_internal2"
-+ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
-+ (match_operator:TI2 3 "boolean_operator"
-+ [(not:TI2
-+ (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
-+ (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
-+ "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
-+ "#"
-+ "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
-+ [(const_int 0)]
-+{
-+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
-+ NULL_RTX);
-+ DONE;
-+}
-+ [(set_attr "type" "integer")
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "TARGET_POWERPC64")
-+ (const_string "8")
-+ (const_string "16")))])
-+
-+;; 128-bit NAND/NOR
-+(define_insn_and_split "*boolcc<mode>3_internal1"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
-+ (match_operator:BOOL_128 3 "boolean_operator"
-+ [(not:BOOL_128
-+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
-+ (not:BOOL_128
-+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
-+ "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
-+{
-+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
-+ return "xxl%q3 %x0,%x1,%x2";
-+
-+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
-+ return "v%q3 %0,%1,%2";
-+
-+ return "#";
-+}
-+ "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
-+ && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
-+ [(const_int 0)]
-+{
-+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
-+ NULL_RTX);
-+ DONE;
-+}
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "vecsimple")
-+ (const_string "integer")))
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "4")
-+ (if_then_else
-+ (match_test "TARGET_POWERPC64")
-+ (const_string "8")
-+ (const_string "16"))))])
-+
-+(define_insn_and_split "*boolcc<mode>3_internal2"
-+ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
-+ (match_operator:TI2 3 "boolean_operator"
-+ [(not:TI2
-+ (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
-+ (not:TI2
-+ (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
-+ "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
-+ "#"
-+ "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
-+ [(const_int 0)]
-+{
-+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
-+ NULL_RTX);
-+ DONE;
-+}
-+ [(set_attr "type" "integer")
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "TARGET_POWERPC64")
-+ (const_string "8")
-+ (const_string "16")))])
-+
-+
-+;; 128-bit EQV
-+(define_insn_and_split "*eqv<mode>3_internal1"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
-+ (not:BOOL_128
-+ (xor:BOOL_128
-+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
-+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
-+ "TARGET_P8_VECTOR"
-+{
-+ if (vsx_register_operand (operands[0], <MODE>mode))
-+ return "xxleqv %x0,%x1,%x2";
-+
-+ return "#";
-+}
-+ "TARGET_P8_VECTOR && reload_completed
-+ && int_reg_operand (operands[0], <MODE>mode)"
-+ [(const_int 0)]
-+{
-+ rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
-+ DONE;
-+}
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "vecsimple")
-+ (const_string "integer")))
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "4")
-+ (if_then_else
-+ (match_test "TARGET_POWERPC64")
-+ (const_string "8")
-+ (const_string "16"))))])
-+
-+(define_insn_and_split "*eqv<mode>3_internal2"
-+ [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
-+ (not:TI2
-+ (xor:TI2
-+ (match_operand:TI2 1 "int_reg_operand" "r,0,r")
-+ (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
-+ "!TARGET_P8_VECTOR"
-+ "#"
-+ "reload_completed && !TARGET_P8_VECTOR"
-+ [(const_int 0)]
-+{
-+ rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
-+ DONE;
-+}
-+ [(set_attr "type" "integer")
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "TARGET_POWERPC64")
-+ (const_string "8")
-+ (const_string "16")))])
-+
-+;; 128-bit one's complement
-+(define_insn_and_split "*one_cmpl<mode>3_internal"
-+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
-+ (not:BOOL_128
-+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
-+ ""
-+{
-+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
-+ return "xxlnor %x0,%x1,%x1";
-+
-+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
-+ return "vnor %0,%1,%1";
-+
-+ return "#";
-+}
-+ "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
-+ [(const_int 0)]
-+{
-+ rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
-+ DONE;
-+}
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "vecsimple")
-+ (const_string "integer")))
-+ (set (attr "length")
-+ (if_then_else
-+ (match_test "vsx_register_operand (operands[0], <MODE>mode)")
-+ (const_string "4")
-+ (if_then_else
-+ (match_test "TARGET_POWERPC64")
-+ (const_string "8")
-+ (const_string "16"))))])
-+
-+
- ;; Now define ways of moving data around.
-
- ;; Set up a register with a value from the GOT table
-@@ -7765,7 +8902,31 @@
- mt%0 %1
- mt%0 %1
- nop"
-- [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
-+ [(set_attr_alternative "type"
-+ [(const_string "*")
-+ (const_string "*")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "mfjmpr")
-+ (const_string "mtjmpr")
-+ (const_string "*")
-+ (const_string "*")])
-+
- (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
-
- (define_insn "*movsi_internal1_single"
-@@ -7787,7 +8948,44 @@
- nop
- stfs%U0%X0 %1,%0
- lfs%U1%X1 %0,%1"
-- [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")
-+ [(set_attr_alternative "type"
-+ [(const_string "*")
-+ (const_string "*")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "mfjmpr")
-+ (const_string "mtjmpr")
-+ (const_string "*")
-+ (const_string "*")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_u")
-+ (const_string "fpstore")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_u")
-+ (const_string "fpload")))])
- (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
-
- ;; Split a load of a large constant into the appropriate two-insn
-@@ -7822,7 +9020,7 @@
- cmp<wd>i %2,%0,0
- mr. %0,%1
- #"
-- [(set_attr "type" "cmp,compare,cmp")
-+ [(set_attr "type" "cmp,fast_compare,cmp")
- (set_attr "length" "4,4,8")])
-
- (define_split
-@@ -7850,7 +9048,26 @@
- mf%1 %0
- mt%0 %1
- nop"
-- [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
-+ [(set_attr_alternative "type"
-+ [(const_string "*")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
-+ (const_string "*")
-+ (const_string "mfjmpr")
-+ (const_string "mtjmpr")
-+ (const_string "*")])])
-
- (define_expand "mov<mode>"
- [(set (match_operand:INT 0 "general_operand" "")
-@@ -7871,7 +9088,26 @@
- mf%1 %0
- mt%0 %1
- nop"
-- [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
-+ [(set_attr_alternative "type"
-+ [(const_string "*")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
-+ (const_string "*")
-+ (const_string "mfjmpr")
-+ (const_string "mtjmpr")
-+ (const_string "*")])])
-
- ;; Here is how to move condition codes around. When we store CC data in
- ;; an integer register or memory, we store just the high-order 4 bits.
-@@ -7899,7 +9135,7 @@
- mf%1 %0
- mt%0 %1
- lwz%U1%X1 %0,%1
-- stw%U0%U1 %1,%0"
-+ stw%U0%X0 %1,%0"
- [(set (attr "type")
- (cond [(eq_attr "alternative" "0,3")
- (const_string "cr_logical")
-@@ -7912,9 +9148,23 @@
- (eq_attr "alternative" "9")
- (const_string "mtjmpr")
- (eq_attr "alternative" "10")
-- (const_string "load")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1],
-+ VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
- (eq_attr "alternative" "11")
-- (const_string "store")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0],
-+ VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
- (match_test "TARGET_MFCRF")
- (const_string "mfcrf")
- ]
-@@ -7926,15 +9176,17 @@
- ;; can produce floating-point values in fixed-point registers. Unless the
- ;; value is a simple constant or already in memory, we deal with this by
- ;; allocating memory and copying the value explicitly via that memory location.
--(define_expand "movsf"
-- [(set (match_operand:SF 0 "nonimmediate_operand" "")
-- (match_operand:SF 1 "any_operand" ""))]
-- ""
-- "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
-
-+;; Move 32-bit binary/decimal floating point
-+(define_expand "mov<mode>"
-+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
-+ (match_operand:FMOVE32 1 "any_operand" ""))]
-+ "<fmove_ok>"
-+ "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
-+
- (define_split
-- [(set (match_operand:SF 0 "gpc_reg_operand" "")
-- (match_operand:SF 1 "const_double_operand" ""))]
-+ [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
-+ (match_operand:FMOVE32 1 "const_double_operand" ""))]
- "reload_completed
- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
- || (GET_CODE (operands[0]) == SUBREG
-@@ -7947,10 +9199,10 @@
- REAL_VALUE_TYPE rv;
-
- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-- REAL_VALUE_TO_TARGET_SINGLE (rv, l);
-+ <real_value_to_target> (rv, l);
-
- if (! TARGET_POWERPC64)
-- operands[2] = operand_subword (operands[0], 0, 0, SFmode);
-+ operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
- else
- operands[2] = gen_lowpart (SImode, operands[0]);
-
-@@ -7957,11 +9209,11 @@
- operands[3] = gen_int_mode (l, SImode);
- }")
-
--(define_insn "*movsf_hardfloat"
-- [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r")
-- (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))]
-- "(gpc_reg_operand (operands[0], SFmode)
-- || gpc_reg_operand (operands[1], SFmode))
-+(define_insn "mov<mode>_hardfloat"
-+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
-+ (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
-+ "(gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))
- && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
- "@
- mr %0,%1
-@@ -7968,21 +9220,68 @@
- lwz%U1%X1 %0,%1
- stw%U0%X0 %1,%0
- fmr %0,%1
-- lfs%U1%X1 %0,%1
-- stfs%U0%X0 %1,%0
-+ xxlor %x0,%x1,%x1
-+ xxlxor %x0,%x0,%x0
-+ <f32_li>
-+ <f32_si>
-+ <f32_lv>
-+ <f32_sv>
-+ mtvsrwz %x0,%1
-+ mfvsrwz %0,%x1
- mt%0 %1
- mf%1 %0
- nop
- #
- #"
-- [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*")
-- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
-+ [(set_attr_alternative "type"
-+ [(const_string "*")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
-+ (const_string "fp")
-+ (const_string "vecsimple")
-+ (const_string "vecsimple")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_u")
-+ (const_string "fpload")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_u")
-+ (const_string "fpstore")))
-+ (const_string "fpload")
-+ (const_string "fpstore")
-+ (const_string "mftgpr")
-+ (const_string "mffgpr")
-+ (const_string "mtjmpr")
-+ (const_string "mfjmpr")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")])
-+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
-
--(define_insn "*movsf_softfloat"
-- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
-- (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
-- "(gpc_reg_operand (operands[0], SFmode)
-- || gpc_reg_operand (operands[1], SFmode))
-+(define_insn "*mov<mode>_softfloat"
-+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
-+ (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
-+ "(gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))
- && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
- "@
- mr %0,%1
-@@ -7995,19 +9294,42 @@
- #
- #
- nop"
-- [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
-+ [(set_attr_alternative "type"
-+ [(const_string "*")
-+ (const_string "mtjmpr")
-+ (const_string "mfjmpr")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")])
- (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
-
-
--(define_expand "movdf"
-- [(set (match_operand:DF 0 "nonimmediate_operand" "")
-- (match_operand:DF 1 "any_operand" ""))]
-+;; Move 64-bit binary/decimal floating point
-+(define_expand "mov<mode>"
-+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
-+ (match_operand:FMOVE64 1 "any_operand" ""))]
- ""
-- "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
-+ "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
-
- (define_split
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (match_operand:DF 1 "const_int_operand" ""))]
-+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
-+ (match_operand:FMOVE64 1 "const_int_operand" ""))]
- "! TARGET_POWERPC64 && reload_completed
- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
- || (GET_CODE (operands[0]) == SUBREG
-@@ -8020,8 +9342,8 @@
- int endian = (WORDS_BIG_ENDIAN == 0);
- HOST_WIDE_INT value = INTVAL (operands[1]);
-
-- operands[2] = operand_subword (operands[0], endian, 0, DFmode);
-- operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
-+ operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
-+ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
- #if HOST_BITS_PER_WIDE_INT == 32
- operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
- #else
-@@ -8031,8 +9353,8 @@
- }")
-
- (define_split
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (match_operand:DF 1 "const_double_operand" ""))]
-+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
-+ (match_operand:FMOVE64 1 "const_double_operand" ""))]
- "! TARGET_POWERPC64 && reload_completed
- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
- || (GET_CODE (operands[0]) == SUBREG
-@@ -8047,17 +9369,17 @@
- REAL_VALUE_TYPE rv;
-
- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-- REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
-+ <real_value_to_target> (rv, l);
-
-- operands[2] = operand_subword (operands[0], endian, 0, DFmode);
-- operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
-+ operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
-+ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
- operands[4] = gen_int_mode (l[endian], SImode);
- operands[5] = gen_int_mode (l[1 - endian], SImode);
- }")
-
- (define_split
-- [(set (match_operand:DF 0 "gpc_reg_operand" "")
-- (match_operand:DF 1 "const_double_operand" ""))]
-+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
-+ (match_operand:FMOVE64 1 "const_double_operand" ""))]
- "TARGET_POWERPC64 && reload_completed
- && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
- || (GET_CODE (operands[0]) == SUBREG
-@@ -8074,7 +9396,7 @@
- #endif
-
- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-- REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
-+ <real_value_to_target> (rv, l);
-
- operands[2] = gen_lowpart (DImode, operands[0]);
- /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
-@@ -8099,22 +9421,19 @@
- ;; since the D-form version of the memory instructions does not need a GPR for
- ;; reloading.
-
--(define_insn "*movdf_hardfloat32"
-- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r")
-- (match_operand:DF 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))]
-+(define_insn "*mov<mode>_hardfloat32"
-+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
-+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
- "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && (gpc_reg_operand (operands[0], DFmode)
-- || gpc_reg_operand (operands[1], DFmode))"
-+ && (gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))"
- "@
- stfd%U0%X0 %1,%0
- lfd%U1%X1 %0,%1
- fmr %0,%1
- lxsd%U1x %x0,%y1
-- lxsd%U1x %x0,%y1
- stxsd%U0x %x1,%y0
-- stxsd%U0x %x1,%y0
- xxlor %x0,%x1,%x1
-- xxlor %x0,%x1,%x1
- xxlxor %x0,%x0,%x0
- #
- #
-@@ -8122,115 +9441,141 @@
- #
- #
- #"
-- [(set_attr "type" "fpstore,fpload,fp,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,store,load,two,fp,fp,*")
-- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")])
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_u")
-+ (const_string "fpstore")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_u")
-+ (const_string "fpload")))
-+ (const_string "fp")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (const_string "fpload"))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_ux")
-+ (const_string "fpstore"))
-+ (const_string "vecsimple")
-+ (const_string "vecsimple")
-+ (const_string "store")
-+ (const_string "load")
-+ (const_string "two")
-+ (const_string "fp")
-+ (const_string "fp")
-+ (const_string "*")])
-+ (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
-
--(define_insn "*movdf_softfloat32"
-- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
-- (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]
-+(define_insn "*mov<mode>_softfloat32"
-+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
-+ (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
- "! TARGET_POWERPC64
- && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
-- || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
-- && (gpc_reg_operand (operands[0], DFmode)
-- || gpc_reg_operand (operands[1], DFmode))"
-+ || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
-+ || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
-+ && (gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))"
- "#"
- [(set_attr "type" "store,load,two,*,*,*")
- (set_attr "length" "8,8,8,8,12,16")])
-
--;; Reload patterns to support gpr load/store with misaligned mem.
--;; and multiple gpr load/store at offset >= 0xfffc
--(define_expand "reload_<mode>_store"
-- [(parallel [(match_operand 0 "memory_operand" "=m")
-- (match_operand 1 "gpc_reg_operand" "r")
-- (match_operand:GPR 2 "register_operand" "=&b")])]
-- ""
--{
-- rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
-- DONE;
--})
--
--(define_expand "reload_<mode>_load"
-- [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
-- (match_operand 1 "memory_operand" "m")
-- (match_operand:GPR 2 "register_operand" "=b")])]
-- ""
--{
-- rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
-- DONE;
--})
--
- ; ld/std require word-aligned displacements -> 'Y' constraint.
- ; List Y->r and r->Y before r->r for reload.
--(define_insn "*movdf_hardfloat64_mfpgpr"
-- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")
-- (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
-- "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
-- && TARGET_DOUBLE_FLOAT
-- && (gpc_reg_operand (operands[0], DFmode)
-- || gpc_reg_operand (operands[1], DFmode))"
-+(define_insn "*mov<mode>_hardfloat64"
-+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
-+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
-+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-+ && (gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))"
- "@
-- std%U0%X0 %1,%0
-- ld%U1%X1 %0,%1
-- mr %0,%1
-- xxlor %x0,%x1,%x1
-- xxlor %x0,%x1,%x1
-- lxsd%U1x %x0,%y1
-- lxsd%U1x %x0,%y1
-- stxsd%U0x %x1,%y0
-- stxsd%U0x %x1,%y0
- stfd%U0%X0 %1,%0
- lfd%U1%X1 %0,%1
- fmr %0,%1
-+ lxsd%U1x %x0,%y1
-+ stxsd%U0x %x1,%y0
-+ xxlor %x0,%x1,%x1
- xxlxor %x0,%x0,%x0
-- mt%0 %1
-- mf%1 %0
-- nop
-- #
-- #
-- #
-- mftgpr %0,%1
-- mffgpr %0,%1"
-- [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
-- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
--
--; ld/std require word-aligned displacements -> 'Y' constraint.
--; List Y->r and r->Y before r->r for reload.
--(define_insn "*movdf_hardfloat64"
-- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,Y,r,!r,ws,?wa,Z,?Z,ws,?wa,wa,*c*l,!r,*h,!r,!r,!r")
-- (match_operand:DF 1 "input_operand" "d,m,d,r,Y,r,Z,Z,ws,wa,ws,wa,j,r,h,0,G,H,F"))]
-- "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
-- && TARGET_DOUBLE_FLOAT
-- && (gpc_reg_operand (operands[0], DFmode)
-- || gpc_reg_operand (operands[1], DFmode))"
-- "@
-- stfd%U0%X0 %1,%0
-- lfd%U1%X1 %0,%1
-- fmr %0,%1
- std%U0%X0 %1,%0
- ld%U1%X1 %0,%1
- mr %0,%1
-- lxsd%U1x %x0,%y1
-- lxsd%U1x %x0,%y1
-- stxsd%U0x %x1,%y0
-- stxsd%U0x %x1,%y0
-- xxlor %x0,%x1,%x1
-- xxlor %x0,%x1,%x1
-- xxlxor %x0,%x0,%x0
- mt%0 %1
- mf%1 %0
- nop
- #
- #
-- #"
-- [(set_attr "type" "fpstore,fpload,fp,store,load,*,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
-- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
-+ #
-+ mftgpr %0,%1
-+ mffgpr %0,%1
-+ mfvsrd %0,%x1
-+ mtvsrd %x0,%1"
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_u")
-+ (const_string "fpstore")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_u")
-+ (const_string "fpload")))
-+ (const_string "fp")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (const_string "fpload"))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_ux")
-+ (const_string "fpstore"))
-+ (const_string "vecsimple")
-+ (const_string "vecsimple")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (const_string "*")
-+ (const_string "mtjmpr")
-+ (const_string "mfjmpr")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "mftgpr")
-+ (const_string "mffgpr")
-+ (const_string "mftgpr")
-+ (const_string "mffgpr")])
-+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
-
--(define_insn "*movdf_softfloat64"
-- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
-- (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
-+(define_insn "*mov<mode>_softfloat64"
-+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
-+ (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
- "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
-- && (gpc_reg_operand (operands[0], DFmode)
-- || gpc_reg_operand (operands[1], DFmode))"
-+ && (gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))"
- "@
- std%U0%X0 %1,%0
- ld%U1%X1 %0,%1
-@@ -8241,38 +9586,87 @@
- #
- #
- nop"
-- [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (const_string "*")
-+ (const_string "mtjmpr")
-+ (const_string "mfjmpr")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")])
- (set_attr "length" "4,4,4,4,4,8,12,16,4")])
-
--(define_expand "movtf"
-- [(set (match_operand:TF 0 "general_operand" "")
-- (match_operand:TF 1 "any_operand" ""))]
-- "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
-- "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
-+(define_expand "mov<mode>"
-+ [(set (match_operand:FMOVE128 0 "general_operand" "")
-+ (match_operand:FMOVE128 1 "any_operand" ""))]
-+ ""
-+ "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
-
- ;; It's important to list Y->r and r->Y before r->r because otherwise
- ;; reload, given m->r, will try to pick r->r and reload it, which
- ;; doesn't make progress.
--(define_insn_and_split "*movtf_internal"
-- [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
-- (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]
-- "!TARGET_IEEEQUAD
-- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
-- && (gpc_reg_operand (operands[0], TFmode)
-- || gpc_reg_operand (operands[1], TFmode))"
-+
-+;; We can't split little endian direct moves of TDmode, because the words are
-+;; not swapped like they are for TImode or TFmode. Subregs therefore are
-+;; problematical. Don't allow direct move for this case.
-+
-+(define_insn_and_split "*mov<mode>_64bit_dm"
-+ [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
-+ (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
-+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
-+ && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
-+ && (gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))"
- "#"
- "&& reload_completed"
- [(pc)]
- { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
-+ [(set_attr "length" "8,8,8,12,12,8,8,8")])
-+
-+(define_insn_and_split "*movtd_64bit_nodm"
-+ [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
-+ (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
-+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
-+ && (gpc_reg_operand (operands[0], TDmode)
-+ || gpc_reg_operand (operands[1], TDmode))"
-+ "#"
-+ "&& reload_completed"
-+ [(pc)]
-+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
-+ [(set_attr "length" "8,8,8,12,12,8")])
-+
-+(define_insn_and_split "*mov<mode>_32bit"
-+ [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
-+ (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
-+ "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
-+ && (gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))"
-+ "#"
-+ "&& reload_completed"
-+ [(pc)]
-+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
- [(set_attr "length" "8,8,8,20,20,16")])
-
--(define_insn_and_split "*movtf_softfloat"
-- [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")
-- (match_operand:TF 1 "input_operand" "r,YGHF,r"))]
-- "!TARGET_IEEEQUAD
-- && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
-- && (gpc_reg_operand (operands[0], TFmode)
-- || gpc_reg_operand (operands[1], TFmode))"
-+(define_insn_and_split "*mov<mode>_softfloat"
-+ [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
-+ (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
-+ "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
-+ && (gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))"
- "#"
- "&& reload_completed"
- [(pc)]
-@@ -8557,6 +9951,252 @@
- operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
- }")
-
-+;; Reload helper functions used by rs6000_secondary_reload. The patterns all
-+;; must have 3 arguments, and scratch register constraint must be a single
-+;; constraint.
-+
-+;; Reload patterns to support gpr load/store with misaligned mem.
-+;; and multiple gpr load/store at offset >= 0xfffc
-+(define_expand "reload_<mode>_store"
-+ [(parallel [(match_operand 0 "memory_operand" "=m")
-+ (match_operand 1 "gpc_reg_operand" "r")
-+ (match_operand:GPR 2 "register_operand" "=&b")])]
-+ ""
-+{
-+ rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
-+ DONE;
-+})
-+
-+(define_expand "reload_<mode>_load"
-+ [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
-+ (match_operand 1 "memory_operand" "m")
-+ (match_operand:GPR 2 "register_operand" "=b")])]
-+ ""
-+{
-+ rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
-+ DONE;
-+})
-+
-+
-+;; Power8 merge instructions to allow direct move to/from floating point
-+;; registers in 32-bit mode. We use TF mode to get two registers to move the
-+;; individual 32-bit parts across. Subreg doesn't work too well on the TF
-+;; value, since it is allocated in reload and not all of the flow information
-+;; is setup for it. We have two patterns to do the two moves between gprs and
-+;; fprs. There isn't a dependancy between the two, but we could potentially
-+;; schedule other instructions between the two instructions. TFmode is
-+;; currently limited to traditional FPR registers. If/when this is changed, we
-+;; will need to revist %L to make sure it works with VSX registers, or add an
-+;; %x version of %L.
-+
-+(define_insn "p8_fmrgow_<mode>"
-+ [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
-+ (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
-+ UNSPEC_P8V_FMRGOW))]
-+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "fmrgow %0,%1,%L1"
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn "p8_mtvsrwz_1"
-+ [(set (match_operand:TF 0 "register_operand" "=d")
-+ (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
-+ UNSPEC_P8V_MTVSRWZ))]
-+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "mtvsrwz %x0,%1"
-+ [(set_attr "type" "mftgpr")])
-+
-+(define_insn "p8_mtvsrwz_2"
-+ [(set (match_operand:TF 0 "register_operand" "+d")
-+ (unspec:TF [(match_dup 0)
-+ (match_operand:SI 1 "register_operand" "r")]
-+ UNSPEC_P8V_MTVSRWZ))]
-+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "mtvsrwz %L0,%1"
-+ [(set_attr "type" "mftgpr")])
-+
-+(define_insn_and_split "reload_fpr_from_gpr<mode>"
-+ [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
-+ (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
-+ UNSPEC_P8V_RELOAD_FROM_GPR))
-+ (clobber (match_operand:TF 2 "register_operand" "=d"))]
-+ "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "#"
-+ "&& reload_completed"
-+ [(const_int 0)]
-+{
-+ rtx dest = operands[0];
-+ rtx src = operands[1];
-+ rtx tmp = operands[2];
-+ rtx gpr_hi_reg = gen_highpart (SImode, src);
-+ rtx gpr_lo_reg = gen_lowpart (SImode, src);
-+
-+ emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
-+ emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
-+ emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
-+ DONE;
-+}
-+ [(set_attr "length" "12")
-+ (set_attr "type" "three")])
-+
-+;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
-+(define_insn "p8_mtvsrd_1"
-+ [(set (match_operand:TF 0 "register_operand" "=ws")
-+ (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
-+ UNSPEC_P8V_MTVSRD))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "mtvsrd %0,%1"
-+ [(set_attr "type" "mftgpr")])
-+
-+(define_insn "p8_mtvsrd_2"
-+ [(set (match_operand:TF 0 "register_operand" "+ws")
-+ (unspec:TF [(match_dup 0)
-+ (match_operand:DI 1 "register_operand" "r")]
-+ UNSPEC_P8V_MTVSRD))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "mtvsrd %L0,%1"
-+ [(set_attr "type" "mftgpr")])
-+
-+(define_insn "p8_xxpermdi_<mode>"
-+ [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
-+ (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
-+ UNSPEC_P8V_XXPERMDI))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "xxpermdi %x0,%1,%L1,0"
-+ [(set_attr "type" "vecperm")])
-+
-+(define_insn_and_split "reload_vsx_from_gpr<mode>"
-+ [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
-+ (unspec:FMOVE128_GPR
-+ [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
-+ UNSPEC_P8V_RELOAD_FROM_GPR))
-+ (clobber (match_operand:TF 2 "register_operand" "=ws"))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "#"
-+ "&& reload_completed"
-+ [(const_int 0)]
-+{
-+ rtx dest = operands[0];
-+ rtx src = operands[1];
-+ rtx tmp = operands[2];
-+ rtx gpr_hi_reg = gen_highpart (DImode, src);
-+ rtx gpr_lo_reg = gen_lowpart (DImode, src);
-+
-+ emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
-+ emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
-+ emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
-+}
-+ [(set_attr "length" "12")
-+ (set_attr "type" "three")])
-+
-+(define_split
-+ [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
-+ (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
-+ "reload_completed
-+ && (int_reg_operand (operands[0], <MODE>mode)
-+ || int_reg_operand (operands[1], <MODE>mode))"
-+ [(pc)]
-+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
-+
-+;; Move SFmode to a VSX from a GPR register. Because scalar floating point
-+;; type is stored internally as double precision in the VSX registers, we have
-+;; to convert it from the vector format.
-+
-+(define_insn_and_split "reload_vsx_from_gprsf"
-+ [(set (match_operand:SF 0 "register_operand" "=wa")
-+ (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
-+ UNSPEC_P8V_RELOAD_FROM_GPR))
-+ (clobber (match_operand:DI 2 "register_operand" "=r"))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "#"
-+ "&& reload_completed"
-+ [(const_int 0)]
-+{
-+ rtx op0 = operands[0];
-+ rtx op1 = operands[1];
-+ rtx op2 = operands[2];
-+ rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);
-+ rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
-+
-+ /* Move SF value to upper 32-bits for xscvspdpn. */
-+ emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
-+ emit_move_insn (op0_di, op2);
-+ emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
-+ DONE;
-+}
-+ [(set_attr "length" "8")
-+ (set_attr "type" "two")])
-+
-+;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
-+;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
-+;; and then doing a move of that.
-+(define_insn "p8_mfvsrd_3_<mode>"
-+ [(set (match_operand:DF 0 "register_operand" "=r")
-+ (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
-+ UNSPEC_P8V_RELOAD_FROM_VSX))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "mfvsrd %0,%x1"
-+ [(set_attr "type" "mftgpr")])
-+
-+(define_insn_and_split "reload_gpr_from_vsx<mode>"
-+ [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
-+ (unspec:FMOVE128_GPR
-+ [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
-+ UNSPEC_P8V_RELOAD_FROM_VSX))
-+ (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "#"
-+ "&& reload_completed"
-+ [(const_int 0)]
-+{
-+ rtx dest = operands[0];
-+ rtx src = operands[1];
-+ rtx tmp = operands[2];
-+ rtx gpr_hi_reg = gen_highpart (DFmode, dest);
-+ rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
-+
-+ emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
-+ emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
-+ emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
-+}
-+ [(set_attr "length" "12")
-+ (set_attr "type" "three")])
-+
-+;; Move SFmode to a GPR from a VSX register. Because scalar floating point
-+;; type is stored internally as double precision, we have to convert it to the
-+;; vector format.
-+
-+(define_insn_and_split "reload_gpr_from_vsxsf"
-+ [(set (match_operand:SF 0 "register_operand" "=r")
-+ (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
-+ UNSPEC_P8V_RELOAD_FROM_VSX))
-+ (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "#"
-+ "&& reload_completed"
-+ [(const_int 0)]
-+{
-+ rtx op0 = operands[0];
-+ rtx op1 = operands[1];
-+ rtx op2 = operands[2];
-+ rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
-+
-+ emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
-+ emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
-+ emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
-+ DONE;
-+}
-+ [(set_attr "length" "12")
-+ (set_attr "type" "three")])
-+
-+(define_insn "p8_mfvsrd_4_disf"
-+ [(set (match_operand:DI 0 "register_operand" "=r")
-+ (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
-+ UNSPEC_P8V_RELOAD_FROM_VSX))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "mfvsrd %0,%x1"
-+ [(set_attr "type" "mftgpr")])
-+
-+
- ;; Next come the multi-word integer load and store and the load and store
- ;; multiple insns.
-
-@@ -8565,8 +10205,8 @@
- ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
- ;; a gpr into a fpr instead of reloading an invalid 'Y' address
- (define_insn "*movdi_internal32"
-- [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
-- (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
-+ [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
-+ (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
- "! TARGET_POWERPC64
- && (gpc_reg_operand (operands[0], DImode)
- || gpc_reg_operand (operands[1], DImode))"
-@@ -8577,15 +10217,34 @@
- stfd%U0%X0 %1,%0
- lfd%U1%X1 %0,%1
- fmr %0,%1
-- #
-- xxlxor %x0,%x0,%x0"
-- [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])
-+ #"
-+ [(set_attr_alternative "type"
-+ [(const_string "store")
-+ (const_string "load")
-+ (const_string "*")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_u")
-+ (const_string "fpstore")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_u")
-+ (const_string "fpload")))
-+ (const_string "fp")
-+ (const_string "*")])])
-
- (define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "const_int_operand" ""))]
- "! TARGET_POWERPC64 && reload_completed
-- && gpr_or_gpr_p (operands[0], operands[1])"
-+ && gpr_or_gpr_p (operands[0], operands[1])
-+ && !direct_move_p (operands[0], operands[1])"
- [(set (match_dup 2) (match_dup 4))
- (set (match_dup 3) (match_dup 1))]
- "
-@@ -8607,14 +10266,15 @@
- [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
- (match_operand:DIFD 1 "input_operand" ""))]
- "reload_completed && !TARGET_POWERPC64
-- && gpr_or_gpr_p (operands[0], operands[1])"
-+ && gpr_or_gpr_p (operands[0], operands[1])
-+ && !direct_move_p (operands[0], operands[1])"
- [(pc)]
- { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
-
--(define_insn "*movdi_mfpgpr"
-- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")
-- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
-- "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
-+(define_insn "*movdi_internal64"
-+ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
-+ (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
-+ "TARGET_POWERPC64
- && (gpc_reg_operand (operands[0], DImode)
- || gpc_reg_operand (operands[1], DImode))"
- "@
-@@ -8631,33 +10291,52 @@
- mt%0 %1
- nop
- mftgpr %0,%1
-- mffgpr %0,%1"
-- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
-- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
-+ mffgpr %0,%1
-+ mfvsrd %0,%x1
-+ mtvsrd %x0,%1"
-+ [(set_attr_alternative "type"
-+ [(if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "load_u")
-+ (const_string "load")))
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")
-+ (const_string "*")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "fpstore_u")
-+ (const_string "fpstore")))
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[1], VOIDmode)")
-+ (const_string "fpload_u")
-+ (const_string "fpload")))
-+ (const_string "fp")
-+ (const_string "mfjmpr")
-+ (const_string "mtjmpr")
-+ (const_string "*")
-+ (const_string "mftgpr")
-+ (const_string "mffgpr")
-+ (const_string "mftgpr")
-+ (const_string "mffgpr")])
-+ (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
-
--(define_insn "*movdi_internal64"
-- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")
-- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]
-- "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
-- && (gpc_reg_operand (operands[0], DImode)
-- || gpc_reg_operand (operands[1], DImode))"
-- "@
-- std%U0%X0 %1,%0
-- ld%U1%X1 %0,%1
-- mr %0,%1
-- li %0,%1
-- lis %0,%v1
-- #
-- stfd%U0%X0 %1,%0
-- lfd%U1%X1 %0,%1
-- fmr %0,%1
-- mf%1 %0
-- mt%0 %1
-- nop
-- xxlxor %x0,%x0,%x0"
-- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")
-- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
--
- ;; immediate value valid for a single instruction hiding in a const_double
- (define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-@@ -8719,14 +10398,16 @@
- FAIL;
- }")
-
--;; TImode is similar, except that we usually want to compute the address into
--;; a register and use lsi/stsi (the exception is during reload).
-+;; TImode/PTImode is similar, except that we usually want to compute the
-+;; address into a register and use lsi/stsi (the exception is during reload).
-
--(define_insn "*movti_string"
-- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
-- (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
-+(define_insn "*mov<mode>_string"
-+ [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
-+ (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
- "! TARGET_POWERPC64
-- && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
-+ && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
-+ && (gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode))"
- "*
- {
- switch (which_alternative)
-@@ -8756,27 +10437,32 @@
- (const_string "always")
- (const_string "conditional")))])
-
--(define_insn "*movti_ppc64"
-- [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")
-- (match_operand:TI 1 "input_operand" "r,Y,r"))]
-- "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
-- || gpc_reg_operand (operands[1], TImode)))
-- && VECTOR_MEM_NONE_P (TImode)"
-- "#"
-- [(set_attr "type" "store,load,*")])
-+(define_insn "*mov<mode>_ppc64"
-+ [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
-+ (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
-+ "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
-+ && (gpc_reg_operand (operands[0], <MODE>mode)
-+ || gpc_reg_operand (operands[1], <MODE>mode)))"
-+{
-+ return rs6000_output_move_128bit (operands);
-+}
-+ [(set_attr "type" "store,store,load,load,*,*")
-+ (set_attr "length" "8")])
-
- (define_split
-- [(set (match_operand:TI 0 "gpc_reg_operand" "")
-- (match_operand:TI 1 "const_double_operand" ""))]
-- "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
-+ [(set (match_operand:TI2 0 "int_reg_operand" "")
-+ (match_operand:TI2 1 "const_double_operand" ""))]
-+ "TARGET_POWERPC64
-+ && (VECTOR_MEM_NONE_P (<MODE>mode)
-+ || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
- [(set (match_dup 2) (match_dup 4))
- (set (match_dup 3) (match_dup 5))]
- "
- {
- operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
-- TImode);
-+ <MODE>mode);
- operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
-- TImode);
-+ <MODE>mode);
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- {
- operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
-@@ -8792,10 +10478,12 @@
- }")
-
- (define_split
-- [(set (match_operand:TI 0 "nonimmediate_operand" "")
-- (match_operand:TI 1 "input_operand" ""))]
-- "reload_completed && VECTOR_MEM_NONE_P (TImode)
-- && gpr_or_gpr_p (operands[0], operands[1])"
-+ [(set (match_operand:TI2 0 "nonimmediate_operand" "")
-+ (match_operand:TI2 1 "input_operand" ""))]
-+ "reload_completed
-+ && gpr_or_gpr_p (operands[0], operands[1])
-+ && !direct_move_p (operands[0], operands[1])
-+ && !quad_load_store_p (operands[0], operands[1])"
- [(pc)]
- { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
-
-@@ -9651,7 +11339,7 @@
- (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
- UNSPEC_TLSGD)
- (clobber (reg:SI LR_REGNO))]
-- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
-+ "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
- {
- if (TARGET_CMODEL != CMODEL_SMALL)
- return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
-@@ -9723,7 +11411,7 @@
- (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
- (set (match_dup 0)
- (lo_sum:TLSmode (match_dup 3)
-- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
-+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
- "
- {
- operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-@@ -9746,7 +11434,8 @@
- (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
- [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
- (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
-- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
-+ (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
-+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
- UNSPEC_TLSGD)))]
- "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
- "addi %0,%1,%2@got@tlsgd@l"
-@@ -9759,7 +11448,8 @@
- (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
- UNSPEC_TLSGD)
- (clobber (reg:SI LR_REGNO))]
-- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
-+ "HAVE_AS_TLS && TARGET_TLS_MARKERS
-+ && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
- "bl %z1(%3@tlsgd)\;nop"
- [(set_attr "type" "branch")
- (set_attr "length" "8")])
-@@ -9791,7 +11481,7 @@
- (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
- UNSPEC_TLSLD)
- (clobber (reg:SI LR_REGNO))]
-- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
-+ "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
- {
- if (TARGET_CMODEL != CMODEL_SMALL)
- return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
-@@ -9858,7 +11548,7 @@
- (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
- (set (match_dup 0)
- (lo_sum:TLSmode (match_dup 2)
-- (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
-+ (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
- "
- {
- operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-@@ -9881,7 +11571,9 @@
- (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
- [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
- (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
-- (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
-+ (unspec:TLSmode [(const_int 0)
-+ (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
-+ UNSPEC_TLSLD)))]
- "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
- "addi %0,%1,%&@got@tlsld@l"
- [(set_attr "length" "4")])
-@@ -9892,7 +11584,8 @@
- (match_operand 2 "" "g")))
- (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
- (clobber (reg:SI LR_REGNO))]
-- "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
-+ "HAVE_AS_TLS && TARGET_TLS_MARKERS
-+ && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
- "bl %z1(%&@tlsld)\;nop"
- [(set_attr "type" "branch")
- (set_attr "length" "8")])
-@@ -9953,7 +11646,7 @@
- (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
- (set (match_dup 0)
- (lo_sum:TLSmode (match_dup 3)
-- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
-+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
- "
- {
- operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-@@ -9976,7 +11669,8 @@
- (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
- [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
- (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
-- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
-+ (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
-+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
- UNSPEC_TLSGOTDTPREL)))]
- "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
- "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
-@@ -10022,7 +11716,7 @@
- (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
- (set (match_dup 0)
- (lo_sum:TLSmode (match_dup 3)
-- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
-+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
- "
- {
- operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-@@ -10045,7 +11739,8 @@
- (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
- [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
- (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
-- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
-+ (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
-+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
- UNSPEC_TLSGOTTPREL)))]
- "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
- "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
-@@ -10261,7 +11956,7 @@
- [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unspec:SI [(const_int 0)] UNSPEC_TOC))
- (use (reg:SI 2))])]
-- "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
-+ "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
- "*
- {
- char buf[30];
-@@ -10276,7 +11971,7 @@
- [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (unspec:DI [(const_int 0)] UNSPEC_TOC))
- (use (reg:DI 2))])]
-- "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
-+ "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
- "*
- {
- char buf[30];
-@@ -10306,7 +12001,7 @@
- [(parallel [(set (reg:SI LR_REGNO)
- (match_operand:SI 0 "immediate_operand" "s"))
- (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
-- "TARGET_ELF && DEFAULT_ABI != ABI_AIX
-+ "TARGET_ELF && DEFAULT_ABI == ABI_V4
- && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
- "")
-
-@@ -10314,7 +12009,7 @@
- [(set (reg:SI LR_REGNO)
- (match_operand:SI 0 "immediate_operand" "s"))
- (use (unspec [(match_dup 0)] UNSPEC_TOC))]
-- "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
-+ "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
- && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
- "bcl 20,31,%0\\n%0:"
- [(set_attr "type" "branch")
-@@ -10324,7 +12019,7 @@
- [(set (reg:SI LR_REGNO)
- (match_operand:SI 0 "immediate_operand" "s"))
- (use (unspec [(match_dup 0)] UNSPEC_TOC))]
-- "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
-+ "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
- && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
- "*
- {
-@@ -10344,7 +12039,7 @@
- (label_ref (match_operand 1 "" ""))]
- UNSPEC_TOCPTR))
- (match_dup 1)])]
-- "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
-+ "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
- "")
-
- (define_insn "load_toc_v4_PIC_1b_normal"
-@@ -10353,7 +12048,7 @@
- (label_ref (match_operand 1 "" ""))]
- UNSPEC_TOCPTR))
- (match_dup 1)]
-- "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
-+ "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
- "bcl 20,31,$+8\;.long %0-$"
- [(set_attr "type" "branch")
- (set_attr "length" "8")])
-@@ -10364,7 +12059,7 @@
- (label_ref (match_operand 1 "" ""))]
- UNSPEC_TOCPTR))
- (match_dup 1)]
-- "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
-+ "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
- "*
- {
- char name[32];
-@@ -10382,7 +12077,7 @@
- (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (minus:SI (match_operand:SI 2 "immediate_operand" "s")
- (match_operand:SI 3 "immediate_operand" "s")))))]
-- "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
-+ "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
- "lwz %0,%2-%3(%1)"
- [(set_attr "type" "load")])
-
-@@ -10392,7 +12087,7 @@
- (high:SI
- (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
- (match_operand:SI 3 "symbol_ref_operand" "s")))))]
-- "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
-+ "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
- "addis %0,%1,%2-%3@ha")
-
- (define_insn "load_toc_v4_PIC_3c"
-@@ -10400,7 +12095,7 @@
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
- (match_operand:SI 3 "symbol_ref_operand" "s"))))]
-- "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
-+ "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
- "addi %0,%1,%2-%3@l")
-
- ;; If the TOC is shared over a translation unit, as happens with all
-@@ -10542,8 +12237,13 @@
-
- operands[0] = XEXP (operands[0], 0);
-
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ {
-+ rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
-+ DONE;
-+ }
-+
- if (GET_CODE (operands[0]) != SYMBOL_REF
-- || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
- || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
- {
- if (INTVAL (operands[2]) & CALL_LONG)
-@@ -10556,12 +12256,6 @@
- operands[0] = force_reg (Pmode, operands[0]);
- break;
-
-- case ABI_AIX:
-- /* AIX function pointers are really pointers to a three word
-- area. */
-- rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
-- DONE;
--
- default:
- gcc_unreachable ();
- }
-@@ -10587,8 +12281,13 @@
-
- operands[1] = XEXP (operands[1], 0);
-
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ {
-+ rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
-+ DONE;
-+ }
-+
- if (GET_CODE (operands[1]) != SYMBOL_REF
-- || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
- || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
- {
- if (INTVAL (operands[3]) & CALL_LONG)
-@@ -10601,12 +12300,6 @@
- operands[1] = force_reg (Pmode, operands[1]);
- break;
-
-- case ABI_AIX:
-- /* AIX function pointers are really pointers to a three word
-- area. */
-- rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
-- DONE;
--
- default:
- gcc_unreachable ();
- }
-@@ -10698,136 +12391,7 @@
- [(set_attr "type" "branch")
- (set_attr "length" "4,8")])
-
--;; Call to indirect functions with the AIX abi using a 3 word descriptor.
--;; Operand0 is the addresss of the function to call
--;; Operand1 is the flag for System V.4 for unprototyped or FP registers
--;; Operand2 is the location in the function descriptor to load r2 from
--;; Operand3 is the stack location to hold the current TOC pointer
-
--(define_insn "call_indirect_aix<ptrsize>"
-- [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
-- (match_operand 1 "" "g,g"))
-- (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
-- (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
-- (use (reg:P STATIC_CHAIN_REGNUM))
-- (clobber (reg:P LR_REGNO))]
-- "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
-- "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
-- [(set_attr "type" "jmpreg")
-- (set_attr "length" "12")])
--
--;; Like call_indirect_aix<ptrsize>, but no use of the static chain
--;; Operand0 is the addresss of the function to call
--;; Operand1 is the flag for System V.4 for unprototyped or FP registers
--;; Operand2 is the location in the function descriptor to load r2 from
--;; Operand3 is the stack location to hold the current TOC pointer
--
--(define_insn "call_indirect_aix<ptrsize>_nor11"
-- [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
-- (match_operand 1 "" "g,g"))
-- (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
-- (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
-- (clobber (reg:P LR_REGNO))]
-- "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
-- "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
-- [(set_attr "type" "jmpreg")
-- (set_attr "length" "12")])
--
--;; Operand0 is the return result of the function
--;; Operand1 is the addresss of the function to call
--;; Operand2 is the flag for System V.4 for unprototyped or FP registers
--;; Operand3 is the location in the function descriptor to load r2 from
--;; Operand4 is the stack location to hold the current TOC pointer
--
--(define_insn "call_value_indirect_aix<ptrsize>"
-- [(set (match_operand 0 "" "")
-- (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
-- (match_operand 2 "" "g,g")))
-- (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
-- (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
-- (use (reg:P STATIC_CHAIN_REGNUM))
-- (clobber (reg:P LR_REGNO))]
-- "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
-- "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
-- [(set_attr "type" "jmpreg")
-- (set_attr "length" "12")])
--
--;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
--;; Operand0 is the return result of the function
--;; Operand1 is the addresss of the function to call
--;; Operand2 is the flag for System V.4 for unprototyped or FP registers
--;; Operand3 is the location in the function descriptor to load r2 from
--;; Operand4 is the stack location to hold the current TOC pointer
--
--(define_insn "call_value_indirect_aix<ptrsize>_nor11"
-- [(set (match_operand 0 "" "")
-- (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
-- (match_operand 2 "" "g,g")))
-- (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
-- (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
-- (clobber (reg:P LR_REGNO))]
-- "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
-- "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
-- [(set_attr "type" "jmpreg")
-- (set_attr "length" "12")])
--
--;; Call to function which may be in another module. Restore the TOC
--;; pointer (r2) after the call unless this is System V.
--;; Operand2 is nonzero if we are using the V.4 calling sequence and
--;; either the function was not prototyped, or it was prototyped as a
--;; variable argument function. It is > 0 if FP registers were passed
--;; and < 0 if they were not.
--
--(define_insn "*call_nonlocal_aix32"
-- [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
-- (match_operand 1 "" "g"))
-- (use (match_operand:SI 2 "immediate_operand" "O"))
-- (clobber (reg:SI LR_REGNO))]
-- "TARGET_32BIT
-- && DEFAULT_ABI == ABI_AIX
-- && (INTVAL (operands[2]) & CALL_LONG) == 0"
-- "bl %z0\;nop"
-- [(set_attr "type" "branch")
-- (set_attr "length" "8")])
--
--(define_insn "*call_nonlocal_aix64"
-- [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
-- (match_operand 1 "" "g"))
-- (use (match_operand:SI 2 "immediate_operand" "O"))
-- (clobber (reg:SI LR_REGNO))]
-- "TARGET_64BIT
-- && DEFAULT_ABI == ABI_AIX
-- && (INTVAL (operands[2]) & CALL_LONG) == 0"
-- "bl %z0\;nop"
-- [(set_attr "type" "branch")
-- (set_attr "length" "8")])
--
--(define_insn "*call_value_nonlocal_aix32"
-- [(set (match_operand 0 "" "")
-- (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
-- (match_operand 2 "" "g")))
-- (use (match_operand:SI 3 "immediate_operand" "O"))
-- (clobber (reg:SI LR_REGNO))]
-- "TARGET_32BIT
-- && DEFAULT_ABI == ABI_AIX
-- && (INTVAL (operands[3]) & CALL_LONG) == 0"
-- "bl %z1\;nop"
-- [(set_attr "type" "branch")
-- (set_attr "length" "8")])
--
--(define_insn "*call_value_nonlocal_aix64"
-- [(set (match_operand 0 "" "")
-- (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
-- (match_operand 2 "" "g")))
-- (use (match_operand:SI 3 "immediate_operand" "O"))
-- (clobber (reg:SI LR_REGNO))]
-- "TARGET_64BIT
-- && DEFAULT_ABI == ABI_AIX
-- && (INTVAL (operands[3]) & CALL_LONG) == 0"
-- "bl %z1\;nop"
-- [(set_attr "type" "branch")
-- (set_attr "length" "8")])
--
- ;; A function pointer under System V is just a normal pointer
- ;; operands[0] is the function pointer
- ;; operands[1] is the stack size to clean up
-@@ -11009,6 +12573,104 @@
- [(set_attr "type" "branch,branch")
- (set_attr "length" "4,8")])
-
-+
-+;; Call to AIX abi function in the same module.
-+
-+(define_insn "*call_local_aix<mode>"
-+ [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
-+ (match_operand 1 "" "g"))
-+ (clobber (reg:P LR_REGNO))]
-+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
-+ "bl %z0"
-+ [(set_attr "type" "branch")
-+ (set_attr "length" "4")])
-+
-+(define_insn "*call_value_local_aix<mode>"
-+ [(set (match_operand 0 "" "")
-+ (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
-+ (match_operand 2 "" "g")))
-+ (clobber (reg:P LR_REGNO))]
-+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
-+ "bl %z1"
-+ [(set_attr "type" "branch")
-+ (set_attr "length" "4")])
-+
-+;; Call to AIX abi function which may be in another module.
-+;; Restore the TOC pointer (r2) after the call.
-+
-+(define_insn "*call_nonlocal_aix<mode>"
-+ [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
-+ (match_operand 1 "" "g"))
-+ (clobber (reg:P LR_REGNO))]
-+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
-+ "bl %z0\;nop"
-+ [(set_attr "type" "branch")
-+ (set_attr "length" "8")])
-+
-+(define_insn "*call_value_nonlocal_aix<mode>"
-+ [(set (match_operand 0 "" "")
-+ (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
-+ (match_operand 2 "" "g")))
-+ (clobber (reg:P LR_REGNO))]
-+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
-+ "bl %z1\;nop"
-+ [(set_attr "type" "branch")
-+ (set_attr "length" "8")])
-+
-+;; Call to indirect functions with the AIX abi using a 3 word descriptor.
-+;; Operand0 is the addresss of the function to call
-+;; Operand2 is the location in the function descriptor to load r2 from
-+;; Operand3 is the stack location to hold the current TOC pointer
-+
-+(define_insn "*call_indirect_aix<mode>"
-+ [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
-+ (match_operand 1 "" "g,g"))
-+ (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
-+ (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
-+ (clobber (reg:P LR_REGNO))]
-+ "DEFAULT_ABI == ABI_AIX"
-+ "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
-+ [(set_attr "type" "jmpreg")
-+ (set_attr "length" "12")])
-+
-+(define_insn "*call_value_indirect_aix<mode>"
-+ [(set (match_operand 0 "" "")
-+ (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
-+ (match_operand 2 "" "g,g")))
-+ (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
-+ (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
-+ (clobber (reg:P LR_REGNO))]
-+ "DEFAULT_ABI == ABI_AIX"
-+ "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
-+ [(set_attr "type" "jmpreg")
-+ (set_attr "length" "12")])
-+
-+;; Call to indirect functions with the ELFv2 ABI.
-+;; Operand0 is the addresss of the function to call
-+;; Operand2 is the stack location to hold the current TOC pointer
-+
-+(define_insn "*call_indirect_elfv2<mode>"
-+ [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
-+ (match_operand 1 "" "g,g"))
-+ (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
-+ (clobber (reg:P LR_REGNO))]
-+ "DEFAULT_ABI == ABI_ELFv2"
-+ "b%T0l\;<ptrload> 2,%2"
-+ [(set_attr "type" "jmpreg")
-+ (set_attr "length" "8")])
-+
-+(define_insn "*call_value_indirect_elfv2<mode>"
-+ [(set (match_operand 0 "" "")
-+ (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
-+ (match_operand 2 "" "g,g")))
-+ (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
-+ (clobber (reg:P LR_REGNO))]
-+ "DEFAULT_ABI == ABI_ELFv2"
-+ "b%T1l\;<ptrload> 2,%3"
-+ [(set_attr "type" "jmpreg")
-+ (set_attr "length" "8")])
-+
-+
- ;; Call subroutine returning any type.
- (define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
-@@ -11056,8 +12718,41 @@
- gcc_assert (GET_CODE (operands[1]) == CONST_INT);
-
- operands[0] = XEXP (operands[0], 0);
-+
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ {
-+ rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
-+ DONE;
-+ }
- }")
-
-+(define_expand "sibcall_value"
-+ [(parallel [(set (match_operand 0 "register_operand" "")
-+ (call (mem:SI (match_operand 1 "address_operand" ""))
-+ (match_operand 2 "" "")))
-+ (use (match_operand 3 "" ""))
-+ (use (reg:SI LR_REGNO))
-+ (simple_return)])]
-+ ""
-+ "
-+{
-+#if TARGET_MACHO
-+ if (MACHOPIC_INDIRECT)
-+ operands[1] = machopic_indirect_call_target (operands[1]);
-+#endif
-+
-+ gcc_assert (GET_CODE (operands[1]) == MEM);
-+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);
-+
-+ operands[1] = XEXP (operands[1], 0);
-+
-+ if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
-+ {
-+ rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
-+ DONE;
-+ }
-+}")
-+
- ;; this and similar patterns must be marked as using LR, otherwise
- ;; dataflow will try to delete the store into it. This is true
- ;; even when the actual reg to jump to is in CTR, when LR was
-@@ -11123,7 +12818,6 @@
- [(set_attr "type" "branch")
- (set_attr "length" "4,8")])
-
--
- (define_insn "*sibcall_value_local64"
- [(set (match_operand 0 "" "")
- (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
-@@ -11145,35 +12839,6 @@
- [(set_attr "type" "branch")
- (set_attr "length" "4,8")])
-
--(define_insn "*sibcall_nonlocal_aix<mode>"
-- [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
-- (match_operand 1 "" "g,g"))
-- (use (match_operand:SI 2 "immediate_operand" "O,O"))
-- (use (reg:SI LR_REGNO))
-- (simple_return)]
-- "DEFAULT_ABI == ABI_AIX
-- && (INTVAL (operands[2]) & CALL_LONG) == 0"
-- "@
-- b %z0
-- b%T0"
-- [(set_attr "type" "branch")
-- (set_attr "length" "4")])
--
--(define_insn "*sibcall_value_nonlocal_aix<mode>"
-- [(set (match_operand 0 "" "")
-- (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
-- (match_operand 2 "" "g,g")))
-- (use (match_operand:SI 3 "immediate_operand" "O,O"))
-- (use (reg:SI LR_REGNO))
-- (simple_return)]
-- "DEFAULT_ABI == ABI_AIX
-- && (INTVAL (operands[3]) & CALL_LONG) == 0"
-- "@
-- b %z1
-- b%T1"
-- [(set_attr "type" "branch")
-- (set_attr "length" "4")])
--
- (define_insn "*sibcall_nonlocal_sysv<mode>"
- [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
- (match_operand 1 "" ""))
-@@ -11204,27 +12869,6 @@
- [(set_attr "type" "branch")
- (set_attr "length" "4,8,4,8")])
-
--(define_expand "sibcall_value"
-- [(parallel [(set (match_operand 0 "register_operand" "")
-- (call (mem:SI (match_operand 1 "address_operand" ""))
-- (match_operand 2 "" "")))
-- (use (match_operand 3 "" ""))
-- (use (reg:SI LR_REGNO))
-- (simple_return)])]
-- ""
-- "
--{
--#if TARGET_MACHO
-- if (MACHOPIC_INDIRECT)
-- operands[1] = machopic_indirect_call_target (operands[1]);
--#endif
--
-- gcc_assert (GET_CODE (operands[1]) == MEM);
-- gcc_assert (GET_CODE (operands[2]) == CONST_INT);
--
-- operands[1] = XEXP (operands[1], 0);
--}")
--
- (define_insn "*sibcall_value_nonlocal_sysv<mode>"
- [(set (match_operand 0 "" "")
- (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
-@@ -11256,6 +12900,31 @@
- [(set_attr "type" "branch")
- (set_attr "length" "4,8,4,8")])
-
-+;; AIX ABI sibling call patterns.
-+
-+(define_insn "*sibcall_aix<mode>"
-+ [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
-+ (match_operand 1 "" "g,g"))
-+ (simple_return)]
-+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
-+ "@
-+ b %z0
-+ b%T0"
-+ [(set_attr "type" "branch")
-+ (set_attr "length" "4")])
-+
-+(define_insn "*sibcall_value_aix<mode>"
-+ [(set (match_operand 0 "" "")
-+ (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
-+ (match_operand 2 "" "g,g")))
-+ (simple_return)]
-+ "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
-+ "@
-+ b %z1
-+ b%T1"
-+ [(set_attr "type" "branch")
-+ (set_attr "length" "4")])
-+
- (define_expand "sibcall_epilogue"
- [(use (const_int 0))]
- ""
-@@ -11294,7 +12963,14 @@
- operands[1] = gen_rtx_REG (Pmode, 0);
- return "st<wd>%U0%X0 %1,%0";
- }
-- [(set_attr "type" "store")
-+ [(set (attr "type")
-+ (if_then_else
-+ (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_ux")
-+ (if_then_else
-+ (match_test "update_address_mem (operands[0], VOIDmode)")
-+ (const_string "store_u")
-+ (const_string "store"))))
- (set_attr "length" "4")])
-
- (define_insn "probe_stack_range<P:mode>"
-@@ -11589,23 +13265,6 @@
- [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
-
--(define_insn "*cmpsf_internal1"
-- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-- (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
-- (match_operand:SF 2 "gpc_reg_operand" "f")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-- "fcmpu %0,%1,%2"
-- [(set_attr "type" "fpcompare")])
--
--(define_insn "*cmpdf_internal1"
-- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-- (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
-- (match_operand:DF 2 "gpc_reg_operand" "d")))]
-- "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-- && !VECTOR_UNIT_VSX_P (DFmode)"
-- "fcmpu %0,%1,%2"
-- [(set_attr "type" "fpcompare")])
--
- ;; Only need to compare second words if first words equal
- (define_insn "*cmptf_internal1"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-@@ -13501,6 +15160,14 @@
- "mfcr %0"
- [(set_attr "type" "mfcr")])
-
-+(define_insn "*crsave"
-+ [(match_parallel 0 "crsave_operation"
-+ [(set (match_operand:SI 1 "memory_operand" "=m")
-+ (match_operand:SI 2 "gpc_reg_operand" "r"))])]
-+ ""
-+ "stw %2,%1"
-+ [(set_attr "type" "store")])
-+
- (define_insn "*stmw"
- [(match_parallel 0 "stmw_operation"
- [(set (match_operand:SI 1 "memory_operand" "=m")
-@@ -13885,7 +15552,7 @@
- (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
- "TARGET_POPCNTD"
- "bpermd %0,%1,%2"
-- [(set_attr "type" "integer")])
-+ [(set_attr "type" "popcnt")])
-
-
- ;; Builtin fma support. Handle
-@@ -13900,6 +15567,20 @@
- ""
- "")
-
-+(define_insn "*fma<mode>4_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
-+ (fma:SFDF
-+ (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
-+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fmadd<Ftrad> %0,%1,%2,%3
-+ xsmadda<Fvsx> %x0,%x1,%x2
-+ xsmaddm<Fvsx> %x0,%x1,%x3"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_maddsub_<Fs>")])
-+
- ; Altivec only has fma and nfms.
- (define_expand "fms<mode>4"
- [(set (match_operand:FMA_F 0 "register_operand" "")
-@@ -13910,6 +15591,20 @@
- "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
- "")
-
-+(define_insn "*fms<mode>4_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
-+ (fma:SFDF
-+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
-+ (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fmsub<Ftrad> %0,%1,%2,%3
-+ xsmsuba<Fvsx> %x0,%x1,%x2
-+ xsmsubm<Fvsx> %x0,%x1,%x3"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_maddsub_<Fs>")])
-+
- ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
- (define_expand "fnma<mode>4"
- [(set (match_operand:FMA_F 0 "register_operand" "")
-@@ -13943,6 +15638,21 @@
- "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
- "")
-
-+(define_insn "*nfma<mode>4_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
-+ (neg:SFDF
-+ (fma:SFDF
-+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
-+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fnmadd<Ftrad> %0,%1,%2,%3
-+ xsnmadda<Fvsx> %x0,%x1,%x2
-+ xsnmaddm<Fvsx> %x0,%x1,%x3"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_maddsub_<Fs>")])
-+
- ; Not an official optab name, but used from builtins.
- (define_expand "nfms<mode>4"
- [(set (match_operand:FMA_F 0 "register_operand" "")
-@@ -13954,6 +15664,23 @@
- ""
- "")
-
-+(define_insn "*nfmssf4_fpr"
-+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
-+ (neg:SFDF
-+ (fma:SFDF
-+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
-+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
-+ (neg:SFDF
-+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
-+ "TARGET_<MODE>_FPR"
-+ "@
-+ fnmsub<Ftrad> %0,%1,%2,%3
-+ xsnmsuba<Fvsx> %x0,%x1,%x2
-+ xsnmsubm<Fvsx> %x0,%x1,%x3"
-+ [(set_attr "type" "fp")
-+ (set_attr "fp_type" "fp_maddsub_<Fs>")])
-+
-+
- (define_expand "rs6000_get_timebase"
- [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
- ""
-@@ -14020,7 +15747,229 @@
- })
-
-
-+;; Power8 fusion support for fusing an addis instruction with a D-form load of
-+;; a GPR. The addis instruction must be adjacent to the load, and use the same
-+;; register that is being loaded. The fused ops must be physically adjacent.
-
-+;; We use define_peephole for the actual addis/load, and the register used to
-+;; hold the addis value must be the same as the register being loaded. We use
-+;; define_peephole2 to change the register used for addis to be the register
-+;; being loaded, since we can look at whether it is dead after the load insn.
-+
-+(define_peephole
-+ [(set (match_operand:P 0 "base_reg_operand" "")
-+ (match_operand:P 1 "fusion_gpr_addis" ""))
-+ (set (match_operand:INT1 2 "base_reg_operand" "")
-+ (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
-+ "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
-+{
-+ return emit_fusion_gpr_load (operands);
-+}
-+ [(set_attr "type" "load")
-+ (set_attr "length" "8")])
-+
-+(define_peephole2
-+ [(set (match_operand:P 0 "base_reg_operand" "")
-+ (match_operand:P 1 "fusion_gpr_addis" ""))
-+ (set (match_operand:INT1 2 "base_reg_operand" "")
-+ (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
-+ "TARGET_P8_FUSION
-+ && (REGNO (operands[0]) != REGNO (operands[2])
-+ || GET_CODE (operands[3]) == SIGN_EXTEND)
-+ && fusion_gpr_load_p (operands, true)"
-+ [(const_int 0)]
-+{
-+ expand_fusion_gpr_load (operands);
-+ DONE;
-+})
-+
-+
-+;; Miscellaneous ISA 2.06 (power7) instructions
-+(define_insn "addg6s"
-+ [(set (match_operand:SI 0 "register_operand" "=r")
-+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
-+ (match_operand:SI 2 "register_operand" "r")]
-+ UNSPEC_ADDG6S))]
-+ "TARGET_POPCNTD"
-+ "addg6s %0,%1,%2"
-+ [(set_attr "type" "integer")
-+ (set_attr "length" "4")])
-+
-+(define_insn "cdtbcd"
-+ [(set (match_operand:SI 0 "register_operand" "=r")
-+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
-+ UNSPEC_CDTBCD))]
-+ "TARGET_POPCNTD"
-+ "cdtbcd %0,%1"
-+ [(set_attr "type" "integer")
-+ (set_attr "length" "4")])
-+
-+(define_insn "cbcdtd"
-+ [(set (match_operand:SI 0 "register_operand" "=r")
-+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
-+ UNSPEC_CBCDTD))]
-+ "TARGET_POPCNTD"
-+ "cbcdtd %0,%1"
-+ [(set_attr "type" "integer")
-+ (set_attr "length" "4")])
-+
-+(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
-+ UNSPEC_DIVEO
-+ UNSPEC_DIVEU
-+ UNSPEC_DIVEUO])
-+
-+(define_int_attr div_extend [(UNSPEC_DIVE "e")
-+ (UNSPEC_DIVEO "eo")
-+ (UNSPEC_DIVEU "eu")
-+ (UNSPEC_DIVEUO "euo")])
-+
-+(define_insn "div<div_extend>_<mode>"
-+ [(set (match_operand:GPR 0 "register_operand" "=r")
-+ (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
-+ (match_operand:GPR 2 "register_operand" "r")]
-+ UNSPEC_DIV_EXTEND))]
-+ "TARGET_POPCNTD"
-+ "div<wd><div_extend> %0,%1,%2"
-+ [(set_attr "type" "<idiv_ldiv>")])
-+
-+
-+;; Pack/unpack 128-bit floating point types that take 2 scalar registers
-+
-+; Type of the 64-bit part when packing/unpacking 128-bit floating point types
-+(define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
-+
-+(define_expand "unpack<mode>"
-+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
-+ (unspec:<FP128_64>
-+ [(match_operand:FMOVE128 1 "register_operand" "")
-+ (match_operand:QI 2 "const_0_to_1_operand" "")]
-+ UNSPEC_UNPACK_128BIT))]
-+ ""
-+ "")
-+
-+;; The Advance Toolchain 7.0-3 added private builtins: __builtin_longdouble_dw0
-+;; and __builtin_longdouble_dw1 to optimize glibc. Add support for these
-+;; builtins here.
-+
-+(define_expand "unpacktf_0"
-+ [(set (match_operand:DF 0 "nonimmediate_operand" "")
-+ (unspec:DF [(match_operand:TF 1 "register_operand" "")
-+ (const_int 0)]
-+ UNSPEC_UNPACK_128BIT))]
-+ ""
-+ "")
-+
-+(define_expand "unpacktf_1"
-+ [(set (match_operand:DF 0 "nonimmediate_operand" "")
-+ (unspec:DF [(match_operand:TF 1 "register_operand" "")
-+ (const_int 1)]
-+ UNSPEC_UNPACK_128BIT))]
-+ ""
-+ "")
-+
-+(define_insn_and_split "unpack<mode>_dm"
-+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
-+ (unspec:<FP128_64>
-+ [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
-+ (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
-+ UNSPEC_UNPACK_128BIT))]
-+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
-+ "#"
-+ "&& reload_completed"
-+ [(set (match_dup 0) (match_dup 3))]
-+{
-+ unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
-+
-+ if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
-+ {
-+ emit_note (NOTE_INSN_DELETED);
-+ DONE;
-+ }
-+
-+ operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
-+}
-+ [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
-+ (set_attr "length" "4")])
-+
-+(define_insn_and_split "unpack<mode>_nodm"
-+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
-+ (unspec:<FP128_64>
-+ [(match_operand:FMOVE128 1 "register_operand" "d,d")
-+ (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
-+ UNSPEC_UNPACK_128BIT))]
-+ "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
-+ "#"
-+ "&& reload_completed"
-+ [(set (match_dup 0) (match_dup 3))]
-+{
-+ unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
-+
-+ if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
-+ {
-+ emit_note (NOTE_INSN_DELETED);
-+ DONE;
-+ }
-+
-+ operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
-+}
-+ [(set_attr "type" "fp,fpstore")
-+ (set_attr "length" "4")])
-+
-+(define_insn_and_split "pack<mode>"
-+ [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
-+ (unspec:FMOVE128
-+ [(match_operand:<FP128_64> 1 "register_operand" "0,d")
-+ (match_operand:<FP128_64> 2 "register_operand" "d,d")]
-+ UNSPEC_PACK_128BIT))]
-+ ""
-+ "@
-+ fmr %L0,%2
-+ #"
-+ "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
-+ [(set (match_dup 3) (match_dup 1))
-+ (set (match_dup 4) (match_dup 2))]
-+{
-+ unsigned dest_hi = REGNO (operands[0]);
-+ unsigned dest_lo = dest_hi + 1;
-+
-+ gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
-+ gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
-+
-+ operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
-+ operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
-+}
-+ [(set_attr "type" "fp,fp")
-+ (set_attr "length" "4,8")])
-+
-+(define_insn "unpackv1ti"
-+ [(set (match_operand:DI 0 "register_operand" "=d,d")
-+ (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
-+ (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
-+ UNSPEC_UNPACK_128BIT))]
-+ "TARGET_VSX"
-+{
-+ if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
-+ return ASM_COMMENT_START " xxpermdi to same register";
-+
-+ operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
-+ return "xxpermdi %x0,%x1,%x1,%3";
-+}
-+ [(set_attr "type" "vecperm")
-+ (set_attr "length" "4")])
-+
-+(define_insn "packv1ti"
-+ [(set (match_operand:V1TI 0 "register_operand" "=wa")
-+ (unspec:V1TI
-+ [(match_operand:DI 1 "register_operand" "d")
-+ (match_operand:DI 2 "register_operand" "d")]
-+ UNSPEC_PACK_128BIT))]
-+ "TARGET_VSX"
-+ "xxpermdi %x0,%x1,%x2,0"
-+ [(set_attr "type" "vecperm")
-+ (set_attr "length" "4")])
-+
-+
-+
- (include "sync.md")
- (include "vector.md")
- (include "vsx.md")
-@@ -14028,3 +15977,5 @@
- (include "spe.md")
- (include "dfp.md")
- (include "paired.md")
-+(include "crypto.md")
-+(include "htm.md")
-Index: gcc/config/rs6000/t-linux64le
-===================================================================
---- a/src/gcc/config/rs6000/t-linux64le (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/t-linux64le (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,3 @@
-+#rs6000/t-linux64le
-+
-+MULTILIB_OSDIRNAMES := $(subst -linux,le-linux,$(MULTILIB_OSDIRNAMES))
-Index: gcc/config/rs6000/t-linux64lebe
-===================================================================
---- a/src/gcc/config/rs6000/t-linux64lebe (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/t-linux64lebe (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,7 @@
-+#rs6000/t-linux64leend
-+
-+MULTILIB_OPTIONS += mbig
-+MULTILIB_DIRNAMES += be
-+MULTILIB_OSDIRNAMES += $(subst =,.mbig=,$(subst libbe32,lib32be,$(subst libbe64,lib64be,$(subst lib,libbe,$(subst le-linux,-linux,$(MULTILIB_OSDIRNAMES))))))
-+MULTILIB_OSDIRNAMES += $(subst $(if $(findstring 64,$(target)),m64,m32).,,$(filter $(if $(findstring 64,$(target)),m64,m32).mbig%,$(MULTILIB_OSDIRNAMES)))
-+MULTILIB_MATCHES := ${MULTILIB_MATCHES_ENDIAN}
-Index: gcc/config/rs6000/rs6000-opts.h
-===================================================================
---- a/src/gcc/config/rs6000/rs6000-opts.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/rs6000-opts.h (.../branches/gcc-4_8-branch)
-@@ -59,7 +59,8 @@
- PROCESSOR_POWER7,
- PROCESSOR_CELL,
- PROCESSOR_PPCA2,
-- PROCESSOR_TITAN
-+ PROCESSOR_TITAN,
-+ PROCESSOR_POWER8
- };
-
- /* FP processor type. */
-@@ -100,7 +101,8 @@
- /* Enumeration to give which calling sequence to use. */
- enum rs6000_abi {
- ABI_NONE,
-- ABI_AIX, /* IBM's AIX */
-+ ABI_AIX, /* IBM's AIX, or Linux ELFv1 */
-+ ABI_ELFv2, /* Linux ELFv2 ABI */
- ABI_V4, /* System V.4/eabi */
- ABI_DARWIN /* Apple's Darwin (OS X kernel) */
- };
-@@ -131,11 +133,14 @@
- CMODEL_LARGE
- };
-
--/* Describe which vector unit to use for a given machine mode. */
-+/* Describe which vector unit to use for a given machine mode. The
-+ VECTOR_MEM_* and VECTOR_UNIT_* macros assume that Altivec, VSX, and
-+ P8_VECTOR are contiguous. */
- enum rs6000_vector {
- VECTOR_NONE, /* Type is not a vector or not supported */
- VECTOR_ALTIVEC, /* Use altivec for vector processing */
- VECTOR_VSX, /* Use VSX for vector processing */
-+ VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */
- VECTOR_PAIRED, /* Use paired floating point for vectors */
- VECTOR_SPE, /* Use SPE for vector processing */
- VECTOR_OTHER /* Some other vector unit */
-Index: gcc/config/rs6000/option-defaults.h
-===================================================================
---- a/src/gcc/config/rs6000/option-defaults.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/option-defaults.h (.../branches/gcc-4_8-branch)
-@@ -54,6 +54,7 @@
- --with-float is ignored if -mhard-float or -msoft-float are
- specified. */
- #define OPTION_DEFAULT_SPECS \
-+ {"abi", "%{!mabi=elfv*:-mabi=%(VALUE)}" }, \
- {"tune", "%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}" }, \
- {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \
- {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \
-Index: gcc/config/rs6000/altivec.h
-===================================================================
---- a/src/gcc/config/rs6000/altivec.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/altivec.h (.../branches/gcc-4_8-branch)
-@@ -319,8 +319,58 @@
- #define vec_sqrt __builtin_vec_sqrt
- #define vec_vsx_ld __builtin_vec_vsx_ld
- #define vec_vsx_st __builtin_vec_vsx_st
-+
-+/* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions
-+ instead of __builtin_vec_<xxx> */
-+#define vec_xxsldwi __builtin_vsx_xxsldwi
-+#define vec_xxpermdi __builtin_vsx_xxpermdi
- #endif
-
-+#ifdef _ARCH_PWR8
-+/* Vector additions added in ISA 2.07. */
-+#define vec_eqv __builtin_vec_eqv
-+#define vec_nand __builtin_vec_nand
-+#define vec_orc __builtin_vec_orc
-+#define vec_vaddcuq __builtin_vec_vaddcuq
-+#define vec_vaddudm __builtin_vec_vaddudm
-+#define vec_vadduqm __builtin_vec_vadduqm
-+#define vec_vbpermq __builtin_vec_vbpermq
-+#define vec_vclz __builtin_vec_vclz
-+#define vec_vclzb __builtin_vec_vclzb
-+#define vec_vclzd __builtin_vec_vclzd
-+#define vec_vclzh __builtin_vec_vclzh
-+#define vec_vclzw __builtin_vec_vclzw
-+#define vec_vaddecuq __builtin_vec_vaddecuq
-+#define vec_vaddeuqm __builtin_vec_vaddeuqm
-+#define vec_vsubecuq __builtin_vec_vsubecuq
-+#define vec_vsubeuqm __builtin_vec_vsubeuqm
-+#define vec_vgbbd __builtin_vec_vgbbd
-+#define vec_vmaxsd __builtin_vec_vmaxsd
-+#define vec_vmaxud __builtin_vec_vmaxud
-+#define vec_vminsd __builtin_vec_vminsd
-+#define vec_vminud __builtin_vec_vminud
-+#define vec_vmrgew __builtin_vec_vmrgew
-+#define vec_vmrgow __builtin_vec_vmrgow
-+#define vec_vpksdss __builtin_vec_vpksdss
-+#define vec_vpksdus __builtin_vec_vpksdus
-+#define vec_vpkudum __builtin_vec_vpkudum
-+#define vec_vpkudus __builtin_vec_vpkudus
-+#define vec_vpopcnt __builtin_vec_vpopcnt
-+#define vec_vpopcntb __builtin_vec_vpopcntb
-+#define vec_vpopcntd __builtin_vec_vpopcntd
-+#define vec_vpopcnth __builtin_vec_vpopcnth
-+#define vec_vpopcntw __builtin_vec_vpopcntw
-+#define vec_vrld __builtin_vec_vrld
-+#define vec_vsld __builtin_vec_vsld
-+#define vec_vsrad __builtin_vec_vsrad
-+#define vec_vsrd __builtin_vec_vsrd
-+#define vec_vsubcuq __builtin_vec_vsubcuq
-+#define vec_vsubudm __builtin_vec_vsubudm
-+#define vec_vsubuqm __builtin_vec_vsubuqm
-+#define vec_vupkhsw __builtin_vec_vupkhsw
-+#define vec_vupklsw __builtin_vec_vupklsw
-+#endif
-+
- /* Predicates.
- For C++, we use templates in order to allow non-parenthesized arguments.
- For C, instead, we use macros since non-parenthesized arguments were
-Index: gcc/config/rs6000/sysv4.h
-===================================================================
---- a/src/gcc/config/rs6000/sysv4.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/rs6000/sysv4.h (.../branches/gcc-4_8-branch)
-@@ -45,7 +45,7 @@
- & (OPTION_MASK_RELOCATABLE \
- | OPTION_MASK_MINIMAL_TOC)) \
- && flag_pic > 1) \
-- || DEFAULT_ABI == ABI_AIX)
-+ || DEFAULT_ABI != ABI_V4)
-
- #define TARGET_BITFIELD_TYPE (! TARGET_NO_BITFIELD_TYPE)
- #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
-@@ -147,7 +147,7 @@
- rs6000_sdata_name); \
- } \
- \
-- else if (flag_pic && DEFAULT_ABI != ABI_AIX \
-+ else if (flag_pic && DEFAULT_ABI == ABI_V4 \
- && (rs6000_sdata == SDATA_EABI \
- || rs6000_sdata == SDATA_SYSV)) \
- { \
-@@ -173,7 +173,7 @@
- error ("-mrelocatable and -mno-minimal-toc are incompatible"); \
- } \
- \
-- if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \
-+ if (TARGET_RELOCATABLE && rs6000_current_abi != ABI_V4) \
- { \
- rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \
- error ("-mrelocatable and -mcall-%s are incompatible", \
-@@ -180,7 +180,7 @@
- rs6000_abi_name); \
- } \
- \
-- if (!TARGET_64BIT && flag_pic > 1 && rs6000_current_abi == ABI_AIX) \
-+ if (!TARGET_64BIT && flag_pic > 1 && rs6000_current_abi != ABI_V4) \
- { \
- flag_pic = 0; \
- error ("-fPIC and -mcall-%s are incompatible", \
-@@ -193,7 +193,7 @@
- } \
- \
- /* Treat -fPIC the same as -mrelocatable. */ \
-- if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \
-+ if (flag_pic > 1 && DEFAULT_ABI == ABI_V4) \
- { \
- rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \
- TARGET_NO_FP_IN_TOC = 1; \
-@@ -317,7 +317,7 @@
-
- /* Put PC relative got entries in .got2. */
- #define MINIMAL_TOC_SECTION_ASM_OP \
-- (TARGET_RELOCATABLE || (flag_pic && DEFAULT_ABI != ABI_AIX) \
-+ (TARGET_RELOCATABLE || (flag_pic && DEFAULT_ABI == ABI_V4) \
- ? "\t.section\t\".got2\",\"aw\"" : "\t.section\t\".got1\",\"aw\"")
-
- #define SDATA_SECTION_ASM_OP "\t.section\t\".sdata\",\"aw\""
-@@ -522,8 +522,6 @@
- #define ENDIAN_SELECT(BIG_OPT, LITTLE_OPT, DEFAULT_OPT) \
- "%{mlittle|mlittle-endian:" LITTLE_OPT ";" \
- "mbig|mbig-endian:" BIG_OPT ";" \
-- "mcall-aixdesc|mcall-freebsd|mcall-netbsd|" \
-- "mcall-openbsd|mcall-linux:" BIG_OPT ";" \
- "mcall-i960-old:" LITTLE_OPT ";" \
- ":" DEFAULT_OPT "}"
-
-@@ -536,25 +534,12 @@
- %{memb|msdata=eabi: -memb}" \
- ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
-
--#define CC1_ENDIAN_BIG_SPEC ""
--
--#define CC1_ENDIAN_LITTLE_SPEC "\
--%{!mstrict-align: %{!mno-strict-align: \
-- %{!mcall-i960-old: \
-- -mstrict-align \
-- } \
--}}"
--
--#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big)"
--
- #ifndef CC1_SECURE_PLT_DEFAULT_SPEC
- #define CC1_SECURE_PLT_DEFAULT_SPEC ""
- #endif
-
--/* Pass -G xxx to the compiler and set correct endian mode. */
-+/* Pass -G xxx to the compiler. */
- #define CC1_SPEC "%{G*} %(cc1_cpu)" \
-- ENDIAN_SELECT(" %(cc1_endian_big)", " %(cc1_endian_little)", \
-- " %(cc1_endian_default)") \
- "%{meabi: %{!mcall-*: -mcall-sysv }} \
- %{!meabi: %{!mno-eabi: \
- %{mrelocatable: -meabi } \
-@@ -908,9 +893,6 @@
- { "link_os_netbsd", LINK_OS_NETBSD_SPEC }, \
- { "link_os_openbsd", LINK_OS_OPENBSD_SPEC }, \
- { "link_os_default", LINK_OS_DEFAULT_SPEC }, \
-- { "cc1_endian_big", CC1_ENDIAN_BIG_SPEC }, \
-- { "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \
-- { "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \
- { "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \
- { "cpp_os_ads", CPP_OS_ADS_SPEC }, \
- { "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \
-Index: gcc/config/darwin.c
-===================================================================
---- a/src/gcc/config/darwin.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/darwin.c (.../branches/gcc-4_8-branch)
-@@ -1329,6 +1329,9 @@
- return NULL_TREE;
- }
-
-+static int classes_seen;
-+static int objc_metadata_seen;
-+
- /* Return the section required for Objective C ABI 2 metadata. */
- static section *
- darwin_objc2_section (tree decl ATTRIBUTE_UNUSED, tree meta, section * base)
-@@ -1338,12 +1341,9 @@
- gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE);
- p = IDENTIFIER_POINTER (ident);
-
-- /* If we are in LTO, then we don't know the state of flag_next_runtime
-- or flag_objc_abi when the code was generated. We set these from the
-- meta-data - which is needed to deal with const string constructors. */
-+ gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi == 2);
-
-- flag_next_runtime = 1;
-- flag_objc_abi = 2;
-+ objc_metadata_seen = 1;
-
- if (base == data_section)
- base = darwin_sections[objc2_metadata_section];
-@@ -1366,7 +1366,10 @@
- else if (!strncmp (p, "V2_NLCL", 7))
- return darwin_sections[objc2_nonlazy_class_section];
- else if (!strncmp (p, "V2_CLAB", 7))
-- return darwin_sections[objc2_classlist_section];
-+ {
-+ classes_seen = 1;
-+ return darwin_sections[objc2_classlist_section];
-+ }
- else if (!strncmp (p, "V2_SRFS", 7))
- return darwin_sections[objc2_selector_refs_section];
- else if (!strncmp (p, "V2_NLCA", 7))
-@@ -1401,13 +1404,10 @@
- gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE);
- p = IDENTIFIER_POINTER (ident);
-
-- /* If we are in LTO, then we don't know the state of flag_next_runtime
-- or flag_objc_abi when the code was generated. We set these from the
-- meta-data - which is needed to deal with const string constructors. */
-- flag_next_runtime = 1;
-- if (!global_options_set.x_flag_objc_abi)
-- flag_objc_abi = 1;
-+ gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi < 2);
-
-+ objc_metadata_seen = 1;
-+
- /* String sections first, cos there are lots of strings. */
- if (!strncmp (p, "V1_STRG", 7))
- return darwin_sections[cstring_section];
-@@ -1419,7 +1419,10 @@
- return darwin_sections[objc_meth_var_types_section];
-
- else if (!strncmp (p, "V1_CLAS", 7))
-- return darwin_sections[objc_class_section];
-+ {
-+ classes_seen = 1;
-+ return darwin_sections[objc_class_section];
-+ }
- else if (!strncmp (p, "V1_META", 7))
- return darwin_sections[objc_meta_class_section];
- else if (!strncmp (p, "V1_CATG", 7))
-@@ -1603,8 +1606,6 @@
- if (TREE_CODE (name) == TYPE_DECL)
- name = DECL_NAME (name);
-
-- /* FIXME: This is unsatisfactory for LTO, since it relies on other
-- metadata determining the source FE. */
- if (!strcmp (IDENTIFIER_POINTER (name), "__builtin_ObjCString"))
- {
- if (flag_next_runtime)
-@@ -2845,6 +2846,33 @@
- finalize_ctors ();
- if (!vec_safe_is_empty (dtors))
- finalize_dtors ();
-+
-+ /* If we are expecting to output NeXT ObjC meta-data, (and we actually see
-+ some) then we output the fix-and-continue marker (Image Info).
-+ This applies to Objective C, Objective C++ and LTO with either language
-+ as part of the input. */
-+ if (flag_next_runtime && objc_metadata_seen)
-+ {
-+ unsigned int flags = 0;
-+ if (flag_objc_abi >= 2)
-+ {
-+ flags = 16;
-+ output_section_asm_op
-+ (darwin_sections[objc2_image_info_section]->unnamed.data);
-+ }
-+ else
-+ output_section_asm_op
-+ (darwin_sections[objc_image_info_section]->unnamed.data);
-+
-+ ASM_OUTPUT_ALIGN (asm_out_file, 2);
-+ fputs ("L_OBJC_ImageInfo:\n", asm_out_file);
-+
-+ flags |= (flag_replace_objc_classes && classes_seen) ? 1 : 0;
-+ flags |= flag_objc_gc ? 2 : 0;
-+
-+ fprintf (asm_out_file, "\t.long\t0\n\t.long\t%u\n", flags);
-+ }
-+
- machopic_finish (asm_out_file);
- if (strcmp (lang_hooks.name, "GNU C++") == 0)
- {
-Index: gcc/config/tilepro/tilepro-c.c
-===================================================================
---- a/src/gcc/config/tilepro/tilepro-c.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/tilepro/tilepro-c.c (.../branches/gcc-4_8-branch)
-@@ -44,6 +44,11 @@
- builtin_define ("__tile_chip__=1");
- builtin_define ("__tile_chip_rev__=0");
-
-+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
-+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
-+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
-+ builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
-+
- TILEPRO_CPU_CPP_ENDIAN_BUILTINS ();
- GNU_USER_TARGET_OS_CPP_BUILTINS ();
- }
-Index: gcc/config/tilepro/tilepro.c
-===================================================================
---- a/src/gcc/config/tilepro/tilepro.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/tilepro/tilepro.c (.../branches/gcc-4_8-branch)
-@@ -3167,6 +3167,12 @@
- }
- if (!pat)
- return NULL_RTX;
-+
-+ /* If we are generating a prefetch, tell the scheduler not to move
-+ it around. */
-+ if (GET_CODE (pat) == PREFETCH)
-+ PREFETCH_SCHEDULE_BARRIER_P (pat) = true;
-+
- emit_insn (pat);
-
- if (nonvoid)
-Index: gcc/config/tilepro/tilepro.md
-===================================================================
---- a/src/gcc/config/tilepro/tilepro.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/tilepro/tilepro.md (.../branches/gcc-4_8-branch)
-@@ -795,7 +795,7 @@
-
- (define_expand "ctzdi2"
- [(set (match_operand:DI 0 "register_operand" "")
-- (ctz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
-+ (ctz:DI (match_operand:DI 1 "register_operand" "")))]
- ""
- {
- rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, result;
-@@ -823,7 +823,7 @@
-
- (define_expand "clzdi2"
- [(set (match_operand:DI 0 "register_operand" "")
-- (clz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
-+ (clz:DI (match_operand:DI 1 "register_operand" "")))]
- ""
- {
- rtx lo, hi, clz_lo, clz_hi, clz_lo_plus_32, result;
-@@ -851,7 +851,7 @@
-
- (define_expand "ffsdi2"
- [(set (match_operand:DI 0 "register_operand" "")
-- (ffs:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
-+ (ffs:DI (match_operand:DI 1 "register_operand" "")))]
- ""
- {
- rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, ctz, ctz_plus_1,ctz_cond;
-Index: gcc/config/arm/arm.c
-===================================================================
---- a/src/gcc/config/arm/arm.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/arm/arm.c (.../branches/gcc-4_8-branch)
-@@ -230,7 +230,6 @@
- static void arm_option_override (void);
- static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
- static bool arm_cannot_copy_insn_p (rtx);
--static bool arm_tls_symbol_p (rtx x);
- static int arm_issue_rate (void);
- static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
- static bool arm_output_addr_const_extra (FILE *, rtx);
-@@ -5425,7 +5424,8 @@
- if (!crtl->uses_pic_offset_table)
- {
- gcc_assert (can_create_pseudo_p ());
-- if (arm_pic_register != INVALID_REGNUM)
-+ if (arm_pic_register != INVALID_REGNUM
-+ && !(TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM))
- {
- if (!cfun->machine->pic_reg)
- cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
-@@ -5451,7 +5451,12 @@
- crtl->uses_pic_offset_table = 1;
- start_sequence ();
-
-- arm_load_pic_register (0UL);
-+ if (TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM
-+ && arm_pic_register > LAST_LO_REGNUM)
-+ emit_move_insn (cfun->machine->pic_reg,
-+ gen_rtx_REG (Pmode, arm_pic_register));
-+ else
-+ arm_load_pic_register (0UL);
-
- seq = get_insns ();
- end_sequence ();
-@@ -5709,6 +5714,14 @@
- emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
- emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));
- }
-+ else if (arm_pic_register != INVALID_REGNUM
-+ && arm_pic_register > LAST_LO_REGNUM
-+ && REGNO (pic_reg) <= LAST_LO_REGNUM)
-+ {
-+ emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));
-+ emit_move_insn (gen_rtx_REG (Pmode, arm_pic_register), pic_reg);
-+ emit_use (gen_rtx_REG (Pmode, arm_pic_register));
-+ }
- else
- emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));
- }
-@@ -6573,6 +6586,32 @@
- rtx
- arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
- {
-+ if (arm_tls_referenced_p (x))
-+ {
-+ rtx addend = NULL;
-+
-+ if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
-+ {
-+ addend = XEXP (XEXP (x, 0), 1);
-+ x = XEXP (XEXP (x, 0), 0);
-+ }
-+
-+ if (GET_CODE (x) != SYMBOL_REF)
-+ return x;
-+
-+ gcc_assert (SYMBOL_REF_TLS_MODEL (x) != 0);
-+
-+ x = legitimize_tls_address (x, NULL_RTX);
-+
-+ if (addend)
-+ {
-+ x = gen_rtx_PLUS (SImode, x, addend);
-+ orig_x = x;
-+ }
-+ else
-+ return x;
-+ }
-+
- if (!TARGET_ARM)
- {
- /* TODO: legitimize_address for Thumb2. */
-@@ -6581,9 +6620,6 @@
- return thumb_legitimize_address (x, orig_x, mode);
- }
-
-- if (arm_tls_symbol_p (x))
-- return legitimize_tls_address (x, NULL_RTX);
--
- if (GET_CODE (x) == PLUS)
- {
- rtx xop0 = XEXP (x, 0);
-@@ -6695,9 +6731,6 @@
- rtx
- thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
- {
-- if (arm_tls_symbol_p (x))
-- return legitimize_tls_address (x, NULL_RTX);
--
- if (GET_CODE (x) == PLUS
- && CONST_INT_P (XEXP (x, 1))
- && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
-@@ -6988,20 +7021,6 @@
-
- /* Test for various thread-local symbols. */
-
--/* Return TRUE if X is a thread-local symbol. */
--
--static bool
--arm_tls_symbol_p (rtx x)
--{
-- if (! TARGET_HAVE_TLS)
-- return false;
--
-- if (GET_CODE (x) != SYMBOL_REF)
-- return false;
--
-- return SYMBOL_REF_TLS_MODEL (x) != 0;
--}
--
- /* Helper for arm_tls_referenced_p. */
-
- static int
-@@ -21279,7 +21298,11 @@
- type_mode);
- }
-
-- op[argc] = expand_normal (arg[argc]);
-+ /* Use EXPAND_MEMORY for NEON_ARG_MEMORY to ensure a MEM_P
-+ be returned. */
-+ op[argc] = expand_expr (arg[argc], NULL_RTX, VOIDmode,
-+ (thisarg == NEON_ARG_MEMORY
-+ ? EXPAND_MEMORY : EXPAND_NORMAL));
-
- switch (thisarg)
- {
-@@ -21298,6 +21321,9 @@
- break;
-
- case NEON_ARG_MEMORY:
-+ /* Check if expand failed. */
-+ if (op[argc] == const0_rtx)
-+ return 0;
- gcc_assert (MEM_P (op[argc]));
- PUT_MODE (op[argc], mode[argc]);
- /* ??? arm_neon.h uses the same built-in functions for signed
-@@ -23555,6 +23581,7 @@
- num_regs = bit_count (saved_regs_mask);
- if ((offsets->outgoing_args != (1 + num_regs)) || cfun->calls_alloca)
- {
-+ emit_insn (gen_blockage ());
- /* Unwind the stack to just below the saved registers. */
- emit_insn (gen_addsi3 (stack_pointer_rtx,
- hard_frame_pointer_rtx,
-@@ -23583,8 +23610,8 @@
-
- if (crtl->calls_eh_return)
- emit_insn (gen_addsi3 (stack_pointer_rtx,
-- stack_pointer_rtx,
-- GEN_INT (ARM_EH_STACKADJ_REGNUM)));
-+ stack_pointer_rtx,
-+ gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)));
-
- if (IS_STACKALIGN (func_type))
- /* Restore the original stack pointer. Before prologue, the stack was
-Index: gcc/config/arm/arm.h
-===================================================================
---- a/src/gcc/config/arm/arm.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/arm/arm.h (.../branches/gcc-4_8-branch)
-@@ -1213,11 +1213,15 @@
- VFPv2.
- In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
- VFP registers in little-endian order. We can't describe that accurately to
-- GCC, so avoid taking subregs of such values. */
--#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
-- (TARGET_VFP && TARGET_BIG_END \
-- && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
-- || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
-+ GCC, so avoid taking subregs of such values.
-+ The only exception is going from a 128-bit to a 64-bit type. In that case
-+ the data layout happens to be consistent for big-endian, so we explicitly allow
-+ that case. */
-+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
-+ (TARGET_VFP && TARGET_BIG_END \
-+ && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \
-+ && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
-+ || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
- && reg_classes_intersect_p (VFP_REGS, (CLASS)))
-
- /* The class value for index registers, and the one for base regs. */
-@@ -2139,14 +2143,9 @@
- #undef ASM_OUTPUT_BEFORE_CASE_LABEL
- #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */
-
--/* Make sure subsequent insns are aligned after a TBB. */
--#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
-- do \
-- { \
-- if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
-- ASM_OUTPUT_ALIGN (FILE, 1); \
-- } \
-- while (0)
-+#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
-+ (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
-+ ? 1 : 0)
-
- #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
- do \
-Index: gcc/config/arm/vfp.md
-===================================================================
---- a/src/gcc/config/arm/vfp.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/arm/vfp.md (.../branches/gcc-4_8-branch)
-@@ -1264,6 +1264,7 @@
- "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
- "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
- [(set_attr "predicable" "<vrint_predicable>")
-+ (set_attr "conds" "<vrint_conds>")
- (set_attr "type" "f_rint<vfp_type>")]
- )
-
-@@ -1280,7 +1281,8 @@
- (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
- "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
- "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-- [(set_attr "type" "f_minmax<vfp_type>")]
-+ [(set_attr "type" "f_minmax<vfp_type>")
-+ (set_attr "conds" "unconditional")]
- )
-
- (define_insn "smin<mode>3"
-@@ -1289,7 +1291,8 @@
- (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
- "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
- "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-- [(set_attr "type" "f_minmax<vfp_type>")]
-+ [(set_attr "type" "f_minmax<vfp_type>")
-+ (set_attr "conds" "unconditional")]
- )
-
- ;; Unimplemented insns:
-Index: gcc/config/arm/ldmstm.md
-===================================================================
---- a/src/gcc/config/arm/ldmstm.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/arm/ldmstm.md (.../branches/gcc-4_8-branch)
-@@ -23,15 +23,15 @@
-
- (define_insn "*ldm4_ia"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (match_operand:SI 5 "s_register_operand" "rk")))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 8))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 12))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
-@@ -41,15 +41,15 @@
-
- (define_insn "*thumb_ldm4_ia"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "low_register_operand" "")
- (mem:SI (match_operand:SI 5 "s_register_operand" "l")))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 8))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 12))))])]
- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
-@@ -60,15 +60,15 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 5 "s_register_operand" "+&rk")
- (plus:SI (match_dup 5) (const_int 16)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (match_dup 5)))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 8))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 12))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
-@@ -80,15 +80,15 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 5 "s_register_operand" "+&l")
- (plus:SI (match_dup 5) (const_int 16)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "low_register_operand" "")
- (mem:SI (match_dup 5)))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 8))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 12))))])]
- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
-@@ -98,13 +98,13 @@
- (define_insn "*stm4_ia"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
-- (match_operand:SI 4 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
- "stm%(ia%)\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
-@@ -115,13 +115,13 @@
- [(set (match_operand:SI 5 "s_register_operand" "+&rk")
- (plus:SI (match_dup 5) (const_int 16)))
- (set (mem:SI (match_dup 5))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
-- (match_operand:SI 4 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
- "stm%(ia%)\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
-@@ -132,13 +132,13 @@
- [(set (match_operand:SI 5 "s_register_operand" "+&l")
- (plus:SI (match_dup 5) (const_int 16)))
- (set (mem:SI (match_dup 5))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "low_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "low_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))
-+ (match_operand:SI 3 "low_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
-- (match_operand:SI 4 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 4 "low_register_operand" ""))])]
- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
- "stm%(ia%)\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")])
-@@ -145,16 +145,16 @@
-
- (define_insn "*ldm4_ib"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
- (const_int 4))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 8))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 12))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 16))))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
-@@ -166,16 +166,16 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 5 "s_register_operand" "+&rk")
- (plus:SI (match_dup 5) (const_int 16)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 4))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 8))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 12))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int 16))))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
-@@ -186,13 +186,13 @@
- (define_insn "*stm4_ib"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
-- (match_operand:SI 4 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
- "stm%(ib%)\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
-@@ -203,13 +203,13 @@
- [(set (match_operand:SI 5 "s_register_operand" "+&rk")
- (plus:SI (match_dup 5) (const_int 16)))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
-- (match_operand:SI 4 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
- "stm%(ib%)\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
-@@ -217,16 +217,16 @@
-
- (define_insn "*ldm4_da"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
- (const_int -12))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -8))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -4))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
- (mem:SI (match_dup 5)))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
- "ldm%(da%)\t%5, {%1, %2, %3, %4}"
-@@ -237,16 +237,16 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 5 "s_register_operand" "+&rk")
- (plus:SI (match_dup 5) (const_int -16)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -12))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -8))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -4))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
- (mem:SI (match_dup 5)))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
- "ldm%(da%)\t%5!, {%1, %2, %3, %4}"
-@@ -256,13 +256,13 @@
- (define_insn "*stm4_da"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))
- (set (mem:SI (match_dup 5))
-- (match_operand:SI 4 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
- "stm%(da%)\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
-@@ -273,13 +273,13 @@
- [(set (match_operand:SI 5 "s_register_operand" "+&rk")
- (plus:SI (match_dup 5) (const_int -16)))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))
- (set (mem:SI (match_dup 5))
-- (match_operand:SI 4 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
- "stm%(da%)\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
-@@ -287,16 +287,16 @@
-
- (define_insn "*ldm4_db"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
- (const_int -16))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -12))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -8))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -4))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
-@@ -308,16 +308,16 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 5 "s_register_operand" "+&rk")
- (plus:SI (match_dup 5) (const_int -16)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -16))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -12))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -8))))
-- (set (match_operand:SI 4 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 5)
- (const_int -4))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
-@@ -328,13 +328,13 @@
- (define_insn "*stm4_db"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
-- (match_operand:SI 4 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
- "stm%(db%)\t%5, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
-@@ -345,13 +345,13 @@
- [(set (match_operand:SI 5 "s_register_operand" "+&rk")
- (plus:SI (match_dup 5) (const_int -16)))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -16)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
-- (match_operand:SI 4 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
- "stm%(db%)\t%5!, {%1, %2, %3, %4}"
- [(set_attr "type" "store4")
-@@ -466,12 +466,12 @@
-
- (define_insn "*ldm3_ia"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (match_operand:SI 4 "s_register_operand" "rk")))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 8))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
-@@ -481,12 +481,12 @@
-
- (define_insn "*thumb_ldm3_ia"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "low_register_operand" "")
- (mem:SI (match_operand:SI 4 "s_register_operand" "l")))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 8))))])]
- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
-@@ -497,12 +497,12 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 4 "s_register_operand" "+&rk")
- (plus:SI (match_dup 4) (const_int 12)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (match_dup 4)))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 8))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
-@@ -514,12 +514,12 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 4 "s_register_operand" "+&l")
- (plus:SI (match_dup 4) (const_int 12)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "low_register_operand" "")
- (mem:SI (match_dup 4)))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 8))))])]
- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
-@@ -529,11 +529,11 @@
- (define_insn "*stm3_ia"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
- "stm%(ia%)\t%4, {%1, %2, %3}"
- [(set_attr "type" "store3")
-@@ -544,11 +544,11 @@
- [(set (match_operand:SI 4 "s_register_operand" "+&rk")
- (plus:SI (match_dup 4) (const_int 12)))
- (set (mem:SI (match_dup 4))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
- "stm%(ia%)\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")
-@@ -559,11 +559,11 @@
- [(set (match_operand:SI 4 "s_register_operand" "+&l")
- (plus:SI (match_dup 4) (const_int 12)))
- (set (mem:SI (match_dup 4))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "low_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "low_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 3 "low_register_operand" ""))])]
- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
- "stm%(ia%)\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")])
-@@ -570,13 +570,13 @@
-
- (define_insn "*ldm3_ib"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
- (const_int 4))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 8))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 12))))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
-@@ -588,13 +588,13 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 4 "s_register_operand" "+&rk")
- (plus:SI (match_dup 4) (const_int 12)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 4))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 8))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int 12))))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
-@@ -605,11 +605,11 @@
- (define_insn "*stm3_ib"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
- "stm%(ib%)\t%4, {%1, %2, %3}"
- [(set_attr "type" "store3")
-@@ -620,11 +620,11 @@
- [(set (match_operand:SI 4 "s_register_operand" "+&rk")
- (plus:SI (match_dup 4) (const_int 12)))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
- "stm%(ib%)\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")
-@@ -632,13 +632,13 @@
-
- (define_insn "*ldm3_da"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
- (const_int -8))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int -4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (match_dup 4)))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
- "ldm%(da%)\t%4, {%1, %2, %3}"
-@@ -649,13 +649,13 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 4 "s_register_operand" "+&rk")
- (plus:SI (match_dup 4) (const_int -12)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int -8))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int -4))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (match_dup 4)))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
- "ldm%(da%)\t%4!, {%1, %2, %3}"
-@@ -665,11 +665,11 @@
- (define_insn "*stm3_da"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (match_dup 4))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
- "stm%(da%)\t%4, {%1, %2, %3}"
- [(set_attr "type" "store3")
-@@ -680,11 +680,11 @@
- [(set (match_operand:SI 4 "s_register_operand" "+&rk")
- (plus:SI (match_dup 4) (const_int -12)))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (match_dup 4))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
- "stm%(da%)\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")
-@@ -692,13 +692,13 @@
-
- (define_insn "*ldm3_db"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
- (const_int -12))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int -8))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int -4))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
-@@ -710,13 +710,13 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 4 "s_register_operand" "+&rk")
- (plus:SI (match_dup 4) (const_int -12)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int -12))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int -8))))
-- (set (match_operand:SI 3 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 4)
- (const_int -4))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
-@@ -727,11 +727,11 @@
- (define_insn "*stm3_db"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
- "stm%(db%)\t%4, {%1, %2, %3}"
- [(set_attr "type" "store3")
-@@ -742,11 +742,11 @@
- [(set (match_operand:SI 4 "s_register_operand" "+&rk")
- (plus:SI (match_dup 4) (const_int -12)))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -12)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
-- (match_operand:SI 3 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
- "stm%(db%)\t%4!, {%1, %2, %3}"
- [(set_attr "type" "store3")
-@@ -847,9 +847,9 @@
-
- (define_insn "*ldm2_ia"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (match_operand:SI 3 "s_register_operand" "rk")))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int 4))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
-@@ -859,9 +859,9 @@
-
- (define_insn "*thumb_ldm2_ia"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "low_register_operand" "")
- (mem:SI (match_operand:SI 3 "s_register_operand" "l")))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int 4))))])]
- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"
-@@ -872,9 +872,9 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 3 "s_register_operand" "+&rk")
- (plus:SI (match_dup 3) (const_int 8)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (match_dup 3)))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int 4))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
-@@ -886,9 +886,9 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 3 "s_register_operand" "+&l")
- (plus:SI (match_dup 3) (const_int 8)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "low_register_operand" "")
- (mem:SI (match_dup 3)))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "low_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int 4))))])]
- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
-@@ -898,9 +898,9 @@
- (define_insn "*stm2_ia"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
- "stm%(ia%)\t%3, {%1, %2}"
- [(set_attr "type" "store2")
-@@ -911,9 +911,9 @@
- [(set (match_operand:SI 3 "s_register_operand" "+&rk")
- (plus:SI (match_dup 3) (const_int 8)))
- (set (mem:SI (match_dup 3))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
- "stm%(ia%)\t%3!, {%1, %2}"
- [(set_attr "type" "store2")
-@@ -924,9 +924,9 @@
- [(set (match_operand:SI 3 "s_register_operand" "+&l")
- (plus:SI (match_dup 3) (const_int 8)))
- (set (mem:SI (match_dup 3))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "low_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 2 "low_register_operand" ""))])]
- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
- "stm%(ia%)\t%3!, {%1, %2}"
- [(set_attr "type" "store2")])
-@@ -933,10 +933,10 @@
-
- (define_insn "*ldm2_ib"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
- (const_int 4))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int 8))))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
-@@ -948,10 +948,10 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 3 "s_register_operand" "+&rk")
- (plus:SI (match_dup 3) (const_int 8)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int 4))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int 8))))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
-@@ -962,9 +962,9 @@
- (define_insn "*stm2_ib"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
- "stm%(ib%)\t%3, {%1, %2}"
- [(set_attr "type" "store2")
-@@ -975,9 +975,9 @@
- [(set (match_operand:SI 3 "s_register_operand" "+&rk")
- (plus:SI (match_dup 3) (const_int 8)))
- (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
- "stm%(ib%)\t%3!, {%1, %2}"
- [(set_attr "type" "store2")
-@@ -985,10 +985,10 @@
-
- (define_insn "*ldm2_da"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
- (const_int -4))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (match_dup 3)))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
- "ldm%(da%)\t%3, {%1, %2}"
-@@ -999,10 +999,10 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 3 "s_register_operand" "+&rk")
- (plus:SI (match_dup 3) (const_int -8)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int -4))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (match_dup 3)))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
- "ldm%(da%)\t%3!, {%1, %2}"
-@@ -1012,9 +1012,9 @@
- (define_insn "*stm2_da"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (match_dup 3))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
- "stm%(da%)\t%3, {%1, %2}"
- [(set_attr "type" "store2")
-@@ -1025,9 +1025,9 @@
- [(set (match_operand:SI 3 "s_register_operand" "+&rk")
- (plus:SI (match_dup 3) (const_int -8)))
- (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (match_dup 3))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
- "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
- "stm%(da%)\t%3!, {%1, %2}"
- [(set_attr "type" "store2")
-@@ -1035,10 +1035,10 @@
-
- (define_insn "*ldm2_db"
- [(match_parallel 0 "load_multiple_operation"
-- [(set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
- (const_int -8))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int -4))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
-@@ -1050,10 +1050,10 @@
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 3 "s_register_operand" "+&rk")
- (plus:SI (match_dup 3) (const_int -8)))
-- (set (match_operand:SI 1 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int -8))))
-- (set (match_operand:SI 2 "arm_hard_register_operand" "")
-+ (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
- (mem:SI (plus:SI (match_dup 3)
- (const_int -4))))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
-@@ -1064,9 +1064,9 @@
- (define_insn "*stm2_db"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
- "stm%(db%)\t%3, {%1, %2}"
- [(set_attr "type" "store2")
-@@ -1077,9 +1077,9 @@
- [(set (match_operand:SI 3 "s_register_operand" "+&rk")
- (plus:SI (match_dup 3) (const_int -8)))
- (set (mem:SI (plus:SI (match_dup 3) (const_int -8)))
-- (match_operand:SI 1 "arm_hard_register_operand" ""))
-+ (match_operand:SI 1 "arm_hard_general_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
-- (match_operand:SI 2 "arm_hard_register_operand" ""))])]
-+ (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
- "stm%(db%)\t%3!, {%1, %2}"
- [(set_attr "type" "store2")
-Index: gcc/config/arm/predicates.md
-===================================================================
---- a/src/gcc/config/arm/predicates.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/arm/predicates.md (.../branches/gcc-4_8-branch)
-@@ -31,11 +31,11 @@
- || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
- })
-
--;; Any hard register.
--(define_predicate "arm_hard_register_operand"
-+;; Any general register.
-+(define_predicate "arm_hard_general_register_operand"
- (match_code "reg")
- {
-- return REGNO (op) < FIRST_PSEUDO_REGISTER;
-+ return REGNO (op) <= LAST_ARM_REGNUM;
- })
-
- ;; A low register.
-@@ -76,6 +76,12 @@
- && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
- })
-
-+(define_predicate "vfp_hard_register_operand"
-+ (match_code "reg")
-+{
-+ return (IS_VFP_REGNUM (REGNO (op)));
-+})
-+
- (define_predicate "zero_operand"
- (and (match_code "const_int,const_double,const_vector")
- (match_test "op == CONST0_RTX (mode)")))
-Index: gcc/config/arm/arm-ldmstm.ml
-===================================================================
---- a/src/gcc/config/arm/arm-ldmstm.ml (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/arm/arm-ldmstm.ml (.../branches/gcc-4_8-branch)
-@@ -67,10 +67,13 @@
- Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")")
- (nregs + 1) (inout_constr op_type) (constr thumb)
-
-+let reg_predicate thumb =
-+ if thumb then "low_register_operand" else "arm_hard_general_register_operand"
-+
- let write_ldm_set thumb nregs offset opnr first =
- let indent = " " in
- Printf.printf "%s" (if first then " [" else indent);
-- Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr;
-+ Printf.printf "(set (match_operand:SI %d \"%s\" \"\")\n" opnr (reg_predicate thumb);
- Printf.printf "%s (mem:SI " indent;
- begin if offset != 0 then Printf.printf "(plus:SI " end;
- Printf.printf "%s" (destreg nregs first IN thumb);
-@@ -84,7 +87,7 @@
- begin if offset != 0 then Printf.printf "(plus:SI " end;
- Printf.printf "%s" (destreg nregs first IN thumb);
- begin if offset != 0 then Printf.printf " (const_int %d))" offset end;
-- Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr
-+ Printf.printf ")\n%s (match_operand:SI %d \"%s\" \"\"))" indent opnr (reg_predicate thumb)
-
- let write_ldm_peep_set extra_indent nregs opnr first =
- let indent = " " ^ extra_indent in
-Index: gcc/config/arm/iterators.md
-===================================================================
---- a/src/gcc/config/arm/iterators.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/arm/iterators.md (.../branches/gcc-4_8-branch)
-@@ -493,6 +493,10 @@
- (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
- (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
-
-+(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional")
-+ (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")
-+ (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")])
-+
- (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p")
- (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m")
- (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")])
-Index: gcc/config/arm/arm.md
-===================================================================
---- a/src/gcc/config/arm/arm.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/arm/arm.md (.../branches/gcc-4_8-branch)
-@@ -11036,7 +11036,7 @@
- [(set (match_operand:SI 1 "s_register_operand" "+rk")
- (plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_operand" "I")))
-- (set (match_operand:DF 3 "arm_hard_register_operand" "")
-+ (set (match_operand:DF 3 "vfp_hard_register_operand" "")
- (mem:DF (match_dup 1)))])]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
- "*
-@@ -11270,7 +11270,9 @@
- (match_operand:SI 1 "" "")
- (match_operand:SI 2 "" ""))]
- "TARGET_32BIT && arm_arch5e"
-- "pld\\t%a0")
-+ "pld\\t%a0"
-+ [(set_attr "type" "load1")]
-+)
-
- ;; General predication pattern
-
-Index: gcc/config/pa/pa.c
-===================================================================
---- a/src/gcc/config/pa/pa.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/pa/pa.c (.../branches/gcc-4_8-branch)
-@@ -912,9 +912,12 @@
- legitimize_tls_address (rtx addr)
- {
- rtx ret, insn, tmp, t1, t2, tp;
-- enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
-
-- switch (model)
-+ /* Currently, we can't handle anything but a SYMBOL_REF. */
-+ if (GET_CODE (addr) != SYMBOL_REF)
-+ return addr;
-+
-+ switch (SYMBOL_REF_TLS_MODEL (addr))
- {
- case TLS_MODEL_GLOBAL_DYNAMIC:
- tmp = gen_reg_rtx (Pmode);
-@@ -1035,7 +1038,7 @@
- && !REG_POINTER (XEXP (x, 1)))
- return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
-
-- if (PA_SYMBOL_REF_TLS_P (x))
-+ if (pa_tls_referenced_p (x))
- return legitimize_tls_address (x);
- else if (flag_pic)
- return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
-@@ -1916,9 +1919,10 @@
- not consider them legitimate constants. Loop optimizations can
- call the emit_move_xxx with one as a source. */
- if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
-+ || (GET_CODE (operand1) == HIGH
-+ && symbolic_operand (XEXP (operand1, 0), mode))
- || function_label_operand (operand1, VOIDmode)
-- || (GET_CODE (operand1) == HIGH
-- && symbolic_operand (XEXP (operand1, 0), mode)))
-+ || pa_tls_referenced_p (operand1))
- {
- int ishighonly = 0;
-
-@@ -2625,7 +2629,7 @@
- if (optype0 == REGOP)
- latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else if (optype0 == OFFSOP)
-- latehalf[0] = adjust_address (operands[0], SImode, 4);
-+ latehalf[0] = adjust_address_nv (operands[0], SImode, 4);
- else
- latehalf[0] = operands[0];
-
-@@ -2632,7 +2636,7 @@
- if (optype1 == REGOP)
- latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- else if (optype1 == OFFSOP)
-- latehalf[1] = adjust_address (operands[1], SImode, 4);
-+ latehalf[1] = adjust_address_nv (operands[1], SImode, 4);
- else if (optype1 == CNSTOP)
- split_double (operands[1], &operands[1], &latehalf[1]);
- else
-@@ -7539,7 +7543,7 @@
- if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET)
- return 8;
-
-- if (TARGET_LONG_ABS_CALL && !flag_pic)
-+ if (!flag_pic)
- return 12;
-
- return 24;
-@@ -8104,7 +8108,8 @@
- return 12;
-
- if (TARGET_FAST_INDIRECT_CALLS
-- || (!TARGET_PORTABLE_RUNTIME
-+ || (!TARGET_LONG_CALLS
-+ && !TARGET_PORTABLE_RUNTIME
- && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
- || distance < MAX_PCREL17F_OFFSET)))
- return 8;
-@@ -10397,7 +10402,7 @@
- /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not
- legitimate constants. The other variants can't be handled by
- the move patterns after reload starts. */
-- if (PA_SYMBOL_REF_TLS_P (x))
-+ if (pa_tls_referenced_p (x))
- return false;
-
- if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE)
-@@ -10522,13 +10527,13 @@
-
- /* When INT14_OK_STRICT is false, a secondary reload is needed
- to adjust the displacement of SImode and DImode floating point
-- instructions. So, we return false when STRICT is true. We
-+ instructions but this may fail when the register also needs
-+ reloading. So, we return false when STRICT is true. We
- also reject long displacements for float mode addresses since
- the majority of accesses will use floating point instructions
- that don't support 14-bit offsets. */
- if (!INT14_OK_STRICT
-- && reload_in_progress
-- && strict
-+ && (strict || !(reload_in_progress || reload_completed))
- && mode != QImode
- && mode != HImode)
- return false;
-@@ -10588,8 +10593,7 @@
- return true;
-
- if (!INT14_OK_STRICT
-- && reload_in_progress
-- && strict
-+ && (strict || !(reload_in_progress || reload_completed))
- && mode != QImode
- && mode != HImode)
- return false;
-Index: gcc/config/pa/pa.h
-===================================================================
---- a/src/gcc/config/pa/pa.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/pa/pa.h (.../branches/gcc-4_8-branch)
-@@ -784,9 +784,9 @@
-
- #define MAX_REGS_PER_ADDRESS 2
-
--/* Non-TLS symbolic references. */
--#define PA_SYMBOL_REF_TLS_P(RTX) \
-- (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
-+/* TLS symbolic reference. */
-+#define PA_SYMBOL_REF_TLS_P(X) \
-+ (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (X) != 0)
-
- /* Recognize any constant value that is a valid address except
- for symbolic addresses. We get better CSE by rejecting them
-@@ -796,7 +796,8 @@
- #define CONSTANT_ADDRESS_P(X) \
- ((GET_CODE (X) == LABEL_REF \
- || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
-- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
-+ || GET_CODE (X) == CONST_INT \
-+ || (GET_CODE (X) == CONST && !pa_tls_referenced_p (X)) \
- || GET_CODE (X) == HIGH) \
- && (reload_in_progress || reload_completed \
- || ! pa_symbolic_expression_p (X)))
-Index: gcc/config/mips/driver-native.c
-===================================================================
---- a/src/gcc/config/mips/driver-native.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/mips/driver-native.c (.../branches/gcc-4_8-branch)
-@@ -58,11 +58,17 @@
- if (strncmp (buf, "cpu model", sizeof ("cpu model") - 1) == 0)
- {
- if (strstr (buf, "Godson2 V0.2") != NULL
-- || strstr (buf, "Loongson-2 V0.2") != NULL)
-+ || strstr (buf, "Loongson-2 V0.2") != NULL
-+ || strstr (buf, "Loongson-2E") != NULL)
- cpu = "loongson2e";
- else if (strstr (buf, "Godson2 V0.3") != NULL
-- || strstr (buf, "Loongson-2 V0.3") != NULL)
-+ || strstr (buf, "Loongson-2 V0.3") != NULL
-+ || strstr (buf, "Loongson-2F") != NULL)
- cpu = "loongson2f";
-+ else if (strstr (buf, "Godson3 V0.5") != NULL
-+ || strstr (buf, "Loongson-3 V0.5") != NULL
-+ || strstr (buf, "Loongson-3A") != NULL)
-+ cpu = "loongson3a";
- else if (strstr (buf, "SiByte SB1") != NULL)
- cpu = "sb1";
- else if (strstr (buf, "R5000") != NULL)
-Index: gcc/config/mips/mips.md
-===================================================================
---- a/src/gcc/config/mips/mips.md (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/mips/mips.md (.../branches/gcc-4_8-branch)
-@@ -73,6 +73,11 @@
- UNSPEC_STORE_LEFT
- UNSPEC_STORE_RIGHT
-
-+ ;; Integer operations that are too cumbersome to describe directly.
-+ UNSPEC_WSBH
-+ UNSPEC_DSBH
-+ UNSPEC_DSHD
-+
- ;; Floating-point moves.
- UNSPEC_LOAD_LOW
- UNSPEC_LOAD_HIGH
-@@ -1294,20 +1299,32 @@
-
- ;; Combiner patterns for unsigned byte-add.
-
--(define_insn "*baddu_si"
-+(define_insn "*baddu_si_eb"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI
-- (plus:QI (match_operand:QI 1 "register_operand" "d")
-- (match_operand:QI 2 "register_operand" "d"))))]
-- "ISA_HAS_BADDU"
-+ (subreg:QI
-+ (plus:SI (match_operand:SI 1 "register_operand" "d")
-+ (match_operand:SI 2 "register_operand" "d")) 3)))]
-+ "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
- "baddu\\t%0,%1,%2"
- [(set_attr "alu_type" "add")])
-
-+(define_insn "*baddu_si_el"
-+ [(set (match_operand:SI 0 "register_operand" "=d")
-+ (zero_extend:SI
-+ (subreg:QI
-+ (plus:SI (match_operand:SI 1 "register_operand" "d")
-+ (match_operand:SI 2 "register_operand" "d")) 0)))]
-+ "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
-+ "baddu\\t%0,%1,%2"
-+ [(set_attr "alu_type" "add")])
-+
- (define_insn "*baddu_di<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (zero_extend:GPR
-- (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d"))
-- (truncate:QI (match_operand:DI 2 "register_operand" "d")))))]
-+ (truncate:QI
-+ (plus:DI (match_operand:DI 1 "register_operand" "d")
-+ (match_operand:DI 2 "register_operand" "d")))))]
- "ISA_HAS_BADDU && TARGET_64BIT"
- "baddu\\t%0,%1,%2"
- [(set_attr "alu_type" "add")])
-@@ -5367,6 +5384,56 @@
- }
- [(set_attr "type" "shift")
- (set_attr "mode" "<MODE>")])
-+
-+(define_insn "bswaphi2"
-+ [(set (match_operand:HI 0 "register_operand" "=d")
-+ (bswap:HI (match_operand:HI 1 "register_operand" "d")))]
-+ "ISA_HAS_WSBH"
-+ "wsbh\t%0,%1"
-+ [(set_attr "type" "shift")])
-+
-+(define_insn_and_split "bswapsi2"
-+ [(set (match_operand:SI 0 "register_operand" "=d")
-+ (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
-+ "ISA_HAS_WSBH && ISA_HAS_ROR"
-+ "#"
-+ ""
-+ [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))
-+ (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
-+ ""
-+ [(set_attr "length" "8")])
-+
-+(define_insn_and_split "bswapdi2"
-+ [(set (match_operand:DI 0 "register_operand" "=d")
-+ (bswap:DI (match_operand:DI 1 "register_operand" "d")))]
-+ "TARGET_64BIT && ISA_HAS_WSBH"
-+ "#"
-+ ""
-+ [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH))
-+ (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))]
-+ ""
-+ [(set_attr "length" "8")])
-+
-+(define_insn "wsbh"
-+ [(set (match_operand:SI 0 "register_operand" "=d")
-+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))]
-+ "ISA_HAS_WSBH"
-+ "wsbh\t%0,%1"
-+ [(set_attr "type" "shift")])
-+
-+(define_insn "dsbh"
-+ [(set (match_operand:DI 0 "register_operand" "=d")
-+ (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))]
-+ "TARGET_64BIT && ISA_HAS_WSBH"
-+ "dsbh\t%0,%1"
-+ [(set_attr "type" "shift")])
-+
-+(define_insn "dshd"
-+ [(set (match_operand:DI 0 "register_operand" "=d")
-+ (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))]
-+ "TARGET_64BIT && ISA_HAS_WSBH"
-+ "dshd\t%0,%1"
-+ [(set_attr "type" "shift")])
-
- ;;
- ;; ....................
-Index: gcc/config/mips/mips.c
-===================================================================
---- a/src/gcc/config/mips/mips.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/mips/mips.c (.../branches/gcc-4_8-branch)
-@@ -3560,17 +3560,6 @@
- }
- }
-
--/* Return the cost of an operand X that can be trucated for free.
-- SPEED says whether we're optimizing for size or speed. */
--
--static int
--mips_truncated_op_cost (rtx x, bool speed)
--{
-- if (GET_CODE (x) == TRUNCATE)
-- x = XEXP (x, 0);
-- return set_src_cost (x, speed);
--}
--
- /* Implement TARGET_RTX_COSTS. */
-
- static bool
-@@ -3951,13 +3940,12 @@
- case ZERO_EXTEND:
- if (outer_code == SET
- && ISA_HAS_BADDU
-+ && (GET_CODE (XEXP (x, 0)) == TRUNCATE
-+ || GET_CODE (XEXP (x, 0)) == SUBREG)
- && GET_MODE (XEXP (x, 0)) == QImode
-- && GET_CODE (XEXP (x, 0)) == PLUS)
-+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
- {
-- rtx plus = XEXP (x, 0);
-- *total = (COSTS_N_INSNS (1)
-- + mips_truncated_op_cost (XEXP (plus, 0), speed)
-- + mips_truncated_op_cost (XEXP (plus, 1), speed));
-+ *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
- return true;
- }
- *total = mips_zero_extend_cost (mode, XEXP (x, 0));
-@@ -8057,7 +8045,7 @@
- case 't':
- {
- int truth = (code == NE) == (letter == 'T');
-- fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
-+ fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
- }
- break;
-
-Index: gcc/config/mips/mips.h
-===================================================================
---- a/src/gcc/config/mips/mips.h (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/config/mips/mips.h (.../branches/gcc-4_8-branch)
-@@ -949,6 +949,11 @@
- || TARGET_SMARTMIPS) \
- && !TARGET_MIPS16)
-
-+/* ISA has the WSBH (word swap bytes within halfwords) instruction.
-+ 64-bit targets also provide DSBH and DSHD. */
-+#define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \
-+ && !TARGET_MIPS16)
-+
- /* ISA has data prefetch instructions. This controls use of 'pref'. */
- #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
- || TARGET_LOONGSON_2EF \
-Index: gcc/stmt.c
-===================================================================
---- a/src/gcc/stmt.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/stmt.c (.../branches/gcc-4_8-branch)
-@@ -1602,19 +1602,28 @@
- #ifdef HAVE_nonlocal_goto
- if (! HAVE_nonlocal_goto)
- #endif
-- /* First adjust our frame pointer to its actual value. It was
-- previously set to the start of the virtual area corresponding to
-- the stacked variables when we branched here and now needs to be
-- adjusted to the actual hardware fp value.
-+ {
-+ /* First adjust our frame pointer to its actual value. It was
-+ previously set to the start of the virtual area corresponding to
-+ the stacked variables when we branched here and now needs to be
-+ adjusted to the actual hardware fp value.
-
-- Assignments are to virtual registers are converted by
-- instantiate_virtual_regs into the corresponding assignment
-- to the underlying register (fp in this case) that makes
-- the original assignment true.
-- So the following insn will actually be
-- decrementing fp by STARTING_FRAME_OFFSET. */
-- emit_move_insn (virtual_stack_vars_rtx, hard_frame_pointer_rtx);
-+ Assignments to virtual registers are converted by
-+ instantiate_virtual_regs into the corresponding assignment
-+ to the underlying register (fp in this case) that makes
-+ the original assignment true.
-+ So the following insn will actually be decrementing fp by
-+ STARTING_FRAME_OFFSET. */
-+ emit_move_insn (virtual_stack_vars_rtx, hard_frame_pointer_rtx);
-
-+ /* Restoring the frame pointer also modifies the hard frame pointer.
-+ Mark it used (so that the previous assignment remains live once
-+ the frame pointer is eliminated) and clobbered (to represent the
-+ implicit update from the assignment). */
-+ emit_use (hard_frame_pointer_rtx);
-+ emit_clobber (hard_frame_pointer_rtx);
-+ }
-+
- #if !HARD_FRAME_POINTER_IS_ARG_POINTER
- if (fixed_regs[ARG_POINTER_REGNUM])
- {
-Index: gcc/params.def
-===================================================================
---- a/src/gcc/params.def (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/params.def (.../branches/gcc-4_8-branch)
-@@ -1014,6 +1014,12 @@
- "strength reduction",
- 50, 1, 999999)
-
-+DEFPARAM (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS,
-+ "uninit-control-dep-attempts",
-+ "Maximum number of nested calls to search for control dependencies "
-+ "during uninitialized variable analysis",
-+ 1000, 1, 0)
-+
- /*
- Local variables:
- mode:c
-Index: gcc/tree-ssanames.c
-===================================================================
---- a/src/gcc/tree-ssanames.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssanames.c (.../branches/gcc-4_8-branch)
-@@ -128,7 +128,7 @@
-
- /* The node was cleared out when we put it on the free list, so
- there is no need to do so again here. */
-- gcc_assert (ssa_name (SSA_NAME_VERSION (t)) == NULL);
-+ gcc_assert ((*SSANAMES (fn))[SSA_NAME_VERSION (t)] == NULL);
- (*SSANAMES (fn))[SSA_NAME_VERSION (t)] = t;
- }
- else
-Index: gcc/regcprop.c
-===================================================================
---- a/src/gcc/regcprop.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/regcprop.c (.../branches/gcc-4_8-branch)
-@@ -747,6 +747,7 @@
- int n_ops, i, alt, predicated;
- bool is_asm, any_replacements;
- rtx set;
-+ rtx link;
- bool replaced[MAX_RECOG_OPERANDS];
- bool changed = false;
- struct kill_set_value_data ksvd;
-@@ -815,6 +816,23 @@
- if (recog_op_alt[i][alt].earlyclobber)
- kill_value (recog_data.operand[i], vd);
-
-+ /* If we have dead sets in the insn, then we need to note these as we
-+ would clobbers. */
-+ for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
-+ {
-+ if (REG_NOTE_KIND (link) == REG_UNUSED)
-+ {
-+ kill_value (XEXP (link, 0), vd);
-+ /* Furthermore, if the insn looked like a single-set,
-+ but the dead store kills the source value of that
-+ set, then we can no-longer use the plain move
-+ special case below. */
-+ if (set
-+ && reg_overlap_mentioned_p (XEXP (link, 0), SET_SRC (set)))
-+ set = NULL;
-+ }
-+ }
-+
- /* Special-case plain move instructions, since we may well
- be able to do the move from a different register class. */
- if (set && REG_P (SET_SRC (set)))
-Index: gcc/tree-ssa-operands.c
-===================================================================
---- a/src/gcc/tree-ssa-operands.c (.../tags/gcc_4_8_2_release)
-+++ b/src/gcc/tree-ssa-operands.c (.../branches/gcc-4_8-branch)
-@@ -626,10 +626,8 @@
- call-clobbered. */
- if (!(call_flags & ECF_NOVOPS))
- {
-- /* A 'pure' or a 'const' function never call-clobbers anything.
-- A 'noreturn' function might, but since we don't return anyway
-- there is no point in recording that. */
-- if (!(call_flags & (ECF_PURE | ECF_CONST | ECF_NORETURN)))
-+ /* A 'pure' or a 'const' function never call-clobbers anything. */
-+ if (!(call_flags & (ECF_PURE | ECF_CONST)))
- add_virtual_operand (stmt, opf_def);
- else if (!(call_flags & ECF_CONST))
- add_virtual_operand (stmt, opf_use);
-Index: libgo/configure
-===================================================================
---- a/src/libgo/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/configure (.../branches/gcc-4_8-branch)
-@@ -6501,7 +6501,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6519,7 +6519,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_i386"
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6538,7 +6541,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -11105,7 +11111,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11108 "configure"
-+#line 11114 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11211,7 +11217,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11214 "configure"
-+#line 11220 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -14700,7 +14706,7 @@
- fi
-
-
--for ac_func in accept4 epoll_create1 faccessat fallocate fchmodat fchownat futimesat inotify_add_watch inotify_init inotify_init1 inotify_rm_watch mkdirat mknodat openat pipe2 renameat sync_file_range splice tee unlinkat unshare utimensat
-+for ac_func in accept4 dup3 epoll_create1 faccessat fallocate fchmodat fchownat futimesat getxattr inotify_add_watch inotify_init inotify_init1 inotify_rm_watch listxattr mkdirat mknodat openat pipe2 removexattr renameat setxattr sync_file_range splice tee unlinkat unshare utimensat
- do :
- as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
- ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"
-Index: libgo/Makefile.in
-===================================================================
---- a/src/libgo/Makefile.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/Makefile.in (.../branches/gcc-4_8-branch)
-@@ -195,7 +195,7 @@
- @LIBGO_IS_LINUX_TRUE@am__objects_5 = getncpu-linux.lo
- am__objects_6 = go-append.lo go-assert.lo go-assert-interface.lo \
- go-byte-array-to-string.lo go-breakpoint.lo go-caller.lo \
-- go-callers.lo go-can-convert-interface.lo go-cgo.lo \
-+ go-callers.lo go-can-convert-interface.lo go-cdiv.lo go-cgo.lo \
- go-check-interface.lo go-construct-map.lo \
- go-convert-interface.lo go-copy.lo go-defer.lo \
- go-deferred-recover.lo go-eface-compare.lo \
-@@ -757,6 +757,7 @@
- runtime/go-caller.c \
- runtime/go-callers.c \
- runtime/go-can-convert-interface.c \
-+ runtime/go-cdiv.c \
- runtime/go-cgo.c \
- runtime/go-check-interface.c \
- runtime/go-construct-map.c \
-@@ -1446,7 +1447,7 @@
- go/go/build/build.go \
- go/go/build/doc.go \
- go/go/build/read.go \
-- syslist.go
-+ go/go/build/syslist.go
-
- go_go_doc_files = \
- go/go/doc/comment.go \
-@@ -2368,6 +2369,7 @@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-caller.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-callers.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-can-convert-interface.Plo@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-cdiv.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-cgo.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-check-interface.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/go-construct-map.Plo@am__quote@
-@@ -2554,6 +2556,13 @@
- @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- @am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o go-can-convert-interface.lo `test -f 'runtime/go-can-convert-interface.c' || echo '$(srcdir)/'`runtime/go-can-convert-interface.c
-
-+go-cdiv.lo: runtime/go-cdiv.c
-+@am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT go-cdiv.lo -MD -MP -MF $(DEPDIR)/go-cdiv.Tpo -c -o go-cdiv.lo `test -f 'runtime/go-cdiv.c' || echo '$(srcdir)/'`runtime/go-cdiv.c
-+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/go-cdiv.Tpo $(DEPDIR)/go-cdiv.Plo
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='runtime/go-cdiv.c' object='go-cdiv.lo' libtool=yes @AMDEPBACKSLASH@
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-+@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o go-cdiv.lo `test -f 'runtime/go-cdiv.c' || echo '$(srcdir)/'`runtime/go-cdiv.c
-+
- go-cgo.lo: runtime/go-cgo.c
- @am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT go-cgo.lo -MD -MP -MF $(DEPDIR)/go-cgo.Tpo -c -o go-cgo.lo `test -f 'runtime/go-cgo.c' || echo '$(srcdir)/'`runtime/go-cgo.c
- @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/go-cgo.Tpo $(DEPDIR)/go-cgo.Plo
-@@ -5062,15 +5071,6 @@
- @$(CHECK)
- .PHONY: go/build/check
-
--syslist.go: s-syslist; @true
--s-syslist: Makefile
-- echo '// Generated automatically by make.' >syslist.go.tmp
-- echo 'package build' >>syslist.go.tmp
-- echo 'const goosList = "$(GOOS)"' >>syslist.go.tmp
-- echo 'const goarchList = "$(GOARCH)"' >>syslist.go.tmp
-- $(SHELL) $(srcdir)/../move-if-change syslist.go.tmp syslist.go
-- $(STAMP) $@
--
- @go_include@ go/doc.lo.dep
- go/doc.lo.dep: $(go_go_doc_files)
- $(BUILDDEPS)
-Index: libgo/runtime/go-defer.c
-===================================================================
---- a/src/libgo/runtime/go-defer.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-defer.c (.../branches/gcc-4_8-branch)
-@@ -27,6 +27,7 @@
- n->__pfn = pfn;
- n->__arg = arg;
- n->__retaddr = NULL;
-+ n->__makefunc_can_recover = 0;
- g->defer = n;
- }
-
-Index: libgo/runtime/go-defer.h
-===================================================================
---- a/src/libgo/runtime/go-defer.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-defer.h (.../branches/gcc-4_8-branch)
-@@ -34,4 +34,10 @@
- set by __go_set_defer_retaddr which is called by the thunks
- created by defer statements. */
- const void *__retaddr;
-+
-+ /* Set to true if a function created by reflect.MakeFunc is
-+ permitted to recover. The return address of such a function
-+ function will be somewhere in libffi, so __retaddr is not
-+ useful. */
-+ _Bool __makefunc_can_recover;
- };
-Index: libgo/runtime/go-int-array-to-string.c
-===================================================================
---- a/src/libgo/runtime/go-int-array-to-string.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-int-array-to-string.c (.../branches/gcc-4_8-branch)
-@@ -30,6 +30,8 @@
-
- if (v < 0 || v > 0x10ffff)
- v = 0xfffd;
-+ else if (0xd800 <= v && v <= 0xdfff)
-+ v = 0xfffd;
-
- if (v <= 0x7f)
- slen += 1;
-@@ -56,6 +58,8 @@
- character. */
- if (v < 0 || v > 0x10ffff)
- v = 0xfffd;
-+ else if (0xd800 <= v && v <= 0xdfff)
-+ v = 0xfffd;
-
- if (v <= 0x7f)
- *s++ = v;
-Index: libgo/runtime/go-nosys.c
-===================================================================
---- a/src/libgo/runtime/go-nosys.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-nosys.c (.../branches/gcc-4_8-branch)
-@@ -43,6 +43,17 @@
- }
- #endif
-
-+#ifndef HAVE_DUP3
-+int
-+dup3 (int oldfd __attribute__ ((unused)),
-+ int newfd __attribute__ ((unused)),
-+ int flags __attribute__ ((unused)))
-+{
-+ errno = ENOSYS;
-+ return -1;
-+}
-+#endif
-+
- #ifndef HAVE_EPOLL_CREATE1
- int
- epoll_create1 (int flags __attribute__ ((unused)))
-@@ -112,6 +123,18 @@
- }
- #endif
-
-+#ifndef HAVE_GETXATTR
-+ssize_t
-+getxattr (const char *path __attribute__ ((unused)),
-+ const char *name __attribute__ ((unused)),
-+ void *value __attribute__ ((unused)),
-+ size_t size __attribute__ ((unused)))
-+{
-+ errno = ENOSYS;
-+ return -1;
-+}
-+#endif
-+
- #ifndef HAVE_INOTIFY_ADD_WATCH
- int
- inotify_add_watch (int fd __attribute__ ((unused)),
-@@ -151,6 +174,17 @@
- }
- #endif
-
-+#ifndef HAVE_LISTXATTR
-+ssize_t
-+listxattr (const char *path __attribute__ ((unused)),
-+ char *list __attribute__ ((unused)),
-+ size_t size __attribute__ ((unused)))
-+{
-+ errno = ENOSYS;
-+ return -1;
-+}
-+#endif
-+
- #ifndef HAVE_MKDIRAT
- int
- mkdirat (int dirfd __attribute__ ((unused)),
-@@ -196,6 +230,16 @@
- }
- #endif
-
-+#ifndef HAVE_REMOVEXATTR
-+int
-+removexattr (const char *path __attribute__ ((unused)),
-+ const char *name __attribute__ ((unused)))
-+{
-+ errno = ENOSYS;
-+ return -1;
-+}
-+#endif
-+
- #ifndef HAVE_RENAMEAT
- int
- renameat (int olddirfd __attribute__ ((unused)),
-@@ -208,6 +252,19 @@
- }
- #endif
-
-+#ifndef HAVE_SETXATTR
-+int
-+setxattr (const char *path __attribute__ ((unused)),
-+ const char *name __attribute__ ((unused)),
-+ const void *value __attribute__ ((unused)),
-+ size_t size __attribute__ ((unused)),
-+ int flags __attribute__ ((unused)))
-+{
-+ errno = ENOSYS;
-+ return -1;
-+}
-+#endif
-+
- #ifndef HAVE_SPLICE
- int
- splice (int fd __attribute__ ((unused)),
-Index: libgo/runtime/runtime.h
-===================================================================
---- a/src/libgo/runtime/runtime.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/runtime.h (.../branches/gcc-4_8-branch)
-@@ -440,7 +440,7 @@
- };
- void runtime_hashinit(void);
-
--void runtime_traceback();
-+void runtime_traceback(void);
- void runtime_tracebackothers(G*);
-
- /*
-@@ -756,6 +756,7 @@
- extern _Bool __go_file_line(uintptr, String*, String*, intgo *);
- extern byte* runtime_progname();
- extern void runtime_main(void*);
-+extern uint32 runtime_in_callers;
-
- int32 getproccount(void);
-
-Index: libgo/runtime/proc.c
-===================================================================
---- a/src/libgo/runtime/proc.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/proc.c (.../branches/gcc-4_8-branch)
-@@ -1716,10 +1716,30 @@
- // entersyscall is going to return immediately after.
-
- void runtime_entersyscall(void) __attribute__ ((no_split_stack));
-+static void doentersyscall(void) __attribute__ ((no_split_stack, noinline));
-
- void
- runtime_entersyscall()
- {
-+ // Save the registers in the g structure so that any pointers
-+ // held in registers will be seen by the garbage collector.
-+ getcontext(&g->gcregs);
-+
-+ // Do the work in a separate function, so that this function
-+ // doesn't save any registers on its own stack. If this
-+ // function does save any registers, we might store the wrong
-+ // value in the call to getcontext.
-+ //
-+ // FIXME: This assumes that we do not need to save any
-+ // callee-saved registers to access the TLS variable g. We
-+ // don't want to put the ucontext_t on the stack because it is
-+ // large and we can not split the stack here.
-+ doentersyscall();
-+}
-+
-+static void
-+doentersyscall()
-+{
- if(m->profilehz > 0)
- runtime_setprof(false);
-
-@@ -1736,10 +1756,6 @@
- }
- #endif
-
-- // Save the registers in the g structure so that any pointers
-- // held in registers will be seen by the garbage collector.
-- getcontext(&g->gcregs);
--
- g->status = Gsyscall;
-
- if(runtime_atomicload(&runtime_sched.sysmonwait)) { // TODO: fast atomic
-@@ -2239,6 +2255,14 @@
- if(prof.fn == nil || prof.hz == 0)
- return;
-
-+ if(runtime_atomicload(&runtime_in_callers) > 0) {
-+ // If SIGPROF arrived while already fetching runtime
-+ // callers we can have trouble on older systems
-+ // because the unwind library calls dl_iterate_phdr
-+ // which was not recursive in the past.
-+ return;
-+ }
-+
- runtime_lock(&prof);
- if(prof.fn == nil) {
- runtime_unlock(&prof);
-Index: libgo/runtime/mgc0.c
-===================================================================
---- a/src/libgo/runtime/mgc0.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/mgc0.c (.../branches/gcc-4_8-branch)
-@@ -174,7 +174,7 @@
- Obj *roots;
- uint32 nroot;
- uint32 rootcap;
--} work;
-+} work __attribute__((aligned(8)));
-
- enum {
- GC_DEFAULT_PTR = GC_NUM_INSTR,
-@@ -239,8 +239,7 @@
- // (Manually inlined copy of MHeap_LookupMaybe.)
- k = (uintptr)obj>>PageShift;
- x = k;
-- if(sizeof(void*) == 8)
-- x -= (uintptr)runtime_mheap->arena_start>>PageShift;
-+ x -= (uintptr)runtime_mheap->arena_start>>PageShift;
- s = runtime_mheap->map[x];
- if(s == nil || k < s->start || k - s->start >= s->npages || s->state != MSpanInUse)
- return false;
-@@ -418,8 +417,7 @@
- // (Manually inlined copy of MHeap_LookupMaybe.)
- k = (uintptr)obj>>PageShift;
- x = k;
-- if(sizeof(void*) == 8)
-- x -= (uintptr)arena_start>>PageShift;
-+ x -= (uintptr)arena_start>>PageShift;
- s = runtime_mheap->map[x];
- if(s == nil || k < s->start || k - s->start >= s->npages || s->state != MSpanInUse)
- continue;
-@@ -466,8 +464,7 @@
- // Ask span about size class.
- // (Manually inlined copy of MHeap_Lookup.)
- x = (uintptr)obj >> PageShift;
-- if(sizeof(void*) == 8)
-- x -= (uintptr)arena_start>>PageShift;
-+ x -= (uintptr)arena_start>>PageShift;
- s = runtime_mheap->map[x];
-
- PREFETCH(obj);
-@@ -585,8 +582,7 @@
- if(t == nil)
- return;
- x = (uintptr)obj >> PageShift;
-- if(sizeof(void*) == 8)
-- x -= (uintptr)(runtime_mheap->arena_start)>>PageShift;
-+ x -= (uintptr)(runtime_mheap->arena_start)>>PageShift;
- s = runtime_mheap->map[x];
- objstart = (byte*)((uintptr)s->start<<PageShift);
- if(s->sizeclass != 0) {
-Index: libgo/runtime/go-signal.c
-===================================================================
---- a/src/libgo/runtime/go-signal.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-signal.c (.../branches/gcc-4_8-branch)
-@@ -234,7 +234,7 @@
- G *g;
-
- g = runtime_g ();
-- runtime_traceback (g);
-+ runtime_traceback ();
- runtime_tracebackothers (g);
-
- /* The gc library calls runtime_dumpregs here, and provides
-@@ -399,6 +399,9 @@
- {
- G *gp;
- M *mp;
-+#ifdef USING_SPLIT_STACK
-+ void *stack_context[10];
-+#endif
-
- /* We are now running on the stack registered via sigaltstack.
- (Actually there is a small span of time between runtime_siginit
-@@ -409,7 +412,7 @@
- if (gp != NULL)
- {
- #ifdef USING_SPLIT_STACK
-- __splitstack_getcontext (&gp->stack_context[0]);
-+ __splitstack_getcontext (&stack_context[0]);
- #endif
- }
-
-@@ -432,7 +435,7 @@
- if (gp != NULL)
- {
- #ifdef USING_SPLIT_STACK
-- __splitstack_setcontext (&gp->stack_context[0]);
-+ __splitstack_setcontext (&stack_context[0]);
- #endif
- }
- }
-Index: libgo/runtime/go-callers.c
-===================================================================
---- a/src/libgo/runtime/go-callers.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-callers.c (.../branches/gcc-4_8-branch)
-@@ -11,6 +11,13 @@
- #include "runtime.h"
- #include "array.h"
-
-+/* This is set to non-zero when calling backtrace_full. This is used
-+ to avoid getting hanging on a recursive lock in dl_iterate_phdr on
-+ older versions of glibc when a SIGPROF signal arrives while
-+ collecting a backtrace. */
-+
-+uint32 runtime_in_callers;
-+
- /* Argument passed to callback function. */
-
- struct callers_data
-@@ -111,8 +118,10 @@
- data.skip = skip + 1;
- data.index = 0;
- data.max = m;
-+ runtime_xadd (&runtime_in_callers, 1);
- backtrace_full (__go_get_backtrace_state (), 0, callback, error_callback,
- &data);
-+ runtime_xadd (&runtime_in_callers, -1);
- return data.index;
- }
-
-Index: libgo/runtime/go-cdiv.c
-===================================================================
---- a/src/libgo/runtime/go-cdiv.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-cdiv.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,46 @@
-+/* go-cdiv.c -- complex division routines
-+
-+ Copyright 2013 The Go Authors. All rights reserved.
-+ Use of this source code is governed by a BSD-style
-+ license that can be found in the LICENSE file. */
-+
-+/* Calls to these functions are generated by the Go frontend for
-+ division of complex64 or complex128. We use these because Go's
-+ complex division expects slightly different results from the GCC
-+ default. When dividing NaN+1.0i / 0+0i, Go expects NaN+NaNi but
-+ GCC generates NaN+Infi. NaN+Infi seems wrong seems the rules of
-+ C99 Annex G specify that if either side of a complex number is Inf,
-+ the the whole number is Inf, but an operation involving NaN ought
-+ to result in NaN, not Inf. */
-+
-+__complex float
-+__go_complex64_div (__complex float a, __complex float b)
-+{
-+ if (__builtin_expect (b == 0+0i, 0))
-+ {
-+ if (!__builtin_isinff (__real__ a)
-+ && !__builtin_isinff (__imag__ a)
-+ && (__builtin_isnanf (__real__ a) || __builtin_isnanf (__imag__ a)))
-+ {
-+ /* Pass "1" to nanf to match math/bits.go. */
-+ return __builtin_nanf("1") + __builtin_nanf("1")*1i;
-+ }
-+ }
-+ return a / b;
-+}
-+
-+__complex double
-+__go_complex128_div (__complex double a, __complex double b)
-+{
-+ if (__builtin_expect (b == 0+0i, 0))
-+ {
-+ if (!__builtin_isinf (__real__ a)
-+ && !__builtin_isinf (__imag__ a)
-+ && (__builtin_isnan (__real__ a) || __builtin_isnan (__imag__ a)))
-+ {
-+ /* Pass "1" to nan to match math/bits.go. */
-+ return __builtin_nan("1") + __builtin_nan("1")*1i;
-+ }
-+ }
-+ return a / b;
-+}
-Index: libgo/runtime/go-reflect-call.c
-===================================================================
---- a/src/libgo/runtime/go-reflect-call.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-reflect-call.c (.../branches/gcc-4_8-branch)
-@@ -98,9 +98,12 @@
- const struct __go_struct_field *fields;
- int i;
-
-+ field_count = descriptor->__fields.__count;
-+ if (field_count == 0) {
-+ return &ffi_type_void;
-+ }
- ret = (ffi_type *) __go_alloc (sizeof (ffi_type));
- ret->type = FFI_TYPE_STRUCT;
-- field_count = descriptor->__fields.__count;
- fields = (const struct __go_struct_field *) descriptor->__fields.__values;
- ret->elements = (ffi_type **) __go_alloc ((field_count + 1)
- * sizeof (ffi_type *));
-Index: libgo/runtime/go-recover.c
-===================================================================
---- a/src/libgo/runtime/go-recover.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-recover.c (.../branches/gcc-4_8-branch)
-@@ -16,12 +16,14 @@
- __go_can_recover--this is, the thunk. */
-
- _Bool
--__go_can_recover (const void* retaddr)
-+__go_can_recover (const void *retaddr)
- {
- G *g;
- struct __go_defer_stack *d;
- const char* ret;
- const char* dret;
-+ Location loc;
-+ const byte *name;
-
- g = runtime_g ();
-
-@@ -52,9 +54,80 @@
- #endif
-
- dret = (const char *) d->__retaddr;
-- return ret <= dret && ret + 16 >= dret;
-+ if (ret <= dret && ret + 16 >= dret)
-+ return 1;
-+
-+ /* If the function calling recover was created by reflect.MakeFunc,
-+ then RETADDR will be somewhere in libffi. Our caller is
-+ permitted to recover if it was called from libffi. */
-+ if (!d->__makefunc_can_recover)
-+ return 0;
-+
-+ if (runtime_callers (2, &loc, 1) < 1)
-+ return 0;
-+
-+ /* If we have no function name, then we weren't called by Go code.
-+ Guess that we were called by libffi. */
-+ if (loc.function.len == 0)
-+ return 1;
-+
-+ if (loc.function.len < 4)
-+ return 0;
-+ name = loc.function.str;
-+ if (*name == '_')
-+ {
-+ if (loc.function.len < 5)
-+ return 0;
-+ ++name;
-+ }
-+
-+ if (name[0] == 'f' && name[1] == 'f' && name[2] == 'i' && name[3] == '_')
-+ return 1;
-+
-+ /* We may also be called by reflect.makeFuncImpl.call, for a
-+ function created by reflect.MakeFunc. */
-+ if (__builtin_strstr ((const char *) name, "makeFuncImpl") != NULL)
-+ return 1;
-+
-+ return 0;
- }
-
-+/* This function is called when code is about to enter a function
-+ created by reflect.MakeFunc. It is called by the function stub
-+ used by MakeFunc. If the stub is permitted to call recover, then a
-+ real MakeFunc function is permitted to call recover. */
-+
-+void
-+__go_makefunc_can_recover (const void *retaddr)
-+{
-+ struct __go_defer_stack *d;
-+
-+ d = runtime_g ()->defer;
-+ if (d != NULL
-+ && !d->__makefunc_can_recover
-+ && __go_can_recover (retaddr))
-+ d->__makefunc_can_recover = 1;
-+}
-+
-+/* This function is called when code is about to exit a function
-+ created by reflect.MakeFunc. It is called by the function stub
-+ used by MakeFunc. It clears the __makefunc_can_recover field.
-+ It's OK to always clear this field, because __go_can_recover will
-+ only be called by a stub created for a function that calls recover.
-+ That stub will not call a function created by reflect.MakeFunc, so
-+ by the time we get here any caller higher up on the call stack no
-+ longer needs the information. */
-+
-+void
-+__go_makefunc_returning (void)
-+{
-+ struct __go_defer_stack *d;
-+
-+ d = runtime_g ()->defer;
-+ if (d != NULL)
-+ d->__makefunc_can_recover = 0;
-+}
-+
- /* This is only called when it is valid for the caller to recover the
- value on top of the panic stack, if there is one. */
-
-Index: libgo/runtime/malloc.goc
-===================================================================
---- a/src/libgo/runtime/malloc.goc (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/malloc.goc (.../branches/gcc-4_8-branch)
-@@ -541,8 +541,7 @@
-
- // (Manually inlined copy of runtime_MHeap_Lookup)
- p = (uintptr)v>>PageShift;
-- if(sizeof(void*) == 8)
-- p -= (uintptr)runtime_mheap->arena_start >> PageShift;
-+ p -= (uintptr)runtime_mheap->arena_start >> PageShift;
- s = runtime_mheap->map[p];
-
- if(s->sizeclass == 0) {
-Index: libgo/runtime/go-make-slice.c
-===================================================================
---- a/src/libgo/runtime/go-make-slice.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/go-make-slice.c (.../branches/gcc-4_8-branch)
-@@ -34,7 +34,10 @@
- std = (const struct __go_slice_type *) td;
-
- ilen = (intgo) len;
-- if (ilen < 0 || (uintptr_t) ilen != len)
-+ if (ilen < 0
-+ || (uintptr_t) ilen != len
-+ || (std->__element_type->__size > 0
-+ && len > MaxMem / std->__element_type->__size))
- runtime_panicstring ("makeslice: len out of range");
-
- icap = (intgo) cap;
-Index: libgo/runtime/mheap.c
-===================================================================
---- a/src/libgo/runtime/mheap.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/runtime/mheap.c (.../branches/gcc-4_8-branch)
-@@ -150,8 +150,7 @@
- runtime_MSpan_Init(t, s->start + npage, s->npages - npage);
- s->npages = npage;
- p = t->start;
-- if(sizeof(void*) == 8)
-- p -= ((uintptr)h->arena_start>>PageShift);
-+ p -= ((uintptr)h->arena_start>>PageShift);
- if(p > 0)
- h->map[p-1] = s;
- h->map[p] = t;
-@@ -169,8 +168,7 @@
- s->elemsize = (sizeclass==0 ? s->npages<<PageShift : (uintptr)runtime_class_to_size[sizeclass]);
- s->types.compression = MTypes_Empty;
- p = s->start;
-- if(sizeof(void*) == 8)
-- p -= ((uintptr)h->arena_start>>PageShift);
-+ p -= ((uintptr)h->arena_start>>PageShift);
- for(n=0; n<npage; n++)
- h->map[p+n] = s;
- return s;
-@@ -241,8 +239,7 @@
- mstats.mspan_sys = h->spanalloc.sys;
- runtime_MSpan_Init(s, (uintptr)v>>PageShift, ask>>PageShift);
- p = s->start;
-- if(sizeof(void*) == 8)
-- p -= ((uintptr)h->arena_start>>PageShift);
-+ p -= ((uintptr)h->arena_start>>PageShift);
- h->map[p] = s;
- h->map[p + s->npages - 1] = s;
- s->state = MSpanInUse;
-@@ -259,8 +256,7 @@
- uintptr p;
-
- p = (uintptr)v;
-- if(sizeof(void*) == 8)
-- p -= (uintptr)h->arena_start;
-+ p -= (uintptr)h->arena_start;
- return h->map[p >> PageShift];
- }
-
-@@ -281,8 +277,7 @@
- return nil;
- p = (uintptr)v>>PageShift;
- q = p;
-- if(sizeof(void*) == 8)
-- q -= (uintptr)h->arena_start >> PageShift;
-+ q -= (uintptr)h->arena_start >> PageShift;
- s = h->map[q];
- if(s == nil || p < s->start || p - s->start >= s->npages)
- return nil;
-@@ -332,8 +327,7 @@
-
- // Coalesce with earlier, later spans.
- p = s->start;
-- if(sizeof(void*) == 8)
-- p -= (uintptr)h->arena_start >> PageShift;
-+ p -= (uintptr)h->arena_start >> PageShift;
- if(p > 0 && (t = h->map[p-1]) != nil && t->state != MSpanInUse) {
- tp = (uintptr*)(t->start<<PageShift);
- *tp |= *sp; // propagate "needs zeroing" mark
-Index: libgo/testsuite/gotest
-===================================================================
---- a/src/libgo/testsuite/gotest (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/testsuite/gotest (.../branches/gcc-4_8-branch)
-@@ -369,7 +369,7 @@
- {
- text="T"
- case "$GOARCH" in
-- ppc64) text="D" ;;
-+ ppc64) text="[TD]" ;;
- esac
-
- symtogo='sed -e s/_test/XXXtest/ -e s/.*_\([^_]*\.\)/\1/ -e s/XXXtest/_test/'
-Index: libgo/mksysinfo.sh
-===================================================================
---- a/src/libgo/mksysinfo.sh (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/mksysinfo.sh (.../branches/gcc-4_8-branch)
-@@ -1035,6 +1035,10 @@
- grep '^const _LOCK_' gen-sysinfo.go |
- sed -e 's/^\(const \)_\(LOCK_[^= ]*\)\(.*\)$/\1\2 = _\2/' >> ${OUT}
-
-+# The PRIO constants.
-+grep '^const _PRIO_' gen-sysinfo.go | \
-+ sed -e 's/^\(const \)_\(PRIO_[^= ]*\)\(.*\)$/\1\2 = _\2/' >> ${OUT}
-+
- # The GNU/Linux LINUX_REBOOT flags.
- grep '^const _LINUX_REBOOT_' gen-sysinfo.go |
- sed -e 's/^\(const \)_\(LINUX_REBOOT_[^= ]*\)\(.*\)$/\1\2 = _\2/' >> ${OUT}
-Index: libgo/config.h.in
-===================================================================
---- a/src/libgo/config.h.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/config.h.in (.../branches/gcc-4_8-branch)
-@@ -39,6 +39,9 @@
- /* Define to 1 if you have the `dl_iterate_phdr' function. */
- #undef HAVE_DL_ITERATE_PHDR
-
-+/* Define to 1 if you have the `dup3' function. */
-+#undef HAVE_DUP3
-+
- /* Define to 1 if you have the `epoll_create1' function. */
- #undef HAVE_EPOLL_CREATE1
-
-@@ -66,6 +69,9 @@
- /* Define if _Unwind_GetIPInfo is available. */
- #undef HAVE_GETIPINFO
-
-+/* Define to 1 if you have the `getxattr' function. */
-+#undef HAVE_GETXATTR
-+
- /* Define to 1 if you have the `inotify_add_watch' function. */
- #undef HAVE_INOTIFY_ADD_WATCH
-
-@@ -111,6 +117,9 @@
- /* Define to 1 if you have the <linux/rtnetlink.h> header file. */
- #undef HAVE_LINUX_RTNETLINK_H
-
-+/* Define to 1 if you have the `listxattr' function. */
-+#undef HAVE_LISTXATTR
-+
- /* Define to 1 if the system has the type `loff_t'. */
- #undef HAVE_LOFF_T
-
-@@ -171,6 +180,9 @@
- /* Define to 1 if you have the `pipe2' function. */
- #undef HAVE_PIPE2
-
-+/* Define to 1 if you have the `removexattr' function. */
-+#undef HAVE_REMOVEXATTR
-+
- /* Define to 1 if you have the `renameat' function. */
- #undef HAVE_RENAMEAT
-
-@@ -180,6 +192,9 @@
- /* Define to 1 if you have the `setenv' function. */
- #undef HAVE_SETENV
-
-+/* Define to 1 if you have the `setxattr' function. */
-+#undef HAVE_SETXATTR
-+
- /* Define to 1 if you have the `sinl' function. */
- #undef HAVE_SINL
-
-Index: libgo/configure.ac
-===================================================================
---- a/src/libgo/configure.ac (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/configure.ac (.../branches/gcc-4_8-branch)
-@@ -503,7 +503,7 @@
- AM_CONDITIONAL(HAVE_STRERROR_R, test "$ac_cv_func_strerror_r" = yes)
- AM_CONDITIONAL(HAVE_WAIT4, test "$ac_cv_func_wait4" = yes)
-
--AC_CHECK_FUNCS(accept4 epoll_create1 faccessat fallocate fchmodat fchownat futimesat inotify_add_watch inotify_init inotify_init1 inotify_rm_watch mkdirat mknodat openat pipe2 renameat sync_file_range splice tee unlinkat unshare utimensat)
-+AC_CHECK_FUNCS(accept4 dup3 epoll_create1 faccessat fallocate fchmodat fchownat futimesat getxattr inotify_add_watch inotify_init inotify_init1 inotify_rm_watch listxattr mkdirat mknodat openat pipe2 removexattr renameat setxattr sync_file_range splice tee unlinkat unshare utimensat)
- AC_TYPE_OFF_T
- AC_CHECK_TYPES([loff_t])
-
-Index: libgo/config/libtool.m4
-===================================================================
---- a/src/libgo/config/libtool.m4 (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/config/libtool.m4 (.../branches/gcc-4_8-branch)
-@@ -1225,7 +1225,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -1239,7 +1239,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_i386"
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -1258,7 +1261,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-Index: libgo/go/reflect/value.go
-===================================================================
---- a/src/libgo/go/reflect/value.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/reflect/value.go (.../branches/gcc-4_8-branch)
-@@ -98,6 +98,7 @@
- flagIndir
- flagAddr
- flagMethod
-+ flagMethodFn // gccgo: first fn parameter is always pointer
- flagKindShift = iota
- flagKindWidth = 5 // there are 27 kinds
- flagKindMask flag = 1<<flagKindWidth - 1
-@@ -433,7 +434,7 @@
- if v.flag&flagMethod != 0 {
- nin++
- }
-- firstPointer := len(in) > 0 && t.In(0).Kind() != Ptr && v.flag&flagMethod == 0 && isMethod(v.typ)
-+ firstPointer := len(in) > 0 && t.In(0).Kind() != Ptr && v.flag&flagMethodFn != 0
- params := make([]unsafe.Pointer, nin)
- off := 0
- if v.flag&flagMethod != 0 {
-@@ -484,33 +485,6 @@
- return ret
- }
-
--// gccgo specific test to see if typ is a method. We can tell by
--// looking at the string to see if there is a receiver. We need this
--// because for gccgo all methods take pointer receivers.
--func isMethod(t *rtype) bool {
-- if Kind(t.kind) != Func {
-- return false
-- }
-- s := *t.string
-- parens := 0
-- params := 0
-- sawRet := false
-- for i, c := range s {
-- if c == '(' {
-- if parens == 0 {
-- params++
-- }
-- parens++
-- } else if c == ')' {
-- parens--
-- } else if parens == 0 && c == ' ' && s[i+1] != '(' && !sawRet {
-- params++
-- sawRet = true
-- }
-- }
-- return params > 2
--}
--
- // methodReceiver returns information about the receiver
- // described by v. The Value v may or may not have the
- // flagMethod bit set, so the kind cached in v.flag should
-@@ -917,6 +891,16 @@
- v = makeMethodValue("Interface", v)
- }
-
-+ if v.flag&flagMethodFn != 0 {
-+ if v.typ.Kind() != Func {
-+ panic("reflect: MethodFn of non-Func")
-+ }
-+ ft := (*funcType)(unsafe.Pointer(v.typ))
-+ if ft.in[0].Kind() != Ptr {
-+ v = makeValueMethod(v)
-+ }
-+ }
-+
- k := v.kind()
- if k == Interface {
- // Special case: return the element inside the interface.
-@@ -1230,8 +1214,7 @@
- // created via reflect have the same underlying code pointer,
- // so their Pointers are equal. The function used here must
- // match the one used in makeMethodValue.
-- // This is not properly implemented for gccgo.
-- f := Zero
-+ f := makeFuncStub
- return **(**uintptr)(unsafe.Pointer(&f))
- }
- p := v.val
-Index: libgo/go/reflect/makefuncgo_386.go
-===================================================================
---- a/src/libgo/go/reflect/makefuncgo_386.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/reflect/makefuncgo_386.go (.../branches/gcc-4_8-branch)
-@@ -14,8 +14,10 @@
- // registers that might hold result values.
- type i386Regs struct {
- esp uint32
-- eax uint32 // Value to return in %eax.
-- st0 uint64 // Value to return in %st(0).
-+ eax uint32 // Value to return in %eax.
-+ st0 float64 // Value to return in %st(0).
-+ sr bool // Set to true if hidden struct pointer.
-+ sf bool // Set to true if returning float
- }
-
- // MakeFuncStubGo implements the 386 calling convention for MakeFunc.
-@@ -56,10 +58,13 @@
- in := make([]Value, 0, len(ftyp.in))
- ap := uintptr(regs.esp)
-
-+ regs.sr = false
-+ regs.sf = false
- var retPtr unsafe.Pointer
- if retStruct {
- retPtr = *(*unsafe.Pointer)(unsafe.Pointer(ap))
- ap += ptrSize
-+ regs.sr = true
- }
-
- for _, rt := range ftyp.in {
-@@ -77,7 +82,7 @@
-
- // Call the real function.
-
-- out := c.fn(in)
-+ out := c.call(in)
-
- if len(out) != len(ftyp.out) {
- panic("reflect: wrong return count from function created by MakeFunc")
-@@ -123,13 +128,16 @@
-
- v := out[0]
- w := v.iword()
-- if v.Kind() != Ptr && v.Kind() != UnsafePointer {
-- w = loadIword(unsafe.Pointer(w), v.typ.size)
-- }
- switch v.Kind() {
-- case Float32, Float64:
-- regs.st0 = uint64(uintptr(w))
-+ case Ptr, UnsafePointer:
-+ regs.eax = uint32(uintptr(w))
-+ case Float32:
-+ regs.st0 = float64(*(*float32)(unsafe.Pointer(w)))
-+ regs.sf = true
-+ case Float64:
-+ regs.st0 = *(*float64)(unsafe.Pointer(w))
-+ regs.sf = true
- default:
-- regs.eax = uint32(uintptr(w))
-+ regs.eax = uint32(uintptr(loadIword(unsafe.Pointer(w), v.typ.size)))
- }
- }
-Index: libgo/go/reflect/makefunc_amd64.S
-===================================================================
---- a/src/libgo/go/reflect/makefunc_amd64.S (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/reflect/makefunc_amd64.S (.../branches/gcc-4_8-branch)
-@@ -61,6 +61,14 @@
- movdqa %xmm6, 0xa0(%rsp)
- movdqa %xmm7, 0xb0(%rsp)
-
-+ /* For MakeFunc functions that call recover. */
-+ movq 8(%rbp), %rdi
-+#ifdef __PIC__
-+ call __go_makefunc_can_recover@PLT
-+#else
-+ call __go_makefunc_can_recover
-+#endif
-+
- # Get function type.
- #ifdef __PIC__
- call __go_get_closure@PLT
-@@ -77,6 +85,13 @@
- call reflect.MakeFuncStubGo
- #endif
-
-+ /* MakeFunc functions can no longer call recover. */
-+#ifdef __PIC__
-+ call __go_makefunc_returning@PLT
-+#else
-+ call __go_makefunc_returning
-+#endif
-+
- # The structure will be updated with any return values. Load
- # all possible return registers before returning to the caller.
-
-Index: libgo/go/reflect/type.go
-===================================================================
---- a/src/libgo/go/reflect/type.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/reflect/type.go (.../branches/gcc-4_8-branch)
-@@ -508,7 +508,7 @@
- m.Type = toType(mt)
- x := new(unsafe.Pointer)
- *x = unsafe.Pointer(&p.tfn)
-- m.Func = Value{mt, unsafe.Pointer(x), fl | flagIndir}
-+ m.Func = Value{mt, unsafe.Pointer(x), fl | flagIndir | flagMethodFn}
- m.Index = i
- return
- }
-Index: libgo/go/reflect/makefunc_386.S
-===================================================================
---- a/src/libgo/go/reflect/makefunc_386.S (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/reflect/makefunc_386.S (.../branches/gcc-4_8-branch)
-@@ -25,9 +25,13 @@
- struct {
- esp uint32 // 0x0
- eax uint32 // 0x4
-- st0 uint64 // 0x8
-+ st0 float64 // 0x8
-+ sr bool // 0x10
-+ sf bool // 0x11
- }
-- */
-+ The sr field is set by the function to a non-zero value if
-+ the function takes a struct hidden pointer that must be
-+ popped off the stack. */
-
- pushl %ebp
- .LCFI0:
-@@ -45,7 +49,16 @@
- leal 8(%ebp), %eax /* Set esp field in struct. */
- movl %eax, -24(%ebp)
-
-+ /* For MakeFunc functions that call recover. */
-+ movl 4(%ebp), %eax
-+ movl %eax, (%esp)
- #ifdef __PIC__
-+ call __go_makefunc_can_recover@PLT
-+#else
-+ call __go_makefunc_can_recover
-+#endif
-+
-+#ifdef __PIC__
- call __go_get_closure@PLT
- #else
- call __go_get_closure
-@@ -62,9 +75,20 @@
- call reflect.MakeFuncStubGo
- #endif
-
-+ /* MakeFunc functions can no longer call recover. */
-+#ifdef __PIC__
-+ call __go_makefunc_returning@PLT
-+#else
-+ call __go_makefunc_returning
-+#endif
-+
- /* Set return registers. */
-
- movl -20(%ebp), %eax
-+
-+ cmpb $0, -7(%ebp)
-+ je 2f
-+
- fldl -16(%ebp)
-
- #ifdef __SSE2__
-@@ -73,12 +97,20 @@
- movsd -16(%ebp), %xmm0
- #endif
-
-+2:
-+ movb -8(%ebp), %dl
-+
- addl $36, %esp
- popl %ebx
- .LCFI3:
- popl %ebp
- .LCFI4:
-+
-+ testb %dl,%dl
-+ jne 1f
- ret
-+1:
-+ ret $4
- .LFE1:
- #ifdef __ELF__
- .size reflect.makeFuncStub, . - reflect.makeFuncStub
-Index: libgo/go/reflect/all_test.go
-===================================================================
---- a/src/libgo/go/reflect/all_test.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/reflect/all_test.go (.../branches/gcc-4_8-branch)
-@@ -1430,6 +1430,46 @@
- }
- }
-
-+type emptyStruct struct{}
-+
-+type nonEmptyStruct struct {
-+ member int
-+}
-+
-+func returnEmpty() emptyStruct {
-+ return emptyStruct{}
-+}
-+
-+func takesEmpty(e emptyStruct) {
-+}
-+
-+func returnNonEmpty(i int) nonEmptyStruct {
-+ return nonEmptyStruct{member: i}
-+}
-+
-+func takesNonEmpty(n nonEmptyStruct) int {
-+ return n.member
-+}
-+
-+func TestCallWithStruct(t *testing.T) {
-+ r := ValueOf(returnEmpty).Call([]Value{})
-+ if len(r) != 1 || r[0].Type() != TypeOf(emptyStruct{}) {
-+ t.Errorf("returning empty struct returned %s instead", r)
-+ }
-+ r = ValueOf(takesEmpty).Call([]Value{ValueOf(emptyStruct{})})
-+ if len(r) != 0 {
-+ t.Errorf("takesEmpty returned values: %s", r)
-+ }
-+ r = ValueOf(returnNonEmpty).Call([]Value{ValueOf(42)})
-+ if len(r) != 1 || r[0].Type() != TypeOf(nonEmptyStruct{}) || r[0].Field(0).Int() != 42 {
-+ t.Errorf("returnNonEmpty returned %s", r)
-+ }
-+ r = ValueOf(takesNonEmpty).Call([]Value{ValueOf(nonEmptyStruct{member: 42})})
-+ if len(r) != 1 || r[0].Type() != TypeOf(1) || r[0].Int() != 42 {
-+ t.Errorf("takesNonEmpty returned %s", r)
-+ }
-+}
-+
- func TestMakeFunc(t *testing.T) {
- switch runtime.GOARCH {
- case "amd64", "386":
-@@ -1587,9 +1627,13 @@
- }
- }
-
--/* Not yet implemented for gccgo
-+func TestMethodValue(t *testing.T) {
-+ switch runtime.GOARCH {
-+ case "amd64", "386":
-+ default:
-+ t.Skip("reflect method values not implemented for " + runtime.GOARCH)
-+ }
-
--func TestMethodValue(t *testing.T) {
- p := Point{3, 4}
- var i int64
-
-@@ -1658,8 +1702,6 @@
- }
- }
-
--*/
--
- // Reflect version of $GOROOT/test/method5.go
-
- // Concrete types implementing M method.
-@@ -1744,7 +1786,12 @@
- func (t4 Tm4) M(x int, b byte) (byte, int) { return b, x + 40 }
-
- func TestMethod5(t *testing.T) {
-- /* Not yet used for gccgo
-+ switch runtime.GOARCH {
-+ case "amd64", "386":
-+ default:
-+ t.Skip("reflect method values not implemented for " + runtime.GOARCH)
-+ }
-+
- CheckF := func(name string, f func(int, byte) (byte, int), inc int) {
- b, x := f(1000, 99)
- if b != 99 || x != 1000+inc {
-@@ -1751,7 +1798,6 @@
- t.Errorf("%s(1000, 99) = %v, %v, want 99, %v", name, b, x, 1000+inc)
- }
- }
-- */
-
- CheckV := func(name string, i Value, inc int) {
- bx := i.Method(0).Call([]Value{ValueOf(1000), ValueOf(byte(99))})
-@@ -1761,9 +1807,7 @@
- t.Errorf("direct %s.M(1000, 99) = %v, %v, want 99, %v", name, b, x, 1000+inc)
- }
-
-- /* Not yet implemented for gccgo
- CheckF(name+".M", i.Method(0).Interface().(func(int, byte) (byte, int)), inc)
-- */
- }
-
- var TinterType = TypeOf(new(Tinter)).Elem()
-Index: libgo/go/reflect/makefunc.go
-===================================================================
---- a/src/libgo/go/reflect/makefunc.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/reflect/makefunc.go (.../branches/gcc-4_8-branch)
-@@ -17,6 +17,11 @@
- code uintptr
- typ *funcType
- fn func([]Value) []Value
-+
-+ // For gccgo we use the same entry point for functions and for
-+ // method values.
-+ method int
-+ rcvr Value
- }
-
- // MakeFunc returns a new function of the given Type
-@@ -61,7 +66,7 @@
- dummy := makeFuncStub
- code := **(**uintptr)(unsafe.Pointer(&dummy))
-
-- impl := &makeFuncImpl{code: code, typ: ftyp, fn: fn}
-+ impl := &makeFuncImpl{code: code, typ: ftyp, fn: fn, method: -1}
-
- return Value{t, unsafe.Pointer(&impl), flag(Func<<flagKindShift) | flagIndir}
- }
-@@ -85,15 +90,94 @@
- panic("reflect: internal error: invalid use of makePartialFunc")
- }
-
-+ switch runtime.GOARCH {
-+ case "amd64", "386":
-+ default:
-+ panic("reflect.makeMethodValue not implemented for " + runtime.GOARCH)
-+ }
-+
- // Ignoring the flagMethod bit, v describes the receiver, not the method type.
- fl := v.flag & (flagRO | flagAddr | flagIndir)
- fl |= flag(v.typ.Kind()) << flagKindShift
- rcvr := Value{v.typ, v.val, fl}
-
-+ // v.Type returns the actual type of the method value.
-+ ft := v.Type().(*rtype)
-+
-+ // Indirect Go func value (dummy) to obtain
-+ // actual code address. (A Go func value is a pointer
-+ // to a C function pointer. http://golang.org/s/go11func.)
-+ dummy := makeFuncStub
-+ code := **(**uintptr)(unsafe.Pointer(&dummy))
-+
- // Cause panic if method is not appropriate.
- // The panic would still happen during the call if we omit this,
- // but we want Interface() and other operations to fail early.
-- methodReceiver(op, rcvr, int(v.flag)>>flagMethodShift)
-+ t, _, _ := methodReceiver(op, rcvr, int(v.flag)>>flagMethodShift)
-
-- panic("reflect makeMethodValue not implemented")
-+ fv := &makeFuncImpl{
-+ code: code,
-+ typ: (*funcType)(unsafe.Pointer(t)),
-+ method: int(v.flag) >> flagMethodShift,
-+ rcvr: rcvr,
-+ }
-+
-+ return Value{ft, unsafe.Pointer(&fv), v.flag&flagRO | flag(Func)<<flagKindShift | flagIndir}
- }
-+
-+// makeValueMethod takes a method function and returns a function that
-+// takes a value receiver and calls the real method with a pointer to
-+// it.
-+func makeValueMethod(v Value) Value {
-+ typ := v.typ
-+ if typ.Kind() != Func {
-+ panic("reflect: call of makeValueMethod with non-Func type")
-+ }
-+ if v.flag&flagMethodFn == 0 {
-+ panic("reflect: call of makeValueMethod with non-MethodFn")
-+ }
-+
-+ switch runtime.GOARCH {
-+ case "amd64", "386":
-+ default:
-+ panic("reflect.makeValueMethod not implemented for " + runtime.GOARCH)
-+ }
-+
-+ t := typ.common()
-+ ftyp := (*funcType)(unsafe.Pointer(t))
-+
-+ // Indirect Go func value (dummy) to obtain
-+ // actual code address. (A Go func value is a pointer
-+ // to a C function pointer. http://golang.org/s/go11func.)
-+ dummy := makeFuncStub
-+ code := **(**uintptr)(unsafe.Pointer(&dummy))
-+
-+ impl := &makeFuncImpl{
-+ code: code,
-+ typ: ftyp,
-+ method: -2,
-+ rcvr: v,
-+ }
-+
-+ return Value{t, unsafe.Pointer(&impl), flag(Func<<flagKindShift) | flagIndir}
-+}
-+
-+// Call the function represented by a makeFuncImpl.
-+func (c *makeFuncImpl) call(in []Value) []Value {
-+ if c.method == -1 {
-+ return c.fn(in)
-+ } else if c.method == -2 {
-+ if c.typ.IsVariadic() {
-+ return c.rcvr.CallSlice(in)
-+ } else {
-+ return c.rcvr.Call(in)
-+ }
-+ } else {
-+ m := c.rcvr.Method(c.method)
-+ if c.typ.IsVariadic() {
-+ return m.CallSlice(in)
-+ } else {
-+ return m.Call(in)
-+ }
-+ }
-+}
-Index: libgo/go/reflect/makefuncgo_amd64.go
-===================================================================
---- a/src/libgo/go/reflect/makefuncgo_amd64.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/reflect/makefuncgo_amd64.go (.../branches/gcc-4_8-branch)
-@@ -319,7 +319,7 @@
- // All the real arguments have been found and turned into
- // Value's. Call the real function.
-
-- out := c.fn(in)
-+ out := c.call(in)
-
- if len(out) != len(ftyp.out) {
- panic("reflect: wrong return count from function created by MakeFunc")
-Index: libgo/go/net/fd_unix.go
-===================================================================
---- a/src/libgo/go/net/fd_unix.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/net/fd_unix.go (.../branches/gcc-4_8-branch)
-@@ -9,6 +9,7 @@
- import (
- "io"
- "os"
-+ "runtime"
- "sync"
- "syscall"
- "time"
-@@ -90,6 +91,16 @@
- if err == nil || err == syscall.EISCONN {
- break
- }
-+
-+ // On Solaris we can see EINVAL if the socket has
-+ // already been accepted and closed by the server.
-+ // Treat this as a successful connection--writes to
-+ // the socket will see EOF. For details and a test
-+ // case in C see http://golang.org/issue/6828.
-+ if runtime.GOOS == "solaris" && err == syscall.EINVAL {
-+ break
-+ }
-+
- if err != syscall.EINPROGRESS && err != syscall.EALREADY && err != syscall.EINTR {
- return err
- }
-Index: libgo/go/go/build/build.go
-===================================================================
---- a/src/libgo/go/go/build/build.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/go/build/build.go (.../branches/gcc-4_8-branch)
-@@ -429,7 +429,7 @@
- switch ctxt.Compiler {
- case "gccgo":
- dir, elem := pathpkg.Split(p.ImportPath)
-- pkga = "pkg/gccgo/" + dir + "lib" + elem + ".a"
-+ pkga = "pkg/gccgo_" + ctxt.GOOS + "_" + ctxt.GOARCH + "/" + dir + "lib" + elem + ".a"
- case "gc":
- suffix := ""
- if ctxt.InstallSuffix != "" {
-Index: libgo/go/go/build/syslist.go
-===================================================================
---- a/src/libgo/go/go/build/syslist.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/go/build/syslist.go (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,8 @@
-+// Copyright 2011 The Go Authors. All rights reserved.
-+// Use of this source code is governed by a BSD-style
-+// license that can be found in the LICENSE file.
-+
-+package build
-+
-+const goosList = "darwin dragonfly freebsd linux netbsd openbsd plan9 windows solaris "
-+const goarchList = "386 amd64 arm alpha m68k mipso32 mipsn32 mipsn64 mipso64 ppc ppc64 sparc sparc64 "
-Index: libgo/go/syscall/libcall_linux.go
-===================================================================
---- a/src/libgo/go/syscall/libcall_linux.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/syscall/libcall_linux.go (.../branches/gcc-4_8-branch)
-@@ -190,6 +190,9 @@
- //sys Adjtimex(buf *Timex) (state int, err error)
- //adjtimex(buf *Timex) _C_int
-
-+//sysnb Dup3(oldfd int, newfd int, flags int) (err error)
-+//dup3(oldfd _C_int, newfd _C_int, flags _C_int) _C_int
-+
- //sys Faccessat(dirfd int, path string, mode uint32, flags int) (err error)
- //faccessat(dirfd _C_int, pathname *byte, mode _C_int, flags _C_int) _C_int
-
-@@ -268,6 +271,9 @@
- return origlen - len(buf), count, names
- }
-
-+//sys Getxattr(path string, attr string, dest []byte) (sz int, err error)
-+//getxattr(path *byte, attr *byte, buf *byte, count Size_t) Ssize_t
-+
- //sys InotifyAddWatch(fd int, pathname string, mask uint32) (watchdesc int, err error)
- //inotify_add_watch(fd _C_int, pathname *byte, mask uint32) _C_int
-
-@@ -283,6 +289,9 @@
- //sys Klogctl(typ int, buf []byte) (n int, err error)
- //klogctl(typ _C_int, bufp *byte, len _C_int) _C_int
-
-+//sys Listxattr(path string, dest []byte) (sz int, err error)
-+//listxattr(path *byte, list *byte, size Size_t) Ssize_t
-+
- //sys Mkdirat(dirfd int, path string, mode uint32) (err error)
- //mkdirat(dirfd _C_int, path *byte, mode Mode_t) _C_int
-
-@@ -305,6 +314,9 @@
- //sys PivotRoot(newroot string, putold string) (err error)
- //pivot_root(newroot *byte, putold *byte) _C_int
-
-+//sys Removexattr(path string, attr string) (err error)
-+//removexattr(path *byte, name *byte) _C_int
-+
- //sys Renameat(olddirfd int, oldpath string, newdirfd int, newpath string) (err error)
- //renameat(olddirfd _C_int, oldpath *byte, newdirfd _C_int, newpath *byte) _C_int
-
-@@ -338,6 +350,9 @@
- //sysnb Setresuid(ruid int, eguid int, suid int) (err error)
- //setresuid(ruid Uid_t, euid Uid_t, suid Uid_t) _C_int
-
-+//sys Setxattr(path string, attr string, data []byte, flags int) (err error)
-+//setxattr(path *byte, name *byte, value *byte, size Size_t, flags _C_int) _C_int
-+
- //sys splice(rfd int, roff *_loff_t, wfd int, woff *_loff_t, len int, flags int) (n int64, err error)
- //splice(rfd _C_int, roff *_loff_t, wfd _C_int, woff *_loff_t, len Size_t, flags _C_uint) Ssize_t
- func Splice(rfd int, roff *int64, wfd int, woff *int64, len int, flags int) (n int64, err error) {
-Index: libgo/go/syscall/socket.go
-===================================================================
---- a/src/libgo/go/syscall/socket.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/syscall/socket.go (.../branches/gcc-4_8-branch)
-@@ -25,7 +25,7 @@
- Pad [96]int8
- }
-
--const SizeofSockaddrAny = 0x1c
-+const SizeofSockaddrAny = 0x6c
-
- type SockaddrInet4 struct {
- Port int
-Index: libgo/go/syscall/libcall_posix.go
-===================================================================
---- a/src/libgo/go/syscall/libcall_posix.go (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/go/syscall/libcall_posix.go (.../branches/gcc-4_8-branch)
-@@ -238,6 +238,9 @@
- //sysnb Getppid() (ppid int)
- //getppid() Pid_t
-
-+//sys Getpriority(which int, who int) (prio int, err error)
-+//getpriority(which _C_int, who _C_int) _C_int
-+
- //sysnb Getrlimit(resource int, rlim *Rlimit) (err error)
- //getrlimit(resource _C_int, rlim *Rlimit) _C_int
-
-@@ -307,6 +310,9 @@
- //sysnb Setpgid(pid int, pgid int) (err error)
- //setpgid(pid Pid_t, pgid Pid_t) _C_int
-
-+//sys Setpriority(which int, who int, prio int) (err error)
-+//setpriority(which _C_int, who _C_int, prio _C_int) _C_int
-+
- //sysnb Setreuid(ruid int, euid int) (err error)
- //setreuid(ruid Uid_t, euid Uid_t) _C_int
-
-Index: libgo/Makefile.am
-===================================================================
---- a/src/libgo/Makefile.am (.../tags/gcc_4_8_2_release)
-+++ b/src/libgo/Makefile.am (.../branches/gcc-4_8-branch)
-@@ -424,6 +424,7 @@
- runtime/go-caller.c \
- runtime/go-callers.c \
- runtime/go-can-convert-interface.c \
-+ runtime/go-cdiv.c \
- runtime/go-cgo.c \
- runtime/go-check-interface.c \
- runtime/go-construct-map.c \
-@@ -1254,7 +1255,7 @@
- go/go/build/build.go \
- go/go/build/doc.go \
- go/go/build/read.go \
-- syslist.go
-+ go/go/build/syslist.go
- go_go_doc_files = \
- go/go/doc/comment.go \
- go/go/doc/doc.go \
-@@ -2712,15 +2713,6 @@
- @$(CHECK)
- .PHONY: go/build/check
-
--syslist.go: s-syslist; @true
--s-syslist: Makefile
-- echo '// Generated automatically by make.' >syslist.go.tmp
-- echo 'package build' >>syslist.go.tmp
-- echo 'const goosList = "$(GOOS)"' >>syslist.go.tmp
-- echo 'const goarchList = "$(GOARCH)"' >>syslist.go.tmp
-- $(SHELL) $(srcdir)/../move-if-change syslist.go.tmp syslist.go
-- $(STAMP) $@
--
- @go_include@ go/doc.lo.dep
- go/doc.lo.dep: $(go_go_doc_files)
- $(BUILDDEPS)
-Index: config.sub
-===================================================================
---- a/src/config.sub (.../tags/gcc_4_8_2_release)
-+++ b/src/config.sub (.../branches/gcc-4_8-branch)
-@@ -1,10 +1,8 @@
- #! /bin/sh
- # Configuration validation subroutine script.
--# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
--# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
--# 2011, 2012, 2013 Free Software Foundation, Inc.
-+# Copyright 1992-2013 Free Software Foundation, Inc.
-
--timestamp='2013-01-11'
-+timestamp='2013-10-01'
-
- # This file is free software; you can redistribute it and/or modify it
- # under the terms of the GNU General Public License as published by
-@@ -70,9 +68,7 @@
- version="\
- GNU config.sub ($timestamp)
-
--Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
--2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
--2012, 2013 Free Software Foundation, Inc.
-+Copyright 1992-2013 Free Software Foundation, Inc.
-
- This is free software; see the source for copying conditions. There is NO
- warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
-@@ -256,12 +252,12 @@
- | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
- | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
- | am33_2.0 \
-- | arc \
-+ | arc | arceb \
- | arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \
- | avr | avr32 \
- | be32 | be64 \
- | bfin \
-- | c4x | clipper \
-+ | c4x | c8051 | clipper \
- | d10v | d30v | dlx | dsp16xx \
- | epiphany \
- | fido | fr30 | frv \
-@@ -269,6 +265,7 @@
- | hexagon \
- | i370 | i860 | i960 | ia64 \
- | ip2k | iq2000 \
-+ | k1om \
- | le32 | le64 \
- | lm32 \
- | m32c | m32r | m32rle | m68000 | m68k | m88k \
-@@ -297,10 +294,10 @@
- | mt \
- | msp430 \
- | nds32 | nds32le | nds32be \
-- | nios | nios2 \
-+ | nios | nios2 | nios2eb | nios2el \
- | ns16k | ns32k \
- | open8 \
-- | or32 \
-+ | or1k | or32 \
- | pdp10 | pdp11 | pj | pjl \
- | powerpc | powerpc64 | powerpc64le | powerpcle \
- | pyramid \
-@@ -328,7 +325,7 @@
- c6x)
- basic_machine=tic6x-unknown
- ;;
-- m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | picochip)
-+ m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip)
- basic_machine=$basic_machine-unknown
- os=-none
- ;;
-@@ -370,13 +367,13 @@
- | aarch64-* | aarch64_be-* \
- | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \
- | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
-- | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \
-+ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \
- | arm-* | armbe-* | armle-* | armeb-* | armv*-* \
- | avr-* | avr32-* \
- | be32-* | be64-* \
- | bfin-* | bs2000-* \
- | c[123]* | c30-* | [cjt]90-* | c4x-* \
-- | clipper-* | craynv-* | cydra-* \
-+ | c8051-* | clipper-* | craynv-* | cydra-* \
- | d10v-* | d30v-* | dlx-* \
- | elxsi-* \
- | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
-@@ -385,6 +382,7 @@
- | hexagon-* \
- | i*86-* | i860-* | i960-* | ia64-* \
- | ip2k-* | iq2000-* \
-+ | k1om-* \
- | le32-* | le64-* \
- | lm32-* \
- | m32c-* | m32r-* | m32rle-* \
-@@ -414,7 +412,7 @@
- | mt-* \
- | msp430-* \
- | nds32-* | nds32le-* | nds32be-* \
-- | nios-* | nios2-* \
-+ | nios-* | nios2-* | nios2eb-* | nios2el-* \
- | none-* | np1-* | ns16k-* | ns32k-* \
- | open8-* \
- | orion-* \
-@@ -798,7 +796,7 @@
- os=-mingw64
- ;;
- mingw32)
-- basic_machine=i386-pc
-+ basic_machine=i686-pc
- os=-mingw32
- ;;
- mingw32ce)
-@@ -834,7 +832,7 @@
- basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'`
- ;;
- msys)
-- basic_machine=i386-pc
-+ basic_machine=i686-pc
- os=-msys
- ;;
- mvs)
-@@ -1550,6 +1548,9 @@
- c4x-* | tic4x-*)
- os=-coff
- ;;
-+ c8051-*)
-+ os=-elf
-+ ;;
- hexagon-*)
- os=-elf
- ;;
-@@ -1593,6 +1594,9 @@
- mips*-*)
- os=-elf
- ;;
-+ or1k-*)
-+ os=-elf
-+ ;;
- or32-*)
- os=-coff
- ;;
-Index: libobjc/configure
-===================================================================
---- a/src/libobjc/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libobjc/configure (.../branches/gcc-4_8-branch)
-@@ -6056,7 +6056,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6081,7 +6081,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6100,7 +6103,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -10595,7 +10601,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10598 "configure"
-+#line 10604 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -10701,7 +10707,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10704 "configure"
-+#line 10710 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11472,7 +11478,7 @@
- enableval=$enable_sjlj_exceptions; :
- else
- cat > conftest.$ac_ext << EOF
--#line 11475 "configure"
-+#line 11481 "configure"
- @interface Frob
- @end
- @implementation Frob
-Index: libobjc/ChangeLog
-===================================================================
---- a/src/libobjc/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libobjc/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,10 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libgfortran/configure
-===================================================================
---- a/src/libgfortran/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libgfortran/configure (.../branches/gcc-4_8-branch)
-@@ -8062,7 +8062,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -8087,7 +8087,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -8106,7 +8109,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -12333,7 +12339,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 12336 "configure"
-+#line 12342 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -12439,7 +12445,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 12442 "configure"
-+#line 12448 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: libgfortran/intrinsics/system_clock.c
-===================================================================
---- a/src/libgfortran/intrinsics/system_clock.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgfortran/intrinsics/system_clock.c (.../branches/gcc-4_8-branch)
-@@ -32,7 +32,8 @@
- /* POSIX states that CLOCK_REALTIME must be present if clock_gettime
- is available, others are optional. */
- #if defined(HAVE_CLOCK_GETTIME) || defined(HAVE_CLOCK_GETTIME_LIBRT)
--#ifdef CLOCK_MONOTONIC
-+#if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK) \
-+ && _POSIX_MONOTONIC_CLOCK >= 0
- #define GF_CLOCK_MONOTONIC CLOCK_MONOTONIC
- #else
- #define GF_CLOCK_MONOTONIC CLOCK_REALTIME
-Index: libgfortran/ChangeLog
-===================================================================
---- a/src/libgfortran/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libgfortran/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,75 @@
-+2014-05-03 Janne Blomqvist <jb@gcc.gnu.org>
-+
-+ Backport from 4.9
-+ PR libfortran/56919
-+ * intrinsics/system_clock.c (GF_CLOCK_MONOTONIC): Check
-+ _POSIX_MONOTONIC_CLOCK as well.
-+
-+2014-04-12 Jerry DeLisle <jvdelisle@gcc.gnu>
-+
-+ Backport from mainline
-+ PR libfortran/60810
-+ * io/unit.c (is_trim_ok): If internal unit is array, do not trim.
-+
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+ * configure: Regenerate.
-+
-+2014-03-15 Dominique d'Humieres <dominiq@lps.ens.fr>
-+
-+ Backport from mainline
-+ PR libgfortran/60128
-+ * io/write_float.def (output_float): Remove unused variable
-+ nzero_real. Replace a double space with a single one.
-+ (determine_en_precision): Fix wrong handling of the EN format.
-+
-+2014-03-15 Jerry DeLisle <jvdelisle@gcc.gnu>
-+
-+ Backport from mainline
-+ PR libfortran/58324
-+ PR libfortran/38199
-+ * io/list_read.c (finish_list_read): Read one character to check
-+ for the end of the file. If it is the end, then issue the file
-+ end error message. If not, use eat_line to reach the end
-+ without giving error. The next attempt to read will then
-+ issue the error as described above.
-+ * io/read.c (read_decimal): Quickly skip spaces to avoid calls
-+ to next_char.
-+ * io/unit.c (is_trim_ok): New helper function to check various
-+ conditions to see if its OK to trim the internal unit string.
-+ (get_internal_unit): Use LEN_TRIM to shorten selected internal
-+ unit strings for optimizing READ. Enable this optimization for
-+ formatted READ.
-+
-+2014-02-21 Jerry DeLisle <jvdelisle@gcc.gnu>
-+ Dominique d'Humieres <dominiq@lps.ens.fr>
-+ Steven G. Kargl <kargl@gcc.gnu.org>
-+
-+ Backport from mainline
-+ PR libfortran/59700
-+ PR libfortran/59764
-+ * io/io.h (struct st_parameter_dt): Assign expanded_read flag to
-+ unused bit. Define new variable line_buffer_pos.
-+ * io/list_read.c (free_saved, next_char, l_push_char,
-+ read_logical, read_real): Replace use of item_count with
-+ line_buffer_pos for line_buffer look ahead.
-+ (read_logical, read_integer, parse_real, read_real, check_type):
-+ Adjust location of free_line to after generating error messages
-+ to retain the correct item count for the message.
-+
-+2014-02-15 Jerry DeLisle <jvdelisle@gcc.gnu>
-+ Dominique d'Humieres <dominiq@lps.ens.fr>
-+
-+ Backport from mainline
-+ PR libfortran/59771
-+ PR libfortran/59774
-+ PR libfortran/59836
-+ * io/write_float.def (output_float): Fix wrong handling of the
-+ Fw.0 format.
-+ (output_float_FMT_G_): Fixes rounding issues with -m32.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libgfortran/io/list_read.c
-===================================================================
---- a/src/libgfortran/io/list_read.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgfortran/io/list_read.c (.../branches/gcc-4_8-branch)
-@@ -118,7 +118,7 @@
- static void
- free_line (st_parameter_dt *dtp)
- {
-- dtp->u.p.item_count = 0;
-+ dtp->u.p.line_buffer_pos = 0;
- dtp->u.p.line_buffer_enabled = 0;
-
- if (dtp->u.p.line_buffer == NULL)
-@@ -150,15 +150,15 @@
- {
- dtp->u.p.at_eol = 0;
-
-- c = dtp->u.p.line_buffer[dtp->u.p.item_count];
-- if (c != '\0' && dtp->u.p.item_count < 64)
-+ c = dtp->u.p.line_buffer[dtp->u.p.line_buffer_pos];
-+ if (c != '\0' && dtp->u.p.line_buffer_pos < 64)
- {
-- dtp->u.p.line_buffer[dtp->u.p.item_count] = '\0';
-- dtp->u.p.item_count++;
-+ dtp->u.p.line_buffer[dtp->u.p.line_buffer_pos] = '\0';
-+ dtp->u.p.line_buffer_pos++;
- goto done;
- }
-
-- dtp->u.p.item_count = 0;
-+ dtp->u.p.line_buffer_pos = 0;
- dtp->u.p.line_buffer_enabled = 0;
- }
-
-@@ -640,7 +640,7 @@
- if (dtp->u.p.line_buffer == NULL)
- dtp->u.p.line_buffer = xcalloc (SCRATCH_SIZE, 1);
-
-- dtp->u.p.line_buffer[dtp->u.p.item_count++] = c;
-+ dtp->u.p.line_buffer[dtp->u.p.line_buffer_pos++] = c;
- }
-
-
-@@ -750,7 +750,7 @@
- {
- dtp->u.p.nml_read_error = 1;
- dtp->u.p.line_buffer_enabled = 1;
-- dtp->u.p.item_count = 0;
-+ dtp->u.p.line_buffer_pos = 0;
- return;
- }
-
-@@ -758,14 +758,17 @@
-
- bad_logical:
-
-- free_line (dtp);
--
- if (nml_bad_return (dtp, c))
-- return;
-+ {
-+ free_line (dtp);
-+ return;
-+ }
-
-+
- free_saved (dtp);
- if (c == EOF)
- {
-+ free_line (dtp);
- hit_eof (dtp);
- return;
- }
-@@ -773,6 +776,7 @@
- eat_line (dtp);
- snprintf (message, MSGLEN, "Bad logical value while reading item %d",
- dtp->u.p.item_count);
-+ free_line (dtp);
- generate_error (&dtp->common, LIBERROR_READ_VALUE, message);
- return;
-
-@@ -913,9 +917,9 @@
- else if (c != '\n')
- eat_line (dtp);
-
-- free_line (dtp);
- snprintf (message, MSGLEN, "Bad integer for item %d in list input",
- dtp->u.p.item_count);
-+ free_line (dtp);
- generate_error (&dtp->common, LIBERROR_READ_VALUE, message);
-
- return;
-@@ -1298,9 +1302,9 @@
- else if (c != '\n')
- eat_line (dtp);
-
-- free_line (dtp);
- snprintf (message, MSGLEN, "Bad floating point number for item %d",
- dtp->u.p.item_count);
-+ free_line (dtp);
- generate_error (&dtp->common, LIBERROR_READ_VALUE, message);
-
- return 1;
-@@ -1406,9 +1410,9 @@
- else if (c != '\n')
- eat_line (dtp);
-
-- free_line (dtp);
- snprintf (message, MSGLEN, "Bad complex value in item %d of list input",
- dtp->u.p.item_count);
-+ free_line (dtp);
- generate_error (&dtp->common, LIBERROR_READ_VALUE, message);
- }
-
-@@ -1770,7 +1774,7 @@
- {
- dtp->u.p.nml_read_error = 1;
- dtp->u.p.line_buffer_enabled = 1;
-- dtp->u.p.item_count = 0;
-+ dtp->u.p.line_buffer_pos = 0;
- return;
- }
-
-@@ -1789,9 +1793,9 @@
- else if (c != '\n')
- eat_line (dtp);
-
-- free_line (dtp);
- snprintf (message, MSGLEN, "Bad real number in item %d of list input",
- dtp->u.p.item_count);
-+ free_line (dtp);
- generate_error (&dtp->common, LIBERROR_READ_VALUE, message);
- }
-
-@@ -1806,11 +1810,10 @@
-
- if (dtp->u.p.saved_type != BT_UNKNOWN && dtp->u.p.saved_type != type)
- {
-- free_line (dtp);
- snprintf (message, MSGLEN, "Read type %s where %s was expected for item %d",
- type_name (dtp->u.p.saved_type), type_name (type),
- dtp->u.p.item_count);
--
-+ free_line (dtp);
- generate_error (&dtp->common, LIBERROR_READ_VALUE, message);
- return 1;
- }
-@@ -1820,12 +1823,12 @@
-
- if (dtp->u.p.saved_length != len)
- {
-- free_line (dtp);
- snprintf (message, MSGLEN,
- "Read kind %d %s where kind %d is required for item %d",
- dtp->u.p.saved_length, type_name (dtp->u.p.saved_type), len,
- dtp->u.p.item_count);
- generate_error (&dtp->common, LIBERROR_READ_VALUE, message);
-+ free_line (dtp);
- return 1;
- }
-
-@@ -2031,8 +2034,6 @@
- void
- finish_list_read (st_parameter_dt *dtp)
- {
-- int err;
--
- free_saved (dtp);
-
- fbuf_flush (dtp->u.p.current_unit, dtp->u.p.mode);
-@@ -2043,12 +2044,22 @@
- return;
- }
-
-- err = eat_line (dtp);
-- if (err == LIBERROR_END)
-+ if (!is_internal_unit (dtp))
- {
-- free_line (dtp);
-- hit_eof (dtp);
-+ int c;
-+ c = next_char (dtp);
-+ if (c == EOF)
-+ {
-+ free_line (dtp);
-+ hit_eof (dtp);
-+ return;
-+ }
-+ if (c != '\n')
-+ eat_line (dtp);
- }
-+
-+ free_line (dtp);
-+
- }
-
- /* NAMELIST INPUT
-Index: libgfortran/io/read.c
-===================================================================
---- a/src/libgfortran/io/read.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgfortran/io/read.c (.../branches/gcc-4_8-branch)
-@@ -655,7 +655,13 @@
-
- if (c == ' ')
- {
-- if (dtp->u.p.blank_status == BLANK_NULL) continue;
-+ if (dtp->u.p.blank_status == BLANK_NULL)
-+ {
-+ /* Skip spaces. */
-+ for ( ; w > 0; p++, w--)
-+ if (*p != ' ') break;
-+ continue;
-+ }
- if (dtp->u.p.blank_status == BLANK_ZERO) c = '0';
- }
-
-Index: libgfortran/io/io.h
-===================================================================
---- a/src/libgfortran/io/io.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libgfortran/io/io.h (.../branches/gcc-4_8-branch)
-@@ -424,7 +424,10 @@
- unsigned g0_no_blanks : 1;
- /* Used to signal use of free_format_data. */
- unsigned format_not_saved : 1;
-- /* 14 unused bits. */
-+ /* A flag used to identify when a non-standard expanded namelist read
-+ has occurred. */
-+ unsigned expanded_read : 1;
-+ /* 13 unused bits. */
-
- /* Used for ungetc() style functionality. Possible values
- are an unsigned char, EOF, or EOF - 1 used to mark the
-@@ -441,9 +444,8 @@
- char *line_buffer;
- struct format_data *fmt;
- namelist_info *ionml;
-- /* A flag used to identify when a non-standard expanded namelist read
-- has occurred. */
-- int expanded_read;
-+ /* Current position within the look-ahead line buffer. */
-+ int line_buffer_pos;
- /* Storage area for values except for strings. Must be
- large enough to hold a complex value (two reals) of the
- largest kind. */
-Index: libgfortran/io/unit.c
-===================================================================
---- a/src/libgfortran/io/unit.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libgfortran/io/unit.c (.../branches/gcc-4_8-branch)
-@@ -29,6 +29,7 @@
- #include "unix.h"
- #include <stdlib.h>
- #include <string.h>
-+#include <stdbool.h>
-
-
- /* IO locking rules:
-@@ -375,6 +376,36 @@
- }
-
-
-+/* Helper function to check rank, stride, format string, and namelist.
-+ This is used for optimization. You can't trim out blanks or shorten
-+ the string if trailing spaces are significant. */
-+static bool
-+is_trim_ok (st_parameter_dt *dtp)
-+{
-+ /* Check rank and stride. */
-+ if (dtp->internal_unit_desc)
-+ return false;
-+ /* Format strings can not have 'BZ' or '/'. */
-+ if (dtp->common.flags & IOPARM_DT_HAS_FORMAT)
-+ {
-+ char *p = dtp->format;
-+ off_t i;
-+ if (dtp->common.flags & IOPARM_DT_HAS_BLANK)
-+ return false;
-+ for (i = 0; i < dtp->format_len; i++)
-+ {
-+ if (p[i] == '/') return false;
-+ if (p[i] == 'b' || p[i] == 'B')
-+ if (p[i+1] == 'z' || p[i+1] == 'Z')
-+ return false;
-+ }
-+ }
-+ if (dtp->u.p.ionml) /* A namelist. */
-+ return false;
-+ return true;
-+}
-+
-+
- gfc_unit *
- get_internal_unit (st_parameter_dt *dtp)
- {
-@@ -402,6 +433,22 @@
- some other file I/O unit. */
- iunit->unit_number = -1;
-
-+ /* As an optimization, adjust the unit record length to not
-+ include trailing blanks. This will not work under certain conditions
-+ where trailing blanks have significance. */
-+ if (dtp->u.p.mode == READING && is_trim_ok (dtp))
-+ {
-+ int len;
-+ if (dtp->common.unit == 0)
-+ len = string_len_trim (dtp->internal_unit_len,
-+ dtp->internal_unit);
-+ else
-+ len = string_len_trim_char4 (dtp->internal_unit_len,
-+ (const gfc_char4_t*) dtp->internal_unit);
-+ dtp->internal_unit_len = len;
-+ iunit->recl = dtp->internal_unit_len;
-+ }
-+
- /* Set up the looping specification from the array descriptor, if any. */
-
- if (is_array_io (dtp))
-@@ -414,27 +461,6 @@
-
- start_record *= iunit->recl;
- }
-- else
-- {
-- /* If we are not processing an array, adjust the unit record length not
-- to include trailing blanks for list-formatted reads. */
-- if (dtp->u.p.mode == READING && !(dtp->common.flags & IOPARM_DT_HAS_FORMAT))
-- {
-- if (dtp->common.unit == 0)
-- {
-- dtp->internal_unit_len =
-- string_len_trim (dtp->internal_unit_len, dtp->internal_unit);
-- iunit->recl = dtp->internal_unit_len;
-- }
-- else
-- {
-- dtp->internal_unit_len =
-- string_len_trim_char4 (dtp->internal_unit_len,
-- (const gfc_char4_t*) dtp->internal_unit);
-- iunit->recl = dtp->internal_unit_len;
-- }
-- }
-- }
-
- /* Set initial values for unit parameters. */
- if (dtp->common.unit)
-Index: libgfortran/io/write_float.def
-===================================================================
---- a/src/libgfortran/io/write_float.def (.../tags/gcc_4_8_2_release)
-+++ b/src/libgfortran/io/write_float.def (.../branches/gcc-4_8-branch)
-@@ -125,8 +125,6 @@
- int nzero;
- /* Number of digits after the decimal point. */
- int nafter;
-- /* Number of zeros after the decimal point, whatever the precision. */
-- int nzero_real;
- int leadzero;
- int nblanks;
- int ndigits, edigits;
-@@ -138,7 +136,6 @@
- p = dtp->u.p.scale_factor;
-
- rchar = '5';
-- nzero_real = -1;
-
- /* We should always know the field width and precision. */
- if (d < 0)
-@@ -191,7 +188,7 @@
- if (nafter < 0)
- nafter = 0;
- nafter = d;
-- nzero = nzero_real = 0;
-+ nzero = 0;
- }
- else /* p < 0 */
- {
-@@ -211,7 +208,6 @@
- nafter = d + nbefore;
- nbefore = 0;
- }
-- nzero_real = nzero;
- if (nzero > d)
- nzero = d;
- }
-@@ -218,7 +214,7 @@
- }
- else
- {
-- nzero = nzero_real = 0;
-+ nzero = 0;
- nafter = d;
- }
-
-@@ -373,7 +369,7 @@
- updown:
-
- rchar = '0';
-- if (w > 0 && d == 0 && p == 0)
-+ if (ft != FMT_F && w > 0 && d == 0 && p == 0)
- nbefore = 1;
- /* Scan for trailing zeros to see if we really need to round it. */
- for(i = nbefore + nafter; i < ndigits; i++)
-@@ -386,13 +382,14 @@
- do_rnd:
-
- if (nbefore + nafter == 0)
-+ /* Handle the case Fw.0 and value < 1.0 */
- {
- ndigits = 0;
-- if (nzero_real == d && digits[0] >= rchar)
-+ if (digits[0] >= rchar)
- {
- /* We rounded to zero but shouldn't have */
-- nzero--;
-- nafter = 1;
-+ nbefore = 1;
-+ digits--;
- digits[0] = '1';
- ndigits = 1;
- }
-@@ -990,7 +987,7 @@
- int d = f->u.real.d;\
- int w = f->u.real.w;\
- fnode newf;\
-- GFC_REAL_ ## x rexp_d, r = 0.5;\
-+ GFC_REAL_ ## x exp_d, r = 0.5, r_sc;\
- int low, high, mid;\
- int ubound, lbound;\
- char *p, pad = ' ';\
-@@ -997,6 +994,7 @@
- int save_scale_factor, nb = 0;\
- try result;\
- int nprinted, precision;\
-+ volatile GFC_REAL_ ## x temp;\
- \
- save_scale_factor = dtp->u.p.scale_factor;\
- \
-@@ -1015,10 +1013,13 @@
- break;\
- }\
- \
-- rexp_d = calculate_exp_ ## x (-d);\
-- if ((m > 0.0 && ((m < 0.1 - 0.1 * r * rexp_d) || (rexp_d * (m + r) >= 1.0)))\
-+ exp_d = calculate_exp_ ## x (d);\
-+ r_sc = (1 - r / exp_d);\
-+ temp = 0.1 * r_sc;\
-+ if ((m > 0.0 && ((m < temp) || (r >= (exp_d - m))))\
- || ((m == 0.0) && !(compile_options.allow_std\
-- & (GFC_STD_F2003 | GFC_STD_F2008))))\
-+ & (GFC_STD_F2003 | GFC_STD_F2008)))\
-+ || d == 0)\
- { \
- newf.format = FMT_E;\
- newf.u.real.w = w;\
-@@ -1038,10 +1039,9 @@
- \
- while (low <= high)\
- { \
-- volatile GFC_REAL_ ## x temp;\
- mid = (low + high) / 2;\
- \
-- temp = (calculate_exp_ ## x (mid - 1) * (1 - r * rexp_d));\
-+ temp = (calculate_exp_ ## x (mid - 1) * r_sc);\
- \
- if (m < temp)\
- { \
-@@ -1121,14 +1121,36 @@
- /* EN format is tricky since the number of significant digits depends
- on the magnitude. Solve it by first printing a temporary value and
- figure out the number of significant digits from the printed
-- exponent. */
-+ exponent. Values y, 0.95*10.0**e <= y <10.0**e, are rounded to
-+ 10.0**e even when the final result will not be rounded to 10.0**e.
-+ For these values the exponent returned by atoi has to be decremented
-+ by one. The values y in the ranges
-+ (1000.0-0.5*10.0**(-d))*10.0**(3*n) <= y < 10.0*(3*(n+1))
-+ (100.0-0.5*10.0**(-d))*10.0**(3*n) <= y < 10.0*(3*n+2)
-+ (10.0-0.5*10.0**(-d))*10.0**(3*n) <= y < 10.0*(3*n+1)
-+ are correctly rounded respectively to 1.0...0*10.0*(3*(n+1)),
-+ 100.0...0*10.0*(3*n), and 10.0...0*10.0*(3*n), where 0...0
-+ represents d zeroes, by the lines 279 to 297. */
-
- #define EN_PREC(x,y)\
- {\
-- GFC_REAL_ ## x tmp; \
-- tmp = * (GFC_REAL_ ## x *)source; \
-+ volatile GFC_REAL_ ## x tmp, one = 1.0;\
-+ tmp = * (GFC_REAL_ ## x *)source;\
- if (isfinite (tmp)) \
-- nprinted = DTOA(y,0,tmp); \
-+ {\
-+ nprinted = DTOA(y,0,tmp);\
-+ int e = atoi (&buffer[4]);\
-+ if (buffer[1] == '1')\
-+ {\
-+ tmp = (calculate_exp_ ## x (-e)) * tmp;\
-+ tmp = one - (tmp < 0 ? -tmp : tmp); \
-+ if (tmp > 0)\
-+ e = e - 1;\
-+ }\
-+ nbefore = e%3;\
-+ if (nbefore < 0)\
-+ nbefore = 3 + nbefore;\
-+ }\
- else\
- nprinted = -1;\
- }\
-@@ -1140,6 +1162,7 @@
- int nprinted;
- char buffer[10];
- const size_t size = 10;
-+ int nbefore; /* digits before decimal point - 1. */
-
- switch (len)
- {
-@@ -1172,16 +1195,6 @@
- if (nprinted == -1)
- return -1;
-
-- int e = atoi (&buffer[5]);
-- int nbefore; /* digits before decimal point - 1. */
-- if (e >= 0)
-- nbefore = e % 3;
-- else
-- {
-- nbefore = (-e) % 3;
-- if (nbefore != 0)
-- nbefore = 3 - nbefore;
-- }
- int prec = f->u.real.d + nbefore;
- if (dtp->u.p.current_unit->round_status != ROUND_UNSPECIFIED
- && dtp->u.p.current_unit->round_status != ROUND_PROCDEFINED)
-Index: libffi/configure
-===================================================================
---- a/src/libffi/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/configure (.../branches/gcc-4_8-branch)
-@@ -613,6 +613,7 @@
- FFI_EXEC_TRAMPOLINE_TABLE
- FFI_EXEC_TRAMPOLINE_TABLE_FALSE
- FFI_EXEC_TRAMPOLINE_TABLE_TRUE
-+HAVE_LONG_DOUBLE_VARIANT
- HAVE_LONG_DOUBLE
- ALLOCA
- TILE_FALSE
-@@ -6392,7 +6393,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6417,7 +6418,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6436,7 +6440,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -10900,7 +10907,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10903 "configure"
-+#line 10910 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11006,7 +11013,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 11009 "configure"
-+#line 11016 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -11443,6 +11450,7 @@
-
-
- TARGETDIR="unknown"
-+HAVE_LONG_DOUBLE_VARIANT=0
- case "$host" in
- aarch64*-*-*)
- TARGET=AARCH64; TARGETDIR=aarch64
-@@ -11540,6 +11548,7 @@
-
- powerpc*-*-linux* | powerpc-*-sysv*)
- TARGET=POWERPC; TARGETDIR=powerpc
-+ HAVE_LONG_DOUBLE_VARIANT=1
- ;;
- powerpc-*-amigaos*)
- TARGET=POWERPC; TARGETDIR=powerpc
-@@ -11555,6 +11564,7 @@
- ;;
- powerpc-*-freebsd* | powerpc-*-openbsd*)
- TARGET=POWERPC_FREEBSD; TARGETDIR=powerpc
-+ HAVE_LONG_DOUBLE_VARIANT=1
- ;;
- powerpc64-*-freebsd*)
- TARGET=POWERPC; TARGETDIR=powerpc
-@@ -12230,17 +12240,25 @@
- # Also AC_SUBST this variable for ffi.h.
- if test -z "$HAVE_LONG_DOUBLE"; then
- HAVE_LONG_DOUBLE=0
-- if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then
-- if test $ac_cv_sizeof_long_double != 0; then
-+ if test $ac_cv_sizeof_long_double != 0; then
-+ if test $HAVE_LONG_DOUBLE_VARIANT != 0; then
-+
-+$as_echo "#define HAVE_LONG_DOUBLE_VARIANT 1" >>confdefs.h
-+
- HAVE_LONG_DOUBLE=1
-+ else
-+ if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then
-+ HAVE_LONG_DOUBLE=1
-
- $as_echo "#define HAVE_LONG_DOUBLE 1" >>confdefs.h
-
-+ fi
- fi
- fi
- fi
-
-
-+
- { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5
- $as_echo_n "checking whether byte ordering is bigendian... " >&6; }
- if test "${ac_cv_c_bigendian+set}" = set; then :
-Index: libffi/Makefile.in
-===================================================================
---- a/src/libffi/Makefile.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/Makefile.in (.../branches/gcc-4_8-branch)
-@@ -48,10 +48,10 @@
- @IA64_TRUE@am__append_11 = src/ia64/ffi.c src/ia64/unix.S
- @M32R_TRUE@am__append_12 = src/m32r/sysv.S src/m32r/ffi.c
- @M68K_TRUE@am__append_13 = src/m68k/ffi.c src/m68k/sysv.S
--@POWERPC_TRUE@am__append_14 = src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S
-+@POWERPC_TRUE@am__append_14 = src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S
- @POWERPC_AIX_TRUE@am__append_15 = src/powerpc/ffi_darwin.c src/powerpc/aix.S src/powerpc/aix_closure.S
- @POWERPC_DARWIN_TRUE@am__append_16 = src/powerpc/ffi_darwin.c src/powerpc/darwin.S src/powerpc/darwin_closure.S
--@POWERPC_FREEBSD_TRUE@am__append_17 = src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S
-+@POWERPC_FREEBSD_TRUE@am__append_17 = src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/sysv.S src/powerpc/ppc_closure.S
- @AARCH64_TRUE@am__append_18 = src/aarch64/sysv.S src/aarch64/ffi.c
- @ARM_TRUE@am__append_19 = src/arm/sysv.S src/arm/ffi.c
- @ARM_TRUE@@FFI_EXEC_TRAMPOLINE_TABLE_TRUE@am__append_20 = src/arm/trampoline.S
-@@ -133,7 +133,9 @@
- @IA64_TRUE@am__objects_11 = src/ia64/ffi.lo src/ia64/unix.lo
- @M32R_TRUE@am__objects_12 = src/m32r/sysv.lo src/m32r/ffi.lo
- @M68K_TRUE@am__objects_13 = src/m68k/ffi.lo src/m68k/sysv.lo
--@POWERPC_TRUE@am__objects_14 = src/powerpc/ffi.lo src/powerpc/sysv.lo \
-+@POWERPC_TRUE@am__objects_14 = src/powerpc/ffi.lo \
-+@POWERPC_TRUE@ src/powerpc/ffi_sysv.lo \
-+@POWERPC_TRUE@ src/powerpc/ffi_linux64.lo src/powerpc/sysv.lo \
- @POWERPC_TRUE@ src/powerpc/ppc_closure.lo \
- @POWERPC_TRUE@ src/powerpc/linux64.lo \
- @POWERPC_TRUE@ src/powerpc/linux64_closure.lo
-@@ -144,6 +146,7 @@
- @POWERPC_DARWIN_TRUE@ src/powerpc/darwin.lo \
- @POWERPC_DARWIN_TRUE@ src/powerpc/darwin_closure.lo
- @POWERPC_FREEBSD_TRUE@am__objects_17 = src/powerpc/ffi.lo \
-+@POWERPC_FREEBSD_TRUE@ src/powerpc/ffi_sysv.lo \
- @POWERPC_FREEBSD_TRUE@ src/powerpc/sysv.lo \
- @POWERPC_FREEBSD_TRUE@ src/powerpc/ppc_closure.lo
- @AARCH64_TRUE@am__objects_18 = src/aarch64/sysv.lo src/aarch64/ffi.lo
-@@ -278,6 +281,7 @@
- FGREP = @FGREP@
- GREP = @GREP@
- HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@
-+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@
- INSTALL = @INSTALL@
- INSTALL_DATA = @INSTALL_DATA@
- INSTALL_PROGRAM = @INSTALL_PROGRAM@
-@@ -387,10 +391,12 @@
- src/ia64/unix.S src/mips/ffi.c src/mips/n32.S src/mips/o32.S \
- src/mips/ffitarget.h src/m32r/ffi.c src/m32r/sysv.S \
- src/m32r/ffitarget.h src/m68k/ffi.c src/m68k/sysv.S \
-- src/m68k/ffitarget.h src/powerpc/ffi.c src/powerpc/sysv.S \
-- src/powerpc/linux64.S src/powerpc/linux64_closure.S \
-- src/powerpc/ppc_closure.S src/powerpc/asm.h \
-- src/powerpc/aix.S src/powerpc/darwin.S \
-+ src/m68k/ffitarget.h \
-+ src/powerpc/ffi.c src/powerpc/ffi_powerpc.h \
-+ src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c \
-+ src/powerpc/sysv.S src/powerpc/linux64.S \
-+ src/powerpc/linux64_closure.S src/powerpc/ppc_closure.S \
-+ src/powerpc/asm.h src/powerpc/aix.S src/powerpc/darwin.S \
- src/powerpc/aix_closure.S src/powerpc/darwin_closure.S \
- src/powerpc/ffi_darwin.c src/powerpc/ffitarget.h \
- src/s390/ffi.c src/s390/sysv.S src/s390/ffitarget.h \
-@@ -711,6 +717,10 @@
- @: > src/powerpc/$(DEPDIR)/$(am__dirstamp)
- src/powerpc/ffi.lo: src/powerpc/$(am__dirstamp) \
- src/powerpc/$(DEPDIR)/$(am__dirstamp)
-+src/powerpc/ffi_sysv.lo: src/powerpc/$(am__dirstamp) \
-+ src/powerpc/$(DEPDIR)/$(am__dirstamp)
-+src/powerpc/ffi_linux64.lo: src/powerpc/$(am__dirstamp) \
-+ src/powerpc/$(DEPDIR)/$(am__dirstamp)
- src/powerpc/sysv.lo: src/powerpc/$(am__dirstamp) \
- src/powerpc/$(DEPDIR)/$(am__dirstamp)
- src/powerpc/ppc_closure.lo: src/powerpc/$(am__dirstamp) \
-@@ -912,6 +922,10 @@
- -rm -f src/powerpc/ffi.lo
- -rm -f src/powerpc/ffi_darwin.$(OBJEXT)
- -rm -f src/powerpc/ffi_darwin.lo
-+ -rm -f src/powerpc/ffi_linux64.$(OBJEXT)
-+ -rm -f src/powerpc/ffi_linux64.lo
-+ -rm -f src/powerpc/ffi_sysv.$(OBJEXT)
-+ -rm -f src/powerpc/ffi_sysv.lo
- -rm -f src/powerpc/linux64.$(OBJEXT)
- -rm -f src/powerpc/linux64.lo
- -rm -f src/powerpc/linux64_closure.$(OBJEXT)
-@@ -1009,6 +1023,8 @@
- @AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/darwin_closure.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi_darwin.Plo@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi_linux64.Plo@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ffi_sysv.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/linux64.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/linux64_closure.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@src/powerpc/$(DEPDIR)/ppc_closure.Plo@am__quote@
-Index: libffi/include/ffi.h.in
-===================================================================
---- a/src/libffi/include/ffi.h.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/include/ffi.h.in (.../branches/gcc-4_8-branch)
-@@ -207,6 +207,11 @@
- #endif
- } ffi_cif;
-
-+#if HAVE_LONG_DOUBLE_VARIANT
-+/* Used to adjust size/alignment of ffi types. */
-+void ffi_prep_types (ffi_abi abi);
-+# endif
-+
- /* Used internally, but overridden by some architectures */
- ffi_status ffi_prep_cif_core(ffi_cif *cif,
- ffi_abi abi,
-Index: libffi/include/Makefile.in
-===================================================================
---- a/src/libffi/include/Makefile.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/include/Makefile.in (.../branches/gcc-4_8-branch)
-@@ -113,6 +113,7 @@
- FGREP = @FGREP@
- GREP = @GREP@
- HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@
-+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@
- INSTALL = @INSTALL@
- INSTALL_DATA = @INSTALL_DATA@
- INSTALL_PROGRAM = @INSTALL_PROGRAM@
-Index: libffi/fficonfig.h.in
-===================================================================
---- a/src/libffi/fficonfig.h.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/fficonfig.h.in (.../branches/gcc-4_8-branch)
-@@ -73,6 +73,9 @@
- /* Define if you have the long double type and it is bigger than a double */
- #undef HAVE_LONG_DOUBLE
-
-+/* Define if you support more than one size of the long double type */
-+#undef HAVE_LONG_DOUBLE_VARIANT
-+
- /* Define to 1 if you have the `memcpy' function. */
- #undef HAVE_MEMCPY
-
-Index: libffi/src/powerpc/ppc_closure.S
-===================================================================
---- a/src/libffi/src/powerpc/ppc_closure.S (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/powerpc/ppc_closure.S (.../branches/gcc-4_8-branch)
-@@ -31,7 +31,7 @@
-
- .file "ppc_closure.S"
-
--#ifndef __powerpc64__
-+#ifndef POWERPC64
-
- ENTRY(ffi_closure_SYSV)
- .LFB1:
-@@ -238,7 +238,7 @@
- lwz %r3,112+0(%r1)
- lwz %r4,112+4(%r1)
- lwz %r5,112+8(%r1)
-- bl .Luint128
-+ b .Luint128
-
- # The return types below are only used when the ABI type is FFI_SYSV.
- # case FFI_SYSV_TYPE_SMALL_STRUCT + 1. One byte struct.
-@@ -378,8 +378,7 @@
- .align 2
- .LEFDE1:
-
--#endif
--
- #if defined __ELF__ && defined __linux__
- .section .note.GNU-stack,"",@progbits
- #endif
-+#endif
-Index: libffi/src/powerpc/ffitarget.h
-===================================================================
---- a/src/libffi/src/powerpc/ffitarget.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/powerpc/ffitarget.h (.../branches/gcc-4_8-branch)
-@@ -60,45 +60,76 @@
- typedef enum ffi_abi {
- FFI_FIRST_ABI = 0,
-
--#ifdef POWERPC
-- FFI_SYSV,
-- FFI_GCC_SYSV,
-- FFI_LINUX64,
-- FFI_LINUX,
-- FFI_LINUX_SOFT_FLOAT,
--# if defined(POWERPC64)
-- FFI_DEFAULT_ABI = FFI_LINUX64,
--# elif defined(__NO_FPRS__)
-- FFI_DEFAULT_ABI = FFI_LINUX_SOFT_FLOAT,
--# elif (__LDBL_MANT_DIG__ == 106)
-- FFI_DEFAULT_ABI = FFI_LINUX,
--# else
-- FFI_DEFAULT_ABI = FFI_GCC_SYSV,
--# endif
--#endif
--
--#ifdef POWERPC_AIX
-+#if defined (POWERPC_AIX)
- FFI_AIX,
- FFI_DARWIN,
- FFI_DEFAULT_ABI = FFI_AIX,
--#endif
-+ FFI_LAST_ABI
-
--#ifdef POWERPC_DARWIN
-+#elif defined (POWERPC_DARWIN)
- FFI_AIX,
- FFI_DARWIN,
- FFI_DEFAULT_ABI = FFI_DARWIN,
--#endif
-+ FFI_LAST_ABI
-
--#ifdef POWERPC_FREEBSD
-- FFI_SYSV,
-- FFI_GCC_SYSV,
-- FFI_LINUX64,
-- FFI_LINUX,
-- FFI_LINUX_SOFT_FLOAT,
-- FFI_DEFAULT_ABI = FFI_SYSV,
-+#else
-+ /* The FFI_COMPAT values are used by old code. Since libffi may be
-+ a shared library we have to support old values for backwards
-+ compatibility. */
-+ FFI_COMPAT_SYSV,
-+ FFI_COMPAT_GCC_SYSV,
-+ FFI_COMPAT_LINUX64,
-+ FFI_COMPAT_LINUX,
-+ FFI_COMPAT_LINUX_SOFT_FLOAT,
-+
-+# if defined (POWERPC64)
-+ /* This bit, always set in new code, must not be set in any of the
-+ old FFI_COMPAT values that might be used for 64-bit linux. We
-+ only need worry about FFI_COMPAT_LINUX64, but to be safe avoid
-+ all old values. */
-+ FFI_LINUX = 8,
-+ /* This and following bits can reuse FFI_COMPAT values. */
-+ FFI_LINUX_STRUCT_ALIGN = 1,
-+ FFI_LINUX_LONG_DOUBLE_128 = 2,
-+ FFI_DEFAULT_ABI = (FFI_LINUX
-+# ifdef __STRUCT_PARM_ALIGN__
-+ | FFI_LINUX_STRUCT_ALIGN
-+# endif
-+# ifdef __LONG_DOUBLE_128__
-+ | FFI_LINUX_LONG_DOUBLE_128
-+# endif
-+ ),
-+ FFI_LAST_ABI = 12
-+
-+# else
-+ /* This bit, always set in new code, must not be set in any of the
-+ old FFI_COMPAT values that might be used for 32-bit linux/sysv/bsd. */
-+ FFI_SYSV = 8,
-+ /* This and following bits can reuse FFI_COMPAT values. */
-+ FFI_SYSV_SOFT_FLOAT = 1,
-+ FFI_SYSV_STRUCT_RET = 2,
-+ FFI_SYSV_IBM_LONG_DOUBLE = 4,
-+ FFI_SYSV_LONG_DOUBLE_128 = 16,
-+
-+ FFI_DEFAULT_ABI = (FFI_SYSV
-+# ifdef __NO_FPRS__
-+ | FFI_SYSV_SOFT_FLOAT
-+# endif
-+# if (defined (__SVR4_STRUCT_RETURN) \
-+ || defined (POWERPC_FREEBSD) && !defined (__AIX_STRUCT_RETURN))
-+ | FFI_SYSV_STRUCT_RET
-+# endif
-+# if __LDBL_MANT_DIG__ == 106
-+ | FFI_SYSV_IBM_LONG_DOUBLE
-+# endif
-+# ifdef __LONG_DOUBLE_128__
-+ | FFI_SYSV_LONG_DOUBLE_128
-+# endif
-+ ),
-+ FFI_LAST_ABI = 32
-+# endif
- #endif
-
-- FFI_LAST_ABI
- } ffi_abi;
- #endif
-
-@@ -106,6 +137,10 @@
-
- #define FFI_CLOSURES 1
- #define FFI_NATIVE_RAW_API 0
-+#if defined (POWERPC) || defined (POWERPC_FREEBSD)
-+# define FFI_TARGET_SPECIFIC_VARIADIC 1
-+# define FFI_EXTRA_CIF_FIELDS unsigned nfixedargs
-+#endif
-
- /* For additional types like the below, take care about the order in
- ppc_closures.S. They must follow after the FFI_TYPE_LAST. */
-@@ -113,19 +148,26 @@
- /* Needed for soft-float long-double-128 support. */
- #define FFI_TYPE_UINT128 (FFI_TYPE_LAST + 1)
-
--/* Needed for FFI_SYSV small structure returns.
-- We use two flag bits, (FLAG_SYSV_SMST_R3, FLAG_SYSV_SMST_R4) which are
-- defined in ffi.c, to determine the exact return type and its size. */
-+/* Needed for FFI_SYSV small structure returns. */
- #define FFI_SYSV_TYPE_SMALL_STRUCT (FFI_TYPE_LAST + 2)
-
--#if defined(POWERPC64) || defined(POWERPC_AIX)
-+/* Used by ELFv2 for homogenous structure returns. */
-+#define FFI_V2_TYPE_FLOAT_HOMOG (FFI_TYPE_LAST + 1)
-+#define FFI_V2_TYPE_DOUBLE_HOMOG (FFI_TYPE_LAST + 2)
-+#define FFI_V2_TYPE_SMALL_STRUCT (FFI_TYPE_LAST + 3)
-+
-+#if _CALL_ELF == 2
-+# define FFI_TRAMPOLINE_SIZE 32
-+#else
-+# if defined(POWERPC64) || defined(POWERPC_AIX)
- # if defined(POWERPC_DARWIN64)
- # define FFI_TRAMPOLINE_SIZE 48
- # else
- # define FFI_TRAMPOLINE_SIZE 24
- # endif
--#else /* POWERPC || POWERPC_AIX */
-+# else /* POWERPC || POWERPC_AIX */
- # define FFI_TRAMPOLINE_SIZE 40
-+# endif
- #endif
-
- #ifndef LIBFFI_ASM
-Index: libffi/src/powerpc/ffi.c
-===================================================================
---- a/src/libffi/src/powerpc/ffi.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/powerpc/ffi.c (.../branches/gcc-4_8-branch)
-@@ -1,5 +1,6 @@
- /* -----------------------------------------------------------------------
-- ffi.c - Copyright (C) 2011 Anthony Green
-+ ffi.c - Copyright (C) 2013 IBM
-+ Copyright (C) 2011 Anthony Green
- Copyright (C) 2011 Kyle Moffett
- Copyright (C) 2008 Red Hat, Inc
- Copyright (C) 2007, 2008 Free Software Foundation, Inc
-@@ -27,966 +28,104 @@
- OTHER DEALINGS IN THE SOFTWARE.
- ----------------------------------------------------------------------- */
-
--#include <ffi.h>
--#include <ffi_common.h>
-+#include "ffi.h"
-+#include "ffi_common.h"
-+#include "ffi_powerpc.h"
-
--#include <stdlib.h>
--#include <stdio.h>
--
--
--extern void ffi_closure_SYSV (void);
--extern void FFI_HIDDEN ffi_closure_LINUX64 (void);
--
--enum {
-- /* The assembly depends on these exact flags. */
-- FLAG_RETURNS_SMST = 1 << (31-31), /* Used for FFI_SYSV small structs. */
-- FLAG_RETURNS_NOTHING = 1 << (31-30), /* These go in cr7 */
--#ifndef __NO_FPRS__
-- FLAG_RETURNS_FP = 1 << (31-29),
--#endif
-- FLAG_RETURNS_64BITS = 1 << (31-28),
--
-- FLAG_RETURNS_128BITS = 1 << (31-27), /* cr6 */
--
-- FLAG_ARG_NEEDS_COPY = 1 << (31- 7),
--#ifndef __NO_FPRS__
-- FLAG_FP_ARGUMENTS = 1 << (31- 6), /* cr1.eq; specified by ABI */
--#endif
-- FLAG_4_GPR_ARGUMENTS = 1 << (31- 5),
-- FLAG_RETVAL_REFERENCE = 1 << (31- 4)
--};
--
--/* About the SYSV ABI. */
--#define ASM_NEEDS_REGISTERS 4
--#define NUM_GPR_ARG_REGISTERS 8
--#ifndef __NO_FPRS__
--# define NUM_FPR_ARG_REGISTERS 8
--#endif
--
--/* ffi_prep_args_SYSV is called by the assembly routine once stack space
-- has been allocated for the function's arguments.
--
-- The stack layout we want looks like this:
--
-- | Return address from ffi_call_SYSV 4bytes | higher addresses
-- |--------------------------------------------|
-- | Previous backchain pointer 4 | stack pointer here
-- |--------------------------------------------|<+ <<< on entry to
-- | Saved r28-r31 4*4 | | ffi_call_SYSV
-- |--------------------------------------------| |
-- | GPR registers r3-r10 8*4 | | ffi_call_SYSV
-- |--------------------------------------------| |
-- | FPR registers f1-f8 (optional) 8*8 | |
-- |--------------------------------------------| | stack |
-- | Space for copied structures | | grows |
-- |--------------------------------------------| | down V
-- | Parameters that didn't fit in registers | |
-- |--------------------------------------------| | lower addresses
-- | Space for callee's LR 4 | |
-- |--------------------------------------------| | stack pointer here
-- | Current backchain pointer 4 |-/ during
-- |--------------------------------------------| <<< ffi_call_SYSV
--
--*/
--
--void
--ffi_prep_args_SYSV (extended_cif *ecif, unsigned *const stack)
-+#if HAVE_LONG_DOUBLE_VARIANT
-+/* Adjust ffi_type_longdouble. */
-+void FFI_HIDDEN
-+ffi_prep_types (ffi_abi abi)
- {
-- const unsigned bytes = ecif->cif->bytes;
-- const unsigned flags = ecif->cif->flags;
--
-- typedef union {
-- char *c;
-- unsigned *u;
-- long long *ll;
-- float *f;
-- double *d;
-- } valp;
--
-- /* 'stacktop' points at the previous backchain pointer. */
-- valp stacktop;
--
-- /* 'gpr_base' points at the space for gpr3, and grows upwards as
-- we use GPR registers. */
-- valp gpr_base;
-- int intarg_count;
--
--#ifndef __NO_FPRS__
-- /* 'fpr_base' points at the space for fpr1, and grows upwards as
-- we use FPR registers. */
-- valp fpr_base;
-- int fparg_count;
--#endif
--
-- /* 'copy_space' grows down as we put structures in it. It should
-- stay 16-byte aligned. */
-- valp copy_space;
--
-- /* 'next_arg' grows up as we put parameters in it. */
-- valp next_arg;
--
-- int i;
-- ffi_type **ptr;
--#ifndef __NO_FPRS__
-- double double_tmp;
--#endif
-- union {
-- void **v;
-- char **c;
-- signed char **sc;
-- unsigned char **uc;
-- signed short **ss;
-- unsigned short **us;
-- unsigned int **ui;
-- long long **ll;
-- float **f;
-- double **d;
-- } p_argv;
-- size_t struct_copy_size;
-- unsigned gprvalue;
--
-- stacktop.c = (char *) stack + bytes;
-- gpr_base.u = stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS;
-- intarg_count = 0;
--#ifndef __NO_FPRS__
-- fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS;
-- fparg_count = 0;
-- copy_space.c = ((flags & FLAG_FP_ARGUMENTS) ? fpr_base.c : gpr_base.c);
--#else
-- copy_space.c = gpr_base.c;
--#endif
-- next_arg.u = stack + 2;
--
-- /* Check that everything starts aligned properly. */
-- FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);
-- FFI_ASSERT (((unsigned long) copy_space.c & 0xF) == 0);
-- FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);
-- FFI_ASSERT ((bytes & 0xF) == 0);
-- FFI_ASSERT (copy_space.c >= next_arg.c);
--
-- /* Deal with return values that are actually pass-by-reference. */
-- if (flags & FLAG_RETVAL_REFERENCE)
-- {
-- *gpr_base.u++ = (unsigned long) (char *) ecif->rvalue;
-- intarg_count++;
-- }
--
-- /* Now for the arguments. */
-- p_argv.v = ecif->avalue;
-- for (ptr = ecif->cif->arg_types, i = ecif->cif->nargs;
-- i > 0;
-- i--, ptr++, p_argv.v++)
-- {
-- unsigned short typenum = (*ptr)->type;
--
-- /* We may need to handle some values depending on ABI */
-- if (ecif->cif->abi == FFI_LINUX_SOFT_FLOAT) {
-- if (typenum == FFI_TYPE_FLOAT)
-- typenum = FFI_TYPE_UINT32;
-- if (typenum == FFI_TYPE_DOUBLE)
-- typenum = FFI_TYPE_UINT64;
-- if (typenum == FFI_TYPE_LONGDOUBLE)
-- typenum = FFI_TYPE_UINT128;
-- } else if (ecif->cif->abi != FFI_LINUX) {
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- if (typenum == FFI_TYPE_LONGDOUBLE)
-- typenum = FFI_TYPE_STRUCT;
--#endif
-- }
--
-- /* Now test the translated value */
-- switch (typenum) {
--#ifndef __NO_FPRS__
-- case FFI_TYPE_FLOAT:
-- /* With FFI_LINUX_SOFT_FLOAT floats are handled like UINT32. */
-- double_tmp = **p_argv.f;
-- if (fparg_count >= NUM_FPR_ARG_REGISTERS)
-- {
-- *next_arg.f = (float) double_tmp;
-- next_arg.u += 1;
-- intarg_count++;
-- }
-- else
-- *fpr_base.d++ = double_tmp;
-- fparg_count++;
-- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-- break;
--
-- case FFI_TYPE_DOUBLE:
-- /* With FFI_LINUX_SOFT_FLOAT doubles are handled like UINT64. */
-- double_tmp = **p_argv.d;
--
-- if (fparg_count >= NUM_FPR_ARG_REGISTERS)
-- {
-- if (intarg_count >= NUM_GPR_ARG_REGISTERS
-- && intarg_count % 2 != 0)
-- {
-- intarg_count++;
-- next_arg.u++;
-- }
-- *next_arg.d = double_tmp;
-- next_arg.u += 2;
-- }
-- else
-- *fpr_base.d++ = double_tmp;
-- fparg_count++;
-- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-- break;
--
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- case FFI_TYPE_LONGDOUBLE:
-- double_tmp = (*p_argv.d)[0];
--
-- if (fparg_count >= NUM_FPR_ARG_REGISTERS - 1)
-- {
-- if (intarg_count >= NUM_GPR_ARG_REGISTERS
-- && intarg_count % 2 != 0)
-- {
-- intarg_count++;
-- next_arg.u++;
-- }
-- *next_arg.d = double_tmp;
-- next_arg.u += 2;
-- double_tmp = (*p_argv.d)[1];
-- *next_arg.d = double_tmp;
-- next_arg.u += 2;
-- }
-- else
-- {
-- *fpr_base.d++ = double_tmp;
-- double_tmp = (*p_argv.d)[1];
-- *fpr_base.d++ = double_tmp;
-- }
--
-- fparg_count += 2;
-- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-- break;
--#endif
--#endif /* have FPRs */
--
-- /*
-- * The soft float ABI for long doubles works like this, a long double
-- * is passed in four consecutive GPRs if available. A maximum of 2
-- * long doubles can be passed in gprs. If we do not have 4 GPRs
-- * left, the long double is passed on the stack, 4-byte aligned.
-- */
-- case FFI_TYPE_UINT128: {
-- unsigned int int_tmp = (*p_argv.ui)[0];
-- unsigned int ii;
-- if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3) {
-- if (intarg_count < NUM_GPR_ARG_REGISTERS)
-- intarg_count += NUM_GPR_ARG_REGISTERS - intarg_count;
-- *(next_arg.u++) = int_tmp;
-- for (ii = 1; ii < 4; ii++) {
-- int_tmp = (*p_argv.ui)[ii];
-- *(next_arg.u++) = int_tmp;
-- }
-- } else {
-- *(gpr_base.u++) = int_tmp;
-- for (ii = 1; ii < 4; ii++) {
-- int_tmp = (*p_argv.ui)[ii];
-- *(gpr_base.u++) = int_tmp;
-- }
-- }
-- intarg_count += 4;
-- break;
-- }
--
-- case FFI_TYPE_UINT64:
-- case FFI_TYPE_SINT64:
-- if (intarg_count == NUM_GPR_ARG_REGISTERS-1)
-- intarg_count++;
-- if (intarg_count >= NUM_GPR_ARG_REGISTERS)
-- {
-- if (intarg_count % 2 != 0)
-- {
-- intarg_count++;
-- next_arg.u++;
-- }
-- *next_arg.ll = **p_argv.ll;
-- next_arg.u += 2;
-- }
-- else
-- {
-- /* whoops: abi states only certain register pairs
-- * can be used for passing long long int
-- * specifically (r3,r4), (r5,r6), (r7,r8),
-- * (r9,r10) and if next arg is long long but
-- * not correct starting register of pair then skip
-- * until the proper starting register
-- */
-- if (intarg_count % 2 != 0)
-- {
-- intarg_count ++;
-- gpr_base.u++;
-- }
-- *gpr_base.ll++ = **p_argv.ll;
-- }
-- intarg_count += 2;
-- break;
--
-- case FFI_TYPE_STRUCT:
-- struct_copy_size = ((*ptr)->size + 15) & ~0xF;
-- copy_space.c -= struct_copy_size;
-- memcpy (copy_space.c, *p_argv.c, (*ptr)->size);
--
-- gprvalue = (unsigned long) copy_space.c;
--
-- FFI_ASSERT (copy_space.c > next_arg.c);
-- FFI_ASSERT (flags & FLAG_ARG_NEEDS_COPY);
-- goto putgpr;
--
-- case FFI_TYPE_UINT8:
-- gprvalue = **p_argv.uc;
-- goto putgpr;
-- case FFI_TYPE_SINT8:
-- gprvalue = **p_argv.sc;
-- goto putgpr;
-- case FFI_TYPE_UINT16:
-- gprvalue = **p_argv.us;
-- goto putgpr;
-- case FFI_TYPE_SINT16:
-- gprvalue = **p_argv.ss;
-- goto putgpr;
--
-- case FFI_TYPE_INT:
-- case FFI_TYPE_UINT32:
-- case FFI_TYPE_SINT32:
-- case FFI_TYPE_POINTER:
--
-- gprvalue = **p_argv.ui;
--
-- putgpr:
-- if (intarg_count >= NUM_GPR_ARG_REGISTERS)
-- *next_arg.u++ = gprvalue;
-- else
-- *gpr_base.u++ = gprvalue;
-- intarg_count++;
-- break;
-- }
-- }
--
-- /* Check that we didn't overrun the stack... */
-- FFI_ASSERT (copy_space.c >= next_arg.c);
-- FFI_ASSERT (gpr_base.u <= stacktop.u - ASM_NEEDS_REGISTERS);
--#ifndef __NO_FPRS__
-- FFI_ASSERT (fpr_base.u
-- <= stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS);
--#endif
-- FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS || intarg_count <= 4);
-+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+# ifdef POWERPC64
-+ ffi_prep_types_linux64 (abi);
-+# else
-+ ffi_prep_types_sysv (abi);
-+# endif
-+# endif
- }
--
--/* About the LINUX64 ABI. */
--enum {
-- NUM_GPR_ARG_REGISTERS64 = 8,
-- NUM_FPR_ARG_REGISTERS64 = 13
--};
--enum { ASM_NEEDS_REGISTERS64 = 4 };
--
--/* ffi_prep_args64 is called by the assembly routine once stack space
-- has been allocated for the function's arguments.
--
-- The stack layout we want looks like this:
--
-- | Ret addr from ffi_call_LINUX64 8bytes | higher addresses
-- |--------------------------------------------|
-- | CR save area 8bytes |
-- |--------------------------------------------|
-- | Previous backchain pointer 8 | stack pointer here
-- |--------------------------------------------|<+ <<< on entry to
-- | Saved r28-r31 4*8 | | ffi_call_LINUX64
-- |--------------------------------------------| |
-- | GPR registers r3-r10 8*8 | |
-- |--------------------------------------------| |
-- | FPR registers f1-f13 (optional) 13*8 | |
-- |--------------------------------------------| |
-- | Parameter save area | |
-- |--------------------------------------------| |
-- | TOC save area 8 | |
-- |--------------------------------------------| | stack |
-- | Linker doubleword 8 | | grows |
-- |--------------------------------------------| | down V
-- | Compiler doubleword 8 | |
-- |--------------------------------------------| | lower addresses
-- | Space for callee's LR 8 | |
-- |--------------------------------------------| |
-- | CR save area 8 | |
-- |--------------------------------------------| | stack pointer here
-- | Current backchain pointer 8 |-/ during
-- |--------------------------------------------| <<< ffi_call_LINUX64
--
--*/
--
--void FFI_HIDDEN
--ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack)
--{
-- const unsigned long bytes = ecif->cif->bytes;
-- const unsigned long flags = ecif->cif->flags;
--
-- typedef union {
-- char *c;
-- unsigned long *ul;
-- float *f;
-- double *d;
-- } valp;
--
-- /* 'stacktop' points at the previous backchain pointer. */
-- valp stacktop;
--
-- /* 'next_arg' points at the space for gpr3, and grows upwards as
-- we use GPR registers, then continues at rest. */
-- valp gpr_base;
-- valp gpr_end;
-- valp rest;
-- valp next_arg;
--
-- /* 'fpr_base' points at the space for fpr3, and grows upwards as
-- we use FPR registers. */
-- valp fpr_base;
-- int fparg_count;
--
-- int i, words;
-- ffi_type **ptr;
-- double double_tmp;
-- union {
-- void **v;
-- char **c;
-- signed char **sc;
-- unsigned char **uc;
-- signed short **ss;
-- unsigned short **us;
-- signed int **si;
-- unsigned int **ui;
-- unsigned long **ul;
-- float **f;
-- double **d;
-- } p_argv;
-- unsigned long gprvalue;
--
-- stacktop.c = (char *) stack + bytes;
-- gpr_base.ul = stacktop.ul - ASM_NEEDS_REGISTERS64 - NUM_GPR_ARG_REGISTERS64;
-- gpr_end.ul = gpr_base.ul + NUM_GPR_ARG_REGISTERS64;
-- rest.ul = stack + 6 + NUM_GPR_ARG_REGISTERS64;
-- fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS64;
-- fparg_count = 0;
-- next_arg.ul = gpr_base.ul;
--
-- /* Check that everything starts aligned properly. */
-- FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);
-- FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);
-- FFI_ASSERT ((bytes & 0xF) == 0);
--
-- /* Deal with return values that are actually pass-by-reference. */
-- if (flags & FLAG_RETVAL_REFERENCE)
-- *next_arg.ul++ = (unsigned long) (char *) ecif->rvalue;
--
-- /* Now for the arguments. */
-- p_argv.v = ecif->avalue;
-- for (ptr = ecif->cif->arg_types, i = ecif->cif->nargs;
-- i > 0;
-- i--, ptr++, p_argv.v++)
-- {
-- switch ((*ptr)->type)
-- {
-- case FFI_TYPE_FLOAT:
-- double_tmp = **p_argv.f;
-- *next_arg.f = (float) double_tmp;
-- if (++next_arg.ul == gpr_end.ul)
-- next_arg.ul = rest.ul;
-- if (fparg_count < NUM_FPR_ARG_REGISTERS64)
-- *fpr_base.d++ = double_tmp;
-- fparg_count++;
-- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-- break;
--
-- case FFI_TYPE_DOUBLE:
-- double_tmp = **p_argv.d;
-- *next_arg.d = double_tmp;
-- if (++next_arg.ul == gpr_end.ul)
-- next_arg.ul = rest.ul;
-- if (fparg_count < NUM_FPR_ARG_REGISTERS64)
-- *fpr_base.d++ = double_tmp;
-- fparg_count++;
-- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-- break;
--
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- case FFI_TYPE_LONGDOUBLE:
-- double_tmp = (*p_argv.d)[0];
-- *next_arg.d = double_tmp;
-- if (++next_arg.ul == gpr_end.ul)
-- next_arg.ul = rest.ul;
-- if (fparg_count < NUM_FPR_ARG_REGISTERS64)
-- *fpr_base.d++ = double_tmp;
-- fparg_count++;
-- double_tmp = (*p_argv.d)[1];
-- *next_arg.d = double_tmp;
-- if (++next_arg.ul == gpr_end.ul)
-- next_arg.ul = rest.ul;
-- if (fparg_count < NUM_FPR_ARG_REGISTERS64)
-- *fpr_base.d++ = double_tmp;
-- fparg_count++;
-- FFI_ASSERT (__LDBL_MANT_DIG__ == 106);
-- FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-- break;
- #endif
-
-- case FFI_TYPE_STRUCT:
-- words = ((*ptr)->size + 7) / 8;
-- if (next_arg.ul >= gpr_base.ul && next_arg.ul + words > gpr_end.ul)
-- {
-- size_t first = gpr_end.c - next_arg.c;
-- memcpy (next_arg.c, *p_argv.c, first);
-- memcpy (rest.c, *p_argv.c + first, (*ptr)->size - first);
-- next_arg.c = rest.c + words * 8 - first;
-- }
-- else
-- {
-- char *where = next_arg.c;
--
--#ifndef __LITTLE_ENDIAN__
-- /* Structures with size less than eight bytes are passed
-- left-padded. */
-- if ((*ptr)->size < 8)
-- where += 8 - (*ptr)->size;
--#endif
-- memcpy (where, *p_argv.c, (*ptr)->size);
-- next_arg.ul += words;
-- if (next_arg.ul == gpr_end.ul)
-- next_arg.ul = rest.ul;
-- }
-- break;
--
-- case FFI_TYPE_UINT8:
-- gprvalue = **p_argv.uc;
-- goto putgpr;
-- case FFI_TYPE_SINT8:
-- gprvalue = **p_argv.sc;
-- goto putgpr;
-- case FFI_TYPE_UINT16:
-- gprvalue = **p_argv.us;
-- goto putgpr;
-- case FFI_TYPE_SINT16:
-- gprvalue = **p_argv.ss;
-- goto putgpr;
-- case FFI_TYPE_UINT32:
-- gprvalue = **p_argv.ui;
-- goto putgpr;
-- case FFI_TYPE_INT:
-- case FFI_TYPE_SINT32:
-- gprvalue = **p_argv.si;
-- goto putgpr;
--
-- case FFI_TYPE_UINT64:
-- case FFI_TYPE_SINT64:
-- case FFI_TYPE_POINTER:
-- gprvalue = **p_argv.ul;
-- putgpr:
-- *next_arg.ul++ = gprvalue;
-- if (next_arg.ul == gpr_end.ul)
-- next_arg.ul = rest.ul;
-- break;
-- }
-- }
--
-- FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS
-- || (next_arg.ul >= gpr_base.ul
-- && next_arg.ul <= gpr_base.ul + 4));
--}
--
--
--
- /* Perform machine dependent cif processing */
--ffi_status
-+ffi_status FFI_HIDDEN
- ffi_prep_cif_machdep (ffi_cif *cif)
- {
-- /* All this is for the SYSV and LINUX64 ABI. */
-- int i;
-- ffi_type **ptr;
-- unsigned bytes;
-- int fparg_count = 0, intarg_count = 0;
-- unsigned flags = 0;
-- unsigned struct_copy_size = 0;
-- unsigned type = cif->rtype->type;
-- unsigned size = cif->rtype->size;
--
-- if (cif->abi != FFI_LINUX64)
-- {
-- /* All the machine-independent calculation of cif->bytes will be wrong.
-- Redo the calculation for SYSV. */
--
-- /* Space for the frame pointer, callee's LR, and the asm's temp regs. */
-- bytes = (2 + ASM_NEEDS_REGISTERS) * sizeof (int);
--
-- /* Space for the GPR registers. */
-- bytes += NUM_GPR_ARG_REGISTERS * sizeof (int);
-- }
-- else
-- {
-- /* 64-bit ABI. */
--
-- /* Space for backchain, CR, LR, cc/ld doubleword, TOC and the asm's temp
-- regs. */
-- bytes = (6 + ASM_NEEDS_REGISTERS64) * sizeof (long);
--
-- /* Space for the mandatory parm save area and general registers. */
-- bytes += 2 * NUM_GPR_ARG_REGISTERS64 * sizeof (long);
-- }
--
-- /* Return value handling. The rules for SYSV are as follows:
-- - 32-bit (or less) integer values are returned in gpr3;
-- - Structures of size <= 4 bytes also returned in gpr3;
-- - 64-bit integer values and structures between 5 and 8 bytes are returned
-- in gpr3 and gpr4;
-- - Single/double FP values are returned in fpr1;
-- - Larger structures are allocated space and a pointer is passed as
-- the first argument.
-- - long doubles (if not equivalent to double) are returned in
-- fpr1,fpr2 for Linux and as for large structs for SysV.
-- For LINUX64:
-- - integer values in gpr3;
-- - Structures/Unions by reference;
-- - Single/double FP values in fpr1, long double in fpr1,fpr2.
-- - soft-float float/doubles are treated as UINT32/UINT64 respectivley.
-- - soft-float long doubles are returned in gpr3-gpr6. */
-- /* First translate for softfloat/nonlinux */
-- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {
-- if (type == FFI_TYPE_FLOAT)
-- type = FFI_TYPE_UINT32;
-- if (type == FFI_TYPE_DOUBLE)
-- type = FFI_TYPE_UINT64;
-- if (type == FFI_TYPE_LONGDOUBLE)
-- type = FFI_TYPE_UINT128;
-- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- if (type == FFI_TYPE_LONGDOUBLE)
-- type = FFI_TYPE_STRUCT;
-+#ifdef POWERPC64
-+ return ffi_prep_cif_linux64 (cif);
-+#else
-+ return ffi_prep_cif_sysv (cif);
- #endif
-- }
-+}
-
-- switch (type)
-- {
--#ifndef __NO_FPRS__
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- case FFI_TYPE_LONGDOUBLE:
-- flags |= FLAG_RETURNS_128BITS;
-- /* Fall through. */
-+ffi_status FFI_HIDDEN
-+ffi_prep_cif_machdep_var (ffi_cif *cif,
-+ unsigned int nfixedargs MAYBE_UNUSED,
-+ unsigned int ntotalargs MAYBE_UNUSED)
-+{
-+#ifdef POWERPC64
-+ return ffi_prep_cif_linux64_var (cif, nfixedargs, ntotalargs);
-+#else
-+ return ffi_prep_cif_sysv (cif);
- #endif
-- case FFI_TYPE_DOUBLE:
-- flags |= FLAG_RETURNS_64BITS;
-- /* Fall through. */
-- case FFI_TYPE_FLOAT:
-- flags |= FLAG_RETURNS_FP;
-- break;
--#endif
--
-- case FFI_TYPE_UINT128:
-- flags |= FLAG_RETURNS_128BITS;
-- /* Fall through. */
-- case FFI_TYPE_UINT64:
-- case FFI_TYPE_SINT64:
-- flags |= FLAG_RETURNS_64BITS;
-- break;
--
-- case FFI_TYPE_STRUCT:
-- /*
-- * The final SYSV ABI says that structures smaller or equal 8 bytes
-- * are returned in r3/r4. The FFI_GCC_SYSV ABI instead returns them
-- * in memory.
-- *
-- * NOTE: The assembly code can safely assume that it just needs to
-- * store both r3 and r4 into a 8-byte word-aligned buffer, as
-- * we allocate a temporary buffer in ffi_call() if this flag is
-- * set.
-- */
-- if (cif->abi == FFI_SYSV && size <= 8)
-- flags |= FLAG_RETURNS_SMST;
-- intarg_count++;
-- flags |= FLAG_RETVAL_REFERENCE;
-- /* Fall through. */
-- case FFI_TYPE_VOID:
-- flags |= FLAG_RETURNS_NOTHING;
-- break;
--
-- default:
-- /* Returns 32-bit integer, or similar. Nothing to do here. */
-- break;
-- }
--
-- if (cif->abi != FFI_LINUX64)
-- /* The first NUM_GPR_ARG_REGISTERS words of integer arguments, and the
-- first NUM_FPR_ARG_REGISTERS fp arguments, go in registers; the rest
-- goes on the stack. Structures and long doubles (if not equivalent
-- to double) are passed as a pointer to a copy of the structure.
-- Stuff on the stack needs to keep proper alignment. */
-- for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)
-- {
-- unsigned short typenum = (*ptr)->type;
--
-- /* We may need to handle some values depending on ABI */
-- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {
-- if (typenum == FFI_TYPE_FLOAT)
-- typenum = FFI_TYPE_UINT32;
-- if (typenum == FFI_TYPE_DOUBLE)
-- typenum = FFI_TYPE_UINT64;
-- if (typenum == FFI_TYPE_LONGDOUBLE)
-- typenum = FFI_TYPE_UINT128;
-- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- if (typenum == FFI_TYPE_LONGDOUBLE)
-- typenum = FFI_TYPE_STRUCT;
--#endif
-- }
--
-- switch (typenum) {
--#ifndef __NO_FPRS__
-- case FFI_TYPE_FLOAT:
-- fparg_count++;
-- /* floating singles are not 8-aligned on stack */
-- break;
--
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- case FFI_TYPE_LONGDOUBLE:
-- fparg_count++;
-- /* Fall thru */
--#endif
-- case FFI_TYPE_DOUBLE:
-- fparg_count++;
-- /* If this FP arg is going on the stack, it must be
-- 8-byte-aligned. */
-- if (fparg_count > NUM_FPR_ARG_REGISTERS
-- && intarg_count >= NUM_GPR_ARG_REGISTERS
-- && intarg_count % 2 != 0)
-- intarg_count++;
-- break;
--#endif
-- case FFI_TYPE_UINT128:
-- /*
-- * A long double in FFI_LINUX_SOFT_FLOAT can use only a set
-- * of four consecutive gprs. If we do not have enough, we
-- * have to adjust the intarg_count value.
-- */
-- if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3
-- && intarg_count < NUM_GPR_ARG_REGISTERS)
-- intarg_count = NUM_GPR_ARG_REGISTERS;
-- intarg_count += 4;
-- break;
--
-- case FFI_TYPE_UINT64:
-- case FFI_TYPE_SINT64:
-- /* 'long long' arguments are passed as two words, but
-- either both words must fit in registers or both go
-- on the stack. If they go on the stack, they must
-- be 8-byte-aligned.
--
-- Also, only certain register pairs can be used for
-- passing long long int -- specifically (r3,r4), (r5,r6),
-- (r7,r8), (r9,r10).
-- */
-- if (intarg_count == NUM_GPR_ARG_REGISTERS-1
-- || intarg_count % 2 != 0)
-- intarg_count++;
-- intarg_count += 2;
-- break;
--
-- case FFI_TYPE_STRUCT:
-- /* We must allocate space for a copy of these to enforce
-- pass-by-value. Pad the space up to a multiple of 16
-- bytes (the maximum alignment required for anything under
-- the SYSV ABI). */
-- struct_copy_size += ((*ptr)->size + 15) & ~0xF;
-- /* Fall through (allocate space for the pointer). */
--
-- case FFI_TYPE_POINTER:
-- case FFI_TYPE_INT:
-- case FFI_TYPE_UINT32:
-- case FFI_TYPE_SINT32:
-- case FFI_TYPE_UINT16:
-- case FFI_TYPE_SINT16:
-- case FFI_TYPE_UINT8:
-- case FFI_TYPE_SINT8:
-- /* Everything else is passed as a 4-byte word in a GPR, either
-- the object itself or a pointer to it. */
-- intarg_count++;
-- break;
-- default:
-- FFI_ASSERT (0);
-- }
-- }
-- else
-- for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)
-- {
-- switch ((*ptr)->type)
-- {
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- case FFI_TYPE_LONGDOUBLE:
-- if (cif->abi == FFI_LINUX_SOFT_FLOAT)
-- intarg_count += 4;
-- else
-- {
-- fparg_count += 2;
-- intarg_count += 2;
-- }
-- break;
--#endif
-- case FFI_TYPE_FLOAT:
-- case FFI_TYPE_DOUBLE:
-- fparg_count++;
-- intarg_count++;
-- break;
--
-- case FFI_TYPE_STRUCT:
-- intarg_count += ((*ptr)->size + 7) / 8;
-- break;
--
-- case FFI_TYPE_POINTER:
-- case FFI_TYPE_UINT64:
-- case FFI_TYPE_SINT64:
-- case FFI_TYPE_INT:
-- case FFI_TYPE_UINT32:
-- case FFI_TYPE_SINT32:
-- case FFI_TYPE_UINT16:
-- case FFI_TYPE_SINT16:
-- case FFI_TYPE_UINT8:
-- case FFI_TYPE_SINT8:
-- /* Everything else is passed as a 8-byte word in a GPR, either
-- the object itself or a pointer to it. */
-- intarg_count++;
-- break;
-- default:
-- FFI_ASSERT (0);
-- }
-- }
--
--#ifndef __NO_FPRS__
-- if (fparg_count != 0)
-- flags |= FLAG_FP_ARGUMENTS;
--#endif
-- if (intarg_count > 4)
-- flags |= FLAG_4_GPR_ARGUMENTS;
-- if (struct_copy_size != 0)
-- flags |= FLAG_ARG_NEEDS_COPY;
--
-- if (cif->abi != FFI_LINUX64)
-- {
--#ifndef __NO_FPRS__
-- /* Space for the FPR registers, if needed. */
-- if (fparg_count != 0)
-- bytes += NUM_FPR_ARG_REGISTERS * sizeof (double);
--#endif
--
-- /* Stack space. */
-- if (intarg_count > NUM_GPR_ARG_REGISTERS)
-- bytes += (intarg_count - NUM_GPR_ARG_REGISTERS) * sizeof (int);
--#ifndef __NO_FPRS__
-- if (fparg_count > NUM_FPR_ARG_REGISTERS)
-- bytes += (fparg_count - NUM_FPR_ARG_REGISTERS) * sizeof (double);
--#endif
-- }
-- else
-- {
--#ifndef __NO_FPRS__
-- /* Space for the FPR registers, if needed. */
-- if (fparg_count != 0)
-- bytes += NUM_FPR_ARG_REGISTERS64 * sizeof (double);
--#endif
--
-- /* Stack space. */
-- if (intarg_count > NUM_GPR_ARG_REGISTERS64)
-- bytes += (intarg_count - NUM_GPR_ARG_REGISTERS64) * sizeof (long);
-- }
--
-- /* The stack space allocated needs to be a multiple of 16 bytes. */
-- bytes = (bytes + 15) & ~0xF;
--
-- /* Add in the space for the copied structures. */
-- bytes += struct_copy_size;
--
-- cif->flags = flags;
-- cif->bytes = bytes;
--
-- return FFI_OK;
- }
-
--extern void ffi_call_SYSV(extended_cif *, unsigned, unsigned, unsigned *,
-- void (*fn)(void));
--extern void FFI_HIDDEN ffi_call_LINUX64(extended_cif *, unsigned long,
-- unsigned long, unsigned long *,
-- void (*fn)(void));
--
- void
- ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
- {
-- /*
-- * The final SYSV ABI says that structures smaller or equal 8 bytes
-- * are returned in r3/r4. The FFI_GCC_SYSV ABI instead returns them
-- * in memory.
-- *
-- * Just to keep things simple for the assembly code, we will always
-- * bounce-buffer struct return values less than or equal to 8 bytes.
-- * This allows the ASM to handle SYSV small structures by directly
-- * writing r3 and r4 to memory without worrying about struct size.
-- */
-- unsigned int smst_buffer[2];
-+ /* The final SYSV ABI says that structures smaller or equal 8 bytes
-+ are returned in r3/r4. A draft ABI used by linux instead returns
-+ them in memory.
-+
-+ We bounce-buffer SYSV small struct return values so that sysv.S
-+ can write r3 and r4 to memory without worrying about struct size.
-+
-+ For ELFv2 ABI, use a bounce buffer for homogeneous structs too,
-+ for similar reasons. */
-+ unsigned long smst_buffer[8];
- extended_cif ecif;
-- unsigned int rsize = 0;
-
- ecif.cif = cif;
- ecif.avalue = avalue;
-
-- /* Ensure that we have a valid struct return value */
- ecif.rvalue = rvalue;
-- if (cif->rtype->type == FFI_TYPE_STRUCT) {
-- rsize = cif->rtype->size;
-- if (rsize <= 8)
-- ecif.rvalue = smst_buffer;
-- else if (!rvalue)
-- ecif.rvalue = alloca(rsize);
-- }
-+ if ((cif->flags & FLAG_RETURNS_SMST) != 0)
-+ ecif.rvalue = smst_buffer;
-+ /* Ensure that we have a valid struct return value.
-+ FIXME: Isn't this just papering over a user problem? */
-+ else if (!rvalue && cif->rtype->type == FFI_TYPE_STRUCT)
-+ ecif.rvalue = alloca (cif->rtype->size);
-
-- switch (cif->abi)
-- {
--#ifndef POWERPC64
--# ifndef __NO_FPRS__
-- case FFI_SYSV:
-- case FFI_GCC_SYSV:
-- case FFI_LINUX:
--# endif
-- case FFI_LINUX_SOFT_FLOAT:
-- ffi_call_SYSV (&ecif, -cif->bytes, cif->flags, ecif.rvalue, fn);
-- break;
-+#ifdef POWERPC64
-+ ffi_call_LINUX64 (&ecif, -(long) cif->bytes, cif->flags, ecif.rvalue, fn);
- #else
-- case FFI_LINUX64:
-- ffi_call_LINUX64 (&ecif, -(long) cif->bytes, cif->flags, ecif.rvalue, fn);
-- break;
-+ ffi_call_SYSV (&ecif, -cif->bytes, cif->flags, ecif.rvalue, fn);
- #endif
-- default:
-- FFI_ASSERT (0);
-- break;
-- }
-
- /* Check for a bounce-buffered return value */
- if (rvalue && ecif.rvalue == smst_buffer)
-- memcpy(rvalue, smst_buffer, rsize);
-+ {
-+ unsigned int rsize = cif->rtype->size;
-+#ifndef __LITTLE_ENDIAN__
-+ /* The SYSV ABI returns a structure of up to 4 bytes in size
-+ left-padded in r3. */
-+# ifndef POWERPC64
-+ if (rsize <= 4)
-+ memcpy (rvalue, (char *) smst_buffer + 4 - rsize, rsize);
-+ else
-+# endif
-+ /* The SYSV ABI returns a structure of up to 8 bytes in size
-+ left-padded in r3/r4, and the ELFv2 ABI similarly returns a
-+ structure of up to 8 bytes in size left-padded in r3. */
-+ if (rsize <= 8)
-+ memcpy (rvalue, (char *) smst_buffer + 8 - rsize, rsize);
-+ else
-+#endif
-+ memcpy (rvalue, smst_buffer, rsize);
-+ }
- }
-
-
--#ifndef POWERPC64
--#define MIN_CACHE_LINE_SIZE 8
--
--static void
--flush_icache (char *wraddr, char *xaddr, int size)
--{
-- int i;
-- for (i = 0; i < size; i += MIN_CACHE_LINE_SIZE)
-- __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;"
-- : : "r" (xaddr + i), "r" (wraddr + i) : "memory");
-- __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;" "sync;" "isync;"
-- : : "r"(xaddr + size - 1), "r"(wraddr + size - 1)
-- : "memory");
--}
--#endif
--
- ffi_status
- ffi_prep_closure_loc (ffi_closure *closure,
- ffi_cif *cif,
-@@ -995,487 +134,8 @@
- void *codeloc)
- {
- #ifdef POWERPC64
-- void **tramp = (void **) &closure->tramp[0];
--
-- if (cif->abi != FFI_LINUX64)
-- return FFI_BAD_ABI;
-- /* Copy function address and TOC from ffi_closure_LINUX64. */
-- memcpy (tramp, (char *) ffi_closure_LINUX64, 16);
-- tramp[2] = codeloc;
-+ return ffi_prep_closure_loc_linux64 (closure, cif, fun, user_data, codeloc);
- #else
-- unsigned int *tramp;
--
-- if (! (cif->abi == FFI_GCC_SYSV
-- || cif->abi == FFI_SYSV
-- || cif->abi == FFI_LINUX
-- || cif->abi == FFI_LINUX_SOFT_FLOAT))
-- return FFI_BAD_ABI;
--
-- tramp = (unsigned int *) &closure->tramp[0];
-- tramp[0] = 0x7c0802a6; /* mflr r0 */
-- tramp[1] = 0x4800000d; /* bl 10 <trampoline_initial+0x10> */
-- tramp[4] = 0x7d6802a6; /* mflr r11 */
-- tramp[5] = 0x7c0803a6; /* mtlr r0 */
-- tramp[6] = 0x800b0000; /* lwz r0,0(r11) */
-- tramp[7] = 0x816b0004; /* lwz r11,4(r11) */
-- tramp[8] = 0x7c0903a6; /* mtctr r0 */
-- tramp[9] = 0x4e800420; /* bctr */
-- *(void **) &tramp[2] = (void *) ffi_closure_SYSV; /* function */
-- *(void **) &tramp[3] = codeloc; /* context */
--
-- /* Flush the icache. */
-- flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE);
-+ return ffi_prep_closure_loc_sysv (closure, cif, fun, user_data, codeloc);
- #endif
--
-- closure->cif = cif;
-- closure->fun = fun;
-- closure->user_data = user_data;
--
-- return FFI_OK;
- }
--
--typedef union
--{
-- float f;
-- double d;
--} ffi_dblfl;
--
--int ffi_closure_helper_SYSV (ffi_closure *, void *, unsigned long *,
-- ffi_dblfl *, unsigned long *);
--
--/* Basically the trampoline invokes ffi_closure_SYSV, and on
-- * entry, r11 holds the address of the closure.
-- * After storing the registers that could possibly contain
-- * parameters to be passed into the stack frame and setting
-- * up space for a return value, ffi_closure_SYSV invokes the
-- * following helper function to do most of the work
-- */
--
--int
--ffi_closure_helper_SYSV (ffi_closure *closure, void *rvalue,
-- unsigned long *pgr, ffi_dblfl *pfr,
-- unsigned long *pst)
--{
-- /* rvalue is the pointer to space for return value in closure assembly */
-- /* pgr is the pointer to where r3-r10 are stored in ffi_closure_SYSV */
-- /* pfr is the pointer to where f1-f8 are stored in ffi_closure_SYSV */
-- /* pst is the pointer to outgoing parameter stack in original caller */
--
-- void ** avalue;
-- ffi_type ** arg_types;
-- long i, avn;
--#ifndef __NO_FPRS__
-- long nf = 0; /* number of floating registers already used */
--#endif
-- long ng = 0; /* number of general registers already used */
--
-- ffi_cif *cif = closure->cif;
-- unsigned size = cif->rtype->size;
-- unsigned short rtypenum = cif->rtype->type;
--
-- avalue = alloca (cif->nargs * sizeof (void *));
--
-- /* First translate for softfloat/nonlinux */
-- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {
-- if (rtypenum == FFI_TYPE_FLOAT)
-- rtypenum = FFI_TYPE_UINT32;
-- if (rtypenum == FFI_TYPE_DOUBLE)
-- rtypenum = FFI_TYPE_UINT64;
-- if (rtypenum == FFI_TYPE_LONGDOUBLE)
-- rtypenum = FFI_TYPE_UINT128;
-- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- if (rtypenum == FFI_TYPE_LONGDOUBLE)
-- rtypenum = FFI_TYPE_STRUCT;
--#endif
-- }
--
--
-- /* Copy the caller's structure return value address so that the closure
-- returns the data directly to the caller.
-- For FFI_SYSV the result is passed in r3/r4 if the struct size is less
-- or equal 8 bytes. */
-- if (rtypenum == FFI_TYPE_STRUCT && ((cif->abi != FFI_SYSV) || (size > 8))) {
-- rvalue = (void *) *pgr;
-- ng++;
-- pgr++;
-- }
--
-- i = 0;
-- avn = cif->nargs;
-- arg_types = cif->arg_types;
--
-- /* Grab the addresses of the arguments from the stack frame. */
-- while (i < avn) {
-- unsigned short typenum = arg_types[i]->type;
--
-- /* We may need to handle some values depending on ABI */
-- if (cif->abi == FFI_LINUX_SOFT_FLOAT) {
-- if (typenum == FFI_TYPE_FLOAT)
-- typenum = FFI_TYPE_UINT32;
-- if (typenum == FFI_TYPE_DOUBLE)
-- typenum = FFI_TYPE_UINT64;
-- if (typenum == FFI_TYPE_LONGDOUBLE)
-- typenum = FFI_TYPE_UINT128;
-- } else if (cif->abi != FFI_LINUX && cif->abi != FFI_LINUX64) {
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- if (typenum == FFI_TYPE_LONGDOUBLE)
-- typenum = FFI_TYPE_STRUCT;
--#endif
-- }
--
-- switch (typenum) {
--#ifndef __NO_FPRS__
-- case FFI_TYPE_FLOAT:
-- /* unfortunately float values are stored as doubles
-- * in the ffi_closure_SYSV code (since we don't check
-- * the type in that routine).
-- */
--
-- /* there are 8 64bit floating point registers */
--
-- if (nf < 8)
-- {
-- double temp = pfr->d;
-- pfr->f = (float) temp;
-- avalue[i] = pfr;
-- nf++;
-- pfr++;
-- }
-- else
-- {
-- /* FIXME? here we are really changing the values
-- * stored in the original calling routines outgoing
-- * parameter stack. This is probably a really
-- * naughty thing to do but...
-- */
-- avalue[i] = pst;
-- pst += 1;
-- }
-- break;
--
-- case FFI_TYPE_DOUBLE:
-- /* On the outgoing stack all values are aligned to 8 */
-- /* there are 8 64bit floating point registers */
--
-- if (nf < 8)
-- {
-- avalue[i] = pfr;
-- nf++;
-- pfr++;
-- }
-- else
-- {
-- if (((long) pst) & 4)
-- pst++;
-- avalue[i] = pst;
-- pst += 2;
-- }
-- break;
--
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- case FFI_TYPE_LONGDOUBLE:
-- if (nf < 7)
-- {
-- avalue[i] = pfr;
-- pfr += 2;
-- nf += 2;
-- }
-- else
-- {
-- if (((long) pst) & 4)
-- pst++;
-- avalue[i] = pst;
-- pst += 4;
-- nf = 8;
-- }
-- break;
--#endif
--#endif /* have FPRS */
--
-- case FFI_TYPE_UINT128:
-- /*
-- * Test if for the whole long double, 4 gprs are available.
-- * otherwise the stuff ends up on the stack.
-- */
-- if (ng < 5) {
-- avalue[i] = pgr;
-- pgr += 4;
-- ng += 4;
-- } else {
-- avalue[i] = pst;
-- pst += 4;
-- ng = 8+4;
-- }
-- break;
--
-- case FFI_TYPE_SINT8:
-- case FFI_TYPE_UINT8:
--#ifndef __LITTLE_ENDIAN__
-- /* there are 8 gpr registers used to pass values */
-- if (ng < 8)
-- {
-- avalue[i] = (char *) pgr + 3;
-- ng++;
-- pgr++;
-- }
-- else
-- {
-- avalue[i] = (char *) pst + 3;
-- pst++;
-- }
-- break;
--#endif
-- case FFI_TYPE_SINT16:
-- case FFI_TYPE_UINT16:
--#ifndef __LITTLE_ENDIAN__
-- /* there are 8 gpr registers used to pass values */
-- if (ng < 8)
-- {
-- avalue[i] = (char *) pgr + 2;
-- ng++;
-- pgr++;
-- }
-- else
-- {
-- avalue[i] = (char *) pst + 2;
-- pst++;
-- }
-- break;
--#endif
-- case FFI_TYPE_SINT32:
-- case FFI_TYPE_UINT32:
-- case FFI_TYPE_POINTER:
-- /* there are 8 gpr registers used to pass values */
-- if (ng < 8)
-- {
-- avalue[i] = pgr;
-- ng++;
-- pgr++;
-- }
-- else
-- {
-- avalue[i] = pst;
-- pst++;
-- }
-- break;
--
-- case FFI_TYPE_STRUCT:
-- /* Structs are passed by reference. The address will appear in a
-- gpr if it is one of the first 8 arguments. */
-- if (ng < 8)
-- {
-- avalue[i] = (void *) *pgr;
-- ng++;
-- pgr++;
-- }
-- else
-- {
-- avalue[i] = (void *) *pst;
-- pst++;
-- }
-- break;
--
-- case FFI_TYPE_SINT64:
-- case FFI_TYPE_UINT64:
-- /* passing long long ints are complex, they must
-- * be passed in suitable register pairs such as
-- * (r3,r4) or (r5,r6) or (r6,r7), or (r7,r8) or (r9,r10)
-- * and if the entire pair aren't available then the outgoing
-- * parameter stack is used for both but an alignment of 8
-- * must will be kept. So we must either look in pgr
-- * or pst to find the correct address for this type
-- * of parameter.
-- */
-- if (ng < 7)
-- {
-- if (ng & 0x01)
-- {
-- /* skip r4, r6, r8 as starting points */
-- ng++;
-- pgr++;
-- }
-- avalue[i] = pgr;
-- ng += 2;
-- pgr += 2;
-- }
-- else
-- {
-- if (((long) pst) & 4)
-- pst++;
-- avalue[i] = pst;
-- pst += 2;
-- ng = 8;
-- }
-- break;
--
-- default:
-- FFI_ASSERT (0);
-- }
--
-- i++;
-- }
--
--
-- (closure->fun) (cif, rvalue, avalue, closure->user_data);
--
-- /* Tell ffi_closure_SYSV how to perform return type promotions.
-- Because the FFI_SYSV ABI returns the structures <= 8 bytes in r3/r4
-- we have to tell ffi_closure_SYSV how to treat them. We combine the base
-- type FFI_SYSV_TYPE_SMALL_STRUCT - 1 with the size of the struct.
-- So a one byte struct gets the return type 16. Return type 1 to 15 are
-- already used and we never have a struct with size zero. That is the reason
-- for the subtraction of 1. See the comment in ffitarget.h about ordering.
-- */
-- if (cif->abi == FFI_SYSV && rtypenum == FFI_TYPE_STRUCT && size <= 8)
-- return (FFI_SYSV_TYPE_SMALL_STRUCT - 1) + size;
-- return rtypenum;
--}
--
--int FFI_HIDDEN ffi_closure_helper_LINUX64 (ffi_closure *, void *,
-- unsigned long *, ffi_dblfl *);
--
--int FFI_HIDDEN
--ffi_closure_helper_LINUX64 (ffi_closure *closure, void *rvalue,
-- unsigned long *pst, ffi_dblfl *pfr)
--{
-- /* rvalue is the pointer to space for return value in closure assembly */
-- /* pst is the pointer to parameter save area
-- (r3-r10 are stored into its first 8 slots by ffi_closure_LINUX64) */
-- /* pfr is the pointer to where f1-f13 are stored in ffi_closure_LINUX64 */
--
-- void **avalue;
-- ffi_type **arg_types;
-- long i, avn;
-- ffi_cif *cif;
-- ffi_dblfl *end_pfr = pfr + NUM_FPR_ARG_REGISTERS64;
--
-- cif = closure->cif;
-- avalue = alloca (cif->nargs * sizeof (void *));
--
-- /* Copy the caller's structure return value address so that the closure
-- returns the data directly to the caller. */
-- if (cif->rtype->type == FFI_TYPE_STRUCT)
-- {
-- rvalue = (void *) *pst;
-- pst++;
-- }
--
-- i = 0;
-- avn = cif->nargs;
-- arg_types = cif->arg_types;
--
-- /* Grab the addresses of the arguments from the stack frame. */
-- while (i < avn)
-- {
-- switch (arg_types[i]->type)
-- {
-- case FFI_TYPE_SINT8:
-- case FFI_TYPE_UINT8:
--#ifndef __LITTLE_ENDIAN__
-- avalue[i] = (char *) pst + 7;
-- pst++;
-- break;
--#endif
-- case FFI_TYPE_SINT16:
-- case FFI_TYPE_UINT16:
--#ifndef __LITTLE_ENDIAN__
-- avalue[i] = (char *) pst + 6;
-- pst++;
-- break;
--#endif
-- case FFI_TYPE_SINT32:
-- case FFI_TYPE_UINT32:
--#ifndef __LITTLE_ENDIAN__
-- avalue[i] = (char *) pst + 4;
-- pst++;
-- break;
--#endif
-- case FFI_TYPE_SINT64:
-- case FFI_TYPE_UINT64:
-- case FFI_TYPE_POINTER:
-- avalue[i] = pst;
-- pst++;
-- break;
--
-- case FFI_TYPE_STRUCT:
--#ifndef __LITTLE_ENDIAN__
-- /* Structures with size less than eight bytes are passed
-- left-padded. */
-- if (arg_types[i]->size < 8)
-- avalue[i] = (char *) pst + 8 - arg_types[i]->size;
-- else
--#endif
-- avalue[i] = pst;
-- pst += (arg_types[i]->size + 7) / 8;
-- break;
--
-- case FFI_TYPE_FLOAT:
-- /* unfortunately float values are stored as doubles
-- * in the ffi_closure_LINUX64 code (since we don't check
-- * the type in that routine).
-- */
--
-- /* there are 13 64bit floating point registers */
--
-- if (pfr < end_pfr)
-- {
-- double temp = pfr->d;
-- pfr->f = (float) temp;
-- avalue[i] = pfr;
-- pfr++;
-- }
-- else
-- avalue[i] = pst;
-- pst++;
-- break;
--
-- case FFI_TYPE_DOUBLE:
-- /* On the outgoing stack all values are aligned to 8 */
-- /* there are 13 64bit floating point registers */
--
-- if (pfr < end_pfr)
-- {
-- avalue[i] = pfr;
-- pfr++;
-- }
-- else
-- avalue[i] = pst;
-- pst++;
-- break;
--
--#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-- case FFI_TYPE_LONGDOUBLE:
-- if (pfr + 1 < end_pfr)
-- {
-- avalue[i] = pfr;
-- pfr += 2;
-- }
-- else
-- {
-- if (pfr < end_pfr)
-- {
-- /* Passed partly in f13 and partly on the stack.
-- Move it all to the stack. */
-- *pst = *(unsigned long *) pfr;
-- pfr++;
-- }
-- avalue[i] = pst;
-- }
-- pst += 2;
-- break;
--#endif
--
-- default:
-- FFI_ASSERT (0);
-- }
--
-- i++;
-- }
--
--
-- (closure->fun) (cif, rvalue, avalue, closure->user_data);
--
-- /* Tell ffi_closure_LINUX64 how to perform return type promotions. */
-- return cif->rtype->type;
--}
-Index: libffi/src/powerpc/sysv.S
-===================================================================
---- a/src/libffi/src/powerpc/sysv.S (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/powerpc/sysv.S (.../branches/gcc-4_8-branch)
-@@ -30,7 +30,7 @@
- #include <ffi.h>
- #include <powerpc/asm.h>
-
--#ifndef __powerpc64__
-+#ifndef POWERPC64
- .globl ffi_prep_args_SYSV
- ENTRY(ffi_call_SYSV)
- .LFB1:
-@@ -213,8 +213,8 @@
- .uleb128 0x1c
- .align 2
- .LEFDE1:
--#endif
-
- #if defined __ELF__ && defined __linux__
- .section .note.GNU-stack,"",@progbits
- #endif
-+#endif
-Index: libffi/src/powerpc/linux64_closure.S
-===================================================================
---- a/src/libffi/src/powerpc/linux64_closure.S (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/powerpc/linux64_closure.S (.../branches/gcc-4_8-branch)
-@@ -30,18 +30,25 @@
-
- .file "linux64_closure.S"
-
--#ifdef __powerpc64__
-+#ifdef POWERPC64
- FFI_HIDDEN (ffi_closure_LINUX64)
- .globl ffi_closure_LINUX64
-+# if _CALL_ELF == 2
-+ .text
-+ffi_closure_LINUX64:
-+ addis %r2, %r12, .TOC.-ffi_closure_LINUX64@ha
-+ addi %r2, %r2, .TOC.-ffi_closure_LINUX64@l
-+ .localentry ffi_closure_LINUX64, . - ffi_closure_LINUX64
-+# else
- .section ".opd","aw"
- .align 3
- ffi_closure_LINUX64:
--#ifdef _CALL_LINUX
-+# ifdef _CALL_LINUX
- .quad .L.ffi_closure_LINUX64,.TOC.@tocbase,0
- .type ffi_closure_LINUX64,@function
- .text
- .L.ffi_closure_LINUX64:
--#else
-+# else
- FFI_HIDDEN (.ffi_closure_LINUX64)
- .globl .ffi_closure_LINUX64
- .quad .ffi_closure_LINUX64,.TOC.@tocbase,0
-@@ -49,61 +56,101 @@
- .type .ffi_closure_LINUX64,@function
- .text
- .ffi_closure_LINUX64:
--#endif
-+# endif
-+# endif
-+
-+# if _CALL_ELF == 2
-+# 32 byte special reg save area + 64 byte parm save area
-+# + 64 byte retval area + 13*8 fpr save area + round to 16
-+# define STACKFRAME 272
-+# define PARMSAVE 32
-+# define RETVAL PARMSAVE+64
-+# else
-+# 48 bytes special reg save area + 64 bytes parm save area
-+# + 16 bytes retval area + 13*8 bytes fpr save area + round to 16
-+# define STACKFRAME 240
-+# define PARMSAVE 48
-+# define RETVAL PARMSAVE+64
-+# endif
-+
- .LFB1:
-- # save general regs into parm save area
-- std %r3, 48(%r1)
-- std %r4, 56(%r1)
-- std %r5, 64(%r1)
-- std %r6, 72(%r1)
-+# if _CALL_ELF == 2
-+ ld %r12, FFI_TRAMPOLINE_SIZE(%r11) # closure->cif
- mflr %r0
-+ lwz %r12, 28(%r12) # cif->flags
-+ mtcrf 0x40, %r12
-+ addi %r12, %r1, PARMSAVE
-+ bt 7, .Lparmsave
-+ # Our caller has not allocated a parameter save area.
-+ # We need to allocate one here and use it to pass gprs to
-+ # ffi_closure_helper_LINUX64.
-+ addi %r12, %r1, -STACKFRAME+PARMSAVE
-+.Lparmsave:
-+ std %r0, 16(%r1)
-+ # Save general regs into parm save area
-+ std %r3, 0(%r12)
-+ std %r4, 8(%r12)
-+ std %r5, 16(%r12)
-+ std %r6, 24(%r12)
-+ std %r7, 32(%r12)
-+ std %r8, 40(%r12)
-+ std %r9, 48(%r12)
-+ std %r10, 56(%r12)
-
-- std %r7, 80(%r1)
-- std %r8, 88(%r1)
-- std %r9, 96(%r1)
-- std %r10, 104(%r1)
-+ # load up the pointer to the parm save area
-+ mr %r5, %r12
-+# else
-+ mflr %r0
-+ # Save general regs into parm save area
-+ # This is the parameter save area set up by our caller.
-+ std %r3, PARMSAVE+0(%r1)
-+ std %r4, PARMSAVE+8(%r1)
-+ std %r5, PARMSAVE+16(%r1)
-+ std %r6, PARMSAVE+24(%r1)
-+ std %r7, PARMSAVE+32(%r1)
-+ std %r8, PARMSAVE+40(%r1)
-+ std %r9, PARMSAVE+48(%r1)
-+ std %r10, PARMSAVE+56(%r1)
-+
- std %r0, 16(%r1)
-
-- # mandatory 48 bytes special reg save area + 64 bytes parm save area
-- # + 16 bytes retval area + 13*8 bytes fpr save area + round to 16
-- stdu %r1, -240(%r1)
--.LCFI0:
-+ # load up the pointer to the parm save area
-+ addi %r5, %r1, PARMSAVE
-+# endif
-
- # next save fpr 1 to fpr 13
-- stfd %f1, 128+(0*8)(%r1)
-- stfd %f2, 128+(1*8)(%r1)
-- stfd %f3, 128+(2*8)(%r1)
-- stfd %f4, 128+(3*8)(%r1)
-- stfd %f5, 128+(4*8)(%r1)
-- stfd %f6, 128+(5*8)(%r1)
-- stfd %f7, 128+(6*8)(%r1)
-- stfd %f8, 128+(7*8)(%r1)
-- stfd %f9, 128+(8*8)(%r1)
-- stfd %f10, 128+(9*8)(%r1)
-- stfd %f11, 128+(10*8)(%r1)
-- stfd %f12, 128+(11*8)(%r1)
-- stfd %f13, 128+(12*8)(%r1)
-+ stfd %f1, -104+(0*8)(%r1)
-+ stfd %f2, -104+(1*8)(%r1)
-+ stfd %f3, -104+(2*8)(%r1)
-+ stfd %f4, -104+(3*8)(%r1)
-+ stfd %f5, -104+(4*8)(%r1)
-+ stfd %f6, -104+(5*8)(%r1)
-+ stfd %f7, -104+(6*8)(%r1)
-+ stfd %f8, -104+(7*8)(%r1)
-+ stfd %f9, -104+(8*8)(%r1)
-+ stfd %f10, -104+(9*8)(%r1)
-+ stfd %f11, -104+(10*8)(%r1)
-+ stfd %f12, -104+(11*8)(%r1)
-+ stfd %f13, -104+(12*8)(%r1)
-
-- # set up registers for the routine that actually does the work
-- # get the context pointer from the trampoline
-- mr %r3, %r11
-+ # load up the pointer to the saved fpr registers */
-+ addi %r6, %r1, -104
-
-- # now load up the pointer to the result storage
-- addi %r4, %r1, 112
-+ # load up the pointer to the result storage
-+ addi %r4, %r1, -STACKFRAME+RETVAL
-
-- # now load up the pointer to the parameter save area
-- # in the previous frame
-- addi %r5, %r1, 240 + 48
-+ stdu %r1, -STACKFRAME(%r1)
-+.LCFI0:
-
-- # now load up the pointer to the saved fpr registers */
-- addi %r6, %r1, 128
-+ # get the context pointer from the trampoline
-+ mr %r3, %r11
-
- # make the call
--#ifdef _CALL_LINUX
-+# if defined _CALL_LINUX || _CALL_ELF == 2
- bl ffi_closure_helper_LINUX64
--#else
-+# else
- bl .ffi_closure_helper_LINUX64
--#endif
-+# endif
- .Lret:
-
- # now r3 contains the return type
-@@ -112,10 +159,12 @@
-
- # look up the proper starting point in table
- # by using return type as offset
-+ ld %r0, STACKFRAME+16(%r1)
-+ cmpldi %r3, FFI_V2_TYPE_SMALL_STRUCT
-+ bge .Lsmall
- mflr %r4 # move address of .Lret to r4
- sldi %r3, %r3, 4 # now multiply return type by 16
- addi %r4, %r4, .Lret_type0 - .Lret
-- ld %r0, 240+16(%r1)
- add %r3, %r3, %r4 # add contents of table to table address
- mtctr %r3
- bctr # jump to it
-@@ -128,117 +177,175 @@
- .Lret_type0:
- # case FFI_TYPE_VOID
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- nop
- # case FFI_TYPE_INT
--#ifdef __LITTLE_ENDIAN__
-- lwa %r3, 112+0(%r1)
--#else
-- lwa %r3, 112+4(%r1)
--#endif
-+# ifdef __LITTLE_ENDIAN__
-+ lwa %r3, RETVAL+0(%r1)
-+# else
-+ lwa %r3, RETVAL+4(%r1)
-+# endif
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_FLOAT
-- lfs %f1, 112+0(%r1)
-+ lfs %f1, RETVAL+0(%r1)
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_DOUBLE
-- lfd %f1, 112+0(%r1)
-+ lfd %f1, RETVAL+0(%r1)
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_LONGDOUBLE
-- lfd %f1, 112+0(%r1)
-+ lfd %f1, RETVAL+0(%r1)
- mtlr %r0
-- lfd %f2, 112+8(%r1)
-+ lfd %f2, RETVAL+8(%r1)
- b .Lfinish
- # case FFI_TYPE_UINT8
--#ifdef __LITTLE_ENDIAN__
-- lbz %r3, 112+0(%r1)
--#else
-- lbz %r3, 112+7(%r1)
--#endif
-+# ifdef __LITTLE_ENDIAN__
-+ lbz %r3, RETVAL+0(%r1)
-+# else
-+ lbz %r3, RETVAL+7(%r1)
-+# endif
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_SINT8
--#ifdef __LITTLE_ENDIAN__
-- lbz %r3, 112+0(%r1)
--#else
-- lbz %r3, 112+7(%r1)
--#endif
-+# ifdef __LITTLE_ENDIAN__
-+ lbz %r3, RETVAL+0(%r1)
-+# else
-+ lbz %r3, RETVAL+7(%r1)
-+# endif
- extsb %r3,%r3
- mtlr %r0
- b .Lfinish
- # case FFI_TYPE_UINT16
--#ifdef __LITTLE_ENDIAN__
-- lhz %r3, 112+0(%r1)
--#else
-- lhz %r3, 112+6(%r1)
--#endif
-+# ifdef __LITTLE_ENDIAN__
-+ lhz %r3, RETVAL+0(%r1)
-+# else
-+ lhz %r3, RETVAL+6(%r1)
-+# endif
- mtlr %r0
- .Lfinish:
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_SINT16
--#ifdef __LITTLE_ENDIAN__
-- lha %r3, 112+0(%r1)
--#else
-- lha %r3, 112+6(%r1)
--#endif
-+# ifdef __LITTLE_ENDIAN__
-+ lha %r3, RETVAL+0(%r1)
-+# else
-+ lha %r3, RETVAL+6(%r1)
-+# endif
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_UINT32
--#ifdef __LITTLE_ENDIAN__
-- lwz %r3, 112+0(%r1)
--#else
-- lwz %r3, 112+4(%r1)
--#endif
-+# ifdef __LITTLE_ENDIAN__
-+ lwz %r3, RETVAL+0(%r1)
-+# else
-+ lwz %r3, RETVAL+4(%r1)
-+# endif
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_SINT32
--#ifdef __LITTLE_ENDIAN__
-- lwa %r3, 112+0(%r1)
--#else
-- lwa %r3, 112+4(%r1)
--#endif
-+# ifdef __LITTLE_ENDIAN__
-+ lwa %r3, RETVAL+0(%r1)
-+# else
-+ lwa %r3, RETVAL+4(%r1)
-+# endif
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_UINT64
-- ld %r3, 112+0(%r1)
-+ ld %r3, RETVAL+0(%r1)
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_SINT64
-- ld %r3, 112+0(%r1)
-+ ld %r3, RETVAL+0(%r1)
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- # case FFI_TYPE_STRUCT
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
- nop
- # case FFI_TYPE_POINTER
-- ld %r3, 112+0(%r1)
-+ ld %r3, RETVAL+0(%r1)
- mtlr %r0
-- addi %r1, %r1, 240
-+ addi %r1, %r1, STACKFRAME
- blr
--# esac
-+# case FFI_V2_TYPE_FLOAT_HOMOG
-+ lfs %f1, RETVAL+0(%r1)
-+ lfs %f2, RETVAL+4(%r1)
-+ lfs %f3, RETVAL+8(%r1)
-+ b .Lmorefloat
-+# case FFI_V2_TYPE_DOUBLE_HOMOG
-+ lfd %f1, RETVAL+0(%r1)
-+ lfd %f2, RETVAL+8(%r1)
-+ lfd %f3, RETVAL+16(%r1)
-+ lfd %f4, RETVAL+24(%r1)
-+ mtlr %r0
-+ lfd %f5, RETVAL+32(%r1)
-+ lfd %f6, RETVAL+40(%r1)
-+ lfd %f7, RETVAL+48(%r1)
-+ lfd %f8, RETVAL+56(%r1)
-+ addi %r1, %r1, STACKFRAME
-+ blr
-+.Lmorefloat:
-+ lfs %f4, RETVAL+12(%r1)
-+ mtlr %r0
-+ lfs %f5, RETVAL+16(%r1)
-+ lfs %f6, RETVAL+20(%r1)
-+ lfs %f7, RETVAL+24(%r1)
-+ lfs %f8, RETVAL+28(%r1)
-+ addi %r1, %r1, STACKFRAME
-+ blr
-+.Lsmall:
-+# ifdef __LITTLE_ENDIAN__
-+ ld %r3,RETVAL+0(%r1)
-+ mtlr %r0
-+ ld %r4,RETVAL+8(%r1)
-+ addi %r1, %r1, STACKFRAME
-+ blr
-+# else
-+ # A struct smaller than a dword is returned in the low bits of r3
-+ # ie. right justified. Larger structs are passed left justified
-+ # in r3 and r4. The return value area on the stack will have
-+ # the structs as they are usually stored in memory.
-+ cmpldi %r3, FFI_V2_TYPE_SMALL_STRUCT + 7 # size 8 bytes?
-+ neg %r5, %r3
-+ ld %r3,RETVAL+0(%r1)
-+ blt .Lsmalldown
-+ mtlr %r0
-+ ld %r4,RETVAL+8(%r1)
-+ addi %r1, %r1, STACKFRAME
-+ blr
-+.Lsmalldown:
-+ addi %r5, %r5, FFI_V2_TYPE_SMALL_STRUCT + 7
-+ mtlr %r0
-+ sldi %r5, %r5, 3
-+ addi %r1, %r1, STACKFRAME
-+ srd %r3, %r3, %r5
-+ blr
-+# endif
-+
- .LFE1:
- .long 0
- .byte 0,12,0,1,128,0,0,0
--#ifdef _CALL_LINUX
-+# if _CALL_ELF == 2
-+ .size ffi_closure_LINUX64,.-ffi_closure_LINUX64
-+# else
-+# ifdef _CALL_LINUX
- .size ffi_closure_LINUX64,.-.L.ffi_closure_LINUX64
--#else
-+# else
- .size .ffi_closure_LINUX64,.-.ffi_closure_LINUX64
--#endif
-+# endif
-+# endif
-
- .section .eh_frame,EH_FRAME_FLAGS,@progbits
- .Lframe1:
-@@ -267,14 +374,14 @@
- .byte 0x2 # DW_CFA_advance_loc1
- .byte .LCFI0-.LFB1
- .byte 0xe # DW_CFA_def_cfa_offset
-- .uleb128 240
-+ .uleb128 STACKFRAME
- .byte 0x11 # DW_CFA_offset_extended_sf
- .uleb128 0x41
- .sleb128 -2
- .align 3
- .LEFDE1:
--#endif
-
--#if defined __ELF__ && defined __linux__
-+# if defined __ELF__ && defined __linux__
- .section .note.GNU-stack,"",@progbits
-+# endif
- #endif
-Index: libffi/src/powerpc/ffi_powerpc.h
-===================================================================
---- a/src/libffi/src/powerpc/ffi_powerpc.h (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/powerpc/ffi_powerpc.h (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,77 @@
-+/* -----------------------------------------------------------------------
-+ ffi_powerpc.h - Copyright (C) 2013 IBM
-+ Copyright (C) 2011 Anthony Green
-+ Copyright (C) 2011 Kyle Moffett
-+ Copyright (C) 2008 Red Hat, Inc
-+ Copyright (C) 2007, 2008 Free Software Foundation, Inc
-+ Copyright (c) 1998 Geoffrey Keating
-+
-+ PowerPC Foreign Function Interface
-+
-+ Permission is hereby granted, free of charge, to any person obtaining
-+ a copy of this software and associated documentation files (the
-+ ``Software''), to deal in the Software without restriction, including
-+ without limitation the rights to use, copy, modify, merge, publish,
-+ distribute, sublicense, and/or sell copies of the Software, and to
-+ permit persons to whom the Software is furnished to do so, subject to
-+ the following conditions:
-+
-+ The above copyright notice and this permission notice shall be included
-+ in all copies or substantial portions of the Software.
-+
-+ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-+ IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ OTHER DEALINGS IN THE SOFTWARE.
-+ ----------------------------------------------------------------------- */
-+
-+enum {
-+ /* The assembly depends on these exact flags. */
-+ /* These go in cr7 */
-+ FLAG_RETURNS_SMST = 1 << (31-31), /* Used for FFI_SYSV small structs. */
-+ FLAG_RETURNS_NOTHING = 1 << (31-30),
-+ FLAG_RETURNS_FP = 1 << (31-29),
-+ FLAG_RETURNS_64BITS = 1 << (31-28),
-+
-+ /* This goes in cr6 */
-+ FLAG_RETURNS_128BITS = 1 << (31-27),
-+
-+ FLAG_COMPAT = 1 << (31- 8), /* Not used by assembly */
-+
-+ /* These go in cr1 */
-+ FLAG_ARG_NEEDS_COPY = 1 << (31- 7), /* Used by sysv code */
-+ FLAG_ARG_NEEDS_PSAVE = FLAG_ARG_NEEDS_COPY, /* Used by linux64 code */
-+ FLAG_FP_ARGUMENTS = 1 << (31- 6), /* cr1.eq; specified by ABI */
-+ FLAG_4_GPR_ARGUMENTS = 1 << (31- 5),
-+ FLAG_RETVAL_REFERENCE = 1 << (31- 4)
-+};
-+
-+typedef union
-+{
-+ float f;
-+ double d;
-+} ffi_dblfl;
-+
-+void FFI_HIDDEN ffi_closure_SYSV (void);
-+void FFI_HIDDEN ffi_call_SYSV(extended_cif *, unsigned, unsigned, unsigned *,
-+ void (*)(void));
-+
-+void FFI_HIDDEN ffi_prep_types_sysv (ffi_abi);
-+ffi_status FFI_HIDDEN ffi_prep_cif_sysv (ffi_cif *);
-+int FFI_HIDDEN ffi_closure_helper_SYSV (ffi_closure *, void *, unsigned long *,
-+ ffi_dblfl *, unsigned long *);
-+
-+void FFI_HIDDEN ffi_call_LINUX64(extended_cif *, unsigned long, unsigned long,
-+ unsigned long *, void (*)(void));
-+void FFI_HIDDEN ffi_closure_LINUX64 (void);
-+
-+void FFI_HIDDEN ffi_prep_types_linux64 (ffi_abi);
-+ffi_status FFI_HIDDEN ffi_prep_cif_linux64 (ffi_cif *);
-+ffi_status FFI_HIDDEN ffi_prep_cif_linux64_var (ffi_cif *, unsigned int,
-+ unsigned int);
-+void FFI_HIDDEN ffi_prep_args64 (extended_cif *, unsigned long *const);
-+int FFI_HIDDEN ffi_closure_helper_LINUX64 (ffi_closure *, void *,
-+ unsigned long *, ffi_dblfl *);
-Index: libffi/src/powerpc/ffi_sysv.c
-===================================================================
---- a/src/libffi/src/powerpc/ffi_sysv.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/powerpc/ffi_sysv.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,931 @@
-+/* -----------------------------------------------------------------------
-+ ffi_sysv.c - Copyright (C) 2013 IBM
-+ Copyright (C) 2011 Anthony Green
-+ Copyright (C) 2011 Kyle Moffett
-+ Copyright (C) 2008 Red Hat, Inc
-+ Copyright (C) 2007, 2008 Free Software Foundation, Inc
-+ Copyright (c) 1998 Geoffrey Keating
-+
-+ PowerPC Foreign Function Interface
-+
-+ Permission is hereby granted, free of charge, to any person obtaining
-+ a copy of this software and associated documentation files (the
-+ ``Software''), to deal in the Software without restriction, including
-+ without limitation the rights to use, copy, modify, merge, publish,
-+ distribute, sublicense, and/or sell copies of the Software, and to
-+ permit persons to whom the Software is furnished to do so, subject to
-+ the following conditions:
-+
-+ The above copyright notice and this permission notice shall be included
-+ in all copies or substantial portions of the Software.
-+
-+ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-+ IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ OTHER DEALINGS IN THE SOFTWARE.
-+ ----------------------------------------------------------------------- */
-+
-+#include "ffi.h"
-+
-+#ifndef POWERPC64
-+#include "ffi_common.h"
-+#include "ffi_powerpc.h"
-+
-+
-+/* About the SYSV ABI. */
-+#define ASM_NEEDS_REGISTERS 4
-+#define NUM_GPR_ARG_REGISTERS 8
-+#define NUM_FPR_ARG_REGISTERS 8
-+
-+
-+#if HAVE_LONG_DOUBLE_VARIANT && FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+/* Adjust size of ffi_type_longdouble. */
-+void FFI_HIDDEN
-+ffi_prep_types_sysv (ffi_abi abi)
-+{
-+ if ((abi & (FFI_SYSV | FFI_SYSV_LONG_DOUBLE_128)) == FFI_SYSV)
-+ {
-+ ffi_type_longdouble.size = 8;
-+ ffi_type_longdouble.alignment = 8;
-+ }
-+ else
-+ {
-+ ffi_type_longdouble.size = 16;
-+ ffi_type_longdouble.alignment = 16;
-+ }
-+}
-+#endif
-+
-+/* Transform long double, double and float to other types as per abi. */
-+static int
-+translate_float (int abi, int type)
-+{
-+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ if (type == FFI_TYPE_LONGDOUBLE
-+ && (abi & FFI_SYSV_LONG_DOUBLE_128) == 0)
-+ type = FFI_TYPE_DOUBLE;
-+#endif
-+ if ((abi & FFI_SYSV_SOFT_FLOAT) != 0)
-+ {
-+ if (type == FFI_TYPE_FLOAT)
-+ type = FFI_TYPE_UINT32;
-+ else if (type == FFI_TYPE_DOUBLE)
-+ type = FFI_TYPE_UINT64;
-+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ else if (type == FFI_TYPE_LONGDOUBLE)
-+ type = FFI_TYPE_UINT128;
-+ }
-+ else if ((abi & FFI_SYSV_IBM_LONG_DOUBLE) == 0)
-+ {
-+ if (type == FFI_TYPE_LONGDOUBLE)
-+ type = FFI_TYPE_STRUCT;
-+#endif
-+ }
-+ return type;
-+}
-+
-+/* Perform machine dependent cif processing */
-+static ffi_status
-+ffi_prep_cif_sysv_core (ffi_cif *cif)
-+{
-+ ffi_type **ptr;
-+ unsigned bytes;
-+ unsigned i, fparg_count = 0, intarg_count = 0;
-+ unsigned flags = cif->flags;
-+ unsigned struct_copy_size = 0;
-+ unsigned type = cif->rtype->type;
-+ unsigned size = cif->rtype->size;
-+
-+ /* The machine-independent calculation of cif->bytes doesn't work
-+ for us. Redo the calculation. */
-+
-+ /* Space for the frame pointer, callee's LR, and the asm's temp regs. */
-+ bytes = (2 + ASM_NEEDS_REGISTERS) * sizeof (int);
-+
-+ /* Space for the GPR registers. */
-+ bytes += NUM_GPR_ARG_REGISTERS * sizeof (int);
-+
-+ /* Return value handling. The rules for SYSV are as follows:
-+ - 32-bit (or less) integer values are returned in gpr3;
-+ - Structures of size <= 4 bytes also returned in gpr3;
-+ - 64-bit integer values and structures between 5 and 8 bytes are returned
-+ in gpr3 and gpr4;
-+ - Larger structures are allocated space and a pointer is passed as
-+ the first argument.
-+ - Single/double FP values are returned in fpr1;
-+ - long doubles (if not equivalent to double) are returned in
-+ fpr1,fpr2 for Linux and as for large structs for SysV. */
-+
-+ type = translate_float (cif->abi, type);
-+
-+ switch (type)
-+ {
-+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ case FFI_TYPE_LONGDOUBLE:
-+ flags |= FLAG_RETURNS_128BITS;
-+ /* Fall through. */
-+#endif
-+ case FFI_TYPE_DOUBLE:
-+ flags |= FLAG_RETURNS_64BITS;
-+ /* Fall through. */
-+ case FFI_TYPE_FLOAT:
-+ flags |= FLAG_RETURNS_FP;
-+#ifdef __NO_FPRS__
-+ return FFI_BAD_ABI;
-+#endif
-+ break;
-+
-+ case FFI_TYPE_UINT128:
-+ flags |= FLAG_RETURNS_128BITS;
-+ /* Fall through. */
-+ case FFI_TYPE_UINT64:
-+ case FFI_TYPE_SINT64:
-+ flags |= FLAG_RETURNS_64BITS;
-+ break;
-+
-+ case FFI_TYPE_STRUCT:
-+ /* The final SYSV ABI says that structures smaller or equal 8 bytes
-+ are returned in r3/r4. A draft ABI used by linux instead
-+ returns them in memory. */
-+ if ((cif->abi & FFI_SYSV_STRUCT_RET) != 0 && size <= 8)
-+ {
-+ flags |= FLAG_RETURNS_SMST;
-+ break;
-+ }
-+ intarg_count++;
-+ flags |= FLAG_RETVAL_REFERENCE;
-+ /* Fall through. */
-+ case FFI_TYPE_VOID:
-+ flags |= FLAG_RETURNS_NOTHING;
-+ break;
-+
-+ default:
-+ /* Returns 32-bit integer, or similar. Nothing to do here. */
-+ break;
-+ }
-+
-+ /* The first NUM_GPR_ARG_REGISTERS words of integer arguments, and the
-+ first NUM_FPR_ARG_REGISTERS fp arguments, go in registers; the rest
-+ goes on the stack. Structures and long doubles (if not equivalent
-+ to double) are passed as a pointer to a copy of the structure.
-+ Stuff on the stack needs to keep proper alignment. */
-+ for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)
-+ {
-+ unsigned short typenum = (*ptr)->type;
-+
-+ typenum = translate_float (cif->abi, typenum);
-+
-+ switch (typenum)
-+ {
-+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ case FFI_TYPE_LONGDOUBLE:
-+ fparg_count++;
-+ /* Fall thru */
-+#endif
-+ case FFI_TYPE_DOUBLE:
-+ fparg_count++;
-+ /* If this FP arg is going on the stack, it must be
-+ 8-byte-aligned. */
-+ if (fparg_count > NUM_FPR_ARG_REGISTERS
-+ && intarg_count >= NUM_GPR_ARG_REGISTERS
-+ && intarg_count % 2 != 0)
-+ intarg_count++;
-+#ifdef __NO_FPRS__
-+ return FFI_BAD_ABI;
-+#endif
-+ break;
-+
-+ case FFI_TYPE_FLOAT:
-+ fparg_count++;
-+#ifdef __NO_FPRS__
-+ return FFI_BAD_ABI;
-+#endif
-+ break;
-+
-+ case FFI_TYPE_UINT128:
-+ /* A long double in FFI_LINUX_SOFT_FLOAT can use only a set
-+ of four consecutive gprs. If we do not have enough, we
-+ have to adjust the intarg_count value. */
-+ if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3
-+ && intarg_count < NUM_GPR_ARG_REGISTERS)
-+ intarg_count = NUM_GPR_ARG_REGISTERS;
-+ intarg_count += 4;
-+ break;
-+
-+ case FFI_TYPE_UINT64:
-+ case FFI_TYPE_SINT64:
-+ /* 'long long' arguments are passed as two words, but
-+ either both words must fit in registers or both go
-+ on the stack. If they go on the stack, they must
-+ be 8-byte-aligned.
-+
-+ Also, only certain register pairs can be used for
-+ passing long long int -- specifically (r3,r4), (r5,r6),
-+ (r7,r8), (r9,r10). */
-+ if (intarg_count == NUM_GPR_ARG_REGISTERS-1
-+ || intarg_count % 2 != 0)
-+ intarg_count++;
-+ intarg_count += 2;
-+ break;
-+
-+ case FFI_TYPE_STRUCT:
-+ /* We must allocate space for a copy of these to enforce
-+ pass-by-value. Pad the space up to a multiple of 16
-+ bytes (the maximum alignment required for anything under
-+ the SYSV ABI). */
-+ struct_copy_size += ((*ptr)->size + 15) & ~0xF;
-+ /* Fall through (allocate space for the pointer). */
-+
-+ case FFI_TYPE_POINTER:
-+ case FFI_TYPE_INT:
-+ case FFI_TYPE_UINT32:
-+ case FFI_TYPE_SINT32:
-+ case FFI_TYPE_UINT16:
-+ case FFI_TYPE_SINT16:
-+ case FFI_TYPE_UINT8:
-+ case FFI_TYPE_SINT8:
-+ /* Everything else is passed as a 4-byte word in a GPR, either
-+ the object itself or a pointer to it. */
-+ intarg_count++;
-+ break;
-+
-+ default:
-+ FFI_ASSERT (0);
-+ }
-+ }
-+
-+ if (fparg_count != 0)
-+ flags |= FLAG_FP_ARGUMENTS;
-+ if (intarg_count > 4)
-+ flags |= FLAG_4_GPR_ARGUMENTS;
-+ if (struct_copy_size != 0)
-+ flags |= FLAG_ARG_NEEDS_COPY;
-+
-+ /* Space for the FPR registers, if needed. */
-+ if (fparg_count != 0)
-+ bytes += NUM_FPR_ARG_REGISTERS * sizeof (double);
-+
-+ /* Stack space. */
-+ if (intarg_count > NUM_GPR_ARG_REGISTERS)
-+ bytes += (intarg_count - NUM_GPR_ARG_REGISTERS) * sizeof (int);
-+ if (fparg_count > NUM_FPR_ARG_REGISTERS)
-+ bytes += (fparg_count - NUM_FPR_ARG_REGISTERS) * sizeof (double);
-+
-+ /* The stack space allocated needs to be a multiple of 16 bytes. */
-+ bytes = (bytes + 15) & ~0xF;
-+
-+ /* Add in the space for the copied structures. */
-+ bytes += struct_copy_size;
-+
-+ cif->flags = flags;
-+ cif->bytes = bytes;
-+
-+ return FFI_OK;
-+}
-+
-+ffi_status FFI_HIDDEN
-+ffi_prep_cif_sysv (ffi_cif *cif)
-+{
-+ if ((cif->abi & FFI_SYSV) == 0)
-+ {
-+ /* This call is from old code. Translate to new ABI values. */
-+ cif->flags |= FLAG_COMPAT;
-+ switch (cif->abi)
-+ {
-+ default:
-+ return FFI_BAD_ABI;
-+
-+ case FFI_COMPAT_SYSV:
-+ cif->abi = FFI_SYSV | FFI_SYSV_STRUCT_RET | FFI_SYSV_LONG_DOUBLE_128;
-+ break;
-+
-+ case FFI_COMPAT_GCC_SYSV:
-+ cif->abi = FFI_SYSV | FFI_SYSV_LONG_DOUBLE_128;
-+ break;
-+
-+ case FFI_COMPAT_LINUX:
-+ cif->abi = (FFI_SYSV | FFI_SYSV_IBM_LONG_DOUBLE
-+ | FFI_SYSV_LONG_DOUBLE_128);
-+ break;
-+
-+ case FFI_COMPAT_LINUX_SOFT_FLOAT:
-+ cif->abi = (FFI_SYSV | FFI_SYSV_SOFT_FLOAT | FFI_SYSV_IBM_LONG_DOUBLE
-+ | FFI_SYSV_LONG_DOUBLE_128);
-+ break;
-+ }
-+ }
-+ return ffi_prep_cif_sysv_core (cif);
-+}
-+
-+/* ffi_prep_args_SYSV is called by the assembly routine once stack space
-+ has been allocated for the function's arguments.
-+
-+ The stack layout we want looks like this:
-+
-+ | Return address from ffi_call_SYSV 4bytes | higher addresses
-+ |--------------------------------------------|
-+ | Previous backchain pointer 4 | stack pointer here
-+ |--------------------------------------------|<+ <<< on entry to
-+ | Saved r28-r31 4*4 | | ffi_call_SYSV
-+ |--------------------------------------------| |
-+ | GPR registers r3-r10 8*4 | | ffi_call_SYSV
-+ |--------------------------------------------| |
-+ | FPR registers f1-f8 (optional) 8*8 | |
-+ |--------------------------------------------| | stack |
-+ | Space for copied structures | | grows |
-+ |--------------------------------------------| | down V
-+ | Parameters that didn't fit in registers | |
-+ |--------------------------------------------| | lower addresses
-+ | Space for callee's LR 4 | |
-+ |--------------------------------------------| | stack pointer here
-+ | Current backchain pointer 4 |-/ during
-+ |--------------------------------------------| <<< ffi_call_SYSV
-+
-+*/
-+
-+void FFI_HIDDEN
-+ffi_prep_args_SYSV (extended_cif *ecif, unsigned *const stack)
-+{
-+ const unsigned bytes = ecif->cif->bytes;
-+ const unsigned flags = ecif->cif->flags;
-+
-+ typedef union
-+ {
-+ char *c;
-+ unsigned *u;
-+ long long *ll;
-+ float *f;
-+ double *d;
-+ } valp;
-+
-+ /* 'stacktop' points at the previous backchain pointer. */
-+ valp stacktop;
-+
-+ /* 'gpr_base' points at the space for gpr3, and grows upwards as
-+ we use GPR registers. */
-+ valp gpr_base;
-+ int intarg_count;
-+
-+#ifndef __NO_FPRS__
-+ /* 'fpr_base' points at the space for fpr1, and grows upwards as
-+ we use FPR registers. */
-+ valp fpr_base;
-+ int fparg_count;
-+#endif
-+
-+ /* 'copy_space' grows down as we put structures in it. It should
-+ stay 16-byte aligned. */
-+ valp copy_space;
-+
-+ /* 'next_arg' grows up as we put parameters in it. */
-+ valp next_arg;
-+
-+ int i;
-+ ffi_type **ptr;
-+#ifndef __NO_FPRS__
-+ double double_tmp;
-+#endif
-+ union
-+ {
-+ void **v;
-+ char **c;
-+ signed char **sc;
-+ unsigned char **uc;
-+ signed short **ss;
-+ unsigned short **us;
-+ unsigned int **ui;
-+ long long **ll;
-+ float **f;
-+ double **d;
-+ } p_argv;
-+ size_t struct_copy_size;
-+ unsigned gprvalue;
-+
-+ stacktop.c = (char *) stack + bytes;
-+ gpr_base.u = stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS;
-+ intarg_count = 0;
-+#ifndef __NO_FPRS__
-+ fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS;
-+ fparg_count = 0;
-+ copy_space.c = ((flags & FLAG_FP_ARGUMENTS) ? fpr_base.c : gpr_base.c);
-+#else
-+ copy_space.c = gpr_base.c;
-+#endif
-+ next_arg.u = stack + 2;
-+
-+ /* Check that everything starts aligned properly. */
-+ FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);
-+ FFI_ASSERT (((unsigned long) copy_space.c & 0xF) == 0);
-+ FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);
-+ FFI_ASSERT ((bytes & 0xF) == 0);
-+ FFI_ASSERT (copy_space.c >= next_arg.c);
-+
-+ /* Deal with return values that are actually pass-by-reference. */
-+ if (flags & FLAG_RETVAL_REFERENCE)
-+ {
-+ *gpr_base.u++ = (unsigned long) (char *) ecif->rvalue;
-+ intarg_count++;
-+ }
-+
-+ /* Now for the arguments. */
-+ p_argv.v = ecif->avalue;
-+ for (ptr = ecif->cif->arg_types, i = ecif->cif->nargs;
-+ i > 0;
-+ i--, ptr++, p_argv.v++)
-+ {
-+ unsigned int typenum = (*ptr)->type;
-+
-+ typenum = translate_float (ecif->cif->abi, typenum);
-+
-+ /* Now test the translated value */
-+ switch (typenum)
-+ {
-+#ifndef __NO_FPRS__
-+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ case FFI_TYPE_LONGDOUBLE:
-+ double_tmp = (*p_argv.d)[0];
-+
-+ if (fparg_count >= NUM_FPR_ARG_REGISTERS - 1)
-+ {
-+ if (intarg_count >= NUM_GPR_ARG_REGISTERS
-+ && intarg_count % 2 != 0)
-+ {
-+ intarg_count++;
-+ next_arg.u++;
-+ }
-+ *next_arg.d = double_tmp;
-+ next_arg.u += 2;
-+ double_tmp = (*p_argv.d)[1];
-+ *next_arg.d = double_tmp;
-+ next_arg.u += 2;
-+ }
-+ else
-+ {
-+ *fpr_base.d++ = double_tmp;
-+ double_tmp = (*p_argv.d)[1];
-+ *fpr_base.d++ = double_tmp;
-+ }
-+
-+ fparg_count += 2;
-+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-+ break;
-+# endif
-+ case FFI_TYPE_DOUBLE:
-+ double_tmp = **p_argv.d;
-+
-+ if (fparg_count >= NUM_FPR_ARG_REGISTERS)
-+ {
-+ if (intarg_count >= NUM_GPR_ARG_REGISTERS
-+ && intarg_count % 2 != 0)
-+ {
-+ intarg_count++;
-+ next_arg.u++;
-+ }
-+ *next_arg.d = double_tmp;
-+ next_arg.u += 2;
-+ }
-+ else
-+ *fpr_base.d++ = double_tmp;
-+ fparg_count++;
-+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-+ break;
-+
-+ case FFI_TYPE_FLOAT:
-+ double_tmp = **p_argv.f;
-+ if (fparg_count >= NUM_FPR_ARG_REGISTERS)
-+ {
-+ *next_arg.f = (float) double_tmp;
-+ next_arg.u += 1;
-+ intarg_count++;
-+ }
-+ else
-+ *fpr_base.d++ = double_tmp;
-+ fparg_count++;
-+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-+ break;
-+#endif /* have FPRs */
-+
-+ case FFI_TYPE_UINT128:
-+ /* The soft float ABI for long doubles works like this, a long double
-+ is passed in four consecutive GPRs if available. A maximum of 2
-+ long doubles can be passed in gprs. If we do not have 4 GPRs
-+ left, the long double is passed on the stack, 4-byte aligned. */
-+ {
-+ unsigned int int_tmp;
-+ unsigned int ii;
-+ if (intarg_count >= NUM_GPR_ARG_REGISTERS - 3)
-+ {
-+ if (intarg_count < NUM_GPR_ARG_REGISTERS)
-+ intarg_count = NUM_GPR_ARG_REGISTERS;
-+ for (ii = 0; ii < 4; ii++)
-+ {
-+ int_tmp = (*p_argv.ui)[ii];
-+ *next_arg.u++ = int_tmp;
-+ }
-+ }
-+ else
-+ {
-+ for (ii = 0; ii < 4; ii++)
-+ {
-+ int_tmp = (*p_argv.ui)[ii];
-+ *gpr_base.u++ = int_tmp;
-+ }
-+ }
-+ intarg_count += 4;
-+ break;
-+ }
-+
-+ case FFI_TYPE_UINT64:
-+ case FFI_TYPE_SINT64:
-+ if (intarg_count == NUM_GPR_ARG_REGISTERS-1)
-+ intarg_count++;
-+ if (intarg_count >= NUM_GPR_ARG_REGISTERS)
-+ {
-+ if (intarg_count % 2 != 0)
-+ {
-+ intarg_count++;
-+ next_arg.u++;
-+ }
-+ *next_arg.ll = **p_argv.ll;
-+ next_arg.u += 2;
-+ }
-+ else
-+ {
-+ /* The abi states only certain register pairs can be
-+ used for passing long long int specifically (r3,r4),
-+ (r5,r6), (r7,r8), (r9,r10). If next arg is long long
-+ but not correct starting register of pair then skip
-+ until the proper starting register. */
-+ if (intarg_count % 2 != 0)
-+ {
-+ intarg_count ++;
-+ gpr_base.u++;
-+ }
-+ *gpr_base.ll++ = **p_argv.ll;
-+ }
-+ intarg_count += 2;
-+ break;
-+
-+ case FFI_TYPE_STRUCT:
-+ struct_copy_size = ((*ptr)->size + 15) & ~0xF;
-+ copy_space.c -= struct_copy_size;
-+ memcpy (copy_space.c, *p_argv.c, (*ptr)->size);
-+
-+ gprvalue = (unsigned long) copy_space.c;
-+
-+ FFI_ASSERT (copy_space.c > next_arg.c);
-+ FFI_ASSERT (flags & FLAG_ARG_NEEDS_COPY);
-+ goto putgpr;
-+
-+ case FFI_TYPE_UINT8:
-+ gprvalue = **p_argv.uc;
-+ goto putgpr;
-+ case FFI_TYPE_SINT8:
-+ gprvalue = **p_argv.sc;
-+ goto putgpr;
-+ case FFI_TYPE_UINT16:
-+ gprvalue = **p_argv.us;
-+ goto putgpr;
-+ case FFI_TYPE_SINT16:
-+ gprvalue = **p_argv.ss;
-+ goto putgpr;
-+
-+ case FFI_TYPE_INT:
-+ case FFI_TYPE_UINT32:
-+ case FFI_TYPE_SINT32:
-+ case FFI_TYPE_POINTER:
-+
-+ gprvalue = **p_argv.ui;
-+
-+ putgpr:
-+ if (intarg_count >= NUM_GPR_ARG_REGISTERS)
-+ *next_arg.u++ = gprvalue;
-+ else
-+ *gpr_base.u++ = gprvalue;
-+ intarg_count++;
-+ break;
-+ }
-+ }
-+
-+ /* Check that we didn't overrun the stack... */
-+ FFI_ASSERT (copy_space.c >= next_arg.c);
-+ FFI_ASSERT (gpr_base.u <= stacktop.u - ASM_NEEDS_REGISTERS);
-+ /* The assert below is testing that the number of integer arguments agrees
-+ with the number found in ffi_prep_cif_machdep(). However, intarg_count
-+ is incremented whenever we place an FP arg on the stack, so account for
-+ that before our assert test. */
-+#ifndef __NO_FPRS__
-+ if (fparg_count > NUM_FPR_ARG_REGISTERS)
-+ intarg_count -= fparg_count - NUM_FPR_ARG_REGISTERS;
-+ FFI_ASSERT (fpr_base.u
-+ <= stacktop.u - ASM_NEEDS_REGISTERS - NUM_GPR_ARG_REGISTERS);
-+#endif
-+ FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS || intarg_count <= 4);
-+}
-+
-+#define MIN_CACHE_LINE_SIZE 8
-+
-+static void
-+flush_icache (char *wraddr, char *xaddr, int size)
-+{
-+ int i;
-+ for (i = 0; i < size; i += MIN_CACHE_LINE_SIZE)
-+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;"
-+ : : "r" (xaddr + i), "r" (wraddr + i) : "memory");
-+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;" "sync;" "isync;"
-+ : : "r"(xaddr + size - 1), "r"(wraddr + size - 1)
-+ : "memory");
-+}
-+
-+ffi_status FFI_HIDDEN
-+ffi_prep_closure_loc_sysv (ffi_closure *closure,
-+ ffi_cif *cif,
-+ void (*fun) (ffi_cif *, void *, void **, void *),
-+ void *user_data,
-+ void *codeloc)
-+{
-+ unsigned int *tramp;
-+
-+ if (cif->abi < FFI_SYSV || cif->abi >= FFI_LAST_ABI)
-+ return FFI_BAD_ABI;
-+
-+ tramp = (unsigned int *) &closure->tramp[0];
-+ tramp[0] = 0x7c0802a6; /* mflr r0 */
-+ tramp[1] = 0x4800000d; /* bl 10 <trampoline_initial+0x10> */
-+ tramp[4] = 0x7d6802a6; /* mflr r11 */
-+ tramp[5] = 0x7c0803a6; /* mtlr r0 */
-+ tramp[6] = 0x800b0000; /* lwz r0,0(r11) */
-+ tramp[7] = 0x816b0004; /* lwz r11,4(r11) */
-+ tramp[8] = 0x7c0903a6; /* mtctr r0 */
-+ tramp[9] = 0x4e800420; /* bctr */
-+ *(void **) &tramp[2] = (void *) ffi_closure_SYSV; /* function */
-+ *(void **) &tramp[3] = codeloc; /* context */
-+
-+ /* Flush the icache. */
-+ flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE);
-+
-+ closure->cif = cif;
-+ closure->fun = fun;
-+ closure->user_data = user_data;
-+
-+ return FFI_OK;
-+}
-+
-+/* Basically the trampoline invokes ffi_closure_SYSV, and on
-+ entry, r11 holds the address of the closure.
-+ After storing the registers that could possibly contain
-+ parameters to be passed into the stack frame and setting
-+ up space for a return value, ffi_closure_SYSV invokes the
-+ following helper function to do most of the work. */
-+
-+int
-+ffi_closure_helper_SYSV (ffi_closure *closure, void *rvalue,
-+ unsigned long *pgr, ffi_dblfl *pfr,
-+ unsigned long *pst)
-+{
-+ /* rvalue is the pointer to space for return value in closure assembly */
-+ /* pgr is the pointer to where r3-r10 are stored in ffi_closure_SYSV */
-+ /* pfr is the pointer to where f1-f8 are stored in ffi_closure_SYSV */
-+ /* pst is the pointer to outgoing parameter stack in original caller */
-+
-+ void ** avalue;
-+ ffi_type ** arg_types;
-+ long i, avn;
-+#ifndef __NO_FPRS__
-+ long nf = 0; /* number of floating registers already used */
-+#endif
-+ long ng = 0; /* number of general registers already used */
-+
-+ ffi_cif *cif = closure->cif;
-+ unsigned size = cif->rtype->size;
-+ unsigned short rtypenum = cif->rtype->type;
-+
-+ avalue = alloca (cif->nargs * sizeof (void *));
-+
-+ /* First translate for softfloat/nonlinux */
-+ rtypenum = translate_float (cif->abi, rtypenum);
-+
-+ /* Copy the caller's structure return value address so that the closure
-+ returns the data directly to the caller.
-+ For FFI_SYSV the result is passed in r3/r4 if the struct size is less
-+ or equal 8 bytes. */
-+ if (rtypenum == FFI_TYPE_STRUCT
-+ && !((cif->abi & FFI_SYSV_STRUCT_RET) != 0 && size <= 8))
-+ {
-+ rvalue = (void *) *pgr;
-+ ng++;
-+ pgr++;
-+ }
-+
-+ i = 0;
-+ avn = cif->nargs;
-+ arg_types = cif->arg_types;
-+
-+ /* Grab the addresses of the arguments from the stack frame. */
-+ while (i < avn) {
-+ unsigned short typenum = arg_types[i]->type;
-+
-+ /* We may need to handle some values depending on ABI. */
-+ typenum = translate_float (cif->abi, typenum);
-+
-+ switch (typenum)
-+ {
-+#ifndef __NO_FPRS__
-+ case FFI_TYPE_FLOAT:
-+ /* Unfortunately float values are stored as doubles
-+ in the ffi_closure_SYSV code (since we don't check
-+ the type in that routine). */
-+ if (nf < NUM_FPR_ARG_REGISTERS)
-+ {
-+ /* FIXME? here we are really changing the values
-+ stored in the original calling routines outgoing
-+ parameter stack. This is probably a really
-+ naughty thing to do but... */
-+ double temp = pfr->d;
-+ pfr->f = (float) temp;
-+ avalue[i] = pfr;
-+ nf++;
-+ pfr++;
-+ }
-+ else
-+ {
-+ avalue[i] = pst;
-+ pst += 1;
-+ }
-+ break;
-+
-+ case FFI_TYPE_DOUBLE:
-+ if (nf < NUM_FPR_ARG_REGISTERS)
-+ {
-+ avalue[i] = pfr;
-+ nf++;
-+ pfr++;
-+ }
-+ else
-+ {
-+ if (((long) pst) & 4)
-+ pst++;
-+ avalue[i] = pst;
-+ pst += 2;
-+ }
-+ break;
-+
-+# if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ case FFI_TYPE_LONGDOUBLE:
-+ if (nf < NUM_FPR_ARG_REGISTERS - 1)
-+ {
-+ avalue[i] = pfr;
-+ pfr += 2;
-+ nf += 2;
-+ }
-+ else
-+ {
-+ if (((long) pst) & 4)
-+ pst++;
-+ avalue[i] = pst;
-+ pst += 4;
-+ nf = 8;
-+ }
-+ break;
-+# endif
-+#endif
-+
-+ case FFI_TYPE_UINT128:
-+ /* Test if for the whole long double, 4 gprs are available.
-+ otherwise the stuff ends up on the stack. */
-+ if (ng < NUM_GPR_ARG_REGISTERS - 3)
-+ {
-+ avalue[i] = pgr;
-+ pgr += 4;
-+ ng += 4;
-+ }
-+ else
-+ {
-+ avalue[i] = pst;
-+ pst += 4;
-+ ng = 8+4;
-+ }
-+ break;
-+
-+ case FFI_TYPE_SINT8:
-+ case FFI_TYPE_UINT8:
-+#ifndef __LITTLE_ENDIAN__
-+ if (ng < NUM_GPR_ARG_REGISTERS)
-+ {
-+ avalue[i] = (char *) pgr + 3;
-+ ng++;
-+ pgr++;
-+ }
-+ else
-+ {
-+ avalue[i] = (char *) pst + 3;
-+ pst++;
-+ }
-+ break;
-+#endif
-+
-+ case FFI_TYPE_SINT16:
-+ case FFI_TYPE_UINT16:
-+#ifndef __LITTLE_ENDIAN__
-+ if (ng < NUM_GPR_ARG_REGISTERS)
-+ {
-+ avalue[i] = (char *) pgr + 2;
-+ ng++;
-+ pgr++;
-+ }
-+ else
-+ {
-+ avalue[i] = (char *) pst + 2;
-+ pst++;
-+ }
-+ break;
-+#endif
-+
-+ case FFI_TYPE_SINT32:
-+ case FFI_TYPE_UINT32:
-+ case FFI_TYPE_POINTER:
-+ if (ng < NUM_GPR_ARG_REGISTERS)
-+ {
-+ avalue[i] = pgr;
-+ ng++;
-+ pgr++;
-+ }
-+ else
-+ {
-+ avalue[i] = pst;
-+ pst++;
-+ }
-+ break;
-+
-+ case FFI_TYPE_STRUCT:
-+ /* Structs are passed by reference. The address will appear in a
-+ gpr if it is one of the first 8 arguments. */
-+ if (ng < NUM_GPR_ARG_REGISTERS)
-+ {
-+ avalue[i] = (void *) *pgr;
-+ ng++;
-+ pgr++;
-+ }
-+ else
-+ {
-+ avalue[i] = (void *) *pst;
-+ pst++;
-+ }
-+ break;
-+
-+ case FFI_TYPE_SINT64:
-+ case FFI_TYPE_UINT64:
-+ /* Passing long long ints are complex, they must
-+ be passed in suitable register pairs such as
-+ (r3,r4) or (r5,r6) or (r6,r7), or (r7,r8) or (r9,r10)
-+ and if the entire pair aren't available then the outgoing
-+ parameter stack is used for both but an alignment of 8
-+ must will be kept. So we must either look in pgr
-+ or pst to find the correct address for this type
-+ of parameter. */
-+ if (ng < NUM_GPR_ARG_REGISTERS - 1)
-+ {
-+ if (ng & 1)
-+ {
-+ /* skip r4, r6, r8 as starting points */
-+ ng++;
-+ pgr++;
-+ }
-+ avalue[i] = pgr;
-+ ng += 2;
-+ pgr += 2;
-+ }
-+ else
-+ {
-+ if (((long) pst) & 4)
-+ pst++;
-+ avalue[i] = pst;
-+ pst += 2;
-+ ng = NUM_GPR_ARG_REGISTERS;
-+ }
-+ break;
-+
-+ default:
-+ FFI_ASSERT (0);
-+ }
-+
-+ i++;
-+ }
-+
-+ (closure->fun) (cif, rvalue, avalue, closure->user_data);
-+
-+ /* Tell ffi_closure_SYSV how to perform return type promotions.
-+ Because the FFI_SYSV ABI returns the structures <= 8 bytes in
-+ r3/r4 we have to tell ffi_closure_SYSV how to treat them. We
-+ combine the base type FFI_SYSV_TYPE_SMALL_STRUCT with the size of
-+ the struct less one. We never have a struct with size zero.
-+ See the comment in ffitarget.h about ordering. */
-+ if (rtypenum == FFI_TYPE_STRUCT
-+ && (cif->abi & FFI_SYSV_STRUCT_RET) != 0 && size <= 8)
-+ return FFI_SYSV_TYPE_SMALL_STRUCT - 1 + size;
-+ return rtypenum;
-+}
-+#endif
-Index: libffi/src/powerpc/linux64.S
-===================================================================
---- a/src/libffi/src/powerpc/linux64.S (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/powerpc/linux64.S (.../branches/gcc-4_8-branch)
-@@ -29,18 +29,25 @@
- #include <fficonfig.h>
- #include <ffi.h>
-
--#ifdef __powerpc64__
-+#ifdef POWERPC64
- .hidden ffi_call_LINUX64
- .globl ffi_call_LINUX64
-+# if _CALL_ELF == 2
-+ .text
-+ffi_call_LINUX64:
-+ addis %r2, %r12, .TOC.-ffi_call_LINUX64@ha
-+ addi %r2, %r2, .TOC.-ffi_call_LINUX64@l
-+ .localentry ffi_call_LINUX64, . - ffi_call_LINUX64
-+# else
- .section ".opd","aw"
- .align 3
- ffi_call_LINUX64:
--#ifdef _CALL_LINUX
-+# ifdef _CALL_LINUX
- .quad .L.ffi_call_LINUX64,.TOC.@tocbase,0
- .type ffi_call_LINUX64,@function
- .text
- .L.ffi_call_LINUX64:
--#else
-+# else
- .hidden .ffi_call_LINUX64
- .globl .ffi_call_LINUX64
- .quad .ffi_call_LINUX64,.TOC.@tocbase,0
-@@ -48,7 +55,8 @@
- .type .ffi_call_LINUX64,@function
- .text
- .ffi_call_LINUX64:
--#endif
-+# endif
-+# endif
- .LFB1:
- mflr %r0
- std %r28, -32(%r1)
-@@ -63,26 +71,35 @@
- mr %r31, %r5 /* flags, */
- mr %r30, %r6 /* rvalue, */
- mr %r29, %r7 /* function address. */
-+/* Save toc pointer, not for the ffi_prep_args64 call, but for the later
-+ bctrl function call. */
-+# if _CALL_ELF == 2
-+ std %r2, 24(%r1)
-+# else
- std %r2, 40(%r1)
-+# endif
-
- /* Call ffi_prep_args64. */
- mr %r4, %r1
--#ifdef _CALL_LINUX
-+# if defined _CALL_LINUX || _CALL_ELF == 2
- bl ffi_prep_args64
--#else
-+# else
- bl .ffi_prep_args64
--#endif
-+# endif
-
-- ld %r0, 0(%r29)
-+# if _CALL_ELF == 2
-+ mr %r12, %r29
-+# else
-+ ld %r12, 0(%r29)
- ld %r2, 8(%r29)
- ld %r11, 16(%r29)
--
-+# endif
- /* Now do the call. */
- /* Set up cr1 with bits 4-7 of the flags. */
- mtcrf 0x40, %r31
-
- /* Get the address to call into CTR. */
-- mtctr %r0
-+ mtctr %r12
- /* Load all those argument registers. */
- ld %r3, -32-(8*8)(%r28)
- ld %r4, -32-(7*8)(%r28)
-@@ -117,12 +134,17 @@
-
- /* This must follow the call immediately, the unwinder
- uses this to find out if r2 has been saved or not. */
-+# if _CALL_ELF == 2
-+ ld %r2, 24(%r1)
-+# else
- ld %r2, 40(%r1)
-+# endif
-
- /* Now, deal with the return value. */
- mtcrf 0x01, %r31
-- bt- 30, .Ldone_return_value
-- bt- 29, .Lfp_return_value
-+ bt 31, .Lstruct_return_value
-+ bt 30, .Ldone_return_value
-+ bt 29, .Lfp_return_value
- std %r3, 0(%r30)
- /* Fall through... */
-
-@@ -130,7 +152,7 @@
- /* Restore the registers we used and return. */
- mr %r1, %r28
- ld %r0, 16(%r28)
-- ld %r28, -32(%r1)
-+ ld %r28, -32(%r28)
- mtlr %r0
- ld %r29, -24(%r1)
- ld %r30, -16(%r1)
-@@ -147,14 +169,48 @@
- .Lfloat_return_value:
- stfs %f1, 0(%r30)
- b .Ldone_return_value
-+
-+.Lstruct_return_value:
-+ bf 29, .Lsmall_struct
-+ bf 28, .Lfloat_homog_return_value
-+ stfd %f1, 0(%r30)
-+ stfd %f2, 8(%r30)
-+ stfd %f3, 16(%r30)
-+ stfd %f4, 24(%r30)
-+ stfd %f5, 32(%r30)
-+ stfd %f6, 40(%r30)
-+ stfd %f7, 48(%r30)
-+ stfd %f8, 56(%r30)
-+ b .Ldone_return_value
-+
-+.Lfloat_homog_return_value:
-+ stfs %f1, 0(%r30)
-+ stfs %f2, 4(%r30)
-+ stfs %f3, 8(%r30)
-+ stfs %f4, 12(%r30)
-+ stfs %f5, 16(%r30)
-+ stfs %f6, 20(%r30)
-+ stfs %f7, 24(%r30)
-+ stfs %f8, 28(%r30)
-+ b .Ldone_return_value
-+
-+.Lsmall_struct:
-+ std %r3, 0(%r30)
-+ std %r4, 8(%r30)
-+ b .Ldone_return_value
-+
- .LFE1:
- .long 0
- .byte 0,12,0,1,128,4,0,0
--#ifdef _CALL_LINUX
-+# if _CALL_ELF == 2
-+ .size ffi_call_LINUX64,.-ffi_call_LINUX64
-+# else
-+# ifdef _CALL_LINUX
- .size ffi_call_LINUX64,.-.L.ffi_call_LINUX64
--#else
-+# else
- .size .ffi_call_LINUX64,.-.ffi_call_LINUX64
--#endif
-+# endif
-+# endif
-
- .section .eh_frame,EH_FRAME_FLAGS,@progbits
- .Lframe1:
-@@ -197,8 +253,8 @@
- .uleb128 0x4
- .align 3
- .LEFDE1:
--#endif
-
--#if defined __ELF__ && defined __linux__
-+# if (defined __ELF__ && defined __linux__) || _CALL_ELF == 2
- .section .note.GNU-stack,"",@progbits
-+# endif
- #endif
-Index: libffi/src/powerpc/ffi_linux64.c
-===================================================================
---- a/src/libffi/src/powerpc/ffi_linux64.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/powerpc/ffi_linux64.c (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,942 @@
-+/* -----------------------------------------------------------------------
-+ ffi_linux64.c - Copyright (C) 2013 IBM
-+ Copyright (C) 2011 Anthony Green
-+ Copyright (C) 2011 Kyle Moffett
-+ Copyright (C) 2008 Red Hat, Inc
-+ Copyright (C) 2007, 2008 Free Software Foundation, Inc
-+ Copyright (c) 1998 Geoffrey Keating
-+
-+ PowerPC Foreign Function Interface
-+
-+ Permission is hereby granted, free of charge, to any person obtaining
-+ a copy of this software and associated documentation files (the
-+ ``Software''), to deal in the Software without restriction, including
-+ without limitation the rights to use, copy, modify, merge, publish,
-+ distribute, sublicense, and/or sell copies of the Software, and to
-+ permit persons to whom the Software is furnished to do so, subject to
-+ the following conditions:
-+
-+ The above copyright notice and this permission notice shall be included
-+ in all copies or substantial portions of the Software.
-+
-+ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-+ IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ OTHER DEALINGS IN THE SOFTWARE.
-+ ----------------------------------------------------------------------- */
-+
-+#include "ffi.h"
-+
-+#ifdef POWERPC64
-+#include "ffi_common.h"
-+#include "ffi_powerpc.h"
-+
-+
-+/* About the LINUX64 ABI. */
-+enum {
-+ NUM_GPR_ARG_REGISTERS64 = 8,
-+ NUM_FPR_ARG_REGISTERS64 = 13
-+};
-+enum { ASM_NEEDS_REGISTERS64 = 4 };
-+
-+
-+#if HAVE_LONG_DOUBLE_VARIANT && FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+/* Adjust size of ffi_type_longdouble. */
-+void FFI_HIDDEN
-+ffi_prep_types_linux64 (ffi_abi abi)
-+{
-+ if ((abi & (FFI_LINUX | FFI_LINUX_LONG_DOUBLE_128)) == FFI_LINUX)
-+ {
-+ ffi_type_longdouble.size = 8;
-+ ffi_type_longdouble.alignment = 8;
-+ }
-+ else
-+ {
-+ ffi_type_longdouble.size = 16;
-+ ffi_type_longdouble.alignment = 16;
-+ }
-+}
-+#endif
-+
-+
-+#if _CALL_ELF == 2
-+static unsigned int
-+discover_homogeneous_aggregate (const ffi_type *t, unsigned int *elnum)
-+{
-+ switch (t->type)
-+ {
-+ case FFI_TYPE_FLOAT:
-+ case FFI_TYPE_DOUBLE:
-+ *elnum = 1;
-+ return (int) t->type;
-+
-+ case FFI_TYPE_STRUCT:;
-+ {
-+ unsigned int base_elt = 0, total_elnum = 0;
-+ ffi_type **el = t->elements;
-+ while (*el)
-+ {
-+ unsigned int el_elt, el_elnum = 0;
-+ el_elt = discover_homogeneous_aggregate (*el, &el_elnum);
-+ if (el_elt == 0
-+ || (base_elt && base_elt != el_elt))
-+ return 0;
-+ base_elt = el_elt;
-+ total_elnum += el_elnum;
-+ if (total_elnum > 8)
-+ return 0;
-+ el++;
-+ }
-+ *elnum = total_elnum;
-+ return base_elt;
-+ }
-+
-+ default:
-+ return 0;
-+ }
-+}
-+#endif
-+
-+
-+/* Perform machine dependent cif processing */
-+static ffi_status
-+ffi_prep_cif_linux64_core (ffi_cif *cif)
-+{
-+ ffi_type **ptr;
-+ unsigned bytes;
-+ unsigned i, fparg_count = 0, intarg_count = 0;
-+ unsigned flags = cif->flags;
-+#if _CALL_ELF == 2
-+ unsigned int elt, elnum;
-+#endif
-+
-+#if FFI_TYPE_LONGDOUBLE == FFI_TYPE_DOUBLE
-+ /* If compiled without long double support.. */
-+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)
-+ return FFI_BAD_ABI;
-+#endif
-+
-+ /* The machine-independent calculation of cif->bytes doesn't work
-+ for us. Redo the calculation. */
-+#if _CALL_ELF == 2
-+ /* Space for backchain, CR, LR, TOC and the asm's temp regs. */
-+ bytes = (4 + ASM_NEEDS_REGISTERS64) * sizeof (long);
-+
-+ /* Space for the general registers. */
-+ bytes += NUM_GPR_ARG_REGISTERS64 * sizeof (long);
-+#else
-+ /* Space for backchain, CR, LR, cc/ld doubleword, TOC and the asm's temp
-+ regs. */
-+ bytes = (6 + ASM_NEEDS_REGISTERS64) * sizeof (long);
-+
-+ /* Space for the mandatory parm save area and general registers. */
-+ bytes += 2 * NUM_GPR_ARG_REGISTERS64 * sizeof (long);
-+#endif
-+
-+ /* Return value handling. */
-+ switch (cif->rtype->type)
-+ {
-+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ case FFI_TYPE_LONGDOUBLE:
-+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)
-+ flags |= FLAG_RETURNS_128BITS;
-+ /* Fall through. */
-+#endif
-+ case FFI_TYPE_DOUBLE:
-+ flags |= FLAG_RETURNS_64BITS;
-+ /* Fall through. */
-+ case FFI_TYPE_FLOAT:
-+ flags |= FLAG_RETURNS_FP;
-+ break;
-+
-+ case FFI_TYPE_UINT128:
-+ flags |= FLAG_RETURNS_128BITS;
-+ /* Fall through. */
-+ case FFI_TYPE_UINT64:
-+ case FFI_TYPE_SINT64:
-+ flags |= FLAG_RETURNS_64BITS;
-+ break;
-+
-+ case FFI_TYPE_STRUCT:
-+#if _CALL_ELF == 2
-+ elt = discover_homogeneous_aggregate (cif->rtype, &elnum);
-+ if (elt)
-+ {
-+ if (elt == FFI_TYPE_DOUBLE)
-+ flags |= FLAG_RETURNS_64BITS;
-+ flags |= FLAG_RETURNS_FP | FLAG_RETURNS_SMST;
-+ break;
-+ }
-+ if (cif->rtype->size <= 16)
-+ {
-+ flags |= FLAG_RETURNS_SMST;
-+ break;
-+ }
-+#endif
-+ intarg_count++;
-+ flags |= FLAG_RETVAL_REFERENCE;
-+ /* Fall through. */
-+ case FFI_TYPE_VOID:
-+ flags |= FLAG_RETURNS_NOTHING;
-+ break;
-+
-+ default:
-+ /* Returns 32-bit integer, or similar. Nothing to do here. */
-+ break;
-+ }
-+
-+ for (ptr = cif->arg_types, i = cif->nargs; i > 0; i--, ptr++)
-+ {
-+ unsigned int align;
-+
-+ switch ((*ptr)->type)
-+ {
-+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ case FFI_TYPE_LONGDOUBLE:
-+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)
-+ {
-+ fparg_count++;
-+ intarg_count++;
-+ }
-+ /* Fall through. */
-+#endif
-+ case FFI_TYPE_DOUBLE:
-+ case FFI_TYPE_FLOAT:
-+ fparg_count++;
-+ intarg_count++;
-+ if (fparg_count > NUM_FPR_ARG_REGISTERS64)
-+ flags |= FLAG_ARG_NEEDS_PSAVE;
-+ break;
-+
-+ case FFI_TYPE_STRUCT:
-+ if ((cif->abi & FFI_LINUX_STRUCT_ALIGN) != 0)
-+ {
-+ align = (*ptr)->alignment;
-+ if (align > 16)
-+ align = 16;
-+ align = align / 8;
-+ if (align > 1)
-+ intarg_count = ALIGN (intarg_count, align);
-+ }
-+ intarg_count += ((*ptr)->size + 7) / 8;
-+#if _CALL_ELF == 2
-+ elt = discover_homogeneous_aggregate (*ptr, &elnum);
-+ if (elt)
-+ {
-+ fparg_count += elnum;
-+ if (fparg_count > NUM_FPR_ARG_REGISTERS64)
-+ flags |= FLAG_ARG_NEEDS_PSAVE;
-+ }
-+ else
-+#endif
-+ {
-+ if (intarg_count > NUM_GPR_ARG_REGISTERS64)
-+ flags |= FLAG_ARG_NEEDS_PSAVE;
-+ }
-+ break;
-+
-+ case FFI_TYPE_POINTER:
-+ case FFI_TYPE_UINT64:
-+ case FFI_TYPE_SINT64:
-+ case FFI_TYPE_INT:
-+ case FFI_TYPE_UINT32:
-+ case FFI_TYPE_SINT32:
-+ case FFI_TYPE_UINT16:
-+ case FFI_TYPE_SINT16:
-+ case FFI_TYPE_UINT8:
-+ case FFI_TYPE_SINT8:
-+ /* Everything else is passed as a 8-byte word in a GPR, either
-+ the object itself or a pointer to it. */
-+ intarg_count++;
-+ if (intarg_count > NUM_GPR_ARG_REGISTERS64)
-+ flags |= FLAG_ARG_NEEDS_PSAVE;
-+ break;
-+ default:
-+ FFI_ASSERT (0);
-+ }
-+ }
-+
-+ if (fparg_count != 0)
-+ flags |= FLAG_FP_ARGUMENTS;
-+ if (intarg_count > 4)
-+ flags |= FLAG_4_GPR_ARGUMENTS;
-+
-+ /* Space for the FPR registers, if needed. */
-+ if (fparg_count != 0)
-+ bytes += NUM_FPR_ARG_REGISTERS64 * sizeof (double);
-+
-+ /* Stack space. */
-+#if _CALL_ELF == 2
-+ if ((flags & FLAG_ARG_NEEDS_PSAVE) != 0)
-+ bytes += intarg_count * sizeof (long);
-+#else
-+ if (intarg_count > NUM_GPR_ARG_REGISTERS64)
-+ bytes += (intarg_count - NUM_GPR_ARG_REGISTERS64) * sizeof (long);
-+#endif
-+
-+ /* The stack space allocated needs to be a multiple of 16 bytes. */
-+ bytes = (bytes + 15) & ~0xF;
-+
-+ cif->flags = flags;
-+ cif->bytes = bytes;
-+
-+ return FFI_OK;
-+}
-+
-+ffi_status FFI_HIDDEN
-+ffi_prep_cif_linux64 (ffi_cif *cif)
-+{
-+ if ((cif->abi & FFI_LINUX) != 0)
-+ cif->nfixedargs = cif->nargs;
-+#if _CALL_ELF != 2
-+ else if (cif->abi == FFI_COMPAT_LINUX64)
-+ {
-+ /* This call is from old code. Don't touch cif->nfixedargs
-+ since old code will be using a smaller cif. */
-+ cif->flags |= FLAG_COMPAT;
-+ /* Translate to new abi value. */
-+ cif->abi = FFI_LINUX | FFI_LINUX_LONG_DOUBLE_128;
-+ }
-+#endif
-+ else
-+ return FFI_BAD_ABI;
-+ return ffi_prep_cif_linux64_core (cif);
-+}
-+
-+ffi_status FFI_HIDDEN
-+ffi_prep_cif_linux64_var (ffi_cif *cif,
-+ unsigned int nfixedargs,
-+ unsigned int ntotalargs MAYBE_UNUSED)
-+{
-+ if ((cif->abi & FFI_LINUX) != 0)
-+ cif->nfixedargs = nfixedargs;
-+#if _CALL_ELF != 2
-+ else if (cif->abi == FFI_COMPAT_LINUX64)
-+ {
-+ /* This call is from old code. Don't touch cif->nfixedargs
-+ since old code will be using a smaller cif. */
-+ cif->flags |= FLAG_COMPAT;
-+ /* Translate to new abi value. */
-+ cif->abi = FFI_LINUX | FFI_LINUX_LONG_DOUBLE_128;
-+ }
-+#endif
-+ else
-+ return FFI_BAD_ABI;
-+#if _CALL_ELF == 2
-+ cif->flags |= FLAG_ARG_NEEDS_PSAVE;
-+#endif
-+ return ffi_prep_cif_linux64_core (cif);
-+}
-+
-+
-+/* ffi_prep_args64 is called by the assembly routine once stack space
-+ has been allocated for the function's arguments.
-+
-+ The stack layout we want looks like this:
-+
-+ | Ret addr from ffi_call_LINUX64 8bytes | higher addresses
-+ |--------------------------------------------|
-+ | CR save area 8bytes |
-+ |--------------------------------------------|
-+ | Previous backchain pointer 8 | stack pointer here
-+ |--------------------------------------------|<+ <<< on entry to
-+ | Saved r28-r31 4*8 | | ffi_call_LINUX64
-+ |--------------------------------------------| |
-+ | GPR registers r3-r10 8*8 | |
-+ |--------------------------------------------| |
-+ | FPR registers f1-f13 (optional) 13*8 | |
-+ |--------------------------------------------| |
-+ | Parameter save area | |
-+ |--------------------------------------------| |
-+ | TOC save area 8 | |
-+ |--------------------------------------------| | stack |
-+ | Linker doubleword 8 | | grows |
-+ |--------------------------------------------| | down V
-+ | Compiler doubleword 8 | |
-+ |--------------------------------------------| | lower addresses
-+ | Space for callee's LR 8 | |
-+ |--------------------------------------------| |
-+ | CR save area 8 | |
-+ |--------------------------------------------| | stack pointer here
-+ | Current backchain pointer 8 |-/ during
-+ |--------------------------------------------| <<< ffi_call_LINUX64
-+
-+*/
-+
-+void FFI_HIDDEN
-+ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack)
-+{
-+ const unsigned long bytes = ecif->cif->bytes;
-+ const unsigned long flags = ecif->cif->flags;
-+
-+ typedef union
-+ {
-+ char *c;
-+ unsigned long *ul;
-+ float *f;
-+ double *d;
-+ size_t p;
-+ } valp;
-+
-+ /* 'stacktop' points at the previous backchain pointer. */
-+ valp stacktop;
-+
-+ /* 'next_arg' points at the space for gpr3, and grows upwards as
-+ we use GPR registers, then continues at rest. */
-+ valp gpr_base;
-+ valp gpr_end;
-+ valp rest;
-+ valp next_arg;
-+
-+ /* 'fpr_base' points at the space for fpr3, and grows upwards as
-+ we use FPR registers. */
-+ valp fpr_base;
-+ unsigned int fparg_count;
-+
-+ unsigned int i, words, nargs, nfixedargs;
-+ ffi_type **ptr;
-+ double double_tmp;
-+ union
-+ {
-+ void **v;
-+ char **c;
-+ signed char **sc;
-+ unsigned char **uc;
-+ signed short **ss;
-+ unsigned short **us;
-+ signed int **si;
-+ unsigned int **ui;
-+ unsigned long **ul;
-+ float **f;
-+ double **d;
-+ } p_argv;
-+ unsigned long gprvalue;
-+ unsigned long align;
-+
-+ stacktop.c = (char *) stack + bytes;
-+ gpr_base.ul = stacktop.ul - ASM_NEEDS_REGISTERS64 - NUM_GPR_ARG_REGISTERS64;
-+ gpr_end.ul = gpr_base.ul + NUM_GPR_ARG_REGISTERS64;
-+#if _CALL_ELF == 2
-+ rest.ul = stack + 4 + NUM_GPR_ARG_REGISTERS64;
-+#else
-+ rest.ul = stack + 6 + NUM_GPR_ARG_REGISTERS64;
-+#endif
-+ fpr_base.d = gpr_base.d - NUM_FPR_ARG_REGISTERS64;
-+ fparg_count = 0;
-+ next_arg.ul = gpr_base.ul;
-+
-+ /* Check that everything starts aligned properly. */
-+ FFI_ASSERT (((unsigned long) (char *) stack & 0xF) == 0);
-+ FFI_ASSERT (((unsigned long) stacktop.c & 0xF) == 0);
-+ FFI_ASSERT ((bytes & 0xF) == 0);
-+
-+ /* Deal with return values that are actually pass-by-reference. */
-+ if (flags & FLAG_RETVAL_REFERENCE)
-+ *next_arg.ul++ = (unsigned long) (char *) ecif->rvalue;
-+
-+ /* Now for the arguments. */
-+ p_argv.v = ecif->avalue;
-+ nargs = ecif->cif->nargs;
-+#if _CALL_ELF != 2
-+ nfixedargs = (unsigned) -1;
-+ if ((flags & FLAG_COMPAT) == 0)
-+#endif
-+ nfixedargs = ecif->cif->nfixedargs;
-+ for (ptr = ecif->cif->arg_types, i = 0;
-+ i < nargs;
-+ i++, ptr++, p_argv.v++)
-+ {
-+#if _CALL_ELF == 2
-+ unsigned int elt, elnum;
-+#endif
-+
-+ switch ((*ptr)->type)
-+ {
-+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ case FFI_TYPE_LONGDOUBLE:
-+ if ((ecif->cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)
-+ {
-+ double_tmp = (*p_argv.d)[0];
-+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)
-+ {
-+ *fpr_base.d++ = double_tmp;
-+# if _CALL_ELF != 2
-+ if ((flags & FLAG_COMPAT) != 0)
-+ *next_arg.d = double_tmp;
-+# endif
-+ }
-+ else
-+ *next_arg.d = double_tmp;
-+ if (++next_arg.ul == gpr_end.ul)
-+ next_arg.ul = rest.ul;
-+ fparg_count++;
-+ double_tmp = (*p_argv.d)[1];
-+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)
-+ {
-+ *fpr_base.d++ = double_tmp;
-+# if _CALL_ELF != 2
-+ if ((flags & FLAG_COMPAT) != 0)
-+ *next_arg.d = double_tmp;
-+# endif
-+ }
-+ else
-+ *next_arg.d = double_tmp;
-+ if (++next_arg.ul == gpr_end.ul)
-+ next_arg.ul = rest.ul;
-+ fparg_count++;
-+ FFI_ASSERT (__LDBL_MANT_DIG__ == 106);
-+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-+ break;
-+ }
-+ /* Fall through. */
-+#endif
-+ case FFI_TYPE_DOUBLE:
-+ double_tmp = **p_argv.d;
-+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)
-+ {
-+ *fpr_base.d++ = double_tmp;
-+#if _CALL_ELF != 2
-+ if ((flags & FLAG_COMPAT) != 0)
-+ *next_arg.d = double_tmp;
-+#endif
-+ }
-+ else
-+ *next_arg.d = double_tmp;
-+ if (++next_arg.ul == gpr_end.ul)
-+ next_arg.ul = rest.ul;
-+ fparg_count++;
-+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-+ break;
-+
-+ case FFI_TYPE_FLOAT:
-+ double_tmp = **p_argv.f;
-+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)
-+ {
-+ *fpr_base.d++ = double_tmp;
-+#if _CALL_ELF != 2
-+ if ((flags & FLAG_COMPAT) != 0)
-+ *next_arg.f = (float) double_tmp;
-+#endif
-+ }
-+ else
-+ *next_arg.f = (float) double_tmp;
-+ if (++next_arg.ul == gpr_end.ul)
-+ next_arg.ul = rest.ul;
-+ fparg_count++;
-+ FFI_ASSERT (flags & FLAG_FP_ARGUMENTS);
-+ break;
-+
-+ case FFI_TYPE_STRUCT:
-+ if ((ecif->cif->abi & FFI_LINUX_STRUCT_ALIGN) != 0)
-+ {
-+ align = (*ptr)->alignment;
-+ if (align > 16)
-+ align = 16;
-+ if (align > 1)
-+ next_arg.p = ALIGN (next_arg.p, align);
-+ }
-+#if _CALL_ELF == 2
-+ elt = discover_homogeneous_aggregate (*ptr, &elnum);
-+ if (elt)
-+ {
-+ union {
-+ void *v;
-+ float *f;
-+ double *d;
-+ } arg;
-+
-+ arg.v = *p_argv.v;
-+ if (elt == FFI_TYPE_FLOAT)
-+ {
-+ do
-+ {
-+ double_tmp = *arg.f++;
-+ if (fparg_count < NUM_FPR_ARG_REGISTERS64
-+ && i < nfixedargs)
-+ *fpr_base.d++ = double_tmp;
-+ else
-+ *next_arg.f = (float) double_tmp;
-+ if (++next_arg.f == gpr_end.f)
-+ next_arg.f = rest.f;
-+ fparg_count++;
-+ }
-+ while (--elnum != 0);
-+ if ((next_arg.p & 3) != 0)
-+ {
-+ if (++next_arg.f == gpr_end.f)
-+ next_arg.f = rest.f;
-+ }
-+ }
-+ else
-+ do
-+ {
-+ double_tmp = *arg.d++;
-+ if (fparg_count < NUM_FPR_ARG_REGISTERS64 && i < nfixedargs)
-+ *fpr_base.d++ = double_tmp;
-+ else
-+ *next_arg.d = double_tmp;
-+ if (++next_arg.d == gpr_end.d)
-+ next_arg.d = rest.d;
-+ fparg_count++;
-+ }
-+ while (--elnum != 0);
-+ }
-+ else
-+#endif
-+ {
-+ words = ((*ptr)->size + 7) / 8;
-+ if (next_arg.ul >= gpr_base.ul && next_arg.ul + words > gpr_end.ul)
-+ {
-+ size_t first = gpr_end.c - next_arg.c;
-+ memcpy (next_arg.c, *p_argv.c, first);
-+ memcpy (rest.c, *p_argv.c + first, (*ptr)->size - first);
-+ next_arg.c = rest.c + words * 8 - first;
-+ }
-+ else
-+ {
-+ char *where = next_arg.c;
-+
-+#ifndef __LITTLE_ENDIAN__
-+ /* Structures with size less than eight bytes are passed
-+ left-padded. */
-+ if ((*ptr)->size < 8)
-+ where += 8 - (*ptr)->size;
-+#endif
-+ memcpy (where, *p_argv.c, (*ptr)->size);
-+ next_arg.ul += words;
-+ if (next_arg.ul == gpr_end.ul)
-+ next_arg.ul = rest.ul;
-+ }
-+ }
-+ break;
-+
-+ case FFI_TYPE_UINT8:
-+ gprvalue = **p_argv.uc;
-+ goto putgpr;
-+ case FFI_TYPE_SINT8:
-+ gprvalue = **p_argv.sc;
-+ goto putgpr;
-+ case FFI_TYPE_UINT16:
-+ gprvalue = **p_argv.us;
-+ goto putgpr;
-+ case FFI_TYPE_SINT16:
-+ gprvalue = **p_argv.ss;
-+ goto putgpr;
-+ case FFI_TYPE_UINT32:
-+ gprvalue = **p_argv.ui;
-+ goto putgpr;
-+ case FFI_TYPE_INT:
-+ case FFI_TYPE_SINT32:
-+ gprvalue = **p_argv.si;
-+ goto putgpr;
-+
-+ case FFI_TYPE_UINT64:
-+ case FFI_TYPE_SINT64:
-+ case FFI_TYPE_POINTER:
-+ gprvalue = **p_argv.ul;
-+ putgpr:
-+ *next_arg.ul++ = gprvalue;
-+ if (next_arg.ul == gpr_end.ul)
-+ next_arg.ul = rest.ul;
-+ break;
-+ }
-+ }
-+
-+ FFI_ASSERT (flags & FLAG_4_GPR_ARGUMENTS
-+ || (next_arg.ul >= gpr_base.ul
-+ && next_arg.ul <= gpr_base.ul + 4));
-+}
-+
-+
-+#if _CALL_ELF == 2
-+#define MIN_CACHE_LINE_SIZE 8
-+
-+static void
-+flush_icache (char *wraddr, char *xaddr, int size)
-+{
-+ int i;
-+ for (i = 0; i < size; i += MIN_CACHE_LINE_SIZE)
-+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;"
-+ : : "r" (xaddr + i), "r" (wraddr + i) : "memory");
-+ __asm__ volatile ("icbi 0,%0;" "dcbf 0,%1;" "sync;" "isync;"
-+ : : "r"(xaddr + size - 1), "r"(wraddr + size - 1)
-+ : "memory");
-+}
-+#endif
-+
-+ffi_status
-+ffi_prep_closure_loc_linux64 (ffi_closure *closure,
-+ ffi_cif *cif,
-+ void (*fun) (ffi_cif *, void *, void **, void *),
-+ void *user_data,
-+ void *codeloc)
-+{
-+#if _CALL_ELF == 2
-+ unsigned int *tramp = (unsigned int *) &closure->tramp[0];
-+
-+ if (cif->abi < FFI_LINUX || cif->abi >= FFI_LAST_ABI)
-+ return FFI_BAD_ABI;
-+
-+ tramp[0] = 0xe96c0018; /* 0: ld 11,2f-0b(12) */
-+ tramp[1] = 0xe98c0010; /* ld 12,1f-0b(12) */
-+ tramp[2] = 0x7d8903a6; /* mtctr 12 */
-+ tramp[3] = 0x4e800420; /* bctr */
-+ /* 1: .quad function_addr */
-+ /* 2: .quad context */
-+ *(void **) &tramp[4] = (void *) ffi_closure_LINUX64;
-+ *(void **) &tramp[6] = codeloc;
-+ flush_icache ((char *)tramp, (char *)codeloc, FFI_TRAMPOLINE_SIZE);
-+#else
-+ void **tramp = (void **) &closure->tramp[0];
-+
-+ if (cif->abi < FFI_LINUX || cif->abi >= FFI_LAST_ABI)
-+ return FFI_BAD_ABI;
-+
-+ /* Copy function address and TOC from ffi_closure_LINUX64. */
-+ memcpy (tramp, (char *) ffi_closure_LINUX64, 16);
-+ tramp[2] = codeloc;
-+#endif
-+
-+ closure->cif = cif;
-+ closure->fun = fun;
-+ closure->user_data = user_data;
-+
-+ return FFI_OK;
-+}
-+
-+
-+int FFI_HIDDEN
-+ffi_closure_helper_LINUX64 (ffi_closure *closure, void *rvalue,
-+ unsigned long *pst, ffi_dblfl *pfr)
-+{
-+ /* rvalue is the pointer to space for return value in closure assembly */
-+ /* pst is the pointer to parameter save area
-+ (r3-r10 are stored into its first 8 slots by ffi_closure_LINUX64) */
-+ /* pfr is the pointer to where f1-f13 are stored in ffi_closure_LINUX64 */
-+
-+ void **avalue;
-+ ffi_type **arg_types;
-+ unsigned long i, avn, nfixedargs;
-+ ffi_cif *cif;
-+ ffi_dblfl *end_pfr = pfr + NUM_FPR_ARG_REGISTERS64;
-+ unsigned long align;
-+
-+ cif = closure->cif;
-+ avalue = alloca (cif->nargs * sizeof (void *));
-+
-+ /* Copy the caller's structure return value address so that the
-+ closure returns the data directly to the caller. */
-+ if (cif->rtype->type == FFI_TYPE_STRUCT
-+ && (cif->flags & FLAG_RETURNS_SMST) == 0)
-+ {
-+ rvalue = (void *) *pst;
-+ pst++;
-+ }
-+
-+ i = 0;
-+ avn = cif->nargs;
-+#if _CALL_ELF != 2
-+ nfixedargs = (unsigned) -1;
-+ if ((cif->flags & FLAG_COMPAT) == 0)
-+#endif
-+ nfixedargs = cif->nfixedargs;
-+ arg_types = cif->arg_types;
-+
-+ /* Grab the addresses of the arguments from the stack frame. */
-+ while (i < avn)
-+ {
-+ unsigned int elt, elnum;
-+
-+ switch (arg_types[i]->type)
-+ {
-+ case FFI_TYPE_SINT8:
-+ case FFI_TYPE_UINT8:
-+#ifndef __LITTLE_ENDIAN__
-+ avalue[i] = (char *) pst + 7;
-+ pst++;
-+ break;
-+#endif
-+
-+ case FFI_TYPE_SINT16:
-+ case FFI_TYPE_UINT16:
-+#ifndef __LITTLE_ENDIAN__
-+ avalue[i] = (char *) pst + 6;
-+ pst++;
-+ break;
-+#endif
-+
-+ case FFI_TYPE_SINT32:
-+ case FFI_TYPE_UINT32:
-+#ifndef __LITTLE_ENDIAN__
-+ avalue[i] = (char *) pst + 4;
-+ pst++;
-+ break;
-+#endif
-+
-+ case FFI_TYPE_SINT64:
-+ case FFI_TYPE_UINT64:
-+ case FFI_TYPE_POINTER:
-+ avalue[i] = pst;
-+ pst++;
-+ break;
-+
-+ case FFI_TYPE_STRUCT:
-+ if ((cif->abi & FFI_LINUX_STRUCT_ALIGN) != 0)
-+ {
-+ align = arg_types[i]->alignment;
-+ if (align > 16)
-+ align = 16;
-+ if (align > 1)
-+ pst = (unsigned long *) ALIGN ((size_t) pst, align);
-+ }
-+ elt = 0;
-+#if _CALL_ELF == 2
-+ elt = discover_homogeneous_aggregate (arg_types[i], &elnum);
-+#endif
-+ if (elt)
-+ {
-+ union {
-+ void *v;
-+ unsigned long *ul;
-+ float *f;
-+ double *d;
-+ size_t p;
-+ } to, from;
-+
-+ /* Repackage the aggregate from its parts. The
-+ aggregate size is not greater than the space taken by
-+ the registers so store back to the register/parameter
-+ save arrays. */
-+ if (pfr + elnum <= end_pfr)
-+ to.v = pfr;
-+ else
-+ to.v = pst;
-+
-+ avalue[i] = to.v;
-+ from.ul = pst;
-+ if (elt == FFI_TYPE_FLOAT)
-+ {
-+ do
-+ {
-+ if (pfr < end_pfr && i < nfixedargs)
-+ {
-+ *to.f = (float) pfr->d;
-+ pfr++;
-+ }
-+ else
-+ *to.f = *from.f;
-+ to.f++;
-+ from.f++;
-+ }
-+ while (--elnum != 0);
-+ }
-+ else
-+ {
-+ do
-+ {
-+ if (pfr < end_pfr && i < nfixedargs)
-+ {
-+ *to.d = pfr->d;
-+ pfr++;
-+ }
-+ else
-+ *to.d = *from.d;
-+ to.d++;
-+ from.d++;
-+ }
-+ while (--elnum != 0);
-+ }
-+ }
-+ else
-+ {
-+#ifndef __LITTLE_ENDIAN__
-+ /* Structures with size less than eight bytes are passed
-+ left-padded. */
-+ if (arg_types[i]->size < 8)
-+ avalue[i] = (char *) pst + 8 - arg_types[i]->size;
-+ else
-+#endif
-+ avalue[i] = pst;
-+ }
-+ pst += (arg_types[i]->size + 7) / 8;
-+ break;
-+
-+#if FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+ case FFI_TYPE_LONGDOUBLE:
-+ if ((cif->abi & FFI_LINUX_LONG_DOUBLE_128) != 0)
-+ {
-+ if (pfr + 1 < end_pfr && i + 1 < nfixedargs)
-+ {
-+ avalue[i] = pfr;
-+ pfr += 2;
-+ }
-+ else
-+ {
-+ if (pfr < end_pfr && i < nfixedargs)
-+ {
-+ /* Passed partly in f13 and partly on the stack.
-+ Move it all to the stack. */
-+ *pst = *(unsigned long *) pfr;
-+ pfr++;
-+ }
-+ avalue[i] = pst;
-+ }
-+ pst += 2;
-+ break;
-+ }
-+ /* Fall through. */
-+#endif
-+ case FFI_TYPE_DOUBLE:
-+ /* On the outgoing stack all values are aligned to 8 */
-+ /* there are 13 64bit floating point registers */
-+
-+ if (pfr < end_pfr && i < nfixedargs)
-+ {
-+ avalue[i] = pfr;
-+ pfr++;
-+ }
-+ else
-+ avalue[i] = pst;
-+ pst++;
-+ break;
-+
-+ case FFI_TYPE_FLOAT:
-+ if (pfr < end_pfr && i < nfixedargs)
-+ {
-+ /* Float values are stored as doubles in the
-+ ffi_closure_LINUX64 code. Fix them here. */
-+ pfr->f = (float) pfr->d;
-+ avalue[i] = pfr;
-+ pfr++;
-+ }
-+ else
-+ avalue[i] = pst;
-+ pst++;
-+ break;
-+
-+ default:
-+ FFI_ASSERT (0);
-+ }
-+
-+ i++;
-+ }
-+
-+
-+ (closure->fun) (cif, rvalue, avalue, closure->user_data);
-+
-+ /* Tell ffi_closure_LINUX64 how to perform return type promotions. */
-+ if ((cif->flags & FLAG_RETURNS_SMST) != 0)
-+ {
-+ if ((cif->flags & FLAG_RETURNS_FP) == 0)
-+ return FFI_V2_TYPE_SMALL_STRUCT + cif->rtype->size - 1;
-+ else if ((cif->flags & FLAG_RETURNS_64BITS) != 0)
-+ return FFI_V2_TYPE_DOUBLE_HOMOG;
-+ else
-+ return FFI_V2_TYPE_FLOAT_HOMOG;
-+ }
-+ return cif->rtype->type;
-+}
-+#endif
-Index: libffi/src/types.c
-===================================================================
---- a/src/libffi/src/types.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/types.c (.../branches/gcc-4_8-branch)
-@@ -44,6 +44,17 @@
- id, NULL \
- }
-
-+#define FFI_NONCONST_TYPEDEF(name, type, id) \
-+struct struct_align_##name { \
-+ char c; \
-+ type x; \
-+}; \
-+ffi_type ffi_type_##name = { \
-+ sizeof(type), \
-+ offsetof(struct struct_align_##name, x), \
-+ id, NULL \
-+}
-+
- /* Size and alignment are fake here. They must not be 0. */
- const ffi_type ffi_type_void = {
- 1, 1, FFI_TYPE_VOID, NULL
-@@ -73,5 +84,9 @@
- # endif
- const ffi_type ffi_type_longdouble = { 16, 16, 4, NULL };
- #elif FFI_TYPE_LONGDOUBLE != FFI_TYPE_DOUBLE
-+# if HAVE_LONG_DOUBLE_VARIANT
-+FFI_NONCONST_TYPEDEF(longdouble, long double, FFI_TYPE_LONGDOUBLE);
-+# else
- FFI_TYPEDEF(longdouble, long double, FFI_TYPE_LONGDOUBLE);
-+# endif
- #endif
-Index: libffi/src/prep_cif.c
-===================================================================
---- a/src/libffi/src/prep_cif.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/src/prep_cif.c (.../branches/gcc-4_8-branch)
-@@ -126,6 +126,10 @@
-
- cif->flags = 0;
-
-+#if HAVE_LONG_DOUBLE_VARIANT
-+ ffi_prep_types (abi);
-+#endif
-+
- /* Initialize the return type if necessary */
- if ((cif->rtype->size == 0) && (initialize_aggregate(cif->rtype) != FFI_OK))
- return FFI_BAD_TYPEDEF;
-Index: libffi/ChangeLog
-===================================================================
---- a/src/libffi/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,39 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport mainline r205844.
-+ 2013-11-18 Alan Modra <amodra@gmail.com>
-+ * src/powerpc/ffitarget.h: Import from upstream.
-+ * src/powerpc/ffi_powerpc.h: Likewise.
-+ * src/powerpc/ffi.c: Likewise.
-+ * src/powerpc/ffi_sysv.c: Likewise.
-+ * src/powerpc/ffi_linux64.c: Likewise.
-+ * src/powerpc/sysv.S: Likewise.
-+ * src/powerpc/ppc_closure.S: Likewise.
-+ * src/powerpc/linux64.S: Likewise.
-+ * src/powerpc/linux64_closure.S: Likewise.
-+ * src/types.c: Likewise.
-+ * Makefile.am (EXTRA_DIST): Add new src/powerpc files.
-+ (nodist_libffi_la_SOURCES <POWERPC, POWERPC_FREEBSD>): Likewise.
-+ * configure.ac (HAVE_LONG_DOUBLE_VARIANT): Define for powerpc.
-+ * include/ffi.h.in (ffi_prep_types): Declare.
-+ * src/prep_cif.c (ffi_prep_cif_core): Call ffi_prep_types.
-+ * configure: Regenerate.
-+ * fficonfig.h.in: Regenerate.
-+ * Makefile.in: Regenerate.
-+ * man/Makefile.in: Regenerate.
-+ * include/Makefile.in: Regenerate.
-+ * testsuite/Makefile.in: Regenerate.
-+
-+ * src/powerpc/ppc_closure.S: Don't bl .Luint128.
-+
-+ * src/powerpc/ffitarget.h: Import from upstream.
-+ * src/powerpc/ffi.c: Likewise.
-+ * src/powerpc/linux64.S: Likewise.
-+ * src/powerpc/linux64_closure.S: Likewise.
-+ * doc/libffi.texi: Likewise.
-+ * testsuite/libffi.call/cls_double_va.c: Likewise.
-+ * testsuite/libffi.call/cls_longdouble_va.c: Likewise.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libffi/testsuite/Makefile.in
-===================================================================
---- a/src/libffi/testsuite/Makefile.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/testsuite/Makefile.in (.../branches/gcc-4_8-branch)
-@@ -88,6 +88,7 @@
- FGREP = @FGREP@
- GREP = @GREP@
- HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@
-+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@
- INSTALL = @INSTALL@
- INSTALL_DATA = @INSTALL_DATA@
- INSTALL_PROGRAM = @INSTALL_PROGRAM@
-Index: libffi/testsuite/libffi.call/cls_double_va.c
-===================================================================
---- a/src/libffi/testsuite/libffi.call/cls_double_va.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/testsuite/libffi.call/cls_double_va.c (.../branches/gcc-4_8-branch)
-@@ -38,7 +38,7 @@
-
- /* This printf call is variadic */
- CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, &ffi_type_sint,
-- arg_types) == FFI_OK);
-+ arg_types) == FFI_OK);
-
- args[0] = &format;
- args[1] = &doubleArg;
-@@ -45,19 +45,17 @@
- args[2] = NULL;
-
- ffi_call(&cif, FFI_FN(printf), &res, args);
-- // { dg-output "7.0" }
-+ /* { dg-output "7.0" } */
- printf("res: %d\n", (int) res);
-- // { dg-output "\nres: 4" }
-+ /* { dg-output "\nres: 4" } */
-
-- /* The call to cls_double_va_fn is static, so have to use a normal prep_cif */
-- CHECK(ffi_prep_cif(&cif, FFI_DEFAULT_ABI, 2, &ffi_type_sint, arg_types) == FFI_OK);
-+ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_double_va_fn, NULL,
-+ code) == FFI_OK);
-
-- CHECK(ffi_prep_closure_loc(pcl, &cif, cls_double_va_fn, NULL, code) == FFI_OK);
--
-- res = ((int(*)(char*, double))(code))(format, doubleArg);
-- // { dg-output "\n7.0" }
-+ res = ((int(*)(char*, ...))(code))(format, doubleArg);
-+ /* { dg-output "\n7.0" } */
- printf("res: %d\n", (int) res);
-- // { dg-output "\nres: 4" }
-+ /* { dg-output "\nres: 4" } */
-
- exit(0);
- }
-Index: libffi/testsuite/libffi.call/cls_longdouble_va.c
-===================================================================
---- a/src/libffi/testsuite/libffi.call/cls_longdouble_va.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/testsuite/libffi.call/cls_longdouble_va.c (.../branches/gcc-4_8-branch)
-@@ -38,7 +38,7 @@
-
- /* This printf call is variadic */
- CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, &ffi_type_sint,
-- arg_types) == FFI_OK);
-+ arg_types) == FFI_OK);
-
- args[0] = &format;
- args[1] = &ldArg;
-@@ -45,20 +45,17 @@
- args[2] = NULL;
-
- ffi_call(&cif, FFI_FN(printf), &res, args);
-- // { dg-output "7.0" }
-+ /* { dg-output "7.0" } */
- printf("res: %d\n", (int) res);
-- // { dg-output "\nres: 4" }
-+ /* { dg-output "\nres: 4" } */
-
-- /* The call to cls_longdouble_va_fn is static, so have to use a normal prep_cif */
-- CHECK(ffi_prep_cif(&cif, FFI_DEFAULT_ABI, 2, &ffi_type_sint,
-- arg_types) == FFI_OK);
-+ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_longdouble_va_fn, NULL,
-+ code) == FFI_OK);
-
-- CHECK(ffi_prep_closure_loc(pcl, &cif, cls_longdouble_va_fn, NULL, code) == FFI_OK);
--
-- res = ((int(*)(char*, long double))(code))(format, ldArg);
-- // { dg-output "\n7.0" }
-+ res = ((int(*)(char*, ...))(code))(format, ldArg);
-+ /* { dg-output "\n7.0" } */
- printf("res: %d\n", (int) res);
-- // { dg-output "\nres: 4" }
-+ /* { dg-output "\nres: 4" } */
-
- exit(0);
- }
-Index: libffi/configure.ac
-===================================================================
---- a/src/libffi/configure.ac (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/configure.ac (.../branches/gcc-4_8-branch)
-@@ -65,6 +65,7 @@
- AM_CONDITIONAL(TESTSUBDIR, test -d $srcdir/testsuite)
-
- TARGETDIR="unknown"
-+HAVE_LONG_DOUBLE_VARIANT=0
- case "$host" in
- aarch64*-*-*)
- TARGET=AARCH64; TARGETDIR=aarch64
-@@ -162,6 +163,7 @@
-
- powerpc*-*-linux* | powerpc-*-sysv*)
- TARGET=POWERPC; TARGETDIR=powerpc
-+ HAVE_LONG_DOUBLE_VARIANT=1
- ;;
- powerpc-*-amigaos*)
- TARGET=POWERPC; TARGETDIR=powerpc
-@@ -177,6 +179,7 @@
- ;;
- powerpc-*-freebsd* | powerpc-*-openbsd*)
- TARGET=POWERPC_FREEBSD; TARGETDIR=powerpc
-+ HAVE_LONG_DOUBLE_VARIANT=1
- ;;
- powerpc64-*-freebsd*)
- TARGET=POWERPC; TARGETDIR=powerpc
-@@ -273,14 +276,20 @@
- # Also AC_SUBST this variable for ffi.h.
- if test -z "$HAVE_LONG_DOUBLE"; then
- HAVE_LONG_DOUBLE=0
-- if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then
-- if test $ac_cv_sizeof_long_double != 0; then
-+ if test $ac_cv_sizeof_long_double != 0; then
-+ if test $HAVE_LONG_DOUBLE_VARIANT != 0; then
-+ AC_DEFINE(HAVE_LONG_DOUBLE_VARIANT, 1, [Define if you support more than one size of the long double type])
- HAVE_LONG_DOUBLE=1
-- AC_DEFINE(HAVE_LONG_DOUBLE, 1, [Define if you have the long double type and it is bigger than a double])
-+ else
-+ if test $ac_cv_sizeof_double != $ac_cv_sizeof_long_double; then
-+ HAVE_LONG_DOUBLE=1
-+ AC_DEFINE(HAVE_LONG_DOUBLE, 1, [Define if you have the long double type and it is bigger than a double])
-+ fi
- fi
- fi
- fi
- AC_SUBST(HAVE_LONG_DOUBLE)
-+AC_SUBST(HAVE_LONG_DOUBLE_VARIANT)
-
- AC_C_BIGENDIAN
-
-Index: libffi/Makefile.am
-===================================================================
---- a/src/libffi/Makefile.am (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/Makefile.am (.../branches/gcc-4_8-branch)
-@@ -15,10 +15,12 @@
- src/ia64/unix.S src/mips/ffi.c src/mips/n32.S src/mips/o32.S \
- src/mips/ffitarget.h src/m32r/ffi.c src/m32r/sysv.S \
- src/m32r/ffitarget.h src/m68k/ffi.c src/m68k/sysv.S \
-- src/m68k/ffitarget.h src/powerpc/ffi.c src/powerpc/sysv.S \
-- src/powerpc/linux64.S src/powerpc/linux64_closure.S \
-- src/powerpc/ppc_closure.S src/powerpc/asm.h \
-- src/powerpc/aix.S src/powerpc/darwin.S \
-+ src/m68k/ffitarget.h \
-+ src/powerpc/ffi.c src/powerpc/ffi_powerpc.h \
-+ src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c \
-+ src/powerpc/sysv.S src/powerpc/linux64.S \
-+ src/powerpc/linux64_closure.S src/powerpc/ppc_closure.S \
-+ src/powerpc/asm.h src/powerpc/aix.S src/powerpc/darwin.S \
- src/powerpc/aix_closure.S src/powerpc/darwin_closure.S \
- src/powerpc/ffi_darwin.c src/powerpc/ffitarget.h \
- src/s390/ffi.c src/s390/sysv.S src/s390/ffitarget.h \
-@@ -179,7 +181,7 @@
- nodist_libffi_la_SOURCES += src/m68k/ffi.c src/m68k/sysv.S
- endif
- if POWERPC
--nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S
-+nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/ffi_linux64.c src/powerpc/sysv.S src/powerpc/ppc_closure.S src/powerpc/linux64.S src/powerpc/linux64_closure.S
- endif
- if POWERPC_AIX
- nodist_libffi_la_SOURCES += src/powerpc/ffi_darwin.c src/powerpc/aix.S src/powerpc/aix_closure.S
-@@ -188,7 +190,7 @@
- nodist_libffi_la_SOURCES += src/powerpc/ffi_darwin.c src/powerpc/darwin.S src/powerpc/darwin_closure.S
- endif
- if POWERPC_FREEBSD
--nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S
-+nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/ffi_sysv.c src/powerpc/sysv.S src/powerpc/ppc_closure.S
- endif
- if AARCH64
- nodist_libffi_la_SOURCES += src/aarch64/sysv.S src/aarch64/ffi.c
-Index: libffi/man/Makefile.in
-===================================================================
---- a/src/libffi/man/Makefile.in (.../tags/gcc_4_8_2_release)
-+++ b/src/libffi/man/Makefile.in (.../branches/gcc-4_8-branch)
-@@ -111,6 +111,7 @@
- FGREP = @FGREP@
- GREP = @GREP@
- HAVE_LONG_DOUBLE = @HAVE_LONG_DOUBLE@
-+HAVE_LONG_DOUBLE_VARIANT = @HAVE_LONG_DOUBLE_VARIANT@
- INSTALL = @INSTALL@
- INSTALL_DATA = @INSTALL_DATA@
- INSTALL_PROGRAM = @INSTALL_PROGRAM@
-Index: libssp/configure
-===================================================================
---- a/src/libssp/configure (.../tags/gcc_4_8_2_release)
-+++ b/src/libssp/configure (.../branches/gcc-4_8-branch)
-@@ -6385,7 +6385,7 @@
- rm -rf conftest*
- ;;
-
--x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
-+x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \
- s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
- # Find out which ABI we are using.
- echo 'int i;' > conftest.$ac_ext
-@@ -6410,7 +6410,10 @@
- ;;
- esac
- ;;
-- ppc64-*linux*|powerpc64-*linux*)
-+ powerpc64le-*linux*)
-+ LD="${LD-ld} -m elf32lppclinux"
-+ ;;
-+ powerpc64-*linux*)
- LD="${LD-ld} -m elf32ppclinux"
- ;;
- s390x-*linux*)
-@@ -6429,7 +6432,10 @@
- x86_64-*linux*)
- LD="${LD-ld} -m elf_x86_64"
- ;;
-- ppc*-*linux*|powerpc*-*linux*)
-+ powerpcle-*linux*)
-+ LD="${LD-ld} -m elf64lppc"
-+ ;;
-+ powerpc-*linux*)
- LD="${LD-ld} -m elf64ppc"
- ;;
- s390*-*linux*|s390*-*tpf*)
-@@ -10658,7 +10664,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10661 "configure"
-+#line 10667 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-@@ -10764,7 +10770,7 @@
- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
- lt_status=$lt_dlunknown
- cat > conftest.$ac_ext <<_LT_EOF
--#line 10767 "configure"
-+#line 10773 "configure"
- #include "confdefs.h"
-
- #if HAVE_DLFCN_H
-Index: libssp/ChangeLog
-===================================================================
---- a/src/libssp/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libssp/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,10 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
-+
-+ * configure: Regenerate.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libcpp/macro.c
-===================================================================
---- a/src/libcpp/macro.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libcpp/macro.c (.../branches/gcc-4_8-branch)
-@@ -1108,21 +1108,22 @@
-
- if (macro->paramc == 0)
- {
-+ unsigned tokens_count = macro_real_token_count (macro);
- if (CPP_OPTION (pfile, track_macro_expansion))
- {
-- unsigned int i, count = macro->count;
-+ unsigned int i;
- const cpp_token *src = macro->exp.tokens;
- const struct line_map *map;
- source_location *virt_locs = NULL;
-- _cpp_buff *macro_tokens =
-- tokens_buff_new (pfile, count, &virt_locs);
-+ _cpp_buff *macro_tokens
-+ = tokens_buff_new (pfile, tokens_count, &virt_locs);
-
- /* Create a macro map to record the locations of the
- tokens that are involved in the expansion. LOCATION
- is the location of the macro expansion point. */
-- map = linemap_enter_macro (pfile->line_table,
-- node, location, count);
-- for (i = 0; i < count; ++i)
-+ map = linemap_enter_macro (pfile->line_table,
-+ node, location, tokens_count);
-+ for (i = 0; i < tokens_count; ++i)
- {
- tokens_buff_add_token (macro_tokens, virt_locs,
- src, src->src_loc,
-@@ -1134,16 +1135,12 @@
- virt_locs,
- (const cpp_token **)
- macro_tokens->base,
-- count);
-- num_macro_tokens_counter += count;
-+ tokens_count);
- }
- else
-- {
-- unsigned tokens_count = macro_real_token_count (macro);
-- _cpp_push_token_context (pfile, node, macro->exp.tokens,
-- tokens_count);
-- num_macro_tokens_counter += tokens_count;
-- }
-+ _cpp_push_token_context (pfile, node, macro->exp.tokens,
-+ tokens_count);
-+ num_macro_tokens_counter += tokens_count;
- }
-
- if (pragma_buff)
-Index: libcpp/line-map.c
-===================================================================
---- a/src/libcpp/line-map.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libcpp/line-map.c (.../branches/gcc-4_8-branch)
-@@ -1024,6 +1024,11 @@
- bool pre_virtual_p, post_virtual_p;
- source_location l0 = pre, l1 = post;
-
-+ if (IS_ADHOC_LOC (l0))
-+ l0 = set->location_adhoc_data_map.data[l0 & MAX_SOURCE_LOCATION].locus;
-+ if (IS_ADHOC_LOC (l1))
-+ l1 = set->location_adhoc_data_map.data[l1 & MAX_SOURCE_LOCATION].locus;
-+
- if (l0 == l1)
- return 0;
-
-Index: libcpp/files.c
-===================================================================
---- a/src/libcpp/files.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libcpp/files.c (.../branches/gcc-4_8-branch)
-@@ -983,6 +983,7 @@
- {
- struct cpp_dir *dir;
- _cpp_file *file;
-+ bool stacked;
-
- dir = search_path_head (pfile, fname, angle_brackets, type);
- if (!dir)
-@@ -993,19 +994,26 @@
- if (type == IT_DEFAULT && file == NULL)
- return false;
-
-- /* Compensate for the increment in linemap_add that occurs in
-- _cpp_stack_file. In the case of a normal #include, we're
-- currently at the start of the line *following* the #include. A
-- separate source_location for this location makes no sense (until
-- we do the LC_LEAVE), and complicates LAST_SOURCE_LINE_LOCATION.
-- This does not apply if we found a PCH file (in which case
-- linemap_add is not called) or we were included from the
-- command-line. */
-+ /* Compensate for the increment in linemap_add that occurs if
-+ _cpp_stack_file actually stacks the file. In the case of a
-+ normal #include, we're currently at the start of the line
-+ *following* the #include. A separate source_location for this
-+ location makes no sense (until we do the LC_LEAVE), and
-+ complicates LAST_SOURCE_LINE_LOCATION. This does not apply if we
-+ found a PCH file (in which case linemap_add is not called) or we
-+ were included from the command-line. */
- if (file->pchname == NULL && file->err_no == 0
- && type != IT_CMDLINE && type != IT_DEFAULT)
- pfile->line_table->highest_location--;
-
-- return _cpp_stack_file (pfile, file, type == IT_IMPORT);
-+ stacked = _cpp_stack_file (pfile, file, type == IT_IMPORT);
-+
-+ if (!stacked)
-+ /* _cpp_stack_file didn't stack the file, so let's rollback the
-+ compensation dance we performed above. */
-+ pfile->line_table->highest_location++;
-+
-+ return stacked;
- }
-
- /* Could not open FILE. The complication is dependency output. */
-Index: libcpp/ChangeLog
-===================================================================
---- a/src/libcpp/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libcpp/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,36 @@
-+2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ Backport from mainline
-+ 2013-11-18 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
-+
-+ * lex.c (search_line_fast): Correct for little endian.
-+
-+2014-03-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ Backport from mainline
-+ 2014-02-19 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR preprocessor/58844
-+ * macro.c (enter_macro_context): Only push
-+ macro_real_token_count (macro) tokens rather than
-+ macro->count tokens, regardless of
-+ CPP_OPTION (pfile, track-macro-expansion).
-+
-+ 2014-02-07 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR preprocessor/56824
-+ * line-map.c (linemap_compare_locations): Look through adhoc locations
-+ for both l0 and l1.
-+
-+2014-03-06 Jakub Jelinek <jakub@redhat.com>
-+
-+ PR preprocessor/60400
-+ Backport from mainline
-+ 2013-06-24 Dehao Chen <dehao@google.com>
-+
-+ * files.c (_cpp_stack_include): Fix the highest_location when header
-+ file is guarded by #ifndef and is included twice.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libcpp/lex.c
-===================================================================
---- a/src/libcpp/lex.c (.../tags/gcc_4_8_2_release)
-+++ b/src/libcpp/lex.c (.../branches/gcc-4_8-branch)
-@@ -559,8 +559,13 @@
- beginning with all ones and shifting in zeros according to the
- mis-alignment. The LVSR instruction pulls the exact shift we
- want from the address. */
-+#ifdef __BIG_ENDIAN__
- mask = __builtin_vec_lvsr(0, s);
- mask = __builtin_vec_perm(zero, ones, mask);
-+#else
-+ mask = __builtin_vec_lvsl(0, s);
-+ mask = __builtin_vec_perm(ones, zero, mask);
-+#endif
- data &= mask;
-
- /* While altivec loads mask addresses, we still need to align S so
-@@ -624,7 +629,11 @@
- /* L now contains 0xff in bytes for which we matched one of the
- relevant characters. We can find the byte index by finding
- its bit index and dividing by 8. */
-+#ifdef __BIG_ENDIAN__
- l = __builtin_clzl(l) >> 3;
-+#else
-+ l = __builtin_ctzl(l) >> 3;
-+#endif
- return s + l;
-
- #undef N
-Index: libcpp/po/pt_BR.po
-===================================================================
---- a/src/libcpp/po/pt_BR.po (.../tags/gcc_4_8_2_release)
-+++ b/src/libcpp/po/pt_BR.po (.../branches/gcc-4_8-branch)
-@@ -0,0 +1,908 @@
-+# Brazilian Portuguese translation for cpplib
-+# Copyright (C) 2013 Free Software Foundation, Inc.
-+# This file is distributed under the same license as the gcc package.
-+# Rafael Ferreira <rafael.f.f1@gmail.com>, 2013.
-+#
-+msgid ""
-+msgstr ""
-+"Project-Id-Version: cpplib 4.8.0\n"
-+"Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"
-+"POT-Creation-Date: 2013-03-15 17:42+0000\n"
-+"PO-Revision-Date: 2013-12-18 03:12-0300\n"
-+"Last-Translator: Rafael Ferreira <rafael.f.f1@gmail.com>\n"
-+"Language-Team: Brazilian Portuguese <ldpbr-translation@lists.sourceforge.net>\n"
-+"Language: pt_BR\n"
-+"MIME-Version: 1.0\n"
-+"Content-Type: text/plain; charset=UTF-8\n"
-+"Content-Transfer-Encoding: 8bit\n"
-+"X-Generator: Poedit 1.5.7\n"
-+"Plural-Forms: nplurals=2; plural=(n > 1);\n"
-+
-+#: charset.c:673
-+#, c-format
-+msgid "conversion from %s to %s not supported by iconv"
-+msgstr "sem suporte a conversão de %s para %s por iconv"
-+
-+#: charset.c:676
-+msgid "iconv_open"
-+msgstr "iconv_open"
-+
-+#: charset.c:684
-+#, c-format
-+msgid "no iconv implementation, cannot convert from %s to %s"
-+msgstr "nenhuma implementação iconv, não foi possível converter de %s para %s"
-+
-+#: charset.c:780
-+#, c-format
-+msgid "character 0x%lx is not in the basic source character set\n"
-+msgstr "caractere 0x%lx não está no conjunto de caracteres fonte básico\n"
-+
-+#: charset.c:797 charset.c:1443
-+msgid "converting to execution character set"
-+msgstr "convertendo para conjunto de caracteres da execução"
-+
-+#: charset.c:803
-+#, c-format
-+msgid "character 0x%lx is not unibyte in execution character set"
-+msgstr "caractere 0x%lx não é unibyte no conjunto de caracteres de execução"
-+
-+#: charset.c:927
-+#, c-format
-+msgid "Character %x might not be NFKC"
-+msgstr "Caractere %x pode não ser NFKC"
-+
-+#: charset.c:993
-+msgid "universal character names are only valid in C++ and C99"
-+msgstr "nomes de caractere universais são válidos apenas em C++ e C99"
-+
-+#: charset.c:996
-+#, c-format
-+msgid "the meaning of '\\%c' is different in traditional C"
-+msgstr "o significado de \"\\%c\" é diferente em C tradicional"
-+
-+#: charset.c:1005
-+msgid "In _cpp_valid_ucn but not a UCN"
-+msgstr "Em _cpp_valid_ucn, mas não é um UCN"
-+
-+#: charset.c:1030
-+#, c-format
-+msgid "incomplete universal character name %.*s"
-+msgstr "nome de caractere universal incompleto %.*s"
-+
-+#: charset.c:1045
-+#, c-format
-+msgid "%.*s is not a valid universal character"
-+msgstr "%.*s não é um caractere universal válido"
-+
-+#: charset.c:1055 lex.c:1117
-+msgid "'$' in identifier or number"
-+msgstr "\"$\" em identificador ou número"
-+
-+#: charset.c:1065
-+#, c-format
-+msgid "universal character %.*s is not valid in an identifier"
-+msgstr "caractere universal %.*s não é válido em um identificador"
-+
-+#: charset.c:1069
-+#, c-format
-+msgid "universal character %.*s is not valid at the start of an identifier"
-+msgstr "caractere universal %.*s não é válido no começo de um identificador"
-+
-+#: charset.c:1101 charset.c:1673
-+msgid "converting UCN to source character set"
-+msgstr "convertendo UCN para conjunto de caracteres fonte"
-+
-+#: charset.c:1105
-+msgid "converting UCN to execution character set"
-+msgstr "convertendo UCN para conjunto de caracteres de execução"
-+
-+#: charset.c:1177
-+msgid "the meaning of '\\x' is different in traditional C"
-+msgstr "o significado de \"\\x\" é diferente em C tradicional"
-+
-+#: charset.c:1194
-+msgid "\\x used with no following hex digits"
-+msgstr "\\x usado com nenhum dígito hexa"
-+
-+#: charset.c:1201
-+msgid "hex escape sequence out of range"
-+msgstr "sequência de escape hexa fora de alcance"
-+
-+#: charset.c:1239
-+msgid "octal escape sequence out of range"
-+msgstr "sequência de escape octal fora de alcance"
-+
-+#: charset.c:1305
-+msgid "the meaning of '\\a' is different in traditional C"
-+msgstr "o significado de \"\\a\" é diferente em C tradicional"
-+
-+#: charset.c:1312
-+#, c-format
-+msgid "non-ISO-standard escape sequence, '\\%c'"
-+msgstr "sequência de escape não padrão ISO, \"\\%c\""
-+
-+#: charset.c:1320
-+#, c-format
-+msgid "unknown escape sequence: '\\%c'"
-+msgstr "sequência de escape desconhecida: \"\\%c\""
-+
-+#: charset.c:1328
-+#, c-format
-+msgid "unknown escape sequence: '\\%s'"
-+msgstr "sequência de escape desconhecida: \"\\%s\""
-+
-+#: charset.c:1335
-+msgid "converting escape sequence to execution character set"
-+msgstr "convertendo sequência de escape para conjunto de caracteres de execução"
-+
-+#: charset.c:1508 charset.c:1572
-+msgid "character constant too long for its type"
-+msgstr "constante caractere muito longa para seu tipo"
-+
-+#: charset.c:1511
-+msgid "multi-character character constant"
-+msgstr "constante de caractere multi-caractere"
-+
-+#: charset.c:1611
-+msgid "empty character constant"
-+msgstr "constante caractere vazia"
-+
-+#: charset.c:1720
-+#, c-format
-+msgid "failure to convert %s to %s"
-+msgstr "falha ao converter %s para %s"
-+
-+#: directives.c:224 directives.c:250
-+#, c-format
-+msgid "extra tokens at end of #%s directive"
-+msgstr "tokens extras ao final da diretiva %#s"
-+
-+#: directives.c:357
-+#, c-format
-+msgid "#%s is a GCC extension"
-+msgstr "#%s é uma extensão GCC"
-+
-+#: directives.c:362
-+#, c-format
-+msgid "#%s is a deprecated GCC extension"
-+msgstr "#%s é uma extensão GCC obsoleta"
-+
-+#: directives.c:375
-+msgid "suggest not using #elif in traditional C"
-+msgstr "sugere-se não usar #elif em C tradicional"
-+
-+#: directives.c:378
-+#, c-format
-+msgid "traditional C ignores #%s with the # indented"
-+msgstr "C tradicional ignora #%s com o # com recuo"
-+
-+#: directives.c:382
-+#, c-format
-+msgid "suggest hiding #%s from traditional C with an indented #"
-+msgstr "sugere-se ocultar #%s do C tradicional com um # com recuo"
-+
-+#: directives.c:408
-+msgid "embedding a directive within macro arguments is not portable"
-+msgstr "embutir uma diretiva dentro de argumentos macro não é portátil"
-+
-+#: directives.c:428
-+msgid "style of line directive is a GCC extension"
-+msgstr "estilo de diretiva de linha é uma extensão GCC"
-+
-+#: directives.c:483
-+#, c-format
-+msgid "invalid preprocessing directive #%s"
-+msgstr "diretiva de preprocessamento inválida #%s"
-+
-+#: directives.c:551
-+msgid "\"defined\" cannot be used as a macro name"
-+msgstr "\"defined\" não pode ser usado como um nome de macro"
-+
-+#: directives.c:557
-+#, c-format
-+msgid "\"%s\" cannot be used as a macro name as it is an operator in C++"
-+msgstr "\"%s\" não pode ser usado como um nome de macro, pois é um operador em C++"
-+
-+#: directives.c:560
-+#, c-format
-+msgid "no macro name given in #%s directive"
-+msgstr "nenhum nome de macro fornecido na diretiva #%s"
-+
-+#: directives.c:563
-+msgid "macro names must be identifiers"
-+msgstr "nomes de macro devem ser identificadores"
-+
-+#: directives.c:612
-+#, c-format
-+msgid "undefining \"%s\""
-+msgstr "removendo definição de \"%s\""
-+
-+#: directives.c:667
-+msgid "missing terminating > character"
-+msgstr "faltando caractere terminador >"
-+
-+#: directives.c:726
-+#, c-format
-+msgid "#%s expects \"FILENAME\" or <FILENAME>"
-+msgstr "#%s espera \"NOME DE ARQUIVO\" OU <NOME DE ARQUIVO>"
-+
-+#: directives.c:772
-+#, c-format
-+msgid "empty filename in #%s"
-+msgstr "nome de arquivo vazio em #%s"
-+
-+#: directives.c:782
-+msgid "#include nested too deeply"
-+msgstr "#include aninhado profundo demais"
-+
-+#: directives.c:823
-+msgid "#include_next in primary source file"
-+msgstr "#include_next no arquivo fonte primário"
-+
-+#: directives.c:849
-+#, c-format
-+msgid "invalid flag \"%s\" in line directive"
-+msgstr "opção inválida \"%s\" na diretiva line"
-+
-+#: directives.c:909
-+msgid "unexpected end of file after #line"
-+msgstr "fim de arquivo inesperado após #line"
-+
-+#: directives.c:912
-+#, c-format
-+msgid "\"%s\" after #line is not a positive integer"
-+msgstr "\"%s\" após #line não é um inteiro positivo"
-+
-+#: directives.c:918 directives.c:920
-+msgid "line number out of range"
-+msgstr "número da linha fora de alcance"
-+
-+#: directives.c:933 directives.c:1013
-+#, c-format
-+msgid "\"%s\" is not a valid filename"
-+msgstr "\"%s\" não é um nome de arquivo válido"
-+
-+#: directives.c:973
-+#, c-format
-+msgid "\"%s\" after # is not a positive integer"
-+msgstr "\"%s\" após # não é um inteiro positivo"
-+
-+#: directives.c:1068 directives.c:1070 directives.c:1072 directives.c:1658
-+#, c-format
-+msgid "%s"
-+msgstr "%s"
-+
-+#: directives.c:1096
-+#, c-format
-+msgid "invalid #%s directive"
-+msgstr "diretiva inválida #%s"
-+
-+#: directives.c:1159
-+#, c-format
-+msgid "registering pragmas in namespace \"%s\" with mismatched name expansion"
-+msgstr "registrando pragmas em espaço de nomes \"%s\" com expansão de nome incompatível"
-+
-+#: directives.c:1168
-+#, c-format
-+msgid "registering pragma \"%s\" with name expansion and no namespace"
-+msgstr "registrando pragma \"%s\" com expansão de nome e nenhum espaço de nomes"
-+
-+#: directives.c:1186
-+#, c-format
-+msgid "registering \"%s\" as both a pragma and a pragma namespace"
-+msgstr "registrando \"%s\" como tanto um pragma e um espaço de nomes de pragma"
-+
-+#: directives.c:1189
-+#, c-format
-+msgid "#pragma %s %s is already registered"
-+msgstr "#pragma %s %s já está registrado"
-+
-+#: directives.c:1192
-+#, c-format
-+msgid "#pragma %s is already registered"
-+msgstr "#pragma %s já está registrado"
-+
-+#: directives.c:1222
-+msgid "registering pragma with NULL handler"
-+msgstr "registrando pragma com manipulador NULO"
-+
-+#: directives.c:1439
-+msgid "#pragma once in main file"
-+msgstr "#pragma ocorre uma vez no arquivo principal"
-+
-+#: directives.c:1462
-+msgid "invalid #pragma push_macro directive"
-+msgstr "diretiva inválida #pragma push_macro"
-+
-+#: directives.c:1517
-+msgid "invalid #pragma pop_macro directive"
-+msgstr "diretiva inválida #pragma pop_macro"
-+
-+#: directives.c:1572
-+msgid "invalid #pragma GCC poison directive"
-+msgstr "diretiva inválida #pragma GCC poison"
-+
-+#: directives.c:1581
-+#, c-format
-+msgid "poisoning existing macro \"%s\""
-+msgstr "envenenando macro existente \"%s\""
-+
-+#: directives.c:1600
-+msgid "#pragma system_header ignored outside include file"
-+msgstr "#pragma system_header ignorado fora do arquivo include"
-+
-+#: directives.c:1625
-+#, c-format
-+msgid "cannot find source file %s"
-+msgstr "não foi possível localizar o arquivo fonte %s"
-+
-+#: directives.c:1629
-+#, c-format
-+msgid "current file is older than %s"
-+msgstr "arquivo atual é mais velho do que %s"
-+
-+#: directives.c:1653
-+#, c-format
-+msgid "invalid \"#pragma GCC %s\" directive"
-+msgstr "diretiva inválida \"#pragma GCC %s\""
-+
-+#: directives.c:1847
-+msgid "_Pragma takes a parenthesized string literal"
-+msgstr "_Pragma leva uma literal de string entre parenteses"
-+
-+#: directives.c:1968
-+msgid "#else without #if"
-+msgstr "#else sem #if"
-+
-+#: directives.c:1973
-+msgid "#else after #else"
-+msgstr "#else após #else"
-+
-+#: directives.c:1975 directives.c:2008
-+msgid "the conditional began here"
-+msgstr "a condicional começou aqui"
-+
-+#: directives.c:2001
-+msgid "#elif without #if"
-+msgstr "#elif sem #if"
-+
-+#: directives.c:2006
-+msgid "#elif after #else"
-+msgstr "#elif após #else"
-+
-+#: directives.c:2044
-+msgid "#endif without #if"
-+msgstr "#endif sem #if"
-+
-+#: directives.c:2124
-+msgid "missing '(' after predicate"
-+msgstr "faltando \"(\" após predicado"
-+
-+#: directives.c:2139
-+msgid "missing ')' to complete answer"
-+msgstr "faltando \")\" para uma resposta completa"
-+
-+#: directives.c:2159
-+msgid "predicate's answer is empty"
-+msgstr "resposta do predicado está vazia"
-+
-+#: directives.c:2186
-+msgid "assertion without predicate"
-+msgstr "asserção sem predicado"
-+
-+#: directives.c:2189
-+msgid "predicate must be an identifier"
-+msgstr "predicado deve ser um identificador"
-+
-+#: directives.c:2275
-+#, c-format
-+msgid "\"%s\" re-asserted"
-+msgstr "\"%s\" re-assertado"
-+
-+#: directives.c:2567
-+#, c-format
-+msgid "unterminated #%s"
-+msgstr "#%s não terminado"
-+
-+#: directives-only.c:221 lex.c:2234 traditional.c:162
-+msgid "unterminated comment"
-+msgstr "comentário não terminado"
-+
-+#: errors.c:234
-+msgid "stdout"
-+msgstr "saída padrão"
-+
-+#: errors.c:236
-+#, c-format
-+msgid "%s: %s"
-+msgstr "%s: %s"
-+
-+#: expr.c:479 expr.c:577
-+msgid "fixed-point constants are a GCC extension"
-+msgstr "constantes de ponto fixo (fixed-point constants) é uma extensão GCC"
-+
-+#: expr.c:504
-+msgid "invalid prefix \"0b\" for floating constant"
-+msgstr "prefixo inválido \"0b\" para constante flutuante"
-+
-+#: expr.c:514
-+msgid "use of C99 hexadecimal floating constant"
-+msgstr "uso de constante flutuante hexadecimal de C99"
-+
-+#: expr.c:545
-+#, c-format
-+msgid "invalid suffix \"%.*s\" on floating constant"
-+msgstr "sufixo inválido \"%.*s\" na constante flutuante"
-+
-+#: expr.c:556 expr.c:616
-+#, c-format
-+msgid "traditional C rejects the \"%.*s\" suffix"
-+msgstr "C tradicional rejeita o sufixo \"%.*s\""
-+
-+#: expr.c:564
-+msgid "suffix for double constant is a GCC extension"
-+msgstr "sufixo para constante dupla (suffix for double constant) é uma extensão GCC"
-+
-+#: expr.c:570
-+#, c-format
-+msgid "invalid suffix \"%.*s\" with hexadecimal floating constant"
-+msgstr "sufixo inválido \"%.*s\" com constante flutuante hexadecimal"
-+
-+#: expr.c:581
-+msgid "decimal float constants are a GCC extension"
-+msgstr "constantes flutuante decimais (decimal float constants) é uma extensão GCC"
-+
-+#: expr.c:599
-+#, c-format
-+msgid "invalid suffix \"%.*s\" on integer constant"
-+msgstr "sufixo inválido \"%.*s\" em constante inteiro"
-+
-+#: expr.c:624
-+msgid "use of C++0x long long integer constant"
-+msgstr "uso de constante longo longo inteiro de C++0x"
-+
-+#: expr.c:625
-+msgid "use of C99 long long integer constant"
-+msgstr "uso de constante longo longo inteiro de C99"
-+
-+#: expr.c:641
-+msgid "imaginary constants are a GCC extension"
-+msgstr "constantes imaginárias (imaginary constants) é uma extensão GCC"
-+
-+#: expr.c:644
-+msgid "binary constants are a GCC extension"
-+msgstr "constantes binárias (binary constants) é uma extensão GCC"
-+
-+#: expr.c:737
-+msgid "integer constant is too large for its type"
-+msgstr "constante inteira é muito grande para seu tipo"
-+
-+#: expr.c:768
-+msgid "integer constant is so large that it is unsigned"
-+msgstr "constante inteira é tão grande que não está assinada"
-+
-+#: expr.c:863
-+msgid "missing ')' after \"defined\""
-+msgstr "faltando \")\" após \"defined\""
-+
-+#: expr.c:870
-+msgid "operator \"defined\" requires an identifier"
-+msgstr "operador \"defined\" requer um identificador"
-+
-+#: expr.c:878
-+#, c-format
-+msgid "(\"%s\" is an alternative token for \"%s\" in C++)"
-+msgstr "(\"%s\" é um token alternativo para \"%s\" em C++)"
-+
-+#: expr.c:888
-+msgid "this use of \"defined\" may not be portable"
-+msgstr "esse uso de \"defined\" pode não ser portátil"
-+
-+#: expr.c:948
-+msgid "user-defined literal in preprocessor expression"
-+msgstr "literal definida pelo usuário em expressão do preprocessador"
-+
-+#: expr.c:953
-+msgid "floating constant in preprocessor expression"
-+msgstr "constante flutuante em expressão do preprocessador"
-+
-+#: expr.c:959
-+msgid "imaginary number in preprocessor expression"
-+msgstr "número imaginário em expressão do preprocessador"
-+
-+#: expr.c:1007
-+#, c-format
-+msgid "\"%s\" is not defined"
-+msgstr "\"%s\" não está definido"
-+
-+#: expr.c:1020
-+msgid "assertions are a GCC extension"
-+msgstr "asserções (assertions) é uma extensão GCC"
-+
-+#: expr.c:1023
-+msgid "assertions are a deprecated extension"
-+msgstr "asserções (assertions) é uma extensão obsoleta"
-+
-+#: expr.c:1268
-+#, c-format
-+msgid "unbalanced stack in %s"
-+msgstr "pilha não balanceada em %s"
-+
-+#: expr.c:1288
-+#, c-format
-+msgid "impossible operator '%u'"
-+msgstr "operador impossível \"%u\""
-+
-+#: expr.c:1389
-+msgid "missing ')' in expression"
-+msgstr "faltando \")\" na expressão"
-+
-+#: expr.c:1418
-+msgid "'?' without following ':'"
-+msgstr "\"?\" sem estar seguido por \":\""
-+
-+#: expr.c:1428
-+msgid "integer overflow in preprocessor expression"
-+msgstr "estouro de inteiro em expressão do preprocessador"
-+
-+#: expr.c:1433
-+msgid "missing '(' in expression"
-+msgstr "faltando \"(\" na expressão"
-+
-+#: expr.c:1465
-+#, c-format
-+msgid "the left operand of \"%s\" changes sign when promoted"
-+msgstr "o operador à esquerda de \"%s\" altera o sinal quando promovido"
-+
-+#: expr.c:1470
-+#, c-format
-+msgid "the right operand of \"%s\" changes sign when promoted"
-+msgstr "o operador à direita de \"%s\" altera o sinal quando promovido"
-+
-+#: expr.c:1729
-+msgid "traditional C rejects the unary plus operator"
-+msgstr "C tradicional rejeita o operador unário mais"
-+
-+#: expr.c:1812
-+msgid "comma operator in operand of #if"
-+msgstr "operador vírgula em operando de #if"
-+
-+#: expr.c:1948
-+msgid "division by zero in #if"
-+msgstr "divisão por zero em #if"
-+
-+#: files.c:505
-+msgid "NULL directory in find_file"
-+msgstr "diretório NULO em find_file"
-+
-+#: files.c:553
-+msgid "one or more PCH files were found, but they were invalid"
-+msgstr "um ou mais arquivos PCH foram encontrados, mas são inválidos"
-+
-+#: files.c:556
-+msgid "use -Winvalid-pch for more information"
-+msgstr "use -Winvalid-pch para mais informações"
-+
-+#: files.c:660
-+#, c-format
-+msgid "%s is a block device"
-+msgstr "%s é um dispositivo de bloco"
-+
-+#: files.c:677
-+#, c-format
-+msgid "%s is too large"
-+msgstr "%s é muito grande"
-+
-+#: files.c:717
-+#, c-format
-+msgid "%s is shorter than expected"
-+msgstr "%s é muito menor do que esperado"
-+
-+#: files.c:953
-+#, c-format
-+msgid "no include path in which to search for %s"
-+msgstr "não foi incluído nenhum caminho no qual se possa procurar por %s"
-+
-+#: files.c:1381
-+msgid "Multiple include guards may be useful for:\n"
-+msgstr "Múltiplos include guards podem ser úteis para:\n"
-+
-+#: init.c:524
-+msgid "cppchar_t must be an unsigned type"
-+msgstr "cppchar_t deve ser um tipo não assinado"
-+
-+#: init.c:528
-+#, c-format
-+msgid "preprocessor arithmetic has maximum precision of %lu bits; target requires %lu bits"
-+msgstr "aritmética do preprocessador possui uma precisão máxima de %lu bits; o alvo requer %lu bits"
-+
-+#: init.c:535
-+msgid "CPP arithmetic must be at least as precise as a target int"
-+msgstr "aritmética do CPP deve ser pelo menos tão precisa quanto um int alvo"
-+
-+#: init.c:538
-+msgid "target char is less than 8 bits wide"
-+msgstr "char alvo é menor do que 8 bits"
-+
-+#: init.c:542
-+msgid "target wchar_t is narrower than target char"
-+msgstr "wchar_t alvo é mais estreito do que o char alvo"
-+
-+#: init.c:546
-+msgid "target int is narrower than target char"
-+msgstr "int alvo é mais estreito do que o char alvo"
-+
-+#: init.c:551
-+msgid "CPP half-integer narrower than CPP character"
-+msgstr "meio-inteiro do CPP é mais estreito do que o caractere do CPP"
-+
-+#: init.c:555
-+#, c-format
-+msgid "CPP on this host cannot handle wide character constants over %lu bits, but the target requires %lu bits"
-+msgstr "CPP nesta máquina não consegue manipular constantes de wide character acima de %lu bits, mas o alvo requer %lu bits"
-+
-+#: lex.c:910
-+msgid "backslash and newline separated by space"
-+msgstr "barra invertida e nova linha separadas por espaço"
-+
-+#: lex.c:915
-+msgid "backslash-newline at end of file"
-+msgstr "barra invertida e nova linha no final do arquivo"
-+
-+#: lex.c:931
-+#, c-format
-+msgid "trigraph ??%c converted to %c"
-+msgstr "trígrafo ??%c convertido para %c"
-+
-+#: lex.c:939
-+#, c-format
-+msgid "trigraph ??%c ignored, use -trigraphs to enable"
-+msgstr "trígrafo ??%c ignorado, use -trigraphs para habilitá-lo"
-+
-+#: lex.c:988
-+msgid "\"/*\" within comment"
-+msgstr "\"/*\" dentro de comentário"
-+
-+#: lex.c:1046
-+#, c-format
-+msgid "%s in preprocessing directive"
-+msgstr "%s em diretiva de preprocessamento"
-+
-+#: lex.c:1055
-+msgid "null character(s) ignored"
-+msgstr "um ou mais caracteres nulos ignorados"
-+
-+#: lex.c:1092
-+#, c-format
-+msgid "`%.*s' is not in NFKC"
-+msgstr "\"%.*s\" não está em NFKC"
-+
-+#: lex.c:1095
-+#, c-format
-+msgid "`%.*s' is not in NFC"
-+msgstr "\"%.*s\" não está em NFC"
-+
-+#: lex.c:1164 lex.c:1241
-+#, c-format
-+msgid "attempt to use poisoned \"%s\""
-+msgstr "tentativa de usar \"%s\" envenenado"
-+
-+#: lex.c:1172 lex.c:1249
-+msgid "__VA_ARGS__ can only appear in the expansion of a C99 variadic macro"
-+msgstr "__VA_ARGS__ pode aparecer apenas na expansão de uma macro variádica C99"
-+
-+#: lex.c:1178 lex.c:1255
-+#, c-format
-+msgid "identifier \"%s\" is a special operator name in C++"
-+msgstr "identificador \"%s\" é o nome de um operador especial em C++"
-+
-+#: lex.c:1399
-+msgid "raw string delimiter longer than 16 characters"
-+msgstr "delimitador de string não tratada (raw) maior do que 16 caracteres"
-+
-+#: lex.c:1402
-+#, c-format
-+msgid "invalid character '%c' in raw string delimiter"
-+msgstr "caractere inválido \"%c\" em delimitador de string não tratada (raw)"
-+
-+#: lex.c:1525 lex.c:1547
-+msgid "unterminated raw string"
-+msgstr "string não tratada (raw) não terminada"
-+
-+#: lex.c:1573 lex.c:1706
-+msgid "invalid suffix on literal; C++11 requires a space between literal and identifier"
-+msgstr "sufixo inválido em literal; C++11 requer um espaço entre literal e identificador"
-+
-+#: lex.c:1684
-+msgid "null character(s) preserved in literal"
-+msgstr "um ou mais caracteres nulos preservados em literal"
-+
-+#: lex.c:1687
-+#, c-format
-+msgid "missing terminating %c character"
-+msgstr "faltando o caractere de terminação %c"
-+
-+#: lex.c:2245
-+msgid "C++ style comments are not allowed in ISO C90"
-+msgstr "comentários no estilo C++ não são permitidos em ISO C90"
-+
-+#: lex.c:2247
-+msgid "(this will be reported only once per input file)"
-+msgstr "(isso será relatado apenas uma vez por arquivo de entrada)"
-+
-+#: lex.c:2252
-+msgid "multi-line comment"
-+msgstr "comentário multilinha"
-+
-+#: lex.c:2583
-+#, c-format
-+msgid "unspellable token %s"
-+msgstr "token %s impronunciável"
-+
-+#: macro.c:191
-+#, c-format
-+msgid "macro \"%s\" is not used"
-+msgstr "macro \"%s\" não é usada"
-+
-+#: macro.c:229 macro.c:426
-+#, c-format
-+msgid "invalid built-in macro \"%s\""
-+msgstr "macro interna inválida \"%s\""
-+
-+#: macro.c:263
-+msgid "could not determine file timestamp"
-+msgstr "não foi possível determinar o arquivo de marca de tempo"
-+
-+#: macro.c:361
-+msgid "could not determine date and time"
-+msgstr "não foi possível determinar a data e a hora"
-+
-+#: macro.c:377
-+msgid "__COUNTER__ expanded inside directive with -fdirectives-only"
-+msgstr "__COUNTER__ expandido dentro diretiva com -fdirectives-only"
-+
-+#: macro.c:535
-+msgid "invalid string literal, ignoring final '\\'"
-+msgstr "literal de string inválida, ignorando final \"\\\""
-+
-+#: macro.c:597
-+#, c-format
-+msgid "pasting \"%s\" and \"%s\" does not give a valid preprocessing token"
-+msgstr "colar \"%s\" em \"%s\" não resulta em nenhum token de preprocessamento válido"
-+
-+#: macro.c:719
-+msgid "ISO C99 requires rest arguments to be used"
-+msgstr "ISO C99 requer que argumentos restantes sejam usados"
-+
-+#: macro.c:724
-+#, c-format
-+msgid "macro \"%s\" requires %u arguments, but only %u given"
-+msgstr "macro \"%s\" requer %u argumentos, mas apenas %u foram fornecidos"
-+
-+#: macro.c:729
-+#, c-format
-+msgid "macro \"%s\" passed %u arguments, but takes just %u"
-+msgstr "macro \"%s\" passou %u argumentos, mas usa apenas %u"
-+
-+#: macro.c:923 traditional.c:680
-+#, c-format
-+msgid "unterminated argument list invoking macro \"%s\""
-+msgstr "lista de argumentos interminável chamando macro \"%s\""
-+
-+#: macro.c:1074
-+#, c-format
-+msgid "function-like macro \"%s\" must be used with arguments in traditional C"
-+msgstr "macro \"%s\" do tipo função deve ser usada com argumento em C tradicional"
-+
-+# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=33305
-+#: macro.c:1746
-+#, c-format
-+msgid "invoking macro %s argument %d: empty macro arguments are undefined in ISO C90 and ISO C++98"
-+msgstr "chamando macro %s argumento %d: argumentos de macro vazios estão indefinidos em ISO C90 e ISO C++98"
-+
-+#: macro.c:2708
-+#, c-format
-+msgid "duplicate macro parameter \"%s\""
-+msgstr "parâmetro de macro \"%s\" duplicado"
-+
-+#: macro.c:2754
-+#, c-format
-+msgid "\"%s\" may not appear in macro parameter list"
-+msgstr "\"%s\" não pode aparecer na lista de parâmetros de macro"
-+
-+#: macro.c:2762
-+msgid "macro parameters must be comma-separated"
-+msgstr "parâmetros de macro devem ser separados por vírgula"
-+
-+#: macro.c:2779
-+msgid "parameter name missing"
-+msgstr "faltando nome de parâmetro"
-+
-+#: macro.c:2797
-+msgid "anonymous variadic macros were introduced in C99"
-+msgstr "macros variádicas anônimas foram introduzidas em C99"
-+
-+#: macro.c:2802
-+msgid "ISO C does not permit named variadic macros"
-+msgstr "ISO C não permite macros variádicas nomeadas"
-+
-+#: macro.c:2811
-+msgid "missing ')' in macro parameter list"
-+msgstr "faltando \")\" na lista de parâmetros de macro"
-+
-+#: macro.c:2860
-+msgid "'##' cannot appear at either end of a macro expansion"
-+msgstr "\"##\" não pode aparecer no final da expansão de macro"
-+
-+#: macro.c:2895
-+msgid "ISO C99 requires whitespace after the macro name"
-+msgstr "ISO C99 requer espaço em branco após o nome de macro"
-+
-+#: macro.c:2919
-+msgid "missing whitespace after the macro name"
-+msgstr "faltando espaço em branco após o nome de macro"
-+
-+#: macro.c:2953
-+msgid "'#' is not followed by a macro parameter"
-+msgstr "\"#\" não está seguido por um parâmetro de macro"
-+
-+#: macro.c:3111
-+#, c-format
-+msgid "\"%s\" redefined"
-+msgstr "\"%s\" re-definido"
-+
-+#: macro.c:3117
-+msgid "this is the location of the previous definition"
-+msgstr "essa é a localização da definição anterior"
-+
-+#: macro.c:3178
-+#, c-format
-+msgid "macro argument \"%s\" would be stringified in traditional C"
-+msgstr "argumento de macro \"%s\" estaria em uma string no C tradicional"
-+
-+#: macro.c:3205
-+#, c-format
-+msgid "invalid hash type %d in cpp_macro_definition"
-+msgstr "tipo de hash inválido %d em cpp_macro_definition"
-+
-+#: pch.c:87 pch.c:345 pch.c:359 pch.c:377 pch.c:383 pch.c:392 pch.c:399
-+msgid "while writing precompiled header"
-+msgstr "enquanto realizava escrita de header pré-compilado"
-+
-+#: pch.c:619
-+#, c-format
-+msgid "%s: not used because `%.*s' is poisoned"
-+msgstr "%s: não usado porque \"%.*s\" está envenenado"
-+
-+#: pch.c:641
-+#, c-format
-+msgid "%s: not used because `%.*s' not defined"
-+msgstr "%s: não usado porque \"%.*s\" não está definido"
-+
-+#: pch.c:653
-+#, c-format
-+msgid "%s: not used because `%.*s' defined as `%s' not `%.*s'"
-+msgstr "%s: não usado porque \"%.*s\" está definido como \"%s\", e não \"%.*s\""
-+
-+#: pch.c:694
-+#, c-format
-+msgid "%s: not used because `%s' is defined"
-+msgstr "%s: não usado porque \"%s\" está definido"
-+
-+#: pch.c:714
-+#, c-format
-+msgid "%s: not used because `__COUNTER__' is invalid"
-+msgstr "%s: não usado porque \"__COUNTER__\" é inválido"
-+
-+#: pch.c:723 pch.c:898
-+msgid "while reading precompiled header"
-+msgstr "enquanto realizava leitura de header pré-compilado"
-+
-+#: traditional.c:750
-+#, c-format
-+msgid "detected recursion whilst expanding macro \"%s\""
-+msgstr "detectada recursão enquanto expandia macro \"%s\""
-+
-+#: traditional.c:968
-+msgid "syntax error in macro parameter list"
-+msgstr "erro de sintaxe na lista de parâmetros de macro"
-Index: libcpp/po/ChangeLog
-===================================================================
---- a/src/libcpp/po/ChangeLog (.../tags/gcc_4_8_2_release)
-+++ b/src/libcpp/po/ChangeLog (.../branches/gcc-4_8-branch)
-@@ -1,3 +1,11 @@
-+2013-12-18 Joseph Myers <joseph@codesourcery.com>
-+
-+ * pt_BR.po: New.
-+
-+2013-11-01 Joseph Myers <joseph@codesourcery.com>
-+
-+ * tr.po: Update.
-+
- 2013-10-16 Release Manager
-
- * GCC 4.8.2 released.
-Index: libcpp/po/tr.po
-===================================================================
---- a/src/libcpp/po/tr.po (.../tags/gcc_4_8_2_release)
-+++ b/src/libcpp/po/tr.po (.../branches/gcc-4_8-branch)
-@@ -1,20 +1,22 @@
- # Turkish translations for cpplib messages.
- # Copyright (C) 2007 Free Software Foundation, Inc.
-+# This file is distributed under the same license as the gcc package.
- #
- # Nilgün Belma Bugüner <nilgun@buguner.name.tr>, 2001, ..., 2007.
-+# Volkan Gezer <vlkngzr@gmail.com>, 2013.
- msgid ""
- msgstr ""
--"Project-Id-Version: cpplib 4.2.0\n"
-+"Project-Id-Version: cpplib 4.8.0\n"
- "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"
--"POT-Creation-Date: 2013-02-24 01:05+0000\n"
--"PO-Revision-Date: 2007-05-23 01:17+0300\n"
--"Last-Translator: Nilgün Belma Bugüner <nilgun@buguner.name.tr>\n"
-+"POT-Creation-Date: 2013-03-15 17:42+0000\n"
-+"PO-Revision-Date: 2013-11-01 22:29+0100\n"
-+"Last-Translator: Volkan Gezer <vlkngzr@gmail.com>\n"
- "Language-Team: Turkish <gnu-tr-u12a@lists.sourceforge.net>\n"
- "Language: tr\n"
- "MIME-Version: 1.0\n"
- "Content-Type: text/plain; charset=UTF-8\n"
- "Content-Transfer-Encoding: 8bit\n"
--"X-Generator: KBabel 1.11.4\n"
-+"X-Generator: Lokalize 1.5\n"
- "Plural-Forms: nplurals=2; plural=(n != 1);\n"
-
- #: charset.c:673
-@@ -121,10 +123,9 @@
- msgstr "ISO standardı olmayan önceleme dizgesi, '\\%c'"
-
- #: charset.c:1320
--#, fuzzy, c-format
--#| msgid "unknown escape sequence '\\%c'"
-+#, c-format
- msgid "unknown escape sequence: '\\%c'"
--msgstr "bilinmeyen önceleme dizgesi '\\%c'"
-+msgstr "bilinmeyen kaçış dizgesi: '\\%c'"
-
- #: charset.c:1328
- #, c-format
-@@ -163,10 +164,9 @@
- msgstr "#%s bir GCC uzantısıdır"
-
- #: directives.c:362
--#, fuzzy, c-format
--#| msgid "#%s is a GCC extension"
-+#, c-format
- msgid "#%s is a deprecated GCC extension"
--msgstr "#%s bir GCC uzantısıdır"
-+msgstr "#%s eskimiş bir GCC uzantısıdır"
-
- #: directives.c:375
- msgid "suggest not using #elif in traditional C"
-@@ -247,7 +247,7 @@
-
- #: directives.c:909
- msgid "unexpected end of file after #line"
--msgstr ""
-+msgstr "#line satırından sonra beklenmeyen dosya sonu"
-
- #: directives.c:912
- #, c-format
-@@ -271,7 +271,7 @@
- #: directives.c:1068 directives.c:1070 directives.c:1072 directives.c:1658
- #, c-format
- msgid "%s"
--msgstr ""
-+msgstr "%s"
-
- #: directives.c:1096
- #, c-format
-@@ -312,16 +312,12 @@
- msgstr "main dosyasında '#pragma once'"
-
- #: directives.c:1462
--#, fuzzy
--#| msgid "invalid #pragma GCC poison directive"
- msgid "invalid #pragma push_macro directive"
--msgstr "geçersiz #pragma GCC poison yönergesi"
-+msgstr "geçersiz #pragma güdümlü_makro yönergesi"
-
- #: directives.c:1517
--#, fuzzy
--#| msgid "invalid #pragma GCC poison directive"
- msgid "invalid #pragma pop_macro directive"
--msgstr "geçersiz #pragma GCC poison yönergesi"
-+msgstr "geçersiz #pragma güdümlü_makro yönergesi"
-
- #: directives.c:1572
- msgid "invalid #pragma GCC poison directive"
-@@ -347,10 +343,9 @@
- msgstr "mevcut dosya %s den daha eski"
-
- #: directives.c:1653
--#, fuzzy, c-format
--#| msgid "invalid #pragma GCC poison directive"
-+#, c-format
- msgid "invalid \"#pragma GCC %s\" directive"
--msgstr "geçersiz #pragma GCC poison yönergesi"
-+msgstr "geçersiz \"#pragma GCC %s\" yönergesi"
-
- #: directives.c:1847
- msgid "_Pragma takes a parenthesized string literal"
-@@ -405,7 +400,7 @@
- msgid "\"%s\" re-asserted"
- msgstr "\"%s\" tekrar olumlanmış"
-
--#: directives.c:2566
-+#: directives.c:2567
- #, c-format
- msgid "unterminated #%s"
- msgstr "sonlandırılmamış #%s"
-@@ -424,16 +419,12 @@
- msgstr "%s: %s"
-
- #: expr.c:479 expr.c:577
--#, fuzzy
--#| msgid "imaginary constants are a GCC extension"
- msgid "fixed-point constants are a GCC extension"
--msgstr "sanal sabitler bir GCC genişletmesidir"
-+msgstr "sabit noktalı sabitler bir GCC uzantısıdır"
-
- #: expr.c:504
--#, fuzzy
--#| msgid "invalid suffix \"%.*s\" on floating constant"
- msgid "invalid prefix \"0b\" for floating constant"
--msgstr "gerçel sabitin \"%.*s\" soneki geçersiz"
-+msgstr "kayan nokta için geçerisz \"0b\" öntakısı"
-
- #: expr.c:514
- msgid "use of C99 hexadecimal floating constant"
-@@ -450,10 +441,8 @@
- msgstr "geleneksel C \"%.*s\" sonekini kullanmaz"
-
- #: expr.c:564
--#, fuzzy
--#| msgid "imaginary constants are a GCC extension"
- msgid "suffix for double constant is a GCC extension"
--msgstr "sanal sabitler bir GCC genişletmesidir"
-+msgstr "çift sabit için öntakı bir GCC uzantısıdır"
-
- #: expr.c:570
- #, c-format
-@@ -461,10 +450,8 @@
- msgstr "onaltılık kayan sabitli \"%.*s\" soneki geçersiz"
-
- #: expr.c:581
--#, fuzzy
--#| msgid "imaginary constants are a GCC extension"
- msgid "decimal float constants are a GCC extension"
--msgstr "sanal sabitler bir GCC genişletmesidir"
-+msgstr "onluk kayan sabitler bir GCC uzantısıdır"
-
- #: expr.c:599
- #, c-format
-@@ -472,10 +459,8 @@
- msgstr "tamsayı sabitte sonek \"%.*s\" soneki geçersiz"
-
- #: expr.c:624
--#, fuzzy
--#| msgid "use of C99 long long integer constant"
- msgid "use of C++0x long long integer constant"
--msgstr "ISO C99 long long tamsayı sabitleri yasaklar"
-+msgstr "ISO C++0x long long tamsayı sabitlerinin kullanımı"
-
- #: expr.c:625
- msgid "use of C99 long long integer constant"
-@@ -486,10 +471,8 @@
- msgstr "sanal sabitler bir GCC genişletmesidir"
-
- #: expr.c:644
--#, fuzzy
--#| msgid "imaginary constants are a GCC extension"
- msgid "binary constants are a GCC extension"
--msgstr "sanal sabitler bir GCC genişletmesidir"
-+msgstr "ikili sabitler bir GCC uzantısıdır"
-
- #: expr.c:737
- msgid "integer constant is too large for its type"
-@@ -517,10 +500,8 @@
- msgstr "\"defined\" bu kullanımıyla uyarlanabilir olmayabilir"
-
- #: expr.c:948
--#, fuzzy
--#| msgid "integer overflow in preprocessor expression"
- msgid "user-defined literal in preprocessor expression"
--msgstr "önişlemci ifadesinde tamsayı taşması"
-+msgstr "önişleyici ifadesinde kullanıcı tanımlı bağımlı"
-
- #: expr.c:953
- msgid "floating constant in preprocessor expression"
-@@ -536,20 +517,17 @@
- msgstr "\"%s\" tanımlı değil"
-
- #: expr.c:1020
--#, fuzzy
--#| msgid "#%s is a GCC extension"
- msgid "assertions are a GCC extension"
--msgstr "#%s bir GCC uzantısıdır"
-+msgstr "belirteçler bir GCC uzantısıdır"
-
- #: expr.c:1023
- msgid "assertions are a deprecated extension"
--msgstr ""
-+msgstr "belirteçler artık kullanılmayan bir ifadedir"
-
- #: expr.c:1268
--#, fuzzy, c-format
--#| msgid "unbalanced stack in #if"
-+#, c-format
- msgid "unbalanced stack in %s"
--msgstr "#if ifadesinde karşılıksız yığın"
-+msgstr "%s içinde dengelenmemiş yığın"
-
- #: expr.c:1288
- #, c-format
-@@ -594,39 +572,39 @@
- msgid "division by zero in #if"
- msgstr "#if içinde sıfırla bölme"
-
--#: files.c:504
-+#: files.c:505
- msgid "NULL directory in find_file"
- msgstr "find_file içinde boş dizin"
-
--#: files.c:542
-+#: files.c:553
- msgid "one or more PCH files were found, but they were invalid"
- msgstr "bir veya daha fazla PCH dosyası bulundu ama bunlar geçersiz"
-
--#: files.c:545
-+#: files.c:556
- msgid "use -Winvalid-pch for more information"
- msgstr "daha fazla bilgi almak için -Winvalid-pch kullanın"
-
--#: files.c:643
-+#: files.c:660
- #, c-format
- msgid "%s is a block device"
- msgstr "%s bir blok aygıtıdır"
-
--#: files.c:660
-+#: files.c:677
- #, c-format
- msgid "%s is too large"
- msgstr "%s çok büyük"
-
--#: files.c:700
-+#: files.c:717
- #, c-format
- msgid "%s is shorter than expected"
- msgstr "%s beklenenden daha kısa"
-
--#: files.c:935
-+#: files.c:953
- #, c-format
- msgid "no include path in which to search for %s"
- msgstr "%s için aranacaklar içinde başlık dosyaları yolu yok"
-
--#: files.c:1363
-+#: files.c:1381
- msgid "Multiple include guards may be useful for:\n"
- msgstr "Çoklu include önlemleri aşağıdakiler için kullanışlı olabilir:\n"
-
-@@ -717,27 +695,24 @@
- #: lex.c:1178 lex.c:1255
- #, c-format
- msgid "identifier \"%s\" is a special operator name in C++"
--msgstr ""
-+msgstr "\"%s\" belirteci, C++'da özel bir işleç adıdır"
-
- #: lex.c:1399
- msgid "raw string delimiter longer than 16 characters"
--msgstr ""
-+msgstr "ham dizge ayracı 16 karakterden uzun"
-
- #: lex.c:1402
--#, fuzzy, c-format
--#| msgid "universal character %.*s is not valid in an identifier"
-+#, c-format
- msgid "invalid character '%c' in raw string delimiter"
--msgstr "evrensel karakter %.*s bir belirteç içinde geçerli değil"
-+msgstr "ham dizge ayracında geçersiz karakter '%c'"
-
- #: lex.c:1525 lex.c:1547
--#, fuzzy
--#| msgid "unterminated #%s"
- msgid "unterminated raw string"
--msgstr "sonlandırılmamış #%s"
-+msgstr "bitirilmemiş ham dizge"
-
- #: lex.c:1573 lex.c:1706
- msgid "invalid suffix on literal; C++11 requires a space between literal and identifier"
--msgstr ""
-+msgstr "geçersiz ifade soneki; C++11 ifade ve tanımlayıcı arasında bir boşluk gerektirir"
-
- #: lex.c:1684
- msgid "null character(s) preserved in literal"
-@@ -785,7 +760,7 @@
-
- #: macro.c:377
- msgid "__COUNTER__ expanded inside directive with -fdirectives-only"
--msgstr ""
-+msgstr "__COUNTER__ -fdirectives-only ile talimat içerisinde genişletildi"
-
- #: macro.c:535
- msgid "invalid string literal, ignoring final '\\'"
-@@ -823,7 +798,7 @@
- #: macro.c:1746
- #, c-format
- msgid "invoking macro %s argument %d: empty macro arguments are undefined in ISO C90 and ISO C++98"
--msgstr ""
-+msgstr "%s makrosu %d argümanı uygulanıyor: ISO C90 ve ISO C++98 içerisinde boş makro argümanları tanımsızdır"
-
- #: macro.c:2708
- #, c-format
-@@ -890,38 +865,36 @@
- msgid "invalid hash type %d in cpp_macro_definition"
- msgstr "cpp_macro_definition içindeki isimli yapı türü %d geçersiz"
-
--#: pch.c:87 pch.c:335 pch.c:347 pch.c:365 pch.c:371 pch.c:380 pch.c:387
-+#: pch.c:87 pch.c:345 pch.c:359 pch.c:377 pch.c:383 pch.c:392 pch.c:399
- msgid "while writing precompiled header"
- msgstr "önderlemeli başlık yazılırken"
-
--#: pch.c:607
--#, fuzzy, c-format
--#| msgid "%s: not used because `%s' is defined"
-+#: pch.c:619
-+#, c-format
- msgid "%s: not used because `%.*s' is poisoned"
--msgstr "%s: `%s' tanımlı olduğundan kullanılmadı"
-+msgstr "%s: `%.*s' zehirli olduğu için kullanılmadı"
-
--#: pch.c:629
-+#: pch.c:641
- #, c-format
- msgid "%s: not used because `%.*s' not defined"
- msgstr "%s: `%.*s' tanımlı olmadığından kullanılmadı"
-
--#: pch.c:641
-+#: pch.c:653
- #, c-format
- msgid "%s: not used because `%.*s' defined as `%s' not `%.*s'"
- msgstr "%s: `%.*s' kullanılmadı çünkü `%s' olarak tanımlı, `%.*s' değil"
-
--#: pch.c:682
-+#: pch.c:694
- #, c-format
- msgid "%s: not used because `%s' is defined"
- msgstr "%s: `%s' tanımlı olduğundan kullanılmadı"
-
--#: pch.c:702
--#, fuzzy, c-format
--#| msgid "%s: not used because `%s' is defined"
-+#: pch.c:714
-+#, c-format
- msgid "%s: not used because `__COUNTER__' is invalid"
--msgstr "%s: `%s' tanımlı olduğundan kullanılmadı"
-+msgstr "%s: `__COUNTER__' geçersiz olduğundan kullanılmadı"
-
--#: pch.c:711 pch.c:886
-+#: pch.c:723 pch.c:898
- msgid "while reading precompiled header"
- msgstr "önderlemeli başlık okunurken"
-
-Index: .
-===================================================================
---- a/src/. (.../tags/gcc_4_8_2_release)
-+++ b/src/. (.../branches/gcc-4_8-branch)
-
-Property changes on: .
-___________________________________________________________________
-Modified: svn:mergeinfo
- Merged /trunk:r202766,204547,206123-206126,206395,206628,207387
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-17 09:29:22 +0000