* Update to SVN 20140502 (r210004) from the gcc-4_9-branch.

git-svn-id: svn://svn.debian.org/svn/gcccvs/branches/sid/gcc-4.9@7333 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca

2 files changed, 3208 insertions, 31 deletions

diff --git a/debian/changelog b/debian/changelog
index b998573..43a8f2d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,6 @@
 gcc-4.9 (4.9.0-2) UNRELEASED; urgency=medium
 
-  * Update to SVN 20140425 (r209789) from the gcc-4_9-branch.
+  * Update to SVN 20140502 (r210004) from the gcc-4_9-branch.
     - Fix PR go/60931, garbage collector issue with non 4kB system page size.
       LP: #1304754.
   * Fix libgcc-dev dependency on gcc, when not building libgcc.
@@ -11,7 +11,7 @@ gcc-4.9 (4.9.0-2) UNRELEASED; urgency=medium
   * Fix the as and ld symlinks for the hppa64 cross compiler.
   * Add the gnat backport for AArch64.
 
- -- Matthias Klose <doko@debian.org>  Fri, 25 Apr 2014 11:45:58 +0200
+ -- Matthias Klose <doko@debian.org>  Fri, 02 May 2014 13:51:28 +0200
 
 gcc-4.9 (4.9.0-1) unstable; urgency=medium
 
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index 52b1418..fd5f151 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 4.9 branch upto 20140425 (r209789).
+# DP: updates from the 4.9 branch upto 20140502 (r210004).
 
 last_updated()
 {
 	cat > ${dir}LAST_UPDATED <<EOF
-Fri Apr 25 11:40:42 CEST 2014
-Fri Apr 25 09:40:42 UTC 2014 (revision 209789)
+Fri May  2 13:37:05 CEST 2014
+Fri May  2 11:37:05 UTC 2014 (revision 210004)
 EOF
 }
 
@@ -574,6 +574,347 @@ Index: libgomp/testsuite/libgomp.c/simd-8.c
 +    abort ();
 +  return 0;
 +}
+Index: libstdc++-v3/include/std/tuple
+===================================================================
+--- a/src/libstdc++-v3/include/std/tuple	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/include/std/tuple	(.../branches/gcc-4_9-branch)
+@@ -710,6 +710,11 @@
+       add_cv<typename tuple_element<__i, _Tp>::type>::type type;
+     };
+ 
++#if __cplusplus > 201103L
++  template<std::size_t __i, typename _Tp>
++    using tuple_element_t = typename tuple_element<__i, _Tp>::type;
++#endif
++
+   /// Finds the size of a given tuple type.
+   template<typename _Tp>
+     struct tuple_size;
+@@ -755,7 +760,7 @@
+                       typename tuple_element<__i, tuple<_Elements...>>::type
+                     >::type
+     get(tuple<_Elements...>& __t) noexcept
+-    { return __get_helper<__i>(__t); }
++    { return std::__get_helper<__i>(__t); }
+ 
+   template<std::size_t __i, typename... _Elements>
+     constexpr typename __add_c_ref<
+@@ -762,7 +767,7 @@
+                       typename tuple_element<__i, tuple<_Elements...>>::type
+                     >::type
+     get(const tuple<_Elements...>& __t) noexcept
+-    { return __get_helper<__i>(__t); }
++    { return std::__get_helper<__i>(__t); }
+ 
+   template<std::size_t __i, typename... _Elements>
+     constexpr typename __add_r_ref<
+@@ -786,17 +791,17 @@
+   template <typename _Tp, typename... _Types>
+     constexpr _Tp&
+     get(tuple<_Types...>& __t) noexcept
+-    { return __get_helper2<_Tp>(__t); }
++    { return std::__get_helper2<_Tp>(__t); }
+ 
+   template <typename _Tp, typename... _Types>
+     constexpr _Tp&&
+     get(tuple<_Types...>&& __t) noexcept
+-    { return std::move(__get_helper2<_Tp>(__t)); }
++    { return std::move(std::__get_helper2<_Tp>(__t)); }
+ 
+   template <typename _Tp, typename... _Types>
+     constexpr const _Tp&
+     get(const tuple<_Types...>& __t) noexcept
+-    { return __get_helper2<_Tp>(__t); }
++    { return std::__get_helper2<_Tp>(__t); }
+ #endif
+ 
+   // This class helps construct the various comparison operations on tuples
+Index: libstdc++-v3/include/experimental/optional
+===================================================================
+--- a/src/libstdc++-v3/include/experimental/optional	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/include/experimental/optional	(.../branches/gcc-4_9-branch)
+@@ -736,12 +736,12 @@
+   template<typename _Tp>
+     constexpr bool
+     operator!=(const optional<_Tp>& __lhs, _Tp const& __rhs)
+-    { return !__lhs || *__lhs != __rhs; }
++    { return !__lhs || !(*__lhs == __rhs); }
+ 
+   template<typename _Tp>
+     constexpr bool
+     operator!=(const _Tp& __lhs, const optional<_Tp>& __rhs)
+-    { return !__rhs || __lhs != *__rhs; }
++    { return !__rhs || !(__lhs == *__rhs); }
+ 
+   template<typename _Tp>
+     constexpr bool
+Index: libstdc++-v3/ChangeLog
+===================================================================
+--- a/src/libstdc++-v3/ChangeLog	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/ChangeLog	(.../branches/gcc-4_9-branch)
+@@ -1,3 +1,26 @@
++2014-04-27  Lars Gullik Bjønnes  <larsbj@gullik.org>
++
++	PR libstdc++/60710
++	* include/experimental/optional (operator!=): Implement in terms of
++	operator==.
++	* testsuite/experimental/optional/relops/1.cc: Remove operator!=.
++	* testsuite/experimental/optional/relops/2.cc: Likewise.
++	* testsuite/experimental/optional/relops/3.cc: Likewise.
++	* testsuite/experimental/optional/relops/4.cc: Likewise.
++	* testsuite/experimental/optional/relops/5.cc: Likewise.
++	* testsuite/experimental/optional/relops/6.cc: Likewise.
++
++2014-04-27  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/60497
++	* include/std/tuple (get): Qualify calls to prevent ADL.
++	* testsuite/20_util/tuple/60497.cc: New.
++
++	* include/std/tuple (tuple_element_t): Define.
++	* testsuite/20_util/tuple/tuple_element.cc: Change to compile-only
++	test.
++	* testsuite/20_util/tuple/tuple_element_t.cc: New.
++
+ 2014-04-22  Release Manager
+ 
+ 	* GCC 4.9.0 released.
+Index: libstdc++-v3/testsuite/experimental/optional/relops/1.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/optional/relops/1.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/optional/relops/1.cc	(.../branches/gcc-4_9-branch)
+@@ -37,10 +37,6 @@
+   { return std::tie(lhs.i, lhs.s) == std::tie(rhs.i, rhs.s); }
+ 
+   bool
+-  operator!=(value_type const& lhs, value_type const& rhs)
+-  { return !(lhs == rhs); }
+-
+-  bool
+   operator<(value_type const& lhs, value_type const& rhs)
+   { return std::tie(lhs.i, lhs.s) < std::tie(rhs.i, rhs.s); }
+ 
+Index: libstdc++-v3/testsuite/experimental/optional/relops/2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/optional/relops/2.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/optional/relops/2.cc	(.../branches/gcc-4_9-branch)
+@@ -37,10 +37,6 @@
+   { return std::tie(lhs.i, lhs.s) == std::tie(rhs.i, rhs.s); }
+ 
+   bool
+-  operator!=(value_type const& lhs, value_type const& rhs)
+-  { return !(lhs == rhs); }
+-
+-  bool
+   operator<(value_type const& lhs, value_type const& rhs)
+   { return std::tie(lhs.i, lhs.s) < std::tie(rhs.i, rhs.s); }
+ 
+Index: libstdc++-v3/testsuite/experimental/optional/relops/3.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/optional/relops/3.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/optional/relops/3.cc	(.../branches/gcc-4_9-branch)
+@@ -37,10 +37,6 @@
+   { return std::tie(lhs.i, lhs.s) == std::tie(rhs.i, rhs.s); }
+ 
+   bool
+-  operator!=(value_type const& lhs, value_type const& rhs)
+-  { return !(lhs == rhs); }
+-
+-  bool
+   operator<(value_type const& lhs, value_type const& rhs)
+   { return std::tie(lhs.i, lhs.s) < std::tie(rhs.i, rhs.s); }
+ 
+Index: libstdc++-v3/testsuite/experimental/optional/relops/4.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/optional/relops/4.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/optional/relops/4.cc	(.../branches/gcc-4_9-branch)
+@@ -37,10 +37,6 @@
+   { return std::tie(lhs.i, lhs.s) == std::tie(rhs.i, rhs.s); }
+ 
+   bool
+-  operator!=(value_type const& lhs, value_type const& rhs)
+-  { return !(lhs == rhs); }
+-
+-  bool
+   operator<(value_type const& lhs, value_type const& rhs)
+   { return std::tie(lhs.i, lhs.s) < std::tie(rhs.i, rhs.s); }
+ 
+Index: libstdc++-v3/testsuite/experimental/optional/relops/5.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/optional/relops/5.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/optional/relops/5.cc	(.../branches/gcc-4_9-branch)
+@@ -37,10 +37,6 @@
+   { return std::tie(lhs.i, lhs.s) == std::tie(rhs.i, rhs.s); }
+ 
+   bool
+-  operator!=(value_type const& lhs, value_type const& rhs)
+-  { return !(lhs == rhs); }
+-
+-  bool
+   operator<(value_type const& lhs, value_type const& rhs)
+   { return std::tie(lhs.i, lhs.s) < std::tie(rhs.i, rhs.s); }
+ 
+Index: libstdc++-v3/testsuite/experimental/optional/relops/6.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/optional/relops/6.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/optional/relops/6.cc	(.../branches/gcc-4_9-branch)
+@@ -37,10 +37,6 @@
+   { return std::tie(lhs.i, lhs.s) == std::tie(rhs.i, rhs.s); }
+ 
+   bool
+-  operator!=(value_type const& lhs, value_type const& rhs)
+-  { return !(lhs == rhs); }
+-
+-  bool
+   operator<(value_type const& lhs, value_type const& rhs)
+   { return std::tie(lhs.i, lhs.s) < std::tie(rhs.i, rhs.s); }
+ 
+Index: libstdc++-v3/testsuite/20_util/tuple/tuple_element.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/tuple/tuple_element.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/tuple/tuple_element.cc	(.../branches/gcc-4_9-branch)
+@@ -1,4 +1,5 @@
+-// { dg-options "-std=gnu++0x" }
++// { dg-options "-std=gnu++11" }
++// { dg-do compile }
+ 
+ // Copyright (C) 2007-2014 Free Software Foundation, Inc.
+ //
+Index: libstdc++-v3/testsuite/20_util/tuple/tuple_element_t.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/tuple/tuple_element_t.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/tuple/tuple_element_t.cc	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,36 @@
++// { dg-options "-std=gnu++14" }
++// { dg-do compile }
++
++// Copyright (C) 2014 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <tuple>
++
++using namespace std;
++
++struct foo
++{ };
++
++int
++main()
++{
++  // As foo isn't constructible from anything else, this
++  // lets us check if the alias is returning foo when it should
++  foo q1;
++  tuple_element_t<0,tuple<foo,void,int> > q2(q1);
++  tuple_element_t<2,tuple<void,int,foo> > q3(q1);
++}
+Index: libstdc++-v3/testsuite/20_util/tuple/60497.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,37 @@
++// { dg-options "-std=gnu++14" }
++// { dg-do compile }
++
++// Copyright (C) 2014 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// libstdc++/60497
++
++#include <tuple>
++
++struct A;
++template<typename T> struct B { T t; };
++
++using element_type = B<A>*;
++using tuple_type = std::tuple<element_type>;
++
++tuple_type t;
++const tuple_type ct;
++
++auto a = std::get<0>(t);
++auto b = std::get<0>(ct);
++auto c = std::get<element_type>(t);
++auto d = std::get<element_type>(ct);
+Index: libgcc/ChangeLog
+===================================================================
+--- a/src/libgcc/ChangeLog	(.../tags/gcc_4_9_0_release)
++++ b/src/libgcc/ChangeLog	(.../branches/gcc-4_9-branch)
+@@ -1,3 +1,10 @@
++2014-04-30  Bernd Edlinger  <bernd.edlinger@hotmail.de>
++
++	Work around for current cygwin32 build problems.
++	* config/i386/cygming-crtbegin.c (__register_frame_info,
++	__deregister_frame_info, _Jv_RegisterClasses): Compile weak default
++	functions only for 64-bit systems.
++
+ 2014-04-22  Release Manager
+ 
+ 	* GCC 4.9.0 released.
+Index: libgcc/config/i386/cygming-crtbegin.c
+===================================================================
+--- a/src/libgcc/config/i386/cygming-crtbegin.c	(.../tags/gcc_4_9_0_release)
++++ b/src/libgcc/config/i386/cygming-crtbegin.c	(.../branches/gcc-4_9-branch)
+@@ -54,6 +54,11 @@
+ 				   TARGET_ATTRIBUTE_WEAK;
+ extern void *__deregister_frame_info (__attribute__((unused)) const void *)
+ 				      TARGET_ATTRIBUTE_WEAK;
++
++/* Work around for current cygwin32 build problems (Bug gas/16858).
++   Compile weak default functions only for 64-bit systems,
++   when absolutely necessary.  */
++#ifdef __x86_64__
+ TARGET_ATTRIBUTE_WEAK void
+ __register_frame_info (__attribute__((unused)) const void *p,
+ 		       __attribute__((unused)) struct object *o)
+@@ -65,6 +70,7 @@
+ {
+   return (void*) 0;
+ }
++#endif
+ #endif /* DWARF2_UNWIND_INFO */
+ 
+ #if TARGET_USE_JCR_SECTION
+@@ -71,10 +77,12 @@
+ extern void _Jv_RegisterClasses (__attribute__((unused)) const void *)
+   TARGET_ATTRIBUTE_WEAK;
+ 
++#ifdef __x86_64__
+ TARGET_ATTRIBUTE_WEAK void
+ _Jv_RegisterClasses (__attribute__((unused)) const void *p)
+ {
+ }
++#endif
+ #endif /* TARGET_USE_JCR_SECTION */
+ 
+ #if defined(HAVE_LD_RO_RW_SECTION_MIXING)
 Index: gcc/tree-ssa-loop-im.c
 ===================================================================
 --- a/src/gcc/tree-ssa-loop-im.c	(.../tags/gcc_4_9_0_release)
@@ -765,7 +1106,35 @@ Index: gcc/DATESTAMP
 +++ b/src/gcc/DATESTAMP	(.../branches/gcc-4_9-branch)
 @@ -1 +1 @@
 -20140422
-+20140425
++20140502
+Index: gcc/tree-tailcall.c
+===================================================================
+--- a/src/gcc/tree-tailcall.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/tree-tailcall.c	(.../branches/gcc-4_9-branch)
+@@ -285,10 +285,20 @@
+     {
+       /* Reject a tailcall if the type conversion might need
+ 	 additional code.  */
+-      if (gimple_assign_cast_p (stmt)
+-	  && TYPE_MODE (TREE_TYPE (dest)) != TYPE_MODE (TREE_TYPE (src_var)))
+-	return false;
++      if (gimple_assign_cast_p (stmt))
++	{
++	  if (TYPE_MODE (TREE_TYPE (dest)) != TYPE_MODE (TREE_TYPE (src_var)))
++	    return false;
+ 
++	  /* Even if the type modes are the same, if the precision of the
++	     type is smaller than mode's precision,
++	     reduce_to_bit_field_precision would generate additional code.  */
++	  if (INTEGRAL_TYPE_P (TREE_TYPE (dest))
++	      && (GET_MODE_PRECISION (TYPE_MODE (TREE_TYPE (dest)))
++		  > TYPE_PRECISION (TREE_TYPE (dest))))
++	    return false;
++	}
++
+       if (src_var != *ass_var)
+ 	return false;
+ 
 Index: gcc/tree.h
 ===================================================================
 --- a/src/gcc/tree.h	(.../tags/gcc_4_9_0_release)
@@ -780,6 +1149,19 @@ Index: gcc/tree.h
  #define OMP_CLAUSE_ALIGNED_ALIGNMENT(NODE) \
    OMP_CLAUSE_OPERAND (OMP_CLAUSE_SUBCODE_CHECK (NODE, OMP_CLAUSE_ALIGNED), 1)
  
+Index: gcc/configure
+===================================================================
+--- a/src/gcc/configure	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/configure	(.../branches/gcc-4_9-branch)
+@@ -24497,7 +24497,7 @@
+        .align 4
+        smac %g2, %g3, %g1
+        umac %g2, %g3, %g1
+-       cas [%g2], %g3, %g1' > conftest.s
++       casa [%g2] 0xb, %g3, %g1' > conftest.s
+     if { ac_try='$gcc_cv_as $gcc_cv_as_flags -Aleon -o conftest.o conftest.s >&5'
+   { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+   (eval $ac_try) 2>&5
 Index: gcc/fold-const.c
 ===================================================================
 --- a/src/gcc/fold-const.c	(.../tags/gcc_4_9_0_release)
@@ -993,7 +1375,225 @@ Index: gcc/ChangeLog
 ===================================================================
 --- a/src/gcc/ChangeLog	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,223 @@
+@@ -1,3 +1,441 @@
++2014-05-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
++
++	Back port from mainline
++	2014-04-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
++
++	* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Check
++	TARGET_SIMD rather than TARGET_GENERAL_REGS_ONLY.
++	(TARGET_SIMD): Take AARCH64_ISA_SIMD into account.
++	(TARGET_FLOAT): Take AARCH64_ISA_FP into account.
++	(TARGET_CRYPTO): Take TARGET_SIMD into account.
++
++2014-04-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from mainline
++	2014-04-24  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	* doc/extend.texi (PowerPC Built-in Functions): Document new
++	powerpc extended divide, bcd, pack/unpack 128-bit, builtin
++	functions.
++	(PowerPC AltiVec/VSX Built-in Functions): Likewise.
++
++	* config/rs6000/predicates.md (const_0_to_3_operand): New
++	predicate to match 0..3 integer constants.
++
++	* config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros
++	to support adding miscellaneous builtin functions.
++	(BU_DFP_MISC_2): Likewise.
++	(BU_P7_MISC_1): Likewise.
++	(BU_P7_MISC_2): Likewise.
++	(BU_P8V_MISC_3): Likewise.
++	(BU_MISC_1): Likewise.
++	(BU_MISC_2): Likewise.
++	(DIVWE): Add extended divide builtin functions.
++	(DIVWEO): Likewise.
++	(DIVWEU): Likewise.
++	(DIVWEUO): Likewise.
++	(DIVDE): Likewise.
++	(DIVDEO): Likewise.
++	(DIVDEU): Likewise.
++	(DIVDEUO): Likewise.
++	(DXEX): Add decimal floating-point builtin functions.
++	(DXEXQ): Likewise.
++	(DDEDPD): Likewise.
++	(DDEDPDQ): Likewise.
++	(DENBCD): Likewise.
++	(DENBCDQ): Likewise.
++	(DIEX): Likewise.
++	(DIEXQ): Likewise.
++	(DSCLI): Likewise.
++	(DSCLIQ): Likewise.
++	(DSCRI): Likewise.
++	(DSCRIQ): Likewise.
++	(CDTBCD): Add new BCD builtin functions.
++	(CBCDTD): Likewise.
++	(ADDG6S): Likewise.
++	(BCDADD): Likewise.
++	(BCDADD_LT): Likewise.
++	(BCDADD_EQ): Likewise.
++	(BCDADD_GT): Likewise.
++	(BCDADD_OV): Likewise.
++	(BCDSUB): Likewise.
++	(BCDSUB_LT): Likewise.
++	(BCDSUB_EQ): Likewise.
++	(BCDSUB_GT): Likewise.
++	(BCDSUB_OV): Likewise.
++	(PACK_TD): Add new pack/unpack 128-bit type builtin functions.
++	(UNPACK_TD): Likewise.
++	(PACK_TF): Likewise.
++	(UNPACK_TF): Likewise.
++	(UNPACK_TF_0): Likewise.
++	(UNPACK_TF_1): Likewise.
++	(PACK_V1TI): Likewise.
++	(UNPACK_V1TI): Likewise.
++
++	* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
++	support for decimal floating point builtin functions.
++	(rs6000_expand_ternop_builtin): Add checks for the new builtin
++	functions that take constant arguments.
++	(rs6000_invalid_builtin): Add decimal floating point builtin
++	support.
++	(rs6000_init_builtins): Setup long double, _Decimal64, and
++	_Decimal128 types for new builtin functions.
++	(builtin_function_type): Set the unsigned flags appropriately for
++	the new builtin functions.
++	(rs6000_opt_masks): Add support for decimal floating point builtin
++	functions.
++
++	* config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal
++	floating point builtin functions.
++	(RS6000_BTM_COMMON): Likewise.
++	(RS6000_BTI_long_double): Likewise.
++	(RS6000_BTI_dfloat64): Likewise.
++	(RS6000_BTI_dfloat128): Likewise.
++	(long_double_type_internal_node): Likewise.
++	(dfloat64_type_internal_node): Likewise.
++	(dfloat128_type_internal_node): Likewise.
++
++	* config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA
++	2.07 bcd arithmetic instructions.
++	(UNSPEC_BCDSUB): Likewise.
++	(UNSPEC_BCD_OVERFLOW): Likewise.
++	(UNSPEC_BCD_ADD_SUB): Likewise.
++	(bcd_add_sub): Likewise.
++	(BCD_TEST): Likewise.
++	(bcd<bcd_add_sub>): Likewise.
++	(bcd<bcd_add_sub>_test): Likewise.
++	(bcd<bcd_add_sub>_test2): Likewise.
++	(bcd<bcd_add_sub>_<code>): Likewise.
++	(peephole2 for combined bcd ops): Likewise.
++
++	* config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new
++	decimal floating point builtin functions.
++	(UNSPEC_DENBCD): Likewise.
++	(UNSPEC_DXEX): Likewise.
++	(UNSPEC_DIEX): Likewise.
++	(UNSPEC_DSCLI): Likewise.
++	(UNSPEC_DSCRI): Likewise.
++	(D64_D128): Likewise.
++	(dfp_suffix): Likewise.
++	(dfp_ddedpd_<mode>): Likewise.
++	(dfp_denbcd_<mode>): Likewise.
++	(dfp_dxex_<mode>): Likewise.
++	(dfp_diex_<mode>): Likewise.
++	(dfp_dscli_<mode>): Likewise.
++	(dfp_dscri_<mode>): Likewise.
++
++	* config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD
++	builtin functions.
++	(UNSPEC_CDTBCD): Likewise.
++	(UNSPEC_CBCDTD): Likewise.
++	(UNSPEC_DIVE): Add support for new extended divide builtin
++	functions.
++	(UNSPEC_DIVEO): Likewise.
++	(UNSPEC_DIVEU): Likewise.
++	(UNSPEC_DIVEUO): Likewise.
++	(UNSPEC_UNPACK_128BIT): Add support for new builtin functions to
++	pack/unpack 128-bit types.
++	(UNSPEC_PACK_128BIT): Likewise.
++	(idiv_ldiv): New mode attribute to set the 32/64-bit divide type.
++	(udiv<mode>3): Use idiv_ldiv mode attribute.
++	(div<mode>3): Likewise.
++	(addg6s): Add new BCD builtin functions.
++	(cdtbcd): Likewise.
++	(cbcdtd): Likewise.
++	(UNSPEC_DIV_EXTEND): Add support for new extended divide
++	instructions.
++	(div_extend): Likewise.
++	(div<div_extend>_<mode>"): Likewise.
++	(FP128_64): Add support for new builtin functions to pack/unpack
++	128-bit types.
++	(unpack<mode>): Likewise.
++	(unpacktf_0): Likewise.
++	(unpacktf_1): Likewise.
++	(unpack<mode>_dm): Likewise.
++	(unpack<mode>_nodm): Likewise.
++	(pack<mode>): Likewise.
++	(unpackv1ti): Likewise.
++	(packv1ti): Likewise.
++
++2014-04-29  Pat Haugen  <pthaugen@us.ibm.com>
++
++	Backport from mainline
++	2014-04-17  Pat Haugen  <pthaugen@us.ibm.com>
++
++	* config/rs6000/rs6000.md (addti3, subti3): New.
++
++2014-04-29  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/60971
++	* tree-tailcall.c (process_assignment): Reject conversions which
++	reduce precision.
++
++2014-04-29  Nick Clifton  <nickc@redhat.com>
++
++	* config/msp430/msp430.md (umulsidi): Fix typo.
++	(mulhisi3): Enable even inside interrupt handlers.
++	* config/msp430/msp430.c (msp430_print_operand): %O: Allow for the
++	bigger return address pushed in large mode.
++
++2014-04-28  Pat Haugen  <pthaugen@us.ibm.com>
++
++	* config/rs6000/sync.md (AINT mode_iterator): Move definition.
++	(loadsync_<mode>): Change mode.
++	(load_quadpti, store_quadpti): New.
++	(atomic_load<mode>, atomic_store<mode>): Add support for TI mode.
++	* config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.
++
++2014-04-28  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* configure.ac: Tweak GAS check for LEON instructions on SPARC.
++	* configure: Regenerate.
++	* config/sparc/sparc.opt (muser-mode): New option.
++	* config/sparc/sync.md (atomic_compare_and_swap<mode>_1): Do not enable
++	for LEON3.
++	(atomic_compare_and_swap_leon3_1): New instruction for LEON3.
++	* doc/invoke.texi (SPARC options): Document -muser-mode.
++
++2014-04-26  Markus Trippelsdorf  <markus@trippelsdorf.de>
++
++	* doc/install.texi (Building with profile feedback): Remove
++	outdated sentence.
++
++2014-04-26  Tom de Vries  <tom@codesourcery.com>
++
++	* config/i386/i386.md (define_expand "ldexpxf3"): Fix out-of-bounds
++	array accesses.
++
++2014-04-25  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/60960
++	* tree-vect-generic.c (expand_vector_operation): Only call
++	expand_vector_divmod if type's mode satisfies VECTOR_MODE_P.
++
++2014-04-25  Eric Botcazou  <ebotcazou@adacore.com>
++
++	PR target/60941
++	* config/sparc/sparc.md (ashlsi3_extend): Delete.
++
 +2014-04-25  Richard Biener  <rguenther@suse.de>
 +
 +	PR ipa/60912
@@ -1217,7 +1817,7 @@ Index: gcc/ChangeLog
  2014-04-22  Release Manager
  
  	* GCC 4.9.0 released.
-@@ -59,8 +284,7 @@
+@@ -59,8 +502,7 @@
  2014-04-11  Tobias Burnus  <burnus@net-b.de>
  
  	PR other/59055
@@ -1227,7 +1827,7 @@ Index: gcc/ChangeLog
  	* doc/gcc.texi (Service): Update description in the @menu
  	* doc/invoke.texi (Option Summary): Remove misplaced and
  	duplicated @menu.
-@@ -86,15 +310,14 @@
+@@ -86,15 +528,14 @@
  2014-04-11  Jakub Jelinek  <jakub@redhat.com>
  
  	PR rtl-optimization/60663
@@ -1246,7 +1846,7 @@ Index: gcc/ChangeLog
  
  2014-04-10  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
  
-@@ -212,9 +435,10 @@
+@@ -212,9 +653,10 @@
  
  2014-04-05  Pitchumani Sivanupandi  <Pitchumani.S@atmel.com>
  
@@ -1260,7 +1860,7 @@ Index: gcc/ChangeLog
  	* config/avr/avr-c.c (avr_cpu_cpp_builtins): use dev_attribute to check
  	errata_skip. Add __AVR_ISA_RMW__ builtin macro if RMW ISA available.
  	* config/avr/avr-devices.c (avr_mcu_types): Update AVR_MCU macro for
-@@ -282,21 +506,21 @@
+@@ -282,21 +724,21 @@
  2014-04-04  Martin Jambor  <mjambor@suse.cz>
  
  	PR ipa/60640
@@ -1293,7 +1893,7 @@ Index: gcc/ChangeLog
  	moved setting of a lot of flags to set_new_clone_decl_and_node_flags.
  
  2014-04-04  Jeff Law  <law@redhat.com>
-@@ -334,8 +558,8 @@
+@@ -334,8 +776,8 @@
  
  	PR tree-optimization/60505
  	* tree-vectorizer.h (struct _stmt_vec_info): Add th field as the
@@ -1304,7 +1904,7 @@ Index: gcc/ChangeLog
  	* tree-vect-loop.c (new_loop_vec_info):
  	Initialize LOOP_VINFO_COST_MODEL_THRESHOLD.
  	* tree-vect-loop.c (vect_analyze_loop_operations):
-@@ -347,8 +571,7 @@
+@@ -347,8 +789,7 @@
  
  2014-04-03  Richard Biener  <rguenther@suse.de>
  
@@ -1314,7 +1914,7 @@ Index: gcc/ChangeLog
  	(streamer_tree_cache_create): Adjust.
  	* tree-streamer.c (streamer_tree_cache_add_to_node_array): Adjust
  	to allow optional nodes array.
-@@ -359,8 +582,7 @@
+@@ -359,8 +800,7 @@
  	* lto-streamer-out.c (create_output_block): Avoid maintaining
  	the node array in the writer cache.
  	(DFS_write_tree): Remove assertion.
@@ -1324,7 +1924,7 @@ Index: gcc/ChangeLog
  	* lto-streamer-in.c (lto_data_in_create): Adjust for
  	streamer_tree_cache_create prototype change.
  
-@@ -381,24 +603,6 @@
+@@ -381,24 +821,6 @@
  	(Weffc++): Remove Scott's numbering, merge lists and reference
  	Wnon-virtual-dtor.
  
@@ -1349,7 +1949,7 @@ Index: gcc/ChangeLog
  2014-04-03  Nick Clifton  <nickc@redhat.com>
  
  	* config/rl78/rl78-expand.md (movqi): Handle (SUBREG (SYMBOL_REF))
-@@ -414,8 +618,8 @@
+@@ -414,8 +836,8 @@
  2014-04-02  Jan Hubicka  <hubicka@ucw.cz>
  
  	PR ipa/60659
@@ -1360,7 +1960,7 @@ Index: gcc/ChangeLog
  	(possible_polymorphic_call_targets): For inconsistent contexts
  	return empty complete list.
  
-@@ -519,8 +723,7 @@
+@@ -519,8 +941,7 @@
  
  2014-04-01  Richard Biener  <rguenther@suse.de>
  
@@ -1370,6 +1970,224 @@ Index: gcc/ChangeLog
  
  2014-04-01  Sebastian Huber  <sebastian.huber@embedded-brains.de>
  
+Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,88 @@
++/* { dg-do compile { target { powerpc*-*-linux* } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target powerpc_vsx_ok } */
++/* { dg-options "-mcpu=power7 -O2" } */
++/* { dg-final { scan-assembler-times "ddedpd " 4    } } */
++/* { dg-final { scan-assembler-times "denbcd " 2    } } */
++/* { dg-final { scan-assembler-times "dxex "   1    } } */
++/* { dg-final { scan-assembler-times "diex "   1    } } */
++/* { dg-final { scan-assembler-times "dscli "  2    } } */
++/* { dg-final { scan-assembler-times "dscri "  2    } } */
++/* { dg-final { scan-assembler-not   "bl __builtin" } } */
++/* { dg-final { scan-assembler-not   "dctqpq"       } } */
++/* { dg-final { scan-assembler-not   "drdpq"        } } */
++/* { dg-final { scan-assembler-not   "stfd"         } } */
++/* { dg-final { scan-assembler-not   "lfd"          } } */
++
++_Decimal64
++do_dedpd_0 (_Decimal64 a)
++{
++  return __builtin_ddedpd (0, a);
++}
++
++_Decimal64
++do_dedpd_1 (_Decimal64 a)
++{
++  return __builtin_ddedpd (1, a);
++}
++
++_Decimal64
++do_dedpd_2 (_Decimal64 a)
++{
++  return __builtin_ddedpd (2, a);
++}
++
++_Decimal64
++do_dedpd_3 (_Decimal64 a)
++{
++  return __builtin_ddedpd (3, a);
++}
++
++_Decimal64
++do_enbcd_0 (_Decimal64 a)
++{
++  return __builtin_denbcd (0, a);
++}
++
++_Decimal64
++do_enbcd_1 (_Decimal64 a)
++{
++  return __builtin_denbcd (1, a);
++}
++
++_Decimal64
++do_xex (_Decimal64 a)
++{
++  return __builtin_dxex (a);
++}
++
++_Decimal64
++do_iex (_Decimal64 a, _Decimal64 b)
++{
++  return __builtin_diex (a, b);
++}
++
++_Decimal64
++do_scli_1 (_Decimal64 a)
++{
++  return __builtin_dscli (a, 1);
++}
++
++_Decimal64
++do_scli_10 (_Decimal64 a)
++{
++  return __builtin_dscli (a, 10);
++}
++
++_Decimal64
++do_scri_1 (_Decimal64 a)
++{
++  return __builtin_dscri (a, 1);
++}
++
++_Decimal64
++do_scri_10 (_Decimal64 a)
++{
++  return __builtin_dscri (a, 10);
++}
+Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,88 @@
++/* { dg-do compile { target { powerpc*-*-linux* } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target powerpc_vsx_ok } */
++/* { dg-options "-mcpu=power7 -O2" } */
++/* { dg-final { scan-assembler-times "ddedpdq " 4    } } */
++/* { dg-final { scan-assembler-times "denbcdq " 2    } } */
++/* { dg-final { scan-assembler-times "dxexq "   1    } } */
++/* { dg-final { scan-assembler-times "diexq "   1    } } */
++/* { dg-final { scan-assembler-times "dscliq "  2    } } */
++/* { dg-final { scan-assembler-times "dscriq "  2    } } */
++/* { dg-final { scan-assembler-not    "bl __builtin" } } */
++/* { dg-final { scan-assembler-not   "dctqpq"        } } */
++/* { dg-final { scan-assembler-not   "drdpq"         } } */
++/* { dg-final { scan-assembler-not   "stfd"          } } */
++/* { dg-final { scan-assembler-not   "lfd"           } } */
++
++_Decimal128
++do_dedpdq_0 (_Decimal128 a)
++{
++  return __builtin_ddedpdq (0, a);
++}
++
++_Decimal128
++do_dedpdq_1 (_Decimal128 a)
++{
++  return __builtin_ddedpdq (1, a);
++}
++
++_Decimal128
++do_dedpdq_2 (_Decimal128 a)
++{
++  return __builtin_ddedpdq (2, a);
++}
++
++_Decimal128
++do_dedpdq_3 (_Decimal128 a)
++{
++  return __builtin_ddedpdq (3, a);
++}
++
++_Decimal128
++do_enbcdq_0 (_Decimal128 a)
++{
++  return __builtin_denbcdq (0, a);
++}
++
++_Decimal128
++do_enbcdq_1 (_Decimal128 a)
++{
++  return __builtin_denbcdq (1, a);
++}
++
++_Decimal128
++do_xexq (_Decimal128 a)
++{
++  return __builtin_dxexq (a);
++}
++
++_Decimal128
++do_iexq (_Decimal128 a, _Decimal128 b)
++{
++  return __builtin_diexq (a, b);
++}
++
++_Decimal128
++do_scliq_1 (_Decimal128 a)
++{
++  return __builtin_dscliq (a, 1);
++}
++
++_Decimal128
++do_scliq_10 (_Decimal128 a)
++{
++  return __builtin_dscliq (a, 10);
++}
++
++_Decimal128
++do_scriq_1 (_Decimal128 a)
++{
++  return __builtin_dscriq (a, 1);
++}
++
++_Decimal128
++do_scriq_10 (_Decimal128 a)
++{
++  return __builtin_dscriq (a, 10);
++}
+Index: gcc/testsuite/gcc.target/powerpc/bcd-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,27 @@
++/* { dg-do compile { target { powerpc*-*-linux* } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target powerpc_vsx_ok } */
++/* { dg-options "-mcpu=power7 -O2" } */
++/* { dg-final { scan-assembler-times "cdtbcd " 1 } } */
++/* { dg-final { scan-assembler-times "cbcdtd " 1 } } */
++/* { dg-final { scan-assembler-times "addg6s " 1 } } */
++/* { dg-final { scan-assembler-not    "bl __builtin" } } */
++
++unsigned int
++to_bcd (unsigned int a)
++{
++  return __builtin_cdtbcd (a);
++}
++
++unsigned int
++from_bcd (unsigned int a)
++{
++  return __builtin_cbcdtd (a);
++}
++
++unsigned int
++bcd_arith (unsigned int a, unsigned int b)
++{
++  return __builtin_addg6s (a, b);
++}
 Index: gcc/testsuite/gcc.target/powerpc/pr60735.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.target/powerpc/pr60735.c	(.../tags/gcc_4_9_0_release)
@@ -1386,6 +2204,633 @@ Index: gcc/testsuite/gcc.target/powerpc/pr60735.c
 +{
 +  *p = *q;
 +}
+Index: gcc/testsuite/gcc.target/powerpc/extend-divide-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,34 @@
++/* { dg-do compile { target { powerpc*-*-linux* } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target powerpc_vsx_ok } */
++/* { dg-options "-mcpu=power7 -O2" } */
++/* { dg-final { scan-assembler-times "divwe "   1 } } */
++/* { dg-final { scan-assembler-times "divweo "  1 } } */
++/* { dg-final { scan-assembler-times "divweu "  1 } } */
++/* { dg-final { scan-assembler-times "divweuo " 1 } } */
++/* { dg-final { scan-assembler-not    "bl __builtin" } } */
++
++int
++div_we (int a, int b)
++{
++  return __builtin_divwe (a, b);
++}
++
++int
++div_weo (int a, int b)
++{
++  return __builtin_divweo (a, b);
++}
++
++unsigned int
++div_weu (unsigned int a, unsigned int b)
++{
++  return __builtin_divweu (a, b);
++}
++
++unsigned int
++div_weuo (unsigned int a, unsigned int b)
++{
++  return __builtin_divweuo (a, b);
++}
+Index: gcc/testsuite/gcc.target/powerpc/bcd-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,44 @@
++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target powerpc_p8vector_ok } */
++/* { dg-options "-mcpu=power8 -O2" } */
++/* { dg-final { scan-assembler-times "bcdadd\[.\] " 2 } } */
++/* { dg-final { scan-assembler-times "bcdsub\[.\] " 2 } } */
++/* { dg-final { scan-assembler-not   "bl __builtin"   } } */
++/* { dg-final { scan-assembler-not   "mtvsr"   	      } } */
++/* { dg-final { scan-assembler-not   "mfvsr"   	      } } */
++/* { dg-final { scan-assembler-not   "lvx"     	      } } */
++/* { dg-final { scan-assembler-not   "lxvw4x"  	      } } */
++/* { dg-final { scan-assembler-not   "lxvd2x"  	      } } */
++/* { dg-final { scan-assembler-not   "stvx"    	      } } */
++/* { dg-final { scan-assembler-not   "stxvw4x" 	      } } */
++/* { dg-final { scan-assembler-not   "stxvd2x" 	      } } */
++
++typedef __int128_t __attribute__((__vector_size__(16)))	vector_128_t;
++typedef __int128_t					scalar_128_t;
++typedef	unsigned long long				scalar_64_t;
++
++vector_128_t
++do_add_0 (vector_128_t a, vector_128_t b)
++{
++  return __builtin_bcdadd (a, b, 0);
++}
++
++vector_128_t
++do_add_1 (vector_128_t a, vector_128_t b)
++{
++  return __builtin_bcdadd (a, b, 1);
++}
++
++vector_128_t
++do_sub_0 (vector_128_t a, vector_128_t b)
++{
++  return __builtin_bcdsub (a, b, 0);
++}
++
++vector_128_t
++do_sub_1 (vector_128_t a, vector_128_t b)
++{
++  return __builtin_bcdsub (a, b, 1);
++}
+Index: gcc/testsuite/gcc.target/powerpc/extend-divide-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,34 @@
++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target powerpc_vsx_ok } */
++/* { dg-options "-mcpu=power7 -O2" } */
++/* { dg-final { scan-assembler-times "divde "   1 } } */
++/* { dg-final { scan-assembler-times "divdeo "  1 } } */
++/* { dg-final { scan-assembler-times "divdeu "  1 } } */
++/* { dg-final { scan-assembler-times "divdeuo " 1 } } */
++/* { dg-final { scan-assembler-not    "bl __builtin" } } */
++
++long
++div_de (long a, long b)
++{
++  return __builtin_divde (a, b);
++}
++
++long
++div_deo (long a, long b)
++{
++  return __builtin_divdeo (a, b);
++}
++
++unsigned long
++div_deu (unsigned long a, unsigned long b)
++{
++  return __builtin_divdeu (a, b);
++}
++
++unsigned long
++div_deuo (unsigned long a, unsigned long b)
++{
++  return __builtin_divdeuo (a, b);
++}
+Index: gcc/testsuite/gcc.target/powerpc/pack01.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pack01.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pack01.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,91 @@
++/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target p8vector_hw } */
++/* { dg-options "-mcpu=power8 -O2" } */
++
++#include <stddef.h>
++#include <stdlib.h>
++#include <altivec.h>
++
++#ifdef DEBUG
++#include <stdio.h>
++#endif
++
++typedef __int128_t __attribute__((__vector_size__(16)))	vector_128_t;
++typedef __int128_t					scalar_128_t;
++typedef	unsigned long long				scalar_64_t;
++
++volatile scalar_64_t one = 1;
++volatile scalar_64_t two = 2;
++
++int
++main (void)
++{
++  scalar_128_t a = (((scalar_128_t)one) << 64) | ((scalar_128_t)two);
++  vector_128_t v1 = (vector_128_t) { a };
++  vector_128_t v2 = __builtin_pack_vector_int128 (one, two);
++  scalar_64_t x0 = __builtin_unpack_vector_int128 (v1, 0);
++  scalar_64_t x1 = __builtin_unpack_vector_int128 (v1, 1);
++  vector_128_t v3 = __builtin_pack_vector_int128 (x0, x1);
++
++  size_t i;
++  union {
++    scalar_128_t i128;
++    vector_128_t v128;
++    scalar_64_t u64;
++    unsigned char uc[sizeof (scalar_128_t)];
++    char c[sizeof (scalar_128_t)];
++  } u, u2;
++
++#ifdef DEBUG
++  {
++    printf ("a  = 0x");
++    u.i128 = a;
++    for (i = 0; i < sizeof (scalar_128_t); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf ("\nv1 = 0x");
++    u.v128 = v1;
++    for (i = 0; i < sizeof (scalar_128_t); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf ("\nv2 = 0x");
++    u.v128 = v2;
++    for (i = 0; i < sizeof (scalar_128_t); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf ("\nv3 = 0x");
++    u.v128 = v3;
++    for (i = 0; i < sizeof (scalar_128_t); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf ("\nx0 = 0x");
++    u.u64 = x0;
++    for (i = 0; i < sizeof (scalar_64_t); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf ("\nx1 = 0x");
++    u.u64 = x1;
++    for (i = 0; i < sizeof (scalar_64_t); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf ("\n");
++  }
++#endif
++
++  u2.i128 = a;
++  u.v128 = v1;
++  if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)
++    abort ();
++
++  u.v128 = v2;
++  if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)
++    abort ();
++
++  u.v128 = v3;
++  if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)
++    abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/bcd-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,103 @@
++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target powerpc_p8vector_ok } */
++/* { dg-options "-mcpu=power8 -O2" } */
++/* { dg-final { scan-assembler-times "bcdadd\[.\] " 4 } } */
++/* { dg-final { scan-assembler-times "bcdsub\[.\] " 4 } } */
++/* { dg-final { scan-assembler-not   "bl __builtin"   } } */
++/* { dg-final { scan-assembler-not   "mtvsr"   	      } } */
++/* { dg-final { scan-assembler-not   "mfvsr"   	      } } */
++/* { dg-final { scan-assembler-not   "lvx"     	      } } */
++/* { dg-final { scan-assembler-not   "lxvw4x"  	      } } */
++/* { dg-final { scan-assembler-not   "lxvd2x"  	      } } */
++/* { dg-final { scan-assembler-not   "stvx"    	      } } */
++/* { dg-final { scan-assembler-not   "stxvw4x" 	      } } */
++/* { dg-final { scan-assembler-not   "stxvd2x" 	      } } */
++
++typedef __int128_t __attribute__((__vector_size__(16)))	vector_128_t;
++typedef __int128_t					scalar_128_t;
++typedef	unsigned long long				scalar_64_t;
++
++/* Test whether the peephole works to allow folding a bcdadd, with a
++   bcdadd_<test> into a single instruction.  */
++
++vector_128_t
++do_add_lt (vector_128_t a, vector_128_t b, int *p)
++{
++  vector_128_t ret = __builtin_bcdadd (a, b, 0);
++  if (__builtin_bcdadd_lt (a, b, 0))
++    *p = 1;
++
++  return ret;
++}
++
++vector_128_t
++do_add_eq (vector_128_t a, vector_128_t b, int *p)
++{
++  vector_128_t ret = __builtin_bcdadd (a, b, 0);
++  if (__builtin_bcdadd_eq (a, b, 0))
++    *p = 1;
++
++  return ret;
++}
++
++vector_128_t
++do_add_gt (vector_128_t a, vector_128_t b, int *p)
++{
++  vector_128_t ret = __builtin_bcdadd (a, b, 0);
++  if (__builtin_bcdadd_gt (a, b, 0))
++    *p = 1;
++
++  return ret;
++}
++
++vector_128_t
++do_add_ov (vector_128_t a, vector_128_t b, int *p)
++{
++  vector_128_t ret = __builtin_bcdadd (a, b, 0);
++  if (__builtin_bcdadd_ov (a, b, 0))
++    *p = 1;
++
++  return ret;
++}
++
++vector_128_t
++do_sub_lt (vector_128_t a, vector_128_t b, int *p)
++{
++  vector_128_t ret = __builtin_bcdsub (a, b, 0);
++  if (__builtin_bcdsub_lt (a, b, 0))
++    *p = 1;
++
++  return ret;
++}
++
++vector_128_t
++do_sub_eq (vector_128_t a, vector_128_t b, int *p)
++{
++  vector_128_t ret = __builtin_bcdsub (a, b, 0);
++  if (__builtin_bcdsub_eq (a, b, 0))
++    *p = 1;
++
++  return ret;
++}
++
++vector_128_t
++do_sub_gt (vector_128_t a, vector_128_t b, int *p)
++{
++  vector_128_t ret = __builtin_bcdsub (a, b, 0);
++  if (__builtin_bcdsub_gt (a, b, 0))
++    *p = 1;
++
++  return ret;
++}
++
++vector_128_t
++do_sub_ov (vector_128_t a, vector_128_t b, int *p)
++{
++  vector_128_t ret = __builtin_bcdsub (a, b, 0);
++  if (__builtin_bcdsub_ov (a, b, 0))
++    *p = 1;
++
++  return ret;
++}
+Index: gcc/testsuite/gcc.target/powerpc/pack02.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pack02.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pack02.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,95 @@
++/* { dg-do run { target { powerpc*-*-linux* } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target vsx_hw } */
++/* { dg-options "-O2" } */
++
++#include <stddef.h>
++#include <stdlib.h>
++#include <math.h>
++
++#ifdef DEBUG
++#include <stdio.h>
++#endif
++
++int
++main (void)
++{
++  double high = pow (2.0, 60);
++  double low  = 2.0;
++  long double a = ((long double)high) + ((long double)low);
++  double x0 = __builtin_unpack_longdouble (a, 0);
++  double x1 = __builtin_unpack_longdouble (a, 1);
++  long double b = __builtin_pack_longdouble (x0, x1);
++
++#ifdef DEBUG
++  {
++    size_t i;
++    union {
++      long double ld;
++      double d;
++      unsigned char uc[sizeof (long double)];
++      char c[sizeof (long double)];
++    } u;
++
++    printf ("a  = 0x");
++    u.ld = a;
++    for (i = 0; i < sizeof (long double); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf (", %Lg\n", a);
++
++    printf ("b  = 0x");
++    u.ld = b;
++    for (i = 0; i < sizeof (long double); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf (", %Lg\n", b);
++
++    printf ("hi = 0x");
++    u.d = high;
++    for (i = 0; i < sizeof (double); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", high);
++
++    printf ("lo = 0x");
++    u.d = low;
++    for (i = 0; i < sizeof (double); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", low);
++
++    printf ("x0 = 0x");
++    u.d = x0;
++    for (i = 0; i < sizeof (double); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x0);
++
++    printf ("x1 = 0x");
++    u.d = x1;
++    for (i = 0; i < sizeof (double); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x1);
++  }
++#endif
++
++  if (high != x0)
++    abort ();
++
++  if (low != x1)
++    abort ();
++
++  if (a != b)
++    abort ();
++
++  if (x0 != high)
++    abort ();
++
++  if (x1 != low)
++    abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/pack03.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pack03.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pack03.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,88 @@
++/* { dg-do run { target { powerpc*-*-linux* } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
++/* { dg-require-effective-target vsx_hw } */
++/* { dg-options "-O2" } */
++
++#include <stddef.h>
++#include <stdlib.h>
++#include <math.h>
++
++#ifdef DEBUG
++#include <stdio.h>
++#endif
++
++int
++main (void)
++{
++  _Decimal128 one	= (_Decimal128)1.0;
++  _Decimal128 two	= (_Decimal128)2.0;
++  _Decimal128 ten	= (_Decimal128)10.0;
++  _Decimal128 a		= one;
++  _Decimal128 b;
++  _Decimal128 c;
++  unsigned long long x0;
++  unsigned long long x1;
++  size_t i;
++
++  for (i = 0; i < 25; i++)
++    a *= ten;
++
++  a += two;
++
++  x0 = __builtin_unpack_dec128 (a, 0);
++  x1 = __builtin_unpack_dec128 (a, 1);
++  b = __builtin_pack_dec128 (x0, x1);
++  c = __builtin_dscliq (one, 25) + two;
++
++#ifdef DEBUG
++  {
++    union {
++      _Decimal128 d;
++      unsigned long long ull;
++      unsigned char uc[sizeof (_Decimal128)];
++    } u;
++
++    printf ("a  = 0x");
++    u.d = a;
++    for (i = 0; i < sizeof (_Decimal128); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf (", %Lg\n", (long double)a);
++
++    printf ("b  = 0x");
++    u.d = b;
++    for (i = 0; i < sizeof (_Decimal128); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf (", %Lg\n", (long double)b);
++
++    printf ("c  = 0x");
++    u.d = c;
++    for (i = 0; i < sizeof (_Decimal128); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf (", %Lg\n", (long double)c);
++
++    printf ("x0 = 0x");
++    u.ull = x0;
++    for (i = 0; i < sizeof (unsigned long long); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf ("\nx1 = 0x");
++    u.ull = x1;
++    for (i = 0; i < sizeof (unsigned long long); i++)
++      printf ("%.2x", u.uc[i]);
++
++    printf ("\n");
++  }
++#endif
++
++  if (a != b)
++    abort ();
++
++  if (a != c)
++    abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/ti_math1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,20 @@
++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
++/* { dg-options "-O2" } */
++/* { dg-final { scan-assembler-times "addc" 1 } } */
++/* { dg-final { scan-assembler-times "adde" 1 } } */
++/* { dg-final { scan-assembler-times "subfc" 1 } } */
++/* { dg-final { scan-assembler-times "subfe" 1 } } */
++/* { dg-final { scan-assembler-not "subf " } } */
++
++__int128
++add_128 (__int128 *ptr, __int128 val)
++{
++	return (*ptr + val);
++}
++
++__int128
++sub_128 (__int128 *ptr, __int128 val)
++{
++	return (*ptr - val);
++}
++
+Index: gcc/testsuite/gcc.target/powerpc/ti_math2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,73 @@
++/* { dg-do run { target { powerpc*-*-* && lp64 } } } */
++/* { dg-options "-O2 -fno-inline" } */
++
++union U {
++  __int128 i128;
++  struct {
++    long l1;
++    long l2;
++  } s;
++};
++
++union U u1,u2;
++
++__int128
++create_128 (long most_sig, long least_sig)
++{
++  union U u;
++
++#if __LITTLE_ENDIAN__
++  u.s.l1 = least_sig;
++  u.s.l2 = most_sig;
++#else
++  u.s.l1 = most_sig;
++  u.s.l2 = least_sig;
++#endif
++  return u.i128;
++}
++
++long most_sig (union U * u)
++{
++#if __LITTLE_ENDIAN__
++  return (*u).s.l2;
++#else
++  return (*u).s.l1;
++#endif
++}
++
++long least_sig (union U * u)
++{
++#if __LITTLE_ENDIAN__
++  return (*u).s.l1;
++#else
++  return (*u).s.l2;
++#endif
++}
++
++__int128
++add_128 (__int128 *ptr, __int128 val)
++{
++	return (*ptr + val);
++}
++
++__int128
++sub_128 (__int128 *ptr, __int128 val)
++{
++	return (*ptr - val);
++}
++
++int
++main (void)
++{
++  /* Do a simple add/sub to make sure carry is happening between the dwords
++     and that dwords are in correct endian order. */
++  u1.i128 = create_128 (1, -1);
++  u2.i128 = add_128 (&u1.i128, 1);
++  if ((most_sig (&u2) != 2) || (least_sig (&u2) != 0))
++    __builtin_abort ();
++  u2.i128 = sub_128 (&u2.i128, 1);
++  if ((most_sig (&u2) != 1) || (least_sig (&u2) != -1))
++    __builtin_abort ();
++  return 0;
++}
++
 Index: gcc/testsuite/gcc.target/i386/vec-may_alias.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.target/i386/vec-may_alias.c	(.../tags/gcc_4_9_0_release)
@@ -1542,6 +2987,77 @@ Index: gcc/testsuite/gfortran.dg/finalize_25.f90
 +    i=s
 +  end subroutine ndm2
 +end program main
+Index: gcc/testsuite/gcc.c-torture/execute/20140425-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,23 @@
++/* PR target/60941 */
++/* Reported by Martin Husemann <martin@netbsd.org> */
++
++extern void abort (void);
++
++static void __attribute__((noinline))
++set (unsigned long *l)
++{
++  *l = 31;
++}
++
++int main (void)
++{
++  unsigned long l;
++  int i;
++
++  set (&l);
++  i = (int) l;
++  l = (unsigned long)(2U << i);
++  if (l != 0)
++    abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/execute/pr60960.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,38 @@
++/* PR tree-optimization/60960 */
++
++typedef unsigned char v4qi __attribute__ ((vector_size (4)));
++
++__attribute__((noinline, noclone)) v4qi
++f1 (v4qi v)
++{
++  return v / 2;
++}
++
++__attribute__((noinline, noclone)) v4qi
++f2 (v4qi v)
++{
++  return v / (v4qi) { 2, 2, 2, 2 };
++}
++
++__attribute__((noinline, noclone)) v4qi
++f3 (v4qi x, v4qi y)
++{
++  return x / y;
++}
++
++int
++main ()
++{
++  v4qi x = { 5, 5, 5, 5 };
++  v4qi y = { 2, 2, 2, 2 };
++  v4qi z = f1 (x);
++  if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)
++    __builtin_abort ();
++  z = f2 (x);
++  if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)
++    __builtin_abort ();
++  z = f3 (x, y);
++  if (__builtin_memcmp (&y, &z, sizeof (y)) != 0)
++    __builtin_abort ();
++  return 0;
++}
 Index: gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c	(.../tags/gcc_4_9_0_release)
@@ -1849,6 +3365,17 @@ Index: gcc/testsuite/gcc.dg/torture/pr60903.c
 +    }
 +  goto lbl;
 +}
+Index: gcc/testsuite/gcc.dg/tree-ssa/alias-30.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/alias-30.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/alias-30.c	(.../branches/gcc-4_9-branch)
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O -fdump-tree-fre-details" } */
++/* { dg-options "-O -fdump-tree-fre1-details" } */
+ 
+ extern int posix_memalign(void **memptr,
+ 			  __SIZE_TYPE__ alignment, __SIZE_TYPE__ size);
 Index: gcc/testsuite/gcc.dg/pr60844.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.dg/pr60844.c	(.../tags/gcc_4_9_0_release)
@@ -1870,6 +3397,16 @@ Index: gcc/testsuite/gcc.dg/pr60844.c
 +      x[2 + b] = e;
 +    }
 +}
+Index: gcc/testsuite/gcc.dg/vect/pr60505.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/vect/pr60505.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/gcc.dg/vect/pr60505.c	(.../branches/gcc-4_9-branch)
+@@ -10,3 +10,5 @@
+     out[i] = (ovec[i] = in[i]);
+   out[num] = ovec[num/2];
+ }
++
++/* { dg-final { cleanup-tree-dump "vect" } } */
 Index: gcc/testsuite/gcc.dg/vect/pr60841.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.dg/vect/pr60841.c	(.../tags/gcc_4_9_0_release)
@@ -2062,7 +3599,60 @@ Index: gcc/testsuite/ChangeLog
 ===================================================================
 --- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,151 @@
+@@ -1,3 +1,204 @@
++2014-04-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from mainline
++	2014-04-24  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	* gcc.target/powerpc/pack01.c: New test to test the new pack and
++	unpack builtin functionss for 128-bit types.
++	* gcc.target/powerpc/pack02.c: Likewise.
++	* gcc.target/powerpc/pack03.c: Likewise.
++	* gcc.target/powerpc/extend-divide-1.c: New test to test extended
++	divide builtin functionss.
++	* gcc.target/powerpc/extend-divide-2.c: Likewise.
++	* gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin
++	functions.
++	* gcc.target/powerpc/bcd-2.c: Likewise.
++	* gcc.target/powerpc/bcd-3.c: Likewise.
++	* gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP
++	builtin functionss.
++	* gcc.target/powerpc/dfp-builtin-2.c: Likewise.
++
++2014-04-29  Pat Haugen  <pthaugen@us.ibm.com>
++
++	Backport from mainline
++	2014-04-17  Pat Haugen  <pthaugen@us.ibm.com>
++
++	* gcc.target/powerpc/ti_math1.c: New.
++	* gcc.target/powerpc/ti_math2.c: New.
++
++2014-04-29  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/60971
++	* c-c++-common/turtore/pr60971.c: New test.
++
++2014-04-26  Uros Bizjak  <ubizjak@gmail.com>
++
++	* gcc.dg/tree-ssa/alias-30.c (dg-options): Dump only fre1 details.
++	* gcc.dg/vect/pr60505.c: Cleanup vect tree dump.
++	* g++.dg/ipa/devirt-27.C (dg-options): Remove -fdump-ipa-devirt.
++
++2014-04-25  Uros Bizjak  <ubizjak@gmail.com>
++
++	* c-c++-common/gomp/pr60823-2.c: Require effective target
++	vect_simd_clones.
++
++2014-04-25  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/60960
++	* gcc.c-torture/execute/pr60960.c: New test.
++
++2014-04-25  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc.c-torture/execute/20140425-1.c: New test.
++
 +2014-04-25  Richard Biener  <rguenther@suse.de>
 +
 +	PR ipa/60912
@@ -2214,7 +3804,7 @@ Index: gcc/testsuite/ChangeLog
  2014-04-22  Release Manager
  
  	* GCC 4.9.0 released.
-@@ -51,7 +199,7 @@
+@@ -51,7 +252,7 @@
  2014-04-12  Jerry DeLisle  <jvdelisle@gcc.gnu>
  
  	PR libfortran/60810
@@ -2223,7 +3813,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-04-11  Steve Ellcey  <sellcey@mips.com>
  	    Jakub Jelinek  <jakub@redhat.com>
-@@ -135,8 +283,7 @@
+@@ -135,8 +336,7 @@
  
  2014-04-08  Jason Merrill  <jason@redhat.com>
  
@@ -2233,7 +3823,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-04-08  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  
-@@ -256,10 +403,10 @@
+@@ -256,10 +456,10 @@
  2014-04-04  Martin Jambor  <mjambor@suse.cz>
  
  	PR ipa/60640
@@ -2248,7 +3838,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-04-04  Jeff Law  <law@redhat.com>
  
-@@ -371,7 +518,7 @@
+@@ -371,7 +571,7 @@
  
  2014-04-01  Fabien Chêne  <fabien@gcc.gnu.org>
  
@@ -2257,7 +3847,7 @@ Index: gcc/testsuite/ChangeLog
  	* g++.dg/init/ctor4-1.C: New.
  	* g++.dg/cpp0x/defaulted2.C: Adjust.
  
-@@ -459,8 +606,8 @@
+@@ -459,8 +659,8 @@
  
  2014-03-27  Jeff Law  <law@redhat.com>
  
@@ -2268,7 +3858,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-03-28  Adam Butcher  <adam@jessamine.co.uk>
  
-@@ -493,14 +640,13 @@
+@@ -493,14 +693,13 @@
  
  2014-03-28  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  
@@ -2286,7 +3876,7 @@ Index: gcc/testsuite/ChangeLog
  	of second source operand.
  	* gcc.target/i386/avx512f-vshuff64x2-2.c: Ditto.
  	* gcc.target/i386/avx512f-vshufi32x4-2.c: Ditto.
-@@ -635,8 +781,8 @@
+@@ -635,8 +834,8 @@
  
  2014-03-24  Marek Polacek  <polacek@redhat.com>
  
@@ -2297,7 +3887,7 @@ Index: gcc/testsuite/ChangeLog
  	* c-c++-common/ubsan/overflow-1.c: Check for unwanted output.
  	* c-c++-common/ubsan/overflow-add-1.c: Likewise.
  	* c-c++-common/ubsan/overflow-mul-1.c: Likewise.
-@@ -721,8 +867,7 @@
+@@ -721,8 +920,7 @@
  2014-03-21  Tobias Burnus  <burnus@net-b.de>
  
  	PR fortran/60599
@@ -2307,6 +3897,37 @@ Index: gcc/testsuite/ChangeLog
  
  2014-03-20  Jakub Jelinek  <jakub@redhat.com>
  
+@@ -1540,8 +1738,7 @@
+ 
+ 2014-02-19  Paul Pluzhnikov  <ppluzhnikov@google.com>
+ 
+-	* gcc.dg/vect/no-vfa-vect-depend-2.c (main1): Fix buffer
+-	overflow.
++	* gcc.dg/vect/no-vfa-vect-depend-2.c (main1): Fix buffer overflow.
+ 
+ 2014-02-19  Jakub Jelinek  <jakub@redhat.com>
+ 
+@@ -1850,8 +2047,7 @@
+ 
+ 2014-02-10  Jakub Jelinek  <jakub@redhat.com>
+ 
+-	* gcc.dg/vect/pr59984.c: Require effective target
+-	vect_simd_clones.
++	* gcc.dg/vect/pr59984.c: Require effective target vect_simd_clones.
+ 
+ 2014-02-09  Paul Thomas  <pault@gcc.gnu.org>
+ 
+@@ -3098,8 +3294,8 @@
+ 	* gfortran.dg/vect/fast-math-mgrid-resid.f: Change
+ 	-fdump-tree-optimized to -fdump-tree-pcom-details in dg-options and
+ 	cleanup-tree-dump from optimized to pcom.  Remove scan-tree-dump-times
+-	for vect_\[^\\n\]*\\+, add scan-tree-dump-times for no suitable chains and
+-	Executing predictive commoning without unrolling.
++	for vect_\[^\\n\]*\\+, add scan-tree-dump-times for no suitable
++	chains and Executing predictive commoning without unrolling.
+ 
+ 2014-01-14  Kirill Yukhin  <kirill.yukhin@intel.com>
+ 
 Index: gcc/testsuite/g++.dg/vect/pr60836.cc
 ===================================================================
 --- a/src/gcc/testsuite/g++.dg/vect/pr60836.cc	(.../tags/gcc_4_9_0_release)
@@ -2392,6 +4013,48 @@ Index: gcc/testsuite/g++.dg/opt/pr60912.C
 +  (new Bar ())->Foo ();
 +  return 0;
 +}
+Index: gcc/testsuite/g++.dg/cpp0x/constexpr-aggr1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-aggr1.C	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-aggr1.C	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,17 @@
++// PR c++/60951
++// { dg-do compile { target c++11 } }
++
++struct Foo {
++  constexpr Foo(int x = 0) : memb(x) {}
++  int memb;
++};
++
++struct FooContainer {
++  Foo foo[2];
++};
++
++void fubar() {
++  int nonConst = 0;
++  FooContainer fooContainer;
++  fooContainer = { { 0, nonConst } };
++}
+Index: gcc/testsuite/g++.dg/cpp0x/defaulted49.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/defaulted49.C	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/defaulted49.C	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,15 @@
++// PR c++/60980
++// { dg-do compile { target c++11 } }
++
++struct x0
++{
++  x0 () = default;
++};
++struct x1
++{
++  x0 x2[2];
++  void x3 ()
++  {
++    x1 ();
++  }
++};
 Index: gcc/testsuite/g++.dg/torture/pr60895.C
 ===================================================================
 --- a/src/gcc/testsuite/g++.dg/torture/pr60895.C	(.../tags/gcc_4_9_0_release)
@@ -2429,6 +4092,56 @@ Index: gcc/testsuite/g++.dg/torture/pr60895.C
 +{
 +  J ();
 +}
+Index: gcc/testsuite/g++.dg/ipa/devirt-27.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ipa/devirt-27.C	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/g++.dg/ipa/devirt-27.C	(.../branches/gcc-4_9-branch)
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O3 -fdump-ipa-devirt -fdump-tree-optimized"  } */
++/* { dg-options "-O3 -fdump-tree-optimized"  } */
+ struct A
+  {
+    int a;
+Index: gcc/testsuite/c-c++-common/torture/pr60971.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/torture/pr60971.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/c-c++-common/torture/pr60971.c	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,34 @@
++/* PR tree-optimization/60971 */
++/* { dg-do run } */
++
++#ifndef __cplusplus
++#define bool _Bool
++#endif
++
++volatile unsigned char c;
++
++__attribute__((noinline)) unsigned char
++foo (void)
++{
++  return c;
++}
++
++__attribute__((noinline)) bool
++bar (void)
++{
++  return foo () & 1;
++}
++
++int
++main ()
++{
++  c = 0x41;
++  c = bar ();
++  if (c != 1)
++    __builtin_abort ();
++  c = 0x20;
++  c = bar ();
++  if (c != 0)
++    __builtin_abort ();
++  return 0;
++}
 Index: gcc/testsuite/c-c++-common/gomp/atomic-16.c
 ===================================================================
 --- a/src/gcc/testsuite/c-c++-common/gomp/atomic-16.c	(.../tags/gcc_4_9_0_release)
@@ -2510,9 +4223,10 @@ Index: gcc/testsuite/c-c++-common/gomp/pr60823-2.c
 ===================================================================
 --- a/src/gcc/testsuite/c-c++-common/gomp/pr60823-2.c	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/testsuite/c-c++-common/gomp/pr60823-2.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,43 @@
+@@ -0,0 +1,44 @@
 +/* PR tree-optimization/60823 */
 +/* { dg-do run } */
++/* { dg-require-effective-target vect_simd_clones } */
 +/* { dg-options "-O2 -fopenmp-simd" } */
 +
 +#pragma omp declare simd simdlen(4) notinbranch
@@ -2608,11 +4322,33 @@ Index: gcc/testsuite/c-c++-common/gomp/pr59073.c
 +  for (i = 0; i < 10; i)	/* { dg-error "invalid increment expression" } */
 +    ;
 +}
+Index: gcc/cp/init.c
+===================================================================
+--- a/src/gcc/cp/init.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/cp/init.c	(.../branches/gcc-4_9-branch)
+@@ -339,7 +339,8 @@
+   gcc_assert (!processing_template_decl
+ 	      || (SCALAR_TYPE_P (type) || TREE_CODE (type) == ARRAY_TYPE));
+ 
+-  if (type_build_ctor_call (type))
++  if (CLASS_TYPE_P (type)
++      && type_build_ctor_call (type))
+     {
+       tree ctor = build_aggr_init_expr
+ 	(type,
 Index: gcc/cp/ChangeLog
 ===================================================================
 --- a/src/gcc/cp/ChangeLog	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/cp/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,15 @@
+@@ -1,3 +1,23 @@
++2014-04-30  Jason Merrill  <jason@redhat.com>
++
++	PR c++/60980
++	* init.c (build_value_init): Don't try to call an array constructor.
++
++	PR c++/60951
++	* typeck2.c (massage_init_elt): Use maybe_constant_init.
++
 +2014-04-24  Jakub Jelinek  <jakub@redhat.com>
 +
 +	* parser.c (cp_parser_omp_atomic): Allow seq_cst before
@@ -2628,6 +4364,19 @@ Index: gcc/cp/ChangeLog
  2014-04-22  Release Manager
  
  	* GCC 4.9.0 released.
+Index: gcc/cp/typeck2.c
+===================================================================
+--- a/src/gcc/cp/typeck2.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/cp/typeck2.c	(.../branches/gcc-4_9-branch)
+@@ -1138,7 +1138,7 @@
+   /* When we defer constant folding within a statement, we may want to
+      defer this folding as well.  */
+   tree t = fold_non_dependent_expr_sfinae (init, complain);
+-  t = maybe_constant_value (t);
++  t = maybe_constant_init (t);
+   if (TREE_CONSTANT (t))
+     init = t;
+   return init;
 Index: gcc/cp/parser.c
 ===================================================================
 --- a/src/gcc/cp/parser.c	(.../tags/gcc_4_9_0_release)
@@ -2849,6 +4598,19 @@ Index: gcc/loop-init.c
      }
  
    /* Apply flags to loops.  */
+Index: gcc/go/gofrontend/import-archive.cc
+===================================================================
+--- a/src/gcc/go/gofrontend/import-archive.cc	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/go/gofrontend/import-archive.cc	(.../branches/gcc-4_9-branch)
+@@ -261,7 +261,7 @@
+   char size_string[size_string_size + 1];
+   memcpy(size_string, hdr->ar_size, size_string_size);
+   char* ps = size_string + size_string_size;
+-  while (ps[-1] == ' ')
++  while (ps > size_string && ps[-1] == ' ')
+     --ps;
+   *ps = '\0';
+ 
 Index: gcc/common/config/msp430/msp430-common.c
 ===================================================================
 --- a/src/gcc/common/config/msp430/msp430-common.c	(.../tags/gcc_4_9_0_release)
@@ -3091,6 +4853,19 @@ Index: gcc/fortran/resolve.c
      return false;
  
    if (sym->attr.is_class && sym->ts.u.derived == NULL)
+Index: gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/configure.ac	(.../branches/gcc-4_9-branch)
+@@ -3725,7 +3725,7 @@
+        .align 4
+        smac %g2, %g3, %g1
+        umac %g2, %g3, %g1
+-       cas [[%g2]], %g3, %g1],,
++       casa [[%g2]] 0xb, %g3, %g1],,
+       [AC_DEFINE(HAVE_AS_LEON, 1,
+                 [Define if your assembler supports LEON instructions.])])
+     ;;
 Index: gcc/tree-vectorizer.h
 ===================================================================
 --- a/src/gcc/tree-vectorizer.h	(.../tags/gcc_4_9_0_release)
@@ -3424,6 +5199,199 @@ Index: gcc/cfgexpand.c
  
  	  var_end_seq
  	    = asan_emit_stack_protection (virtual_stack_vars_rtx,
+Index: gcc/po/ChangeLog
+===================================================================
+--- a/src/gcc/po/ChangeLog	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/po/ChangeLog	(.../branches/gcc-4_9-branch)
+@@ -1,3 +1,7 @@
++2014-05-01  Joseph Myers  <joseph@codesourcery.com>
++
++	* sv.po: Update.
++
+ 2014-04-22  Release Manager
+ 
+ 	* GCC 4.9.0 released.
+Index: gcc/po/sv.po
+===================================================================
+--- a/src/gcc/po/sv.po	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/po/sv.po	(.../branches/gcc-4_9-branch)
+@@ -16,7 +16,7 @@
+ "Project-Id-Version: gcc 4.9-b20140202\n"
+ "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"
+ "POT-Creation-Date: 2014-02-02 17:35+0000\n"
+-"PO-Revision-Date: 2014-03-30 20:23+0200\n"
++"PO-Revision-Date: 2014-04-11 20:56+0200\n"
+ "Last-Translator: Göran Uddeborg <goeran@uddeborg.se>\n"
+ "Language-Team: Swedish <tp-sv@listor.tp-sv.se>\n"
+ "Language: sv\n"
+@@ -1493,7 +1493,7 @@
+ 
+ #: cif-code.def:125
+ msgid "callee refers to comdat-local symbols"
+-msgstr "den anropade referarar till comdat-lokala symboler"
++msgstr "den anropade refererar till comdat-lokala symboler"
+ 
+ #. The remainder are real diagnostic types.
+ #: diagnostic.def:33
+@@ -6065,7 +6065,7 @@
+ 
+ #: c-family/c.opt:653
+ msgid "Warn about __TIME__, __DATE__ and __TIMESTAMP__ usage"
+-msgstr "Warn för använding av __TIME__, __DATE__ och __TIMESTAMP__"
++msgstr "Varna för användning av __TIME__, __DATE__ och __TIMESTAMP__"
+ 
+ #: c-family/c.opt:657
+ msgid "Warn if a property for an Objective-C object has no assign semantics specified"
+@@ -12220,7 +12220,7 @@
+ 
+ #: common.opt:811
+ msgid "Aggressively optimize loops using language constraints"
+-msgstr "Optimera aggresivt slingor med användning av språkbegränsningar"
++msgstr "Optimera aggressivt slingor med användning av språkbegränsningar"
+ 
+ #: common.opt:815
+ msgid "Align the start of functions"
+@@ -13449,7 +13449,7 @@
+ 
+ #: common.opt:2332
+ msgid "Enables the dynamic vectorizer cost model.  Preserved for backward compatibility."
+-msgstr "Aktivera den dynamiska kostnadsmodellen för vekoriseraren.  Bevarad för bakåtkompatibilitet."
++msgstr "Aktivera den dynamiska kostnadsmodellen för vektoriseraren.  Bevarad för bakåtkompatibilitet."
+ 
+ #: common.opt:2336
+ msgid "Enables the unlimited vectorizer cost model.  Preserved for backward compatibility."
+@@ -19151,7 +19151,7 @@
+ #: c/c-array-notation.c:721 cp/cp-array-notation.c:610
+ #, gcc-internal-format
+ msgid "rank mismatch between %qE and %qE"
+-msgstr "ordingen stämmer inte mellan %qE och %qE"
++msgstr "ordningen stämmer inte mellan %qE och %qE"
+ 
+ #. Here the original expression is printed as a "heads-up"
+ #. to the programmer.  This is because since there is no
+@@ -25782,7 +25782,7 @@
+ msgid "too much stack space to dispose of: %d"
+ msgstr "för mycket stackutrymme att göra av med: %d"
+ 
+-# Förmodligen en felstavning i orginalet, men tills jag vet säkert
++# Förmodligen en felstavning i originalet, men tills jag vet säkert
+ # behåller jag den
+ #: config/v850/v850.c:2788
+ #, gcc-internal-format, gfc-internal-format
+@@ -28130,7 +28130,7 @@
+ #: c/c-parser.c:6884
+ #, gcc-internal-format
+ msgid "%<_Generic%> selector of type %qT is not compatible with any association"
+-msgstr "%<_Generic%>-väljare av typ %qT är inte kompatiblem med någon association"
++msgstr "%<_Generic%>-väljare av typ %qT är inte kompatibel med någon association"
+ 
+ #: c/c-parser.c:7039 c/c-parser.c:7519 c/c-parser.c:7538
+ #, gcc-internal-format
+@@ -28185,7 +28185,7 @@
+ #: c/c-parser.c:7505 cp/parser.c:5807
+ #, gcc-internal-format
+ msgid "consecutive %<_Cilk_spawn%> keywords are not permitted"
+-msgstr "konsektiva %<_Cilk_spawn%>-nyckelord är inte tillåtet"
++msgstr "konsekutiva %<_Cilk_spawn%>-nyckelord är inte tillåtet"
+ 
+ #: c/c-parser.c:7573
+ #, gcc-internal-format
+@@ -31055,7 +31055,7 @@
+ #: cp/cp-array-notation.c:849 cp/cp-array-notation.c:855
+ #, gcc-internal-format
+ msgid "rank mismatch with controlling expression of parent if-statement"
+-msgstr "ordingen stämmer inte med det styrande uttrycket i förälder-if-satsen"
++msgstr "ordningen stämmer inte med det styrande uttrycket i förälder-if-satsen"
+ 
+ #: cp/cp-array-notation.c:1250
+ #, gcc-internal-format
+@@ -31090,7 +31090,7 @@
+ #: cp/cp-array-notation.c:1422
+ #, gcc-internal-format
+ msgid "array notation cannot be used with function type"
+-msgstr "vektornotation kan inte användas användas med en funktionstyp"
++msgstr "vektornotation kan inte användas med en funktionstyp"
+ 
+ #: cp/cp-array-notation.c:1432
+ #, gcc-internal-format
+@@ -31100,7 +31100,7 @@
+ #: cp/cp-array-notation.c:1438
+ #, gcc-internal-format
+ msgid "rank of an array notation triplet%'s length is not zero"
+-msgstr "ordingen på en vektornotations trippels längd är inte noll"
++msgstr "ordningen på en vektornotations trippels längd är inte noll"
+ 
+ #: cp/cp-array-notation.c:1443
+ #, gcc-internal-format
+@@ -31450,7 +31450,7 @@
+ #: cp/cvt.c:1659
+ #, gcc-internal-format
+ msgid "ambiguous default type conversion from %qT"
+-msgstr "tvetydig standartypkonvertering från %qT"
++msgstr "tvetydig standardtypkonvertering från %qT"
+ 
+ #: cp/cvt.c:1661
+ #, gcc-internal-format
+@@ -33747,7 +33747,7 @@
+ #: cp/decl.c:14531 cp/decl2.c:4673
+ #, gcc-internal-format
+ msgid "use of %qD before deduction of %<auto%>"
+-msgstr "använding av %qD före härledning av %<auto%>"
++msgstr "användning av %qD före härledning av %<auto%>"
+ 
+ #: cp/decl2.c:322
+ #, gcc-internal-format
+@@ -36027,7 +36027,7 @@
+ #: cp/parser.c:14516
+ #, gcc-internal-format
+ msgid "use of %<auto%> in parameter declaration only available with -std=c++1y or -std=gnu++1y"
+-msgstr "använding av %<auto%> i parameterdeklarationer är endast tillgängligt med -std=c++1y eller -std=gnu++1y"
++msgstr "användning av %<auto%> i parameterdeklarationer är endast tillgängligt med -std=c++1y eller -std=gnu++1y"
+ 
+ #: cp/parser.c:14521
+ #, gcc-internal-format
+@@ -37288,7 +37288,7 @@
+ #: cp/pt.c:4861
+ #, gcc-internal-format
+ msgid "template arguments to %qD do not match original template %qD"
+-msgstr "mallargument till %qD stämmer inte med orginalmallen %qD"
++msgstr "mallargument till %qD stämmer inte med originalmallen %qD"
+ 
+ #: cp/pt.c:4865
+ #, gcc-internal-format
+@@ -38326,7 +38326,7 @@
+ #: cp/semantics.c:3800
+ #, gcc-internal-format
+ msgid "second operand of %<offsetof%> is neither a single identifier nor a sequence of member accesses and array references"
+-msgstr "andra operanden till %<offsetof%> är varken en ensam idientifierare eller en sekvens av medlemsåtkomster och vektorreferenser"
++msgstr "andra operanden till %<offsetof%> är varken en ensam identifierare eller en sekvens av medlemsåtkomster och vektorreferenser"
+ 
+ #: cp/semantics.c:3808
+ #, gcc-internal-format
+@@ -48120,7 +48120,7 @@
+ #: fortran/resolve.c:13229
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Variable '%s' at %L with coarray component shall be a nonpointer, nonallocatable scalar, which is not a coarray"
+-msgstr "Variabeln ”%s” vid %L med co-vektorkomponent skall vara en skalär som inte är en pekare eller allokerbar och inte en co-vaktor"
++msgstr "Variabeln ”%s” vid %L med co-vektorkomponent skall vara en skalär som inte är en pekare eller allokerbar och inte en co-vektor"
+ 
+ #: fortran/resolve.c:13244
+ #, gcc-internal-format, gfc-internal-format
+@@ -49576,12 +49576,12 @@
+ #: lto/lto-symtab.c:404
+ #, gcc-internal-format
+ msgid "type of %qD does not match original declaration"
+-msgstr "typen på %qD stämmer inte med orginaldeklarationen"
++msgstr "typen på %qD stämmer inte med originaldeklarationen"
+ 
+ #: lto/lto-symtab.c:412
+ #, gcc-internal-format
+ msgid "alignment of %qD is bigger than original declaration"
+-msgstr "justering av %qD är större än orginaldeklarationen"
++msgstr "justering av %qD är större än originaldeklarationen"
+ 
+ #: lto/lto-symtab.c:418 lto/lto-symtab.c:517
+ #, gcc-internal-format
 Index: gcc/tree-nested.c
 ===================================================================
 --- a/src/gcc/tree-nested.c	(.../tags/gcc_4_9_0_release)
@@ -3492,6 +5460,20 @@ Index: gcc/tree-inline.c
  	}
        if ((TREE_CODE (TREE_TYPE (result)) == COMPLEX_TYPE
             || TREE_CODE (TREE_TYPE (result)) == VECTOR_TYPE)
+Index: gcc/tree-vect-generic.c
+===================================================================
+--- a/src/gcc/tree-vect-generic.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/tree-vect-generic.c	(.../branches/gcc-4_9-branch)
+@@ -971,7 +971,8 @@
+ 
+ 	  if (!optimize
+ 	      || !VECTOR_INTEGER_TYPE_P (type)
+-	      || TREE_CODE (rhs2) != VECTOR_CST)
++	      || TREE_CODE (rhs2) != VECTOR_CST
++	      || !VECTOR_MODE_P (TYPE_MODE (type)))
+ 	    break;
+ 
+ 	  ret = expand_vector_divmod (gsi, type, rhs1, rhs2, code);
 Index: gcc/config.gcc
 ===================================================================
 --- a/src/gcc/config.gcc	(.../tags/gcc_4_9_0_release)
@@ -3726,6 +5708,78 @@ Index: gcc/tree-ssa-reassoc.c
  		  release_defs (stmt);
  		  /* We might end up removing the last stmt above which
  		     places the iterator to the end of the sequence.
+Index: gcc/config/sparc/sparc.md
+===================================================================
+--- a/src/gcc/config/sparc/sparc.md	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/sparc/sparc.md	(.../branches/gcc-4_9-branch)
+@@ -5795,19 +5795,6 @@
+ }
+   [(set_attr "type" "shift")])
+ 
+-(define_insn "*ashlsi3_extend"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
+-	(zero_extend:DI
+-	  (ashift:SI (match_operand:SI 1 "register_operand" "r")
+-		     (match_operand:SI 2 "arith_operand" "rI"))))]
+-  "TARGET_ARCH64"
+-{
+-  if (GET_CODE (operands[2]) == CONST_INT)
+-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+-  return "sll\t%1, %2, %0";
+-}
+-  [(set_attr "type" "shift")])
+-
+ (define_expand "ashldi3"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(ashift:DI (match_operand:DI 1 "register_operand" "r")
+Index: gcc/config/sparc/sparc.opt
+===================================================================
+--- a/src/gcc/config/sparc/sparc.opt	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/sparc/sparc.opt	(.../branches/gcc-4_9-branch)
+@@ -113,6 +113,10 @@
+ Target
+ Optimize tail call instructions in assembler and linker
+ 
++muser-mode
++Target Report Mask(USER_MODE)
++Do not generate code that can only run in supervisor mode
++
+ mcpu=
+ Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
+ Use features of and schedule code for given CPU
+Index: gcc/config/sparc/sync.md
+===================================================================
+--- a/src/gcc/config/sparc/sync.md	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/sparc/sync.md	(.../branches/gcc-4_9-branch)
+@@ -200,10 +200,27 @@
+ 	  [(match_operand:I48MODE 2 "register_operand" "r")
+ 	   (match_operand:I48MODE 3 "register_operand" "0")]
+ 	  UNSPECV_CAS))]
+-  "(TARGET_V9 || TARGET_LEON3) && (<MODE>mode != DImode || TARGET_ARCH64)"
++  "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)"
+   "cas<modesuffix>\t%1, %2, %0"
+   [(set_attr "type" "multi")])
+ 
++(define_insn "*atomic_compare_and_swap_leon3_1"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(match_operand:SI 1 "mem_noofs_operand" "+w"))
++   (set (match_dup 1)
++	(unspec_volatile:SI
++	  [(match_operand:SI 2 "register_operand" "r")
++	   (match_operand:SI 3 "register_operand" "0")]
++	  UNSPECV_CAS))]
++  "TARGET_LEON3"
++{
++  if (TARGET_USER_MODE)
++    return "casa\t%1 0xa, %2, %0"; /* ASI for user data space.  */
++  else
++    return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space.  */
++}
++  [(set_attr "type" "multi")])
++
+ (define_insn "*atomic_compare_and_swapdi_v8plus"
+   [(set (match_operand:DI 0 "register_operand" "=h")
+ 	(match_operand:DI 1 "mem_noofs_operand" "+w"))
 Index: gcc/config/i386/cygwin.h
 ===================================================================
 --- a/src/gcc/config/i386/cygwin.h	(.../tags/gcc_4_9_0_release)
@@ -3738,6 +5792,32 @@ Index: gcc/config/i386/cygwin.h
     crtend.o%s"
  
  /* Normally, -lgcc is not needed since everything in it is in the DLL, but we
+Index: gcc/config/i386/i386.md
+===================================================================
+--- a/src/gcc/config/i386/i386.md	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/i386/i386.md	(.../branches/gcc-4_9-branch)
+@@ -14427,15 +14427,16 @@
+   "TARGET_USE_FANCY_MATH_387
+    && flag_unsafe_math_optimizations"
+ {
++  rtx tmp1, tmp2;
+   if (optimize_insn_for_size_p ())
+     FAIL;
+ 
+-  operands[3] = gen_reg_rtx (XFmode);
+-  operands[4] = gen_reg_rtx (XFmode);
++  tmp1 = gen_reg_rtx (XFmode);
++  tmp2 = gen_reg_rtx (XFmode);
+ 
+-  emit_insn (gen_floatsixf2 (operands[3], operands[2]));
+-  emit_insn (gen_fscalexf4_i387 (operands[0], operands[4],
+-                                 operands[1], operands[3]));
++  emit_insn (gen_floatsixf2 (tmp1, operands[2]));
++  emit_insn (gen_fscalexf4_i387 (operands[0], tmp2,
++                                 operands[1], tmp1));
+   DONE;
+ })
+ 
 Index: gcc/config/i386/mingw32.h
 ===================================================================
 --- a/src/gcc/config/i386/mingw32.h	(.../tags/gcc_4_9_0_release)
@@ -3784,6 +5864,237 @@ Index: gcc/config/i386/i386.c
          target = gen_reg_rtx (SImode);
  
        emit_insn (gen_zero_extendqisi2 (target, op2));
+Index: gcc/config/aarch64/aarch64.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.h	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/aarch64/aarch64.h	(.../branches/gcc-4_9-branch)
+@@ -32,7 +32,7 @@
+       else						\
+ 	builtin_define ("__AARCH64EL__");		\
+ 							\
+-      if (!TARGET_GENERAL_REGS_ONLY)			\
++      if (TARGET_SIMD)					\
+ 	builtin_define ("__ARM_NEON");			\
+ 							\
+       switch (aarch64_cmodel)				\
+@@ -83,9 +83,9 @@
+ #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
+ 
+ /* AdvSIMD is supported in the default configuration, unless disabled by
+-   -mgeneral-regs-only.  */
+-#define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY
+-#define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY
++   -mgeneral-regs-only or by the +nosimd extension.  */
++#define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
++#define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
+ 
+ #define UNITS_PER_WORD		8
+ 
+@@ -185,8 +185,8 @@
+ extern unsigned long aarch64_tune_flags;
+ #define AARCH64_TUNE_SLOWMUL       (aarch64_tune_flags & AARCH64_FL_SLOWMUL)
+ 
+-/* Crypto is an optional feature.  */
+-#define TARGET_CRYPTO AARCH64_ISA_CRYPTO
++/* Crypto is an optional extension to AdvSIMD.  */
++#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
+ 
+ /* Standard register usage.  */
+ 
+Index: gcc/config/rs6000/predicates.md
+===================================================================
+--- a/src/gcc/config/rs6000/predicates.md	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/rs6000/predicates.md	(.../branches/gcc-4_9-branch)
+@@ -171,6 +171,11 @@
+   (and (match_code "const_int")
+        (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
+ 
++;; Match op = 0..3.
++(define_predicate "const_0_to_3_operand"
++  (and (match_code "const_int")
++       (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
++
+ ;; Match op = 2 or op = 3.
+ (define_predicate "const_2_to_3_operand"
+   (and (match_code "const_int")
+@@ -624,7 +629,7 @@
+        (match_test "offsettable_nonstrict_memref_p (op)")))
+ 
+ ;; Return 1 if the operand is suitable for load/store quad memory.
+-;; This predicate only checks for non-atomic loads/stores.
++;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
+ (define_predicate "quad_memory_operand"
+   (match_code "mem")
+ {
+@@ -631,7 +636,7 @@
+   rtx addr, op0, op1;
+   int ret;
+ 
+-  if (!TARGET_QUAD_MEMORY)
++  if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
+     ret = 0;
+ 
+   else if (!memory_operand (op, mode))
+Index: gcc/config/rs6000/rs6000-builtin.def
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000-builtin.def	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/rs6000/rs6000-builtin.def	(.../branches/gcc-4_9-branch)
+@@ -570,6 +570,75 @@
+ 		    MASK,				/* MASK */	\
+ 		    (ATTR | RS6000_BTC_SPECIAL),	/* ATTR */	\
+ 		    CODE_FOR_nothing)			/* ICODE */
++
++
++/* Decimal floating point builtins for instructions.  */
++#define BU_DFP_MISC_1(ENUM, NAME, ATTR, ICODE)				\
++  RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
++		    "__builtin_" NAME,			/* NAME */	\
++		    RS6000_BTM_DFP,			/* MASK */	\
++		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
++		     | RS6000_BTC_UNARY),				\
++		    CODE_FOR_ ## ICODE)			/* ICODE */
++
++#define BU_DFP_MISC_2(ENUM, NAME, ATTR, ICODE)				\
++  RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
++		    "__builtin_" NAME,			/* NAME */	\
++		    RS6000_BTM_DFP,			/* MASK */	\
++		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
++		     | RS6000_BTC_BINARY),				\
++		    CODE_FOR_ ## ICODE)			/* ICODE */
++
++
++/* Miscellaneous builtins for instructions added in ISA 2.06.  These
++   instructions don't require either the DFP or VSX options, just the basic ISA
++   2.06 (popcntd) enablement since they operate on general purpose
++   registers.  */
++#define BU_P7_MISC_1(ENUM, NAME, ATTR, ICODE)				\
++  RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
++		    "__builtin_" NAME,			/* NAME */	\
++		    RS6000_BTM_POPCNTD,			/* MASK */	\
++		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
++		     | RS6000_BTC_UNARY),				\
++		    CODE_FOR_ ## ICODE)			/* ICODE */
++
++#define BU_P7_MISC_2(ENUM, NAME, ATTR, ICODE)				\
++  RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
++		    "__builtin_" NAME,			/* NAME */	\
++		    RS6000_BTM_POPCNTD,			/* MASK */	\
++		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
++		     | RS6000_BTC_BINARY),				\
++		    CODE_FOR_ ## ICODE)			/* ICODE */
++
++
++/* Miscellaneous builtins for instructions added in ISA 2.07.  These
++   instructions do require the ISA 2.07 vector support, but they aren't vector
++   instructions.  */
++#define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE)				\
++  RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
++		    "__builtin_" NAME,			/* NAME */	\
++		    RS6000_BTM_P8_VECTOR,		/* MASK */	\
++		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
++		     | RS6000_BTC_TERNARY),				\
++		    CODE_FOR_ ## ICODE)			/* ICODE */
++
++/* Miscellaneous builtins.  */
++#define BU_MISC_1(ENUM, NAME, ATTR, ICODE)				\
++  RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
++		    "__builtin_" NAME,			/* NAME */	\
++		    RS6000_BTM_ALWAYS,			/* MASK */	\
++		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
++		     | RS6000_BTC_UNARY),				\
++		    CODE_FOR_ ## ICODE)			/* ICODE */
++
++#define BU_MISC_2(ENUM, NAME, ATTR, ICODE)				\
++  RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM,		/* ENUM */	\
++		    "__builtin_" NAME,			/* NAME */	\
++		    RS6000_BTM_ALWAYS,			/* MASK */	\
++		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
++		     | RS6000_BTC_BINARY),				\
++		    CODE_FOR_ ## ICODE)			/* ICODE */
++
+ #endif
+ 
+ /* Insure 0 is not a legitimate index.  */
+@@ -1412,10 +1481,10 @@
+ BU_P8V_AV_2 (ORC_V2DF,		"orc_v2df",	CONST,	orcv2df3)
+ 
+ /* 3 argument altivec instructions added in ISA 2.07.  */
+-BU_P8V_AV_3 (VADDEUQM,		"vaddeuqm",	 CONST,	altivec_vaddeuqm)
+-BU_P8V_AV_3 (VADDECUQ,		"vaddecuq",	 CONST,	altivec_vaddecuq)
+-BU_P8V_AV_3 (VSUBEUQM,		"vsubeuqm",	 CONST,	altivec_vsubeuqm)
+-BU_P8V_AV_3 (VSUBECUQ,		"vsubecuq",	 CONST,	altivec_vsubecuq)
++BU_P8V_AV_3 (VADDEUQM,		"vaddeuqm",	CONST,	altivec_vaddeuqm)
++BU_P8V_AV_3 (VADDECUQ,		"vaddecuq",	CONST,	altivec_vaddecuq)
++BU_P8V_AV_3 (VSUBEUQM,		"vsubeuqm",	CONST,	altivec_vsubeuqm)
++BU_P8V_AV_3 (VSUBECUQ,		"vsubecuq",	CONST,	altivec_vsubecuq)
+ 
+ /* Vector comparison instructions added in ISA 2.07.  */
+ BU_P8V_AV_2 (VCMPEQUD,		"vcmpequd",	CONST,	vector_eqv2di)
+@@ -1475,6 +1544,64 @@
+ BU_P8V_OVERLOAD_3 (VSUBEUQM,	"vsubeuqm")
+ 
+ 
++/* 2 argument extended divide functions added in ISA 2.06.  */
++BU_P7_MISC_2 (DIVWE,		"divwe",	CONST,	dive_si)
++BU_P7_MISC_2 (DIVWEO,		"divweo",	CONST,	diveo_si)
++BU_P7_MISC_2 (DIVWEU,		"divweu",	CONST,	diveu_si)
++BU_P7_MISC_2 (DIVWEUO,		"divweuo",	CONST,	diveuo_si)
++BU_P7_MISC_2 (DIVDE,		"divde",	CONST,	dive_di)
++BU_P7_MISC_2 (DIVDEO,		"divdeo",	CONST,	diveo_di)
++BU_P7_MISC_2 (DIVDEU,		"divdeu",	CONST,	diveu_di)
++BU_P7_MISC_2 (DIVDEUO,		"divdeuo",	CONST,	diveuo_di)
++
++/* 1 argument DFP (decimal floating point) functions added in ISA 2.05.  */
++BU_DFP_MISC_1 (DXEX,		"dxex",		CONST,	dfp_dxex_dd)
++BU_DFP_MISC_1 (DXEXQ,		"dxexq",	CONST,	dfp_dxex_td)
++
++/* 2 argument DFP (decimal floating point) functions added in ISA 2.05.  */
++BU_DFP_MISC_2 (DDEDPD,		"ddedpd",	CONST,	dfp_ddedpd_dd)
++BU_DFP_MISC_2 (DDEDPDQ,		"ddedpdq",	CONST,	dfp_ddedpd_td)
++BU_DFP_MISC_2 (DENBCD,		"denbcd",	CONST,	dfp_denbcd_dd)
++BU_DFP_MISC_2 (DENBCDQ,		"denbcdq",	CONST,	dfp_denbcd_td)
++BU_DFP_MISC_2 (DIEX,		"diex",		CONST,	dfp_diex_dd)
++BU_DFP_MISC_2 (DIEXQ,		"diexq",	CONST,	dfp_diex_td)
++BU_DFP_MISC_2 (DSCLI,		"dscli",	CONST,	dfp_dscli_dd)
++BU_DFP_MISC_2 (DSCLIQ,		"dscliq",	CONST,	dfp_dscli_td)
++BU_DFP_MISC_2 (DSCRI,		"dscri",	CONST,	dfp_dscri_dd)
++BU_DFP_MISC_2 (DSCRIQ,		"dscriq",	CONST,	dfp_dscri_td)
++
++/* 1 argument BCD functions added in ISA 2.06.  */
++BU_P7_MISC_1 (CDTBCD,		"cdtbcd",	CONST,	cdtbcd)
++BU_P7_MISC_1 (CBCDTD,		"cbcdtd",	CONST,	cbcdtd)
++
++/* 2 argument BCD functions added in ISA 2.06.  */
++BU_P7_MISC_2 (ADDG6S,		"addg6s",	CONST,	addg6s)
++
++/* 3 argument BCD functions added in ISA 2.07.  */
++BU_P8V_MISC_3 (BCDADD,		"bcdadd",	CONST,	bcdadd)
++BU_P8V_MISC_3 (BCDADD_LT,	"bcdadd_lt",	CONST,	bcdadd_lt)
++BU_P8V_MISC_3 (BCDADD_EQ,	"bcdadd_eq",	CONST,	bcdadd_eq)
++BU_P8V_MISC_3 (BCDADD_GT,	"bcdadd_gt",	CONST,	bcdadd_gt)
++BU_P8V_MISC_3 (BCDADD_OV,	"bcdadd_ov",	CONST,	bcdadd_unordered)
++BU_P8V_MISC_3 (BCDSUB,		"bcdsub",	CONST,	bcdsub)
++BU_P8V_MISC_3 (BCDSUB_LT,	"bcdsub_lt",	CONST,	bcdsub_lt)
++BU_P8V_MISC_3 (BCDSUB_EQ,	"bcdsub_eq",	CONST,	bcdsub_eq)
++BU_P8V_MISC_3 (BCDSUB_GT,	"bcdsub_gt",	CONST,	bcdsub_gt)
++BU_P8V_MISC_3 (BCDSUB_OV,	"bcdsub_ov",	CONST,	bcdsub_unordered)
++
++/* 2 argument pack/unpack 128-bit floating point types.  */
++BU_DFP_MISC_2 (PACK_TD,		"pack_dec128",		CONST,	packtd)
++BU_DFP_MISC_2 (UNPACK_TD,	"unpack_dec128",	CONST,	unpacktd)
++
++BU_MISC_2 (PACK_TF,		"pack_longdouble",	CONST,	packtf)
++BU_MISC_2 (UNPACK_TF,		"unpack_longdouble",	CONST,	unpacktf)
++BU_MISC_1 (UNPACK_TF_0,		"longdouble_dw0",	CONST,	unpacktf_0)
++BU_MISC_1 (UNPACK_TF_1,		"longdouble_dw1",	CONST,	unpacktf_1)
++
++BU_P7_MISC_2 (PACK_V1TI,	"pack_vector_int128",	CONST,	packv1ti)
++BU_P7_MISC_2 (UNPACK_V1TI,	"unpack_vector_int128",	CONST,	unpackv1ti)
++
++
+ /* 1 argument crypto functions.  */
+ BU_CRYPTO_1 (VSBOX,		"vsbox",	  CONST, crypto_vsbox)
+ 
 Index: gcc/config/rs6000/rs6000.c
 ===================================================================
 --- a/src/gcc/config/rs6000/rs6000.c	(.../tags/gcc_4_9_0_release)
@@ -3813,6 +6124,161 @@ Index: gcc/config/rs6000/rs6000.c
    if (TARGET_LINK_STACK)
      fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
  
+@@ -3017,7 +3035,8 @@
+ 	  | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL      : 0)
+ 	  | ((TARGET_P8_VECTOR)		    ? RS6000_BTM_P8_VECTOR : 0)
+ 	  | ((TARGET_CRYPTO)		    ? RS6000_BTM_CRYPTO	   : 0)
+-	  | ((TARGET_HTM)		    ? RS6000_BTM_HTM	   : 0));
++	  | ((TARGET_HTM)		    ? RS6000_BTM_HTM	   : 0)
++	  | ((TARGET_DFP)		    ? RS6000_BTM_DFP	   : 0));
+ }
+ 
+ /* Override command line options.  Mostly we process the processor type and
+@@ -12381,7 +12400,15 @@
+ 	}
+     }
+   else if (icode == CODE_FOR_vsx_set_v2df
+-           || icode == CODE_FOR_vsx_set_v2di)
++           || icode == CODE_FOR_vsx_set_v2di
++	   || icode == CODE_FOR_bcdadd
++	   || icode == CODE_FOR_bcdadd_lt
++	   || icode == CODE_FOR_bcdadd_eq
++	   || icode == CODE_FOR_bcdadd_gt
++	   || icode == CODE_FOR_bcdsub
++	   || icode == CODE_FOR_bcdsub_lt
++	   || icode == CODE_FOR_bcdsub_eq
++	   || icode == CODE_FOR_bcdsub_gt)
+     {
+       /* Only allow 1-bit unsigned literals.  */
+       STRIP_NOPS (arg2);
+@@ -12392,6 +12419,44 @@
+ 	  return const0_rtx;
+ 	}
+     }
++  else if (icode == CODE_FOR_dfp_ddedpd_dd
++           || icode == CODE_FOR_dfp_ddedpd_td)
++    {
++      /* Only allow 2-bit unsigned literals where the value is 0 or 2.  */
++      STRIP_NOPS (arg0);
++      if (TREE_CODE (arg0) != INTEGER_CST
++	  || TREE_INT_CST_LOW (arg2) & ~0x3)
++	{
++	  error ("argument 1 must be 0 or 2");
++	  return const0_rtx;
++	}
++    }
++  else if (icode == CODE_FOR_dfp_denbcd_dd
++	   || icode == CODE_FOR_dfp_denbcd_td)
++    {
++      /* Only allow 1-bit unsigned literals.  */
++      STRIP_NOPS (arg0);
++      if (TREE_CODE (arg0) != INTEGER_CST
++	  || TREE_INT_CST_LOW (arg0) & ~0x1)
++	{
++	  error ("argument 1 must be a 1-bit unsigned literal");
++	  return const0_rtx;
++	}
++    }
++  else if (icode == CODE_FOR_dfp_dscli_dd
++           || icode == CODE_FOR_dfp_dscli_td
++	   || icode == CODE_FOR_dfp_dscri_dd
++	   || icode == CODE_FOR_dfp_dscri_td)
++    {
++      /* Only allow 6-bit unsigned literals.  */
++      STRIP_NOPS (arg1);
++      if (TREE_CODE (arg1) != INTEGER_CST
++	  || TREE_INT_CST_LOW (arg1) & ~0x3f)
++	{
++	  error ("argument 2 must be a 6-bit unsigned literal");
++	  return const0_rtx;
++	}
++    }
+   else if (icode == CODE_FOR_crypto_vshasigmaw
+ 	   || icode == CODE_FOR_crypto_vshasigmad)
+     {
+@@ -13483,6 +13548,14 @@
+     error ("Builtin function %s requires the -mpaired option", name);
+   else if ((fnmask & RS6000_BTM_SPE) != 0)
+     error ("Builtin function %s requires the -mspe option", name);
++  else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
++	   == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
++    error ("Builtin function %s requires the -mhard-dfp and"
++	   "-mpower8-vector options", name);
++  else if ((fnmask & RS6000_BTM_DFP) != 0)
++    error ("Builtin function %s requires the -mhard-dfp option", name);
++  else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
++    error ("Builtin function %s requires the -mpower8-vector option", name);
+   else
+     error ("Builtin function %s is not supported with the current options",
+ 	   name);
+@@ -13762,6 +13835,9 @@
+   uintTI_type_internal_node = unsigned_intTI_type_node;
+   float_type_internal_node = float_type_node;
+   double_type_internal_node = double_type_node;
++  long_double_type_internal_node = long_double_type_node;
++  dfloat64_type_internal_node = dfloat64_type_node;
++  dfloat128_type_internal_node = dfloat128_type_node;
+   void_type_internal_node = void_type_node;
+ 
+   /* Initialize the modes for builtin_function_type, mapping a machine mode to
+@@ -13776,6 +13852,9 @@
+   builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
+   builtin_mode_to_type[SFmode][0] = float_type_node;
+   builtin_mode_to_type[DFmode][0] = double_type_node;
++  builtin_mode_to_type[TFmode][0] = long_double_type_node;
++  builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
++  builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
+   builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
+   builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
+   builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
+@@ -14868,6 +14947,8 @@
+       /* unsigned 1 argument functions.  */
+     case CRYPTO_BUILTIN_VSBOX:
+     case P8V_BUILTIN_VGBBD:
++    case MISC_BUILTIN_CDTBCD:
++    case MISC_BUILTIN_CBCDTD:
+       h.uns_p[0] = 1;
+       h.uns_p[1] = 1;
+       break;
+@@ -14886,6 +14967,11 @@
+     case CRYPTO_BUILTIN_VPMSUMW:
+     case CRYPTO_BUILTIN_VPMSUMD:
+     case CRYPTO_BUILTIN_VPMSUM:
++    case MISC_BUILTIN_ADDG6S:
++    case MISC_BUILTIN_DIVWEU:
++    case MISC_BUILTIN_DIVWEUO:
++    case MISC_BUILTIN_DIVDEU:
++    case MISC_BUILTIN_DIVDEUO:
+       h.uns_p[0] = 1;
+       h.uns_p[1] = 1;
+       h.uns_p[2] = 1;
+@@ -14947,9 +15033,18 @@
+       /* signed args, unsigned return.  */
+     case VSX_BUILTIN_XVCVDPUXDS_UNS:
+     case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
++    case MISC_BUILTIN_UNPACK_TD:
++    case MISC_BUILTIN_UNPACK_V1TI:
+       h.uns_p[0] = 1;
+       break;
+ 
++      /* unsigned arguments for 128-bit pack instructions.  */
++    case MISC_BUILTIN_PACK_TD:
++    case MISC_BUILTIN_PACK_V1TI:
++      h.uns_p[1] = 1;
++      h.uns_p[2] = 1;
++      break;
++
+     default:
+       break;
+     }
+@@ -31203,6 +31298,7 @@
+   { "power8-vector",	 RS6000_BTM_P8_VECTOR,	false, false },
+   { "crypto",		 RS6000_BTM_CRYPTO,	false, false },
+   { "htm",		 RS6000_BTM_HTM,	false, false },
++  { "hard-dfp",		 RS6000_BTM_DFP,	false, false },
+ };
+ 
+ /* Option variables that we want to support inside attribute((target)) and
 Index: gcc/config/rs6000/vsx.md
 ===================================================================
 --- a/src/gcc/config/rs6000/vsx.md	(.../tags/gcc_4_9_0_release)
@@ -3845,11 +6311,520 @@ Index: gcc/config/rs6000/vsx.md
    [(set_attr "type" "vecperm")])
  
  ;; Shift left double by word immediate
+Index: gcc/config/rs6000/rs6000.h
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.h	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/rs6000/rs6000.h	(.../branches/gcc-4_9-branch)
+@@ -2516,6 +2516,7 @@
+ #define RS6000_BTM_FRSQRTES	MASK_POPCNTB	/* FRSQRTES instruction.  */
+ #define RS6000_BTM_POPCNTD	MASK_POPCNTD	/* Target supports ISA 2.06.  */
+ #define RS6000_BTM_CELL		MASK_FPRND	/* Target is cell powerpc.  */
++#define RS6000_BTM_DFP		MASK_DFP	/* Decimal floating point.  */
+ 
+ #define RS6000_BTM_COMMON	(RS6000_BTM_ALTIVEC			\
+ 				 | RS6000_BTM_VSX			\
+@@ -2527,7 +2528,8 @@
+ 				 | RS6000_BTM_FRSQRTES			\
+ 				 | RS6000_BTM_HTM			\
+ 				 | RS6000_BTM_POPCNTD			\
+-				 | RS6000_BTM_CELL)
++				 | RS6000_BTM_CELL			\
++				 | RS6000_BTM_DFP)
+ 
+ /* Define builtin enum index.  */
+ 
+@@ -2622,6 +2624,9 @@
+   RS6000_BTI_UINTTI,		 /* unsigned_intTI_type_node */
+   RS6000_BTI_float,	         /* float_type_node */
+   RS6000_BTI_double,	         /* double_type_node */
++  RS6000_BTI_long_double,        /* long_double_type_node */
++  RS6000_BTI_dfloat64,		 /* dfloat64_type_node */
++  RS6000_BTI_dfloat128,		 /* dfloat128_type_node */
+   RS6000_BTI_void,	         /* void_type_node */
+   RS6000_BTI_MAX
+ };
+@@ -2673,6 +2678,9 @@
+ #define uintTI_type_internal_node	 (rs6000_builtin_types[RS6000_BTI_UINTTI])
+ #define float_type_internal_node	 (rs6000_builtin_types[RS6000_BTI_float])
+ #define double_type_internal_node	 (rs6000_builtin_types[RS6000_BTI_double])
++#define long_double_type_internal_node	 (rs6000_builtin_types[RS6000_BTI_long_double])
++#define dfloat64_type_internal_node	 (rs6000_builtin_types[RS6000_BTI_dfloat64])
++#define dfloat128_type_internal_node	 (rs6000_builtin_types[RS6000_BTI_dfloat128])
+ #define void_type_internal_node		 (rs6000_builtin_types[RS6000_BTI_void])
+ 
+ extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
+Index: gcc/config/rs6000/altivec.md
+===================================================================
+--- a/src/gcc/config/rs6000/altivec.md	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/rs6000/altivec.md	(.../branches/gcc-4_9-branch)
+@@ -143,6 +143,9 @@
+    UNSPEC_VSUBEUQM
+    UNSPEC_VSUBECUQ
+    UNSPEC_VBPERMQ
++   UNSPEC_BCDADD
++   UNSPEC_BCDSUB
++   UNSPEC_BCD_OVERFLOW
+ ])
+ 
+ (define_c_enum "unspecv"
+@@ -3334,3 +3337,112 @@
+   "vbpermq %0,%1,%2"
+   [(set_attr "length" "4")
+    (set_attr "type" "vecsimple")])
++
++;; Decimal Integer operations
++(define_int_iterator UNSPEC_BCD_ADD_SUB [UNSPEC_BCDADD UNSPEC_BCDSUB])
++
++(define_int_attr bcd_add_sub [(UNSPEC_BCDADD "add")
++			      (UNSPEC_BCDSUB "sub")])
++
++(define_code_iterator BCD_TEST [eq lt gt unordered])
++
++(define_insn "bcd<bcd_add_sub>"
++  [(set (match_operand:V1TI 0 "register_operand" "")
++	(unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")
++		      (match_operand:V1TI 2 "register_operand" "")
++		      (match_operand:QI 3 "const_0_to_1_operand" "")]
++		     UNSPEC_BCD_ADD_SUB))
++   (clobber (reg:CCFP 74))]
++  "TARGET_P8_VECTOR"
++  "bcd<bcd_add_sub>. %0,%1,%2,%3"
++  [(set_attr "length" "4")
++   (set_attr "type" "vecsimple")])
++
++;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we
++;; can use the unordered test for BCD nans and add/subtracts that overflow.  An
++;; UNORDERED test on an integer type (like V1TImode) is not defined.  The type
++;; probably should be one that can go in the VMX (Altivec) registers, so we
++;; can't use DDmode or DFmode.
++(define_insn "*bcd<bcd_add_sub>_test"
++  [(set (reg:CCFP 74)
++	(compare:CCFP
++	 (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v")
++		       (match_operand:V1TI 2 "register_operand" "v")
++		       (match_operand:QI 3 "const_0_to_1_operand" "i")]
++		      UNSPEC_BCD_ADD_SUB)
++	 (match_operand:V2DF 4 "zero_constant" "j")))
++   (clobber (match_scratch:V1TI 0 "=v"))]
++  "TARGET_P8_VECTOR"
++  "bcd<bcd_add_sub>. %0,%1,%2,%3"
++  [(set_attr "length" "4")
++   (set_attr "type" "vecsimple")])
++
++(define_insn "*bcd<bcd_add_sub>_test2"
++  [(set (match_operand:V1TI 0 "register_operand" "=v")
++	(unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v")
++		      (match_operand:V1TI 2 "register_operand" "v")
++		      (match_operand:QI 3 "const_0_to_1_operand" "i")]
++		     UNSPEC_BCD_ADD_SUB))
++   (set (reg:CCFP 74)
++	(compare:CCFP
++	 (unspec:V2DF [(match_dup 1)
++		       (match_dup 2)
++		       (match_dup 3)]
++		      UNSPEC_BCD_ADD_SUB)
++	 (match_operand:V2DF 4 "zero_constant" "j")))]
++  "TARGET_P8_VECTOR"
++  "bcd<bcd_add_sub>. %0,%1,%2,%3"
++  [(set_attr "length" "4")
++   (set_attr "type" "vecsimple")])
++
++(define_expand "bcd<bcd_add_sub>_<code>"
++  [(parallel [(set (reg:CCFP 74)
++		   (compare:CCFP
++		    (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")
++				  (match_operand:V1TI 2 "register_operand" "")
++				  (match_operand:QI 3 "const_0_to_1_operand" "")]
++				 UNSPEC_BCD_ADD_SUB)
++		    (match_dup 4)))
++	      (clobber (match_scratch:V1TI 5 ""))])
++   (set (match_operand:SI 0 "register_operand" "")
++	(BCD_TEST:SI (reg:CCFP 74)
++		     (const_int 0)))]
++  "TARGET_P8_VECTOR"
++{
++  operands[4] = CONST0_RTX (V2DFmode);
++})
++
++;; Peephole2 pattern to combine a bcdadd/bcdsub that calculates the value and
++;; the bcdadd/bcdsub that tests the value.  The combiner won't work since
++;; CR6 is a hard coded register.  Unfortunately, all of the Altivec predicate
++;; support is hard coded to use the fixed register CR6 instead of creating
++;; a register class for CR6.
++
++(define_peephole2
++  [(parallel [(set (match_operand:V1TI 0 "register_operand" "")
++		   (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")
++				 (match_operand:V1TI 2 "register_operand" "")
++				 (match_operand:QI 3 "const_0_to_1_operand" "")]
++				UNSPEC_BCD_ADD_SUB))
++	      (clobber (reg:CCFP 74))])
++   (parallel [(set (reg:CCFP 74)
++		   (compare:CCFP
++		    (unspec:V2DF [(match_dup 1)
++				  (match_dup 2)
++				  (match_dup 3)]
++				 UNSPEC_BCD_ADD_SUB)
++		    (match_operand:V2DF 4 "zero_constant" "")))
++	      (clobber (match_operand:V1TI 5 "register_operand" ""))])]
++  "TARGET_P8_VECTOR"
++  [(parallel [(set (match_dup 0)
++		   (unspec:V1TI [(match_dup 1)
++				 (match_dup 2)
++				 (match_dup 3)]
++				UNSPEC_BCD_ADD_SUB))
++	      (set (reg:CCFP 74)
++		   (compare:CCFP
++		    (unspec:V2DF [(match_dup 1)
++				  (match_dup 2)
++				  (match_dup 3)]
++				 UNSPEC_BCD_ADD_SUB)
++		    (match_dup 4)))])])
+Index: gcc/config/rs6000/dfp.md
+===================================================================
+--- a/src/gcc/config/rs6000/dfp.md	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/rs6000/dfp.md	(.../branches/gcc-4_9-branch)
+@@ -322,3 +322,72 @@
+   "TARGET_DFP"
+   "dctfixq %0,%1"
+   [(set_attr "type" "fp")])
++
++
++;; Decimal builtin support
++
++(define_c_enum "unspec"
++  [UNSPEC_DDEDPD
++   UNSPEC_DENBCD
++   UNSPEC_DXEX
++   UNSPEC_DIEX
++   UNSPEC_DSCLI
++   UNSPEC_DSCRI])
++
++(define_mode_iterator D64_D128 [DD TD])
++
++(define_mode_attr dfp_suffix [(DD "")
++			      (TD "q")])
++
++(define_insn "dfp_ddedpd_<mode>"
++  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
++	(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")
++			  (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
++			 UNSPEC_DDEDPD))]
++  "TARGET_DFP"
++  "ddedpd<dfp_suffix> %1,%0,%2"
++  [(set_attr "type" "fp")])
++
++(define_insn "dfp_denbcd_<mode>"
++  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
++	(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")
++			  (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
++			 UNSPEC_DENBCD))]
++  "TARGET_DFP"
++  "denbcd<dfp_suffix> %1,%0,%2"
++  [(set_attr "type" "fp")])
++
++(define_insn "dfp_dxex_<mode>"
++  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
++	(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]
++			 UNSPEC_DXEX))]
++  "TARGET_DFP"
++  "dxex<dfp_suffix> %0,%1"
++  [(set_attr "type" "fp")])
++
++(define_insn "dfp_diex_<mode>"
++  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
++	(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
++			  (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
++			 UNSPEC_DXEX))]
++  "TARGET_DFP"
++  "diex<dfp_suffix> %0,%1,%2"
++  [(set_attr "type" "fp")])
++
++(define_insn "dfp_dscli_<mode>"
++  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
++	(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
++			  (match_operand:QI 2 "immediate_operand" "i")]
++			 UNSPEC_DSCLI))]
++  "TARGET_DFP"
++  "dscli<dfp_suffix> %0,%1,%2"
++  [(set_attr "type" "fp")])
++
++(define_insn "dfp_dscri_<mode>"
++  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
++	(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
++			  (match_operand:QI 2 "immediate_operand" "i")]
++			 UNSPEC_DSCRI))]
++  "TARGET_DFP"
++  "dscri<dfp_suffix> %0,%1,%2"
++  [(set_attr "type" "fp")])
+Index: gcc/config/rs6000/sync.md
+===================================================================
+--- a/src/gcc/config/rs6000/sync.md	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/rs6000/sync.md	(.../branches/gcc-4_9-branch)
+@@ -107,10 +107,17 @@
+   "isync"
+   [(set_attr "type" "isync")])
+ 
++;; Types that we should provide atomic instructions for.
++(define_mode_iterator AINT [QI
++			    HI
++			    SI
++			    (DI "TARGET_POWERPC64")
++			    (TI "TARGET_SYNC_TI")])
++
+ ;; The control dependency used for load dependency described
+ ;; in B.2.3 of the Power ISA 2.06B.
+ (define_insn "loadsync_<mode>"
+-  [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")]
++  [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")]
+ 			UNSPECV_ISYNC)
+    (clobber (match_scratch:CC 1 "=y"))]
+   ""
+@@ -118,19 +125,57 @@
+   [(set_attr "type" "isync")
+    (set_attr "length" "12")])
+ 
++(define_insn "load_quadpti"
++  [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
++	(unspec:PTI
++	 [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))]
++  "TARGET_SYNC_TI
++   && !reg_mentioned_p (operands[0], operands[1])"
++  "lq %0,%1"
++  [(set_attr "type" "load")
++   (set_attr "length" "4")])
++
+ (define_expand "atomic_load<mode>"
+-  [(set (match_operand:INT1 0 "register_operand" "")		;; output
+-	(match_operand:INT1 1 "memory_operand" ""))		;; memory
++  [(set (match_operand:AINT 0 "register_operand" "")		;; output
++	(match_operand:AINT 1 "memory_operand" ""))		;; memory
+    (use (match_operand:SI 2 "const_int_operand" ""))]		;; model
+   ""
+ {
++  if (<MODE>mode == TImode && !TARGET_SYNC_TI)
++    FAIL;
++
+   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
+ 
+   if (model == MEMMODEL_SEQ_CST)
+     emit_insn (gen_hwsync ());
+ 
+-  emit_move_insn (operands[0], operands[1]);
++  if (<MODE>mode != TImode)
++    emit_move_insn (operands[0], operands[1]);
++  else
++    {
++      rtx op0 = operands[0];
++      rtx op1 = operands[1];
++      rtx pti_reg = gen_reg_rtx (PTImode);
+ 
++      // Can't have indexed address for 'lq'
++      if (indexed_address (XEXP (op1, 0), TImode))
++	{
++	  rtx old_addr = XEXP (op1, 0);
++	  rtx new_addr = force_reg (Pmode, old_addr);
++	  operands[1] = op1 = replace_equiv_address (op1, new_addr);
++	}
++
++      emit_insn (gen_load_quadpti (pti_reg, op1));
++
++      if (WORDS_BIG_ENDIAN)
++	emit_move_insn (op0, gen_lowpart (TImode, pti_reg));
++      else
++	{
++	  emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti_reg));
++	  emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti_reg));
++	}
++    }
++
+   switch (model)
+     {
+     case MEMMODEL_RELAXED:
+@@ -146,12 +191,24 @@
+   DONE;
+ })
+ 
++(define_insn "store_quadpti"
++  [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ")
++	(unspec:PTI
++	 [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))]
++  "TARGET_SYNC_TI"
++  "stq %1,%0"
++  [(set_attr "type" "store")
++   (set_attr "length" "4")])
++
+ (define_expand "atomic_store<mode>"
+-  [(set (match_operand:INT1 0 "memory_operand" "")		;; memory
+-	(match_operand:INT1 1 "register_operand" ""))		;; input
++  [(set (match_operand:AINT 0 "memory_operand" "")		;; memory
++	(match_operand:AINT 1 "register_operand" ""))		;; input
+    (use (match_operand:SI 2 "const_int_operand" ""))]		;; model
+   ""
+ {
++  if (<MODE>mode == TImode && !TARGET_SYNC_TI)
++    FAIL;
++
+   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
+   switch (model)
+     {
+@@ -166,7 +223,33 @@
+     default:
+       gcc_unreachable ();
+     }
+-  emit_move_insn (operands[0], operands[1]);
++  if (<MODE>mode != TImode)
++    emit_move_insn (operands[0], operands[1]);
++  else
++    {
++      rtx op0 = operands[0];
++      rtx op1 = operands[1];
++      rtx pti_reg = gen_reg_rtx (PTImode);
++
++      // Can't have indexed address for 'stq'
++      if (indexed_address (XEXP (op0, 0), TImode))
++	{
++	  rtx old_addr = XEXP (op0, 0);
++	  rtx new_addr = force_reg (Pmode, old_addr);
++	  operands[0] = op0 = replace_equiv_address (op0, new_addr);
++	}
++
++      if (WORDS_BIG_ENDIAN)
++	emit_move_insn (pti_reg, gen_lowpart (PTImode, op1));
++      else
++	{
++	  emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode, op1));
++	  emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode, op1));
++	}
++
++      emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg));
++    }
++
+   DONE;
+ })
+ 
+@@ -180,14 +263,6 @@
+ 			      SI
+ 			      (DI "TARGET_POWERPC64")])
+ 
+-;; Types that we should provide atomic instructions for.
+-
+-(define_mode_iterator AINT [QI
+-			    HI
+-			    SI
+-			    (DI "TARGET_POWERPC64")
+-			    (TI "TARGET_SYNC_TI")])
+-
+ (define_insn "load_locked<mode>"
+   [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")
+ 	(unspec_volatile:ATOMIC
 Index: gcc/config/rs6000/rs6000.md
 ===================================================================
 --- a/src/gcc/config/rs6000/rs6000.md	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/config/rs6000/rs6000.md	(.../branches/gcc-4_9-branch)
-@@ -9395,7 +9395,8 @@
+@@ -125,6 +125,16 @@
+    UNSPEC_P8V_MTVSRD
+    UNSPEC_P8V_XXPERMDI
+    UNSPEC_P8V_RELOAD_FROM_VSX
++   UNSPEC_ADDG6S
++   UNSPEC_CDTBCD
++   UNSPEC_CBCDTD
++   UNSPEC_DIVE
++   UNSPEC_DIVEO
++   UNSPEC_DIVEU
++   UNSPEC_DIVEUO
++   UNSPEC_UNPACK_128BIT
++   UNSPEC_PACK_128BIT
++   UNSPEC_LSQ
+   ])
+ 
+ ;;
+@@ -481,6 +491,10 @@
+ 					 (V2DF	"X,X,X,X,X")
+ 					 (V1TI	"X,X,X,X,X")])
+ 
++;; Mode attribute to give the correct type for integer divides
++(define_mode_attr idiv_ldiv [(SI "idiv")
++			     (DI "ldiv")])
++
+ 
+ ;; Start with fixed-point load and store insns.  Here we put only the more
+ ;; complex forms.  Basic data transfer is done later.
+@@ -2755,10 +2769,7 @@
+ 		  (match_operand:GPR 2 "gpc_reg_operand" "r")))]
+   ""
+   "div<wd>u %0,%1,%2"
+-   [(set (attr "type")
+-      (cond [(match_operand:SI 0 "" "")
+-		(const_string "idiv")]
+-	(const_string "ldiv")))])
++   [(set_attr "type" "<idiv_ldiv>")])
+ 
+ 
+ ;; For powers of two we can do srai/aze for divide and then adjust for
+@@ -2782,10 +2793,7 @@
+ 		 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
+   ""
+   "div<wd> %0,%1,%2"
+-  [(set (attr "type")
+-     (cond [(match_operand:SI 0 "" "")
+-		(const_string "idiv")]
+-	(const_string "ldiv")))])
++  [(set_attr "type" "<idiv_ldiv>")])
+ 
+ (define_expand "mod<mode>3"
+   [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
+@@ -6534,6 +6542,49 @@
+   [(set_attr "length" "8")
+    (set_attr "type" "fpload")])
+ 
++;; Define the TImode operations that can be done in a small number
++;; of instructions.  The & constraints are to prevent the register
++;; allocator from allocating registers that overlap with the inputs
++;; (for example, having an input in 7,8 and an output in 6,7).  We
++;; also allow for the output being the same as one of the inputs.
++
++(define_insn "addti3"
++  [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
++	(plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
++		 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
++  "TARGET_64BIT"
++{
++  if (WORDS_BIG_ENDIAN)
++    return (GET_CODE (operands[2])) != CONST_INT
++	    ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
++	    : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
++  else
++    return (GET_CODE (operands[2])) != CONST_INT
++	    ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
++	    : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
++}
++  [(set_attr "type" "two")
++   (set_attr "length" "8")])
++
++(define_insn "subti3"
++  [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
++	(minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
++		  (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
++  "TARGET_64BIT"
++{
++  if (WORDS_BIG_ENDIAN)
++    return (GET_CODE (operands[1]) != CONST_INT)
++	    ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
++	    : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
++  else
++    return (GET_CODE (operands[1]) != CONST_INT)
++	    ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
++	    : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
++}
++  [(set_attr "type" "two")
++   (set_attr "length" "8")])
++
++
+ ;; Define the DImode operations that can be done in a small number
+ ;; of instructions.  The & constraints are to prevent the register
+ ;; allocator from allocating registers that overlap with the inputs
+@@ -9395,7 +9446,8 @@
  	(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
    "! TARGET_POWERPC64 
     && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) 
@@ -3859,6 +6834,199 @@ Index: gcc/config/rs6000/rs6000.md
     && (gpc_reg_operand (operands[0], <MODE>mode)
         || gpc_reg_operand (operands[1], <MODE>mode))"
    "#"
+@@ -15691,7 +15743,192 @@
+ })
+ 
+ 
++;; Miscellaneous ISA 2.06 (power7) instructions
++(define_insn "addg6s"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(unspec:SI [(match_operand:SI 1 "register_operand" "r")
++		    (match_operand:SI 2 "register_operand" "r")]
++		   UNSPEC_ADDG6S))]
++  "TARGET_POPCNTD"
++  "addg6s %0,%1,%2"
++  [(set_attr "type" "integer")
++   (set_attr "length" "4")])
+ 
++(define_insn "cdtbcd"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
++		   UNSPEC_CDTBCD))]
++  "TARGET_POPCNTD"
++  "cdtbcd %0,%1"
++  [(set_attr "type" "integer")
++   (set_attr "length" "4")])
++
++(define_insn "cbcdtd"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
++		   UNSPEC_CBCDTD))]
++  "TARGET_POPCNTD"
++  "cbcdtd %0,%1"
++  [(set_attr "type" "integer")
++   (set_attr "length" "4")])
++
++(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
++					UNSPEC_DIVEO
++					UNSPEC_DIVEU
++					UNSPEC_DIVEUO])
++
++(define_int_attr div_extend [(UNSPEC_DIVE	"e")
++			     (UNSPEC_DIVEO	"eo")
++			     (UNSPEC_DIVEU	"eu")
++			     (UNSPEC_DIVEUO	"euo")])
++
++(define_insn "div<div_extend>_<mode>"
++  [(set (match_operand:GPR 0 "register_operand" "=r")
++	(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
++		     (match_operand:GPR 2 "register_operand" "r")]
++		    UNSPEC_DIV_EXTEND))]
++  "TARGET_POPCNTD"
++  "div<wd><div_extend> %0,%1,%2"
++  [(set_attr "type" "<idiv_ldiv>")])
++
++
++;; Pack/unpack 128-bit floating point types that take 2 scalar registers
++
++; Type of the 64-bit part when packing/unpacking 128-bit floating point types
++(define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
++
++(define_expand "unpack<mode>"
++  [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
++	(unspec:<FP128_64>
++	 [(match_operand:FMOVE128 1 "register_operand" "")
++	  (match_operand:QI 2 "const_0_to_1_operand" "")]
++	 UNSPEC_UNPACK_128BIT))]
++  ""
++  "")
++
++;; The Advance Toolchain 7.0-3 added private builtins: __builtin_longdouble_dw0
++;; and __builtin_longdouble_dw1 to optimize glibc.  Add support for these
++;; builtins here.
++
++(define_expand "unpacktf_0"
++  [(set (match_operand:DF 0 "nonimmediate_operand" "")
++	(unspec:DF [(match_operand:TF 1 "register_operand" "")
++		    (const_int 0)]
++	 UNSPEC_UNPACK_128BIT))]
++  ""
++  "")
++
++(define_expand "unpacktf_1"
++  [(set (match_operand:DF 0 "nonimmediate_operand" "")
++	(unspec:DF [(match_operand:TF 1 "register_operand" "")
++		    (const_int 1)]
++	 UNSPEC_UNPACK_128BIT))]
++  ""
++  "")
++
++(define_insn_and_split "unpack<mode>_dm"
++  [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
++	(unspec:<FP128_64>
++	 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
++	  (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
++	 UNSPEC_UNPACK_128BIT))]
++  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
++  "#"
++  "&& reload_completed"
++  [(set (match_dup 0) (match_dup 3))]
++{
++  unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
++
++  if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
++    {
++      emit_note (NOTE_INSN_DELETED);
++      DONE;
++    }
++
++  operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
++}
++  [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
++   (set_attr "length" "4")])
++
++(define_insn_and_split "unpack<mode>_nodm"
++  [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
++	(unspec:<FP128_64>
++	 [(match_operand:FMOVE128 1 "register_operand" "d,d")
++	  (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
++	 UNSPEC_UNPACK_128BIT))]
++  "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
++  "#"
++  "&& reload_completed"
++  [(set (match_dup 0) (match_dup 3))]
++{
++  unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
++
++  if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
++    {
++      emit_note (NOTE_INSN_DELETED);
++      DONE;
++    }
++
++  operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
++}
++  [(set_attr "type" "fp,fpstore")
++   (set_attr "length" "4")])
++
++(define_insn_and_split "pack<mode>"
++  [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
++	(unspec:FMOVE128
++	 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
++	  (match_operand:<FP128_64> 2 "register_operand" "d,d")]
++	 UNSPEC_PACK_128BIT))]
++  ""
++  "@
++   fmr %L0,%2
++   #"
++  "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
++  [(set (match_dup 3) (match_dup 1))
++   (set (match_dup 4) (match_dup 2))]
++{
++  unsigned dest_hi = REGNO (operands[0]);
++  unsigned dest_lo = dest_hi + 1;
++
++  gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
++  gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
++
++  operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
++  operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
++}
++  [(set_attr "type" "fp,fp")
++   (set_attr "length" "4,8")])
++
++(define_insn "unpackv1ti"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
++		    (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
++	 UNSPEC_UNPACK_128BIT))]
++  "TARGET_VSX"
++{
++  if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
++    return ASM_COMMENT_START " xxpermdi to same register";
++
++  operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
++  return "xxpermdi %x0,%x1,%x1,%3";
++}
++  [(set_attr "type" "vecperm")
++   (set_attr "length" "4")])
++
++(define_insn "packv1ti"
++  [(set (match_operand:V1TI 0 "register_operand" "=wa")
++	(unspec:V1TI
++	 [(match_operand:DI 1 "register_operand" "d")
++	  (match_operand:DI 2 "register_operand" "d")]
++	 UNSPEC_PACK_128BIT))]
++  "TARGET_VSX"
++  "xxpermdi %x0,%x1,%x2,0"
++  [(set_attr "type" "vecperm")
++   (set_attr "length" "4")])
++
++
++
+ (include "sync.md")
+ (include "vector.md")
+ (include "vsx.md")
 Index: gcc/config/msp430/msp430-opts.h
 ===================================================================
 --- a/src/gcc/config/msp430/msp430-opts.h	(.../tags/gcc_4_9_0_release)
@@ -3928,7 +7096,7 @@ Index: gcc/config/msp430/msp430.md
  	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
  		 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
 -  "optimize > 2 && msp430_hwmult_enabled ()"
-+  "optimize > 2 && msp430_hwmult_type != NONE && ! msp430_is_interrupt_func ()"
++  "optimize > 2 && msp430_hwmult_type != NONE"
    "*
 -    if (msp430_is_f5_mcu ())
 -      return \"MOV.W %1, &0x04C2 { MOV.W %2, &0x04C8 { MOV.W &0x04CA, %L0 { MOV.W &0x04CC, %H0\";
@@ -3987,7 +7155,7 @@ Index: gcc/config/msp430/msp430.md
 +      return \"PUSH.W sr { DINT { MOV.W %L1, &0x04D0 { MOV.W %H1, &0x04D2 { MOV.W %L2, &0x04E0 { MOV.W %H2, &0x04E2 { MOV.W &0x04E4, %A0 { MOV.W &0x04E6, %B0 { MOV.W &0x04E8, %C0 { MOV.W &0x04EA, %D0 { POP.W sr\";
      else
 -      return \"MOV.W %L1, &0x0140 { MOV.W %H1, &0x0141 { MOV.W %L2, &0x0150 { MOV.W %H2, &0x0152 { MOV.W &0x0154, %A0 { MOV.W &0x0156, %B0 { MOV.W &0x0158, %C0 { MOV.W &0x015A, %D0\";
-+      return \"PUSH.W sr { DINT { MOV.W %L1, &0x0140 { MOV.W %H1, &0x0141 { MOV.W %L2, &0x0150 { MOV.W %H2, &0x0152 { MOV.W &0x0154, %A0 { MOV.W &0x0156, %B0 { MOV.W &0x0158, %C0 { MOV.W &0x015A, %D0 { POP.W sr\";
++      return \"PUSH.W sr { DINT { MOV.W %L1, &0x0140 { MOV.W %H1, &0x0142 { MOV.W %L2, &0x0150 { MOV.W %H2, &0x0152 { MOV.W &0x0154, %A0 { MOV.W &0x0156, %B0 { MOV.W &0x0158, %C0 { MOV.W &0x015A, %D0 { POP.W sr\";
    "
  )
 Index: gcc/config/msp430/msp430.c
@@ -4159,6 +7327,15 @@ Index: gcc/config/msp430/msp430.c
  	    name = "__mulsi2_hw32";
  	  else
  	    name = "__mulsi2";
+@@ -2203,7 +2162,7 @@
+ 	 because builtins are expanded before the frame layout is determined.  */
+       fprintf (file, "%d",
+ 	       msp430_initial_elimination_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM)
+-	        - 2);
++	       - (TARGET_LARGE ? 4 : 2));
+       return;
+ 
+     case 'J':
 Index: gcc/config/msp430/msp430.opt
 ===================================================================
 --- a/src/gcc/config/msp430/msp430.opt	(.../tags/gcc_4_9_0_release)