* Update to SVN 20140623 (r211892) from the gcc-4_9-branch.

git-svn-id: svn://svn.debian.org/svn/gcccvs/branches/sid/gcc-4.9@7466 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca

2 files changed, 692 insertions, 35 deletions

diff --git a/debian/changelog b/debian/changelog
index 74889f3..1cd46e2 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,6 @@
 gcc-4.9 (4.9.0-8) UNRELEASED; urgency=medium
 
-  * Update to SVN 20140618 (r211773) from the gcc-4_9-branch.
+  * Update to SVN 20140623 (r211892) from the gcc-4_9-branch.
 
   * Don't ignore dpkg-shlibdeps errors for libstdc++6, left over from initial
     4.9 uploads.
@@ -12,7 +12,7 @@ gcc-4.9 (4.9.0-8) UNRELEASED; urgency=medium
   * Update libstdc++ and libvtv symbols files for builds configured with
     --enable-vtable-verify.
 
- -- Matthias Klose <doko@debian.org>  Wed, 18 Jun 2014 10:55:20 +0200
+ -- Matthias Klose <doko@debian.org>  Mon, 23 Jun 2014 16:02:40 +0200
 
 gcc-4.9 (4.9.0-7) unstable; urgency=medium
 
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index b5c61b8..3a094e0 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 4.9 branch upto 20140618 (r211773).
+# DP: updates from the 4.9 branch upto 20140623 (r211892).
 
 last_update()
 {
 	cat > ${dir}LAST_UPDATED <EOF
-Wed Jun 18 11:17:45 CEST 2014
-Wed Jun 18 09:17:45 UTC 2014 (revision 211773)
+Mon Jun 23 14:48:13 CEST 2014
+Mon Jun 23 12:48:13 UTC 2014 (revision 211892)
 EOF
 }
 
@@ -3930,6 +3930,32 @@ Index: gcc/c/c-decl.c
  	    {
  	      if (name)
  		error_at (loc, "%<_Alignas%> specifiers cannot reduce "
+Index: gcc/cgraph.c
+===================================================================
+--- a/src/gcc/cgraph.c	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/cgraph.c	(.../branches/gcc-4_9-branch)
+@@ -2566,11 +2566,16 @@
+       skipped_thunk = true;
+     }
+ 
+-  if (skipped_thunk
+-      && (!node2->clone_of
+-	  || !node2->clone.args_to_skip
+-	  || !bitmap_bit_p (node2->clone.args_to_skip, 0)))
+-    return false;
++  if (skipped_thunk)
++    {
++      if (!node2->clone.args_to_skip
++	  || !bitmap_bit_p (node2->clone.args_to_skip, 0))
++	return false;
++      if (node2->former_clone_of == node->decl)
++	return true;
++      else if (!node2->clone_of)
++	return false;
++    }
+ 
+   while (node != node2 && node2)
+     node2 = node2->clone_of;
 Index: gcc/cgraph.h
 ===================================================================
 --- a/src/gcc/cgraph.h	(.../tags/gcc_4_9_0_release)
@@ -3948,7 +3974,7 @@ Index: gcc/DATESTAMP
 +++ b/src/gcc/DATESTAMP	(.../branches/gcc-4_9-branch)
 @@ -1 +1 @@
 -20140422
-+20140618
++20140623
 Index: gcc/tree-tailcall.c
 ===================================================================
 --- a/src/gcc/tree-tailcall.c	(.../tags/gcc_4_9_0_release)
@@ -4841,7 +4867,71 @@ Index: gcc/ChangeLog
 ===================================================================
 --- a/src/gcc/ChangeLog	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,1185 @@
+@@ -1,3 +1,1249 @@
++2014-06-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
++
++	* config/aarch64/aarch64-simd.md (aarch64_sqdmulh_lane<mode>):
++	New expander.
++	(aarch64_sqrdmulh_lane<mode>): Likewise.
++	(aarch64_sq<r>dmulh_lane<mode>): Rename to...
++	(aarch64_sq<r>dmulh_lane<mode>_interna): ...this.
++	(aarch64_sqdmulh_laneq<mode>): New expander.
++	(aarch64_sqrdmulh_laneq<mode>): Likewise.
++	(aarch64_sq<r>dmulh_laneq<mode>): Rename to...
++	(aarch64_sq<r>dmulh_laneq<mode>_internal): ...this.
++	(aarch64_sqdmulh_lane<mode>): New expander.
++	(aarch64_sqrdmulh_lane<mode>): Likewise.
++	(aarch64_sq<r>dmulh_lane<mode>): Rename to...
++	(aarch64_sq<r>dmulh_lane<mode>_internal): ...this.
++	(aarch64_sqdmlal_lane<mode>): Add lane flip for big-endian.
++	(aarch64_sqdmlal_laneq<mode>): Likewise.
++	(aarch64_sqdmlsl_lane<mode>): Likewise.
++	(aarch64_sqdmlsl_laneq<mode>): Likewise.
++	(aarch64_sqdmlal2_lane<mode>): Likewise.
++	(aarch64_sqdmlal2_laneq<mode>): Likewise.
++	(aarch64_sqdmlsl2_lane<mode>): Likewise.
++	(aarch64_sqdmlsl2_laneq<mode>): Likewise.
++	(aarch64_sqdmull_lane<mode>): Likewise.
++	(aarch64_sqdmull_laneq<mode>): Likewise.
++	(aarch64_sqdmull2_lane<mode>): Likewise.
++	(aarch64_sqdmull2_laneq<mode>): Likewise.
++
++2014-06-20  Martin Jambor  <mjambor@suse.cz>
++
++	PR ipa/61540
++	* ipa-prop.c (impossible_devirt_target): New function.
++	(try_make_edge_direct_virtual_call): Use it, also instead of
++	asserting.
++
++2014-06-20  Martin Jambor  <mjambor@suse.cz>
++
++	PR ipa/61211
++	* cgraph.c (clone_of_p): Allow skipped_branch to deal with
++	expanded clones.
++
++2014-06-20  Chung-Lin Tang  <cltang@codesourcery.com>
++
++	Backport from mainline
++
++	2014-06-20  Julian Brown  <julian@codesourcery.com>
++	            Chung-Lin Tang  <cltang@codesourcery.com>
++
++	* config/arm/arm.c (arm_output_mi_thunk): Fix offset for
++	TARGET_THUMB1_ONLY. Add comments.
++
++2014-06-18  Uros Bizjak  <ubizjak@gmail.com>
++
++	Backport from mainline
++	2014-06-16  Uros Bizjak  <ubizjak@gmail.com>
++
++	* config/i386/i386.c (decide_alg): Correctly handle
++	maximum size of stringop algorithm.
++
++2014-06-18  Richard Henderson  <rth@redhat.com>
++
++	PR target/61545
++	* config/aarch64/aarch64.md (tlsdesc_small): Clobber CC_REGNUM.
++
 +2014-06-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 +
 +	PR target/61483
@@ -6027,7 +6117,7 @@ Index: gcc/ChangeLog
  2014-04-22  Release Manager
  
  	* GCC 4.9.0 released.
-@@ -59,8 +1246,7 @@
+@@ -59,8 +1310,7 @@
  2014-04-11  Tobias Burnus  <burnus@net-b.de>
  
  	PR other/59055
@@ -6037,7 +6127,7 @@ Index: gcc/ChangeLog
  	* doc/gcc.texi (Service): Update description in the @menu
  	* doc/invoke.texi (Option Summary): Remove misplaced and
  	duplicated @menu.
-@@ -86,15 +1272,14 @@
+@@ -86,15 +1336,14 @@
  2014-04-11  Jakub Jelinek  <jakub@redhat.com>
  
  	PR rtl-optimization/60663
@@ -6056,7 +6146,7 @@ Index: gcc/ChangeLog
  
  2014-04-10  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
  
-@@ -212,9 +1397,10 @@
+@@ -212,9 +1461,10 @@
  
  2014-04-05  Pitchumani Sivanupandi  <Pitchumani.S@atmel.com>
  
@@ -6070,7 +6160,7 @@ Index: gcc/ChangeLog
  	* config/avr/avr-c.c (avr_cpu_cpp_builtins): use dev_attribute to check
  	errata_skip. Add __AVR_ISA_RMW__ builtin macro if RMW ISA available.
  	* config/avr/avr-devices.c (avr_mcu_types): Update AVR_MCU macro for
-@@ -282,21 +1468,21 @@
+@@ -282,21 +1532,21 @@
  2014-04-04  Martin Jambor  <mjambor@suse.cz>
  
  	PR ipa/60640
@@ -6103,7 +6193,7 @@ Index: gcc/ChangeLog
  	moved setting of a lot of flags to set_new_clone_decl_and_node_flags.
  
  2014-04-04  Jeff Law  <law@redhat.com>
-@@ -334,8 +1520,8 @@
+@@ -334,8 +1584,8 @@
  
  	PR tree-optimization/60505
  	* tree-vectorizer.h (struct _stmt_vec_info): Add th field as the
@@ -6114,7 +6204,7 @@ Index: gcc/ChangeLog
  	* tree-vect-loop.c (new_loop_vec_info):
  	Initialize LOOP_VINFO_COST_MODEL_THRESHOLD.
  	* tree-vect-loop.c (vect_analyze_loop_operations):
-@@ -347,8 +1533,7 @@
+@@ -347,8 +1597,7 @@
  
  2014-04-03  Richard Biener  <rguenther@suse.de>
  
@@ -6124,7 +6214,7 @@ Index: gcc/ChangeLog
  	(streamer_tree_cache_create): Adjust.
  	* tree-streamer.c (streamer_tree_cache_add_to_node_array): Adjust
  	to allow optional nodes array.
-@@ -359,8 +1544,7 @@
+@@ -359,8 +1608,7 @@
  	* lto-streamer-out.c (create_output_block): Avoid maintaining
  	the node array in the writer cache.
  	(DFS_write_tree): Remove assertion.
@@ -6134,7 +6224,7 @@ Index: gcc/ChangeLog
  	* lto-streamer-in.c (lto_data_in_create): Adjust for
  	streamer_tree_cache_create prototype change.
  
-@@ -381,24 +1565,6 @@
+@@ -381,24 +1629,6 @@
  	(Weffc++): Remove Scott's numbering, merge lists and reference
  	Wnon-virtual-dtor.
  
@@ -6159,7 +6249,7 @@ Index: gcc/ChangeLog
  2014-04-03  Nick Clifton  <nickc@redhat.com>
  
  	* config/rl78/rl78-expand.md (movqi): Handle (SUBREG (SYMBOL_REF))
-@@ -414,8 +1580,8 @@
+@@ -414,8 +1644,8 @@
  2014-04-02  Jan Hubicka  <hubicka@ucw.cz>
  
  	PR ipa/60659
@@ -6170,7 +6260,7 @@ Index: gcc/ChangeLog
  	(possible_polymorphic_call_targets): For inconsistent contexts
  	return empty complete list.
  
-@@ -519,8 +1685,7 @@
+@@ -519,8 +1749,7 @@
  
  2014-04-01  Richard Biener  <rguenther@suse.de>
  
@@ -6180,7 +6270,7 @@ Index: gcc/ChangeLog
  
  2014-04-01  Sebastian Huber  <sebastian.huber@embedded-brains.de>
  
-@@ -1031,10 +2196,10 @@
+@@ -1031,10 +2260,10 @@
  
  	PR tree-optimization/60577
  	* tree-core.h (struct tree_base): Document nothrow_flag use
@@ -9396,7 +9486,12 @@ Index: gcc/testsuite/ChangeLog
 ===================================================================
 --- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,550 @@
+@@ -1,3 +1,555 @@
++2014-06-20  Martin Jambor  <mjambor@suse.cz>
++
++	PR ipa/61540
++        * g++.dg/ipa/pr61540.C: New test.
++
 +2014-06-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 +
 +	PR target/61483
@@ -9947,7 +10042,7 @@ Index: gcc/testsuite/ChangeLog
  2014-04-22  Release Manager
  
  	* GCC 4.9.0 released.
-@@ -51,7 +598,7 @@
+@@ -51,7 +603,7 @@
  2014-04-12  Jerry DeLisle  <jvdelisle@gcc.gnu>
  
  	PR libfortran/60810
@@ -9956,7 +10051,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-04-11  Steve Ellcey  <sellcey@mips.com>
  	    Jakub Jelinek  <jakub@redhat.com>
-@@ -135,8 +682,7 @@
+@@ -135,8 +687,7 @@
  
  2014-04-08  Jason Merrill  <jason@redhat.com>
  
@@ -9966,7 +10061,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-04-08  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  
-@@ -256,10 +802,10 @@
+@@ -256,10 +807,10 @@
  2014-04-04  Martin Jambor  <mjambor@suse.cz>
  
  	PR ipa/60640
@@ -9981,7 +10076,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-04-04  Jeff Law  <law@redhat.com>
  
-@@ -371,7 +917,7 @@
+@@ -371,7 +922,7 @@
  
  2014-04-01  Fabien Chêne  <fabien@gcc.gnu.org>
  
@@ -9990,7 +10085,7 @@ Index: gcc/testsuite/ChangeLog
  	* g++.dg/init/ctor4-1.C: New.
  	* g++.dg/cpp0x/defaulted2.C: Adjust.
  
-@@ -459,8 +1005,8 @@
+@@ -459,8 +1010,8 @@
  
  2014-03-27  Jeff Law  <law@redhat.com>
  
@@ -10001,7 +10096,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-03-28  Adam Butcher  <adam@jessamine.co.uk>
  
-@@ -493,14 +1039,13 @@
+@@ -493,14 +1044,13 @@
  
  2014-03-28  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  
@@ -10019,7 +10114,7 @@ Index: gcc/testsuite/ChangeLog
  	of second source operand.
  	* gcc.target/i386/avx512f-vshuff64x2-2.c: Ditto.
  	* gcc.target/i386/avx512f-vshufi32x4-2.c: Ditto.
-@@ -635,8 +1180,8 @@
+@@ -635,8 +1185,8 @@
  
  2014-03-24  Marek Polacek  <polacek@redhat.com>
  
@@ -10030,7 +10125,7 @@ Index: gcc/testsuite/ChangeLog
  	* c-c++-common/ubsan/overflow-1.c: Check for unwanted output.
  	* c-c++-common/ubsan/overflow-add-1.c: Likewise.
  	* c-c++-common/ubsan/overflow-mul-1.c: Likewise.
-@@ -721,8 +1266,7 @@
+@@ -721,8 +1271,7 @@
  2014-03-21  Tobias Burnus  <burnus@net-b.de>
  
  	PR fortran/60599
@@ -10040,7 +10135,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-03-20  Jakub Jelinek  <jakub@redhat.com>
  
-@@ -1540,8 +2084,7 @@
+@@ -1540,8 +2089,7 @@
  
  2014-02-19  Paul Pluzhnikov  <ppluzhnikov@google.com>
  
@@ -10050,7 +10145,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-02-19  Jakub Jelinek  <jakub@redhat.com>
  
-@@ -1850,8 +2393,7 @@
+@@ -1850,8 +2398,7 @@
  
  2014-02-10  Jakub Jelinek  <jakub@redhat.com>
  
@@ -10060,7 +10155,7 @@ Index: gcc/testsuite/ChangeLog
  
  2014-02-09  Paul Thomas  <pault@gcc.gnu.org>
  
-@@ -3098,8 +3640,8 @@
+@@ -3098,8 +3645,8 @@
  	* gfortran.dg/vect/fast-math-mgrid-resid.f: Change
  	-fdump-tree-optimized to -fdump-tree-pcom-details in dg-options and
  	cleanup-tree-dump from optimized to pcom.  Remove scan-tree-dump-times
@@ -10714,6 +10809,25 @@ Index: gcc/testsuite/g++.dg/cpp0x/constexpr-aggr1.C
 +  FooContainer fooContainer;
 +  fooContainer = { { 0, nonConst } };
 +}
+Index: gcc/testsuite/g++.dg/cpp0x/variadic159.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic159.C	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic159.C	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,14 @@
++// PR c++/61507
++// { dg-do compile { target c++11 } }
++
++struct A {
++  void foo(const int &);
++  void foo(float);
++};
++
++template <typename... Args>
++void bar(void (A::*memfun)(Args...), Args... args);
++
++void go(const int& i) {
++  bar<const int &>(&A::foo, i);
++}
 Index: gcc/testsuite/g++.dg/cpp0x/defaulted49.C
 ===================================================================
 --- a/src/gcc/testsuite/g++.dg/cpp0x/defaulted49.C	(.../tags/gcc_4_9_0_release)
@@ -10734,6 +10848,24 @@ Index: gcc/testsuite/g++.dg/cpp0x/defaulted49.C
 +    x1 ();
 +  }
 +};
+Index: gcc/testsuite/g++.dg/cpp0x/ref-qual15.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/ref-qual15.C	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/ref-qual15.C	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,13 @@
++// PR c++/59296
++// { dg-do compile { target c++11 } }
++
++struct Type
++{
++  void get() const& { }
++  void get() const&& { }
++};
++
++int main()
++{
++  Type{}.get();
++}
 Index: gcc/testsuite/g++.dg/cpp0x/nsdmi-template10.C
 ===================================================================
 --- a/src/gcc/testsuite/g++.dg/cpp0x/nsdmi-template10.C	(.../tags/gcc_4_9_0_release)
@@ -10799,6 +10931,43 @@ Index: gcc/testsuite/g++.dg/cpp0x/sfinae50.C
 +
 +static_assert (is_foo<A>::value == 1, "");
 +static_assert (is_foo<A1>::value == 0, "");
+Index: gcc/testsuite/g++.dg/cpp0x/constexpr-template7.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-template7.C	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-template7.C	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,32 @@
++// PR c++/61556
++// { dg-do compile { target c++11 } }
++
++class ValueType {
++public:
++    constexpr operator int() const {return m_ID;};
++    constexpr ValueType(const int v)
++        : m_ID(v) {}
++private:
++    int m_ID;
++};
++
++class ValueTypeEnum {
++public:
++    static constexpr ValueType doubleval = ValueType(1);
++};
++
++template <int format>
++class ValueTypeInfo {
++};
++
++template <typename Format>
++class FillFunctor {
++public:
++    FillFunctor() {
++        ValueTypeInfo<ValueTypeEnum::doubleval> v;
++    }
++};
++
++int main() {
++    ValueTypeInfo<ValueTypeEnum::doubleval> v;
++}
 Index: gcc/testsuite/g++.dg/torture/pr60895.C
 ===================================================================
 --- a/src/gcc/testsuite/g++.dg/torture/pr60895.C	(.../tags/gcc_4_9_0_release)
@@ -10978,6 +11147,52 @@ Index: gcc/testsuite/g++.dg/ipa/devirt-11.C
 -/* { dg-final { scan-ipa-dump-times "Discovered a virtual call to a known target" 3 "inline"  } } */
 +/* { dg-final { scan-ipa-dump "Discovered a virtual call to a known target" "inline"  } } */
  /* { dg-final { cleanup-ipa-dump "inline" } } */
+Index: gcc/testsuite/g++.dg/ipa/pr61540.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ipa/pr61540.C	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/testsuite/g++.dg/ipa/pr61540.C	(.../branches/gcc-4_9-branch)
+@@ -0,0 +1,41 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -fno-early-inlining -fdump-ipa-cp" } */
++
++struct data {
++  data(int) {}
++};
++
++struct top {
++  virtual int topf() {}
++};
++
++struct intermediate: top {
++    int topf() /* override */ { return 0; }
++};
++
++struct child1: top {
++    void childf()
++    {
++        data d(topf());
++    }
++};
++
++struct child2: intermediate {};
++
++void test(top& t)
++{
++    child1& c = static_cast<child1&>(t);
++    c.childf();
++    child2 d;
++    test(d);
++}
++
++int main (int argc, char **argv)
++{
++  child1 c;
++  test (c);
++  return 0;
++}
++
++/* { dg-final { scan-ipa-dump "Type inconsident devirtualization" "cp" } } */
++/* { dg-final { cleanup-ipa-dump "cp" } } */
 Index: gcc/testsuite/g++.dg/template/local-fn1.C
 ===================================================================
 --- a/src/gcc/testsuite/g++.dg/template/local-fn1.C	(.../tags/gcc_4_9_0_release)
@@ -11782,7 +11997,26 @@ Index: gcc/cp/ChangeLog
 ===================================================================
 --- a/src/gcc/cp/ChangeLog	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/cp/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,90 @@
+@@ -1,3 +1,109 @@
++2014-06-20  Jason Merrill  <jason@redhat.com>
++
++	PR c++/59296
++	* call.c (add_function_candidate): Avoid special 'this' handling
++	if we have a ref-qualifier.
++
++	PR c++/61556
++	* call.c (build_over_call): Call build_this in template path.
++
++2014-06-19  Jason Merrill  <jason@redhat.com>
++
++	PR c++/59296
++	* call.c (add_function_candidate): Set LOOKUP_NO_RVAL_BIND
++	|LOOKUP_NO_TEMP_BIND for ref-qualifier handling.
++
++	PR c++/61507
++	* pt.c (resolve_overloaded_unification): Preserve
++	ARGUMENT_PACK_EXPLICIT_ARGS.
++
 +2014-06-18  Jason Merrill  <jason@redhat.com>
 +
 +	PR c++/60605
@@ -12139,6 +12373,24 @@ Index: gcc/cp/pt.c
  	  {
  	    /* The template parameter pack is used in a function parameter
  	       pack.  If this is the end of the parameter list, the
+@@ -16674,7 +16698,16 @@
+       int i = TREE_VEC_LENGTH (targs);
+       for (; i--; )
+ 	if (TREE_VEC_ELT (tempargs, i))
+-	  TREE_VEC_ELT (targs, i) = TREE_VEC_ELT (tempargs, i);
++	  {
++	    tree old = TREE_VEC_ELT (targs, i);
++	    tree new_ = TREE_VEC_ELT (tempargs, i);
++	    if (new_ && old && ARGUMENT_PACK_P (old)
++		&& ARGUMENT_PACK_EXPLICIT_ARGS (old))
++	      /* Don't forget explicit template arguments in a pack.  */
++	      ARGUMENT_PACK_EXPLICIT_ARGS (new_)
++		= ARGUMENT_PACK_EXPLICIT_ARGS (old);
++	    TREE_VEC_ELT (targs, i) = new_;
++	  }
+     }
+   if (good)
+     return true;
 Index: gcc/cp/parser.c
 ===================================================================
 --- a/src/gcc/cp/parser.c	(.../tags/gcc_4_9_0_release)
@@ -12258,7 +12510,17 @@ Index: gcc/cp/call.c
 ===================================================================
 --- a/src/gcc/cp/call.c	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/cp/call.c	(.../branches/gcc-4_9-branch)
-@@ -3677,11 +3677,20 @@
+@@ -1994,6 +1994,9 @@
+ 		     object parameter has reference type.  */
+ 		  bool rv = FUNCTION_RVALUE_QUALIFIED (TREE_TYPE (fn));
+ 		  parmtype = cp_build_reference_type (parmtype, rv);
++		  /* The special handling of 'this' conversions in compare_ics
++		     does not apply if there is a ref-qualifier.  */
++		  is_this = false;
+ 		}
+ 	      else
+ 		{
+@@ -3677,11 +3680,20 @@
        return cand;
      }
  
@@ -12281,6 +12543,31 @@ Index: gcc/cp/call.c
       build_identity_conv (TREE_TYPE (expr), expr));
    conv->cand = cand;
    if (cand->viable == -1)
+@@ -6751,7 +6763,7 @@
+ 
+ 	  ++nargs;
+ 	  alcarray = XALLOCAVEC (tree, nargs);
+-	  alcarray[0] = first_arg;
++	  alcarray[0] = build_this (first_arg);
+ 	  FOR_EACH_VEC_SAFE_ELT (args, ix, arg)
+ 	    alcarray[ix + 1] = arg;
+ 	  argarray = alcarray;
+@@ -8446,10 +8458,11 @@
+   /* [over.ics.rank]
+ 
+      --S1 and S2 are reference bindings (_dcl.init.ref_) and neither refers
+-     to an implicit object parameter, and either S1 binds an lvalue reference
+-     to an lvalue and S2 binds an rvalue reference or S1 binds an rvalue
+-     reference to an rvalue and S2 binds an lvalue reference
+-     (C++0x draft standard, 13.3.3.2)
++     to an implicit object parameter of a non-static member function
++     declared without a ref-qualifier, and either S1 binds an lvalue
++     reference to an lvalue and S2 binds an rvalue reference or S1 binds an
++     rvalue reference to an rvalue and S2 binds an lvalue reference (C++0x
++     draft standard, 13.3.3.2)
+ 
+      --S1 and S2 are reference bindings (_dcl.init.ref_), and the
+      types to which the references refer are the same type except for
 Index: gcc/cp/lambda.c
 ===================================================================
 --- a/src/gcc/cp/lambda.c	(.../tags/gcc_4_9_0_release)
@@ -14916,7 +15203,79 @@ Index: gcc/ipa-prop.c
 ===================================================================
 --- a/src/gcc/ipa-prop.c	(.../tags/gcc_4_9_0_release)
 +++ b/src/gcc/ipa-prop.c	(.../branches/gcc-4_9-branch)
-@@ -2877,8 +2877,10 @@
+@@ -2701,6 +2701,29 @@
+   return cs;
+ }
+ 
++/* Return the target to be used in cases of impossible devirtualization.  IE
++   and target (the latter can be NULL) are dumped when dumping is enabled.  */
++
++static tree
++impossible_devirt_target (struct cgraph_edge *ie, tree target)
++{
++  if (dump_file)
++    {
++      if (target)
++	fprintf (dump_file,
++		 "Type inconsident devirtualization: %s/%i->%s\n",
++		 ie->caller->name (), ie->caller->order,
++		 IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (target)));
++      else
++	fprintf (dump_file,
++		 "No devirtualization target in %s/%i\n",
++		 ie->caller->name (), ie->caller->order);
++    }
++  tree new_target = builtin_decl_implicit (BUILT_IN_UNREACHABLE);
++  cgraph_get_create_node (new_target);
++  return new_target;
++}
++
+ /* Try to find a destination for indirect edge IE that corresponds to a virtual
+    call based on a formal parameter which is described by jump function JFUNC
+    and if it can be determined, make it direct and return the direct edge.
+@@ -2735,15 +2758,7 @@
+ 		   && DECL_FUNCTION_CODE (target) == BUILT_IN_UNREACHABLE)
+ 		  || !possible_polymorphic_call_target_p
+ 		       (ie, cgraph_get_node (target)))
+-		{
+-		  if (dump_file)
+-		    fprintf (dump_file,
+-			     "Type inconsident devirtualization: %s/%i->%s\n",
+-			     ie->caller->name (), ie->caller->order,
+-			     IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (target)));
+-		  target = builtin_decl_implicit (BUILT_IN_UNREACHABLE);
+-		  cgraph_get_create_node (target);
+-		}
++		target = impossible_devirt_target (ie, target);
+ 	      return ipa_make_edge_direct_to_target (ie, target);
+ 	    }
+ 	}
+@@ -2773,10 +2788,7 @@
+       if (targets.length () == 1)
+ 	target = targets[0]->decl;
+       else
+-	{
+-          target = builtin_decl_implicit (BUILT_IN_UNREACHABLE);
+-	  cgraph_get_create_node (target);
+-	}
++	target = impossible_devirt_target (ie, NULL_TREE);
+     }
+   else
+     {
+@@ -2791,10 +2803,8 @@
+ 
+   if (target)
+     {
+-#ifdef ENABLE_CHECKING
+-      gcc_assert (possible_polymorphic_call_target_p
+-	 (ie, cgraph_get_node (target)));
+-#endif
++      if (!possible_polymorphic_call_target_p (ie, cgraph_get_node (target)))
++	target = impossible_devirt_target (ie, target);
+       return ipa_make_edge_direct_to_target (ie, target);
+     }
+   else
+@@ -2877,8 +2887,10 @@
        else if (jfunc->type == IPA_JF_PASS_THROUGH
  	       && ipa_get_jf_pass_through_operation (jfunc) == NOP_EXPR)
  	{
@@ -14929,7 +15288,7 @@ Index: gcc/ipa-prop.c
  	    ici->param_index = -1;
  	  else
  	    ici->param_index = ipa_get_jf_pass_through_formal_id (jfunc);
-@@ -2885,8 +2887,10 @@
+@@ -2885,8 +2897,10 @@
  	}
        else if (jfunc->type == IPA_JF_ANCESTOR)
  	{
@@ -14942,7 +15301,7 @@ Index: gcc/ipa-prop.c
  	    ici->param_index = -1;
  	  else
  	    {
-@@ -3650,6 +3654,7 @@
+@@ -3650,6 +3664,7 @@
  
    TREE_TYPE (fndecl) = new_type;
    DECL_VIRTUAL_P (fndecl) = 0;
@@ -27592,6 +27951,33 @@ Index: gcc/config/i386/i386.c
  	  for (i = 0; i < 32; i++)
  	    vec[i] = vt2;
  	  vt = gen_rtx_CONST_VECTOR (V32QImode, gen_rtvec_v (32, vec));
+@@ -23794,7 +23794,7 @@
+ {
+   const struct stringop_algs * algs;
+   bool optimize_for_speed;
+-  int max = -1;
++  int max = 0;
+   const struct processor_costs *cost;
+   int i;
+   bool any_alg_usable_p = false;
+@@ -23832,7 +23832,7 @@
+   /* If expected size is not known but max size is small enough
+      so inline version is a win, set expected size into
+      the range.  */
+-  if (max > 1 && (unsigned HOST_WIDE_INT) max >= max_size
++  if (((max > 1 && (unsigned HOST_WIDE_INT) max >= max_size) || max == -1)
+       && expected_size == -1)
+     expected_size = min_size / 2 + max_size / 2;
+ 
+@@ -23921,7 +23921,7 @@
+             *dynamic_check = 128;
+           return loop_1_byte;
+         }
+-      if (max == -1)
++      if (max <= 0)
+ 	max = 4096;
+       alg = decide_alg (count, max / 2, min_size, max_size, memset,
+ 			zero_memset, dynamic_check, noalign);
 @@ -24151,8 +24151,13 @@
      align = MEM_ALIGN (dst) / BITS_PER_UNIT;
  
@@ -28032,6 +28418,249 @@ Index: gcc/config/rtems.h
  <http://www.gnu.org/licenses/>.  */
  
  /* The system headers under RTEMS are C++-aware.  */
+Index: gcc/config/aarch64/aarch64-simd.md
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-simd.md	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/aarch64/aarch64-simd.md	(.../branches/gcc-4_9-branch)
+@@ -2633,7 +2633,41 @@
+ 
+ ;; sq<r>dmulh_lane
+ 
+-(define_insn "aarch64_sq<r>dmulh_lane<mode>"
++(define_expand "aarch64_sqdmulh_lane<mode>"
++  [(match_operand:VDQHS 0 "register_operand" "")
++   (match_operand:VDQHS 1 "register_operand" "")
++   (match_operand:<VCOND> 2 "register_operand" "")
++   (match_operand:SI 3 "immediate_operand" "")]
++  "TARGET_SIMD"
++  {
++     aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
++     operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
++     emit_insn (gen_aarch64_sqdmulh_lane<mode>_internal (operands[0],
++                                                         operands[1],
++                                                         operands[2],
++                                                         operands[3]));
++     DONE;
++  }
++)
++
++(define_expand "aarch64_sqrdmulh_lane<mode>"
++  [(match_operand:VDQHS 0 "register_operand" "")
++   (match_operand:VDQHS 1 "register_operand" "")
++   (match_operand:<VCOND> 2 "register_operand" "")
++   (match_operand:SI 3 "immediate_operand" "")]
++  "TARGET_SIMD"
++  {
++     aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
++     operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
++     emit_insn (gen_aarch64_sqrdmulh_lane<mode>_internal (operands[0],
++                                                          operands[1],
++                                                          operands[2],
++                                                          operands[3]));
++     DONE;
++  }
++)
++
++(define_insn "aarch64_sq<r>dmulh_lane<mode>_internal"
+   [(set (match_operand:VDQHS 0 "register_operand" "=w")
+         (unspec:VDQHS
+ 	  [(match_operand:VDQHS 1 "register_operand" "w")
+@@ -2649,7 +2683,41 @@
+   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
+ )
+ 
+-(define_insn "aarch64_sq<r>dmulh_laneq<mode>"
++(define_expand "aarch64_sqdmulh_laneq<mode>"
++  [(match_operand:VDQHS 0 "register_operand" "")
++   (match_operand:VDQHS 1 "register_operand" "")
++   (match_operand:<VCONQ> 2 "register_operand" "")
++   (match_operand:SI 3 "immediate_operand" "")]
++  "TARGET_SIMD"
++  {
++     aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
++     operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
++     emit_insn (gen_aarch64_sqdmulh_laneq<mode>_internal (operands[0],
++                                                          operands[1],
++                                                          operands[2],
++                                                          operands[3]));
++     DONE;
++   }
++)
++
++(define_expand "aarch64_sqrdmulh_laneq<mode>"
++  [(match_operand:VDQHS 0 "register_operand" "")
++   (match_operand:VDQHS 1 "register_operand" "")
++   (match_operand:<VCONQ> 2 "register_operand" "")
++   (match_operand:SI 3 "immediate_operand" "")]
++  "TARGET_SIMD"
++  {
++     aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
++     operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
++     emit_insn (gen_aarch64_sqrdmulh_laneq<mode>_internal (operands[0],
++                                                           operands[1],
++                                                           operands[2],
++                                                           operands[3]));
++     DONE;
++   }
++)
++
++(define_insn "aarch64_sq<r>dmulh_laneq<mode>_internal"
+   [(set (match_operand:VDQHS 0 "register_operand" "=w")
+         (unspec:VDQHS
+ 	  [(match_operand:VDQHS 1 "register_operand" "w")
+@@ -2659,13 +2727,46 @@
+ 	 VQDMULH))]
+   "TARGET_SIMD"
+   "*
+-   aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
+    operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
+    return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
+   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
+ )
+ 
+-(define_insn "aarch64_sq<r>dmulh_lane<mode>"
++(define_expand "aarch64_sqdmulh_lane<mode>"
++  [(match_operand:SD_HSI 0 "register_operand" "")
++   (match_operand:SD_HSI 1 "register_operand" "")
++   (match_operand:<VCONQ> 2 "register_operand" "")
++   (match_operand:SI 3 "immediate_operand" "")]
++  "TARGET_SIMD"
++  {
++    aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
++    operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
++    emit_insn (gen_aarch64_sqdmulh_lane<mode>_internal (operands[0],
++                                                        operands[1],
++                                                        operands[2],
++                                                        operands[3]));
++    DONE;
++  }
++)
++
++(define_expand "aarch64_sqrdmulh_lane<mode>"
++  [(match_operand:SD_HSI 0 "register_operand" "")
++   (match_operand:SD_HSI 1 "register_operand" "")
++   (match_operand:<VCONQ> 2 "register_operand" "")
++   (match_operand:SI 3 "immediate_operand" "")]
++  "TARGET_SIMD"
++  {
++    aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
++    operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
++    emit_insn (gen_aarch64_sqrdmulh_lane<mode>_internal (operands[0],
++                                                         operands[1],
++                                                         operands[2],
++                                                         operands[3]));
++    DONE;
++  }
++)
++
++(define_insn "aarch64_sq<r>dmulh_lane<mode>_internal"
+   [(set (match_operand:SD_HSI 0 "register_operand" "=w")
+         (unspec:SD_HSI
+ 	  [(match_operand:SD_HSI 1 "register_operand" "w")
+@@ -2675,7 +2776,6 @@
+ 	 VQDMULH))]
+   "TARGET_SIMD"
+   "*
+-   aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
+    operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
+    return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
+   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
+@@ -2757,6 +2857,7 @@
+   "TARGET_SIMD"
+ {
+   aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCON>mode) / 2);
++  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
+   emit_insn (gen_aarch64_sqdmlal_lane<mode>_internal (operands[0], operands[1],
+ 						      operands[2], operands[3],
+ 						      operands[4]));
+@@ -2772,6 +2873,7 @@
+   "TARGET_SIMD"
+ {
+   aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCON>mode));
++  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCON>mode, INTVAL (operands[4])));
+   emit_insn (gen_aarch64_sqdmlal_lane<mode>_internal (operands[0], operands[1],
+ 						      operands[2], operands[3],
+ 						      operands[4]));
+@@ -2787,6 +2889,7 @@
+   "TARGET_SIMD"
+ {
+   aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCON>mode) / 2);
++  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCON>mode, INTVAL (operands[4])));
+   emit_insn (gen_aarch64_sqdmlsl_lane<mode>_internal (operands[0], operands[1],
+ 						      operands[2], operands[3],
+ 						      operands[4]));
+@@ -2802,6 +2905,7 @@
+   "TARGET_SIMD"
+ {
+   aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCON>mode));
++  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCON>mode, INTVAL (operands[4])));
+   emit_insn (gen_aarch64_sqdmlsl_lane<mode>_internal (operands[0], operands[1],
+ 						      operands[2], operands[3],
+ 						      operands[4]));
+@@ -2913,6 +3017,7 @@
+ {
+   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
+   aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode) / 2);
++  operands[4] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[4])));
+   emit_insn (gen_aarch64_sqdmlal2_lane<mode>_internal (operands[0], operands[1],
+ 						       operands[2], operands[3],
+ 						       operands[4], p));
+@@ -2929,6 +3034,7 @@
+ {
+   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
+   aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
++  operands[4] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[4])));
+   emit_insn (gen_aarch64_sqdmlal2_lane<mode>_internal (operands[0], operands[1],
+ 						       operands[2], operands[3],
+ 						       operands[4], p));
+@@ -2945,6 +3051,7 @@
+ {
+   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
+   aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode) / 2);
++  operands[4] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[4])));
+   emit_insn (gen_aarch64_sqdmlsl2_lane<mode>_internal (operands[0], operands[1],
+ 						       operands[2], operands[3],
+ 						       operands[4], p));
+@@ -2961,6 +3068,7 @@
+ {
+   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
+   aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
++  operands[4] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[4])));
+   emit_insn (gen_aarch64_sqdmlsl2_lane<mode>_internal (operands[0], operands[1],
+ 						       operands[2], operands[3],
+ 						       operands[4], p));
+@@ -3081,6 +3189,7 @@
+   "TARGET_SIMD"
+ {
+   aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCON>mode) / 2);
++  operands[3] = GEN_INT (ENDIAN_LANE_N (<VCON>mode, INTVAL (operands[3])));
+   emit_insn (gen_aarch64_sqdmull_lane<mode>_internal (operands[0], operands[1],
+ 						      operands[2], operands[3]));
+   DONE;
+@@ -3094,6 +3203,7 @@
+   "TARGET_SIMD"
+ {
+   aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCON>mode));
++  operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
+   emit_insn (gen_aarch64_sqdmull_lane<mode>_internal
+ 	       (operands[0], operands[1], operands[2], operands[3]));
+   DONE;
+@@ -3186,6 +3296,7 @@
+ {
+   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
+   aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode) / 2);
++  operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3])));
+   emit_insn (gen_aarch64_sqdmull2_lane<mode>_internal (operands[0], operands[1],
+ 						       operands[2], operands[3],
+ 						       p));
+@@ -3201,6 +3312,7 @@
+ {
+   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
+   aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
++  operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3])));
+   emit_insn (gen_aarch64_sqdmull2_lane<mode>_internal (operands[0], operands[1],
+ 						       operands[2], operands[3],
+ 						       p));
 Index: gcc/config/aarch64/arm_neon.h
 ===================================================================
 --- a/src/gcc/config/aarch64/arm_neon.h	(.../tags/gcc_4_9_0_release)
@@ -28054,6 +28683,18 @@ Index: gcc/config/aarch64/arm_neon.h
             : /* No clobbers */);
    return result;
  }
+Index: gcc/config/aarch64/aarch64.md
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.md	(.../tags/gcc_4_9_0_release)
++++ b/src/gcc/config/aarch64/aarch64.md	(.../branches/gcc-4_9-branch)
+@@ -3608,6 +3608,7 @@
+         (unspec:DI [(match_operand:DI 0 "aarch64_valid_symref" "S")]
+ 		   UNSPEC_TLSDESC))
+    (clobber (reg:DI LR_REGNUM))
++   (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:DI 1 "=r"))]
+   "TARGET_TLS_DESC"
+   "adrp\\tx0, %A0\;ldr\\t%1, [x0, #%L0]\;add\\tx0, x0, %L0\;.tlsdesccall\\t%0\;blr\\t%1"
 Index: gcc/config/aarch64/aarch64.c
 ===================================================================
 --- a/src/gcc/config/aarch64/aarch64.c	(.../tags/gcc_4_9_0_release)
@@ -29693,6 +30334,22 @@ Index: gcc/config/arm/arm.c
  	insn = PREV_INSN (insn);
  
        /* Find the last cbranchsi4_insn in basic block BB.  */
+@@ -28183,9 +28183,13 @@
+       fputs (":\n", file);
+       if (flag_pic)
+ 	{
+-	  /* Output ".word .LTHUNKn-7-.LTHUNKPCn".  */
++	  /* Output ".word .LTHUNKn-[3,7]-.LTHUNKPCn".  */
+ 	  rtx tem = XEXP (DECL_RTL (function), 0);
+-	  tem = plus_constant (GET_MODE (tem), tem, -7);
++	  /* For TARGET_THUMB1_ONLY the thunk is in Thumb mode, so the PC
++	     pipeline offset is four rather than eight.  Adjust the offset
++	     accordingly.  */
++	  tem = plus_constant (GET_MODE (tem), tem,
++			       TARGET_THUMB1_ONLY ? -3 : -7);
+ 	  tem = gen_rtx_MINUS (GET_MODE (tem),
+ 			       tem,
+ 			       gen_rtx_SYMBOL_REF (Pmode,
 Index: gcc/config/arm/arm.h
 ===================================================================
 --- a/src/gcc/config/arm/arm.h	(.../tags/gcc_4_9_0_release)