* Update to SVN 20150903 (r227431, 5.2.1) from the gcc-5-branch.

git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-5@8214 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca

2 files changed, 670 insertions, 30 deletions

diff --git a/debian/changelog b/debian/changelog
index 195d754..f9b75a2 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,6 @@
 gcc-5 (5.2.1-16) UNRELEASED; urgency=medium
 
-  * Update to SVN 20150902 (r227402, 5.2.1) from the gcc-5-branch.
+  * Update to SVN 20150903 (r227431, 5.2.1) from the gcc-5-branch.
     - Backport the filesystem TS library.
   * libstdc++-dev: Install libstdc++fs.a.
   * Again, configure with --enable-targets=powerpcle-linux on ppc64el.
@@ -8,7 +8,7 @@ gcc-5 (5.2.1-16) UNRELEASED; urgency=medium
   * libgo-dev: Install libgolibbegin.a.
   * Apply proposed patch for PR target/67280 (ARM). LP: #1482320.
 
- -- Matthias Klose <doko@debian.org>  Wed, 02 Sep 2015 16:29:44 +0200
+ -- Matthias Klose <doko@debian.org>  Thu, 03 Sep 2015 12:16:15 +0200
 
 gcc-5 (5.2.1-15) unstable; urgency=medium
 
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index 654608a..1befccd 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 5 branch upto 20150902 (r227402).
+# DP: updates from the 5 branch upto 20150903 (r227431).
 
 last_update()
 {
 	cat > ${dir}LAST_UPDATED <EOF
-Wed Sep  2 16:14:59 CEST 2015
-Wed Sep  2 14:14:59 UTC 2015 (revision 227402)
+Thu Sep  3 12:02:38 CEST 2015
+Thu Sep  3 10:02:38 UTC 2015 (revision 227431)
 EOF
 }
 
@@ -11886,7 +11886,7 @@ Index: gcc/DATESTAMP
 +++ b/src/gcc/DATESTAMP	(.../branches/gcc-5-branch)
 @@ -1 +1 @@
 -20150716
-+20150902
++20150903
 Index: gcc/postreload.c
 ===================================================================
 --- a/src/gcc/postreload.c	(.../tags/gcc_5_2_0_release)
@@ -12351,7 +12351,48 @@ Index: gcc/ChangeLog
 ===================================================================
 --- a/src/gcc/ChangeLog	(.../tags/gcc_5_2_0_release)
 +++ b/src/gcc/ChangeLog	(.../branches/gcc-5-branch)
-@@ -1,3 +1,568 @@
+@@ -1,3 +1,609 @@
++2015-09-03  Richard Biener  <rguenther@suse.de>
++
++	PR ipa/66705
++	* tree-ssa-structalias.c (ctor_for_analysis): New function.
++	(create_variable_info_for_1): Use ctor_for_analysis instead
++	of get_constructor.
++	(create_variable_info_for): Likewise.
++
++2015-09-02  Uros Bizjak  <ubizjak@gmail.com>
++
++	Backport from mainline:
++	2015-08-27  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/67317
++	* config/i386/i386.md (*add<mode>3_cc): Remove insn pattern.
++	(addqi3_cc): Ditto.
++	(UNSPEC_ADD_CARRY): Remove.
++	(addqi3_cconly_overflow): New expander.
++	(*add<dwi>3_doubleword): Split to add<mode>3_cconly_overflow.
++	Adjust for changed add<mode>3_carry.
++	(*neg<dwi>2_doubleword): Adjust for changed add<mode>3_carry.
++	(*sub<dwi>3_doubleword): Adjust for changed sub<mode>3_carry.
++	(<plusminus_insn><mode>3_carry): Remove expander.
++	(*<plusminus_insn><mode>3_carry): Split insn pattern to
++	add<mode>3_carry and sub<mode>3_carry.
++	(plusminus_carry_mnemonic): Remove code attribute.
++	(add<mode>3_carry): Canonicalize insn pattern.
++	(*addsi3_carry_zext): Ditto.
++	(sub<mode>3_carry): Ditto.
++	(*subsi3_carry_zext): Ditto.
++	(adcx<mode>3): Remove insn pattern.
++	(addcarry<mode>): New insn pattern.
++	(subborrow<mode>): Ditto.
++	* config/i386/i386.c (ix86_expand_strlensi_unroll_1): Use
++	gen_addqi3_cconly_overflow instead of gen_addqi3_cc.
++	(ix86_expand_builtin) <case IX86_BUILTIN_SBB32,
++	case IX86_BUILTIN_SBB64, case IX86_BUILTIN_ADDCARRY32,
++	case IX86_BUILTIN_ADDCARRY64>: Use CODE_FOR_subborrowsi,
++	CODE_FOR_subborrowdi, CODE_FOR_addcarrysi and CODE_FOR_addcarrydi.
++	Rewrite expander to not clobber carry flag chains.
++
 +2015-09-02  Alan Modra  <amodra@gmail.com>
 +
 +	PR target/67417
@@ -12920,7 +12961,7 @@ Index: gcc/ChangeLog
  2015-07-16  Release Manager
  
  	* GCC 5.2.0 released.
-@@ -119,8 +684,8 @@
+@@ -119,8 +725,8 @@
  2015-07-09  Iain Sandoe  <iain@codesourcery.com>
  
  	PR target/66523
@@ -13519,6 +13560,18 @@ Index: gcc/testsuite/gcc.target/aarch64/fnmul-4.c
 +  /* { dg-final { scan-assembler "fnmul\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */
 +  return -(a * b);
 +}
+Index: gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c	(.../branches/gcc-5-branch)
+@@ -1,6 +1,6 @@
+ /* { dg-do compile { target { ! ia32 } } } */
+ /* { dg-options "-madx -O2" } */
+-/* { dg-final { scan-assembler-times "adcx" 2 } } */
++/* { dg-final { scan-assembler-times "adc\[xq\]" 2 } } */
+ /* { dg-final { scan-assembler-times "sbbq" 1 } } */
+ 
+ #include <x86intrin.h>
 Index: gcc/testsuite/gcc.target/i386/pr66648.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.target/i386/pr66648.c	(.../tags/gcc_5_2_0_release)
@@ -13667,6 +13720,75 @@ Index: gcc/testsuite/gcc.target/i386/pr66838.c
 +  ms_abi_func();
 +  return 0;
 +}
+Index: gcc/testsuite/gcc.target/i386/pr67317-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr67317-1.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr67317-1.c	(.../branches/gcc-5-branch)
+@@ -0,0 +1,18 @@
++/* PR target/67317 */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++typedef unsigned int u32;
++
++u32 testcarry_u32 (u32 a, u32 b, u32 c, u32 d)
++{
++  u32 result0, result1;
++
++  __builtin_ia32_addcarryx_u32
++    (__builtin_ia32_addcarryx_u32 (0, a, c, &result0), b, d, &result1);
++
++  return result0 ^ result1;
++}
++
++/* { dg-final { scan-assembler-not "addb" } } */
++/* { dg-final { scan-assembler-not "setn?c" } } */
+Index: gcc/testsuite/gcc.target/i386/pr67317-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr67317-2.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr67317-2.c	(.../branches/gcc-5-branch)
+@@ -0,0 +1,18 @@
++/* PR target/67317 */
++/* { dg-do compile { target { ! ia32 } } } */
++/* { dg-options "-O2" } */
++
++typedef unsigned long long u64;
++
++u64 testcarry_u64 (u64 a, u64 b, u64 c, u64 d)
++{
++  u64 result0, result1;
++
++  __builtin_ia32_addcarryx_u64
++    (__builtin_ia32_addcarryx_u64 (0, a, c, &result0), b, d, &result1);
++
++  return result0 ^ result1;
++}
++
++/* { dg-final { scan-assembler-not "addb" } } */
++/* { dg-final { scan-assembler-not "setn?c" } } */
+Index: gcc/testsuite/gcc.target/i386/pr67317-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr67317-3.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr67317-3.c	(.../branches/gcc-5-branch)
+@@ -0,0 +1,18 @@
++/* PR target/67317 */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++typedef unsigned int u32;
++
++u32 testcarry_u32 (u32 a, u32 b, u32 c, u32 d)
++{
++  u32 result0, result1;
++
++  __builtin_ia32_sbb_u32
++    (__builtin_ia32_sbb_u32 (0, a, c, &result0), b, d, &result1);
++
++  return result0 ^ result1;
++}
++
++/* { dg-final { scan-assembler-not "addb" } } */
++/* { dg-final { scan-assembler-not "setn?c" } } */
 Index: gcc/testsuite/gcc.target/i386/readeflags-1.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.target/i386/readeflags-1.c	(.../tags/gcc_5_2_0_release)
@@ -13715,6 +13837,41 @@ Index: gcc/testsuite/gcc.target/i386/pr66703.c
 +/* { dg-options "-O0 -mtune=pentium" } */
 +
 +#include "readeflags-1.c"
+Index: gcc/testsuite/gcc.target/i386/pr67317-4.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr67317-4.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr67317-4.c	(.../branches/gcc-5-branch)
+@@ -0,0 +1,18 @@
++/* PR target/67317 */
++/* { dg-do compile { target { ! ia32 } } } */
++/* { dg-options "-O2" } */
++
++typedef unsigned long long u64;
++
++u64 testcarry_u64 (u64 a, u64 b, u64 c, u64 d)
++{
++  u64 result0, result1;
++
++  __builtin_ia32_sbb_u64
++    (__builtin_ia32_sbb_u64 (0, a, c, &result0), b, d, &result1);
++
++  return result0 ^ result1;
++}
++
++/* { dg-final { scan-assembler-not "addb" } } */
++/* { dg-final { scan-assembler-not "setn?c" } } */
+Index: gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c	(.../branches/gcc-5-branch)
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-options "-madx -O2" } */
+-/* { dg-final { scan-assembler-times "adcx" 2 } } */
++/* { dg-final { scan-assembler-times "adc\[xl\]" 2 } } */
+ /* { dg-final { scan-assembler-times "sbbl" 1 } } */
+ 
+ #include <x86intrin.h>
 Index: gcc/testsuite/gcc.target/i386/pr66922.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.target/i386/pr66922.c	(.../tags/gcc_5_2_0_release)
@@ -14918,7 +15075,25 @@ Index: gcc/testsuite/ChangeLog
 ===================================================================
 --- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_5_2_0_release)
 +++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-5-branch)
-@@ -1,3 +1,392 @@
+@@ -1,3 +1,410 @@
++2015-09-03  Richard Biener  <rguenther@suse.de>
++
++	PR ipa/66705
++	* g++.dg/lto/pr66705_0.C: New testcase.
++
++2015-09-02  Uros Bizjak  <ubizjak@gmail.com>
++
++	Backport from mainline:
++	2015-08-27  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/67317
++	* gcc.target/i386/pr67317-1.c: New test.
++	* gcc.target/i386/pr67317-2.c: Ditto.
++	* gcc.target/i386/pr67317-3.c: Ditto.
++	* gcc.target/i386/pr67317-4.c: Ditto.
++	* gcc.target/i386/adx-addcarryx32-1.c: Also scan for adcl.
++	* gcc.target/i386/adx-addcarryx32-2.c: Also scan for adcq.
++
 +2015-08-31  Marek Polacek  <polacek@redhat.com>
 +
 +	Backport from mainline
@@ -15311,7 +15486,7 @@ Index: gcc/testsuite/ChangeLog
  2015-07-16  Release Manager
  
  	* GCC 5.2.0 released.
-@@ -792,7 +1181,7 @@
+@@ -792,7 +1199,7 @@
  	Add missing ChangeLog entry for r222341.
  
  	Backport from trunk r222273
@@ -15849,6 +16024,26 @@ Index: gcc/testsuite/g++.dg/conversion/access1.C
  };
  
  void foo()
+Index: gcc/testsuite/g++.dg/lto/pr66705_0.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/lto/pr66705_0.C	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/g++.dg/lto/pr66705_0.C	(.../branches/gcc-5-branch)
+@@ -0,0 +1,15 @@
++// { dg-lto-do link }
++// { dg-lto-options { { -O2 -flto -flto-partition=max -fipa-pta } } }
++// { dg-extra-ld-options "-r -nostdlib" }
++
++class A {
++public:
++    A();
++};
++int a = 0;
++void foo() {
++    a = 0;
++    A b;
++    for (; a;)
++      ;
++}
 Index: gcc/testsuite/g++.dg/warn/deprecated-9.C
 ===================================================================
 --- a/src/gcc/testsuite/g++.dg/warn/deprecated-9.C	(.../tags/gcc_5_2_0_release)
@@ -533470,6 +533665,51 @@ Index: gcc/combine.c
  		  && (c1 & ~GET_MODE_MASK (tmode)) == 0
  		  && c1 != mask
  		  && c1 != GET_MODE_MASK (tmode))
+Index: gcc/tree-ssa-structalias.c
+===================================================================
+--- a/src/gcc/tree-ssa-structalias.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/tree-ssa-structalias.c	(.../branches/gcc-5-branch)
+@@ -5650,7 +5650,6 @@
+   auto_vec<fieldoff_s> fieldstack;
+   fieldoff_s *fo;
+   unsigned int i;
+-  varpool_node *vnode;
+ 
+   if (!declsize
+       || !tree_fits_uhwi_p (declsize))
+@@ -5668,12 +5667,10 @@
+   /* Collect field information.  */
+   if (use_field_sensitive
+       && var_can_have_subvars (decl)
+-      /* ???  Force us to not use subfields for global initializers
+-	 in IPA mode.  Else we'd have to parse arbitrary initializers.  */
++      /* ???  Force us to not use subfields for globals in IPA mode.
++	 Else we'd have to parse arbitrary initializers.  */
+       && !(in_ipa_mode
+-	   && is_global_var (decl)
+-	   && (vnode = varpool_node::get (decl))
+-	   && vnode->get_constructor ()))
++	   && is_global_var (decl)))
+     {
+       fieldoff_s *fo = NULL;
+       bool notokay = false;
+@@ -5805,13 +5802,13 @@
+ 
+ 	  /* If this is a global variable with an initializer and we are in
+ 	     IPA mode generate constraints for it.  */
+-	  if (vnode->get_constructor ()
+-	      && vnode->definition)
++	  ipa_ref *ref;
++	  for (unsigned idx = 0; vnode->iterate_reference (idx, ref); ++idx)
+ 	    {
+ 	      auto_vec<ce_s> rhsc;
+ 	      struct constraint_expr lhs, *rhsp;
+ 	      unsigned i;
+-	      get_constraint_for_rhs (vnode->get_constructor (), &rhsc);
++	      get_constraint_for_address_of (ref->referred->decl, &rhsc);
+ 	      lhs.var = vi->id;
+ 	      lhs.offset = 0;
+ 	      lhs.type = SCALAR;
 Index: gcc/config/alpha/alpha.c
 ===================================================================
 --- a/src/gcc/config/alpha/alpha.c	(.../tags/gcc_5_2_0_release)
@@ -533618,7 +533858,15 @@ Index: gcc/config/i386/i386.md
 ===================================================================
 --- a/src/gcc/config/i386/i386.md	(.../tags/gcc_5_2_0_release)
 +++ b/src/gcc/config/i386/i386.md	(.../branches/gcc-5-branch)
-@@ -783,7 +783,8 @@
+@@ -102,7 +102,6 @@
+   UNSPEC_SAHF
+   UNSPEC_PARITY
+   UNSPEC_FSTCW
+-  UNSPEC_ADD_CARRY
+   UNSPEC_FLDCW
+   UNSPEC_REP
+   UNSPEC_LD_MPIC	; load_macho_picbase
+@@ -783,7 +782,8 @@
  (define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
  		    sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
  		    avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
@@ -533628,7 +533876,7 @@ Index: gcc/config/i386/i386.md
    (const_string "base"))
  
  (define_attr "enabled" ""
-@@ -818,6 +819,8 @@
+@@ -818,6 +818,8 @@
  	 (eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW")
  	 (eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ")
  	 (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ")
@@ -533637,7 +533885,16 @@ Index: gcc/config/i386/i386.md
  	]
  	(const_int 1)))
  
-@@ -5051,11 +5054,11 @@
+@@ -844,8 +846,6 @@
+ (define_code_attr plusminus_mnemonic
+   [(plus "add") (ss_plus "adds") (us_plus "addus")
+    (minus "sub") (ss_minus "subs") (us_minus "subus")])
+-(define_code_attr plusminus_carry_mnemonic
+-  [(plus "adc") (minus "sbb")])
+ (define_code_attr multdiv_mnemonic
+   [(mult "mul") (div "div")])
+ 
+@@ -5051,11 +5051,11 @@
    /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
       Assemble the 64-bit DImode value in an xmm register.  */
    emit_insn (gen_sse2_loadld (operands[3], CONST0_RTX (V4SImode),
@@ -533652,7 +533909,257 @@ Index: gcc/config/i386/i386.md
  
    operands[3] = gen_rtx_REG (DImode, REGNO (operands[3]));
  })
-@@ -13237,7 +13240,8 @@
+@@ -5213,46 +5213,21 @@
+   "ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
+   "#"
+   "reload_completed"
+-  [(parallel [(set (reg:CC FLAGS_REG)
+-		   (unspec:CC [(match_dup 1) (match_dup 2)]
+-			      UNSPEC_ADD_CARRY))
++  [(parallel [(set (reg:CCC FLAGS_REG)
++		   (compare:CCC
++		     (plus:DWIH (match_dup 1) (match_dup 2))
++		     (match_dup 1)))
+ 	      (set (match_dup 0)
+ 		   (plus:DWIH (match_dup 1) (match_dup 2)))])
+    (parallel [(set (match_dup 3)
+ 		   (plus:DWIH
+-		     (match_dup 4)
+ 		     (plus:DWIH
+ 		       (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
+-		       (match_dup 5))))
++		       (match_dup 4))
++		     (match_dup 5)))
+ 	      (clobber (reg:CC FLAGS_REG))])]
+   "split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);")
+ 
+-(define_insn "*add<mode>3_cc"
+-  [(set (reg:CC FLAGS_REG)
+-	(unspec:CC
+-	  [(match_operand:SWI48 1 "nonimmediate_operand" "%0,0")
+-	   (match_operand:SWI48 2 "<general_operand>" "r<i>,rm")]
+-	  UNSPEC_ADD_CARRY))
+-   (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
+-	(plus:SWI48 (match_dup 1) (match_dup 2)))]
+-  "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+-  "add{<imodesuffix>}\t{%2, %0|%0, %2}"
+-  [(set_attr "type" "alu")
+-   (set_attr "mode" "<MODE>")])
+-
+-(define_insn "addqi3_cc"
+-  [(set (reg:CC FLAGS_REG)
+-	(unspec:CC
+-	  [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
+-	   (match_operand:QI 2 "general_operand" "qn,qm")]
+-	  UNSPEC_ADD_CARRY))
+-   (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
+-	(plus:QI (match_dup 1) (match_dup 2)))]
+-  "ix86_binary_operator_ok (PLUS, QImode, operands)"
+-  "add{b}\t{%2, %0|%0, %2}"
+-  [(set_attr "type" "alu")
+-   (set_attr "mode" "QI")])
+-
+ (define_insn "*add<mode>_1"
+   [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r")
+ 	(plus:SWI48
+@@ -6160,10 +6135,10 @@
+ 		   (minus:DWIH (match_dup 1) (match_dup 2)))])
+    (parallel [(set (match_dup 3)
+ 		   (minus:DWIH
+-		     (match_dup 4)
+-		     (plus:DWIH
+-		       (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
+-		       (match_dup 5))))
++		     (minus:DWIH
++		       (match_dup 4)
++		       (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0)))
++		     (match_dup 5)))
+ 	      (clobber (reg:CC FLAGS_REG))])]
+   "split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);")
+ 
+@@ -6327,29 +6302,17 @@
+ 
+ ;; Add with carry and subtract with borrow
+ 
+-(define_expand "<plusminus_insn><mode>3_carry"
+-  [(parallel
+-    [(set (match_operand:SWI 0 "nonimmediate_operand")
+-	  (plusminus:SWI
+-	    (match_operand:SWI 1 "nonimmediate_operand")
+-	    (plus:SWI (match_operator:SWI 4 "ix86_carry_flag_operator"
+-		       [(match_operand 3 "flags_reg_operand")
+-			(const_int 0)])
+-		      (match_operand:SWI 2 "<general_operand>"))))
+-     (clobber (reg:CC FLAGS_REG))])]
+-  "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)")
+-
+-(define_insn "*<plusminus_insn><mode>3_carry"
++(define_insn "add<mode>3_carry"
+   [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+-	(plusminus:SWI
+-	  (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
++	(plus:SWI
+ 	  (plus:SWI
+-	    (match_operator 3 "ix86_carry_flag_operator"
+-	     [(reg FLAGS_REG) (const_int 0)])
+-	    (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))))
++	    (match_operator:SWI 4 "ix86_carry_flag_operator"
++	     [(match_operand 3 "flags_reg_operand") (const_int 0)])
++	    (match_operand:SWI 1 "nonimmediate_operand" "%0,0"))
++	  (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
+    (clobber (reg:CC FLAGS_REG))]
+   "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+-  "<plusminus_carry_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
++  "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
+   [(set_attr "type" "alu")
+    (set_attr "use_carry" "1")
+    (set_attr "pent_pair" "pu")
+@@ -6358,10 +6321,11 @@
+ (define_insn "*addsi3_carry_zext"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(zero_extend:DI
+-	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
+-		   (plus:SI (match_operator 3 "ix86_carry_flag_operator"
+-			     [(reg FLAGS_REG) (const_int 0)])
+-			    (match_operand:SI 2 "x86_64_general_operand" "rme")))))
++	  (plus:SI
++	    (plus:SI (match_operator:SI 3 "ix86_carry_flag_operator"
++		      [(reg FLAGS_REG) (const_int 0)])
++		     (match_operand:SI 1 "register_operand" "%0"))
++	    (match_operand:SI 2 "x86_64_general_operand" "rme"))))
+    (clobber (reg:CC FLAGS_REG))]
+   "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
+   "adc{l}\t{%2, %k0|%k0, %2}"
+@@ -6370,45 +6334,96 @@
+    (set_attr "pent_pair" "pu")
+    (set_attr "mode" "SI")])
+ 
++;; There is no point to generate ADCX instruction. ADC is shorter and faster.
++
++(define_insn "addcarry<mode>"
++  [(set (reg:CCC FLAGS_REG)
++	(compare:CCC
++	  (plus:SWI48
++	    (plus:SWI48
++	      (match_operator:SWI48 4 "ix86_carry_flag_operator"
++	       [(match_operand 3 "flags_reg_operand") (const_int 0)])
++	      (match_operand:SWI48 1 "nonimmediate_operand" "%0"))
++	    (match_operand:SWI48 2 "nonimmediate_operand" "rm"))
++	  (match_dup 1)))
++   (set (match_operand:SWI48 0 "register_operand" "=r")
++	(plus:SWI48 (plus:SWI48 (match_op_dup 4
++				 [(match_dup 3) (const_int 0)])
++				(match_dup 1))
++		    (match_dup 2)))]
++  "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
++  "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
++  [(set_attr "type" "alu")
++   (set_attr "use_carry" "1")
++   (set_attr "pent_pair" "pu")
++   (set_attr "mode" "<MODE>")])
++
++(define_insn "sub<mode>3_carry"
++  [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
++	(minus:SWI
++	  (minus:SWI
++	    (match_operand:SWI 1 "nonimmediate_operand" "0,0")
++	    (match_operator:SWI 4 "ix86_carry_flag_operator"
++	     [(match_operand 3 "flags_reg_operand") (const_int 0)]))
++	  (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
++   (clobber (reg:CC FLAGS_REG))]
++  "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
++  "sbb{<imodesuffix>}\t{%2, %0|%0, %2}"
++  [(set_attr "type" "alu")
++   (set_attr "use_carry" "1")
++   (set_attr "pent_pair" "pu")
++   (set_attr "mode" "<MODE>")])
++
+ (define_insn "*subsi3_carry_zext"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(zero_extend:DI
+-	  (minus:SI (match_operand:SI 1 "register_operand" "0")
+-		    (plus:SI (match_operator 3 "ix86_carry_flag_operator"
+-			      [(reg FLAGS_REG) (const_int 0)])
+-			     (match_operand:SI 2 "x86_64_general_operand" "rme")))))
++	  (minus:SI
++	    (minus:SI
++	      (match_operand:SI 1 "register_operand" "0")
++	      (match_operator:SI 3 "ix86_carry_flag_operator"
++	       [(reg FLAGS_REG) (const_int 0)]))
++	    (match_operand:SI 2 "x86_64_general_operand" "rme"))))
+    (clobber (reg:CC FLAGS_REG))]
+   "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
+   "sbb{l}\t{%2, %k0|%k0, %2}"
+   [(set_attr "type" "alu")
++   (set_attr "use_carry" "1")
+    (set_attr "pent_pair" "pu")
+    (set_attr "mode" "SI")])
+-
+-;; ADCX instruction
+ 
+-(define_insn "adcx<mode>3"
++(define_insn "subborrow<mode>"
+   [(set (reg:CCC FLAGS_REG)
+ 	(compare:CCC
++	  (match_operand:SWI48 1 "nonimmediate_operand" "0")
+ 	  (plus:SWI48
+-	    (match_operand:SWI48 1 "nonimmediate_operand" "%0")
+-	    (plus:SWI48
+-	      (match_operator 4 "ix86_carry_flag_operator"
+-	       [(match_operand 3 "flags_reg_operand") (const_int 0)])
+-	      (match_operand:SWI48 2 "nonimmediate_operand" "rm")))
+-	  (const_int 0)))
++	    (match_operator:SWI48 4 "ix86_carry_flag_operator"
++	     [(match_operand 3 "flags_reg_operand") (const_int 0)])
++	    (match_operand:SWI48 2 "nonimmediate_operand" "rm"))))
+    (set (match_operand:SWI48 0 "register_operand" "=r")
+-	(plus:SWI48 (match_dup 1)
+-		    (plus:SWI48 (match_op_dup 4
+-				 [(match_dup 3) (const_int 0)])
+-				(match_dup 2))))]
+-  "TARGET_ADX && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+-  "adcx\t{%2, %0|%0, %2}"
++	(minus:SWI48 (minus:SWI48 (match_dup 1)
++				  (match_op_dup 4
++				   [(match_dup 3) (const_int 0)]))
++		     (match_dup 2)))]
++  "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
++  "sbb{<imodesuffix>}\t{%2, %0|%0, %2}"
+   [(set_attr "type" "alu")
+    (set_attr "use_carry" "1")
++   (set_attr "pent_pair" "pu")
+    (set_attr "mode" "<MODE>")])
+ 
+ ;; Overflow setting add instructions
+ 
++(define_expand "addqi3_cconly_overflow"
++  [(parallel
++     [(set (reg:CCC FLAGS_REG)
++	   (compare:CCC
++	     (plus:QI
++	       (match_operand:QI 0 "nonimmediate_operand")
++	       (match_operand:QI 1 "general_operand"))
++	     (match_dup 0)))
++      (clobber (match_scratch:QI 2))])]
++  "!(MEM_P (operands[0]) && MEM_P (operands[1]))")
++
+ (define_insn "*add<mode>3_cconly_overflow"
+   [(set (reg:CCC FLAGS_REG)
+ 	(compare:CCC
+@@ -8754,9 +8769,9 @@
+      (set (match_dup 0) (neg:DWIH (match_dup 1)))])
+    (parallel
+     [(set (match_dup 2)
+-	  (plus:DWIH (match_dup 3)
+-		     (plus:DWIH (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
+-				(const_int 0))))
++	  (plus:DWIH (plus:DWIH (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
++				(match_dup 3))
++		     (const_int 0)))
+      (clobber (reg:CC FLAGS_REG))])
+    (parallel
+     [(set (match_dup 2)
+@@ -13237,7 +13252,8 @@
  	(call:P
  	 (mem:QI (match_operand 2 "constant_call_address_operand" "Bz"))
  	 (match_operand 3)))
@@ -533662,7 +534169,7 @@ Index: gcc/config/i386/i386.md
  	     UNSPEC_TLS_GD)]
    "TARGET_64BIT"
  {
-@@ -13261,8 +13265,9 @@
+@@ -13261,8 +13277,9 @@
  	 (mem:QI (plus:DI (match_operand:DI 2 "register_operand" "b")
  			  (match_operand:DI 3 "immediate_operand" "i")))
  	 (match_operand 4)))
@@ -533674,7 +534181,7 @@ Index: gcc/config/i386/i386.md
    "TARGET_64BIT && ix86_cmodel == CM_LARGE_PIC && !TARGET_PECOFF
     && GET_CODE (operands[3]) == CONST
     && GET_CODE (XEXP (operands[3], 0)) == UNSPEC
-@@ -13283,7 +13288,8 @@
+@@ -13283,7 +13300,8 @@
  	  (call:P
  	   (mem:QI (match_operand 2))
  	   (const_int 0)))
@@ -533684,7 +534191,7 @@ Index: gcc/config/i386/i386.md
  	       UNSPEC_TLS_GD)])]
    "TARGET_64BIT"
    "ix86_tls_descriptor_calls_expanded_in_cfun = true;")
-@@ -13333,7 +13339,7 @@
+@@ -13333,7 +13351,7 @@
  	(call:P
  	 (mem:QI (match_operand 1 "constant_call_address_operand" "Bz"))
  	 (match_operand 2)))
@@ -533693,7 +534200,7 @@ Index: gcc/config/i386/i386.md
    "TARGET_64BIT"
  {
    output_asm_insn
-@@ -13351,7 +13357,7 @@
+@@ -13351,7 +13369,7 @@
  	 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "b")
  			  (match_operand:DI 2 "immediate_operand" "i")))
  	 (match_operand 3)))
@@ -533702,7 +534209,7 @@ Index: gcc/config/i386/i386.md
    "TARGET_64BIT && ix86_cmodel == CM_LARGE_PIC && !TARGET_PECOFF
     && GET_CODE (operands[2]) == CONST
     && GET_CODE (XEXP (operands[2], 0)) == UNSPEC
-@@ -13372,7 +13378,7 @@
+@@ -13372,7 +13390,7 @@
  	   (call:P
  	    (mem:QI (match_operand 1))
  	    (const_int 0)))
@@ -533711,7 +534218,7 @@ Index: gcc/config/i386/i386.md
    "TARGET_64BIT"
    "ix86_tls_descriptor_calls_expanded_in_cfun = true;")
  
-@@ -17431,8 +17437,8 @@
+@@ -17431,8 +17449,8 @@
  ;; lifetime information then.
  
  (define_peephole2
@@ -533722,7 +534229,7 @@ Index: gcc/config/i386/i386.md
    "optimize_insn_for_speed_p ()
     && ((TARGET_NOT_UNPAIRABLE
  	&& (!MEM_P (operands[0])
-@@ -17576,8 +17582,10 @@
+@@ -17576,8 +17594,10 @@
                       [(match_dup 0)
                        (match_operand 2 "memory_operand")]))]
    "REGNO (operands[0]) != REGNO (operands[1])
@@ -533735,7 +534242,7 @@ Index: gcc/config/i386/i386.md
    [(set (match_dup 0) (match_dup 2))
     (set (match_dup 0)
          (match_op_dup 3 [(match_dup 0) (match_dup 1)]))])
-@@ -17725,7 +17733,7 @@
+@@ -17725,7 +17745,7 @@
  	(match_operand 1 "const0_operand"))]
    "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
     && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
@@ -533744,7 +534251,7 @@ Index: gcc/config/i386/i386.md
     && peep2_regno_dead_p (0, FLAGS_REG)"
    [(parallel [(set (match_dup 0) (const_int 0))
  	      (clobber (reg:CC FLAGS_REG))])]
-@@ -17746,6 +17754,7 @@
+@@ -17746,6 +17766,7 @@
    [(set (match_operand:SWI248 0 "register_operand")
  	(const_int -1))]
    "(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
@@ -533752,7 +534259,7 @@ Index: gcc/config/i386/i386.md
     && peep2_regno_dead_p (0, FLAGS_REG)"
    [(parallel [(set (match_dup 0) (const_int -1))
  	      (clobber (reg:CC FLAGS_REG))])]
-@@ -18113,11 +18122,13 @@
+@@ -18113,11 +18134,13 @@
  
    operands[1] = gen_rtx_PLUS (word_mode, base,
  			      gen_rtx_MULT (word_mode, index, GEN_INT (scale)));
@@ -533942,7 +534449,112 @@ Index: gcc/config/i386/i386.c
  	  && (count < (unsigned HOST_WIDE_INT) size_needed
  	      || (align_bytes == 0
  		  && count < ((unsigned HOST_WIDE_INT) size_needed
-@@ -50335,6 +50337,14 @@
+@@ -25557,7 +25559,7 @@
+ 
+   /* Avoid branch in fixing the byte.  */
+   tmpreg = gen_lowpart (QImode, tmpreg);
+-  emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
++  emit_insn (gen_addqi3_cconly_overflow (tmpreg, tmpreg));
+   tmp = gen_rtx_REG (CCmode, FLAGS_REG);
+   cmp = gen_rtx_LTU (VOIDmode, tmp, const0_rtx);
+   emit_insn (ix86_gen_sub3_carry (out, out, GEN_INT (3), tmp, cmp));
+@@ -39522,53 +39524,41 @@
+       return target;
+ 
+     case IX86_BUILTIN_SBB32:
+-      icode = CODE_FOR_subsi3_carry;
++      icode = CODE_FOR_subborrowsi;
+       mode0 = SImode;
+-      goto addcarryx;
++      goto handlecarry;
+ 
+     case IX86_BUILTIN_SBB64:
+-      icode = CODE_FOR_subdi3_carry;
++      icode = CODE_FOR_subborrowdi;
+       mode0 = DImode;
+-      goto addcarryx;
++      goto handlecarry;
+ 
+     case IX86_BUILTIN_ADDCARRYX32:
+-      icode = TARGET_ADX ? CODE_FOR_adcxsi3 : CODE_FOR_addsi3_carry;
++      icode = CODE_FOR_addcarrysi;
+       mode0 = SImode;
+-      goto addcarryx;
++      goto handlecarry;
+ 
+     case IX86_BUILTIN_ADDCARRYX64:
+-      icode = TARGET_ADX ? CODE_FOR_adcxdi3 : CODE_FOR_adddi3_carry;
++      icode = CODE_FOR_addcarrydi;
+       mode0 = DImode;
+ 
+-addcarryx:
++    handlecarry:
+       arg0 = CALL_EXPR_ARG (exp, 0); /* unsigned char c_in.  */
+       arg1 = CALL_EXPR_ARG (exp, 1); /* unsigned int src1.  */
+       arg2 = CALL_EXPR_ARG (exp, 2); /* unsigned int src2.  */
+       arg3 = CALL_EXPR_ARG (exp, 3); /* unsigned int *sum_out.  */
+ 
+-      op0 = gen_reg_rtx (QImode);
+-
+-      /* Generate CF from input operand.  */
+       op1 = expand_normal (arg0);
+       op1 = copy_to_mode_reg (QImode, convert_to_mode (QImode, op1, 1));
+-      emit_insn (gen_addqi3_cc (op0, op1, constm1_rtx));
+ 
+-      /* Gen ADCX instruction to compute X+Y+CF.  */
+       op2 = expand_normal (arg1);
++      if (!register_operand (op2, mode0))
++	op2 = copy_to_mode_reg (mode0, op2);
++
+       op3 = expand_normal (arg2);
+-
+-      if (!REG_P (op2))
+-	op2 = copy_to_mode_reg (mode0, op2);
+-      if (!REG_P (op3))
++      if (!register_operand (op3, mode0))
+ 	op3 = copy_to_mode_reg (mode0, op3);
+ 
+-      op0 = gen_reg_rtx (mode0);
+-
+-      op4 = gen_rtx_REG (CCCmode, FLAGS_REG);
+-      pat = gen_rtx_LTU (VOIDmode, op4, const0_rtx);
+-      emit_insn (GEN_FCN (icode) (op0, op2, op3, op4, pat));
+-
+-      /* Store the result.  */
+       op4 = expand_normal (arg3);
+       if (!address_operand (op4, VOIDmode))
+ 	{
+@@ -39575,8 +39565,17 @@
+ 	  op4 = convert_memory_address (Pmode, op4);
+ 	  op4 = copy_addr_to_reg (op4);
+ 	}
+-      emit_move_insn (gen_rtx_MEM (mode0, op4), op0);
+ 
++      /* Generate CF from input operand.  */
++      emit_insn (gen_addqi3_cconly_overflow (op1, constm1_rtx));
++
++      /* Generate instruction that consumes CF.  */
++      op0 = gen_reg_rtx (mode0);
++
++      op1 = gen_rtx_REG (CCCmode, FLAGS_REG);
++      pat = gen_rtx_LTU (mode0, op1, const0_rtx);
++      emit_insn (GEN_FCN (icode) (op0, op2, op3, op1, pat));
++
+       /* Return current CF value.  */
+       if (target == 0)
+         target = gen_reg_rtx (QImode);
+@@ -39583,6 +39582,10 @@
+ 
+       PUT_MODE (pat, QImode);
+       emit_insn (gen_rtx_SET (VOIDmode, target, pat));
++
++      /* Store the result.  */
++      emit_move_insn (gen_rtx_MEM (mode0, op4), op0);
++
+       return target;
+ 
+     case IX86_BUILTIN_READ_FLAGS:
+@@ -50335,6 +50338,14 @@
    unsigned int size = INTVAL (operands[1]);
    unsigned int pos = INTVAL (operands[2]);
  
@@ -533957,7 +534569,7 @@ Index: gcc/config/i386/i386.c
    if (GET_CODE (dst) == SUBREG)
      {
        pos += SUBREG_BYTE (dst) * BITS_PER_UNIT;
-@@ -50341,9 +50351,6 @@
+@@ -50341,9 +50352,6 @@
        dst = SUBREG_REG (dst);
      }
  
@@ -533967,7 +534579,7 @@ Index: gcc/config/i386/i386.c
    switch (GET_MODE (dst))
      {
      case V16QImode:
-@@ -50391,6 +50398,10 @@
+@@ -50391,6 +50399,10 @@
  	    return false;
  	  }
  
@@ -533978,7 +534590,7 @@ Index: gcc/config/i386/i386.c
  	rtx d = dst;
  	if (GET_MODE (dst) != dstmode)
  	  d = gen_reg_rtx (dstmode);
-@@ -51516,7 +51527,7 @@
+@@ -51516,7 +51528,7 @@
  static unsigned HOST_WIDE_INT
  ix86_memmodel_check (unsigned HOST_WIDE_INT val)
  {
@@ -533987,7 +534599,7 @@ Index: gcc/config/i386/i386.c
    bool strong;
  
    if (val & ~(unsigned HOST_WIDE_INT)(IX86_HLE_ACQUIRE|IX86_HLE_RELEASE
-@@ -51527,14 +51538,14 @@
+@@ -51527,14 +51539,14 @@
  	       "Unknown architecture specific memory model");
        return MEMMODEL_SEQ_CST;
      }
@@ -535644,6 +536256,29 @@ Index: libgfortran/configure
  else
  
  
+Index: libgfortran/runtime/error.c
+===================================================================
+--- a/src/libgfortran/runtime/error.c	(.../tags/gcc_5_2_0_release)
++++ b/src/libgfortran/runtime/error.c	(.../branches/gcc-5-branch)
+@@ -221,8 +221,16 @@
+ #ifdef HAVE_STRERROR_L
+   locale_t myloc = newlocale (LC_CTYPE_MASK | LC_MESSAGES_MASK, "",
+ 			      (locale_t) 0);
+-  char *p = strerror_l (errnum, myloc);
+-  freelocale (myloc);
++  char *p;
++  if (myloc)
++    {
++      p = strerror_l (errnum, myloc);
++      freelocale (myloc);
++    }
++  else
++    /* newlocale might fail e.g. due to running out of memory, fall
++       back to the simpler strerror.  */
++    p = strerror (errnum);
+   return p;
+ #elif defined(HAVE_STRERROR_R)
+ #ifdef HAVE_USELOCALE
 Index: libgfortran/configure.ac
 ===================================================================
 --- a/src/libgfortran/configure.ac	(.../tags/gcc_5_2_0_release)
@@ -535666,7 +536301,12 @@ Index: libgfortran/ChangeLog
 ===================================================================
 --- a/src/libgfortran/ChangeLog	(.../tags/gcc_5_2_0_release)
 +++ b/src/libgfortran/ChangeLog	(.../branches/gcc-5-branch)
-@@ -1,3 +1,20 @@
+@@ -1,3 +1,25 @@
++2015-09-02  Janne Blomqvist  <jb@gcc.gnu.org>
++
++	PR libfortran/67414
++	* runtime/error.c (gf_strerror): Handle newlocale() failure.
++
 +2015-08-28  James Greenhalgh  <james.greenhalgh@arm.com>
 +
 +	* configure.ac: Define HAVE_FTRUNCATE for ARM/AArch64/SH newlib