* Update to SVN 20150825 (r227166, 5.2.1) from the gcc-5-branch.

git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-5@8206 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca

4 files changed, 443 insertions, 91 deletions

diff --git a/debian/changelog b/debian/changelog
index 0140edf..46046c2 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,13 +1,13 @@
 gcc-5 (5.2.1-16) UNRELEASED; urgency=medium
 
-  * Update to SVN 20150820 (r227033, 5.2.1) from the gcc-5-branch.
+  * Update to SVN 20150825 (r227166, 5.2.1) from the gcc-5-branch.
     - Backport the filesystem TS library.
   * libstdc++-dev: Install libstdc++fs.a.
   * Again, configure with --enable-targets=powerpcle-linux on ppc64el.
   * Apply proposed patch for PR target/67211 (ppc64el).
   * libgo-dev: Install libgolibbegin.a.
 
- -- Matthias Klose <doko@debian.org>  Wed, 19 Aug 2015 18:04:00 +0200
+ -- Matthias Klose <doko@debian.org>  Tue, 25 Aug 2015 15:56:11 +0200
 
 gcc-5 (5.2.1-15) unstable; urgency=medium
 
diff --git a/debian/patches/pr67211.diff b/debian/patches/pr67211.diff
deleted file mode 100644
index 75cc85e..0000000
--- a/debian/patches/pr67211.diff
+++ /dev/null
@@ -1,76 +0,0 @@
-# DP: Proposed patch for PR target/67211
-
-2015-08-19  Michael Meissner  <meissner@linux.vnet.ibm.com>
-
-	PR target/67211
-	* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Set
-	-mefficient-unaligned-vsx on ISA 2.7.
-
-	* config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Convert
-	option to a masked option.
-
-	* config/rs6000/rs6000.c (rs6000_option_override_internal): Rework
-	logic for -mefficient-unaligned-vsx so that it is set via an arch
-	ISA option, instead of being set if -mtune=power8 is set.
-
---- a/src/gcc/config/rs6000/rs6000-cpus.def
-+++ b/src/gcc/config/rs6000/rs6000-cpus.def
-@@ -53,6 +53,7 @@
- 				 | OPTION_MASK_P8_VECTOR		\
- 				 | OPTION_MASK_CRYPTO			\
- 				 | OPTION_MASK_DIRECT_MOVE		\
-+				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
- 				 | OPTION_MASK_HTM			\
- 				 | OPTION_MASK_QUAD_MEMORY		\
-   				 | OPTION_MASK_QUAD_MEMORY_ATOMIC	\
-@@ -78,6 +79,7 @@
- 				 | OPTION_MASK_DFP			\
- 				 | OPTION_MASK_DIRECT_MOVE		\
- 				 | OPTION_MASK_DLMZB			\
-+				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
- 				 | OPTION_MASK_FPRND			\
- 				 | OPTION_MASK_HTM			\
- 				 | OPTION_MASK_ISEL			\
---- a/src/gcc/config/rs6000/rs6000.opt
-+++ b/src/gcc/config/rs6000/rs6000.opt
-@@ -212,7 +212,7 @@ Target Undocumented Var(TARGET_ALLOW_MOV
- ; Allow/disallow the movmisalign in DF/DI vectors
- 
- mefficient-unaligned-vector
--Target Undocumented Report Var(TARGET_EFFICIENT_UNALIGNED_VSX) Init(-1) Save
-+Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
- ; Consider unaligned VSX accesses to be efficient/inefficient
- 
- mallow-df-permute
---- a/src/gcc/config/rs6000/rs6000.c
-+++ b/src/gcc/config/rs6000/rs6000.c
-@@ -4256,15 +4256,21 @@ rs6000_option_override_internal (bool gl
-      TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
-      TARGET_EFFICIENT_UNALIGNED_VSX must be as well.  The converse is
-      not true.  */
--  if (TARGET_EFFICIENT_UNALIGNED_VSX == -1) {
--    if (TARGET_VSX && rs6000_cpu == PROCESSOR_POWER8
--	&& TARGET_ALLOW_MOVMISALIGN != 0)
--      TARGET_EFFICIENT_UNALIGNED_VSX = 1;
--    else
--      TARGET_EFFICIENT_UNALIGNED_VSX = 0;
--  }
-+  if (TARGET_EFFICIENT_UNALIGNED_VSX && !TARGET_VSX)
-+    {
-+      error ("-mefficient-unaligned-vsx requires -mvsx");
-+      rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
-+    }
-+
-+  if (TARGET_EFFICIENT_UNALIGNED_VSX && !TARGET_ALLOW_MOVMISALIGN)
-+    {
-+      if ((rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX) != 0)
-+	error ("-mefficient-unaligned-vsx requires -mallow-movmisalign");
-+      rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
-+    }
- 
--  if (TARGET_ALLOW_MOVMISALIGN == -1 && rs6000_cpu == PROCESSOR_POWER8)
-+  /* Set -mallow-movmisalign to on explicitly if we have ISA 2.07 support.  */
-+  if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR & TARGET_DIRECT_MOVE)
-     TARGET_ALLOW_MOVMISALIGN = 1;
- 
-   /* Set the builtin mask of the various options used that could affect which
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index f0fa7ac..e36c22d 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 5 branch upto 20150819 (r227033).
+# DP: updates from the 5 branch upto 20150825 (r227166).
 
 last_update()
 {
 	cat > ${dir}LAST_UPDATED <EOF
-Thu Aug 20 15:48:55 CEST 2015
-Thu Aug 20 13:48:55 UTC 2015 (revision 227033)
+Tue Aug 25 15:52:53 CEST 2015
+Tue Aug 25 13:52:53 UTC 2015 (revision 227166)
 EOF
 }
 
@@ -12,6 +12,83 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_5_2_0_release svn://gcc.gnu.o
 	| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
 	| awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0'
 
+Index: libgomp/iter.c
+===================================================================
+--- a/src/libgomp/iter.c	(.../tags/gcc_5_2_0_release)
++++ b/src/libgomp/iter.c	(.../branches/gcc-5-branch)
+@@ -218,7 +218,7 @@
+ 	}
+     }
+ 
+-  start = ws->next;
++  start = __atomic_load_n (&ws->next, MEMMODEL_RELAXED);
+   while (1)
+     {
+       long left = end - start;
+@@ -301,7 +301,7 @@
+   long start, end, nend, incr;
+   unsigned long chunk_size;
+ 
+-  start = ws->next;
++  start = __atomic_load_n (&ws->next, MEMMODEL_RELAXED);
+   end = ws->end;
+   incr = ws->incr;
+   chunk_size = ws->chunk_size;
+Index: libgomp/iter_ull.c
+===================================================================
+--- a/src/libgomp/iter_ull.c	(.../tags/gcc_5_2_0_release)
++++ b/src/libgomp/iter_ull.c	(.../branches/gcc-5-branch)
+@@ -219,7 +219,7 @@
+ 	}
+     }
+ 
+-  start = ws->next_ull;
++  start = __atomic_load_n (&ws->next_ull, MEMMODEL_RELAXED);
+   while (1)
+     {
+       gomp_ull left = end - start;
+@@ -305,7 +305,7 @@
+   gomp_ull start, end, nend, incr;
+   gomp_ull chunk_size;
+ 
+-  start = ws->next_ull;
++  start = __atomic_load_n (&ws->next_ull, MEMMODEL_RELAXED);
+   end = ws->end_ull;
+   incr = ws->incr_ull;
+   chunk_size = ws->chunk_size_ull;
+Index: libgomp/ChangeLog
+===================================================================
+--- a/src/libgomp/ChangeLog	(.../tags/gcc_5_2_0_release)
++++ b/src/libgomp/ChangeLog	(.../branches/gcc-5-branch)
+@@ -1,3 +1,13 @@
++2015-08-24  Joost VandeVondele  <vondele@gnu.gcc.org>
++
++	PR libgomp/66761
++	PR libgomp/67303
++	* iter.c (gomp_iter_dynamic_next): Employ an atomic load.
++	(gomp_iter_guided_next): Idem.
++	* iter_ull.c (gomp_iter_ull_dynamic_next): Idem.
++	(gomp_iter_ull_guided_next): Idem.
++	* config/linux/wait.h (do_spin): Idem.
++
+ 2015-07-16  Release Manager
+ 
+ 	* GCC 5.2.0 released.
+Index: libgomp/config/linux/wait.h
+===================================================================
+--- a/src/libgomp/config/linux/wait.h	(.../tags/gcc_5_2_0_release)
++++ b/src/libgomp/config/linux/wait.h	(.../branches/gcc-5-branch)
+@@ -49,7 +49,9 @@
+ {
+   unsigned long long i, count = gomp_spin_count_var;
+ 
+-  if (__builtin_expect (gomp_managed_threads > gomp_available_cpus, 0))
++  if (__builtin_expect (__atomic_load_n (&gomp_managed_threads,
++                                         MEMMODEL_RELAXED)
++                        > gomp_available_cpus, 0))
+     count = gomp_throttled_spin_count_var;
+   for (i = 0; i < count; i++)
+     if (__builtin_expect (__atomic_load_n (addr, MEMMODEL_RELAXED) != val, 0))
 Index: libstdc++-v3/configure
 ===================================================================
 --- a/src/libstdc++-v3/configure	(.../tags/gcc_5_2_0_release)
@@ -11733,7 +11810,7 @@ Index: gcc/DATESTAMP
 +++ b/src/gcc/DATESTAMP	(.../branches/gcc-5-branch)
 @@ -1 +1 @@
 -20150716
-+20150820
++20150825
 Index: gcc/postreload.c
 ===================================================================
 --- a/src/gcc/postreload.c	(.../tags/gcc_5_2_0_release)
@@ -12198,7 +12275,38 @@ Index: gcc/ChangeLog
 ===================================================================
 --- a/src/gcc/ChangeLog	(.../tags/gcc_5_2_0_release)
 +++ b/src/gcc/ChangeLog	(.../branches/gcc-5-branch)
-@@ -1,3 +1,503 @@
+@@ -1,3 +1,534 @@
++2015-08-25  Dominik Vogt  <vogt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2015-08-21  Dominik Vogt  <vogt@linux.vnet.ibm.com>
++
++    	* config/s390/s390-builtins.def: Fix value range of vec_load_bndry.
++
++2015-08-24  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from mainline:
++	2015-08-24  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/67211
++	* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Set
++	-mefficient-unaligned-vsx on ISA 2.7.
++
++	* config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Convert
++	option to a masked option.
++
++	* config/rs6000/rs6000.c (rs6000_option_override_internal): Rework
++	logic for -mefficient-unaligned-vsx so that it is set via an arch
++	ISA option, instead of being set if -mtune=power8 is set. Move
++	-mefficient-unaligned-vsx and -mallow-movmisalign handling to be
++	near other default option handling.
++
++2015-08-20  Georg-Johann Lay  <avr@gjlay.de>
++
++	* config/avr/avr.c (avr_insert_attributes): In diagnostic essage:
++	Multiply argument avr_n_flash by 64 to match unit of "KiB".
++	(avr_pgm_check_var_decl): Same.
++
 +2015-08-18  Segher Boessenkool  <segher@kernel.crashing.org>
 +
 +	Backport from mainline:
@@ -12702,7 +12810,7 @@ Index: gcc/ChangeLog
  2015-07-16  Release Manager
  
  	* GCC 5.2.0 released.
-@@ -119,8 +619,8 @@
+@@ -119,8 +650,8 @@
  2015-07-09  Iain Sandoe  <iain@codesourcery.com>
  
  	PR target/66523
@@ -13634,6 +13742,91 @@ Index: gcc/testsuite/gcc.target/i386/mpx/pr66581.c
 +  *d = 1;
 +  goto *a;
 +}
+Index: gcc/testsuite/gcc.target/s390/zvector/vec-load_bndry-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/zvector/vec-load_bndry-1.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/zvector/vec-load_bndry-1.c	(.../branches/gcc-5-branch)
+@@ -0,0 +1,80 @@
++/* { dg-do compile { target { s390*-*-* } } } */
++/* { dg-options "-O0 -mzarch -march=z13 -mzvector" } */
++
++#include <vecintrin.h>
++
++signed char
++foo64 (signed char *p)
++{
++  return vec_load_bndry (p, 64)[0];
++  /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),0" 1 } } */
++}
++
++signed char
++foo128 (signed char *p)
++{
++  return
++    vec_load_bndry (p, 128)[0]
++    + vec_load_bndry (p + 16, 128)[0];
++  /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),1" 2 } } */
++}
++
++signed char
++foo256 (signed char *p)
++{
++  return
++    vec_load_bndry (p, 256)[0]
++    + vec_load_bndry (p + 16, 256)[0]
++    + vec_load_bndry (p + 32, 256)[0];
++  /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),2" 3 } } */
++}
++
++signed char
++foo512 (signed char *p)
++{
++  return
++    vec_load_bndry (p, 512)[0]
++    + vec_load_bndry (p + 16, 512)[0]
++    + vec_load_bndry (p + 32, 512)[0]
++    + vec_load_bndry (p + 48, 512)[0];
++  /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),3" 4 } } */
++}
++
++signed char
++foo1024 (signed char *p)
++{
++  return
++    vec_load_bndry (p, 1024)[0]
++    + vec_load_bndry (p + 16, 1024)[0]
++    + vec_load_bndry (p + 32, 1024)[0]
++    + vec_load_bndry (p + 48, 1024)[0]
++    + vec_load_bndry (p + 64, 1024)[0];
++  /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),4" 5 } } */
++}
++
++signed char
++foo2048 (signed char *p)
++{
++  return
++    vec_load_bndry (p, 2048)[0]
++    + vec_load_bndry (p + 16, 2048)[0]
++    + vec_load_bndry (p + 32, 2048)[0]
++    + vec_load_bndry (p + 48, 2048)[0]
++    + vec_load_bndry (p + 64, 2048)[0]
++    + vec_load_bndry (p + 80, 2048)[0];
++  /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),5" 6 } } */
++}
++
++signed char
++foo4096 (signed char *p)
++{
++  return
++    vec_load_bndry (p, 4096)[0]
++    + vec_load_bndry (p + 16, 4096)[0]
++    + vec_load_bndry (p + 32, 4096)[0]
++    + vec_load_bndry (p + 48, 4096)[0]
++    + vec_load_bndry (p + 64, 4096)[0]
++    + vec_load_bndry (p + 80, 4096)[0]
++    + vec_load_bndry (p + 96, 4096)[0];
++  /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),6" 7 } } */
++}
 Index: gcc/testsuite/gfortran.dg/pr66864.f90
 ===================================================================
 --- a/src/gcc/testsuite/gfortran.dg/pr66864.f90	(.../tags/gcc_5_2_0_release)
@@ -14556,7 +14749,22 @@ Index: gcc/testsuite/ChangeLog
 ===================================================================
 --- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_5_2_0_release)
 +++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-5-branch)
-@@ -1,3 +1,362 @@
+@@ -1,3 +1,377 @@
++2015-08-25  Dominik Vogt  <vogt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2015-08-21  Dominik Vogt  <vogt@linux.vnet.ibm.com>
++
++    	* gcc.target/s390/zvector/vec-load_bndry-1.c: New test.
++
++2015-08-24  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Backport from mainline:
++	2015-08-24  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/67211
++	* g++.dg/pr67211.C: New test.
++
 +2015-08-18  Segher Boessenkool  <segher@kernel.crashing.org>
 +
 +	Backport from mainline:
@@ -14919,7 +15127,7 @@ Index: gcc/testsuite/ChangeLog
  2015-07-16  Release Manager
  
  	* GCC 5.2.0 released.
-@@ -792,7 +1151,7 @@
+@@ -792,7 +1166,7 @@
  	Add missing ChangeLog entry for r222341.
  
  	Backport from trunk r222273
@@ -14928,6 +15136,61 @@ Index: gcc/testsuite/ChangeLog
  	* gcc.target/i386/avx512bw-vpermi2w-2.c: Fix includes to use actual
  	headers.
  	* gcc.target/i386/avx512bw-vpermt2w-2.c: Likewise.
+Index: gcc/testsuite/g++.dg/pr67211.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/pr67211.C	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/g++.dg/pr67211.C	(.../branches/gcc-5-branch)
+@@ -0,0 +1,50 @@
++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
++/* { dg-require-effective-target powerpc_p8vector_ok } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
++/* { dg-options "-mcpu=power7 -mtune=power8 -O3 -w" } */
++
++/* target/67211, compiler got a 'insn does not satisfy its constraints' error.  */
++
++template <typename _InputIterator, typename _ForwardIterator>
++void find_first_of(_InputIterator, _InputIterator, _ForwardIterator p3,
++                   _ForwardIterator p4) {
++  for (; p3 != p4; ++p3)
++    ;
++}
++
++template <typename, typename, typename> struct A {
++  int _S_buffer_size;
++  int *_M_cur;
++  int *_M_first;
++  int *_M_last;
++  int **_M_node;
++  void operator++() {
++    if (_M_cur == _M_last)
++      m_fn1(_M_node + 1);
++  }
++  void m_fn1(int **p1) {
++    _M_node = p1;
++    _M_first = *p1;
++    _M_last = _M_first + _S_buffer_size;
++  }
++};
++
++template <typename _Tp, typename _Ref, typename _Ptr>
++bool operator==(A<_Tp, _Ref, _Ptr>, A<_Tp, _Ref, _Ptr>);
++template <typename _Tp, typename _Ref, typename _Ptr>
++bool operator!=(A<_Tp, _Ref, _Ptr> p1, A<_Tp, _Ref, _Ptr> p2) {
++  return p1 == p2;
++}
++
++class B {
++public:
++  A<int, int, int> m_fn2();
++};
++struct {
++  B j;
++} a;
++void Linked() {
++  A<int, int, int> b, c, d;
++  find_first_of(d, c, b, a.j.m_fn2());
++}
 Index: gcc/testsuite/g++.dg/cpp0x/alignas1.C
 ===================================================================
 --- a/src/gcc/testsuite/g++.dg/cpp0x/alignas1.C	(.../tags/gcc_5_2_0_release)
@@ -533059,6 +533322,35 @@ Index: gcc/config/alpha/alpha.c
      emit_label (XEXP (label2, 0));
  }
  
+Index: gcc/config/s390/s390-builtins.def
+===================================================================
+--- a/src/gcc/config/s390/s390-builtins.def	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/config/s390/s390-builtins.def	(.../branches/gcc-5-branch)
+@@ -438,15 +438,15 @@
+ B_DEF      (s390_vllezg,                vec_insert_and_zerov2di,0,              B_VX,               0,                  BT_FN_UV2DI_ULONGLONGCONSTPTR)
+ 
+ OB_DEF     (s390_vec_load_bndry,        s390_vec_load_bndry_s8,s390_vec_load_bndry_dbl,B_VX,        BT_FN_OV4SI_INTCONSTPTR_INT)
+-OB_DEF_VAR (s390_vec_load_bndry_s8,     s390_vlbb,          O2_U3,              BT_OV_V16QI_SCHARCONSTPTR_USHORT)
+-OB_DEF_VAR (s390_vec_load_bndry_u8,     s390_vlbb,          O2_U3,              BT_OV_UV16QI_UCHARCONSTPTR_USHORT)
+-OB_DEF_VAR (s390_vec_load_bndry_s16,    s390_vlbb,          O2_U3,              BT_OV_V8HI_SHORTCONSTPTR_USHORT)
+-OB_DEF_VAR (s390_vec_load_bndry_u16,    s390_vlbb,          O2_U3,              BT_OV_UV8HI_USHORTCONSTPTR_USHORT)
+-OB_DEF_VAR (s390_vec_load_bndry_s32,    s390_vlbb,          O2_U3,              BT_OV_V4SI_INTCONSTPTR_USHORT)
+-OB_DEF_VAR (s390_vec_load_bndry_u32,    s390_vlbb,          O2_U3,              BT_OV_UV4SI_UINTCONSTPTR_USHORT)
+-OB_DEF_VAR (s390_vec_load_bndry_s64,    s390_vlbb,          O2_U3,              BT_OV_V2DI_LONGLONGCONSTPTR_USHORT)
+-OB_DEF_VAR (s390_vec_load_bndry_u64,    s390_vlbb,          O2_U3,              BT_OV_UV2DI_ULONGLONGCONSTPTR_USHORT)
+-OB_DEF_VAR (s390_vec_load_bndry_dbl,    s390_vlbb,          O2_U3,              BT_OV_V2DF_DBLCONSTPTR_USHORT)
++OB_DEF_VAR (s390_vec_load_bndry_s8,     s390_vlbb,          O2_U16,              BT_OV_V16QI_SCHARCONSTPTR_USHORT)
++OB_DEF_VAR (s390_vec_load_bndry_u8,     s390_vlbb,          O2_U16,              BT_OV_UV16QI_UCHARCONSTPTR_USHORT)
++OB_DEF_VAR (s390_vec_load_bndry_s16,    s390_vlbb,          O2_U16,              BT_OV_V8HI_SHORTCONSTPTR_USHORT)
++OB_DEF_VAR (s390_vec_load_bndry_u16,    s390_vlbb,          O2_U16,              BT_OV_UV8HI_USHORTCONSTPTR_USHORT)
++OB_DEF_VAR (s390_vec_load_bndry_s32,    s390_vlbb,          O2_U16,              BT_OV_V4SI_INTCONSTPTR_USHORT)
++OB_DEF_VAR (s390_vec_load_bndry_u32,    s390_vlbb,          O2_U16,              BT_OV_UV4SI_UINTCONSTPTR_USHORT)
++OB_DEF_VAR (s390_vec_load_bndry_s64,    s390_vlbb,          O2_U16,              BT_OV_V2DI_LONGLONGCONSTPTR_USHORT)
++OB_DEF_VAR (s390_vec_load_bndry_u64,    s390_vlbb,          O2_U16,              BT_OV_UV2DI_ULONGLONGCONSTPTR_USHORT)
++OB_DEF_VAR (s390_vec_load_bndry_dbl,    s390_vlbb,          O2_U16,              BT_OV_V2DF_DBLCONSTPTR_USHORT)
+ 
+ B_DEF      (s390_vlbb,                  vlbb,               0,                  B_VX,               O2_U3,              BT_FN_UV16QI_UCHARCONSTPTR_USHORT)
+ 
 Index: gcc/config/s390/s390.md
 ===================================================================
 --- a/src/gcc/config/s390/s390.md	(.../tags/gcc_5_2_0_release)
@@ -533596,6 +533888,32 @@ Index: gcc/config/avr/avr-dimode.md
    "%~call __<extend_u>mulsidi3"
    [(set_attr "adjust_len" "call")
     (set_attr "cc" "clobber")])
+Index: gcc/config/avr/avr.c
+===================================================================
+--- a/src/gcc/config/avr/avr.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/config/avr/avr.c	(.../branches/gcc-5-branch)
+@@ -9272,10 +9272,10 @@
+         {
+           if (TYPE_P (node))
+             error ("%qT uses address space %qs beyond flash of %d KiB",
+-                   node, avr_addrspace[as].name, avr_n_flash);
++                   node, avr_addrspace[as].name, 64 * avr_n_flash);
+           else
+             error ("%s %q+D uses address space %qs beyond flash of %d KiB",
+-                   reason, node, avr_addrspace[as].name, avr_n_flash);
++                   reason, node, avr_addrspace[as].name, 64 * avr_n_flash);
+         }
+       else
+         {
+@@ -9322,7 +9322,7 @@
+       if (avr_addrspace[as].segment >= avr_n_flash)
+         {
+           error ("variable %q+D located in address space %qs beyond flash "
+-                 "of %d KiB", node, avr_addrspace[as].name, avr_n_flash);
++                 "of %d KiB", node, avr_addrspace[as].name, 64 * avr_n_flash);
+         }
+       else if (!AVR_HAVE_LPM && avr_addrspace[as].pointer_size > 2)
+ 	{
 Index: gcc/config/ia64/ia64.c
 ===================================================================
 --- a/src/gcc/config/ia64/ia64.c	(.../tags/gcc_5_2_0_release)
@@ -534042,11 +534360,113 @@ Index: gcc/config/rs6000/htm.md
  			    UNSPECV_HTM_TABORT))]
    "TARGET_HTM"
    "tabort. %0"
+Index: gcc/config/rs6000/rs6000-cpus.def
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000-cpus.def	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/config/rs6000/rs6000-cpus.def	(.../branches/gcc-5-branch)
+@@ -53,6 +53,7 @@
+ 				 | OPTION_MASK_P8_VECTOR		\
+ 				 | OPTION_MASK_CRYPTO			\
+ 				 | OPTION_MASK_DIRECT_MOVE		\
++				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
+ 				 | OPTION_MASK_HTM			\
+ 				 | OPTION_MASK_QUAD_MEMORY		\
+   				 | OPTION_MASK_QUAD_MEMORY_ATOMIC	\
+@@ -78,6 +79,7 @@
+ 				 | OPTION_MASK_DFP			\
+ 				 | OPTION_MASK_DIRECT_MOVE		\
+ 				 | OPTION_MASK_DLMZB			\
++				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
+ 				 | OPTION_MASK_FPRND			\
+ 				 | OPTION_MASK_HTM			\
+ 				 | OPTION_MASK_ISEL			\
+Index: gcc/config/rs6000/rs6000.opt
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.opt	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/config/rs6000/rs6000.opt	(.../branches/gcc-5-branch)
+@@ -212,7 +212,7 @@
+ ; Allow/disallow the movmisalign in DF/DI vectors
+ 
+ mefficient-unaligned-vector
+-Target Undocumented Report Var(TARGET_EFFICIENT_UNALIGNED_VSX) Init(-1) Save
++Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
+ ; Consider unaligned VSX accesses to be efficient/inefficient
+ 
+ mallow-df-permute
 Index: gcc/config/rs6000/rs6000.c
 ===================================================================
 --- a/src/gcc/config/rs6000/rs6000.c	(.../tags/gcc_5_2_0_release)
 +++ b/src/gcc/config/rs6000/rs6000.c	(.../branches/gcc-5-branch)
-@@ -20537,12 +20537,15 @@
+@@ -3692,6 +3692,45 @@
+       && optimize >= 3)
+     rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
+ 
++  /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
++     support. If we only have ISA 2.06 support, and the user did not specify
++     the switch, leave it set to -1 so the movmisalign patterns are enabled,
++     but we don't enable the full vectorization support  */
++  if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
++    TARGET_ALLOW_MOVMISALIGN = 1;
++
++  else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
++    {
++      if (TARGET_ALLOW_MOVMISALIGN > 0)
++	error ("-mallow-movmisalign requires -mvsx");
++
++      TARGET_ALLOW_MOVMISALIGN = 0;
++    }
++
++  /* Determine when unaligned vector accesses are permitted, and when
++     they are preferred over masked Altivec loads.  Note that if
++     TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
++     TARGET_EFFICIENT_UNALIGNED_VSX must be as well.  The converse is
++     not true.  */
++  if (TARGET_EFFICIENT_UNALIGNED_VSX)
++    {
++      if (!TARGET_VSX)
++	{
++	  if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
++	    error ("-mefficient-unaligned-vsx requires -mvsx");
++
++	  rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
++	}
++
++      else if (!TARGET_ALLOW_MOVMISALIGN)
++	{
++	  if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
++	    error ("-mefficient-unaligned-vsx requires -mallow-movmisalign");
++
++	  rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
++	}
++    }
++
+   if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
+     rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
+ 
+@@ -4251,22 +4290,6 @@
+ 	}
+     }
+ 
+-  /* Determine when unaligned vector accesses are permitted, and when
+-     they are preferred over masked Altivec loads.  Note that if
+-     TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
+-     TARGET_EFFICIENT_UNALIGNED_VSX must be as well.  The converse is
+-     not true.  */
+-  if (TARGET_EFFICIENT_UNALIGNED_VSX == -1) {
+-    if (TARGET_VSX && rs6000_cpu == PROCESSOR_POWER8
+-	&& TARGET_ALLOW_MOVMISALIGN != 0)
+-      TARGET_EFFICIENT_UNALIGNED_VSX = 1;
+-    else
+-      TARGET_EFFICIENT_UNALIGNED_VSX = 0;
+-  }
+-
+-  if (TARGET_ALLOW_MOVMISALIGN == -1 && rs6000_cpu == PROCESSOR_POWER8)
+-    TARGET_ALLOW_MOVMISALIGN = 1;
+-
+   /* Set the builtin mask of the various options used that could affect which
+      builtins were used.  In the past we used target_flags, but we've run out
+      of bits, and some options like SPE and PAIRED are no longer in
+@@ -20537,12 +20560,15 @@
      case MEMMODEL_RELAXED:
      case MEMMODEL_CONSUME:
      case MEMMODEL_ACQUIRE:
@@ -534062,7 +534482,7 @@ Index: gcc/config/rs6000/rs6000.c
        emit_insn (gen_hwsync ());
        break;
      default:
-@@ -20559,10 +20562,13 @@
+@@ -20559,10 +20585,13 @@
      case MEMMODEL_RELAXED:
      case MEMMODEL_CONSUME:
      case MEMMODEL_RELEASE:
@@ -534076,7 +534496,7 @@ Index: gcc/config/rs6000/rs6000.c
        emit_insn (gen_isync ());
        break;
      default:
-@@ -20662,8 +20668,8 @@
+@@ -20662,8 +20691,8 @@
    oldval = operands[3];
    newval = operands[4];
    is_weak = (INTVAL (operands[5]) != 0);
@@ -534087,7 +534507,7 @@ Index: gcc/config/rs6000/rs6000.c
    orig_mode = mode = GET_MODE (mem);
  
    mask = shift = NULL_RTX;
-@@ -20751,12 +20757,12 @@
+@@ -20751,12 +20780,12 @@
        emit_unlikely_jump (x, label1);
      }
  
@@ -534102,6 +534522,15 @@ Index: gcc/config/rs6000/rs6000.c
      emit_label (XEXP (label2, 0));
  
    if (shift)
+@@ -32274,6 +32303,8 @@
+   { "crypto",			OPTION_MASK_CRYPTO,		false, true  },
+   { "direct-move",		OPTION_MASK_DIRECT_MOVE,	false, true  },
+   { "dlmzb",			OPTION_MASK_DLMZB,		false, true  },
++  { "efficient-unaligned-vsx",	OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
++								false, true  },
+   { "fprnd",			OPTION_MASK_FPRND,		false, true  },
+   { "hard-dfp",			OPTION_MASK_DFP,		false, true  },
+   { "htm",			OPTION_MASK_HTM,		false, true  },
 Index: gcc/config/rs6000/sync.md
 ===================================================================
 --- a/src/gcc/config/rs6000/sync.md	(.../tags/gcc_5_2_0_release)
diff --git a/debian/rules.patch b/debian/rules.patch
index 0269649..8bf488a 100644
--- a/debian/rules.patch
+++ b/debian/rules.patch
@@ -89,7 +89,6 @@ debian_patches += \
 	gccgo-sendfile-fix \
 	pr66368 \
 	gcc-sh-bootstrap-ignore \
-	pr67211 \
 
 ifeq ($(libstdcxx_abi),new)
   debian_patches += libstdc++-functexcept