* Update to SVN 20150828 (r227299, 5.2.1) from the gcc-5-branch.

git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-5@8211 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca

2 files changed, 282 insertions, 11 deletions

diff --git a/debian/changelog b/debian/changelog
index 46046c2..20be06e 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,13 +1,13 @@
 gcc-5 (5.2.1-16) UNRELEASED; urgency=medium
 
-  * Update to SVN 20150825 (r227166, 5.2.1) from the gcc-5-branch.
+  * Update to SVN 20150828 (r227299, 5.2.1) from the gcc-5-branch.
     - Backport the filesystem TS library.
   * libstdc++-dev: Install libstdc++fs.a.
   * Again, configure with --enable-targets=powerpcle-linux on ppc64el.
   * Apply proposed patch for PR target/67211 (ppc64el).
   * libgo-dev: Install libgolibbegin.a.
 
- -- Matthias Klose <doko@debian.org>  Tue, 25 Aug 2015 15:56:11 +0200
+ -- Matthias Klose <doko@debian.org>  Fri, 28 Aug 2015 16:20:22 +0200
 
 gcc-5 (5.2.1-15) unstable; urgency=medium
 
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index e36c22d..7b529a5 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 5 branch upto 20150825 (r227166).
+# DP: updates from the 5 branch upto 20150828 (r227299).
 
 last_update()
 {
 	cat > ${dir}LAST_UPDATED <EOF
-Tue Aug 25 15:52:53 CEST 2015
-Tue Aug 25 13:52:53 UTC 2015 (revision 227166)
+Fri Aug 28 16:16:24 CEST 2015
+Fri Aug 28 14:16:24 UTC 2015 (revision 227299)
 EOF
 }
 
@@ -7208,6 +7208,23 @@ Index: libstdc++-v3/include/bits/locale_conv.h
  _GLIBCXX_END_NAMESPACE_CXX11
  
    /// Buffer conversions
+Index: libstdc++-v3/include/bits/regex_scanner.tcc
+===================================================================
+--- a/src/libstdc++-v3/include/bits/regex_scanner.tcc	(.../tags/gcc_5_2_0_release)
++++ b/src/libstdc++-v3/include/bits/regex_scanner.tcc	(.../branches/gcc-5-branch)
+@@ -99,6 +99,12 @@
+       auto __c = *_M_current++;
+       const char* __pos;
+ 
++      if (std::strchr(_M_spec_char, _M_ctype.narrow(__c, '\0')) == nullptr)
++	{
++	  _M_token = _S_token_ord_char;
++	  _M_value.assign(1, __c);
++	  return;
++	}
+       if (__c == '\\')
+ 	{
+ 	  if (_M_current == _M_end)
 Index: libstdc++-v3/include/bits/quoted_string.h
 ===================================================================
 --- a/src/libstdc++-v3/include/bits/quoted_string.h	(.../tags/gcc_5_2_0_release)
@@ -7620,7 +7637,19 @@ Index: libstdc++-v3/ChangeLog
 ===================================================================
 --- a/src/libstdc++-v3/ChangeLog	(.../tags/gcc_5_2_0_release)
 +++ b/src/libstdc++-v3/ChangeLog	(.../branches/gcc-5-branch)
-@@ -1,3 +1,132 @@
+@@ -1,3 +1,144 @@
++2015-08-28  Tim Shen  <timshen@google.com>
++
++	Backport from mainline
++	2015-08-28  Tim Shen  <timshen@google.com>
++
++	PR libstdc++/67362
++	* include/bits/regex_scanner.tcc (_Scanner<>::_M_scan_normal):
++	Always returns ordinary char token if the char isn't
++	considered a special char.
++	* testsuite/28_regex/regression.cc: New test file for collecting
++	regression testcases from, typically, bugzilla.
++
 +2015-08-20  Jonathan Wakely  <jwakely@redhat.com>
 +
 +	* python/Makefile.am: Ensure gdb.py is installed for libstdc++ not
@@ -7834,6 +7863,53 @@ Index: libstdc++-v3/testsuite/Makefile.in
  mostlyclean-generic:
  
  clean-generic:
+Index: libstdc++-v3/testsuite/28_regex/regression.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/28_regex/regression.cc	(.../tags/gcc_5_2_0_release)
++++ b/src/libstdc++-v3/testsuite/28_regex/regression.cc	(.../branches/gcc-5-branch)
+@@ -0,0 +1,42 @@
++// { dg-options "-std=gnu++11" }
++
++//
++// Copyright (C) 2015 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++//
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++//
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <testsuite_hooks.h>
++#include <testsuite_regex.h>
++
++using namespace __gnu_test;
++using namespace std;
++
++// PR libstdc++/67362
++void
++test01()
++{
++  bool test __attribute__((unused)) = true;
++
++  regex re("((.)", regex_constants::basic);
++}
++
++int
++main()
++{
++  test01();
++  return 0;
++}
++
 Index: libstdc++-v3/testsuite/28_regex/algorithms/regex_match/cstring_bracket_01.cc
 ===================================================================
 --- a/src/libstdc++-v3/testsuite/28_regex/algorithms/regex_match/cstring_bracket_01.cc	(.../tags/gcc_5_2_0_release)
@@ -11810,7 +11886,7 @@ Index: gcc/DATESTAMP
 +++ b/src/gcc/DATESTAMP	(.../branches/gcc-5-branch)
 @@ -1 +1 @@
 -20150716
-+20150825
++20150828
 Index: gcc/postreload.c
 ===================================================================
 --- a/src/gcc/postreload.c	(.../tags/gcc_5_2_0_release)
@@ -12275,7 +12351,25 @@ Index: gcc/ChangeLog
 ===================================================================
 --- a/src/gcc/ChangeLog	(.../tags/gcc_5_2_0_release)
 +++ b/src/gcc/ChangeLog	(.../branches/gcc-5-branch)
-@@ -1,3 +1,534 @@
+@@ -1,3 +1,552 @@
++2015-08-27  Pat Haugen  <pthaugen@us.ibm.com>
++
++	Backport from mainline:
++	2015-08-27  Pat Haugen  <pthaugen@us.ibm.com>
++
++	* config/rs6000/vector.md (vec_shr_<mode>): Fix to do a shift
++	instead of a rotate.
++
++2015-08-26  Renlin Li  <renlin.li@arm.com>
++
++	Backport from mainline
++	2015-08-24  Renlin Li  <renlin.li@arm.com>
++
++	* config/arm/arm-protos.h (arm_valid_symbolic_address_p): Declare.
++	* config/arm/arm.c (arm_valid_symbolic_address_p): Define.
++	* config/arm/arm.md (arm_movt): Use arm_valid_symbolic_address_p.
++	* config/arm/constraints.md ("j"): Add check for high code.
++
 +2015-08-25  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 +
 +	Backport from mainline
@@ -12810,7 +12904,7 @@ Index: gcc/ChangeLog
  2015-07-16  Release Manager
  
  	* GCC 5.2.0 released.
-@@ -119,8 +650,8 @@
+@@ -119,8 +668,8 @@
  2015-07-09  Iain Sandoe  <iain@codesourcery.com>
  
  	PR target/66523
@@ -12888,6 +12982,45 @@ Index: gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c
 +{
 +  return __builtin_tabort (10);
 +}
+Index: gcc/testsuite/gcc.target/powerpc/vec-shr.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vec-shr.c	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vec-shr.c	(.../branches/gcc-5-branch)
+@@ -0,0 +1,34 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -fno-inline" } */
++
++#include <stdlib.h>
++
++typedef struct { double r, i; } complex;
++#define LEN 30
++complex c[LEN];
++double d[LEN];
++
++void
++foo (complex *c, double *d, int len1)
++{
++  int i;
++  for (i = 0; i < len1; i++)
++    {
++      c[i].r = d[i];
++      c[i].i = 0.0;
++    }
++}
++
++int
++main (void)
++{
++  int i;
++  for (i = 0; i < LEN; i++)
++    d[i] = (double) i;
++  foo (c, d, LEN);
++  for (i=0;i<LEN;i++)
++    if ((c[i].r != (double) i) || (c[i].i != 0.0))
++      abort ();
++  return 0;
++}
++
 Index: gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c	(.../tags/gcc_5_2_0_release)
@@ -14749,7 +14882,14 @@ Index: gcc/testsuite/ChangeLog
 ===================================================================
 --- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_5_2_0_release)
 +++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-5-branch)
-@@ -1,3 +1,377 @@
+@@ -1,3 +1,384 @@
++2015-08-27  Pat Haugen  <pthaugen@us.ibm.com>
++
++	Backport from mainline:
++	2015-08-27  Pat Haugen  <pthaugen@us.ibm.com>
++
++	* gcc.target/powerpc/vec-shr.c: New.
++
 +2015-08-25  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 +
 +	Backport from mainline
@@ -15127,7 +15267,7 @@ Index: gcc/testsuite/ChangeLog
  2015-07-16  Release Manager
  
  	* GCC 5.2.0 released.
-@@ -792,7 +1166,7 @@
+@@ -792,7 +1173,7 @@
  	Add missing ChangeLog entry for r222341.
  
  	Backport from trunk r222273
@@ -534347,6 +534487,62 @@ Index: gcc/config/aarch64/aarch64-linux.h
     -X						\
     %{mbig-endian:-EB} %{mlittle-endian:-EL}     \
     -maarch64linux%{mabi=ilp32:32}%{mbig-endian:b}"
+Index: gcc/config/rs6000/vector.md
+===================================================================
+--- a/src/gcc/config/rs6000/vector.md	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/config/rs6000/vector.md	(.../branches/gcc-5-branch)
+@@ -918,6 +918,8 @@
+ ;; General shift amounts can be supported using vsro + vsr. We're
+ ;; not expecting to see these yet (the vectorizer currently
+ ;; generates only shifts by a whole number of vector elements).
++;; Note that the vec_shr operation is actually defined as 
++;; 'shift toward element 0' so is a shr for LE and shl for BE.
+ (define_expand "vec_shr_<mode>"
+   [(match_operand:VEC_L 0 "vlogical_operand" "")
+    (match_operand:VEC_L 1 "vlogical_operand" "")
+@@ -928,6 +930,7 @@
+   rtx bitshift = operands[2];
+   rtx shift;
+   rtx insn;
++  rtx zero_reg, op1, op2;
+   HOST_WIDE_INT bitshift_val;
+   HOST_WIDE_INT byteshift_val;
+ 
+@@ -937,19 +940,29 @@
+   if (bitshift_val & 0x7)
+     FAIL;
+   byteshift_val = (bitshift_val >> 3);
++  zero_reg = gen_reg_rtx (<MODE>mode);
++  emit_move_insn (zero_reg, CONST0_RTX (<MODE>mode));
+   if (!BYTES_BIG_ENDIAN)
+-    byteshift_val = 16 - byteshift_val;
++    {
++      byteshift_val = 16 - byteshift_val;
++      op1 = zero_reg;
++      op2 = operands[1];
++    }
++  else
++    {
++      op1 = operands[1];
++      op2 = zero_reg;
++    }
++
+   if (TARGET_VSX && (byteshift_val & 0x3) == 0)
+     {
+       shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
+-      insn = gen_vsx_xxsldwi_<mode> (operands[0], operands[1], operands[1],
+-				     shift);
++      insn = gen_vsx_xxsldwi_<mode> (operands[0], op1, op2, shift);
+     }
+   else
+     {
+       shift = gen_rtx_CONST_INT (QImode, byteshift_val);
+-      insn = gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
+-					shift);
++      insn = gen_altivec_vsldoi_<mode> (operands[0], op1, op2, shift);
+     }
+ 
+   emit_insn (insn);
 Index: gcc/config/rs6000/htm.md
 ===================================================================
 --- a/src/gcc/config/rs6000/htm.md	(.../tags/gcc_5_2_0_release)
@@ -534738,6 +534934,58 @@ Index: gcc/config/arm/arm.c
      arm_post_atomic_barrier (model);
  }
  
+@@ -28792,7 +28811,39 @@
+   #undef BRANCH
+ }
+ 
++/* Returns true if the pattern is a valid symbolic address, which is either a
++   symbol_ref or (symbol_ref + addend).
+ 
++   According to the ARM ELF ABI, the initial addend of REL-type relocations
++   processing MOVW and MOVT instructions is formed by interpreting the 16-bit
++   literal field of the instruction as a 16-bit signed value in the range
++   -32768 <= A < 32768.  */
++
++bool
++arm_valid_symbolic_address_p (rtx addr)
++{
++  rtx xop0, xop1 = NULL_RTX;
++  rtx tmp = addr;
++
++  if (GET_CODE (tmp) == SYMBOL_REF || GET_CODE (tmp) == LABEL_REF)
++    return true;
++
++  /* (const (plus: symbol_ref const_int))  */
++  if (GET_CODE (addr) == CONST)
++    tmp = XEXP (addr, 0);
++
++  if (GET_CODE (tmp) == PLUS)
++    {
++      xop0 = XEXP (tmp, 0);
++      xop1 = XEXP (tmp, 1);
++
++      if (GET_CODE (xop0) == SYMBOL_REF && CONST_INT_P (xop1))
++	  return IN_RANGE (INTVAL (xop1), -0x8000, 0x7fff);
++    }
++
++  return false;
++}
++
+ /* Returns true if a valid comparison operation and makes
+    the operands in a form that is valid.  */
+ bool
+Index: gcc/config/arm/arm-protos.h
+===================================================================
+--- a/src/gcc/config/arm/arm-protos.h	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/config/arm/arm-protos.h	(.../branches/gcc-5-branch)
+@@ -312,6 +312,7 @@
+ 
+ extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
+ 					   rtx);
++extern bool arm_valid_symbolic_address_p (rtx);
+ extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
+ #endif /* RTX_CODE */
+ 
 Index: gcc/config/arm/vfp.md
 ===================================================================
 --- a/src/gcc/config/arm/vfp.md	(.../tags/gcc_5_2_0_release)
@@ -534779,6 +535027,20 @@ Index: gcc/config/arm/vfp.md
    "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
    "vnmul%?.f64\\t%P0, %P1, %P2"
    [(set_attr "predicable" "yes")
+Index: gcc/config/arm/constraints.md
+===================================================================
+--- a/src/gcc/config/arm/constraints.md	(.../tags/gcc_5_2_0_release)
++++ b/src/gcc/config/arm/constraints.md	(.../branches/gcc-5-branch)
+@@ -67,7 +67,8 @@
+ (define_constraint "j"
+  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
+  (and (match_test "TARGET_32BIT && arm_arch_thumb2")
+-      (ior (match_code "high")
++      (ior (and (match_code "high")
++		(match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
+ 	   (and (match_code "const_int")
+                 (match_test "(ival & 0xffff0000) == 0")))))
+ 
 Index: gcc/config/arm/sync.md
 ===================================================================
 --- a/src/gcc/config/arm/sync.md	(.../tags/gcc_5_2_0_release)
@@ -534844,6 +535106,15 @@ Index: gcc/config/arm/arm.md
  	   && !HARD_REGNO_MODE_OK (REGNO (operands[1]), DImode))
      {
        /* Avoid STRD's from an odd-numbered register pair in ARM state
+@@ -5662,7 +5662,7 @@
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ 	(lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ 		   (match_operand:SI 2 "general_operand"      "i")))]
+-  "arm_arch_thumb2"
++  "arm_arch_thumb2 && arm_valid_symbolic_address_p (operands[2])"
+   "movt%?\t%0, #:upper16:%c2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
 Index: gcc/config/pa/pa.md
 ===================================================================
 --- a/src/gcc/config/pa/pa.md	(.../tags/gcc_5_2_0_release)