diff options
| -rw-r--r-- | debian/changelog | 1 | ||||
| -rw-r--r-- | debian/patches/pr67211.diff | 76 | ||||
| -rw-r--r-- | debian/rules.patch | 1 |
3 files changed, 78 insertions, 0 deletions
diff --git a/debian/changelog b/debian/changelog index 3904cb4..fbc5de0 100644 --- a/debian/changelog +++ b/debian/changelog @@ -2,6 +2,7 @@ gcc-5 (5.2.1-16) UNRELEASED; urgency=medium * Update to SVN 20150819 (r227013, 5.2.1) from the gcc-5-branch. * Again, configure with --enable-targets=powerpcle-linux on ppc64el. + * Apply proposed patch for PR target/67211 (ppc64el). -- Matthias Klose <doko@debian.org> Wed, 19 Aug 2015 18:04:00 +0200 diff --git a/debian/patches/pr67211.diff b/debian/patches/pr67211.diff new file mode 100644 index 0000000..75cc85e --- /dev/null +++ b/debian/patches/pr67211.diff @@ -0,0 +1,76 @@ +# DP: Proposed patch for PR target/67211 + +2015-08-19 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/67211 + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Set + -mefficient-unaligned-vsx on ISA 2.7. + + * config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Convert + option to a masked option. + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Rework + logic for -mefficient-unaligned-vsx so that it is set via an arch + ISA option, instead of being set if -mtune=power8 is set. + +--- a/src/gcc/config/rs6000/rs6000-cpus.def ++++ b/src/gcc/config/rs6000/rs6000-cpus.def +@@ -53,6 +53,7 @@ + | OPTION_MASK_P8_VECTOR \ + | OPTION_MASK_CRYPTO \ + | OPTION_MASK_DIRECT_MOVE \ ++ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ + | OPTION_MASK_HTM \ + | OPTION_MASK_QUAD_MEMORY \ + | OPTION_MASK_QUAD_MEMORY_ATOMIC \ +@@ -78,6 +79,7 @@ + | OPTION_MASK_DFP \ + | OPTION_MASK_DIRECT_MOVE \ + | OPTION_MASK_DLMZB \ ++ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ + | OPTION_MASK_FPRND \ + | OPTION_MASK_HTM \ + | OPTION_MASK_ISEL \ +--- a/src/gcc/config/rs6000/rs6000.opt ++++ b/src/gcc/config/rs6000/rs6000.opt +@@ -212,7 +212,7 @@ Target Undocumented Var(TARGET_ALLOW_MOV + ; Allow/disallow the movmisalign in DF/DI vectors + + mefficient-unaligned-vector +-Target Undocumented Report Var(TARGET_EFFICIENT_UNALIGNED_VSX) Init(-1) Save ++Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags) + ; Consider unaligned VSX accesses to be efficient/inefficient + + mallow-df-permute +--- a/src/gcc/config/rs6000/rs6000.c ++++ b/src/gcc/config/rs6000/rs6000.c +@@ -4256,15 +4256,21 @@ rs6000_option_override_internal (bool gl + TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then + TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is + not true. */ +- if (TARGET_EFFICIENT_UNALIGNED_VSX == -1) { +- if (TARGET_VSX && rs6000_cpu == PROCESSOR_POWER8 +- && TARGET_ALLOW_MOVMISALIGN != 0) +- TARGET_EFFICIENT_UNALIGNED_VSX = 1; +- else +- TARGET_EFFICIENT_UNALIGNED_VSX = 0; +- } ++ if (TARGET_EFFICIENT_UNALIGNED_VSX && !TARGET_VSX) ++ { ++ error ("-mefficient-unaligned-vsx requires -mvsx"); ++ rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX; ++ } ++ ++ if (TARGET_EFFICIENT_UNALIGNED_VSX && !TARGET_ALLOW_MOVMISALIGN) ++ { ++ if ((rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX) != 0) ++ error ("-mefficient-unaligned-vsx requires -mallow-movmisalign"); ++ rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX; ++ } + +- if (TARGET_ALLOW_MOVMISALIGN == -1 && rs6000_cpu == PROCESSOR_POWER8) ++ /* Set -mallow-movmisalign to on explicitly if we have ISA 2.07 support. */ ++ if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR & TARGET_DIRECT_MOVE) + TARGET_ALLOW_MOVMISALIGN = 1; + + /* Set the builtin mask of the various options used that could affect which diff --git a/debian/rules.patch b/debian/rules.patch index 8bf488a..0269649 100644 --- a/debian/rules.patch +++ b/debian/rules.patch @@ -89,6 +89,7 @@ debian_patches += \ gccgo-sendfile-fix \ pr66368 \ gcc-sh-bootstrap-ignore \ + pr67211 \ ifeq ($(libstdcxx_abi),new) debian_patches += libstdc++-functexcept |