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# DP: Revert r78543 for Linaro builds
Index: b/src/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c
+++ b/src/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c
@@ -1,15 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target arm_arch_v7ve_ok } */
-/* { dg-options "-O2" } */
-/* { dg-add-options arm_arch_v7ve } */
-
-#include <stdatomic.h>
-
-atomic_llong x = 0;
-
-atomic_llong get_x()
-{
- return atomic_load(&x);
-}
-
-/* { dg-final { scan-assembler "ldrd" } } */
Index: b/src/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
+++ b/src/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
@@ -1,15 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target arm_arch_v7r_ok } */
-/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-r5" } } */
-/* { dg-options "-O2 -mcpu=cortex-r5" } */
-
-#include <stdatomic.h>
-
-atomic_llong x = 0;
-
-atomic_llong get_x()
-{
- return atomic_load(&x);
-}
-
-/* { dg-final { scan-assembler-not "ldrd" } } */
Index: b/src/gcc/config/arm/arm.c
===================================================================
--- a/src/gcc/config/arm/arm.c
+++ b/src/gcc/config/arm/arm.c
@@ -859,9 +859,6 @@ int arm_arch_thumb2;
int arm_arch_arm_hwdiv;
int arm_arch_thumb_hwdiv;
-/* Nonzero if this chip supports the Large Physical Address Extension. */
-int arm_arch_lpae;
-
/* Nonzero if chip disallows volatile memory access in IT block. */
int arm_arch_no_volatile_ce;
@@ -3184,7 +3181,6 @@ arm_option_override (void)
arm_arch_iwmmxt2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT2);
arm_arch_thumb_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB_DIV);
arm_arch_arm_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARM_DIV);
- arm_arch_lpae = ARM_FSET_HAS_CPU1 (insn_flags, FL_LPAE);
arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE);
arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32);
Index: b/src/gcc/config/arm/arm.h
===================================================================
--- a/src/gcc/config/arm/arm.h
+++ b/src/gcc/config/arm/arm.h
@@ -254,7 +254,8 @@ extern void (*arm_lang_output_object_att
#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
/* Nonzero if this chip supports LPAE. */
-#define TARGET_HAVE_LPAE (arm_arch_lpae)
+#define TARGET_HAVE_LPAE \
+ (arm_arch7 && ARM_FSET_HAS_CPU1 (insn_flags, FL_FOR_ARCH7VE))
/* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
Index: b/src/gcc/config/arm/arm-protos.h
===================================================================
--- a/src/gcc/config/arm/arm-protos.h
+++ b/src/gcc/config/arm/arm-protos.h
@@ -360,7 +360,7 @@ extern bool arm_is_constant_pool_ref (rt
#define FL_STRONG (1 << 8) /* StrongARM */
#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
#define FL_XSCALE (1 << 10) /* XScale */
-#define FL_LPAE (1 << 11) /* ARMv7-A LPAE. */
+/* spare (1 << 11) */
#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
@@ -412,7 +412,7 @@ extern bool arm_is_constant_pool_ref (rt
#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
-#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV | FL_LPAE)
+#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
@@ -608,9 +608,6 @@ extern int arm_arch_thumb2;
extern int arm_arch_arm_hwdiv;
extern int arm_arch_thumb_hwdiv;
-/* Nonzero if this chip supports the Large Physical Address Extension. */
-extern int arm_arch_lpae;
-
/* Nonzero if chip disallows volatile memory access in IT block. */
extern int arm_arch_no_volatile_ce;
|
