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author | Robert Mustacchi <rm@joyent.com> | 2011-06-24 13:49:54 -0700 |
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committer | Robert Mustacchi <rm@joyent.com> | 2011-06-24 13:49:54 -0700 |
commit | 68396ea9c0fe4f75ce30b1eba2c44c43c13344bb (patch) | |
tree | 802587d411d9db461e6500c5b635043315f81c27 /hw/realview_gic.c | |
download | illumos-kvm-cmd-68396ea9c0fe4f75ce30b1eba2c44c43c13344bb.tar.gz |
Initial commit of d32e8d0b8d9e0ef7cf7ab2e74548982972789dfc from qemu-kvm
Diffstat (limited to 'hw/realview_gic.c')
-rw-r--r-- | hw/realview_gic.c | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/hw/realview_gic.c b/hw/realview_gic.c new file mode 100644 index 0000000..db908b6 --- /dev/null +++ b/hw/realview_gic.c @@ -0,0 +1,79 @@ +/* + * ARM RealView Emulation Baseboard Interrupt Controller + * + * Copyright (c) 2006-2007 CodeSourcery. + * Written by Paul Brook + * + * This code is licenced under the GPL. + */ + +#include "sysbus.h" + +#define GIC_NIRQ 96 +#define NCPU 1 + +/* Only a single "CPU" interface is present. */ +static inline int +gic_get_current_cpu(void) +{ + return 0; +} + +#include "arm_gic.c" + +typedef struct { + gic_state gic; + int iomemtype; +} RealViewGICState; + +static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset) +{ + gic_state *s = (gic_state *)opaque; + return gic_cpu_read(s, gic_get_current_cpu(), offset); +} + +static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset, + uint32_t value) +{ + gic_state *s = (gic_state *)opaque; + gic_cpu_write(s, gic_get_current_cpu(), offset, value); +} + +static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = { + realview_gic_cpu_read, + realview_gic_cpu_read, + realview_gic_cpu_read +}; + +static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = { + realview_gic_cpu_write, + realview_gic_cpu_write, + realview_gic_cpu_write +}; + +static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base) +{ + RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); + cpu_register_physical_memory(base, 0x1000, s->iomemtype); + cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype); +} + +static int realview_gic_init(SysBusDevice *dev) +{ + RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); + + gic_init(&s->gic); + s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn, + realview_gic_cpu_writefn, s, + DEVICE_NATIVE_ENDIAN); + sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map); + return 0; +} + +static void realview_gic_register_devices(void) +{ + sysbus_register_dev("realview_gic", sizeof(RealViewGICState), + realview_gic_init); +} + +device_init(realview_gic_register_devices) |