diff options
| author | Robert Mustacchi <rm@joyent.com> | 2011-06-24 13:49:54 -0700 |
|---|---|---|
| committer | Robert Mustacchi <rm@joyent.com> | 2011-06-24 13:49:54 -0700 |
| commit | 68396ea9c0fe4f75ce30b1eba2c44c43c13344bb (patch) | |
| tree | 802587d411d9db461e6500c5b635043315f81c27 /target-mips | |
| download | illumos-kvm-cmd-68396ea9c0fe4f75ce30b1eba2c44c43c13344bb.tar.gz | |
Initial commit of d32e8d0b8d9e0ef7cf7ab2e74548982972789dfc from qemu-kvm
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/TODO | 52 | ||||
| -rw-r--r-- | target-mips/cpu.h | 659 | ||||
| -rw-r--r-- | target-mips/exec.h | 98 | ||||
| -rw-r--r-- | target-mips/helper.c | 696 | ||||
| -rw-r--r-- | target-mips/helper.h | 290 | ||||
| -rw-r--r-- | target-mips/machine.c | 308 | ||||
| -rw-r--r-- | target-mips/mips-defs.h | 72 | ||||
| -rw-r--r-- | target-mips/op_helper.c | 3044 | ||||
| -rw-r--r-- | target-mips/translate.c | 12746 | ||||
| -rw-r--r-- | target-mips/translate_init.c | 594 |
10 files changed, 18559 insertions, 0 deletions
diff --git a/target-mips/TODO b/target-mips/TODO new file mode 100644 index 0000000..9101881 --- /dev/null +++ b/target-mips/TODO @@ -0,0 +1,52 @@ +Unsolved issues/bugs in the mips/mipsel backend +----------------------------------------------- + +General +------- +- Unimplemented ASEs: + - MDMX + - SmartMIPS + - DSP r1 + - DSP r2 +- MT ASE only partially implemented and not functional +- Shadow register support only partially implemented, + lacks set switching on interrupt/exception. +- 34K ITC not implemented. +- A general lack of documentation, especially for technical internals. + Existing documentation is x86-centric. +- Reverse endianness bit not implemented +- The TLB emulation is very inefficient: + Qemu's softmmu implements a x86-style MMU, with separate entries + for read/write/execute, a TLB index which is just a modulo of the + virtual address, and a set of TLBs for each user/kernel/supervisor + MMU mode. + MIPS has a single entry for read/write/execute and only one MMU mode. + But it is fully associative with randomized entry indices, and uses + up to 256 ASID tags as additional matching criterion (which roughly + equates to 256 MMU modes). It also has a global flag which causes + entries to match regardless of ASID. + To cope with these differences, Qemu currently flushes the TLB at + each ASID change. Using the MMU modes to implement ASIDs hinges on + implementing the global bit efficiently. +- save/restore of the CPU state is not implemented (see machine.c). + +MIPS64 +------ +- Userland emulation (both n32 and n64) not functional. + +"Generic" 4Kc system emulation +------------------------------ +- Doesn't correspond to any real hardware. Should be removed some day, + U-Boot is the last remaining user. + +PICA 61 system emulation +------------------------ +- No framebuffer support yet. + +MALTA system emulation +---------------------- +- We fake firmware support instead of doing the real thing +- Real firmware (YAMON) falls over when trying to init RAM, presumably + due to lacking system controller emulation. +- Bonito system controller not implemented +- MSC1 system controller not implemented diff --git a/target-mips/cpu.h b/target-mips/cpu.h new file mode 100644 index 0000000..2419aa9 --- /dev/null +++ b/target-mips/cpu.h @@ -0,0 +1,659 @@ +#if !defined (__MIPS_CPU_H__) +#define __MIPS_CPU_H__ + +#define TARGET_HAS_ICE 1 + +#define ELF_MACHINE EM_MIPS + +#define CPUState struct CPUMIPSState + +#include "config.h" +#include "qemu-common.h" +#include "mips-defs.h" +#include "cpu-defs.h" +#include "softfloat.h" + +// uint_fast8_t and uint_fast16_t not in <sys/int_types.h> +// XXX: move that elsewhere +#if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10 +typedef unsigned char uint_fast8_t; +typedef unsigned int uint_fast16_t; +#endif + +struct CPUMIPSState; + +typedef struct r4k_tlb_t r4k_tlb_t; +struct r4k_tlb_t { + target_ulong VPN; + uint32_t PageMask; + uint_fast8_t ASID; + uint_fast16_t G:1; + uint_fast16_t C0:3; + uint_fast16_t C1:3; + uint_fast16_t V0:1; + uint_fast16_t V1:1; + uint_fast16_t D0:1; + uint_fast16_t D1:1; + target_ulong PFN[2]; +}; + +#if !defined(CONFIG_USER_ONLY) +typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; +struct CPUMIPSTLBContext { + uint32_t nb_tlb; + uint32_t tlb_in_use; + int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type); + void (*helper_tlbwi) (void); + void (*helper_tlbwr) (void); + void (*helper_tlbp) (void); + void (*helper_tlbr) (void); + union { + struct { + r4k_tlb_t tlb[MIPS_TLB_MAX]; + } r4k; + } mmu; +}; +#endif + +typedef union fpr_t fpr_t; +union fpr_t { + float64 fd; /* ieee double precision */ + float32 fs[2];/* ieee single precision */ + uint64_t d; /* binary double fixed-point */ + uint32_t w[2]; /* binary single fixed-point */ +}; +/* define FP_ENDIAN_IDX to access the same location + * in the fpr_t union regardless of the host endianess + */ +#if defined(HOST_WORDS_BIGENDIAN) +# define FP_ENDIAN_IDX 1 +#else +# define FP_ENDIAN_IDX 0 +#endif + +typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; +struct CPUMIPSFPUContext { + /* Floating point registers */ + fpr_t fpr[32]; + float_status fp_status; + /* fpu implementation/revision register (fir) */ + uint32_t fcr0; +#define FCR0_F64 22 +#define FCR0_L 21 +#define FCR0_W 20 +#define FCR0_3D 19 +#define FCR0_PS 18 +#define FCR0_D 17 +#define FCR0_S 16 +#define FCR0_PRID 8 +#define FCR0_REV 0 + /* fcsr */ + uint32_t fcr31; +#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) +#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) +#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) +#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) +#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) +#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) +#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) +#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) +#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) +#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) +#define FP_INEXACT 1 +#define FP_UNDERFLOW 2 +#define FP_OVERFLOW 4 +#define FP_DIV0 8 +#define FP_INVALID 16 +#define FP_UNIMPLEMENTED 32 +}; + +#define NB_MMU_MODES 3 + +typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; +struct CPUMIPSMVPContext { + int32_t CP0_MVPControl; +#define CP0MVPCo_CPA 3 +#define CP0MVPCo_STLB 2 +#define CP0MVPCo_VPC 1 +#define CP0MVPCo_EVP 0 + int32_t CP0_MVPConf0; +#define CP0MVPC0_M 31 +#define CP0MVPC0_TLBS 29 +#define CP0MVPC0_GS 28 +#define CP0MVPC0_PCP 27 +#define CP0MVPC0_PTLBE 16 +#define CP0MVPC0_TCA 15 +#define CP0MVPC0_PVPE 10 +#define CP0MVPC0_PTC 0 + int32_t CP0_MVPConf1; +#define CP0MVPC1_CIM 31 +#define CP0MVPC1_CIF 30 +#define CP0MVPC1_PCX 20 +#define CP0MVPC1_PCP2 10 +#define CP0MVPC1_PCP1 0 +}; + +typedef struct mips_def_t mips_def_t; + +#define MIPS_SHADOW_SET_MAX 16 +#define MIPS_TC_MAX 5 +#define MIPS_FPU_MAX 1 +#define MIPS_DSP_ACC 4 + +typedef struct TCState TCState; +struct TCState { + target_ulong gpr[32]; + target_ulong PC; + target_ulong HI[MIPS_DSP_ACC]; + target_ulong LO[MIPS_DSP_ACC]; + target_ulong ACX[MIPS_DSP_ACC]; + target_ulong DSPControl; + int32_t CP0_TCStatus; +#define CP0TCSt_TCU3 31 +#define CP0TCSt_TCU2 30 +#define CP0TCSt_TCU1 29 +#define CP0TCSt_TCU0 28 +#define CP0TCSt_TMX 27 +#define CP0TCSt_RNST 23 +#define CP0TCSt_TDS 21 +#define CP0TCSt_DT 20 +#define CP0TCSt_DA 15 +#define CP0TCSt_A 13 +#define CP0TCSt_TKSU 11 +#define CP0TCSt_IXMT 10 +#define CP0TCSt_TASID 0 + int32_t CP0_TCBind; +#define CP0TCBd_CurTC 21 +#define CP0TCBd_TBE 17 +#define CP0TCBd_CurVPE 0 + target_ulong CP0_TCHalt; + target_ulong CP0_TCContext; + target_ulong CP0_TCSchedule; + target_ulong CP0_TCScheFBack; + int32_t CP0_Debug_tcstatus; +}; + +typedef struct CPUMIPSState CPUMIPSState; +struct CPUMIPSState { + TCState active_tc; + CPUMIPSFPUContext active_fpu; + + uint32_t current_tc; + uint32_t current_fpu; + + uint32_t SEGBITS; + uint32_t PABITS; + target_ulong SEGMask; + target_ulong PAMask; + + int32_t CP0_Index; + /* CP0_MVP* are per MVP registers. */ + int32_t CP0_Random; + int32_t CP0_VPEControl; +#define CP0VPECo_YSI 21 +#define CP0VPECo_GSI 20 +#define CP0VPECo_EXCPT 16 +#define CP0VPECo_TE 15 +#define CP0VPECo_TargTC 0 + int32_t CP0_VPEConf0; +#define CP0VPEC0_M 31 +#define CP0VPEC0_XTC 21 +#define CP0VPEC0_TCS 19 +#define CP0VPEC0_SCS 18 +#define CP0VPEC0_DSC 17 +#define CP0VPEC0_ICS 16 +#define CP0VPEC0_MVP 1 +#define CP0VPEC0_VPA 0 + int32_t CP0_VPEConf1; +#define CP0VPEC1_NCX 20 +#define CP0VPEC1_NCP2 10 +#define CP0VPEC1_NCP1 0 + target_ulong CP0_YQMask; + target_ulong CP0_VPESchedule; + target_ulong CP0_VPEScheFBack; + int32_t CP0_VPEOpt; +#define CP0VPEOpt_IWX7 15 +#define CP0VPEOpt_IWX6 14 +#define CP0VPEOpt_IWX5 13 +#define CP0VPEOpt_IWX4 12 +#define CP0VPEOpt_IWX3 11 +#define CP0VPEOpt_IWX2 10 +#define CP0VPEOpt_IWX1 9 +#define CP0VPEOpt_IWX0 8 +#define CP0VPEOpt_DWX7 7 +#define CP0VPEOpt_DWX6 6 +#define CP0VPEOpt_DWX5 5 +#define CP0VPEOpt_DWX4 4 +#define CP0VPEOpt_DWX3 3 +#define CP0VPEOpt_DWX2 2 +#define CP0VPEOpt_DWX1 1 +#define CP0VPEOpt_DWX0 0 + target_ulong CP0_EntryLo0; + target_ulong CP0_EntryLo1; + target_ulong CP0_Context; + int32_t CP0_PageMask; + int32_t CP0_PageGrain; + int32_t CP0_Wired; + int32_t CP0_SRSConf0_rw_bitmask; + int32_t CP0_SRSConf0; +#define CP0SRSC0_M 31 +#define CP0SRSC0_SRS3 20 +#define CP0SRSC0_SRS2 10 +#define CP0SRSC0_SRS1 0 + int32_t CP0_SRSConf1_rw_bitmask; + int32_t CP0_SRSConf1; +#define CP0SRSC1_M 31 +#define CP0SRSC1_SRS6 20 +#define CP0SRSC1_SRS5 10 +#define CP0SRSC1_SRS4 0 + int32_t CP0_SRSConf2_rw_bitmask; + int32_t CP0_SRSConf2; +#define CP0SRSC2_M 31 +#define CP0SRSC2_SRS9 20 +#define CP0SRSC2_SRS8 10 +#define CP0SRSC2_SRS7 0 + int32_t CP0_SRSConf3_rw_bitmask; + int32_t CP0_SRSConf3; +#define CP0SRSC3_M 31 +#define CP0SRSC3_SRS12 20 +#define CP0SRSC3_SRS11 10 +#define CP0SRSC3_SRS10 0 + int32_t CP0_SRSConf4_rw_bitmask; + int32_t CP0_SRSConf4; +#define CP0SRSC4_SRS15 20 +#define CP0SRSC4_SRS14 10 +#define CP0SRSC4_SRS13 0 + int32_t CP0_HWREna; + target_ulong CP0_BadVAddr; + int32_t CP0_Count; + target_ulong CP0_EntryHi; + int32_t CP0_Compare; + int32_t CP0_Status; +#define CP0St_CU3 31 +#define CP0St_CU2 30 +#define CP0St_CU1 29 +#define CP0St_CU0 28 +#define CP0St_RP 27 +#define CP0St_FR 26 +#define CP0St_RE 25 +#define CP0St_MX 24 +#define CP0St_PX 23 +#define CP0St_BEV 22 +#define CP0St_TS 21 +#define CP0St_SR 20 +#define CP0St_NMI 19 +#define CP0St_IM 8 +#define CP0St_KX 7 +#define CP0St_SX 6 +#define CP0St_UX 5 +#define CP0St_KSU 3 +#define CP0St_ERL 2 +#define CP0St_EXL 1 +#define CP0St_IE 0 + int32_t CP0_IntCtl; +#define CP0IntCtl_IPTI 29 +#define CP0IntCtl_IPPC1 26 +#define CP0IntCtl_VS 5 + int32_t CP0_SRSCtl; +#define CP0SRSCtl_HSS 26 +#define CP0SRSCtl_EICSS 18 +#define CP0SRSCtl_ESS 12 +#define CP0SRSCtl_PSS 6 +#define CP0SRSCtl_CSS 0 + int32_t CP0_SRSMap; +#define CP0SRSMap_SSV7 28 +#define CP0SRSMap_SSV6 24 +#define CP0SRSMap_SSV5 20 +#define CP0SRSMap_SSV4 16 +#define CP0SRSMap_SSV3 12 +#define CP0SRSMap_SSV2 8 +#define CP0SRSMap_SSV1 4 +#define CP0SRSMap_SSV0 0 + int32_t CP0_Cause; +#define CP0Ca_BD 31 +#define CP0Ca_TI 30 +#define CP0Ca_CE 28 +#define CP0Ca_DC 27 +#define CP0Ca_PCI 26 +#define CP0Ca_IV 23 +#define CP0Ca_WP 22 +#define CP0Ca_IP 8 +#define CP0Ca_IP_mask 0x0000FF00 +#define CP0Ca_EC 2 + target_ulong CP0_EPC; + int32_t CP0_PRid; + int32_t CP0_EBase; + int32_t CP0_Config0; +#define CP0C0_M 31 +#define CP0C0_K23 28 +#define CP0C0_KU 25 +#define CP0C0_MDU 20 +#define CP0C0_MM 17 +#define CP0C0_BM 16 +#define CP0C0_BE 15 +#define CP0C0_AT 13 +#define CP0C0_AR 10 +#define CP0C0_MT 7 +#define CP0C0_VI 3 +#define CP0C0_K0 0 + int32_t CP0_Config1; +#define CP0C1_M 31 +#define CP0C1_MMU 25 +#define CP0C1_IS 22 +#define CP0C1_IL 19 +#define CP0C1_IA 16 +#define CP0C1_DS 13 +#define CP0C1_DL 10 +#define CP0C1_DA 7 +#define CP0C1_C2 6 +#define CP0C1_MD 5 +#define CP0C1_PC 4 +#define CP0C1_WR 3 +#define CP0C1_CA 2 +#define CP0C1_EP 1 +#define CP0C1_FP 0 + int32_t CP0_Config2; +#define CP0C2_M 31 +#define CP0C2_TU 28 +#define CP0C2_TS 24 +#define CP0C2_TL 20 +#define CP0C2_TA 16 +#define CP0C2_SU 12 +#define CP0C2_SS 8 +#define CP0C2_SL 4 +#define CP0C2_SA 0 + int32_t CP0_Config3; +#define CP0C3_M 31 +#define CP0C3_ISA_ON_EXC 16 +#define CP0C3_DSPP 10 +#define CP0C3_LPA 7 +#define CP0C3_VEIC 6 +#define CP0C3_VInt 5 +#define CP0C3_SP 4 +#define CP0C3_MT 2 +#define CP0C3_SM 1 +#define CP0C3_TL 0 + int32_t CP0_Config6; + int32_t CP0_Config7; + /* XXX: Maybe make LLAddr per-TC? */ + target_ulong lladdr; + target_ulong llval; + target_ulong llnewval; + target_ulong llreg; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; + target_ulong CP0_WatchLo[8]; + int32_t CP0_WatchHi[8]; + target_ulong CP0_XContext; + int32_t CP0_Framemask; + int32_t CP0_Debug; +#define CP0DB_DBD 31 +#define CP0DB_DM 30 +#define CP0DB_LSNM 28 +#define CP0DB_Doze 27 +#define CP0DB_Halt 26 +#define CP0DB_CNT 25 +#define CP0DB_IBEP 24 +#define CP0DB_DBEP 21 +#define CP0DB_IEXI 20 +#define CP0DB_VER 15 +#define CP0DB_DEC 10 +#define CP0DB_SSt 8 +#define CP0DB_DINT 5 +#define CP0DB_DIB 4 +#define CP0DB_DDBS 3 +#define CP0DB_DDBL 2 +#define CP0DB_DBp 1 +#define CP0DB_DSS 0 + target_ulong CP0_DEPC; + int32_t CP0_Performance0; + int32_t CP0_TagLo; + int32_t CP0_DataLo; + int32_t CP0_TagHi; + int32_t CP0_DataHi; + target_ulong CP0_ErrorEPC; + int32_t CP0_DESAVE; + /* We waste some space so we can handle shadow registers like TCs. */ + TCState tcs[MIPS_SHADOW_SET_MAX]; + CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; + /* Qemu */ + int error_code; + uint32_t hflags; /* CPU State */ + /* TMASK defines different execution modes */ +#define MIPS_HFLAG_TMASK 0x007FF +#define MIPS_HFLAG_MODE 0x00007 /* execution modes */ + /* The KSU flags must be the lowest bits in hflags. The flag order + must be the same as defined for CP0 Status. This allows to use + the bits as the value of mmu_idx. */ +#define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ +#define MIPS_HFLAG_UM 0x00002 /* user mode flag */ +#define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ +#define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ +#define MIPS_HFLAG_DM 0x00004 /* Debug mode */ +#define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ +#define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ +#define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ +#define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ + /* True if the MIPS IV COP1X instructions can be used. This also + controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S + and RSQRT.D. */ +#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ +#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ +#define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */ +#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ +#define MIPS_HFLAG_M16_SHIFT 10 + /* If translation is interrupted between the branch instruction and + * the delay slot, record what type of branch it is so that we can + * resume translation properly. It might be possible to reduce + * this from three bits to two. */ +#define MIPS_HFLAG_BMASK_BASE 0x03800 +#define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ +#define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ +#define MIPS_HFLAG_BL 0x01800 /* Likely branch */ +#define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ + /* Extra flags about the current pending branch. */ +#define MIPS_HFLAG_BMASK_EXT 0x3C000 +#define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ +#define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ +#define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ +#define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */ +#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) + target_ulong btarget; /* Jump / branch target */ + target_ulong bcond; /* Branch condition (if needed) */ + + int SYNCI_Step; /* Address step size for SYNCI */ + int CCRes; /* Cycle count resolution/divisor */ + uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ + uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ + int insn_flags; /* Supported instruction set */ + + target_ulong tls_value; /* For usermode emulation */ + + CPU_COMMON + + CPUMIPSMVPContext *mvp; +#if !defined(CONFIG_USER_ONLY) + CPUMIPSTLBContext *tlb; +#endif + + const mips_def_t *cpu_model; + void *irq[8]; + struct QEMUTimer *timer; /* Internal timer */ +}; + +#if !defined(CONFIG_USER_ONLY) +int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type); +int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type); +int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type); +void r4k_helper_tlbwi (void); +void r4k_helper_tlbwr (void); +void r4k_helper_tlbp (void); +void r4k_helper_tlbr (void); + +void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, + int unused, int size); +#endif + +void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); + +#define cpu_init cpu_mips_init +#define cpu_exec cpu_mips_exec +#define cpu_gen_code cpu_mips_gen_code +#define cpu_signal_handler cpu_mips_signal_handler +#define cpu_list mips_cpu_list + +#define CPU_SAVE_VERSION 3 + +/* MMU modes definitions. We carefully match the indices with our + hflags layout. */ +#define MMU_MODE0_SUFFIX _kernel +#define MMU_MODE1_SUFFIX _super +#define MMU_MODE2_SUFFIX _user +#define MMU_USER_IDX 2 +static inline int cpu_mmu_index (CPUState *env) +{ + return env->hflags & MIPS_HFLAG_KSU; +} + +static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) +{ + if (newsp) + env->active_tc.gpr[29] = newsp; + env->active_tc.gpr[7] = 0; + env->active_tc.gpr[2] = 0; +} + +static inline int cpu_mips_hw_interrupts_pending(CPUState *env) +{ + int32_t pending; + int32_t status; + int r; + + if (!(env->CP0_Status & (1 << CP0St_IE)) || + (env->CP0_Status & (1 << CP0St_EXL)) || + (env->CP0_Status & (1 << CP0St_ERL)) || + (env->hflags & MIPS_HFLAG_DM)) { + /* Interrupts are disabled */ + return 0; + } + + pending = env->CP0_Cause & CP0Ca_IP_mask; + status = env->CP0_Status & CP0Ca_IP_mask; + + if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { + /* A MIPS configured with a vectorizing external interrupt controller + will feed a vector into the Cause pending lines. The core treats + the status lines as a vector level, not as indiviual masks. */ + r = pending > status; + } else { + /* A MIPS configured with compatibility or VInt (Vectored Interrupts) + treats the pending lines as individual interrupt lines, the status + lines are individual masks. */ + r = pending & status; + } + return r; +} + +#include "cpu-all.h" + +/* Memory access type : + * may be needed for precise access rights control and precise exceptions. + */ +enum { + /* 1 bit to define user level / supervisor access */ + ACCESS_USER = 0x00, + ACCESS_SUPER = 0x01, + /* 1 bit to indicate direction */ + ACCESS_STORE = 0x02, + /* Type of instruction that generated the access */ + ACCESS_CODE = 0x10, /* Code fetch access */ + ACCESS_INT = 0x20, /* Integer load/store access */ + ACCESS_FLOAT = 0x30, /* floating point load/store access */ +}; + +/* Exceptions */ +enum { + EXCP_NONE = -1, + EXCP_RESET = 0, + EXCP_SRESET, + EXCP_DSS, + EXCP_DINT, + EXCP_DDBL, + EXCP_DDBS, + EXCP_NMI, + EXCP_MCHECK, + EXCP_EXT_INTERRUPT, /* 8 */ + EXCP_DFWATCH, + EXCP_DIB, + EXCP_IWATCH, + EXCP_AdEL, + EXCP_AdES, + EXCP_TLBF, + EXCP_IBE, + EXCP_DBp, /* 16 */ + EXCP_SYSCALL, + EXCP_BREAK, + EXCP_CpU, + EXCP_RI, + EXCP_OVERFLOW, + EXCP_TRAP, + EXCP_FPE, + EXCP_DWATCH, /* 24 */ + EXCP_LTLBL, + EXCP_TLBL, + EXCP_TLBS, + EXCP_DBE, + EXCP_THREAD, + EXCP_MDMX, + EXCP_C2E, + EXCP_CACHE, /* 32 */ + + EXCP_LAST = EXCP_CACHE, +}; +/* Dummy exception for conditional stores. */ +#define EXCP_SC 0x100 + +int cpu_mips_exec(CPUMIPSState *s); +CPUMIPSState *cpu_mips_init(const char *cpu_model); +//~ uint32_t cpu_mips_get_clock (void); +int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); + +/* mips_timer.c */ +uint32_t cpu_mips_get_random (CPUState *env); +uint32_t cpu_mips_get_count (CPUState *env); +void cpu_mips_store_count (CPUState *env, uint32_t value); +void cpu_mips_store_compare (CPUState *env, uint32_t value); +void cpu_mips_start_count(CPUState *env); +void cpu_mips_stop_count(CPUState *env); + +/* mips_int.c */ +void cpu_mips_soft_irq(CPUState *env, int irq, int level); + +/* helper.c */ +int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, + int mmu_idx, int is_softmmu); +#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault +void do_interrupt (CPUState *env); +#if !defined(CONFIG_USER_ONLY) +void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra); +target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address, + int rw); +#endif + +static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, + target_ulong *cs_base, int *flags) +{ + *pc = env->active_tc.PC; + *cs_base = 0; + *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); +} + +static inline void cpu_set_tls(CPUState *env, target_ulong newtls) +{ + env->tls_value = newtls; +} + +#endif /* !defined (__MIPS_CPU_H__) */ diff --git a/target-mips/exec.h b/target-mips/exec.h new file mode 100644 index 0000000..1273654 --- /dev/null +++ b/target-mips/exec.h @@ -0,0 +1,98 @@ +#if !defined(__QEMU_MIPS_EXEC_H__) +#define __QEMU_MIPS_EXEC_H__ + +//#define DEBUG_OP + +#include "config.h" +#include "mips-defs.h" +#include "dyngen-exec.h" +#include "cpu-defs.h" + +register struct CPUMIPSState *env asm(AREG0); + +#include "cpu.h" +#include "exec-all.h" + +#if !defined(CONFIG_USER_ONLY) +#include "softmmu_exec.h" +#endif /* !defined(CONFIG_USER_ONLY) */ + +static inline int cpu_has_work(CPUState *env) +{ + int has_work = 0; + + /* It is implementation dependent if non-enabled interrupts + wake-up the CPU, however most of the implementations only + check for interrupts that can be taken. */ + if ((env->interrupt_request & CPU_INTERRUPT_HARD) && + cpu_mips_hw_interrupts_pending(env)) { + has_work = 1; + } + + if (env->interrupt_request & CPU_INTERRUPT_TIMER) { + has_work = 1; + } + + return has_work; +} + +static inline int cpu_halted(CPUState *env) +{ + if (!env->halted) + return 0; + if (cpu_has_work(env)) { + env->halted = 0; + return 0; + } + return EXCP_HALTED; +} + +static inline void compute_hflags(CPUState *env) +{ + env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | + MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | + MIPS_HFLAG_UX); + if (!(env->CP0_Status & (1 << CP0St_EXL)) && + !(env->CP0_Status & (1 << CP0St_ERL)) && + !(env->hflags & MIPS_HFLAG_DM)) { + env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; + } +#if defined(TARGET_MIPS64) + if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || + (env->CP0_Status & (1 << CP0St_PX)) || + (env->CP0_Status & (1 << CP0St_UX))) + env->hflags |= MIPS_HFLAG_64; + if (env->CP0_Status & (1 << CP0St_UX)) + env->hflags |= MIPS_HFLAG_UX; +#endif + if ((env->CP0_Status & (1 << CP0St_CU0)) || + !(env->hflags & MIPS_HFLAG_KSU)) + env->hflags |= MIPS_HFLAG_CP0; + if (env->CP0_Status & (1 << CP0St_CU1)) + env->hflags |= MIPS_HFLAG_FPU; + if (env->CP0_Status & (1 << CP0St_FR)) + env->hflags |= MIPS_HFLAG_F64; + if (env->insn_flags & ISA_MIPS32R2) { + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) + env->hflags |= MIPS_HFLAG_COP1X; + } else if (env->insn_flags & ISA_MIPS32) { + if (env->hflags & MIPS_HFLAG_64) + env->hflags |= MIPS_HFLAG_COP1X; + } else if (env->insn_flags & ISA_MIPS4) { + /* All supported MIPS IV CPUs use the XX (CU3) to enable + and disable the MIPS IV extensions to the MIPS III ISA. + Some other MIPS IV CPUs ignore the bit, so the check here + would be too restrictive for them. */ + if (env->CP0_Status & (1 << CP0St_CU3)) + env->hflags |= MIPS_HFLAG_COP1X; + } +} + +static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) +{ + env->active_tc.PC = tb->pc; + env->hflags &= ~MIPS_HFLAG_BMASK; + env->hflags |= tb->flags & MIPS_HFLAG_BMASK; +} + +#endif /* !defined(__QEMU_MIPS_EXEC_H__) */ diff --git a/target-mips/helper.c b/target-mips/helper.c new file mode 100644 index 0000000..bdc1e53 --- /dev/null +++ b/target-mips/helper.c @@ -0,0 +1,696 @@ +/* + * MIPS emulation helpers for qemu. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include <stdarg.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <inttypes.h> +#include <signal.h> + +#include "cpu.h" +#include "exec-all.h" + +enum { + TLBRET_DIRTY = -4, + TLBRET_INVALID = -3, + TLBRET_NOMATCH = -2, + TLBRET_BADADDR = -1, + TLBRET_MATCH = 0 +}; + +#if !defined(CONFIG_USER_ONLY) + +/* no MMU emulation */ +int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type) +{ + *physical = address; + *prot = PAGE_READ | PAGE_WRITE; + return TLBRET_MATCH; +} + +/* fixed mapping MMU emulation */ +int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type) +{ + if (address <= (int32_t)0x7FFFFFFFUL) { + if (!(env->CP0_Status & (1 << CP0St_ERL))) + *physical = address + 0x40000000UL; + else + *physical = address; + } else if (address <= (int32_t)0xBFFFFFFFUL) + *physical = address & 0x1FFFFFFF; + else + *physical = address; + + *prot = PAGE_READ | PAGE_WRITE; + return TLBRET_MATCH; +} + +/* MIPS32/MIPS64 R4000-style MMU emulation */ +int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type) +{ + uint8_t ASID = env->CP0_EntryHi & 0xFF; + int i; + + for (i = 0; i < env->tlb->tlb_in_use; i++) { + r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + target_ulong tag = address & ~mask; + target_ulong VPN = tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &= env->SEGMask; +#endif + + /* Check ASID, virtual page number & size */ + if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { + /* TLB match */ + int n = !!(address & mask & ~(mask >> 1)); + /* Check access rights */ + if (!(n ? tlb->V1 : tlb->V0)) + return TLBRET_INVALID; + if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { + *physical = tlb->PFN[n] | (address & (mask >> 1)); + *prot = PAGE_READ; + if (n ? tlb->D1 : tlb->D0) + *prot |= PAGE_WRITE; + return TLBRET_MATCH; + } + return TLBRET_DIRTY; + } + } + return TLBRET_NOMATCH; +} + +static int get_physical_address (CPUState *env, target_phys_addr_t *physical, + int *prot, target_ulong address, + int rw, int access_type) +{ + /* User mode can only access useg/xuseg */ + int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; + int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; + int kernel_mode = !user_mode && !supervisor_mode; +#if defined(TARGET_MIPS64) + int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; + int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; + int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; +#endif + int ret = TLBRET_MATCH; + +#if 0 + qemu_log("user mode %d h %08x\n", user_mode, env->hflags); +#endif + + if (address <= (int32_t)0x7FFFFFFFUL) { + /* useg */ + if (env->CP0_Status & (1 << CP0St_ERL)) { + *physical = address & 0xFFFFFFFF; + *prot = PAGE_READ | PAGE_WRITE; + } else { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } +#if defined(TARGET_MIPS64) + } else if (address < 0x4000000000000000ULL) { + /* xuseg */ + if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } + } else if (address < 0x8000000000000000ULL) { + /* xsseg */ + if ((supervisor_mode || kernel_mode) && + SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } + } else if (address < 0xC000000000000000ULL) { + /* xkphys */ + if (kernel_mode && KX && + (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { + *physical = address & env->PAMask; + *prot = PAGE_READ | PAGE_WRITE; + } else { + ret = TLBRET_BADADDR; + } + } else if (address < 0xFFFFFFFF80000000ULL) { + /* xkseg */ + if (kernel_mode && KX && + address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } +#endif + } else if (address < (int32_t)0xA0000000UL) { + /* kseg0 */ + if (kernel_mode) { + *physical = address - (int32_t)0x80000000UL; + *prot = PAGE_READ | PAGE_WRITE; + } else { + ret = TLBRET_BADADDR; + } + } else if (address < (int32_t)0xC0000000UL) { + /* kseg1 */ + if (kernel_mode) { + *physical = address - (int32_t)0xA0000000UL; + *prot = PAGE_READ | PAGE_WRITE; + } else { + ret = TLBRET_BADADDR; + } + } else if (address < (int32_t)0xE0000000UL) { + /* sseg (kseg2) */ + if (supervisor_mode || kernel_mode) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } + } else { + /* kseg3 */ + /* XXX: debug segment is not emulated */ + if (kernel_mode) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } + } +#if 0 + qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n", + address, rw, access_type, *physical, *prot, ret); +#endif + + return ret; +} +#endif + +static void raise_mmu_exception(CPUState *env, target_ulong address, + int rw, int tlb_error) +{ + int exception = 0, error_code = 0; + + switch (tlb_error) { + default: + case TLBRET_BADADDR: + /* Reference to kernel address from user mode or supervisor mode */ + /* Reference to supervisor address from user mode */ + if (rw) + exception = EXCP_AdES; + else + exception = EXCP_AdEL; + break; + case TLBRET_NOMATCH: + /* No TLB match for a mapped address */ + if (rw) + exception = EXCP_TLBS; + else + exception = EXCP_TLBL; + error_code = 1; + break; + case TLBRET_INVALID: + /* TLB match with no valid bit */ + if (rw) + exception = EXCP_TLBS; + else + exception = EXCP_TLBL; + break; + case TLBRET_DIRTY: + /* TLB match but 'D' bit is cleared */ + exception = EXCP_LTLBL; + break; + + } + /* Raise exception */ + env->CP0_BadVAddr = address; + env->CP0_Context = (env->CP0_Context & ~0x007fffff) | + ((address >> 9) & 0x007ffff0); + env->CP0_EntryHi = + (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); +#if defined(TARGET_MIPS64) + env->CP0_EntryHi &= env->SEGMask; + env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | + ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | + ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); +#endif + env->exception_index = exception; + env->error_code = error_code; +} + +#if !defined(CONFIG_USER_ONLY) +target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +{ + target_phys_addr_t phys_addr; + int prot; + + if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) + return -1; + return phys_addr; +} +#endif + +int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, + int mmu_idx, int is_softmmu) +{ +#if !defined(CONFIG_USER_ONLY) + target_phys_addr_t physical; + int prot; +#endif + int access_type; + int ret = 0; + +#if 0 + log_cpu_state(env, 0); +#endif + qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", + __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu); + + rw &= 1; + + /* data access */ + /* XXX: put correct access by using cpu_restore_state() + correctly */ + access_type = ACCESS_INT; +#if defined(CONFIG_USER_ONLY) + ret = TLBRET_NOMATCH; +#else + ret = get_physical_address(env, &physical, &prot, + address, rw, access_type); + qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n", + __func__, address, ret, physical, prot); + if (ret == TLBRET_MATCH) { + tlb_set_page(env, address & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + ret = 0; + } else if (ret < 0) +#endif + { + raise_mmu_exception(env, address, rw, ret); + ret = 1; + } + + return ret; +} + +#if !defined(CONFIG_USER_ONLY) +target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw) +{ + target_phys_addr_t physical; + int prot; + int access_type; + int ret = 0; + + rw &= 1; + + /* data access */ + access_type = ACCESS_INT; + ret = get_physical_address(env, &physical, &prot, + address, rw, access_type); + if (ret != TLBRET_MATCH) { + raise_mmu_exception(env, address, rw, ret); + return -1LL; + } else { + return physical; + } +} +#endif + +static const char * const excp_names[EXCP_LAST + 1] = { + [EXCP_RESET] = "reset", + [EXCP_SRESET] = "soft reset", + [EXCP_DSS] = "debug single step", + [EXCP_DINT] = "debug interrupt", + [EXCP_NMI] = "non-maskable interrupt", + [EXCP_MCHECK] = "machine check", + [EXCP_EXT_INTERRUPT] = "interrupt", + [EXCP_DFWATCH] = "deferred watchpoint", + [EXCP_DIB] = "debug instruction breakpoint", + [EXCP_IWATCH] = "instruction fetch watchpoint", + [EXCP_AdEL] = "address error load", + [EXCP_AdES] = "address error store", + [EXCP_TLBF] = "TLB refill", + [EXCP_IBE] = "instruction bus error", + [EXCP_DBp] = "debug breakpoint", + [EXCP_SYSCALL] = "syscall", + [EXCP_BREAK] = "break", + [EXCP_CpU] = "coprocessor unusable", + [EXCP_RI] = "reserved instruction", + [EXCP_OVERFLOW] = "arithmetic overflow", + [EXCP_TRAP] = "trap", + [EXCP_FPE] = "floating point", + [EXCP_DDBS] = "debug data break store", + [EXCP_DWATCH] = "data watchpoint", + [EXCP_LTLBL] = "TLB modify", + [EXCP_TLBL] = "TLB load", + [EXCP_TLBS] = "TLB store", + [EXCP_DBE] = "data bus error", + [EXCP_DDBL] = "debug data break load", + [EXCP_THREAD] = "thread", + [EXCP_MDMX] = "MDMX", + [EXCP_C2E] = "precise coprocessor 2", + [EXCP_CACHE] = "cache error", +}; + +#if !defined(CONFIG_USER_ONLY) +static target_ulong exception_resume_pc (CPUState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode = !!(env->hflags & MIPS_HFLAG_M16); + bad_pc = env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* If the exception was raised from a delay slot, come back to + the jump. */ + bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +static void set_hflags_for_handler (CPUState *env) +{ + /* Exception handlers are entered in 32-bit mode. */ + env->hflags &= ~(MIPS_HFLAG_M16); + /* ...except that microMIPS lets you choose. */ + if (env->insn_flags & ASE_MICROMIPS) { + env->hflags |= (!!(env->CP0_Config3 + & (1 << CP0C3_ISA_ON_EXC)) + << MIPS_HFLAG_M16_SHIFT); + } +} +#endif + +void do_interrupt (CPUState *env) +{ +#if !defined(CONFIG_USER_ONLY) + target_ulong offset; + int cause = -1; + const char *name; + + if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { + if (env->exception_index < 0 || env->exception_index > EXCP_LAST) + name = "unknown"; + else + name = excp_names[env->exception_index]; + + qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", + __func__, env->active_tc.PC, env->CP0_EPC, name); + } + if (env->exception_index == EXCP_EXT_INTERRUPT && + (env->hflags & MIPS_HFLAG_DM)) + env->exception_index = EXCP_DINT; + offset = 0x180; + switch (env->exception_index) { + case EXCP_DSS: + env->CP0_Debug |= 1 << CP0DB_DSS; + /* Debug single step cannot be raised inside a delay slot and + resume will always occur on the next instruction + (but we assume the pc has always been updated during + code translation). */ + env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); + goto enter_debug_mode; + case EXCP_DINT: + env->CP0_Debug |= 1 << CP0DB_DINT; + goto set_DEPC; + case EXCP_DIB: + env->CP0_Debug |= 1 << CP0DB_DIB; + goto set_DEPC; + case EXCP_DBp: + env->CP0_Debug |= 1 << CP0DB_DBp; + goto set_DEPC; + case EXCP_DDBS: + env->CP0_Debug |= 1 << CP0DB_DDBS; + goto set_DEPC; + case EXCP_DDBL: + env->CP0_Debug |= 1 << CP0DB_DDBL; + set_DEPC: + env->CP0_DEPC = exception_resume_pc(env); + env->hflags &= ~MIPS_HFLAG_BMASK; + enter_debug_mode: + env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; + env->hflags &= ~(MIPS_HFLAG_KSU); + /* EJTAG probe trap enable is not implemented... */ + if (!(env->CP0_Status & (1 << CP0St_EXL))) + env->CP0_Cause &= ~(1 << CP0Ca_BD); + env->active_tc.PC = (int32_t)0xBFC00480; + set_hflags_for_handler(env); + break; + case EXCP_RESET: + cpu_reset(env); + break; + case EXCP_SRESET: + env->CP0_Status |= (1 << CP0St_SR); + memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); + goto set_error_EPC; + case EXCP_NMI: + env->CP0_Status |= (1 << CP0St_NMI); + set_error_EPC: + env->CP0_ErrorEPC = exception_resume_pc(env); + env->hflags &= ~MIPS_HFLAG_BMASK; + env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); + env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; + env->hflags &= ~(MIPS_HFLAG_KSU); + if (!(env->CP0_Status & (1 << CP0St_EXL))) + env->CP0_Cause &= ~(1 << CP0Ca_BD); + env->active_tc.PC = (int32_t)0xBFC00000; + set_hflags_for_handler(env); + break; + case EXCP_EXT_INTERRUPT: + cause = 0; + if (env->CP0_Cause & (1 << CP0Ca_IV)) + offset = 0x200; + + if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) { + /* Vectored Interrupts. */ + unsigned int spacing; + unsigned int vector; + unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8; + + /* Compute the Vector Spacing. */ + spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1); + spacing <<= 5; + + if (env->CP0_Config3 & (1 << CP0C3_VInt)) { + /* For VInt mode, the MIPS computes the vector internally. */ + for (vector = 0; vector < 8; vector++) { + if (pending & 1) { + /* Found it. */ + break; + } + pending >>= 1; + } + } else { + /* For VEIC mode, the external interrupt controller feeds the + vector throught the CP0Cause IP lines. */ + vector = pending; + } + offset = 0x200 + vector * spacing; + } + goto set_EPC; + case EXCP_LTLBL: + cause = 1; + goto set_EPC; + case EXCP_TLBL: + cause = 2; + if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { +#if defined(TARGET_MIPS64) + int R = env->CP0_BadVAddr >> 62; + int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; + int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; + int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; + + if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && + (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) + offset = 0x080; + else +#endif + offset = 0x000; + } + goto set_EPC; + case EXCP_TLBS: + cause = 3; + if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { +#if defined(TARGET_MIPS64) + int R = env->CP0_BadVAddr >> 62; + int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; + int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; + int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; + + if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && + (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) + offset = 0x080; + else +#endif + offset = 0x000; + } + goto set_EPC; + case EXCP_AdEL: + cause = 4; + goto set_EPC; + case EXCP_AdES: + cause = 5; + goto set_EPC; + case EXCP_IBE: + cause = 6; + goto set_EPC; + case EXCP_DBE: + cause = 7; + goto set_EPC; + case EXCP_SYSCALL: + cause = 8; + goto set_EPC; + case EXCP_BREAK: + cause = 9; + goto set_EPC; + case EXCP_RI: + cause = 10; + goto set_EPC; + case EXCP_CpU: + cause = 11; + env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | + (env->error_code << CP0Ca_CE); + goto set_EPC; + case EXCP_OVERFLOW: + cause = 12; + goto set_EPC; + case EXCP_TRAP: + cause = 13; + goto set_EPC; + case EXCP_FPE: + cause = 15; + goto set_EPC; + case EXCP_C2E: + cause = 18; + goto set_EPC; + case EXCP_MDMX: + cause = 22; + goto set_EPC; + case EXCP_DWATCH: + cause = 23; + /* XXX: TODO: manage defered watch exceptions */ + goto set_EPC; + case EXCP_MCHECK: + cause = 24; + goto set_EPC; + case EXCP_THREAD: + cause = 25; + goto set_EPC; + case EXCP_CACHE: + cause = 30; + if (env->CP0_Status & (1 << CP0St_BEV)) { + offset = 0x100; + } else { + offset = 0x20000100; + } + set_EPC: + if (!(env->CP0_Status & (1 << CP0St_EXL))) { + env->CP0_EPC = exception_resume_pc(env); + if (env->hflags & MIPS_HFLAG_BMASK) { + env->CP0_Cause |= (1 << CP0Ca_BD); + } else { + env->CP0_Cause &= ~(1 << CP0Ca_BD); + } + env->CP0_Status |= (1 << CP0St_EXL); + env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; + env->hflags &= ~(MIPS_HFLAG_KSU); + } + env->hflags &= ~MIPS_HFLAG_BMASK; + if (env->CP0_Status & (1 << CP0St_BEV)) { + env->active_tc.PC = (int32_t)0xBFC00200; + } else { + env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); + } + env->active_tc.PC += offset; + set_hflags_for_handler(env); + env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); + break; + default: + qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index); + printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); + exit(1); + } + if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { + qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" + " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", + __func__, env->active_tc.PC, env->CP0_EPC, cause, + env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, + env->CP0_DEPC); + } +#endif + env->exception_index = EXCP_NONE; +} + +#if !defined(CONFIG_USER_ONLY) +void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) +{ + r4k_tlb_t *tlb; + target_ulong addr; + target_ulong end; + uint8_t ASID = env->CP0_EntryHi & 0xFF; + target_ulong mask; + + tlb = &env->tlb->mmu.r4k.tlb[idx]; + /* The qemu TLB is flushed when the ASID changes, so no need to + flush these entries again. */ + if (tlb->G == 0 && tlb->ASID != ASID) { + return; + } + + if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { + /* For tlbwr, we can shadow the discarded entry into + a new (fake) TLB entry, as long as the guest can not + tell that it's there. */ + env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; + env->tlb->tlb_in_use++; + return; + } + + /* 1k pages are not supported. */ + mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + if (tlb->V0) { + addr = tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { + addr |= 0x3FFFFF0000000000ULL; + } +#endif + end = addr | (mask >> 1); + while (addr < end) { + tlb_flush_page (env, addr); + addr += TARGET_PAGE_SIZE; + } + } + if (tlb->V1) { + addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); +#if defined(TARGET_MIPS64) + if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { + addr |= 0x3FFFFF0000000000ULL; + } +#endif + end = addr | mask; + while (addr - 1 < end) { + tlb_flush_page (env, addr); + addr += TARGET_PAGE_SIZE; + } + } +} +#endif diff --git a/target-mips/helper.h b/target-mips/helper.h new file mode 100644 index 0000000..297ab64 --- /dev/null +++ b/target-mips/helper.h @@ -0,0 +1,290 @@ +#include "def-helper.h" + +DEF_HELPER_2(raise_exception_err, void, i32, int) +DEF_HELPER_1(raise_exception, void, i32) + +#ifdef TARGET_MIPS64 +DEF_HELPER_3(ldl, tl, tl, tl, int) +DEF_HELPER_3(ldr, tl, tl, tl, int) +DEF_HELPER_3(sdl, void, tl, tl, int) +DEF_HELPER_3(sdr, void, tl, tl, int) +#endif +DEF_HELPER_3(lwl, tl, tl, tl, int) +DEF_HELPER_3(lwr, tl, tl, tl, int) +DEF_HELPER_3(swl, void, tl, tl, int) +DEF_HELPER_3(swr, void, tl, tl, int) + +#ifndef CONFIG_USER_ONLY +DEF_HELPER_2(ll, tl, tl, int) +DEF_HELPER_3(sc, tl, tl, tl, int) +#ifdef TARGET_MIPS64 +DEF_HELPER_2(lld, tl, tl, int) +DEF_HELPER_3(scd, tl, tl, tl, int) +#endif +#endif + +DEF_HELPER_FLAGS_1(clo, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) +DEF_HELPER_FLAGS_1(clz, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) +#ifdef TARGET_MIPS64 +DEF_HELPER_FLAGS_1(dclo, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) +DEF_HELPER_FLAGS_1(dclz, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) +DEF_HELPER_2(dmult, void, tl, tl) +DEF_HELPER_2(dmultu, void, tl, tl) +#endif + +DEF_HELPER_2(muls, tl, tl, tl) +DEF_HELPER_2(mulsu, tl, tl, tl) +DEF_HELPER_2(macc, tl, tl, tl) +DEF_HELPER_2(maccu, tl, tl, tl) +DEF_HELPER_2(msac, tl, tl, tl) +DEF_HELPER_2(msacu, tl, tl, tl) +DEF_HELPER_2(mulhi, tl, tl, tl) +DEF_HELPER_2(mulhiu, tl, tl, tl) +DEF_HELPER_2(mulshi, tl, tl, tl) +DEF_HELPER_2(mulshiu, tl, tl, tl) +DEF_HELPER_2(macchi, tl, tl, tl) +DEF_HELPER_2(macchiu, tl, tl, tl) +DEF_HELPER_2(msachi, tl, tl, tl) +DEF_HELPER_2(msachiu, tl, tl, tl) + +#ifndef CONFIG_USER_ONLY +/* CP0 helpers */ +DEF_HELPER_0(mfc0_mvpcontrol, tl) +DEF_HELPER_0(mfc0_mvpconf0, tl) +DEF_HELPER_0(mfc0_mvpconf1, tl) +DEF_HELPER_0(mfc0_random, tl) +DEF_HELPER_0(mfc0_tcstatus, tl) +DEF_HELPER_0(mftc0_tcstatus, tl) +DEF_HELPER_0(mfc0_tcbind, tl) +DEF_HELPER_0(mftc0_tcbind, tl) +DEF_HELPER_0(mfc0_tcrestart, tl) +DEF_HELPER_0(mftc0_tcrestart, tl) +DEF_HELPER_0(mfc0_tchalt, tl) +DEF_HELPER_0(mftc0_tchalt, tl) +DEF_HELPER_0(mfc0_tccontext, tl) +DEF_HELPER_0(mftc0_tccontext, tl) +DEF_HELPER_0(mfc0_tcschedule, tl) +DEF_HELPER_0(mftc0_tcschedule, tl) +DEF_HELPER_0(mfc0_tcschefback, tl) +DEF_HELPER_0(mftc0_tcschefback, tl) +DEF_HELPER_0(mfc0_count, tl) +DEF_HELPER_0(mftc0_entryhi, tl) +DEF_HELPER_0(mftc0_status, tl) +DEF_HELPER_0(mfc0_lladdr, tl) +DEF_HELPER_1(mfc0_watchlo, tl, i32) +DEF_HELPER_1(mfc0_watchhi, tl, i32) +DEF_HELPER_0(mfc0_debug, tl) +DEF_HELPER_0(mftc0_debug, tl) +#ifdef TARGET_MIPS64 +DEF_HELPER_0(dmfc0_tcrestart, tl) +DEF_HELPER_0(dmfc0_tchalt, tl) +DEF_HELPER_0(dmfc0_tccontext, tl) +DEF_HELPER_0(dmfc0_tcschedule, tl) +DEF_HELPER_0(dmfc0_tcschefback, tl) +DEF_HELPER_0(dmfc0_lladdr, tl) +DEF_HELPER_1(dmfc0_watchlo, tl, i32) +#endif /* TARGET_MIPS64 */ + +DEF_HELPER_1(mtc0_index, void, tl) +DEF_HELPER_1(mtc0_mvpcontrol, void, tl) +DEF_HELPER_1(mtc0_vpecontrol, void, tl) +DEF_HELPER_1(mtc0_vpeconf0, void, tl) +DEF_HELPER_1(mtc0_vpeconf1, void, tl) +DEF_HELPER_1(mtc0_yqmask, void, tl) +DEF_HELPER_1(mtc0_vpeopt, void, tl) +DEF_HELPER_1(mtc0_entrylo0, void, tl) +DEF_HELPER_1(mtc0_tcstatus, void, tl) +DEF_HELPER_1(mttc0_tcstatus, void, tl) +DEF_HELPER_1(mtc0_tcbind, void, tl) +DEF_HELPER_1(mttc0_tcbind, void, tl) +DEF_HELPER_1(mtc0_tcrestart, void, tl) +DEF_HELPER_1(mttc0_tcrestart, void, tl) +DEF_HELPER_1(mtc0_tchalt, void, tl) +DEF_HELPER_1(mttc0_tchalt, void, tl) +DEF_HELPER_1(mtc0_tccontext, void, tl) +DEF_HELPER_1(mttc0_tccontext, void, tl) +DEF_HELPER_1(mtc0_tcschedule, void, tl) +DEF_HELPER_1(mttc0_tcschedule, void, tl) +DEF_HELPER_1(mtc0_tcschefback, void, tl) +DEF_HELPER_1(mttc0_tcschefback, void, tl) +DEF_HELPER_1(mtc0_entrylo1, void, tl) +DEF_HELPER_1(mtc0_context, void, tl) +DEF_HELPER_1(mtc0_pagemask, void, tl) +DEF_HELPER_1(mtc0_pagegrain, void, tl) +DEF_HELPER_1(mtc0_wired, void, tl) +DEF_HELPER_1(mtc0_srsconf0, void, tl) +DEF_HELPER_1(mtc0_srsconf1, void, tl) +DEF_HELPER_1(mtc0_srsconf2, void, tl) +DEF_HELPER_1(mtc0_srsconf3, void, tl) +DEF_HELPER_1(mtc0_srsconf4, void, tl) +DEF_HELPER_1(mtc0_hwrena, void, tl) +DEF_HELPER_1(mtc0_count, void, tl) +DEF_HELPER_1(mtc0_entryhi, void, tl) +DEF_HELPER_1(mttc0_entryhi, void, tl) +DEF_HELPER_1(mtc0_compare, void, tl) +DEF_HELPER_1(mtc0_status, void, tl) +DEF_HELPER_1(mttc0_status, void, tl) +DEF_HELPER_1(mtc0_intctl, void, tl) +DEF_HELPER_1(mtc0_srsctl, void, tl) +DEF_HELPER_1(mtc0_cause, void, tl) +DEF_HELPER_1(mtc0_ebase, void, tl) +DEF_HELPER_1(mtc0_config0, void, tl) +DEF_HELPER_1(mtc0_config2, void, tl) +DEF_HELPER_1(mtc0_lladdr, void, tl) +DEF_HELPER_2(mtc0_watchlo, void, tl, i32) +DEF_HELPER_2(mtc0_watchhi, void, tl, i32) +DEF_HELPER_1(mtc0_xcontext, void, tl) +DEF_HELPER_1(mtc0_framemask, void, tl) +DEF_HELPER_1(mtc0_debug, void, tl) +DEF_HELPER_1(mttc0_debug, void, tl) +DEF_HELPER_1(mtc0_performance0, void, tl) +DEF_HELPER_1(mtc0_taglo, void, tl) +DEF_HELPER_1(mtc0_datalo, void, tl) +DEF_HELPER_1(mtc0_taghi, void, tl) +DEF_HELPER_1(mtc0_datahi, void, tl) + +/* MIPS MT functions */ +DEF_HELPER_1(mftgpr, tl, i32); +DEF_HELPER_1(mftlo, tl, i32) +DEF_HELPER_1(mfthi, tl, i32) +DEF_HELPER_1(mftacx, tl, i32) +DEF_HELPER_0(mftdsp, tl) +DEF_HELPER_2(mttgpr, void, tl, i32) +DEF_HELPER_2(mttlo, void, tl, i32) +DEF_HELPER_2(mtthi, void, tl, i32) +DEF_HELPER_2(mttacx, void, tl, i32) +DEF_HELPER_1(mttdsp, void, tl) +DEF_HELPER_0(dmt, tl) +DEF_HELPER_0(emt, tl) +DEF_HELPER_0(dvpe, tl) +DEF_HELPER_0(evpe, tl) +#endif /* !CONFIG_USER_ONLY */ + +/* microMIPS functions */ +DEF_HELPER_3(lwm, void, tl, tl, i32); +DEF_HELPER_3(swm, void, tl, tl, i32); +#ifdef TARGET_MIPS64 +DEF_HELPER_3(ldm, void, tl, tl, i32); +DEF_HELPER_3(sdm, void, tl, tl, i32); +#endif + +DEF_HELPER_2(fork, void, tl, tl) +DEF_HELPER_1(yield, tl, tl) + +/* CP1 functions */ +DEF_HELPER_1(cfc1, tl, i32) +DEF_HELPER_2(ctc1, void, tl, i32) + +DEF_HELPER_1(float_cvtd_s, i64, i32) +DEF_HELPER_1(float_cvtd_w, i64, i32) +DEF_HELPER_1(float_cvtd_l, i64, i64) +DEF_HELPER_1(float_cvtl_d, i64, i64) +DEF_HELPER_1(float_cvtl_s, i64, i32) +DEF_HELPER_1(float_cvtps_pw, i64, i64) +DEF_HELPER_1(float_cvtpw_ps, i64, i64) +DEF_HELPER_1(float_cvts_d, i32, i64) +DEF_HELPER_1(float_cvts_w, i32, i32) +DEF_HELPER_1(float_cvts_l, i32, i64) +DEF_HELPER_1(float_cvts_pl, i32, i32) +DEF_HELPER_1(float_cvts_pu, i32, i32) +DEF_HELPER_1(float_cvtw_s, i32, i32) +DEF_HELPER_1(float_cvtw_d, i32, i64) + +DEF_HELPER_2(float_addr_ps, i64, i64, i64) +DEF_HELPER_2(float_mulr_ps, i64, i64, i64) + +#define FOP_PROTO(op) \ +DEF_HELPER_1(float_ ## op ## l_s, i64, i32) \ +DEF_HELPER_1(float_ ## op ## l_d, i64, i64) \ +DEF_HELPER_1(float_ ## op ## w_s, i32, i32) \ +DEF_HELPER_1(float_ ## op ## w_d, i32, i64) +FOP_PROTO(round) +FOP_PROTO(trunc) +FOP_PROTO(ceil) +FOP_PROTO(floor) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_1(float_ ## op ## _s, i32, i32) \ +DEF_HELPER_1(float_ ## op ## _d, i64, i64) +FOP_PROTO(sqrt) +FOP_PROTO(rsqrt) +FOP_PROTO(recip) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_1(float_ ## op ## _s, i32, i32) \ +DEF_HELPER_1(float_ ## op ## _d, i64, i64) \ +DEF_HELPER_1(float_ ## op ## _ps, i64, i64) +FOP_PROTO(abs) +FOP_PROTO(chs) +FOP_PROTO(recip1) +FOP_PROTO(rsqrt1) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_2(float_ ## op ## _s, i32, i32, i32) \ +DEF_HELPER_2(float_ ## op ## _d, i64, i64, i64) \ +DEF_HELPER_2(float_ ## op ## _ps, i64, i64, i64) +FOP_PROTO(add) +FOP_PROTO(sub) +FOP_PROTO(mul) +FOP_PROTO(div) +FOP_PROTO(recip2) +FOP_PROTO(rsqrt2) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_3(float_ ## op ## _s, i32, i32, i32, i32) \ +DEF_HELPER_3(float_ ## op ## _d, i64, i64, i64, i64) \ +DEF_HELPER_3(float_ ## op ## _ps, i64, i64, i64, i64) +FOP_PROTO(muladd) +FOP_PROTO(mulsub) +FOP_PROTO(nmuladd) +FOP_PROTO(nmulsub) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_3(cmp_d_ ## op, void, i64, i64, int) \ +DEF_HELPER_3(cmpabs_d_ ## op, void, i64, i64, int) \ +DEF_HELPER_3(cmp_s_ ## op, void, i32, i32, int) \ +DEF_HELPER_3(cmpabs_s_ ## op, void, i32, i32, int) \ +DEF_HELPER_3(cmp_ps_ ## op, void, i64, i64, int) \ +DEF_HELPER_3(cmpabs_ps_ ## op, void, i64, i64, int) +FOP_PROTO(f) +FOP_PROTO(un) +FOP_PROTO(eq) +FOP_PROTO(ueq) +FOP_PROTO(olt) +FOP_PROTO(ult) +FOP_PROTO(ole) +FOP_PROTO(ule) +FOP_PROTO(sf) +FOP_PROTO(ngle) +FOP_PROTO(seq) +FOP_PROTO(ngl) +FOP_PROTO(lt) +FOP_PROTO(nge) +FOP_PROTO(le) +FOP_PROTO(ngt) +#undef FOP_PROTO + +/* Special functions */ +#ifndef CONFIG_USER_ONLY +DEF_HELPER_0(tlbwi, void) +DEF_HELPER_0(tlbwr, void) +DEF_HELPER_0(tlbp, void) +DEF_HELPER_0(tlbr, void) +DEF_HELPER_0(di, tl) +DEF_HELPER_0(ei, tl) +DEF_HELPER_0(eret, void) +DEF_HELPER_0(deret, void) +#endif /* !CONFIG_USER_ONLY */ +DEF_HELPER_0(rdhwr_cpunum, tl) +DEF_HELPER_0(rdhwr_synci_step, tl) +DEF_HELPER_0(rdhwr_cc, tl) +DEF_HELPER_0(rdhwr_ccres, tl) +DEF_HELPER_1(pmon, void, int) +DEF_HELPER_0(wait, void) + +#include "def-helper.h" diff --git a/target-mips/machine.c b/target-mips/machine.c new file mode 100644 index 0000000..9ffac71 --- /dev/null +++ b/target-mips/machine.c @@ -0,0 +1,308 @@ +#include "hw/hw.h" +#include "hw/boards.h" + +#include "exec-all.h" + +static void save_tc(QEMUFile *f, TCState *tc) +{ + int i; + + /* Save active TC */ + for(i = 0; i < 32; i++) + qemu_put_betls(f, &tc->gpr[i]); + qemu_put_betls(f, &tc->PC); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_put_betls(f, &tc->HI[i]); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_put_betls(f, &tc->LO[i]); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_put_betls(f, &tc->ACX[i]); + qemu_put_betls(f, &tc->DSPControl); + qemu_put_sbe32s(f, &tc->CP0_TCStatus); + qemu_put_sbe32s(f, &tc->CP0_TCBind); + qemu_put_betls(f, &tc->CP0_TCHalt); + qemu_put_betls(f, &tc->CP0_TCContext); + qemu_put_betls(f, &tc->CP0_TCSchedule); + qemu_put_betls(f, &tc->CP0_TCScheFBack); + qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); +} + +static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) +{ + int i; + + for(i = 0; i < 32; i++) + qemu_put_be64s(f, &fpu->fpr[i].d); + qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess); + qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode); + qemu_put_s8s(f, &fpu->fp_status.float_exception_flags); + qemu_put_be32s(f, &fpu->fcr0); + qemu_put_be32s(f, &fpu->fcr31); +} + +void cpu_save(QEMUFile *f, void *opaque) +{ + CPUState *env = opaque; + int i; + + /* Save active TC */ + save_tc(f, &env->active_tc); + + /* Save active FPU */ + save_fpu(f, &env->active_fpu); + + /* Save MVP */ + qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl); + qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0); + qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1); + + /* Save TLB */ + qemu_put_be32s(f, &env->tlb->nb_tlb); + qemu_put_be32s(f, &env->tlb->tlb_in_use); + for(i = 0; i < MIPS_TLB_MAX; i++) { + uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) | + (env->tlb->mmu.r4k.tlb[i].C0 << 7) | + (env->tlb->mmu.r4k.tlb[i].C1 << 4) | + (env->tlb->mmu.r4k.tlb[i].V0 << 3) | + (env->tlb->mmu.r4k.tlb[i].V1 << 2) | + (env->tlb->mmu.r4k.tlb[i].D0 << 1) | + (env->tlb->mmu.r4k.tlb[i].D1 << 0)); + uint8_t asid; + + qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); + qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); + asid = env->tlb->mmu.r4k.tlb[i].ASID; + qemu_put_8s(f, &asid); + qemu_put_be16s(f, &flags); + qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]); + qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]); + } + + /* Save CPU metastate */ + qemu_put_be32s(f, &env->current_tc); + qemu_put_be32s(f, &env->current_fpu); + qemu_put_sbe32s(f, &env->error_code); + qemu_put_be32s(f, &env->hflags); + qemu_put_betls(f, &env->btarget); + i = env->bcond; + qemu_put_sbe32s(f, &i); + + /* Save remaining CP1 registers */ + qemu_put_sbe32s(f, &env->CP0_Index); + qemu_put_sbe32s(f, &env->CP0_Random); + qemu_put_sbe32s(f, &env->CP0_VPEControl); + qemu_put_sbe32s(f, &env->CP0_VPEConf0); + qemu_put_sbe32s(f, &env->CP0_VPEConf1); + qemu_put_betls(f, &env->CP0_YQMask); + qemu_put_betls(f, &env->CP0_VPESchedule); + qemu_put_betls(f, &env->CP0_VPEScheFBack); + qemu_put_sbe32s(f, &env->CP0_VPEOpt); + qemu_put_betls(f, &env->CP0_EntryLo0); + qemu_put_betls(f, &env->CP0_EntryLo1); + qemu_put_betls(f, &env->CP0_Context); + qemu_put_sbe32s(f, &env->CP0_PageMask); + qemu_put_sbe32s(f, &env->CP0_PageGrain); + qemu_put_sbe32s(f, &env->CP0_Wired); + qemu_put_sbe32s(f, &env->CP0_SRSConf0); + qemu_put_sbe32s(f, &env->CP0_SRSConf1); + qemu_put_sbe32s(f, &env->CP0_SRSConf2); + qemu_put_sbe32s(f, &env->CP0_SRSConf3); + qemu_put_sbe32s(f, &env->CP0_SRSConf4); + qemu_put_sbe32s(f, &env->CP0_HWREna); + qemu_put_betls(f, &env->CP0_BadVAddr); + qemu_put_sbe32s(f, &env->CP0_Count); + qemu_put_betls(f, &env->CP0_EntryHi); + qemu_put_sbe32s(f, &env->CP0_Compare); + qemu_put_sbe32s(f, &env->CP0_Status); + qemu_put_sbe32s(f, &env->CP0_IntCtl); + qemu_put_sbe32s(f, &env->CP0_SRSCtl); + qemu_put_sbe32s(f, &env->CP0_SRSMap); + qemu_put_sbe32s(f, &env->CP0_Cause); + qemu_put_betls(f, &env->CP0_EPC); + qemu_put_sbe32s(f, &env->CP0_PRid); + qemu_put_sbe32s(f, &env->CP0_EBase); + qemu_put_sbe32s(f, &env->CP0_Config0); + qemu_put_sbe32s(f, &env->CP0_Config1); + qemu_put_sbe32s(f, &env->CP0_Config2); + qemu_put_sbe32s(f, &env->CP0_Config3); + qemu_put_sbe32s(f, &env->CP0_Config6); + qemu_put_sbe32s(f, &env->CP0_Config7); + qemu_put_betls(f, &env->lladdr); + for(i = 0; i < 8; i++) + qemu_put_betls(f, &env->CP0_WatchLo[i]); + for(i = 0; i < 8; i++) + qemu_put_sbe32s(f, &env->CP0_WatchHi[i]); + qemu_put_betls(f, &env->CP0_XContext); + qemu_put_sbe32s(f, &env->CP0_Framemask); + qemu_put_sbe32s(f, &env->CP0_Debug); + qemu_put_betls(f, &env->CP0_DEPC); + qemu_put_sbe32s(f, &env->CP0_Performance0); + qemu_put_sbe32s(f, &env->CP0_TagLo); + qemu_put_sbe32s(f, &env->CP0_DataLo); + qemu_put_sbe32s(f, &env->CP0_TagHi); + qemu_put_sbe32s(f, &env->CP0_DataHi); + qemu_put_betls(f, &env->CP0_ErrorEPC); + qemu_put_sbe32s(f, &env->CP0_DESAVE); + + /* Save inactive TC state */ + for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) + save_tc(f, &env->tcs[i]); + for (i = 0; i < MIPS_FPU_MAX; i++) + save_fpu(f, &env->fpus[i]); +} + +static void load_tc(QEMUFile *f, TCState *tc) +{ + int i; + + /* Save active TC */ + for(i = 0; i < 32; i++) + qemu_get_betls(f, &tc->gpr[i]); + qemu_get_betls(f, &tc->PC); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_get_betls(f, &tc->HI[i]); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_get_betls(f, &tc->LO[i]); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_get_betls(f, &tc->ACX[i]); + qemu_get_betls(f, &tc->DSPControl); + qemu_get_sbe32s(f, &tc->CP0_TCStatus); + qemu_get_sbe32s(f, &tc->CP0_TCBind); + qemu_get_betls(f, &tc->CP0_TCHalt); + qemu_get_betls(f, &tc->CP0_TCContext); + qemu_get_betls(f, &tc->CP0_TCSchedule); + qemu_get_betls(f, &tc->CP0_TCScheFBack); + qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); +} + +static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) +{ + int i; + + for(i = 0; i < 32; i++) + qemu_get_be64s(f, &fpu->fpr[i].d); + qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess); + qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode); + qemu_get_s8s(f, &fpu->fp_status.float_exception_flags); + qemu_get_be32s(f, &fpu->fcr0); + qemu_get_be32s(f, &fpu->fcr31); +} + +int cpu_load(QEMUFile *f, void *opaque, int version_id) +{ + CPUState *env = opaque; + int i; + + if (version_id != 3) + return -EINVAL; + + /* Load active TC */ + load_tc(f, &env->active_tc); + + /* Load active FPU */ + load_fpu(f, &env->active_fpu); + + /* Load MVP */ + qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl); + qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0); + qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1); + + /* Load TLB */ + qemu_get_be32s(f, &env->tlb->nb_tlb); + qemu_get_be32s(f, &env->tlb->tlb_in_use); + for(i = 0; i < MIPS_TLB_MAX; i++) { + uint16_t flags; + uint8_t asid; + + qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); + qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); + qemu_get_8s(f, &asid); + env->tlb->mmu.r4k.tlb[i].ASID = asid; + qemu_get_be16s(f, &flags); + env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1; + env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3; + env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3; + env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1; + env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1; + env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1; + env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1; + qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]); + qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]); + } + + /* Load CPU metastate */ + qemu_get_be32s(f, &env->current_tc); + qemu_get_be32s(f, &env->current_fpu); + qemu_get_sbe32s(f, &env->error_code); + qemu_get_be32s(f, &env->hflags); + qemu_get_betls(f, &env->btarget); + qemu_get_sbe32s(f, &i); + env->bcond = i; + + /* Load remaining CP1 registers */ + qemu_get_sbe32s(f, &env->CP0_Index); + qemu_get_sbe32s(f, &env->CP0_Random); + qemu_get_sbe32s(f, &env->CP0_VPEControl); + qemu_get_sbe32s(f, &env->CP0_VPEConf0); + qemu_get_sbe32s(f, &env->CP0_VPEConf1); + qemu_get_betls(f, &env->CP0_YQMask); + qemu_get_betls(f, &env->CP0_VPESchedule); + qemu_get_betls(f, &env->CP0_VPEScheFBack); + qemu_get_sbe32s(f, &env->CP0_VPEOpt); + qemu_get_betls(f, &env->CP0_EntryLo0); + qemu_get_betls(f, &env->CP0_EntryLo1); + qemu_get_betls(f, &env->CP0_Context); + qemu_get_sbe32s(f, &env->CP0_PageMask); + qemu_get_sbe32s(f, &env->CP0_PageGrain); + qemu_get_sbe32s(f, &env->CP0_Wired); + qemu_get_sbe32s(f, &env->CP0_SRSConf0); + qemu_get_sbe32s(f, &env->CP0_SRSConf1); + qemu_get_sbe32s(f, &env->CP0_SRSConf2); + qemu_get_sbe32s(f, &env->CP0_SRSConf3); + qemu_get_sbe32s(f, &env->CP0_SRSConf4); + qemu_get_sbe32s(f, &env->CP0_HWREna); + qemu_get_betls(f, &env->CP0_BadVAddr); + qemu_get_sbe32s(f, &env->CP0_Count); + qemu_get_betls(f, &env->CP0_EntryHi); + qemu_get_sbe32s(f, &env->CP0_Compare); + qemu_get_sbe32s(f, &env->CP0_Status); + qemu_get_sbe32s(f, &env->CP0_IntCtl); + qemu_get_sbe32s(f, &env->CP0_SRSCtl); + qemu_get_sbe32s(f, &env->CP0_SRSMap); + qemu_get_sbe32s(f, &env->CP0_Cause); + qemu_get_betls(f, &env->CP0_EPC); + qemu_get_sbe32s(f, &env->CP0_PRid); + qemu_get_sbe32s(f, &env->CP0_EBase); + qemu_get_sbe32s(f, &env->CP0_Config0); + qemu_get_sbe32s(f, &env->CP0_Config1); + qemu_get_sbe32s(f, &env->CP0_Config2); + qemu_get_sbe32s(f, &env->CP0_Config3); + qemu_get_sbe32s(f, &env->CP0_Config6); + qemu_get_sbe32s(f, &env->CP0_Config7); + qemu_get_betls(f, &env->lladdr); + for(i = 0; i < 8; i++) + qemu_get_betls(f, &env->CP0_WatchLo[i]); + for(i = 0; i < 8; i++) + qemu_get_sbe32s(f, &env->CP0_WatchHi[i]); + qemu_get_betls(f, &env->CP0_XContext); + qemu_get_sbe32s(f, &env->CP0_Framemask); + qemu_get_sbe32s(f, &env->CP0_Debug); + qemu_get_betls(f, &env->CP0_DEPC); + qemu_get_sbe32s(f, &env->CP0_Performance0); + qemu_get_sbe32s(f, &env->CP0_TagLo); + qemu_get_sbe32s(f, &env->CP0_DataLo); + qemu_get_sbe32s(f, &env->CP0_TagHi); + qemu_get_sbe32s(f, &env->CP0_DataHi); + qemu_get_betls(f, &env->CP0_ErrorEPC); + qemu_get_sbe32s(f, &env->CP0_DESAVE); + + /* Load inactive TC state */ + for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) + load_tc(f, &env->tcs[i]); + for (i = 0; i < MIPS_FPU_MAX; i++) + load_fpu(f, &env->fpus[i]); + + /* XXX: ensure compatiblity for halted bit ? */ + tlb_flush(env, 1); + return 0; +} diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h new file mode 100644 index 0000000..bf094a3 --- /dev/null +++ b/target-mips/mips-defs.h @@ -0,0 +1,72 @@ +#if !defined (__QEMU_MIPS_DEFS_H__) +#define __QEMU_MIPS_DEFS_H__ + +/* If we want to use host float regs... */ +//#define USE_HOST_FLOAT_REGS + +/* Real pages are variable size... */ +#define TARGET_PAGE_BITS 12 +#define MIPS_TLB_MAX 128 + +#if defined(TARGET_MIPS64) +#define TARGET_LONG_BITS 64 +#define TARGET_PHYS_ADDR_SPACE_BITS 36 +#define TARGET_VIRT_ADDR_SPACE_BITS 42 +#else +#define TARGET_LONG_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 36 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif + +/* Masks used to mark instructions to indicate which ISA level they + were introduced in. */ +#define ISA_MIPS1 0x00000001 +#define ISA_MIPS2 0x00000002 +#define ISA_MIPS3 0x00000004 +#define ISA_MIPS4 0x00000008 +#define ISA_MIPS5 0x00000010 +#define ISA_MIPS32 0x00000020 +#define ISA_MIPS32R2 0x00000040 +#define ISA_MIPS64 0x00000080 +#define ISA_MIPS64R2 0x00000100 + +/* MIPS ASEs. */ +#define ASE_MIPS16 0x00001000 +#define ASE_MIPS3D 0x00002000 +#define ASE_MDMX 0x00004000 +#define ASE_DSP 0x00008000 +#define ASE_DSPR2 0x00010000 +#define ASE_MT 0x00020000 +#define ASE_SMARTMIPS 0x00040000 +#define ASE_MICROMIPS 0x00080000 + +/* Chip specific instructions. */ +#define INSN_LOONGSON2E 0x20000000 +#define INSN_LOONGSON2F 0x40000000 +#define INSN_VR54XX 0x80000000 + +/* MIPS CPU defines. */ +#define CPU_MIPS1 (ISA_MIPS1) +#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) +#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) +#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) +#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) +#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) + +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) + +/* MIPS Technologies "Release 1" */ +#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) + +/* MIPS Technologies "Release 2" */ +#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) + +/* Strictly follow the architecture standard: + - Disallow "special" instruction handling for PMON/SPIM. + Note that we still maintain Count/Compare to match the host clock. */ +//#define MIPS_STRICT_STANDARD 1 + +#endif /* !defined (__QEMU_MIPS_DEFS_H__) */ diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c new file mode 100644 index 0000000..669faf1 --- /dev/null +++ b/target-mips/op_helper.c @@ -0,0 +1,3044 @@ +/* + * MIPS emulation helpers for qemu. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include <stdlib.h> +#include "exec.h" + +#include "host-utils.h" + +#include "helper.h" + +#ifndef CONFIG_USER_ONLY +static inline void cpu_mips_tlb_flush (CPUState *env, int flush_global); +#endif + +/*****************************************************************************/ +/* Exceptions processing helpers */ + +void helper_raise_exception_err (uint32_t exception, int error_code) +{ +#if 1 + if (exception < 0x100) + qemu_log("%s: %d %d\n", __func__, exception, error_code); +#endif + env->exception_index = exception; + env->error_code = error_code; + cpu_loop_exit(); +} + +void helper_raise_exception (uint32_t exception) +{ + helper_raise_exception_err(exception, 0); +} + +#if !defined(CONFIG_USER_ONLY) +static void do_restore_state (void *pc_ptr) +{ + TranslationBlock *tb; + unsigned long pc = (unsigned long) pc_ptr; + + tb = tb_find_pc (pc); + if (tb) { + cpu_restore_state (tb, env, pc, NULL); + } +} +#endif + +#if defined(CONFIG_USER_ONLY) +#define HELPER_LD(name, insn, type) \ +static inline type do_##name(target_ulong addr, int mem_idx) \ +{ \ + return (type) insn##_raw(addr); \ +} +#else +#define HELPER_LD(name, insn, type) \ +static inline type do_##name(target_ulong addr, int mem_idx) \ +{ \ + switch (mem_idx) \ + { \ + case 0: return (type) insn##_kernel(addr); break; \ + case 1: return (type) insn##_super(addr); break; \ + default: \ + case 2: return (type) insn##_user(addr); break; \ + } \ +} +#endif +HELPER_LD(lbu, ldub, uint8_t) +HELPER_LD(lw, ldl, int32_t) +#ifdef TARGET_MIPS64 +HELPER_LD(ld, ldq, int64_t) +#endif +#undef HELPER_LD + +#if defined(CONFIG_USER_ONLY) +#define HELPER_ST(name, insn, type) \ +static inline void do_##name(target_ulong addr, type val, int mem_idx) \ +{ \ + insn##_raw(addr, val); \ +} +#else +#define HELPER_ST(name, insn, type) \ +static inline void do_##name(target_ulong addr, type val, int mem_idx) \ +{ \ + switch (mem_idx) \ + { \ + case 0: insn##_kernel(addr, val); break; \ + case 1: insn##_super(addr, val); break; \ + default: \ + case 2: insn##_user(addr, val); break; \ + } \ +} +#endif +HELPER_ST(sb, stb, uint8_t) +HELPER_ST(sw, stl, uint32_t) +#ifdef TARGET_MIPS64 +HELPER_ST(sd, stq, uint64_t) +#endif +#undef HELPER_ST + +target_ulong helper_clo (target_ulong arg1) +{ + return clo32(arg1); +} + +target_ulong helper_clz (target_ulong arg1) +{ + return clz32(arg1); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_dclo (target_ulong arg1) +{ + return clo64(arg1); +} + +target_ulong helper_dclz (target_ulong arg1) +{ + return clz64(arg1); +} +#endif /* TARGET_MIPS64 */ + +/* 64 bits arithmetic for 32 bits hosts */ +static inline uint64_t get_HILO (void) +{ + return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; +} + +static inline void set_HILO (uint64_t HILO) +{ + env->active_tc.LO[0] = (int32_t)HILO; + env->active_tc.HI[0] = (int32_t)(HILO >> 32); +} + +static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO) +{ + env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); + arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32); +} + +static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO) +{ + arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); + env->active_tc.HI[0] = (int32_t)(HILO >> 32); +} + +/* Multiplication variants of the vr54xx. */ +target_ulong helper_muls (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_macc (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_macchi (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_maccu (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_msac (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_msachi (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_msacu (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); + + return arg1; +} + +target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); + + return arg1; +} + +target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +#ifdef TARGET_MIPS64 +void helper_dmult (target_ulong arg1, target_ulong arg2) +{ + muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); +} + +void helper_dmultu (target_ulong arg1, target_ulong arg2) +{ + mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); +} +#endif + +#ifndef CONFIG_USER_ONLY + +static inline target_phys_addr_t do_translate_address(target_ulong address, int rw) +{ + target_phys_addr_t lladdr; + + lladdr = cpu_mips_translate_address(env, address, rw); + + if (lladdr == -1LL) { + cpu_loop_exit(); + } else { + return lladdr; + } +} + +#define HELPER_LD_ATOMIC(name, insn) \ +target_ulong helper_##name(target_ulong arg, int mem_idx) \ +{ \ + env->lladdr = do_translate_address(arg, 0); \ + env->llval = do_##insn(arg, mem_idx); \ + return env->llval; \ +} +HELPER_LD_ATOMIC(ll, lw) +#ifdef TARGET_MIPS64 +HELPER_LD_ATOMIC(lld, ld) +#endif +#undef HELPER_LD_ATOMIC + +#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ +target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \ +{ \ + target_long tmp; \ + \ + if (arg2 & almask) { \ + env->CP0_BadVAddr = arg2; \ + helper_raise_exception(EXCP_AdES); \ + } \ + if (do_translate_address(arg2, 1) == env->lladdr) { \ + tmp = do_##ld_insn(arg2, mem_idx); \ + if (tmp == env->llval) { \ + do_##st_insn(arg2, arg1, mem_idx); \ + return 1; \ + } \ + } \ + return 0; \ +} +HELPER_ST_ATOMIC(sc, lw, sw, 0x3) +#ifdef TARGET_MIPS64 +HELPER_ST_ATOMIC(scd, ld, sd, 0x7) +#endif +#undef HELPER_ST_ATOMIC +#endif + +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK(v) ((v) & 3) +#define GET_OFFSET(addr, offset) (addr + (offset)) +#else +#define GET_LMASK(v) (((v) & 3) ^ 3) +#define GET_OFFSET(addr, offset) (addr - (offset)) +#endif + +target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + target_ulong tmp; + + tmp = do_lbu(arg2, mem_idx); + arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); + + if (GET_LMASK(arg2) <= 2) { + tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); + arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); + } + + if (GET_LMASK(arg2) <= 1) { + tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); + arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); + } + + if (GET_LMASK(arg2) == 0) { + tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); + arg1 = (arg1 & 0xFFFFFF00) | tmp; + } + return (int32_t)arg1; +} + +target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + target_ulong tmp; + + tmp = do_lbu(arg2, mem_idx); + arg1 = (arg1 & 0xFFFFFF00) | tmp; + + if (GET_LMASK(arg2) >= 1) { + tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); + arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); + } + + if (GET_LMASK(arg2) >= 2) { + tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); + arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); + } + + if (GET_LMASK(arg2) == 3) { + tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); + arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); + } + return (int32_t)arg1; +} + +void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx); + + if (GET_LMASK(arg2) <= 2) + do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); + + if (GET_LMASK(arg2) <= 1) + do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); + + if (GET_LMASK(arg2) == 0) + do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); +} + +void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + do_sb(arg2, (uint8_t)arg1, mem_idx); + + if (GET_LMASK(arg2) >= 1) + do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + + if (GET_LMASK(arg2) >= 2) + do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + + if (GET_LMASK(arg2) == 3) + do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); +} + +#if defined(TARGET_MIPS64) +/* "half" load and stores. We must do the memory access inline, + or fault handling won't work. */ + +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK64(v) ((v) & 7) +#else +#define GET_LMASK64(v) (((v) & 7) ^ 7) +#endif + +target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + uint64_t tmp; + + tmp = do_lbu(arg2, mem_idx); + arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); + + if (GET_LMASK64(arg2) <= 6) { + tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); + arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); + } + + if (GET_LMASK64(arg2) <= 5) { + tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); + arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); + } + + if (GET_LMASK64(arg2) <= 4) { + tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); + arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); + } + + if (GET_LMASK64(arg2) <= 3) { + tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx); + arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); + } + + if (GET_LMASK64(arg2) <= 2) { + tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); + } + + if (GET_LMASK64(arg2) <= 1) { + tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); + } + + if (GET_LMASK64(arg2) == 0) { + tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; + } + + return arg1; +} + +target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + uint64_t tmp; + + tmp = do_lbu(arg2, mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; + + if (GET_LMASK64(arg2) >= 1) { + tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); + } + + if (GET_LMASK64(arg2) >= 2) { + tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); + } + + if (GET_LMASK64(arg2) >= 3) { + tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); + arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); + } + + if (GET_LMASK64(arg2) >= 4) { + tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx); + arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); + } + + if (GET_LMASK64(arg2) >= 5) { + tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx); + arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); + } + + if (GET_LMASK64(arg2) >= 6) { + tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx); + arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); + } + + if (GET_LMASK64(arg2) == 7) { + tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx); + arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); + } + + return arg1; +} + +void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx); + + if (GET_LMASK64(arg2) <= 6) + do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); + + if (GET_LMASK64(arg2) <= 5) + do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); + + if (GET_LMASK64(arg2) <= 4) + do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); + + if (GET_LMASK64(arg2) <= 3) + do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); + + if (GET_LMASK64(arg2) <= 2) + do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); + + if (GET_LMASK64(arg2) <= 1) + do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); + + if (GET_LMASK64(arg2) <= 0) + do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); +} + +void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + do_sb(arg2, (uint8_t)arg1, mem_idx); + + if (GET_LMASK64(arg2) >= 1) + do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + + if (GET_LMASK64(arg2) >= 2) + do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + + if (GET_LMASK64(arg2) >= 3) + do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); + + if (GET_LMASK64(arg2) >= 4) + do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); + + if (GET_LMASK64(arg2) >= 5) + do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); + + if (GET_LMASK64(arg2) >= 6) + do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); + + if (GET_LMASK64(arg2) == 7) + do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); +} +#endif /* TARGET_MIPS64 */ + +static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; + +void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +{ + target_ulong base_reglist = reglist & 0xf; + target_ulong do_r31 = reglist & 0x10; +#ifdef CONFIG_USER_ONLY +#undef ldfun +#define ldfun ldl_raw +#else + uint32_t (*ldfun)(target_ulong); + + switch (mem_idx) + { + case 0: ldfun = ldl_kernel; break; + case 1: ldfun = ldl_super; break; + default: + case 2: ldfun = ldl_user; break; + } +#endif + + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { + target_ulong i; + + for (i = 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] = (target_long) ldfun(addr); + addr += 4; + } + } + + if (do_r31) { + env->active_tc.gpr[31] = (target_long) ldfun(addr); + } +} + +void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +{ + target_ulong base_reglist = reglist & 0xf; + target_ulong do_r31 = reglist & 0x10; +#ifdef CONFIG_USER_ONLY +#undef stfun +#define stfun stl_raw +#else + void (*stfun)(target_ulong, uint32_t); + + switch (mem_idx) + { + case 0: stfun = stl_kernel; break; + case 1: stfun = stl_super; break; + default: + case 2: stfun = stl_user; break; + } +#endif + + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { + target_ulong i; + + for (i = 0; i < base_reglist; i++) { + stfun(addr, env->active_tc.gpr[multiple_regs[i]]); + addr += 4; + } + } + + if (do_r31) { + stfun(addr, env->active_tc.gpr[31]); + } +} + +#if defined(TARGET_MIPS64) +void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +{ + target_ulong base_reglist = reglist & 0xf; + target_ulong do_r31 = reglist & 0x10; +#ifdef CONFIG_USER_ONLY +#undef ldfun +#define ldfun ldq_raw +#else + uint64_t (*ldfun)(target_ulong); + + switch (mem_idx) + { + case 0: ldfun = ldq_kernel; break; + case 1: ldfun = ldq_super; break; + default: + case 2: ldfun = ldq_user; break; + } +#endif + + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { + target_ulong i; + + for (i = 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] = ldfun(addr); + addr += 8; + } + } + + if (do_r31) { + env->active_tc.gpr[31] = ldfun(addr); + } +} + +void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +{ + target_ulong base_reglist = reglist & 0xf; + target_ulong do_r31 = reglist & 0x10; +#ifdef CONFIG_USER_ONLY +#undef stfun +#define stfun stq_raw +#else + void (*stfun)(target_ulong, uint64_t); + + switch (mem_idx) + { + case 0: stfun = stq_kernel; break; + case 1: stfun = stq_super; break; + default: + case 2: stfun = stq_user; break; + } +#endif + + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { + target_ulong i; + + for (i = 0; i < base_reglist; i++) { + stfun(addr, env->active_tc.gpr[multiple_regs[i]]); + addr += 8; + } + } + + if (do_r31) { + stfun(addr, env->active_tc.gpr[31]); + } +} +#endif + +#ifndef CONFIG_USER_ONLY +/* CP0 helpers */ +target_ulong helper_mfc0_mvpcontrol (void) +{ + return env->mvp->CP0_MVPControl; +} + +target_ulong helper_mfc0_mvpconf0 (void) +{ + return env->mvp->CP0_MVPConf0; +} + +target_ulong helper_mfc0_mvpconf1 (void) +{ + return env->mvp->CP0_MVPConf1; +} + +target_ulong helper_mfc0_random (void) +{ + return (int32_t)cpu_mips_get_random(env); +} + +target_ulong helper_mfc0_tcstatus (void) +{ + return env->active_tc.CP0_TCStatus; +} + +target_ulong helper_mftc0_tcstatus(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCStatus; + else + return env->tcs[other_tc].CP0_TCStatus; +} + +target_ulong helper_mfc0_tcbind (void) +{ + return env->active_tc.CP0_TCBind; +} + +target_ulong helper_mftc0_tcbind(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCBind; + else + return env->tcs[other_tc].CP0_TCBind; +} + +target_ulong helper_mfc0_tcrestart (void) +{ + return env->active_tc.PC; +} + +target_ulong helper_mftc0_tcrestart(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.PC; + else + return env->tcs[other_tc].PC; +} + +target_ulong helper_mfc0_tchalt (void) +{ + return env->active_tc.CP0_TCHalt; +} + +target_ulong helper_mftc0_tchalt(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCHalt; + else + return env->tcs[other_tc].CP0_TCHalt; +} + +target_ulong helper_mfc0_tccontext (void) +{ + return env->active_tc.CP0_TCContext; +} + +target_ulong helper_mftc0_tccontext(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCContext; + else + return env->tcs[other_tc].CP0_TCContext; +} + +target_ulong helper_mfc0_tcschedule (void) +{ + return env->active_tc.CP0_TCSchedule; +} + +target_ulong helper_mftc0_tcschedule(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCSchedule; + else + return env->tcs[other_tc].CP0_TCSchedule; +} + +target_ulong helper_mfc0_tcschefback (void) +{ + return env->active_tc.CP0_TCScheFBack; +} + +target_ulong helper_mftc0_tcschefback(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCScheFBack; + else + return env->tcs[other_tc].CP0_TCScheFBack; +} + +target_ulong helper_mfc0_count (void) +{ + return (int32_t)cpu_mips_get_count(env); +} + +target_ulong helper_mftc0_entryhi(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tcstatus; + + if (other_tc == env->current_tc) + tcstatus = env->active_tc.CP0_TCStatus; + else + tcstatus = env->tcs[other_tc].CP0_TCStatus; + + return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff); +} + +target_ulong helper_mftc0_status(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + target_ulong t0; + int32_t tcstatus; + + if (other_tc == env->current_tc) + tcstatus = env->active_tc.CP0_TCStatus; + else + tcstatus = env->tcs[other_tc].CP0_TCStatus; + + t0 = env->CP0_Status & ~0xf1000018; + t0 |= tcstatus & (0xf << CP0TCSt_TCU0); + t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX); + t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); + + return t0; +} + +target_ulong helper_mfc0_lladdr (void) +{ + return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); +} + +target_ulong helper_mfc0_watchlo (uint32_t sel) +{ + return (int32_t)env->CP0_WatchLo[sel]; +} + +target_ulong helper_mfc0_watchhi (uint32_t sel) +{ + return env->CP0_WatchHi[sel]; +} + +target_ulong helper_mfc0_debug (void) +{ + target_ulong t0 = env->CP0_Debug; + if (env->hflags & MIPS_HFLAG_DM) + t0 |= 1 << CP0DB_DM; + + return t0; +} + +target_ulong helper_mftc0_debug(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tcstatus; + + if (other_tc == env->current_tc) + tcstatus = env->active_tc.CP0_Debug_tcstatus; + else + tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus; + + /* XXX: Might be wrong, check with EJTAG spec. */ + return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | + (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_dmfc0_tcrestart (void) +{ + return env->active_tc.PC; +} + +target_ulong helper_dmfc0_tchalt (void) +{ + return env->active_tc.CP0_TCHalt; +} + +target_ulong helper_dmfc0_tccontext (void) +{ + return env->active_tc.CP0_TCContext; +} + +target_ulong helper_dmfc0_tcschedule (void) +{ + return env->active_tc.CP0_TCSchedule; +} + +target_ulong helper_dmfc0_tcschefback (void) +{ + return env->active_tc.CP0_TCScheFBack; +} + +target_ulong helper_dmfc0_lladdr (void) +{ + return env->lladdr >> env->CP0_LLAddr_shift; +} + +target_ulong helper_dmfc0_watchlo (uint32_t sel) +{ + return env->CP0_WatchLo[sel]; +} +#endif /* TARGET_MIPS64 */ + +void helper_mtc0_index (target_ulong arg1) +{ + int num = 1; + unsigned int tmp = env->tlb->nb_tlb; + + do { + tmp >>= 1; + num <<= 1; + } while (tmp); + env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); +} + +void helper_mtc0_mvpcontrol (target_ulong arg1) +{ + uint32_t mask = 0; + uint32_t newval; + + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) + mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | + (1 << CP0MVPCo_EVP); + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (1 << CP0MVPCo_STLB); + newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); + + // TODO: Enable/disable shared TLB, enable/disable VPEs. + + env->mvp->CP0_MVPControl = newval; +} + +void helper_mtc0_vpecontrol (target_ulong arg1) +{ + uint32_t mask; + uint32_t newval; + + mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | + (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); + newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); + + /* Yield scheduler intercept not implemented. */ + /* Gating storage scheduler intercept not implemented. */ + + // TODO: Enable/disable TCs. + + env->CP0_VPEControl = newval; +} + +void helper_mtc0_vpeconf0 (target_ulong arg1) +{ + uint32_t mask = 0; + uint32_t newval; + + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) + mask |= (0xff << CP0VPEC0_XTC); + mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); + } + newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); + + // TODO: TC exclusive handling due to ERL/EXL. + + env->CP0_VPEConf0 = newval; +} + +void helper_mtc0_vpeconf1 (target_ulong arg1) +{ + uint32_t mask = 0; + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | + (0xff << CP0VPEC1_NCP1); + newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); + + /* UDI not implemented. */ + /* CP2 not implemented. */ + + // TODO: Handle FPU (CP1) binding. + + env->CP0_VPEConf1 = newval; +} + +void helper_mtc0_yqmask (target_ulong arg1) +{ + /* Yield qualifier inputs not implemented. */ + env->CP0_YQMask = 0x00000000; +} + +void helper_mtc0_vpeopt (target_ulong arg1) +{ + env->CP0_VPEOpt = arg1 & 0x0000ffff; +} + +void helper_mtc0_entrylo0 (target_ulong arg1) +{ + /* Large physaddr (PABITS) not implemented */ + /* 1k pages not implemented */ + env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF; +} + +void helper_mtc0_tcstatus (target_ulong arg1) +{ + uint32_t mask = env->CP0_TCStatus_rw_bitmask; + uint32_t newval; + + newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); + + // TODO: Sync with CP0_Status. + + env->active_tc.CP0_TCStatus = newval; +} + +void helper_mttc0_tcstatus (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + // TODO: Sync with CP0_Status. + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCStatus = arg1; + else + env->tcs[other_tc].CP0_TCStatus = arg1; +} + +void helper_mtc0_tcbind (target_ulong arg1) +{ + uint32_t mask = (1 << CP0TCBd_TBE); + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (1 << CP0TCBd_CurVPE); + newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); + env->active_tc.CP0_TCBind = newval; +} + +void helper_mttc0_tcbind (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t mask = (1 << CP0TCBd_TBE); + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (1 << CP0TCBd_CurVPE); + if (other_tc == env->current_tc) { + newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); + env->active_tc.CP0_TCBind = newval; + } else { + newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); + env->tcs[other_tc].CP0_TCBind = newval; + } +} + +void helper_mtc0_tcrestart (target_ulong arg1) +{ + env->active_tc.PC = arg1; + env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); + env->lladdr = 0ULL; + /* MIPS16 not implemented. */ +} + +void helper_mttc0_tcrestart (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) { + env->active_tc.PC = arg1; + env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); + env->lladdr = 0ULL; + /* MIPS16 not implemented. */ + } else { + env->tcs[other_tc].PC = arg1; + env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); + env->lladdr = 0ULL; + /* MIPS16 not implemented. */ + } +} + +void helper_mtc0_tchalt (target_ulong arg1) +{ + env->active_tc.CP0_TCHalt = arg1 & 0x1; + + // TODO: Halt TC / Restart (if allocated+active) TC. +} + +void helper_mttc0_tchalt (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + // TODO: Halt TC / Restart (if allocated+active) TC. + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCHalt = arg1; + else + env->tcs[other_tc].CP0_TCHalt = arg1; +} + +void helper_mtc0_tccontext (target_ulong arg1) +{ + env->active_tc.CP0_TCContext = arg1; +} + +void helper_mttc0_tccontext (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCContext = arg1; + else + env->tcs[other_tc].CP0_TCContext = arg1; +} + +void helper_mtc0_tcschedule (target_ulong arg1) +{ + env->active_tc.CP0_TCSchedule = arg1; +} + +void helper_mttc0_tcschedule (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCSchedule = arg1; + else + env->tcs[other_tc].CP0_TCSchedule = arg1; +} + +void helper_mtc0_tcschefback (target_ulong arg1) +{ + env->active_tc.CP0_TCScheFBack = arg1; +} + +void helper_mttc0_tcschefback (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCScheFBack = arg1; + else + env->tcs[other_tc].CP0_TCScheFBack = arg1; +} + +void helper_mtc0_entrylo1 (target_ulong arg1) +{ + /* Large physaddr (PABITS) not implemented */ + /* 1k pages not implemented */ + env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF; +} + +void helper_mtc0_context (target_ulong arg1) +{ + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); +} + +void helper_mtc0_pagemask (target_ulong arg1) +{ + /* 1k pages not implemented */ + env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); +} + +void helper_mtc0_pagegrain (target_ulong arg1) +{ + /* SmartMIPS not implemented */ + /* Large physaddr (PABITS) not implemented */ + /* 1k pages not implemented */ + env->CP0_PageGrain = 0; +} + +void helper_mtc0_wired (target_ulong arg1) +{ + env->CP0_Wired = arg1 % env->tlb->nb_tlb; +} + +void helper_mtc0_srsconf0 (target_ulong arg1) +{ + env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; +} + +void helper_mtc0_srsconf1 (target_ulong arg1) +{ + env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; +} + +void helper_mtc0_srsconf2 (target_ulong arg1) +{ + env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; +} + +void helper_mtc0_srsconf3 (target_ulong arg1) +{ + env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; +} + +void helper_mtc0_srsconf4 (target_ulong arg1) +{ + env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; +} + +void helper_mtc0_hwrena (target_ulong arg1) +{ + env->CP0_HWREna = arg1 & 0x0000000F; +} + +void helper_mtc0_count (target_ulong arg1) +{ + cpu_mips_store_count(env, arg1); +} + +void helper_mtc0_entryhi (target_ulong arg1) +{ + target_ulong old, val; + + /* 1k pages not implemented */ + val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF); +#if defined(TARGET_MIPS64) + val &= env->SEGMask; +#endif + old = env->CP0_EntryHi; + env->CP0_EntryHi = val; + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff; + env->active_tc.CP0_TCStatus = tcst | (val & 0xff); + } + /* If the ASID changes, flush qemu's TLB. */ + if ((old & 0xFF) != (val & 0xFF)) + cpu_mips_tlb_flush(env, 1); +} + +void helper_mttc0_entryhi(target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tcstatus; + + env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff); + if (other_tc == env->current_tc) { + tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff); + env->active_tc.CP0_TCStatus = tcstatus; + } else { + tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff); + env->tcs[other_tc].CP0_TCStatus = tcstatus; + } +} + +void helper_mtc0_compare (target_ulong arg1) +{ + cpu_mips_store_compare(env, arg1); +} + +void helper_mtc0_status (target_ulong arg1) +{ + uint32_t val, old; + uint32_t mask = env->CP0_Status_rw_bitmask; + + val = arg1 & mask; + old = env->CP0_Status; + env->CP0_Status = (env->CP0_Status & ~mask) | val; + compute_hflags(env); + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x", + old, old & env->CP0_Cause & CP0Ca_IP_mask, + val, val & env->CP0_Cause & CP0Ca_IP_mask, + env->CP0_Cause); + switch (env->hflags & MIPS_HFLAG_KSU) { + case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; + case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; + case MIPS_HFLAG_KM: qemu_log("\n"); break; + default: cpu_abort(env, "Invalid MMU mode!\n"); break; + } + } +} + +void helper_mttc0_status(target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus; + + env->CP0_Status = arg1 & ~0xf1000018; + tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0)); + tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); + tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); + if (other_tc == env->current_tc) + env->active_tc.CP0_TCStatus = tcstatus; + else + env->tcs[other_tc].CP0_TCStatus = tcstatus; +} + +void helper_mtc0_intctl (target_ulong arg1) +{ + /* vectored interrupts not implemented, no performance counters. */ + env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0); +} + +void helper_mtc0_srsctl (target_ulong arg1) +{ + uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); + env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); +} + +void helper_mtc0_cause (target_ulong arg1) +{ + uint32_t mask = 0x00C00300; + uint32_t old = env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS32R2) + mask |= 1 << CP0Ca_DC; + + env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) + cpu_mips_stop_count(env); + else + cpu_mips_start_count(env); + } + + /* Set/reset software interrupts */ + for (i = 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); + } + } +} + +void helper_mtc0_ebase (target_ulong arg1) +{ + /* vectored interrupts not implemented */ + env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); +} + +void helper_mtc0_config0 (target_ulong arg1) +{ + env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); +} + +void helper_mtc0_config2 (target_ulong arg1) +{ + /* tertiary/secondary caches not implemented */ + env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); +} + +void helper_mtc0_lladdr (target_ulong arg1) +{ + target_long mask = env->CP0_LLAddr_rw_bitmask; + arg1 = arg1 << env->CP0_LLAddr_shift; + env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); +} + +void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel) +{ + /* Watch exceptions for instructions, data loads, data stores + not implemented. */ + env->CP0_WatchLo[sel] = (arg1 & ~0x7); +} + +void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel) +{ + env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); + env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); +} + +void helper_mtc0_xcontext (target_ulong arg1) +{ + target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; + env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); +} + +void helper_mtc0_framemask (target_ulong arg1) +{ + env->CP0_Framemask = arg1; /* XXX */ +} + +void helper_mtc0_debug (target_ulong arg1) +{ + env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); + if (arg1 & (1 << CP0DB_DM)) + env->hflags |= MIPS_HFLAG_DM; + else + env->hflags &= ~MIPS_HFLAG_DM; +} + +void helper_mttc0_debug(target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); + + /* XXX: Might be wrong, check with EJTAG spec. */ + if (other_tc == env->current_tc) + env->active_tc.CP0_Debug_tcstatus = val; + else + env->tcs[other_tc].CP0_Debug_tcstatus = val; + env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | + (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); +} + +void helper_mtc0_performance0 (target_ulong arg1) +{ + env->CP0_Performance0 = arg1 & 0x000007ff; +} + +void helper_mtc0_taglo (target_ulong arg1) +{ + env->CP0_TagLo = arg1 & 0xFFFFFCF6; +} + +void helper_mtc0_datalo (target_ulong arg1) +{ + env->CP0_DataLo = arg1; /* XXX */ +} + +void helper_mtc0_taghi (target_ulong arg1) +{ + env->CP0_TagHi = arg1; /* XXX */ +} + +void helper_mtc0_datahi (target_ulong arg1) +{ + env->CP0_DataHi = arg1; /* XXX */ +} + +/* MIPS MT functions */ +target_ulong helper_mftgpr(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.gpr[sel]; + else + return env->tcs[other_tc].gpr[sel]; +} + +target_ulong helper_mftlo(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.LO[sel]; + else + return env->tcs[other_tc].LO[sel]; +} + +target_ulong helper_mfthi(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.HI[sel]; + else + return env->tcs[other_tc].HI[sel]; +} + +target_ulong helper_mftacx(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.ACX[sel]; + else + return env->tcs[other_tc].ACX[sel]; +} + +target_ulong helper_mftdsp(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.DSPControl; + else + return env->tcs[other_tc].DSPControl; +} + +void helper_mttgpr(target_ulong arg1, uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.gpr[sel] = arg1; + else + env->tcs[other_tc].gpr[sel] = arg1; +} + +void helper_mttlo(target_ulong arg1, uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.LO[sel] = arg1; + else + env->tcs[other_tc].LO[sel] = arg1; +} + +void helper_mtthi(target_ulong arg1, uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.HI[sel] = arg1; + else + env->tcs[other_tc].HI[sel] = arg1; +} + +void helper_mttacx(target_ulong arg1, uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.ACX[sel] = arg1; + else + env->tcs[other_tc].ACX[sel] = arg1; +} + +void helper_mttdsp(target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.DSPControl = arg1; + else + env->tcs[other_tc].DSPControl = arg1; +} + +/* MIPS MT functions */ +target_ulong helper_dmt(void) +{ + // TODO + return 0; +} + +target_ulong helper_emt(void) +{ + // TODO + return 0; +} + +target_ulong helper_dvpe(void) +{ + // TODO + return 0; +} + +target_ulong helper_evpe(void) +{ + // TODO + return 0; +} +#endif /* !CONFIG_USER_ONLY */ + +void helper_fork(target_ulong arg1, target_ulong arg2) +{ + // arg1 = rt, arg2 = rs + arg1 = 0; + // TODO: store to TC register +} + +target_ulong helper_yield(target_ulong arg) +{ + target_long arg1 = arg; + + if (arg1 < 0) { + /* No scheduling policy implemented. */ + if (arg1 != -2) { + if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && + env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; + helper_raise_exception(EXCP_THREAD); + } + } + } else if (arg1 == 0) { + if (0 /* TODO: TC underflow */) { + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + helper_raise_exception(EXCP_THREAD); + } else { + // TODO: Deallocate TC + } + } else if (arg1 > 0) { + /* Yield qualifier inputs not implemented. */ + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; + helper_raise_exception(EXCP_THREAD); + } + return env->CP0_YQMask; +} + +#ifndef CONFIG_USER_ONLY +/* TLB management */ +static void cpu_mips_tlb_flush (CPUState *env, int flush_global) +{ + /* Flush qemu's TLB and discard all shadowed entries. */ + tlb_flush (env, flush_global); + env->tlb->tlb_in_use = env->tlb->nb_tlb; +} + +static void r4k_mips_tlb_flush_extra (CPUState *env, int first) +{ + /* Discard entries from env->tlb[first] onwards. */ + while (env->tlb->tlb_in_use > first) { + r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); + } +} + +static void r4k_fill_tlb (int idx) +{ + r4k_tlb_t *tlb; + + /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ + tlb = &env->tlb->mmu.r4k.tlb[idx]; + tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + tlb->VPN &= env->SEGMask; +#endif + tlb->ASID = env->CP0_EntryHi & 0xFF; + tlb->PageMask = env->CP0_PageMask; + tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; + tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; + tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; + tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; + tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; + tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; + tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; + tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; +} + +void r4k_helper_tlbwi (void) +{ + int idx; + + idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + + /* Discard cached TLB entries. We could avoid doing this if the + tlbwi is just upgrading access permissions on the current entry; + that might be a further win. */ + r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); + + r4k_invalidate_tlb(env, idx, 0); + r4k_fill_tlb(idx); +} + +void r4k_helper_tlbwr (void) +{ + int r = cpu_mips_get_random(env); + + r4k_invalidate_tlb(env, r, 1); + r4k_fill_tlb(r); +} + +void r4k_helper_tlbp (void) +{ + r4k_tlb_t *tlb; + target_ulong mask; + target_ulong tag; + target_ulong VPN; + uint8_t ASID; + int i; + + ASID = env->CP0_EntryHi & 0xFF; + for (i = 0; i < env->tlb->nb_tlb; i++) { + tlb = &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag = env->CP0_EntryHi & ~mask; + VPN = tlb->VPN & ~mask; + /* Check ASID, virtual page number & size */ + if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { + /* TLB match */ + env->CP0_Index = i; + break; + } + } + if (i == env->tlb->nb_tlb) { + /* No match. Discard any shadow entries, if any of them match. */ + for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { + tlb = &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag = env->CP0_EntryHi & ~mask; + VPN = tlb->VPN & ~mask; + /* Check ASID, virtual page number & size */ + if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { + r4k_mips_tlb_flush_extra (env, i); + break; + } + } + + env->CP0_Index |= 0x80000000; + } +} + +void r4k_helper_tlbr (void) +{ + r4k_tlb_t *tlb; + uint8_t ASID; + int idx; + + ASID = env->CP0_EntryHi & 0xFF; + idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb = &env->tlb->mmu.r4k.tlb[idx]; + + /* If this will change the current ASID, flush qemu's TLB. */ + if (ASID != tlb->ASID) + cpu_mips_tlb_flush (env, 1); + + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + + env->CP0_EntryHi = tlb->VPN | tlb->ASID; + env->CP0_PageMask = tlb->PageMask; + env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | + (tlb->C0 << 3) | (tlb->PFN[0] >> 6); + env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | + (tlb->C1 << 3) | (tlb->PFN[1] >> 6); +} + +void helper_tlbwi(void) +{ + env->tlb->helper_tlbwi(); +} + +void helper_tlbwr(void) +{ + env->tlb->helper_tlbwr(); +} + +void helper_tlbp(void) +{ + env->tlb->helper_tlbp(); +} + +void helper_tlbr(void) +{ + env->tlb->helper_tlbr(); +} + +/* Specials */ +target_ulong helper_di (void) +{ + target_ulong t0 = env->CP0_Status; + + env->CP0_Status = t0 & ~(1 << CP0St_IE); + return t0; +} + +target_ulong helper_ei (void) +{ + target_ulong t0 = env->CP0_Status; + + env->CP0_Status = t0 | (1 << CP0St_IE); + return t0; +} + +static void debug_pre_eret (void) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + if (env->hflags & MIPS_HFLAG_DM) + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + qemu_log("\n"); + } +} + +static void debug_post_eret (void) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + if (env->hflags & MIPS_HFLAG_DM) + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + switch (env->hflags & MIPS_HFLAG_KSU) { + case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; + case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; + case MIPS_HFLAG_KM: qemu_log("\n"); break; + default: cpu_abort(env, "Invalid MMU mode!\n"); break; + } + } +} + +static void set_pc (target_ulong error_pc) +{ + env->active_tc.PC = error_pc & ~(target_ulong)1; + if (error_pc & 1) { + env->hflags |= MIPS_HFLAG_M16; + } else { + env->hflags &= ~(MIPS_HFLAG_M16); + } +} + +void helper_eret (void) +{ + debug_pre_eret(); + if (env->CP0_Status & (1 << CP0St_ERL)) { + set_pc(env->CP0_ErrorEPC); + env->CP0_Status &= ~(1 << CP0St_ERL); + } else { + set_pc(env->CP0_EPC); + env->CP0_Status &= ~(1 << CP0St_EXL); + } + compute_hflags(env); + debug_post_eret(); + env->lladdr = 1; +} + +void helper_deret (void) +{ + debug_pre_eret(); + set_pc(env->CP0_DEPC); + + env->hflags &= MIPS_HFLAG_DM; + compute_hflags(env); + debug_post_eret(); + env->lladdr = 1; +} +#endif /* !CONFIG_USER_ONLY */ + +target_ulong helper_rdhwr_cpunum(void) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || + (env->CP0_HWREna & (1 << 0))) + return env->CP0_EBase & 0x3ff; + else + helper_raise_exception(EXCP_RI); + + return 0; +} + +target_ulong helper_rdhwr_synci_step(void) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || + (env->CP0_HWREna & (1 << 1))) + return env->SYNCI_Step; + else + helper_raise_exception(EXCP_RI); + + return 0; +} + +target_ulong helper_rdhwr_cc(void) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || + (env->CP0_HWREna & (1 << 2))) + return env->CP0_Count; + else + helper_raise_exception(EXCP_RI); + + return 0; +} + +target_ulong helper_rdhwr_ccres(void) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || + (env->CP0_HWREna & (1 << 3))) + return env->CCRes; + else + helper_raise_exception(EXCP_RI); + + return 0; +} + +void helper_pmon (int function) +{ + function /= 2; + switch (function) { + case 2: /* TODO: char inbyte(int waitflag); */ + if (env->active_tc.gpr[4] == 0) + env->active_tc.gpr[2] = -1; + /* Fall through */ + case 11: /* TODO: char inbyte (void); */ + env->active_tc.gpr[2] = -1; + break; + case 3: + case 12: + printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); + break; + case 17: + break; + case 158: + { + unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4]; + printf("%s", fmt); + } + break; + } +} + +void helper_wait (void) +{ + env->halted = 1; + helper_raise_exception(EXCP_HLT); +} + +#if !defined(CONFIG_USER_ONLY) + +static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); + +#define MMUSUFFIX _mmu +#define ALIGNED_ONLY + +#define SHIFT 0 +#include "softmmu_template.h" + +#define SHIFT 1 +#include "softmmu_template.h" + +#define SHIFT 2 +#include "softmmu_template.h" + +#define SHIFT 3 +#include "softmmu_template.h" + +static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) +{ + env->CP0_BadVAddr = addr; + do_restore_state (retaddr); + helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); +} + +void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) +{ + TranslationBlock *tb; + CPUState *saved_env; + unsigned long pc; + int ret; + + /* XXX: hack to restore env in all cases, even if not called from + generated code */ + saved_env = env; + env = cpu_single_env; + ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); + if (ret) { + if (retaddr) { + /* now we have a real cpu fault */ + pc = (unsigned long)retaddr; + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, NULL); + } + } + helper_raise_exception_err(env->exception_index, env->error_code); + } + env = saved_env; +} + +void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, + int unused, int size) +{ + if (is_exec) + helper_raise_exception(EXCP_IBE); + else + helper_raise_exception(EXCP_DBE); +} +#endif /* !CONFIG_USER_ONLY */ + +/* Complex FPU operations which may need stack space. */ + +#define FLOAT_ONE32 make_float32(0x3f8 << 20) +#define FLOAT_ONE64 make_float64(0x3ffULL << 52) +#define FLOAT_TWO32 make_float32(1 << 30) +#define FLOAT_TWO64 make_float64(1ULL << 62) +#define FLOAT_QNAN32 0x7fbfffff +#define FLOAT_QNAN64 0x7ff7ffffffffffffULL +#define FLOAT_SNAN32 0x7fffffff +#define FLOAT_SNAN64 0x7fffffffffffffffULL + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +static unsigned int ieee_rm[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; + +#define RESTORE_ROUNDING_MODE \ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status) + +#define RESTORE_FLUSH_MODE \ + set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); + +target_ulong helper_cfc1 (uint32_t reg) +{ + target_ulong arg1; + + switch (reg) { + case 0: + arg1 = (int32_t)env->active_fpu.fcr0; + break; + case 25: + arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); + break; + case 26: + arg1 = env->active_fpu.fcr31 & 0x0003f07c; + break; + case 28: + arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); + break; + default: + arg1 = (int32_t)env->active_fpu.fcr31; + break; + } + + return arg1; +} + +void helper_ctc1 (target_ulong arg1, uint32_t reg) +{ + switch(reg) { + case 25: + if (arg1 & 0xffffff00) + return; + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | + ((arg1 & 0x1) << 23); + break; + case 26: + if (arg1 & 0x007c0000) + return; + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); + break; + case 28: + if (arg1 & 0x007c0000) + return; + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | + ((arg1 & 0x4) << 22); + break; + case 31: + if (arg1 & 0x007c0000) + return; + env->active_fpu.fcr31 = arg1; + break; + default: + return; + } + /* set rounding mode */ + RESTORE_ROUNDING_MODE; + /* set flush-to-zero mode */ + RESTORE_FLUSH_MODE; + set_float_exception_flags(0, &env->active_fpu.fp_status); + if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) + helper_raise_exception(EXCP_FPE); +} + +static inline char ieee_ex_to_mips(char xcpt) +{ + return (xcpt & float_flag_inexact) >> 5 | + (xcpt & float_flag_underflow) >> 3 | + (xcpt & float_flag_overflow) >> 1 | + (xcpt & float_flag_divbyzero) << 1 | + (xcpt & float_flag_invalid) << 4; +} + +static inline char mips_ex_to_ieee(char xcpt) +{ + return (xcpt & FP_INEXACT) << 5 | + (xcpt & FP_UNDERFLOW) << 3 | + (xcpt & FP_OVERFLOW) << 1 | + (xcpt & FP_DIV0) >> 1 | + (xcpt & FP_INVALID) >> 4; +} + +static inline void update_fcr31(void) +{ + int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); + + SET_FP_CAUSE(env->active_fpu.fcr31, tmp); + if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) + helper_raise_exception(EXCP_FPE); + else + UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); +} + +/* Float support. + Single precition routines have a "s" suffix, double precision a + "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", + paired single lower "pl", paired single upper "pu". */ + +/* unary operations, modifying fp status */ +uint64_t helper_float_sqrt_d(uint64_t fdt0) +{ + return float64_sqrt(fdt0, &env->active_fpu.fp_status); +} + +uint32_t helper_float_sqrt_s(uint32_t fst0) +{ + return float32_sqrt(fst0, &env->active_fpu.fp_status); +} + +uint64_t helper_float_cvtd_s(uint32_t fst0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint64_t helper_float_cvtd_w(uint32_t wt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint64_t helper_float_cvtd_l(uint64_t dt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint64_t helper_float_cvtl_d(uint64_t fdt0) +{ + uint64_t dt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_cvtl_s(uint32_t fst0) +{ + uint64_t dt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_cvtps_pw(uint64_t dt0) +{ + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_cvtpw_ps(uint64_t fdt0) +{ + uint32_t wt2; + uint32_t wth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FLOAT_SNAN32; + wth2 = FLOAT_SNAN32; + } + return ((uint64_t)wth2 << 32) | wt2; +} + +uint32_t helper_float_cvts_d(uint64_t fdt0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint32_t helper_float_cvts_w(uint32_t wt0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint32_t helper_float_cvts_l(uint64_t dt0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint32_t helper_float_cvts_pl(uint32_t wt0) +{ + uint32_t wt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = wt0; + update_fcr31(); + return wt2; +} + +uint32_t helper_float_cvts_pu(uint32_t wth0) +{ + uint32_t wt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = wth0; + update_fcr31(); + return wt2; +} + +uint32_t helper_float_cvtw_s(uint32_t fst0) +{ + uint32_t wt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_cvtw_d(uint64_t fdt0) +{ + uint32_t wt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint64_t helper_float_roundl_d(uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_roundl_s(uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint32_t helper_float_roundw_d(uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_roundw_s(uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint64_t helper_float_truncl_d(uint64_t fdt0) +{ + uint64_t dt2; + + dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_truncl_s(uint32_t fst0) +{ + uint64_t dt2; + + dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint32_t helper_float_truncw_d(uint64_t fdt0) +{ + uint32_t wt2; + + wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_truncw_s(uint32_t fst0) +{ + uint32_t wt2; + + wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint64_t helper_float_ceill_d(uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_ceill_s(uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint32_t helper_float_ceilw_d(uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_ceilw_s(uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint64_t helper_float_floorl_d(uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_floorl_s(uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint32_t helper_float_floorw_d(uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_floorw_s(uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +/* unary operations, not modifying fp status */ +#define FLOAT_UNOP(name) \ +uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ +{ \ + return float64_ ## name(fdt0); \ +} \ +uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ +{ \ + return float32_ ## name(fst0); \ +} \ +uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ +{ \ + uint32_t wt0; \ + uint32_t wth0; \ + \ + wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ + wth0 = float32_ ## name(fdt0 >> 32); \ + return ((uint64_t)wth0 << 32) | wt0; \ +} +FLOAT_UNOP(abs) +FLOAT_UNOP(chs) +#undef FLOAT_UNOP + +/* MIPS specific unary operations */ +uint64_t helper_float_recip_d(uint64_t fdt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_recip_s(uint32_t fst0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_rsqrt_d(uint64_t fdt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); + fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_rsqrt_s(uint32_t fst0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_recip1_d(uint64_t fdt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_recip1_s(uint32_t fst0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_recip1_ps(uint64_t fdt0) +{ + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_rsqrt1_d(uint64_t fdt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); + fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_rsqrt1_s(uint32_t fst0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_rsqrt1_ps(uint64_t fdt0) +{ + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +#define FLOAT_OP(name, p) void helper_float_##name##_##p(void) + +/* binary operations */ +#define FLOAT_BINOP(name) \ +uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \ +{ \ + uint64_t dt2; \ + \ + set_float_exception_flags(0, &env->active_fpu.fp_status); \ + dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ + update_fcr31(); \ + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ + dt2 = FLOAT_QNAN64; \ + return dt2; \ +} \ + \ +uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \ +{ \ + uint32_t wt2; \ + \ + set_float_exception_flags(0, &env->active_fpu.fp_status); \ + wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ + update_fcr31(); \ + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ + wt2 = FLOAT_QNAN32; \ + return wt2; \ +} \ + \ +uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ +{ \ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ + uint32_t fsth0 = fdt0 >> 32; \ + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ + uint32_t fsth1 = fdt1 >> 32; \ + uint32_t wt2; \ + uint32_t wth2; \ + \ + set_float_exception_flags(0, &env->active_fpu.fp_status); \ + wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ + wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ + update_fcr31(); \ + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \ + wt2 = FLOAT_QNAN32; \ + wth2 = FLOAT_QNAN32; \ + } \ + return ((uint64_t)wth2 << 32) | wt2; \ +} + +FLOAT_BINOP(add) +FLOAT_BINOP(sub) +FLOAT_BINOP(mul) +FLOAT_BINOP(div) +#undef FLOAT_BINOP + +/* ternary operations */ +#define FLOAT_TERNOP(name1, name2) \ +uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ + return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ +} \ + \ +uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ + uint32_t fst2) \ +{ \ + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ + return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ +} \ + \ +uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ + uint32_t fsth0 = fdt0 >> 32; \ + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ + uint32_t fsth1 = fdt1 >> 32; \ + uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ + uint32_t fsth2 = fdt2 >> 32; \ + \ + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ + fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ + fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ + fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ + return ((uint64_t)fsth2 << 32) | fst2; \ +} + +FLOAT_TERNOP(mul, add) +FLOAT_TERNOP(mul, sub) +#undef FLOAT_TERNOP + +/* negated ternary operations */ +#define FLOAT_NTERNOP(name1, name2) \ +uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ + fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ + return float64_chs(fdt2); \ +} \ + \ +uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ + uint32_t fst2) \ +{ \ + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ + fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ + return float32_chs(fst2); \ +} \ + \ +uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\ + uint64_t fdt2) \ +{ \ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ + uint32_t fsth0 = fdt0 >> 32; \ + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ + uint32_t fsth1 = fdt1 >> 32; \ + uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ + uint32_t fsth2 = fdt2 >> 32; \ + \ + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ + fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ + fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ + fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ + fst2 = float32_chs(fst2); \ + fsth2 = float32_chs(fsth2); \ + return ((uint64_t)fsth2 << 32) | fst2; \ +} + +FLOAT_NTERNOP(mul, add) +FLOAT_NTERNOP(mul, sub) +#undef FLOAT_NTERNOP + +/* MIPS specific binary operations */ +uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2) +{ + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); + fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2) +{ + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) +{ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fst2 = fdt2 & 0XFFFFFFFF; + uint32_t fsth2 = fdt2 >> 32; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); + fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); + fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2) +{ + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); + fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); + fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2) +{ + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) +{ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fst2 = fdt2 & 0XFFFFFFFF; + uint32_t fsth2 = fdt2 >> 32; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); + fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); + fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); + fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1) +{ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fst1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); + fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) +{ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fst1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); + fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +/* compare operations */ +#define FOP_COND_D(op, cond) \ +void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +{ \ + int c = cond; \ + update_fcr31(); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} \ +void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +{ \ + int c; \ + fdt0 = float64_abs(fdt0); \ + fdt1 = float64_abs(fdt1); \ + c = cond; \ + update_fcr31(); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} + +static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) +{ + if (float64_is_signaling_nan(a) || + float64_is_signaling_nan(b) || + (sig && (float64_is_quiet_nan(a) || float64_is_quiet_nan(b)))) { + float_raise(float_flag_invalid, status); + return 1; + } else if (float64_is_quiet_nan(a) || float64_is_quiet_nan(b)) { + return 1; + } else { + return 0; + } +} + +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0)) +FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)) +FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0)) +FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)) +FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) + +#define FOP_COND_S(op, cond) \ +void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ +{ \ + int c = cond; \ + update_fcr31(); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} \ +void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ +{ \ + int c; \ + fst0 = float32_abs(fst0); \ + fst1 = float32_abs(fst1); \ + c = cond; \ + update_fcr31(); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} + +static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM) +{ + if (float32_is_signaling_nan(a) || + float32_is_signaling_nan(b) || + (sig && (float32_is_quiet_nan(a) || float32_is_quiet_nan(b)))) { + float_raise(float_flag_invalid, status); + return 1; + } else if (float32_is_quiet_nan(a) || float32_is_quiet_nan(b)) { + return 1; + } else { + return 0; + } +} + +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0)) +FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)) +FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0)) +FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)) +FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) + +#define FOP_COND_PS(op, condl, condh) \ +void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +{ \ + uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ + uint32_t fsth0 = float32_abs(fdt0 >> 32); \ + uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ + uint32_t fsth1 = float32_abs(fdt1 >> 32); \ + int cl = condl; \ + int ch = condh; \ + \ + update_fcr31(); \ + if (cl) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ + if (ch) \ + SET_FP_COND(cc + 1, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc + 1, env->active_fpu); \ +} \ +void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +{ \ + uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ + uint32_t fsth0 = float32_abs(fdt0 >> 32); \ + uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ + uint32_t fsth1 = float32_abs(fdt1 >> 32); \ + int cl = condl; \ + int ch = condh; \ + \ + update_fcr31(); \ + if (cl) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ + if (ch) \ + SET_FP_COND(cc + 1, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc + 1, env->active_fpu); \ +} + +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0), + (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0)) +FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)) +FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0), + (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0)) +FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)) +FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) diff --git a/target-mips/translate.c b/target-mips/translate.c new file mode 100644 index 0000000..0f93e2a --- /dev/null +++ b/target-mips/translate.c @@ -0,0 +1,12746 @@ +/* + * MIPS32 emulation for qemu: main translation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +#include <stdarg.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <inttypes.h> + +#include "cpu.h" +#include "exec-all.h" +#include "disas.h" +#include "tcg-op.h" +#include "qemu-common.h" + +#include "helper.h" +#define GEN_HELPER 1 +#include "helper.h" + +//#define MIPS_DEBUG_DISAS +//#define MIPS_DEBUG_SIGN_EXTENSIONS + +/* MIPS major opcodes */ +#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) + +enum { + /* indirect opcode tables */ + OPC_SPECIAL = (0x00 << 26), + OPC_REGIMM = (0x01 << 26), + OPC_CP0 = (0x10 << 26), + OPC_CP1 = (0x11 << 26), + OPC_CP2 = (0x12 << 26), + OPC_CP3 = (0x13 << 26), + OPC_SPECIAL2 = (0x1C << 26), + OPC_SPECIAL3 = (0x1F << 26), + /* arithmetic with immediate */ + OPC_ADDI = (0x08 << 26), + OPC_ADDIU = (0x09 << 26), + OPC_SLTI = (0x0A << 26), + OPC_SLTIU = (0x0B << 26), + /* logic with immediate */ + OPC_ANDI = (0x0C << 26), + OPC_ORI = (0x0D << 26), + OPC_XORI = (0x0E << 26), + OPC_LUI = (0x0F << 26), + /* arithmetic with immediate */ + OPC_DADDI = (0x18 << 26), + OPC_DADDIU = (0x19 << 26), + /* Jump and branches */ + OPC_J = (0x02 << 26), + OPC_JAL = (0x03 << 26), + OPC_JALS = OPC_JAL | 0x5, + OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */ + OPC_BEQL = (0x14 << 26), + OPC_BNE = (0x05 << 26), + OPC_BNEL = (0x15 << 26), + OPC_BLEZ = (0x06 << 26), + OPC_BLEZL = (0x16 << 26), + OPC_BGTZ = (0x07 << 26), + OPC_BGTZL = (0x17 << 26), + OPC_JALX = (0x1D << 26), /* MIPS 16 only */ + OPC_JALXS = OPC_JALX | 0x5, + /* Load and stores */ + OPC_LDL = (0x1A << 26), + OPC_LDR = (0x1B << 26), + OPC_LB = (0x20 << 26), + OPC_LH = (0x21 << 26), + OPC_LWL = (0x22 << 26), + OPC_LW = (0x23 << 26), + OPC_LWPC = OPC_LW | 0x5, + OPC_LBU = (0x24 << 26), + OPC_LHU = (0x25 << 26), + OPC_LWR = (0x26 << 26), + OPC_LWU = (0x27 << 26), + OPC_SB = (0x28 << 26), + OPC_SH = (0x29 << 26), + OPC_SWL = (0x2A << 26), + OPC_SW = (0x2B << 26), + OPC_SDL = (0x2C << 26), + OPC_SDR = (0x2D << 26), + OPC_SWR = (0x2E << 26), + OPC_LL = (0x30 << 26), + OPC_LLD = (0x34 << 26), + OPC_LD = (0x37 << 26), + OPC_LDPC = OPC_LD | 0x5, + OPC_SC = (0x38 << 26), + OPC_SCD = (0x3C << 26), + OPC_SD = (0x3F << 26), + /* Floating point load/store */ + OPC_LWC1 = (0x31 << 26), + OPC_LWC2 = (0x32 << 26), + OPC_LDC1 = (0x35 << 26), + OPC_LDC2 = (0x36 << 26), + OPC_SWC1 = (0x39 << 26), + OPC_SWC2 = (0x3A << 26), + OPC_SDC1 = (0x3D << 26), + OPC_SDC2 = (0x3E << 26), + /* MDMX ASE specific */ + OPC_MDMX = (0x1E << 26), + /* Cache and prefetch */ + OPC_CACHE = (0x2F << 26), + OPC_PREF = (0x33 << 26), + /* Reserved major opcode */ + OPC_MAJOR3B_RESERVED = (0x3B << 26), +}; + +/* MIPS special opcodes */ +#define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F) + +enum { + /* Shifts */ + OPC_SLL = 0x00 | OPC_SPECIAL, + /* NOP is SLL r0, r0, 0 */ + /* SSNOP is SLL r0, r0, 1 */ + /* EHB is SLL r0, r0, 3 */ + OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */ + OPC_ROTR = OPC_SRL | (1 << 21), + OPC_SRA = 0x03 | OPC_SPECIAL, + OPC_SLLV = 0x04 | OPC_SPECIAL, + OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */ + OPC_ROTRV = OPC_SRLV | (1 << 6), + OPC_SRAV = 0x07 | OPC_SPECIAL, + OPC_DSLLV = 0x14 | OPC_SPECIAL, + OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */ + OPC_DROTRV = OPC_DSRLV | (1 << 6), + OPC_DSRAV = 0x17 | OPC_SPECIAL, + OPC_DSLL = 0x38 | OPC_SPECIAL, + OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */ + OPC_DROTR = OPC_DSRL | (1 << 21), + OPC_DSRA = 0x3B | OPC_SPECIAL, + OPC_DSLL32 = 0x3C | OPC_SPECIAL, + OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */ + OPC_DROTR32 = OPC_DSRL32 | (1 << 21), + OPC_DSRA32 = 0x3F | OPC_SPECIAL, + /* Multiplication / division */ + OPC_MULT = 0x18 | OPC_SPECIAL, + OPC_MULTU = 0x19 | OPC_SPECIAL, + OPC_DIV = 0x1A | OPC_SPECIAL, + OPC_DIVU = 0x1B | OPC_SPECIAL, + OPC_DMULT = 0x1C | OPC_SPECIAL, + OPC_DMULTU = 0x1D | OPC_SPECIAL, + OPC_DDIV = 0x1E | OPC_SPECIAL, + OPC_DDIVU = 0x1F | OPC_SPECIAL, + /* 2 registers arithmetic / logic */ + OPC_ADD = 0x20 | OPC_SPECIAL, + OPC_ADDU = 0x21 | OPC_SPECIAL, + OPC_SUB = 0x22 | OPC_SPECIAL, + OPC_SUBU = 0x23 | OPC_SPECIAL, + OPC_AND = 0x24 | OPC_SPECIAL, + OPC_OR = 0x25 | OPC_SPECIAL, + OPC_XOR = 0x26 | OPC_SPECIAL, + OPC_NOR = 0x27 | OPC_SPECIAL, + OPC_SLT = 0x2A | OPC_SPECIAL, + OPC_SLTU = 0x2B | OPC_SPECIAL, + OPC_DADD = 0x2C | OPC_SPECIAL, + OPC_DADDU = 0x2D | OPC_SPECIAL, + OPC_DSUB = 0x2E | OPC_SPECIAL, + OPC_DSUBU = 0x2F | OPC_SPECIAL, + /* Jumps */ + OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */ + OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */ + OPC_JALRC = OPC_JALR | (0x5 << 6), + OPC_JALRS = 0x10 | OPC_SPECIAL | (0x5 << 6), + /* Traps */ + OPC_TGE = 0x30 | OPC_SPECIAL, + OPC_TGEU = 0x31 | OPC_SPECIAL, + OPC_TLT = 0x32 | OPC_SPECIAL, + OPC_TLTU = 0x33 | OPC_SPECIAL, + OPC_TEQ = 0x34 | OPC_SPECIAL, + OPC_TNE = 0x36 | OPC_SPECIAL, + /* HI / LO registers load & stores */ + OPC_MFHI = 0x10 | OPC_SPECIAL, + OPC_MTHI = 0x11 | OPC_SPECIAL, + OPC_MFLO = 0x12 | OPC_SPECIAL, + OPC_MTLO = 0x13 | OPC_SPECIAL, + /* Conditional moves */ + OPC_MOVZ = 0x0A | OPC_SPECIAL, + OPC_MOVN = 0x0B | OPC_SPECIAL, + + OPC_MOVCI = 0x01 | OPC_SPECIAL, + + /* Special */ + OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */ + OPC_SYSCALL = 0x0C | OPC_SPECIAL, + OPC_BREAK = 0x0D | OPC_SPECIAL, + OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */ + OPC_SYNC = 0x0F | OPC_SPECIAL, + + OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL, + OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL, + OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL, + OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL, + OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL, + OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL, + OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, +}; + +/* Multiplication variants of the vr54xx. */ +#define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6)) + +enum { + OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT, + OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU, + OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT, + OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU, + OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT, + OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU, + OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT, + OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU, + OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT, + OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU, + OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT, + OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU, + OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT, + OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU, +}; + +/* REGIMM (rt field) opcodes */ +#define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16)) + +enum { + OPC_BLTZ = (0x00 << 16) | OPC_REGIMM, + OPC_BLTZL = (0x02 << 16) | OPC_REGIMM, + OPC_BGEZ = (0x01 << 16) | OPC_REGIMM, + OPC_BGEZL = (0x03 << 16) | OPC_REGIMM, + OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM, + OPC_BLTZALS = OPC_BLTZAL | 0x5, /* microMIPS */ + OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM, + OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM, + OPC_BGEZALS = OPC_BGEZAL | 0x5, /* microMIPS */ + OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM, + OPC_TGEI = (0x08 << 16) | OPC_REGIMM, + OPC_TGEIU = (0x09 << 16) | OPC_REGIMM, + OPC_TLTI = (0x0A << 16) | OPC_REGIMM, + OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, + OPC_TEQI = (0x0C << 16) | OPC_REGIMM, + OPC_TNEI = (0x0E << 16) | OPC_REGIMM, + OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, +}; + +/* Special2 opcodes */ +#define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F) + +enum { + /* Multiply & xxx operations */ + OPC_MADD = 0x00 | OPC_SPECIAL2, + OPC_MADDU = 0x01 | OPC_SPECIAL2, + OPC_MUL = 0x02 | OPC_SPECIAL2, + OPC_MSUB = 0x04 | OPC_SPECIAL2, + OPC_MSUBU = 0x05 | OPC_SPECIAL2, + /* Loongson 2F */ + OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2, + OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, + OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, + OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, + OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2, + OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2, + OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2, + OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2, + OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, + OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2, + OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2, + OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2, + /* Misc */ + OPC_CLZ = 0x20 | OPC_SPECIAL2, + OPC_CLO = 0x21 | OPC_SPECIAL2, + OPC_DCLZ = 0x24 | OPC_SPECIAL2, + OPC_DCLO = 0x25 | OPC_SPECIAL2, + /* Special */ + OPC_SDBBP = 0x3F | OPC_SPECIAL2, +}; + +/* Special3 opcodes */ +#define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F) + +enum { + OPC_EXT = 0x00 | OPC_SPECIAL3, + OPC_DEXTM = 0x01 | OPC_SPECIAL3, + OPC_DEXTU = 0x02 | OPC_SPECIAL3, + OPC_DEXT = 0x03 | OPC_SPECIAL3, + OPC_INS = 0x04 | OPC_SPECIAL3, + OPC_DINSM = 0x05 | OPC_SPECIAL3, + OPC_DINSU = 0x06 | OPC_SPECIAL3, + OPC_DINS = 0x07 | OPC_SPECIAL3, + OPC_FORK = 0x08 | OPC_SPECIAL3, + OPC_YIELD = 0x09 | OPC_SPECIAL3, + OPC_BSHFL = 0x20 | OPC_SPECIAL3, + OPC_DBSHFL = 0x24 | OPC_SPECIAL3, + OPC_RDHWR = 0x3B | OPC_SPECIAL3, + + /* Loongson 2E */ + OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3, + OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, + OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3, + OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3, + OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, + OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, + OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3, + OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3, + OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3, + OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, + OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, + OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, +}; + +/* BSHFL opcodes */ +#define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) + +enum { + OPC_WSBH = (0x02 << 6) | OPC_BSHFL, + OPC_SEB = (0x10 << 6) | OPC_BSHFL, + OPC_SEH = (0x18 << 6) | OPC_BSHFL, +}; + +/* DBSHFL opcodes */ +#define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) + +enum { + OPC_DSBH = (0x02 << 6) | OPC_DBSHFL, + OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, +}; + +/* Coprocessor 0 (rs field) */ +#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) + +enum { + OPC_MFC0 = (0x00 << 21) | OPC_CP0, + OPC_DMFC0 = (0x01 << 21) | OPC_CP0, + OPC_MTC0 = (0x04 << 21) | OPC_CP0, + OPC_DMTC0 = (0x05 << 21) | OPC_CP0, + OPC_MFTR = (0x08 << 21) | OPC_CP0, + OPC_RDPGPR = (0x0A << 21) | OPC_CP0, + OPC_MFMC0 = (0x0B << 21) | OPC_CP0, + OPC_MTTR = (0x0C << 21) | OPC_CP0, + OPC_WRPGPR = (0x0E << 21) | OPC_CP0, + OPC_C0 = (0x10 << 21) | OPC_CP0, + OPC_C0_FIRST = (0x10 << 21) | OPC_CP0, + OPC_C0_LAST = (0x1F << 21) | OPC_CP0, +}; + +/* MFMC0 opcodes */ +#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF) + +enum { + OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, + OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, + OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0, + OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0, + OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, + OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0, +}; + +/* Coprocessor 0 (with rs == C0) */ +#define MASK_C0(op) MASK_CP0(op) | (op & 0x3F) + +enum { + OPC_TLBR = 0x01 | OPC_C0, + OPC_TLBWI = 0x02 | OPC_C0, + OPC_TLBWR = 0x06 | OPC_C0, + OPC_TLBP = 0x08 | OPC_C0, + OPC_RFE = 0x10 | OPC_C0, + OPC_ERET = 0x18 | OPC_C0, + OPC_DERET = 0x1F | OPC_C0, + OPC_WAIT = 0x20 | OPC_C0, +}; + +/* Coprocessor 1 (rs field) */ +#define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) + +/* Values for the fmt field in FP instructions */ +enum { + /* 0 - 15 are reserved */ + FMT_S = 16, /* single fp */ + FMT_D = 17, /* double fp */ + FMT_E = 18, /* extended fp */ + FMT_Q = 19, /* quad fp */ + FMT_W = 20, /* 32-bit fixed */ + FMT_L = 21, /* 64-bit fixed */ + FMT_PS = 22, /* paired single fp */ + /* 23 - 31 are reserved */ +}; + +enum { + OPC_MFC1 = (0x00 << 21) | OPC_CP1, + OPC_DMFC1 = (0x01 << 21) | OPC_CP1, + OPC_CFC1 = (0x02 << 21) | OPC_CP1, + OPC_MFHC1 = (0x03 << 21) | OPC_CP1, + OPC_MTC1 = (0x04 << 21) | OPC_CP1, + OPC_DMTC1 = (0x05 << 21) | OPC_CP1, + OPC_CTC1 = (0x06 << 21) | OPC_CP1, + OPC_MTHC1 = (0x07 << 21) | OPC_CP1, + OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */ + OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1, + OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1, + OPC_S_FMT = (FMT_S << 21) | OPC_CP1, + OPC_D_FMT = (FMT_D << 21) | OPC_CP1, + OPC_E_FMT = (FMT_E << 21) | OPC_CP1, + OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1, + OPC_W_FMT = (FMT_W << 21) | OPC_CP1, + OPC_L_FMT = (FMT_L << 21) | OPC_CP1, + OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1, +}; + +#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F) +#define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16)) + +enum { + OPC_BC1F = (0x00 << 16) | OPC_BC1, + OPC_BC1T = (0x01 << 16) | OPC_BC1, + OPC_BC1FL = (0x02 << 16) | OPC_BC1, + OPC_BC1TL = (0x03 << 16) | OPC_BC1, +}; + +enum { + OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2, + OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2, +}; + +enum { + OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4, + OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4, +}; + +#define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) + +enum { + OPC_MFC2 = (0x00 << 21) | OPC_CP2, + OPC_DMFC2 = (0x01 << 21) | OPC_CP2, + OPC_CFC2 = (0x02 << 21) | OPC_CP2, + OPC_MFHC2 = (0x03 << 21) | OPC_CP2, + OPC_MTC2 = (0x04 << 21) | OPC_CP2, + OPC_DMTC2 = (0x05 << 21) | OPC_CP2, + OPC_CTC2 = (0x06 << 21) | OPC_CP2, + OPC_MTHC2 = (0x07 << 21) | OPC_CP2, + OPC_BC2 = (0x08 << 21) | OPC_CP2, +}; + +#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F) + +enum { + OPC_LWXC1 = 0x00 | OPC_CP3, + OPC_LDXC1 = 0x01 | OPC_CP3, + OPC_LUXC1 = 0x05 | OPC_CP3, + OPC_SWXC1 = 0x08 | OPC_CP3, + OPC_SDXC1 = 0x09 | OPC_CP3, + OPC_SUXC1 = 0x0D | OPC_CP3, + OPC_PREFX = 0x0F | OPC_CP3, + OPC_ALNV_PS = 0x1E | OPC_CP3, + OPC_MADD_S = 0x20 | OPC_CP3, + OPC_MADD_D = 0x21 | OPC_CP3, + OPC_MADD_PS = 0x26 | OPC_CP3, + OPC_MSUB_S = 0x28 | OPC_CP3, + OPC_MSUB_D = 0x29 | OPC_CP3, + OPC_MSUB_PS = 0x2E | OPC_CP3, + OPC_NMADD_S = 0x30 | OPC_CP3, + OPC_NMADD_D = 0x31 | OPC_CP3, + OPC_NMADD_PS= 0x36 | OPC_CP3, + OPC_NMSUB_S = 0x38 | OPC_CP3, + OPC_NMSUB_D = 0x39 | OPC_CP3, + OPC_NMSUB_PS= 0x3E | OPC_CP3, +}; + +/* global register indices */ +static TCGv_ptr cpu_env; +static TCGv cpu_gpr[32], cpu_PC; +static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC]; +static TCGv cpu_dspctrl, btarget, bcond; +static TCGv_i32 hflags; +static TCGv_i32 fpu_fcr0, fpu_fcr31; + +static uint32_t gen_opc_hflags[OPC_BUF_SIZE]; + +#include "gen-icount.h" + +#define gen_helper_0i(name, arg) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg); \ + gen_helper_##name(helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +#define gen_helper_1i(name, arg1, arg2) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ + gen_helper_##name(arg1, helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +#define gen_helper_2i(name, arg1, arg2, arg3) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ + gen_helper_##name(arg1, arg2, helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +#define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg4); \ + gen_helper_##name(arg1, arg2, arg3, helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +typedef struct DisasContext { + struct TranslationBlock *tb; + target_ulong pc, saved_pc; + uint32_t opcode; + int singlestep_enabled; + /* Routine used to access memory */ + int mem_idx; + uint32_t hflags, saved_hflags; + int bstate; + target_ulong btarget; +} DisasContext; + +enum { + BS_NONE = 0, /* We go out of the TB without reaching a branch or an + * exception condition */ + BS_STOP = 1, /* We want to stop translation for any reason */ + BS_BRANCH = 2, /* We reached a branch condition */ + BS_EXCP = 3, /* We reached an exception condition */ +}; + +static const char *regnames[] = + { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; + +static const char *regnames_HI[] = + { "HI0", "HI1", "HI2", "HI3", }; + +static const char *regnames_LO[] = + { "LO0", "LO1", "LO2", "LO3", }; + +static const char *regnames_ACX[] = + { "ACX0", "ACX1", "ACX2", "ACX3", }; + +static const char *fregnames[] = + { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; + +#ifdef MIPS_DEBUG_DISAS +#define MIPS_DEBUG(fmt, ...) \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, \ + TARGET_FMT_lx ": %08x " fmt "\n", \ + ctx->pc, ctx->opcode , ## __VA_ARGS__) +#define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) +#else +#define MIPS_DEBUG(fmt, ...) do { } while(0) +#define LOG_DISAS(...) do { } while (0) +#endif + +#define MIPS_INVAL(op) \ +do { \ + MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \ + ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \ +} while (0) + +/* General purpose registers moves. */ +static inline void gen_load_gpr (TCGv t, int reg) +{ + if (reg == 0) + tcg_gen_movi_tl(t, 0); + else + tcg_gen_mov_tl(t, cpu_gpr[reg]); +} + +static inline void gen_store_gpr (TCGv t, int reg) +{ + if (reg != 0) + tcg_gen_mov_tl(cpu_gpr[reg], t); +} + +/* Moves to/from ACX register. */ +static inline void gen_load_ACX (TCGv t, int reg) +{ + tcg_gen_mov_tl(t, cpu_ACX[reg]); +} + +static inline void gen_store_ACX (TCGv t, int reg) +{ + tcg_gen_mov_tl(cpu_ACX[reg], t); +} + +/* Moves to/from shadow registers. */ +static inline void gen_load_srsgpr (int from, int to) +{ + TCGv t0 = tcg_temp_new(); + + if (from == 0) + tcg_gen_movi_tl(t0, 0); + else { + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_ptr addr = tcg_temp_new_ptr(); + + tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); + tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); + tcg_gen_andi_i32(t2, t2, 0xf); + tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); + tcg_gen_ext_i32_ptr(addr, t2); + tcg_gen_add_ptr(addr, cpu_env, addr); + + tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); + tcg_temp_free_ptr(addr); + tcg_temp_free_i32(t2); + } + gen_store_gpr(t0, to); + tcg_temp_free(t0); +} + +static inline void gen_store_srsgpr (int from, int to) +{ + if (to != 0) { + TCGv t0 = tcg_temp_new(); + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_ptr addr = tcg_temp_new_ptr(); + + gen_load_gpr(t0, from); + tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); + tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); + tcg_gen_andi_i32(t2, t2, 0xf); + tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); + tcg_gen_ext_i32_ptr(addr, t2); + tcg_gen_add_ptr(addr, cpu_env, addr); + + tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); + tcg_temp_free_ptr(addr); + tcg_temp_free_i32(t2); + tcg_temp_free(t0); + } +} + +/* Floating point register moves. */ +static inline void gen_load_fpr32 (TCGv_i32 t, int reg) +{ + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); +} + +static inline void gen_store_fpr32 (TCGv_i32 t, int reg) +{ + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); +} + +static inline void gen_load_fpr32h (TCGv_i32 t, int reg) +{ + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); +} + +static inline void gen_store_fpr32h (TCGv_i32 t, int reg) +{ + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); +} + +static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) +{ + if (ctx->hflags & MIPS_HFLAG_F64) { + tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); + } else { + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); + gen_load_fpr32(t0, reg & ~1); + gen_load_fpr32(t1, reg | 1); + tcg_gen_concat_i32_i64(t, t0, t1); + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); + } +} + +static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) +{ + if (ctx->hflags & MIPS_HFLAG_F64) { + tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(t1, t); + gen_store_fpr32(t1, reg & ~1); + tcg_gen_shri_i64(t0, t, 32); + tcg_gen_trunc_i64_i32(t1, t0); + gen_store_fpr32(t1, reg | 1); + tcg_temp_free_i32(t1); + tcg_temp_free_i64(t0); + } +} + +static inline int get_fp_bit (int cc) +{ + if (cc) + return 24 + cc; + else + return 23; +} + +/* Tests */ +static inline void gen_save_pc(target_ulong pc) +{ + tcg_gen_movi_tl(cpu_PC, pc); +} + +static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) +{ + LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); + if (do_save_pc && ctx->pc != ctx->saved_pc) { + gen_save_pc(ctx->pc); + ctx->saved_pc = ctx->pc; + } + if (ctx->hflags != ctx->saved_hflags) { + tcg_gen_movi_i32(hflags, ctx->hflags); + ctx->saved_hflags = ctx->hflags; + switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { + case MIPS_HFLAG_BR: + break; + case MIPS_HFLAG_BC: + case MIPS_HFLAG_BL: + case MIPS_HFLAG_B: + tcg_gen_movi_tl(btarget, ctx->btarget); + break; + } + } +} + +static inline void restore_cpu_state (CPUState *env, DisasContext *ctx) +{ + ctx->saved_hflags = ctx->hflags; + switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { + case MIPS_HFLAG_BR: + break; + case MIPS_HFLAG_BC: + case MIPS_HFLAG_BL: + case MIPS_HFLAG_B: + ctx->btarget = env->btarget; + break; + } +} + +static inline void +generate_exception_err (DisasContext *ctx, int excp, int err) +{ + TCGv_i32 texcp = tcg_const_i32(excp); + TCGv_i32 terr = tcg_const_i32(err); + save_cpu_state(ctx, 1); + gen_helper_raise_exception_err(texcp, terr); + tcg_temp_free_i32(terr); + tcg_temp_free_i32(texcp); +} + +static inline void +generate_exception (DisasContext *ctx, int excp) +{ + save_cpu_state(ctx, 1); + gen_helper_0i(raise_exception, excp); +} + +/* Addresses computation */ +static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) +{ + tcg_gen_add_tl(ret, arg0, arg1); + +#if defined(TARGET_MIPS64) + /* For compatibility with 32-bit code, data reference in user mode + with Status_UX = 0 should be casted to 32-bit and sign extended. + See the MIPS64 PRA manual, section 4.10. */ + if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && + !(ctx->hflags & MIPS_HFLAG_UX)) { + tcg_gen_ext32s_i64(ret, ret); + } +#endif +} + +static inline void check_cp0_enabled(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) + generate_exception_err(ctx, EXCP_CpU, 0); +} + +static inline void check_cp1_enabled(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) + generate_exception_err(ctx, EXCP_CpU, 1); +} + +/* Verify that the processor is running with COP1X instructions enabled. + This is associated with the nabla symbol in the MIPS32 and MIPS64 + opcode tables. */ + +static inline void check_cop1x(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) + generate_exception(ctx, EXCP_RI); +} + +/* Verify that the processor is running with 64-bit floating-point + operations enabled. */ + +static inline void check_cp1_64bitmode(DisasContext *ctx) +{ + if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) + generate_exception(ctx, EXCP_RI); +} + +/* + * Verify if floating point register is valid; an operation is not defined + * if bit 0 of any register specification is set and the FR bit in the + * Status register equals zero, since the register numbers specify an + * even-odd pair of adjacent coprocessor general registers. When the FR bit + * in the Status register equals one, both even and odd register numbers + * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers. + * + * Multiple 64 bit wide registers can be checked by calling + * gen_op_cp1_registers(freg1 | freg2 | ... | fregN); + */ +static inline void check_cp1_registers(DisasContext *ctx, int regs) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) + generate_exception(ctx, EXCP_RI); +} + +/* This code generates a "reserved instruction" exception if the + CPU does not support the instruction set corresponding to flags. */ +static inline void check_insn(CPUState *env, DisasContext *ctx, int flags) +{ + if (unlikely(!(env->insn_flags & flags))) + generate_exception(ctx, EXCP_RI); +} + +/* This code generates a "reserved instruction" exception if 64-bit + instructions are not enabled. */ +static inline void check_mips_64(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) + generate_exception(ctx, EXCP_RI); +} + +/* Define small wrappers for gen_load_fpr* so that we have a uniform + calling interface for 32 and 64-bit FPRs. No sense in changing + all callers for gen_load_fpr32 when we need the CTX parameter for + this one use. */ +#define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(x, y) +#define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y) +#define FOP_CONDS(type, abs, fmt, ifmt, bits) \ +static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ + int ft, int fs, int cc) \ +{ \ + TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \ + TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \ + switch (ifmt) { \ + case FMT_PS: \ + check_cp1_64bitmode(ctx); \ + break; \ + case FMT_D: \ + if (abs) { \ + check_cop1x(ctx); \ + } \ + check_cp1_registers(ctx, fs | ft); \ + break; \ + case FMT_S: \ + if (abs) { \ + check_cop1x(ctx); \ + } \ + break; \ + } \ + gen_ldcmp_fpr##bits (ctx, fp0, fs); \ + gen_ldcmp_fpr##bits (ctx, fp1, ft); \ + switch (n) { \ + case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\ + case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\ + case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\ + case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\ + case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\ + case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\ + case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\ + case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\ + case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\ + case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\ + case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\ + case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\ + case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\ + case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\ + case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\ + case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\ + default: abort(); \ + } \ + tcg_temp_free_i##bits (fp0); \ + tcg_temp_free_i##bits (fp1); \ +} + +FOP_CONDS(, 0, d, FMT_D, 64) +FOP_CONDS(abs, 1, d, FMT_D, 64) +FOP_CONDS(, 0, s, FMT_S, 32) +FOP_CONDS(abs, 1, s, FMT_S, 32) +FOP_CONDS(, 0, ps, FMT_PS, 64) +FOP_CONDS(abs, 1, ps, FMT_PS, 64) +#undef FOP_CONDS +#undef gen_ldcmp_fpr32 +#undef gen_ldcmp_fpr64 + +/* load/store instructions. */ +#define OP_LD(insn,fname) \ +static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ +{ \ + tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ +} +OP_LD(lb,ld8s); +OP_LD(lbu,ld8u); +OP_LD(lh,ld16s); +OP_LD(lhu,ld16u); +OP_LD(lw,ld32s); +#if defined(TARGET_MIPS64) +OP_LD(lwu,ld32u); +OP_LD(ld,ld64); +#endif +#undef OP_LD + +#define OP_ST(insn,fname) \ +static inline void op_st_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \ +{ \ + tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \ +} +OP_ST(sb,st8); +OP_ST(sh,st16); +OP_ST(sw,st32); +#if defined(TARGET_MIPS64) +OP_ST(sd,st64); +#endif +#undef OP_ST + +#ifdef CONFIG_USER_ONLY +#define OP_LD_ATOMIC(insn,fname) \ +static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ +{ \ + TCGv t0 = tcg_temp_new(); \ + tcg_gen_mov_tl(t0, arg1); \ + tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \ + tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \ + tcg_temp_free(t0); \ +} +#else +#define OP_LD_ATOMIC(insn,fname) \ +static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ +{ \ + gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \ +} +#endif +OP_LD_ATOMIC(ll,ld32s); +#if defined(TARGET_MIPS64) +OP_LD_ATOMIC(lld,ld64); +#endif +#undef OP_LD_ATOMIC + +#ifdef CONFIG_USER_ONLY +#define OP_ST_ATOMIC(insn,fname,ldname,almask) \ +static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \ +{ \ + TCGv t0 = tcg_temp_new(); \ + int l1 = gen_new_label(); \ + int l2 = gen_new_label(); \ + \ + tcg_gen_andi_tl(t0, arg2, almask); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \ + tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \ + generate_exception(ctx, EXCP_AdES); \ + gen_set_label(l1); \ + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \ + tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \ + tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \ + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \ + tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \ + gen_helper_0i(raise_exception, EXCP_SC); \ + gen_set_label(l2); \ + tcg_gen_movi_tl(t0, 0); \ + gen_store_gpr(t0, rt); \ + tcg_temp_free(t0); \ +} +#else +#define OP_ST_ATOMIC(insn,fname,ldname,almask) \ +static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \ +{ \ + TCGv t0 = tcg_temp_new(); \ + gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \ + gen_store_gpr(t0, rt); \ + tcg_temp_free(t0); \ +} +#endif +OP_ST_ATOMIC(sc,st32,ld32s,0x3); +#if defined(TARGET_MIPS64) +OP_ST_ATOMIC(scd,st64,ld64,0x7); +#endif +#undef OP_ST_ATOMIC + +static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, + int base, int16_t offset) +{ + if (base == 0) { + tcg_gen_movi_tl(addr, offset); + } else if (offset == 0) { + gen_load_gpr(addr, base); + } else { + tcg_gen_movi_tl(addr, offset); + gen_op_addr_add(ctx, addr, cpu_gpr[base], addr); + } +} + +static target_ulong pc_relative_pc (DisasContext *ctx) +{ + target_ulong pc = ctx->pc; + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4; + + pc -= branch_bytes; + } + + pc &= ~(target_ulong)3; + return pc; +} + +/* Load */ +static void gen_ld (CPUState *env, DisasContext *ctx, uint32_t opc, + int rt, int base, int16_t offset) +{ + const char *opn = "ld"; + TCGv t0, t1; + + if (rt == 0 && env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) { + /* Loongson CPU uses a load to zero register for prefetch. + We emulate it as a NOP. On other CPU we must perform the + actual memory access. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_base_offset_addr(ctx, t0, base, offset); + + switch (opc) { +#if defined(TARGET_MIPS64) + case OPC_LWU: + save_cpu_state(ctx, 0); + op_ld_lwu(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lwu"; + break; + case OPC_LD: + save_cpu_state(ctx, 0); + op_ld_ld(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "ld"; + break; + case OPC_LLD: + save_cpu_state(ctx, 1); + op_ld_lld(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lld"; + break; + case OPC_LDL: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx); + gen_store_gpr(t1, rt); + opn = "ldl"; + break; + case OPC_LDR: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx); + gen_store_gpr(t1, rt); + opn = "ldr"; + break; + case OPC_LDPC: + save_cpu_state(ctx, 0); + tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); + gen_op_addr_add(ctx, t0, t0, t1); + op_ld_ld(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "ldpc"; + break; +#endif + case OPC_LWPC: + save_cpu_state(ctx, 0); + tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); + gen_op_addr_add(ctx, t0, t0, t1); + op_ld_lw(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lwpc"; + break; + case OPC_LW: + save_cpu_state(ctx, 0); + op_ld_lw(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lw"; + break; + case OPC_LH: + save_cpu_state(ctx, 0); + op_ld_lh(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lh"; + break; + case OPC_LHU: + save_cpu_state(ctx, 0); + op_ld_lhu(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lhu"; + break; + case OPC_LB: + save_cpu_state(ctx, 0); + op_ld_lb(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lb"; + break; + case OPC_LBU: + save_cpu_state(ctx, 0); + op_ld_lbu(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lbu"; + break; + case OPC_LWL: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx); + gen_store_gpr(t1, rt); + opn = "lwl"; + break; + case OPC_LWR: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx); + gen_store_gpr(t1, rt); + opn = "lwr"; + break; + case OPC_LL: + save_cpu_state(ctx, 1); + op_ld_ll(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "ll"; + break; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* Store */ +static void gen_st (DisasContext *ctx, uint32_t opc, int rt, + int base, int16_t offset) +{ + const char *opn = "st"; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_base_offset_addr(ctx, t0, base, offset); + gen_load_gpr(t1, rt); + switch (opc) { +#if defined(TARGET_MIPS64) + case OPC_SD: + save_cpu_state(ctx, 0); + op_st_sd(t1, t0, ctx); + opn = "sd"; + break; + case OPC_SDL: + save_cpu_state(ctx, 1); + gen_helper_2i(sdl, t1, t0, ctx->mem_idx); + opn = "sdl"; + break; + case OPC_SDR: + save_cpu_state(ctx, 1); + gen_helper_2i(sdr, t1, t0, ctx->mem_idx); + opn = "sdr"; + break; +#endif + case OPC_SW: + save_cpu_state(ctx, 0); + op_st_sw(t1, t0, ctx); + opn = "sw"; + break; + case OPC_SH: + save_cpu_state(ctx, 0); + op_st_sh(t1, t0, ctx); + opn = "sh"; + break; + case OPC_SB: + save_cpu_state(ctx, 0); + op_st_sb(t1, t0, ctx); + opn = "sb"; + break; + case OPC_SWL: + save_cpu_state(ctx, 1); + gen_helper_2i(swl, t1, t0, ctx->mem_idx); + opn = "swl"; + break; + case OPC_SWR: + save_cpu_state(ctx, 1); + gen_helper_2i(swr, t1, t0, ctx->mem_idx); + opn = "swr"; + break; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + + +/* Store conditional */ +static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, + int base, int16_t offset) +{ + const char *opn = "st_cond"; + TCGv t0, t1; + + t0 = tcg_temp_local_new(); + + gen_base_offset_addr(ctx, t0, base, offset); + /* Don't do NOP if destination is zero: we must perform the actual + memory access. */ + + t1 = tcg_temp_local_new(); + gen_load_gpr(t1, rt); + switch (opc) { +#if defined(TARGET_MIPS64) + case OPC_SCD: + save_cpu_state(ctx, 1); + op_st_scd(t1, t0, rt, ctx); + opn = "scd"; + break; +#endif + case OPC_SC: + save_cpu_state(ctx, 1); + op_st_sc(t1, t0, rt, ctx); + opn = "sc"; + break; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); + tcg_temp_free(t1); + tcg_temp_free(t0); +} + +/* Load and store */ +static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, + int base, int16_t offset) +{ + const char *opn = "flt_ldst"; + TCGv t0 = tcg_temp_new(); + + gen_base_offset_addr(ctx, t0, base, offset); + /* Don't do NOP if destination is zero: we must perform the actual + memory access. */ + switch (opc) { + case OPC_LWC1: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32(fp0, ft); + tcg_temp_free_i32(fp0); + } + opn = "lwc1"; + break; + case OPC_SWC1: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv t1 = tcg_temp_new(); + + gen_load_fpr32(fp0, ft); + tcg_gen_extu_i32_tl(t1, fp0); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); + tcg_temp_free(t1); + tcg_temp_free_i32(fp0); + } + opn = "swc1"; + break; + case OPC_LDC1: + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); + gen_store_fpr64(ctx, fp0, ft); + tcg_temp_free_i64(fp0); + } + opn = "ldc1"; + break; + case OPC_SDC1: + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, ft); + tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); + tcg_temp_free_i64(fp0); + } + opn = "sdc1"; + break; + default: + MIPS_INVAL(opn); + generate_exception(ctx, EXCP_RI); + goto out; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]); + out: + tcg_temp_free(t0); +} + +static void gen_cop1_ldst(CPUState *env, DisasContext *ctx, + uint32_t op, int rt, int rs, int16_t imm) +{ + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + gen_flt_ldst(ctx, op, rt, rs, imm); + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } +} + +/* Arithmetic with immediate operand */ +static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) +{ + target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ + const char *opn = "imm arith"; + + if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { + /* If no destination, treat it as a NOP. + For addi, we must generate the overflow exception when needed. */ + MIPS_DEBUG("NOP"); + return; + } + switch (opc) { + case OPC_ADDI: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + tcg_gen_addi_tl(t0, t1, uimm); + tcg_gen_ext32s_tl(t0, t0); + + tcg_gen_xori_tl(t1, t1, ~uimm); + tcg_gen_xori_tl(t2, t0, uimm); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of same sign, result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + tcg_gen_ext32s_tl(t0, t0); + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + } + opn = "addi"; + break; + case OPC_ADDIU: + if (rs != 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } else { + tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } + opn = "addiu"; + break; +#if defined(TARGET_MIPS64) + case OPC_DADDI: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + tcg_gen_addi_tl(t0, t1, uimm); + + tcg_gen_xori_tl(t1, t1, ~uimm); + tcg_gen_xori_tl(t2, t0, uimm); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of same sign, result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + } + opn = "daddi"; + break; + case OPC_DADDIU: + if (rs != 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + } else { + tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } + opn = "daddiu"; + break; +#endif + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); +} + +/* Logic with immediate operand */ +static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm) +{ + target_ulong uimm; + const char *opn = "imm logic"; + + if (rt == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + uimm = (uint16_t)imm; + switch (opc) { + case OPC_ANDI: + if (likely(rs != 0)) + tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + else + tcg_gen_movi_tl(cpu_gpr[rt], 0); + opn = "andi"; + break; + case OPC_ORI: + if (rs != 0) + tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + else + tcg_gen_movi_tl(cpu_gpr[rt], uimm); + opn = "ori"; + break; + case OPC_XORI: + if (likely(rs != 0)) + tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + else + tcg_gen_movi_tl(cpu_gpr[rt], uimm); + opn = "xori"; + break; + case OPC_LUI: + tcg_gen_movi_tl(cpu_gpr[rt], imm << 16); + opn = "lui"; + break; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); +} + +/* Set on less than with immediate operand */ +static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm) +{ + target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ + const char *opn = "imm arith"; + TCGv t0; + + if (rt == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + t0 = tcg_temp_new(); + gen_load_gpr(t0, rs); + switch (opc) { + case OPC_SLTI: + tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm); + opn = "slti"; + break; + case OPC_SLTIU: + tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm); + opn = "sltiu"; + break; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); + tcg_temp_free(t0); +} + +/* Shifts with immediate operand */ +static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) +{ + target_ulong uimm = ((uint16_t)imm) & 0x1f; + const char *opn = "imm shift"; + TCGv t0; + + if (rt == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + gen_load_gpr(t0, rs); + switch (opc) { + case OPC_SLL: + tcg_gen_shli_tl(t0, t0, uimm); + tcg_gen_ext32s_tl(cpu_gpr[rt], t0); + opn = "sll"; + break; + case OPC_SRA: + tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); + opn = "sra"; + break; + case OPC_SRL: + if (uimm != 0) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); + } else { + tcg_gen_ext32s_tl(cpu_gpr[rt], t0); + } + opn = "srl"; + break; + case OPC_ROTR: + if (uimm != 0) { + TCGv_i32 t1 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t1, t0); + tcg_gen_rotri_i32(t1, t1, uimm); + tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); + tcg_temp_free_i32(t1); + } else { + tcg_gen_ext32s_tl(cpu_gpr[rt], t0); + } + opn = "rotr"; + break; +#if defined(TARGET_MIPS64) + case OPC_DSLL: + tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm); + opn = "dsll"; + break; + case OPC_DSRA: + tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); + opn = "dsra"; + break; + case OPC_DSRL: + tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); + opn = "dsrl"; + break; + case OPC_DROTR: + if (uimm != 0) { + tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm); + } else { + tcg_gen_mov_tl(cpu_gpr[rt], t0); + } + opn = "drotr"; + break; + case OPC_DSLL32: + tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32); + opn = "dsll32"; + break; + case OPC_DSRA32: + tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32); + opn = "dsra32"; + break; + case OPC_DSRL32: + tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); + opn = "dsrl32"; + break; + case OPC_DROTR32: + tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32); + opn = "drotr32"; + break; +#endif + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); + tcg_temp_free(t0); +} + +/* Arithmetic */ +static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + const char *opn = "arith"; + + if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB + && opc != OPC_DADD && opc != OPC_DSUB) { + /* If no destination, treat it as a NOP. + For add & sub, we must generate the overflow exception when needed. */ + MIPS_DEBUG("NOP"); + return; + } + + switch (opc) { + case OPC_ADD: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_add_tl(t0, t1, t2); + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_xor_tl(t1, t1, t2); + tcg_gen_xor_tl(t2, t0, t2); + tcg_gen_andc_tl(t1, t2, t1); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of same sign, result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + opn = "add"; + break; + case OPC_ADDU: + if (rs != 0 && rt != 0) { + tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } else if (rs == 0 && rt != 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "addu"; + break; + case OPC_SUB: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_sub_tl(t0, t1, t2); + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_xor_tl(t2, t1, t2); + tcg_gen_xor_tl(t1, t0, t1); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of different sign, first operand and result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + opn = "sub"; + break; + case OPC_SUBU: + if (rs != 0 && rt != 0) { + tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } else if (rs == 0 && rt != 0) { + tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "subu"; + break; +#if defined(TARGET_MIPS64) + case OPC_DADD: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_add_tl(t0, t1, t2); + tcg_gen_xor_tl(t1, t1, t2); + tcg_gen_xor_tl(t2, t0, t2); + tcg_gen_andc_tl(t1, t2, t1); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of same sign, result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + opn = "dadd"; + break; + case OPC_DADDU: + if (rs != 0 && rt != 0) { + tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "daddu"; + break; + case OPC_DSUB: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_sub_tl(t0, t1, t2); + tcg_gen_xor_tl(t2, t1, t2); + tcg_gen_xor_tl(t1, t0, t1); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of different sign, first operand and result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + opn = "dsub"; + break; + case OPC_DSUBU: + if (rs != 0 && rt != 0) { + tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "dsubu"; + break; +#endif + case OPC_MUL: + if (likely(rs != 0 && rt != 0)) { + tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "mul"; + break; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); +} + +/* Conditional move */ +static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt) +{ + const char *opn = "cond move"; + int l1; + + if (rd == 0) { + /* If no destination, treat it as a NOP. + For add & sub, we must generate the overflow exception when needed. */ + MIPS_DEBUG("NOP"); + return; + } + + l1 = gen_new_label(); + switch (opc) { + case OPC_MOVN: + if (likely(rt != 0)) + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rt], 0, l1); + else + tcg_gen_br(l1); + opn = "movn"; + break; + case OPC_MOVZ: + if (likely(rt != 0)) + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rt], 0, l1); + opn = "movz"; + break; + } + if (rs != 0) + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + else + tcg_gen_movi_tl(cpu_gpr[rd], 0); + gen_set_label(l1); + + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); +} + +/* Logic */ +static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt) +{ + const char *opn = "logic"; + + if (rd == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + switch (opc) { + case OPC_AND: + if (likely(rs != 0 && rt != 0)) { + tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "and"; + break; + case OPC_NOR: + if (rs != 0 && rt != 0) { + tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0)); + } + opn = "nor"; + break; + case OPC_OR: + if (likely(rs != 0 && rt != 0)) { + tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "or"; + break; + case OPC_XOR: + if (likely(rs != 0 && rt != 0)) { + tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "xor"; + break; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); +} + +/* Set on lower than */ +static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt) +{ + const char *opn = "slt"; + TCGv t0, t1; + + if (rd == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + switch (opc) { + case OPC_SLT: + tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1); + opn = "slt"; + break; + case OPC_SLTU: + tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1); + opn = "sltu"; + break; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* Shifts */ +static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + const char *opn = "shifts"; + TCGv t0, t1; + + if (rd == 0) { + /* If no destination, treat it as a NOP. + For add & sub, we must generate the overflow exception when needed. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + switch (opc) { + case OPC_SLLV: + tcg_gen_andi_tl(t0, t0, 0x1f); + tcg_gen_shl_tl(t0, t1, t0); + tcg_gen_ext32s_tl(cpu_gpr[rd], t0); + opn = "sllv"; + break; + case OPC_SRAV: + tcg_gen_andi_tl(t0, t0, 0x1f); + tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); + opn = "srav"; + break; + case OPC_SRLV: + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_andi_tl(t0, t0, 0x1f); + tcg_gen_shr_tl(t0, t1, t0); + tcg_gen_ext32s_tl(cpu_gpr[rd], t0); + opn = "srlv"; + break; + case OPC_ROTRV: + { + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_andi_i32(t2, t2, 0x1f); + tcg_gen_rotr_i32(t2, t3, t2); + tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + opn = "rotrv"; + } + break; +#if defined(TARGET_MIPS64) + case OPC_DSLLV: + tcg_gen_andi_tl(t0, t0, 0x3f); + tcg_gen_shl_tl(cpu_gpr[rd], t1, t0); + opn = "dsllv"; + break; + case OPC_DSRAV: + tcg_gen_andi_tl(t0, t0, 0x3f); + tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); + opn = "dsrav"; + break; + case OPC_DSRLV: + tcg_gen_andi_tl(t0, t0, 0x3f); + tcg_gen_shr_tl(cpu_gpr[rd], t1, t0); + opn = "dsrlv"; + break; + case OPC_DROTRV: + tcg_gen_andi_tl(t0, t0, 0x3f); + tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0); + opn = "drotrv"; + break; +#endif + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* Arithmetic on HI/LO registers */ +static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) +{ + const char *opn = "hilo"; + + if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + switch (opc) { + case OPC_MFHI: + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]); + opn = "mfhi"; + break; + case OPC_MFLO: + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]); + opn = "mflo"; + break; + case OPC_MTHI: + if (reg != 0) + tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]); + else + tcg_gen_movi_tl(cpu_HI[0], 0); + opn = "mthi"; + break; + case OPC_MTLO: + if (reg != 0) + tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]); + else + tcg_gen_movi_tl(cpu_LO[0], 0); + opn = "mtlo"; + break; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s", opn, regnames[reg]); +} + +static void gen_muldiv (DisasContext *ctx, uint32_t opc, + int rs, int rt) +{ + const char *opn = "mul/div"; + TCGv t0, t1; + + switch (opc) { + case OPC_DIV: + case OPC_DIVU: +#if defined(TARGET_MIPS64) + case OPC_DDIV: + case OPC_DDIVU: +#endif + t0 = tcg_temp_local_new(); + t1 = tcg_temp_local_new(); + break; + default: + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + break; + } + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + switch (opc) { + case OPC_DIV: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_ext32s_tl(t1, t1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); + + tcg_gen_mov_tl(cpu_LO[0], t0); + tcg_gen_movi_tl(cpu_HI[0], 0); + tcg_gen_br(l1); + gen_set_label(l2); + tcg_gen_div_tl(cpu_LO[0], t0, t1); + tcg_gen_rem_tl(cpu_HI[0], t0, t1); + tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]); + tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]); + gen_set_label(l1); + } + opn = "div"; + break; + case OPC_DIVU: + { + int l1 = gen_new_label(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_divu_tl(cpu_LO[0], t0, t1); + tcg_gen_remu_tl(cpu_HI[0], t0, t1); + tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]); + tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]); + gen_set_label(l1); + } + opn = "divu"; + break; + case OPC_MULT: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "mult"; + break; + case OPC_MULTU: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "multu"; + break; +#if defined(TARGET_MIPS64) + case OPC_DDIV: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); + tcg_gen_mov_tl(cpu_LO[0], t0); + tcg_gen_movi_tl(cpu_HI[0], 0); + tcg_gen_br(l1); + gen_set_label(l2); + tcg_gen_div_i64(cpu_LO[0], t0, t1); + tcg_gen_rem_i64(cpu_HI[0], t0, t1); + gen_set_label(l1); + } + opn = "ddiv"; + break; + case OPC_DDIVU: + { + int l1 = gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_divu_i64(cpu_LO[0], t0, t1); + tcg_gen_remu_i64(cpu_HI[0], t0, t1); + gen_set_label(l1); + } + opn = "ddivu"; + break; + case OPC_DMULT: + gen_helper_dmult(t0, t1); + opn = "dmult"; + break; + case OPC_DMULTU: + gen_helper_dmultu(t0, t1); + opn = "dmultu"; + break; +#endif + case OPC_MADD: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "madd"; + break; + case OPC_MADDU: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "maddu"; + break; + case OPC_MSUB: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_sub_i64(t2, t3, t2); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "msub"; + break; + case OPC_MSUBU: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_sub_i64(t2, t3, t2); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "msubu"; + break; + default: + MIPS_INVAL(opn); + generate_exception(ctx, EXCP_RI); + goto out; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]); + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + const char *opn = "mul vr54xx"; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + switch (opc) { + case OPC_VR54XX_MULS: + gen_helper_muls(t0, t0, t1); + opn = "muls"; + break; + case OPC_VR54XX_MULSU: + gen_helper_mulsu(t0, t0, t1); + opn = "mulsu"; + break; + case OPC_VR54XX_MACC: + gen_helper_macc(t0, t0, t1); + opn = "macc"; + break; + case OPC_VR54XX_MACCU: + gen_helper_maccu(t0, t0, t1); + opn = "maccu"; + break; + case OPC_VR54XX_MSAC: + gen_helper_msac(t0, t0, t1); + opn = "msac"; + break; + case OPC_VR54XX_MSACU: + gen_helper_msacu(t0, t0, t1); + opn = "msacu"; + break; + case OPC_VR54XX_MULHI: + gen_helper_mulhi(t0, t0, t1); + opn = "mulhi"; + break; + case OPC_VR54XX_MULHIU: + gen_helper_mulhiu(t0, t0, t1); + opn = "mulhiu"; + break; + case OPC_VR54XX_MULSHI: + gen_helper_mulshi(t0, t0, t1); + opn = "mulshi"; + break; + case OPC_VR54XX_MULSHIU: + gen_helper_mulshiu(t0, t0, t1); + opn = "mulshiu"; + break; + case OPC_VR54XX_MACCHI: + gen_helper_macchi(t0, t0, t1); + opn = "macchi"; + break; + case OPC_VR54XX_MACCHIU: + gen_helper_macchiu(t0, t0, t1); + opn = "macchiu"; + break; + case OPC_VR54XX_MSACHI: + gen_helper_msachi(t0, t0, t1); + opn = "msachi"; + break; + case OPC_VR54XX_MSACHIU: + gen_helper_msachiu(t0, t0, t1); + opn = "msachiu"; + break; + default: + MIPS_INVAL("mul vr54xx"); + generate_exception(ctx, EXCP_RI); + goto out; + } + gen_store_gpr(t0, rd); + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); + + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_cl (DisasContext *ctx, uint32_t opc, + int rd, int rs) +{ + const char *opn = "CLx"; + TCGv t0; + + if (rd == 0) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + t0 = tcg_temp_new(); + gen_load_gpr(t0, rs); + switch (opc) { + case OPC_CLO: + gen_helper_clo(cpu_gpr[rd], t0); + opn = "clo"; + break; + case OPC_CLZ: + gen_helper_clz(cpu_gpr[rd], t0); + opn = "clz"; + break; +#if defined(TARGET_MIPS64) + case OPC_DCLO: + gen_helper_dclo(cpu_gpr[rd], t0); + opn = "dclo"; + break; + case OPC_DCLZ: + gen_helper_dclz(cpu_gpr[rd], t0); + opn = "dclz"; + break; +#endif + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); + tcg_temp_free(t0); +} + +/* Godson integer instructions */ +static void gen_loongson_integer (DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + const char *opn = "loongson"; + TCGv t0, t1; + + if (rd == 0) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + switch (opc) { + case OPC_MULT_G_2E: + case OPC_MULT_G_2F: + case OPC_MULTU_G_2E: + case OPC_MULTU_G_2F: +#if defined(TARGET_MIPS64) + case OPC_DMULT_G_2E: + case OPC_DMULT_G_2F: + case OPC_DMULTU_G_2E: + case OPC_DMULTU_G_2F: +#endif + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + break; + default: + t0 = tcg_temp_local_new(); + t1 = tcg_temp_local_new(); + break; + } + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + switch (opc) { + case OPC_MULT_G_2E: + case OPC_MULT_G_2F: + tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + opn = "mult.g"; + break; + case OPC_MULTU_G_2E: + case OPC_MULTU_G_2F: + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + opn = "multu.g"; + break; + case OPC_DIV_G_2E: + case OPC_DIV_G_2F: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + int l3 = gen_new_label(); + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_ext32s_tl(t1, t1); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l3); + gen_set_label(l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + tcg_gen_br(l3); + gen_set_label(l2); + tcg_gen_div_tl(cpu_gpr[rd], t0, t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + gen_set_label(l3); + } + opn = "div.g"; + break; + case OPC_DIVU_G_2E: + case OPC_DIVU_G_2F: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + gen_set_label(l2); + } + opn = "divu.g"; + break; + case OPC_MOD_G_2E: + case OPC_MOD_G_2F: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + int l3 = gen_new_label(); + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); + gen_set_label(l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l3); + gen_set_label(l2); + tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + gen_set_label(l3); + } + opn = "mod.g"; + break; + case OPC_MODU_G_2E: + case OPC_MODU_G_2F: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + gen_set_label(l2); + } + opn = "modu.g"; + break; +#if defined(TARGET_MIPS64) + case OPC_DMULT_G_2E: + case OPC_DMULT_G_2F: + tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); + opn = "dmult.g"; + break; + case OPC_DMULTU_G_2E: + case OPC_DMULTU_G_2F: + tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); + opn = "dmultu.g"; + break; + case OPC_DDIV_G_2E: + case OPC_DDIV_G_2F: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + int l3 = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l3); + gen_set_label(l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + tcg_gen_br(l3); + gen_set_label(l2); + tcg_gen_div_tl(cpu_gpr[rd], t0, t1); + gen_set_label(l3); + } + opn = "ddiv.g"; + break; + case OPC_DDIVU_G_2E: + case OPC_DDIVU_G_2F: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); + gen_set_label(l2); + } + opn = "ddivu.g"; + break; + case OPC_DMOD_G_2E: + case OPC_DMOD_G_2F: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + int l3 = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); + gen_set_label(l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l3); + gen_set_label(l2); + tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); + gen_set_label(l3); + } + opn = "dmod.g"; + break; + case OPC_DMODU_G_2E: + case OPC_DMODU_G_2F: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); + gen_set_label(l2); + } + opn = "dmodu.g"; + break; +#endif + } + + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* Traps */ +static void gen_trap (DisasContext *ctx, uint32_t opc, + int rs, int rt, int16_t imm) +{ + int cond; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + cond = 0; + /* Load needed operands */ + switch (opc) { + case OPC_TEQ: + case OPC_TGE: + case OPC_TGEU: + case OPC_TLT: + case OPC_TLTU: + case OPC_TNE: + /* Compare two registers */ + if (rs != rt) { + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + cond = 1; + } + break; + case OPC_TEQI: + case OPC_TGEI: + case OPC_TGEIU: + case OPC_TLTI: + case OPC_TLTIU: + case OPC_TNEI: + /* Compare register to immediate */ + if (rs != 0 || imm != 0) { + gen_load_gpr(t0, rs); + tcg_gen_movi_tl(t1, (int32_t)imm); + cond = 1; + } + break; + } + if (cond == 0) { + switch (opc) { + case OPC_TEQ: /* rs == rs */ + case OPC_TEQI: /* r0 == 0 */ + case OPC_TGE: /* rs >= rs */ + case OPC_TGEI: /* r0 >= 0 */ + case OPC_TGEU: /* rs >= rs unsigned */ + case OPC_TGEIU: /* r0 >= 0 unsigned */ + /* Always trap */ + generate_exception(ctx, EXCP_TRAP); + break; + case OPC_TLT: /* rs < rs */ + case OPC_TLTI: /* r0 < 0 */ + case OPC_TLTU: /* rs < rs unsigned */ + case OPC_TLTIU: /* r0 < 0 unsigned */ + case OPC_TNE: /* rs != rs */ + case OPC_TNEI: /* r0 != 0 */ + /* Never trap: treat as NOP. */ + break; + } + } else { + int l1 = gen_new_label(); + + switch (opc) { + case OPC_TEQ: + case OPC_TEQI: + tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); + break; + case OPC_TGE: + case OPC_TGEI: + tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1); + break; + case OPC_TGEU: + case OPC_TGEIU: + tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1); + break; + case OPC_TLT: + case OPC_TLTI: + tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); + break; + case OPC_TLTU: + case OPC_TLTIU: + tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); + break; + case OPC_TNE: + case OPC_TNEI: + tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1); + break; + } + generate_exception(ctx, EXCP_TRAP); + gen_set_label(l1); + } + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) +{ + TranslationBlock *tb; + tb = ctx->tb; + if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && + likely(!ctx->singlestep_enabled)) { + tcg_gen_goto_tb(n); + gen_save_pc(dest); + tcg_gen_exit_tb((long)tb + n); + } else { + gen_save_pc(dest); + if (ctx->singlestep_enabled) { + save_cpu_state(ctx, 0); + gen_helper_0i(raise_exception, EXCP_DEBUG); + } + tcg_gen_exit_tb(0); + } +} + +/* Branches (before delay slot) */ +static void gen_compute_branch (DisasContext *ctx, uint32_t opc, + int insn_bytes, + int rs, int rt, int32_t offset) +{ + target_ulong btgt = -1; + int blink = 0; + int bcond_compute = 0; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { +#ifdef MIPS_DEBUG_DISAS + LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc); +#endif + generate_exception(ctx, EXCP_RI); + goto out; + } + + /* Load needed operands */ + switch (opc) { + case OPC_BEQ: + case OPC_BEQL: + case OPC_BNE: + case OPC_BNEL: + /* Compare two registers */ + if (rs != rt) { + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + bcond_compute = 1; + } + btgt = ctx->pc + insn_bytes + offset; + break; + case OPC_BGEZ: + case OPC_BGEZAL: + case OPC_BGEZALS: + case OPC_BGEZALL: + case OPC_BGEZL: + case OPC_BGTZ: + case OPC_BGTZL: + case OPC_BLEZ: + case OPC_BLEZL: + case OPC_BLTZ: + case OPC_BLTZAL: + case OPC_BLTZALS: + case OPC_BLTZALL: + case OPC_BLTZL: + /* Compare to zero */ + if (rs != 0) { + gen_load_gpr(t0, rs); + bcond_compute = 1; + } + btgt = ctx->pc + insn_bytes + offset; + break; + case OPC_J: + case OPC_JAL: + case OPC_JALX: + case OPC_JALS: + case OPC_JALXS: + /* Jump to immediate */ + btgt = ((ctx->pc + insn_bytes) & (int32_t)0xF0000000) | (uint32_t)offset; + break; + case OPC_JR: + case OPC_JALR: + case OPC_JALRC: + case OPC_JALRS: + /* Jump to register */ + if (offset != 0 && offset != 16) { + /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the + others are reserved. */ + MIPS_INVAL("jump hint"); + generate_exception(ctx, EXCP_RI); + goto out; + } + gen_load_gpr(btarget, rs); + break; + default: + MIPS_INVAL("branch/jump"); + generate_exception(ctx, EXCP_RI); + goto out; + } + if (bcond_compute == 0) { + /* No condition to be computed */ + switch (opc) { + case OPC_BEQ: /* rx == rx */ + case OPC_BEQL: /* rx == rx likely */ + case OPC_BGEZ: /* 0 >= 0 */ + case OPC_BGEZL: /* 0 >= 0 likely */ + case OPC_BLEZ: /* 0 <= 0 */ + case OPC_BLEZL: /* 0 <= 0 likely */ + /* Always take */ + ctx->hflags |= MIPS_HFLAG_B; + MIPS_DEBUG("balways"); + break; + case OPC_BGEZALS: + case OPC_BGEZAL: /* 0 >= 0 */ + case OPC_BGEZALL: /* 0 >= 0 likely */ + ctx->hflags |= (opc == OPC_BGEZALS + ? MIPS_HFLAG_BDS16 + : MIPS_HFLAG_BDS32); + /* Always take and link */ + blink = 31; + ctx->hflags |= MIPS_HFLAG_B; + MIPS_DEBUG("balways and link"); + break; + case OPC_BNE: /* rx != rx */ + case OPC_BGTZ: /* 0 > 0 */ + case OPC_BLTZ: /* 0 < 0 */ + /* Treat as NOP. */ + MIPS_DEBUG("bnever (NOP)"); + goto out; + case OPC_BLTZALS: + case OPC_BLTZAL: /* 0 < 0 */ + ctx->hflags |= (opc == OPC_BLTZALS + ? MIPS_HFLAG_BDS16 + : MIPS_HFLAG_BDS32); + /* Handle as an unconditional branch to get correct delay + slot checking. */ + blink = 31; + btgt = ctx->pc + (opc == OPC_BLTZALS ? 6 : 8); + ctx->hflags |= MIPS_HFLAG_B; + MIPS_DEBUG("bnever and link"); + break; + case OPC_BLTZALL: /* 0 < 0 likely */ + tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8); + /* Skip the instruction in the delay slot */ + MIPS_DEBUG("bnever, link and skip"); + ctx->pc += 4; + goto out; + case OPC_BNEL: /* rx != rx likely */ + case OPC_BGTZL: /* 0 > 0 likely */ + case OPC_BLTZL: /* 0 < 0 likely */ + /* Skip the instruction in the delay slot */ + MIPS_DEBUG("bnever and skip"); + ctx->pc += 4; + goto out; + case OPC_J: + ctx->hflags |= MIPS_HFLAG_B; + MIPS_DEBUG("j " TARGET_FMT_lx, btgt); + break; + case OPC_JALXS: + case OPC_JALX: + ctx->hflags |= MIPS_HFLAG_BX; + /* Fallthrough */ + case OPC_JALS: + case OPC_JAL: + blink = 31; + ctx->hflags |= MIPS_HFLAG_B; + ctx->hflags |= ((opc == OPC_JALS || opc == OPC_JALXS) + ? MIPS_HFLAG_BDS16 + : MIPS_HFLAG_BDS32); + MIPS_DEBUG("jal " TARGET_FMT_lx, btgt); + break; + case OPC_JR: + ctx->hflags |= MIPS_HFLAG_BR; + if (insn_bytes == 4) + ctx->hflags |= MIPS_HFLAG_BDS32; + MIPS_DEBUG("jr %s", regnames[rs]); + break; + case OPC_JALRS: + case OPC_JALR: + case OPC_JALRC: + blink = rt; + ctx->hflags |= MIPS_HFLAG_BR; + ctx->hflags |= (opc == OPC_JALRS + ? MIPS_HFLAG_BDS16 + : MIPS_HFLAG_BDS32); + MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]); + break; + default: + MIPS_INVAL("branch/jump"); + generate_exception(ctx, EXCP_RI); + goto out; + } + } else { + switch (opc) { + case OPC_BEQ: + tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); + MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx, + regnames[rs], regnames[rt], btgt); + goto not_likely; + case OPC_BEQL: + tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); + MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx, + regnames[rs], regnames[rt], btgt); + goto likely; + case OPC_BNE: + tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); + MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx, + regnames[rs], regnames[rt], btgt); + goto not_likely; + case OPC_BNEL: + tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); + MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx, + regnames[rs], regnames[rt], btgt); + goto likely; + case OPC_BGEZ: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); + MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto not_likely; + case OPC_BGEZL: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); + MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BGEZALS: + case OPC_BGEZAL: + ctx->hflags |= (opc == OPC_BGEZALS + ? MIPS_HFLAG_BDS16 + : MIPS_HFLAG_BDS32); + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); + MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt); + blink = 31; + goto not_likely; + case OPC_BGEZALL: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); + blink = 31; + MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BGTZ: + tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); + MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto not_likely; + case OPC_BGTZL: + tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); + MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BLEZ: + tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); + MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto not_likely; + case OPC_BLEZL: + tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); + MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BLTZ: + tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); + MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto not_likely; + case OPC_BLTZL: + tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); + MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BLTZALS: + case OPC_BLTZAL: + ctx->hflags |= (opc == OPC_BLTZALS + ? MIPS_HFLAG_BDS16 + : MIPS_HFLAG_BDS32); + tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); + blink = 31; + MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt); + not_likely: + ctx->hflags |= MIPS_HFLAG_BC; + break; + case OPC_BLTZALL: + tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); + blink = 31; + MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt); + likely: + ctx->hflags |= MIPS_HFLAG_BL; + break; + default: + MIPS_INVAL("conditional branch/jump"); + generate_exception(ctx, EXCP_RI); + goto out; + } + } + MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx, + blink, ctx->hflags, btgt); + + ctx->btarget = btgt; + if (blink > 0) { + int post_delay = insn_bytes; + int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16); + + if (opc != OPC_JALRC) + post_delay += ((ctx->hflags & MIPS_HFLAG_BDS16) ? 2 : 4); + + tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + post_delay + lowbit); + } + + out: + if (insn_bytes == 2) + ctx->hflags |= MIPS_HFLAG_B16; + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* special3 bitfield operations */ +static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, + int rs, int lsb, int msb) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + target_ulong mask; + + gen_load_gpr(t1, rs); + switch (opc) { + case OPC_EXT: + if (lsb + msb > 31) + goto fail; + tcg_gen_shri_tl(t0, t1, lsb); + if (msb != 31) { + tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1); + } else { + tcg_gen_ext32s_tl(t0, t0); + } + break; +#if defined(TARGET_MIPS64) + case OPC_DEXTM: + tcg_gen_shri_tl(t0, t1, lsb); + if (msb != 31) { + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1); + } + break; + case OPC_DEXTU: + tcg_gen_shri_tl(t0, t1, lsb + 32); + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); + break; + case OPC_DEXT: + tcg_gen_shri_tl(t0, t1, lsb); + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); + break; +#endif + case OPC_INS: + if (lsb > msb) + goto fail; + mask = ((msb - lsb + 1 < 32) ? ((1 << (msb - lsb + 1)) - 1) : ~0) << lsb; + gen_load_gpr(t0, rt); + tcg_gen_andi_tl(t0, t0, ~mask); + tcg_gen_shli_tl(t1, t1, lsb); + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_ext32s_tl(t0, t0); + break; +#if defined(TARGET_MIPS64) + case OPC_DINSM: + if (lsb > msb) + goto fail; + mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) - 1) : ~0ULL) << lsb; + gen_load_gpr(t0, rt); + tcg_gen_andi_tl(t0, t0, ~mask); + tcg_gen_shli_tl(t1, t1, lsb); + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_or_tl(t0, t0, t1); + break; + case OPC_DINSU: + if (lsb > msb) + goto fail; + mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32); + gen_load_gpr(t0, rt); + tcg_gen_andi_tl(t0, t0, ~mask); + tcg_gen_shli_tl(t1, t1, lsb + 32); + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_or_tl(t0, t0, t1); + break; + case OPC_DINS: + if (lsb > msb) + goto fail; + gen_load_gpr(t0, rt); + mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb; + gen_load_gpr(t0, rt); + tcg_gen_andi_tl(t0, t0, ~mask); + tcg_gen_shli_tl(t1, t1, lsb); + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_or_tl(t0, t0, t1); + break; +#endif + default: +fail: + MIPS_INVAL("bitops"); + generate_exception(ctx, EXCP_RI); + tcg_temp_free(t0); + tcg_temp_free(t1); + return; + } + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) +{ + TCGv t0; + + if (rd == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + gen_load_gpr(t0, rt); + switch (op2) { + case OPC_WSBH: + { + TCGv t1 = tcg_temp_new(); + + tcg_gen_shri_tl(t1, t0, 8); + tcg_gen_andi_tl(t1, t1, 0x00FF00FF); + tcg_gen_shli_tl(t0, t0, 8); + tcg_gen_andi_tl(t0, t0, ~0x00FF00FF); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], t0); + } + break; + case OPC_SEB: + tcg_gen_ext8s_tl(cpu_gpr[rd], t0); + break; + case OPC_SEH: + tcg_gen_ext16s_tl(cpu_gpr[rd], t0); + break; +#if defined(TARGET_MIPS64) + case OPC_DSBH: + { + TCGv t1 = tcg_temp_new(); + + tcg_gen_shri_tl(t1, t0, 8); + tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL); + tcg_gen_shli_tl(t0, t0, 8); + tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL); + tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t1); + } + break; + case OPC_DSHD: + { + TCGv t1 = tcg_temp_new(); + + tcg_gen_shri_tl(t1, t0, 16); + tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL); + tcg_gen_shli_tl(t0, t0, 16); + tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL); + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_shri_tl(t1, t0, 32); + tcg_gen_shli_tl(t0, t0, 32); + tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t1); + } + break; +#endif + default: + MIPS_INVAL("bsfhl"); + generate_exception(ctx, EXCP_RI); + tcg_temp_free(t0); + return; + } + tcg_temp_free(t0); +} + +#ifndef CONFIG_USER_ONLY +/* CP0 (MMU and control) */ +static inline void gen_mfc0_load32 (TCGv arg, target_ulong off) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_ld_i32(t0, cpu_env, off); + tcg_gen_ext_i32_tl(arg, t0); + tcg_temp_free_i32(t0); +} + +static inline void gen_mfc0_load64 (TCGv arg, target_ulong off) +{ + tcg_gen_ld_tl(arg, cpu_env, off); + tcg_gen_ext32s_tl(arg, arg); +} + +static inline void gen_mtc0_store32 (TCGv arg, target_ulong off) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t0, arg); + tcg_gen_st_i32(t0, cpu_env, off); + tcg_temp_free_i32(t0); +} + +static inline void gen_mtc0_store64 (TCGv arg, target_ulong off) +{ + tcg_gen_ext32s_tl(arg, arg); + tcg_gen_st_tl(arg, cpu_env, off); +} + +static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +{ + const char *rn = "invalid"; + + if (sel != 0) + check_insn(env, ctx, ISA_MIPS32); + + switch (reg) { + case 0: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index)); + rn = "Index"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpcontrol(arg); + rn = "MVPControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpconf0(arg); + rn = "MVPConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpconf1(arg); + rn = "MVPConf1"; + break; + default: + goto die; + } + break; + case 1: + switch (sel) { + case 0: + gen_helper_mfc0_random(arg); + rn = "Random"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl)); + rn = "VPEControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0)); + rn = "VPEConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1)); + rn = "VPEConf1"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask)); + rn = "YQMask"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule)); + rn = "VPESchedule"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack)); + rn = "VPEScheFBack"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt)); + rn = "VPEOpt"; + break; + default: + goto die; + } + break; + case 2: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0)); + tcg_gen_ext32s_tl(arg, arg); + rn = "EntryLo0"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcstatus(arg); + rn = "TCStatus"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcbind(arg); + rn = "TCBind"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcrestart(arg); + rn = "TCRestart"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tchalt(arg); + rn = "TCHalt"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tccontext(arg); + rn = "TCContext"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcschedule(arg); + rn = "TCSchedule"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcschefback(arg); + rn = "TCScheFBack"; + break; + default: + goto die; + } + break; + case 3: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1)); + tcg_gen_ext32s_tl(arg, arg); + rn = "EntryLo1"; + break; + default: + goto die; + } + break; + case 4: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context)); + tcg_gen_ext32s_tl(arg, arg); + rn = "Context"; + break; + case 1: +// gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */ + rn = "ContextConfig"; +// break; + default: + goto die; + } + break; + case 5: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask)); + rn = "PageMask"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain)); + rn = "PageGrain"; + break; + default: + goto die; + } + break; + case 6: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired)); + rn = "Wired"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0)); + rn = "SRSConf0"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1)); + rn = "SRSConf1"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2)); + rn = "SRSConf2"; + break; + case 4: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3)); + rn = "SRSConf3"; + break; + case 5: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4)); + rn = "SRSConf4"; + break; + default: + goto die; + } + break; + case 7: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna)); + rn = "HWREna"; + break; + default: + goto die; + } + break; + case 8: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr)); + tcg_gen_ext32s_tl(arg, arg); + rn = "BadVAddr"; + break; + default: + goto die; + } + break; + case 9: + switch (sel) { + case 0: + /* Mark as an IO operation because we read the time. */ + if (use_icount) + gen_io_start(); + gen_helper_mfc0_count(arg); + if (use_icount) { + gen_io_end(); + } + /* Break the TB to be able to take timer interrupts immediately + after reading count. */ + ctx->bstate = BS_STOP; + rn = "Count"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 10: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi)); + tcg_gen_ext32s_tl(arg, arg); + rn = "EntryHi"; + break; + default: + goto die; + } + break; + case 11: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare)); + rn = "Compare"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 12: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status)); + rn = "Status"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl)); + rn = "IntCtl"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl)); + rn = "SRSCtl"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap)); + rn = "SRSMap"; + break; + default: + goto die; + } + break; + case 13: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause)); + rn = "Cause"; + break; + default: + goto die; + } + break; + case 14: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC)); + tcg_gen_ext32s_tl(arg, arg); + rn = "EPC"; + break; + default: + goto die; + } + break; + case 15: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid)); + rn = "PRid"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase)); + rn = "EBase"; + break; + default: + goto die; + } + break; + case 16: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0)); + rn = "Config"; + break; + case 1: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1)); + rn = "Config1"; + break; + case 2: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2)); + rn = "Config2"; + break; + case 3: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3)); + rn = "Config3"; + break; + /* 4,5 are reserved */ + /* 6,7 are implementation dependent */ + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6)); + rn = "Config6"; + break; + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7)); + rn = "Config7"; + break; + default: + goto die; + } + break; + case 17: + switch (sel) { + case 0: + gen_helper_mfc0_lladdr(arg); + rn = "LLAddr"; + break; + default: + goto die; + } + break; + case 18: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mfc0_watchlo, arg, sel); + rn = "WatchLo"; + break; + default: + goto die; + } + break; + case 19: + switch (sel) { + case 0 ...7: + gen_helper_1i(mfc0_watchhi, arg, sel); + rn = "WatchHi"; + break; + default: + goto die; + } + break; + case 20: + switch (sel) { + case 0: +#if defined(TARGET_MIPS64) + check_insn(env, ctx, ISA_MIPS3); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext)); + tcg_gen_ext32s_tl(arg, arg); + rn = "XContext"; + break; +#endif + default: + goto die; + } + break; + case 21: + /* Officially reserved, but sel 0 is used for R1x000 framemask */ + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask)); + rn = "Framemask"; + break; + default: + goto die; + } + break; + case 22: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "'Diagnostic"; /* implementation dependent */ + break; + case 23: + switch (sel) { + case 0: + gen_helper_mfc0_debug(arg); /* EJTAG support */ + rn = "Debug"; + break; + case 1: +// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */ + rn = "TraceControl"; +// break; + case 2: +// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */ + rn = "TraceControl2"; +// break; + case 3: +// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */ + rn = "UserTraceData"; +// break; + case 4: +// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */ + rn = "TraceBPC"; +// break; + default: + goto die; + } + break; + case 24: + switch (sel) { + case 0: + /* EJTAG support */ + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC)); + tcg_gen_ext32s_tl(arg, arg); + rn = "DEPC"; + break; + default: + goto die; + } + break; + case 25: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0)); + rn = "Performance0"; + break; + case 1: +// gen_helper_mfc0_performance1(arg); + rn = "Performance1"; +// break; + case 2: +// gen_helper_mfc0_performance2(arg); + rn = "Performance2"; +// break; + case 3: +// gen_helper_mfc0_performance3(arg); + rn = "Performance3"; +// break; + case 4: +// gen_helper_mfc0_performance4(arg); + rn = "Performance4"; +// break; + case 5: +// gen_helper_mfc0_performance5(arg); + rn = "Performance5"; +// break; + case 6: +// gen_helper_mfc0_performance6(arg); + rn = "Performance6"; +// break; + case 7: +// gen_helper_mfc0_performance7(arg); + rn = "Performance7"; +// break; + default: + goto die; + } + break; + case 26: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "ECC"; + break; + case 27: + switch (sel) { + case 0 ... 3: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "CacheErr"; + break; + default: + goto die; + } + break; + case 28: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo)); + rn = "TagLo"; + break; + case 1: + case 3: + case 5: + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo)); + rn = "DataLo"; + break; + default: + goto die; + } + break; + case 29: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi)); + rn = "TagHi"; + break; + case 1: + case 3: + case 5: + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi)); + rn = "DataHi"; + break; + default: + goto die; + } + break; + case 30: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC)); + tcg_gen_ext32s_tl(arg, arg); + rn = "ErrorEPC"; + break; + default: + goto die; + } + break; + case 31: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE)); + rn = "DESAVE"; + break; + default: + goto die; + } + break; + default: + goto die; + } + (void)rn; /* avoid a compiler warning */ + LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel); + return; + +die: + LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel); + generate_exception(ctx, EXCP_RI); +} + +static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +{ + const char *rn = "invalid"; + + if (sel != 0) + check_insn(env, ctx, ISA_MIPS32); + + if (use_icount) + gen_io_start(); + + switch (reg) { + case 0: + switch (sel) { + case 0: + gen_helper_mtc0_index(arg); + rn = "Index"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_mvpcontrol(arg); + rn = "MVPControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + /* ignored */ + rn = "MVPConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + /* ignored */ + rn = "MVPConf1"; + break; + default: + goto die; + } + break; + case 1: + switch (sel) { + case 0: + /* ignored */ + rn = "Random"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpecontrol(arg); + rn = "VPEControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeconf0(arg); + rn = "VPEConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeconf1(arg); + rn = "VPEConf1"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_yqmask(arg); + rn = "YQMask"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule)); + rn = "VPESchedule"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack)); + rn = "VPEScheFBack"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeopt(arg); + rn = "VPEOpt"; + break; + default: + goto die; + } + break; + case 2: + switch (sel) { + case 0: + gen_helper_mtc0_entrylo0(arg); + rn = "EntryLo0"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcstatus(arg); + rn = "TCStatus"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcbind(arg); + rn = "TCBind"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcrestart(arg); + rn = "TCRestart"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tchalt(arg); + rn = "TCHalt"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tccontext(arg); + rn = "TCContext"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcschedule(arg); + rn = "TCSchedule"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcschefback(arg); + rn = "TCScheFBack"; + break; + default: + goto die; + } + break; + case 3: + switch (sel) { + case 0: + gen_helper_mtc0_entrylo1(arg); + rn = "EntryLo1"; + break; + default: + goto die; + } + break; + case 4: + switch (sel) { + case 0: + gen_helper_mtc0_context(arg); + rn = "Context"; + break; + case 1: +// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */ + rn = "ContextConfig"; +// break; + default: + goto die; + } + break; + case 5: + switch (sel) { + case 0: + gen_helper_mtc0_pagemask(arg); + rn = "PageMask"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_pagegrain(arg); + rn = "PageGrain"; + break; + default: + goto die; + } + break; + case 6: + switch (sel) { + case 0: + gen_helper_mtc0_wired(arg); + rn = "Wired"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf0(arg); + rn = "SRSConf0"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf1(arg); + rn = "SRSConf1"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf2(arg); + rn = "SRSConf2"; + break; + case 4: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf3(arg); + rn = "SRSConf3"; + break; + case 5: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf4(arg); + rn = "SRSConf4"; + break; + default: + goto die; + } + break; + case 7: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_hwrena(arg); + rn = "HWREna"; + break; + default: + goto die; + } + break; + case 8: + /* ignored */ + rn = "BadVAddr"; + break; + case 9: + switch (sel) { + case 0: + gen_helper_mtc0_count(arg); + rn = "Count"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 10: + switch (sel) { + case 0: + gen_helper_mtc0_entryhi(arg); + rn = "EntryHi"; + break; + default: + goto die; + } + break; + case 11: + switch (sel) { + case 0: + gen_helper_mtc0_compare(arg); + rn = "Compare"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 12: + switch (sel) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_mtc0_status(arg); + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; + rn = "Status"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_intctl(arg); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "IntCtl"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsctl(arg); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "SRSCtl"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap)); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "SRSMap"; + break; + default: + goto die; + } + break; + case 13: + switch (sel) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_mtc0_cause(arg); + rn = "Cause"; + break; + default: + goto die; + } + break; + case 14: + switch (sel) { + case 0: + gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC)); + rn = "EPC"; + break; + default: + goto die; + } + break; + case 15: + switch (sel) { + case 0: + /* ignored */ + rn = "PRid"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_ebase(arg); + rn = "EBase"; + break; + default: + goto die; + } + break; + case 16: + switch (sel) { + case 0: + gen_helper_mtc0_config0(arg); + rn = "Config"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 1: + /* ignored, read only */ + rn = "Config1"; + break; + case 2: + gen_helper_mtc0_config2(arg); + rn = "Config2"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 3: + /* ignored, read only */ + rn = "Config3"; + break; + /* 4,5 are reserved */ + /* 6,7 are implementation dependent */ + case 6: + /* ignored */ + rn = "Config6"; + break; + case 7: + /* ignored */ + rn = "Config7"; + break; + default: + rn = "Invalid config selector"; + goto die; + } + break; + case 17: + switch (sel) { + case 0: + gen_helper_mtc0_lladdr(arg); + rn = "LLAddr"; + break; + default: + goto die; + } + break; + case 18: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mtc0_watchlo, arg, sel); + rn = "WatchLo"; + break; + default: + goto die; + } + break; + case 19: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mtc0_watchhi, arg, sel); + rn = "WatchHi"; + break; + default: + goto die; + } + break; + case 20: + switch (sel) { + case 0: +#if defined(TARGET_MIPS64) + check_insn(env, ctx, ISA_MIPS3); + gen_helper_mtc0_xcontext(arg); + rn = "XContext"; + break; +#endif + default: + goto die; + } + break; + case 21: + /* Officially reserved, but sel 0 is used for R1x000 framemask */ + switch (sel) { + case 0: + gen_helper_mtc0_framemask(arg); + rn = "Framemask"; + break; + default: + goto die; + } + break; + case 22: + /* ignored */ + rn = "Diagnostic"; /* implementation dependent */ + break; + case 23: + switch (sel) { + case 0: + gen_helper_mtc0_debug(arg); /* EJTAG support */ + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; + rn = "Debug"; + break; + case 1: +// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */ + rn = "TraceControl"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; +// break; + case 2: +// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */ + rn = "TraceControl2"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; +// break; + case 3: + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; +// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */ + rn = "UserTraceData"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; +// break; + case 4: +// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "TraceBPC"; +// break; + default: + goto die; + } + break; + case 24: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC)); + rn = "DEPC"; + break; + default: + goto die; + } + break; + case 25: + switch (sel) { + case 0: + gen_helper_mtc0_performance0(arg); + rn = "Performance0"; + break; + case 1: +// gen_helper_mtc0_performance1(arg); + rn = "Performance1"; +// break; + case 2: +// gen_helper_mtc0_performance2(arg); + rn = "Performance2"; +// break; + case 3: +// gen_helper_mtc0_performance3(arg); + rn = "Performance3"; +// break; + case 4: +// gen_helper_mtc0_performance4(arg); + rn = "Performance4"; +// break; + case 5: +// gen_helper_mtc0_performance5(arg); + rn = "Performance5"; +// break; + case 6: +// gen_helper_mtc0_performance6(arg); + rn = "Performance6"; +// break; + case 7: +// gen_helper_mtc0_performance7(arg); + rn = "Performance7"; +// break; + default: + goto die; + } + break; + case 26: + /* ignored */ + rn = "ECC"; + break; + case 27: + switch (sel) { + case 0 ... 3: + /* ignored */ + rn = "CacheErr"; + break; + default: + goto die; + } + break; + case 28: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_helper_mtc0_taglo(arg); + rn = "TagLo"; + break; + case 1: + case 3: + case 5: + case 7: + gen_helper_mtc0_datalo(arg); + rn = "DataLo"; + break; + default: + goto die; + } + break; + case 29: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_helper_mtc0_taghi(arg); + rn = "TagHi"; + break; + case 1: + case 3: + case 5: + case 7: + gen_helper_mtc0_datahi(arg); + rn = "DataHi"; + break; + default: + rn = "invalid sel"; + goto die; + } + break; + case 30: + switch (sel) { + case 0: + gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC)); + rn = "ErrorEPC"; + break; + default: + goto die; + } + break; + case 31: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE)); + rn = "DESAVE"; + break; + default: + goto die; + } + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + default: + goto die; + } + (void)rn; /* avoid a compiler warning */ + LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); + /* For simplicity assume that all writes can cause interrupts. */ + if (use_icount) { + gen_io_end(); + ctx->bstate = BS_STOP; + } + return; + +die: + LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); + generate_exception(ctx, EXCP_RI); +} + +#if defined(TARGET_MIPS64) +static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +{ + const char *rn = "invalid"; + + if (sel != 0) + check_insn(env, ctx, ISA_MIPS64); + + switch (reg) { + case 0: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index)); + rn = "Index"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpcontrol(arg); + rn = "MVPControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpconf0(arg); + rn = "MVPConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpconf1(arg); + rn = "MVPConf1"; + break; + default: + goto die; + } + break; + case 1: + switch (sel) { + case 0: + gen_helper_mfc0_random(arg); + rn = "Random"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl)); + rn = "VPEControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0)); + rn = "VPEConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1)); + rn = "VPEConf1"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask)); + rn = "YQMask"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule)); + rn = "VPESchedule"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); + rn = "VPEScheFBack"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt)); + rn = "VPEOpt"; + break; + default: + goto die; + } + break; + case 2: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0)); + rn = "EntryLo0"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcstatus(arg); + rn = "TCStatus"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcbind(arg); + rn = "TCBind"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tcrestart(arg); + rn = "TCRestart"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tchalt(arg); + rn = "TCHalt"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tccontext(arg); + rn = "TCContext"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tcschedule(arg); + rn = "TCSchedule"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tcschefback(arg); + rn = "TCScheFBack"; + break; + default: + goto die; + } + break; + case 3: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1)); + rn = "EntryLo1"; + break; + default: + goto die; + } + break; + case 4: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context)); + rn = "Context"; + break; + case 1: +// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */ + rn = "ContextConfig"; +// break; + default: + goto die; + } + break; + case 5: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask)); + rn = "PageMask"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain)); + rn = "PageGrain"; + break; + default: + goto die; + } + break; + case 6: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired)); + rn = "Wired"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0)); + rn = "SRSConf0"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1)); + rn = "SRSConf1"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2)); + rn = "SRSConf2"; + break; + case 4: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3)); + rn = "SRSConf3"; + break; + case 5: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4)); + rn = "SRSConf4"; + break; + default: + goto die; + } + break; + case 7: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna)); + rn = "HWREna"; + break; + default: + goto die; + } + break; + case 8: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr)); + rn = "BadVAddr"; + break; + default: + goto die; + } + break; + case 9: + switch (sel) { + case 0: + /* Mark as an IO operation because we read the time. */ + if (use_icount) + gen_io_start(); + gen_helper_mfc0_count(arg); + if (use_icount) { + gen_io_end(); + } + /* Break the TB to be able to take timer interrupts immediately + after reading count. */ + ctx->bstate = BS_STOP; + rn = "Count"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 10: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi)); + rn = "EntryHi"; + break; + default: + goto die; + } + break; + case 11: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare)); + rn = "Compare"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 12: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status)); + rn = "Status"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl)); + rn = "IntCtl"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl)); + rn = "SRSCtl"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap)); + rn = "SRSMap"; + break; + default: + goto die; + } + break; + case 13: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause)); + rn = "Cause"; + break; + default: + goto die; + } + break; + case 14: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC)); + rn = "EPC"; + break; + default: + goto die; + } + break; + case 15: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid)); + rn = "PRid"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase)); + rn = "EBase"; + break; + default: + goto die; + } + break; + case 16: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0)); + rn = "Config"; + break; + case 1: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1)); + rn = "Config1"; + break; + case 2: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2)); + rn = "Config2"; + break; + case 3: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3)); + rn = "Config3"; + break; + /* 6,7 are implementation dependent */ + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6)); + rn = "Config6"; + break; + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7)); + rn = "Config7"; + break; + default: + goto die; + } + break; + case 17: + switch (sel) { + case 0: + gen_helper_dmfc0_lladdr(arg); + rn = "LLAddr"; + break; + default: + goto die; + } + break; + case 18: + switch (sel) { + case 0 ... 7: + gen_helper_1i(dmfc0_watchlo, arg, sel); + rn = "WatchLo"; + break; + default: + goto die; + } + break; + case 19: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mfc0_watchhi, arg, sel); + rn = "WatchHi"; + break; + default: + goto die; + } + break; + case 20: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS3); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext)); + rn = "XContext"; + break; + default: + goto die; + } + break; + case 21: + /* Officially reserved, but sel 0 is used for R1x000 framemask */ + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask)); + rn = "Framemask"; + break; + default: + goto die; + } + break; + case 22: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "'Diagnostic"; /* implementation dependent */ + break; + case 23: + switch (sel) { + case 0: + gen_helper_mfc0_debug(arg); /* EJTAG support */ + rn = "Debug"; + break; + case 1: +// gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */ + rn = "TraceControl"; +// break; + case 2: +// gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */ + rn = "TraceControl2"; +// break; + case 3: +// gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */ + rn = "UserTraceData"; +// break; + case 4: +// gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */ + rn = "TraceBPC"; +// break; + default: + goto die; + } + break; + case 24: + switch (sel) { + case 0: + /* EJTAG support */ + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC)); + rn = "DEPC"; + break; + default: + goto die; + } + break; + case 25: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0)); + rn = "Performance0"; + break; + case 1: +// gen_helper_dmfc0_performance1(arg); + rn = "Performance1"; +// break; + case 2: +// gen_helper_dmfc0_performance2(arg); + rn = "Performance2"; +// break; + case 3: +// gen_helper_dmfc0_performance3(arg); + rn = "Performance3"; +// break; + case 4: +// gen_helper_dmfc0_performance4(arg); + rn = "Performance4"; +// break; + case 5: +// gen_helper_dmfc0_performance5(arg); + rn = "Performance5"; +// break; + case 6: +// gen_helper_dmfc0_performance6(arg); + rn = "Performance6"; +// break; + case 7: +// gen_helper_dmfc0_performance7(arg); + rn = "Performance7"; +// break; + default: + goto die; + } + break; + case 26: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "ECC"; + break; + case 27: + switch (sel) { + /* ignored */ + case 0 ... 3: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "CacheErr"; + break; + default: + goto die; + } + break; + case 28: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo)); + rn = "TagLo"; + break; + case 1: + case 3: + case 5: + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo)); + rn = "DataLo"; + break; + default: + goto die; + } + break; + case 29: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi)); + rn = "TagHi"; + break; + case 1: + case 3: + case 5: + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi)); + rn = "DataHi"; + break; + default: + goto die; + } + break; + case 30: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC)); + rn = "ErrorEPC"; + break; + default: + goto die; + } + break; + case 31: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE)); + rn = "DESAVE"; + break; + default: + goto die; + } + break; + default: + goto die; + } + (void)rn; /* avoid a compiler warning */ + LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel); + return; + +die: + LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel); + generate_exception(ctx, EXCP_RI); +} + +static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +{ + const char *rn = "invalid"; + + if (sel != 0) + check_insn(env, ctx, ISA_MIPS64); + + if (use_icount) + gen_io_start(); + + switch (reg) { + case 0: + switch (sel) { + case 0: + gen_helper_mtc0_index(arg); + rn = "Index"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_mvpcontrol(arg); + rn = "MVPControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + /* ignored */ + rn = "MVPConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + /* ignored */ + rn = "MVPConf1"; + break; + default: + goto die; + } + break; + case 1: + switch (sel) { + case 0: + /* ignored */ + rn = "Random"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpecontrol(arg); + rn = "VPEControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeconf0(arg); + rn = "VPEConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeconf1(arg); + rn = "VPEConf1"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_yqmask(arg); + rn = "YQMask"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule)); + rn = "VPESchedule"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); + rn = "VPEScheFBack"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeopt(arg); + rn = "VPEOpt"; + break; + default: + goto die; + } + break; + case 2: + switch (sel) { + case 0: + gen_helper_mtc0_entrylo0(arg); + rn = "EntryLo0"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcstatus(arg); + rn = "TCStatus"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcbind(arg); + rn = "TCBind"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcrestart(arg); + rn = "TCRestart"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tchalt(arg); + rn = "TCHalt"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tccontext(arg); + rn = "TCContext"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcschedule(arg); + rn = "TCSchedule"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcschefback(arg); + rn = "TCScheFBack"; + break; + default: + goto die; + } + break; + case 3: + switch (sel) { + case 0: + gen_helper_mtc0_entrylo1(arg); + rn = "EntryLo1"; + break; + default: + goto die; + } + break; + case 4: + switch (sel) { + case 0: + gen_helper_mtc0_context(arg); + rn = "Context"; + break; + case 1: +// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */ + rn = "ContextConfig"; +// break; + default: + goto die; + } + break; + case 5: + switch (sel) { + case 0: + gen_helper_mtc0_pagemask(arg); + rn = "PageMask"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_pagegrain(arg); + rn = "PageGrain"; + break; + default: + goto die; + } + break; + case 6: + switch (sel) { + case 0: + gen_helper_mtc0_wired(arg); + rn = "Wired"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf0(arg); + rn = "SRSConf0"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf1(arg); + rn = "SRSConf1"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf2(arg); + rn = "SRSConf2"; + break; + case 4: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf3(arg); + rn = "SRSConf3"; + break; + case 5: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf4(arg); + rn = "SRSConf4"; + break; + default: + goto die; + } + break; + case 7: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_hwrena(arg); + rn = "HWREna"; + break; + default: + goto die; + } + break; + case 8: + /* ignored */ + rn = "BadVAddr"; + break; + case 9: + switch (sel) { + case 0: + gen_helper_mtc0_count(arg); + rn = "Count"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 10: + switch (sel) { + case 0: + gen_helper_mtc0_entryhi(arg); + rn = "EntryHi"; + break; + default: + goto die; + } + break; + case 11: + switch (sel) { + case 0: + gen_helper_mtc0_compare(arg); + rn = "Compare"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 12: + switch (sel) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_mtc0_status(arg); + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; + rn = "Status"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_intctl(arg); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "IntCtl"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsctl(arg); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "SRSCtl"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap)); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "SRSMap"; + break; + default: + goto die; + } + break; + case 13: + switch (sel) { + case 0: + save_cpu_state(ctx, 1); + /* Mark as an IO operation because we may trigger a software + interrupt. */ + if (use_icount) { + gen_io_start(); + } + gen_helper_mtc0_cause(arg); + if (use_icount) { + gen_io_end(); + } + /* Stop translation as we may have triggered an intetrupt */ + ctx->bstate = BS_STOP; + rn = "Cause"; + break; + default: + goto die; + } + break; + case 14: + switch (sel) { + case 0: + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC)); + rn = "EPC"; + break; + default: + goto die; + } + break; + case 15: + switch (sel) { + case 0: + /* ignored */ + rn = "PRid"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_ebase(arg); + rn = "EBase"; + break; + default: + goto die; + } + break; + case 16: + switch (sel) { + case 0: + gen_helper_mtc0_config0(arg); + rn = "Config"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 1: + /* ignored, read only */ + rn = "Config1"; + break; + case 2: + gen_helper_mtc0_config2(arg); + rn = "Config2"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 3: + /* ignored */ + rn = "Config3"; + break; + /* 6,7 are implementation dependent */ + default: + rn = "Invalid config selector"; + goto die; + } + break; + case 17: + switch (sel) { + case 0: + gen_helper_mtc0_lladdr(arg); + rn = "LLAddr"; + break; + default: + goto die; + } + break; + case 18: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mtc0_watchlo, arg, sel); + rn = "WatchLo"; + break; + default: + goto die; + } + break; + case 19: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mtc0_watchhi, arg, sel); + rn = "WatchHi"; + break; + default: + goto die; + } + break; + case 20: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS3); + gen_helper_mtc0_xcontext(arg); + rn = "XContext"; + break; + default: + goto die; + } + break; + case 21: + /* Officially reserved, but sel 0 is used for R1x000 framemask */ + switch (sel) { + case 0: + gen_helper_mtc0_framemask(arg); + rn = "Framemask"; + break; + default: + goto die; + } + break; + case 22: + /* ignored */ + rn = "Diagnostic"; /* implementation dependent */ + break; + case 23: + switch (sel) { + case 0: + gen_helper_mtc0_debug(arg); /* EJTAG support */ + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; + rn = "Debug"; + break; + case 1: +// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "TraceControl"; +// break; + case 2: +// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "TraceControl2"; +// break; + case 3: +// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "UserTraceData"; +// break; + case 4: +// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "TraceBPC"; +// break; + default: + goto die; + } + break; + case 24: + switch (sel) { + case 0: + /* EJTAG support */ + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC)); + rn = "DEPC"; + break; + default: + goto die; + } + break; + case 25: + switch (sel) { + case 0: + gen_helper_mtc0_performance0(arg); + rn = "Performance0"; + break; + case 1: +// gen_helper_mtc0_performance1(arg); + rn = "Performance1"; +// break; + case 2: +// gen_helper_mtc0_performance2(arg); + rn = "Performance2"; +// break; + case 3: +// gen_helper_mtc0_performance3(arg); + rn = "Performance3"; +// break; + case 4: +// gen_helper_mtc0_performance4(arg); + rn = "Performance4"; +// break; + case 5: +// gen_helper_mtc0_performance5(arg); + rn = "Performance5"; +// break; + case 6: +// gen_helper_mtc0_performance6(arg); + rn = "Performance6"; +// break; + case 7: +// gen_helper_mtc0_performance7(arg); + rn = "Performance7"; +// break; + default: + goto die; + } + break; + case 26: + /* ignored */ + rn = "ECC"; + break; + case 27: + switch (sel) { + case 0 ... 3: + /* ignored */ + rn = "CacheErr"; + break; + default: + goto die; + } + break; + case 28: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_helper_mtc0_taglo(arg); + rn = "TagLo"; + break; + case 1: + case 3: + case 5: + case 7: + gen_helper_mtc0_datalo(arg); + rn = "DataLo"; + break; + default: + goto die; + } + break; + case 29: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_helper_mtc0_taghi(arg); + rn = "TagHi"; + break; + case 1: + case 3: + case 5: + case 7: + gen_helper_mtc0_datahi(arg); + rn = "DataHi"; + break; + default: + rn = "invalid sel"; + goto die; + } + break; + case 30: + switch (sel) { + case 0: + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC)); + rn = "ErrorEPC"; + break; + default: + goto die; + } + break; + case 31: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE)); + rn = "DESAVE"; + break; + default: + goto die; + } + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + default: + goto die; + } + (void)rn; /* avoid a compiler warning */ + LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); + /* For simplicity assume that all writes can cause interrupts. */ + if (use_icount) { + gen_io_end(); + ctx->bstate = BS_STOP; + } + return; + +die: + LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); + generate_exception(ctx, EXCP_RI); +} +#endif /* TARGET_MIPS64 */ + +static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd, + int u, int sel, int h) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + TCGv t0 = tcg_temp_local_new(); + + if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && + ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != + (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) + tcg_gen_movi_tl(t0, -1); + else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > + (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) + tcg_gen_movi_tl(t0, -1); + else if (u == 0) { + switch (rt) { + case 2: + switch (sel) { + case 1: + gen_helper_mftc0_tcstatus(t0); + break; + case 2: + gen_helper_mftc0_tcbind(t0); + break; + case 3: + gen_helper_mftc0_tcrestart(t0); + break; + case 4: + gen_helper_mftc0_tchalt(t0); + break; + case 5: + gen_helper_mftc0_tccontext(t0); + break; + case 6: + gen_helper_mftc0_tcschedule(t0); + break; + case 7: + gen_helper_mftc0_tcschefback(t0); + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + break; + } + break; + case 10: + switch (sel) { + case 0: + gen_helper_mftc0_entryhi(t0); + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + break; + } + case 12: + switch (sel) { + case 0: + gen_helper_mftc0_status(t0); + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + break; + } + case 23: + switch (sel) { + case 0: + gen_helper_mftc0_debug(t0); + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + break; + } + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + } + } else switch (sel) { + /* GPR registers. */ + case 0: + gen_helper_1i(mftgpr, t0, rt); + break; + /* Auxiliary CPU registers */ + case 1: + switch (rt) { + case 0: + gen_helper_1i(mftlo, t0, 0); + break; + case 1: + gen_helper_1i(mfthi, t0, 0); + break; + case 2: + gen_helper_1i(mftacx, t0, 0); + break; + case 4: + gen_helper_1i(mftlo, t0, 1); + break; + case 5: + gen_helper_1i(mfthi, t0, 1); + break; + case 6: + gen_helper_1i(mftacx, t0, 1); + break; + case 8: + gen_helper_1i(mftlo, t0, 2); + break; + case 9: + gen_helper_1i(mfthi, t0, 2); + break; + case 10: + gen_helper_1i(mftacx, t0, 2); + break; + case 12: + gen_helper_1i(mftlo, t0, 3); + break; + case 13: + gen_helper_1i(mfthi, t0, 3); + break; + case 14: + gen_helper_1i(mftacx, t0, 3); + break; + case 16: + gen_helper_mftdsp(t0); + break; + default: + goto die; + } + break; + /* Floating point (COP1). */ + case 2: + /* XXX: For now we support only a single FPU context. */ + if (h == 0) { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, rt); + tcg_gen_ext_i32_tl(t0, fp0); + tcg_temp_free_i32(fp0); + } else { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, rt); + tcg_gen_ext_i32_tl(t0, fp0); + tcg_temp_free_i32(fp0); + } + break; + case 3: + /* XXX: For now we support only a single FPU context. */ + gen_helper_1i(cfc1, t0, rt); + break; + /* COP2: Not implemented. */ + case 4: + case 5: + /* fall through */ + default: + goto die; + } + LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + return; + +die: + tcg_temp_free(t0); + LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); + generate_exception(ctx, EXCP_RI); +} + +static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt, + int u, int sel, int h) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + TCGv t0 = tcg_temp_local_new(); + + gen_load_gpr(t0, rt); + if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && + ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != + (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) + /* NOP */ ; + else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > + (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) + /* NOP */ ; + else if (u == 0) { + switch (rd) { + case 2: + switch (sel) { + case 1: + gen_helper_mttc0_tcstatus(t0); + break; + case 2: + gen_helper_mttc0_tcbind(t0); + break; + case 3: + gen_helper_mttc0_tcrestart(t0); + break; + case 4: + gen_helper_mttc0_tchalt(t0); + break; + case 5: + gen_helper_mttc0_tccontext(t0); + break; + case 6: + gen_helper_mttc0_tcschedule(t0); + break; + case 7: + gen_helper_mttc0_tcschefback(t0); + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + break; + } + break; + case 10: + switch (sel) { + case 0: + gen_helper_mttc0_entryhi(t0); + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + break; + } + case 12: + switch (sel) { + case 0: + gen_helper_mttc0_status(t0); + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + break; + } + case 23: + switch (sel) { + case 0: + gen_helper_mttc0_debug(t0); + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + break; + } + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + } + } else switch (sel) { + /* GPR registers. */ + case 0: + gen_helper_1i(mttgpr, t0, rd); + break; + /* Auxiliary CPU registers */ + case 1: + switch (rd) { + case 0: + gen_helper_1i(mttlo, t0, 0); + break; + case 1: + gen_helper_1i(mtthi, t0, 0); + break; + case 2: + gen_helper_1i(mttacx, t0, 0); + break; + case 4: + gen_helper_1i(mttlo, t0, 1); + break; + case 5: + gen_helper_1i(mtthi, t0, 1); + break; + case 6: + gen_helper_1i(mttacx, t0, 1); + break; + case 8: + gen_helper_1i(mttlo, t0, 2); + break; + case 9: + gen_helper_1i(mtthi, t0, 2); + break; + case 10: + gen_helper_1i(mttacx, t0, 2); + break; + case 12: + gen_helper_1i(mttlo, t0, 3); + break; + case 13: + gen_helper_1i(mtthi, t0, 3); + break; + case 14: + gen_helper_1i(mttacx, t0, 3); + break; + case 16: + gen_helper_mttdsp(t0); + break; + default: + goto die; + } + break; + /* Floating point (COP1). */ + case 2: + /* XXX: For now we support only a single FPU context. */ + if (h == 0) { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32(fp0, rd); + tcg_temp_free_i32(fp0); + } else { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32h(fp0, rd); + tcg_temp_free_i32(fp0); + } + break; + case 3: + /* XXX: For now we support only a single FPU context. */ + gen_helper_1i(ctc1, t0, rd); + break; + /* COP2: Not implemented. */ + case 4: + case 5: + /* fall through */ + default: + goto die; + } + LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); + tcg_temp_free(t0); + return; + +die: + tcg_temp_free(t0); + LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); + generate_exception(ctx, EXCP_RI); +} + +static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd) +{ + const char *opn = "ldst"; + + switch (opc) { + case OPC_MFC0: + if (rt == 0) { + /* Treat as NOP. */ + return; + } + gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); + opn = "mfc0"; + break; + case OPC_MTC0: + { + TCGv t0 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7); + tcg_temp_free(t0); + } + opn = "mtc0"; + break; +#if defined(TARGET_MIPS64) + case OPC_DMFC0: + check_insn(env, ctx, ISA_MIPS3); + if (rt == 0) { + /* Treat as NOP. */ + return; + } + gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); + opn = "dmfc0"; + break; + case OPC_DMTC0: + check_insn(env, ctx, ISA_MIPS3); + { + TCGv t0 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7); + tcg_temp_free(t0); + } + opn = "dmtc0"; + break; +#endif + case OPC_MFTR: + check_insn(env, ctx, ASE_MT); + if (rd == 0) { + /* Treat as NOP. */ + return; + } + gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, + ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); + opn = "mftr"; + break; + case OPC_MTTR: + check_insn(env, ctx, ASE_MT); + gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, + ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); + opn = "mttr"; + break; + case OPC_TLBWI: + opn = "tlbwi"; + if (!env->tlb->helper_tlbwi) + goto die; + gen_helper_tlbwi(); + break; + case OPC_TLBWR: + opn = "tlbwr"; + if (!env->tlb->helper_tlbwr) + goto die; + gen_helper_tlbwr(); + break; + case OPC_TLBP: + opn = "tlbp"; + if (!env->tlb->helper_tlbp) + goto die; + gen_helper_tlbp(); + break; + case OPC_TLBR: + opn = "tlbr"; + if (!env->tlb->helper_tlbr) + goto die; + gen_helper_tlbr(); + break; + case OPC_ERET: + opn = "eret"; + check_insn(env, ctx, ISA_MIPS2); + gen_helper_eret(); + ctx->bstate = BS_EXCP; + break; + case OPC_DERET: + opn = "deret"; + check_insn(env, ctx, ISA_MIPS32); + if (!(ctx->hflags & MIPS_HFLAG_DM)) { + MIPS_INVAL(opn); + generate_exception(ctx, EXCP_RI); + } else { + gen_helper_deret(); + ctx->bstate = BS_EXCP; + } + break; + case OPC_WAIT: + opn = "wait"; + check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); + /* If we get an exception, we want to restart at next instruction */ + ctx->pc += 4; + save_cpu_state(ctx, 1); + ctx->pc -= 4; + gen_helper_wait(); + ctx->bstate = BS_EXCP; + break; + default: + die: + MIPS_INVAL(opn); + generate_exception(ctx, EXCP_RI); + return; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd); +} +#endif /* !CONFIG_USER_ONLY */ + +/* CP1 Branches (before delay slot) */ +static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, + int32_t cc, int32_t offset) +{ + target_ulong btarget; + const char *opn = "cp1 cond branch"; + TCGv_i32 t0 = tcg_temp_new_i32(); + + if (cc != 0) + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + + btarget = ctx->pc + 4 + offset; + + switch (op) { + case OPC_BC1F: + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + opn = "bc1f"; + goto not_likely; + case OPC_BC1FL: + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + opn = "bc1fl"; + goto likely; + case OPC_BC1T: + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + opn = "bc1t"; + goto not_likely; + case OPC_BC1TL: + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + opn = "bc1tl"; + likely: + ctx->hflags |= MIPS_HFLAG_BL; + break; + case OPC_BC1FANY2: + { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_nor_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + } + opn = "bc1any2f"; + goto not_likely; + case OPC_BC1TANY2: + { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + } + opn = "bc1any2t"; + goto not_likely; + case OPC_BC1FANY4: + { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); + tcg_gen_nor_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + } + opn = "bc1any4f"; + goto not_likely; + case OPC_BC1TANY4: + { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + } + opn = "bc1any4t"; + not_likely: + ctx->hflags |= MIPS_HFLAG_BC; + break; + default: + MIPS_INVAL(opn); + generate_exception (ctx, EXCP_RI); + goto out; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn, + ctx->hflags, btarget); + ctx->btarget = btarget; + + out: + tcg_temp_free_i32(t0); +} + +/* Coprocessor 1 (FPU) */ + +#define FOP(func, fmt) (((fmt) << 21) | (func)) + +enum fopcode { + OPC_ADD_S = FOP(0, FMT_S), + OPC_SUB_S = FOP(1, FMT_S), + OPC_MUL_S = FOP(2, FMT_S), + OPC_DIV_S = FOP(3, FMT_S), + OPC_SQRT_S = FOP(4, FMT_S), + OPC_ABS_S = FOP(5, FMT_S), + OPC_MOV_S = FOP(6, FMT_S), + OPC_NEG_S = FOP(7, FMT_S), + OPC_ROUND_L_S = FOP(8, FMT_S), + OPC_TRUNC_L_S = FOP(9, FMT_S), + OPC_CEIL_L_S = FOP(10, FMT_S), + OPC_FLOOR_L_S = FOP(11, FMT_S), + OPC_ROUND_W_S = FOP(12, FMT_S), + OPC_TRUNC_W_S = FOP(13, FMT_S), + OPC_CEIL_W_S = FOP(14, FMT_S), + OPC_FLOOR_W_S = FOP(15, FMT_S), + OPC_MOVCF_S = FOP(17, FMT_S), + OPC_MOVZ_S = FOP(18, FMT_S), + OPC_MOVN_S = FOP(19, FMT_S), + OPC_RECIP_S = FOP(21, FMT_S), + OPC_RSQRT_S = FOP(22, FMT_S), + OPC_RECIP2_S = FOP(28, FMT_S), + OPC_RECIP1_S = FOP(29, FMT_S), + OPC_RSQRT1_S = FOP(30, FMT_S), + OPC_RSQRT2_S = FOP(31, FMT_S), + OPC_CVT_D_S = FOP(33, FMT_S), + OPC_CVT_W_S = FOP(36, FMT_S), + OPC_CVT_L_S = FOP(37, FMT_S), + OPC_CVT_PS_S = FOP(38, FMT_S), + OPC_CMP_F_S = FOP (48, FMT_S), + OPC_CMP_UN_S = FOP (49, FMT_S), + OPC_CMP_EQ_S = FOP (50, FMT_S), + OPC_CMP_UEQ_S = FOP (51, FMT_S), + OPC_CMP_OLT_S = FOP (52, FMT_S), + OPC_CMP_ULT_S = FOP (53, FMT_S), + OPC_CMP_OLE_S = FOP (54, FMT_S), + OPC_CMP_ULE_S = FOP (55, FMT_S), + OPC_CMP_SF_S = FOP (56, FMT_S), + OPC_CMP_NGLE_S = FOP (57, FMT_S), + OPC_CMP_SEQ_S = FOP (58, FMT_S), + OPC_CMP_NGL_S = FOP (59, FMT_S), + OPC_CMP_LT_S = FOP (60, FMT_S), + OPC_CMP_NGE_S = FOP (61, FMT_S), + OPC_CMP_LE_S = FOP (62, FMT_S), + OPC_CMP_NGT_S = FOP (63, FMT_S), + + OPC_ADD_D = FOP(0, FMT_D), + OPC_SUB_D = FOP(1, FMT_D), + OPC_MUL_D = FOP(2, FMT_D), + OPC_DIV_D = FOP(3, FMT_D), + OPC_SQRT_D = FOP(4, FMT_D), + OPC_ABS_D = FOP(5, FMT_D), + OPC_MOV_D = FOP(6, FMT_D), + OPC_NEG_D = FOP(7, FMT_D), + OPC_ROUND_L_D = FOP(8, FMT_D), + OPC_TRUNC_L_D = FOP(9, FMT_D), + OPC_CEIL_L_D = FOP(10, FMT_D), + OPC_FLOOR_L_D = FOP(11, FMT_D), + OPC_ROUND_W_D = FOP(12, FMT_D), + OPC_TRUNC_W_D = FOP(13, FMT_D), + OPC_CEIL_W_D = FOP(14, FMT_D), + OPC_FLOOR_W_D = FOP(15, FMT_D), + OPC_MOVCF_D = FOP(17, FMT_D), + OPC_MOVZ_D = FOP(18, FMT_D), + OPC_MOVN_D = FOP(19, FMT_D), + OPC_RECIP_D = FOP(21, FMT_D), + OPC_RSQRT_D = FOP(22, FMT_D), + OPC_RECIP2_D = FOP(28, FMT_D), + OPC_RECIP1_D = FOP(29, FMT_D), + OPC_RSQRT1_D = FOP(30, FMT_D), + OPC_RSQRT2_D = FOP(31, FMT_D), + OPC_CVT_S_D = FOP(32, FMT_D), + OPC_CVT_W_D = FOP(36, FMT_D), + OPC_CVT_L_D = FOP(37, FMT_D), + OPC_CMP_F_D = FOP (48, FMT_D), + OPC_CMP_UN_D = FOP (49, FMT_D), + OPC_CMP_EQ_D = FOP (50, FMT_D), + OPC_CMP_UEQ_D = FOP (51, FMT_D), + OPC_CMP_OLT_D = FOP (52, FMT_D), + OPC_CMP_ULT_D = FOP (53, FMT_D), + OPC_CMP_OLE_D = FOP (54, FMT_D), + OPC_CMP_ULE_D = FOP (55, FMT_D), + OPC_CMP_SF_D = FOP (56, FMT_D), + OPC_CMP_NGLE_D = FOP (57, FMT_D), + OPC_CMP_SEQ_D = FOP (58, FMT_D), + OPC_CMP_NGL_D = FOP (59, FMT_D), + OPC_CMP_LT_D = FOP (60, FMT_D), + OPC_CMP_NGE_D = FOP (61, FMT_D), + OPC_CMP_LE_D = FOP (62, FMT_D), + OPC_CMP_NGT_D = FOP (63, FMT_D), + + OPC_CVT_S_W = FOP(32, FMT_W), + OPC_CVT_D_W = FOP(33, FMT_W), + OPC_CVT_S_L = FOP(32, FMT_L), + OPC_CVT_D_L = FOP(33, FMT_L), + OPC_CVT_PS_PW = FOP(38, FMT_W), + + OPC_ADD_PS = FOP(0, FMT_PS), + OPC_SUB_PS = FOP(1, FMT_PS), + OPC_MUL_PS = FOP(2, FMT_PS), + OPC_DIV_PS = FOP(3, FMT_PS), + OPC_ABS_PS = FOP(5, FMT_PS), + OPC_MOV_PS = FOP(6, FMT_PS), + OPC_NEG_PS = FOP(7, FMT_PS), + OPC_MOVCF_PS = FOP(17, FMT_PS), + OPC_MOVZ_PS = FOP(18, FMT_PS), + OPC_MOVN_PS = FOP(19, FMT_PS), + OPC_ADDR_PS = FOP(24, FMT_PS), + OPC_MULR_PS = FOP(26, FMT_PS), + OPC_RECIP2_PS = FOP(28, FMT_PS), + OPC_RECIP1_PS = FOP(29, FMT_PS), + OPC_RSQRT1_PS = FOP(30, FMT_PS), + OPC_RSQRT2_PS = FOP(31, FMT_PS), + + OPC_CVT_S_PU = FOP(32, FMT_PS), + OPC_CVT_PW_PS = FOP(36, FMT_PS), + OPC_CVT_S_PL = FOP(40, FMT_PS), + OPC_PLL_PS = FOP(44, FMT_PS), + OPC_PLU_PS = FOP(45, FMT_PS), + OPC_PUL_PS = FOP(46, FMT_PS), + OPC_PUU_PS = FOP(47, FMT_PS), + OPC_CMP_F_PS = FOP (48, FMT_PS), + OPC_CMP_UN_PS = FOP (49, FMT_PS), + OPC_CMP_EQ_PS = FOP (50, FMT_PS), + OPC_CMP_UEQ_PS = FOP (51, FMT_PS), + OPC_CMP_OLT_PS = FOP (52, FMT_PS), + OPC_CMP_ULT_PS = FOP (53, FMT_PS), + OPC_CMP_OLE_PS = FOP (54, FMT_PS), + OPC_CMP_ULE_PS = FOP (55, FMT_PS), + OPC_CMP_SF_PS = FOP (56, FMT_PS), + OPC_CMP_NGLE_PS = FOP (57, FMT_PS), + OPC_CMP_SEQ_PS = FOP (58, FMT_PS), + OPC_CMP_NGL_PS = FOP (59, FMT_PS), + OPC_CMP_LT_PS = FOP (60, FMT_PS), + OPC_CMP_NGE_PS = FOP (61, FMT_PS), + OPC_CMP_LE_PS = FOP (62, FMT_PS), + OPC_CMP_NGT_PS = FOP (63, FMT_PS), +}; + +static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) +{ + const char *opn = "cp1 move"; + TCGv t0 = tcg_temp_new(); + + switch (opc) { + case OPC_MFC1: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + tcg_gen_ext_i32_tl(t0, fp0); + tcg_temp_free_i32(fp0); + } + gen_store_gpr(t0, rt); + opn = "mfc1"; + break; + case OPC_MTC1: + gen_load_gpr(t0, rt); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32(fp0, fs); + tcg_temp_free_i32(fp0); + } + opn = "mtc1"; + break; + case OPC_CFC1: + gen_helper_1i(cfc1, t0, fs); + gen_store_gpr(t0, rt); + opn = "cfc1"; + break; + case OPC_CTC1: + gen_load_gpr(t0, rt); + gen_helper_1i(ctc1, t0, fs); + opn = "ctc1"; + break; +#if defined(TARGET_MIPS64) + case OPC_DMFC1: + gen_load_fpr64(ctx, t0, fs); + gen_store_gpr(t0, rt); + opn = "dmfc1"; + break; + case OPC_DMTC1: + gen_load_gpr(t0, rt); + gen_store_fpr64(ctx, t0, fs); + opn = "dmtc1"; + break; +#endif + case OPC_MFHC1: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, fs); + tcg_gen_ext_i32_tl(t0, fp0); + tcg_temp_free_i32(fp0); + } + gen_store_gpr(t0, rt); + opn = "mfhc1"; + break; + case OPC_MTHC1: + gen_load_gpr(t0, rt); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32h(fp0, fs); + tcg_temp_free_i32(fp0); + } + opn = "mthc1"; + break; + default: + MIPS_INVAL(opn); + generate_exception (ctx, EXCP_RI); + goto out; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]); + + out: + tcg_temp_free(t0); +} + +static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) +{ + int l1; + TCGCond cond; + TCGv_i32 t0; + + if (rd == 0) { + /* Treat as NOP. */ + return; + } + + if (tf) + cond = TCG_COND_EQ; + else + cond = TCG_COND_NE; + + l1 = gen_new_label(); + t0 = tcg_temp_new_i32(); + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + tcg_temp_free_i32(t0); + if (rs == 0) { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } else { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } + gen_set_label(l1); +} + +static inline void gen_movcf_s (int fs, int fd, int cc, int tf) +{ + int cond; + TCGv_i32 t0 = tcg_temp_new_i32(); + int l1 = gen_new_label(); + + if (tf) + cond = TCG_COND_EQ; + else + cond = TCG_COND_NE; + + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + gen_load_fpr32(t0, fs); + gen_store_fpr32(t0, fd); + gen_set_label(l1); + tcg_temp_free_i32(t0); +} + +static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) +{ + int cond; + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i64 fp0; + int l1 = gen_new_label(); + + if (tf) + cond = TCG_COND_EQ; + else + cond = TCG_COND_NE; + + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + tcg_temp_free_i32(t0); + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); +} + +static inline void gen_movcf_ps (int fs, int fd, int cc, int tf) +{ + int cond; + TCGv_i32 t0 = tcg_temp_new_i32(); + int l1 = gen_new_label(); + int l2 = gen_new_label(); + + if (tf) + cond = TCG_COND_EQ; + else + cond = TCG_COND_NE; + + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + gen_load_fpr32(t0, fs); + gen_store_fpr32(t0, fd); + gen_set_label(l1); + + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1)); + tcg_gen_brcondi_i32(cond, t0, 0, l2); + gen_load_fpr32h(t0, fs); + gen_store_fpr32h(t0, fd); + tcg_temp_free_i32(t0); + gen_set_label(l2); +} + + +static void gen_farith (DisasContext *ctx, enum fopcode op1, + int ft, int fs, int fd, int cc) +{ + const char *opn = "farith"; + const char *condnames[] = { + "c.f", + "c.un", + "c.eq", + "c.ueq", + "c.olt", + "c.ult", + "c.ole", + "c.ule", + "c.sf", + "c.ngle", + "c.seq", + "c.ngl", + "c.lt", + "c.nge", + "c.le", + "c.ngt", + }; + const char *condnames_abs[] = { + "cabs.f", + "cabs.un", + "cabs.eq", + "cabs.ueq", + "cabs.olt", + "cabs.ult", + "cabs.ole", + "cabs.ule", + "cabs.sf", + "cabs.ngle", + "cabs.seq", + "cabs.ngl", + "cabs.lt", + "cabs.nge", + "cabs.le", + "cabs.ngt", + }; + enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP; + uint32_t func = ctx->opcode & 0x3f; + + switch (op1) { + case OPC_ADD_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_add_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "add.s"; + optype = BINOP; + break; + case OPC_SUB_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_sub_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "sub.s"; + optype = BINOP; + break; + case OPC_MUL_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_mul_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "mul.s"; + optype = BINOP; + break; + case OPC_DIV_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_div_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "div.s"; + optype = BINOP; + break; + case OPC_SQRT_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_sqrt_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "sqrt.s"; + break; + case OPC_ABS_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_abs_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "abs.s"; + break; + case OPC_MOV_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "mov.s"; + break; + case OPC_NEG_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_chs_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "neg.s"; + break; + case OPC_ROUND_L_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_roundl_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "round.l.s"; + break; + case OPC_TRUNC_L_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_truncl_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "trunc.l.s"; + break; + case OPC_CEIL_L_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_ceill_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "ceil.l.s"; + break; + case OPC_FLOOR_L_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_floorl_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "floor.l.s"; + break; + case OPC_ROUND_W_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_roundw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "round.w.s"; + break; + case OPC_TRUNC_W_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_truncw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "trunc.w.s"; + break; + case OPC_CEIL_W_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_ceilw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "ceil.w.s"; + break; + case OPC_FLOOR_W_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_floorw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "floor.w.s"; + break; + case OPC_MOVCF_S: + gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1); + opn = "movcf.s"; + break; + case OPC_MOVZ_S: + { + int l1 = gen_new_label(); + TCGv_i32 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); + } + fp0 = tcg_temp_new_i32(); + gen_load_fpr32(fp0, fs); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + gen_set_label(l1); + } + opn = "movz.s"; + break; + case OPC_MOVN_S: + { + int l1 = gen_new_label(); + TCGv_i32 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); + fp0 = tcg_temp_new_i32(); + gen_load_fpr32(fp0, fs); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + gen_set_label(l1); + } + } + opn = "movn.s"; + break; + case OPC_RECIP_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_recip_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "recip.s"; + break; + case OPC_RSQRT_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_rsqrt_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "rsqrt.s"; + break; + case OPC_RECIP2_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, fd); + gen_helper_float_recip2_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "recip2.s"; + break; + case OPC_RECIP1_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_recip1_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "recip1.s"; + break; + case OPC_RSQRT1_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_rsqrt1_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "rsqrt1.s"; + break; + case OPC_RSQRT2_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_rsqrt2_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "rsqrt2.s"; + break; + case OPC_CVT_D_S: + check_cp1_registers(ctx, fd); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_cvtd_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "cvt.d.s"; + break; + case OPC_CVT_W_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_cvtw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "cvt.w.s"; + break; + case OPC_CVT_L_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_cvtl_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "cvt.l.s"; + break; + case OPC_CVT_PS_S: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp64 = tcg_temp_new_i64(); + TCGv_i32 fp32_0 = tcg_temp_new_i32(); + TCGv_i32 fp32_1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp32_0, fs); + gen_load_fpr32(fp32_1, ft); + tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1); + tcg_temp_free_i32(fp32_1); + tcg_temp_free_i32(fp32_0); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "cvt.ps.s"; + break; + case OPC_CMP_F_S: + case OPC_CMP_UN_S: + case OPC_CMP_EQ_S: + case OPC_CMP_UEQ_S: + case OPC_CMP_OLT_S: + case OPC_CMP_ULT_S: + case OPC_CMP_OLE_S: + case OPC_CMP_ULE_S: + case OPC_CMP_SF_S: + case OPC_CMP_NGLE_S: + case OPC_CMP_SEQ_S: + case OPC_CMP_NGL_S: + case OPC_CMP_LT_S: + case OPC_CMP_NGE_S: + case OPC_CMP_LE_S: + case OPC_CMP_NGT_S: + if (ctx->opcode & (1 << 6)) { + gen_cmpabs_s(ctx, func-48, ft, fs, cc); + opn = condnames_abs[func-48]; + } else { + gen_cmp_s(ctx, func-48, ft, fs, cc); + opn = condnames[func-48]; + } + break; + case OPC_ADD_D: + check_cp1_registers(ctx, fs | ft | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_add_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "add.d"; + optype = BINOP; + break; + case OPC_SUB_D: + check_cp1_registers(ctx, fs | ft | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_sub_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "sub.d"; + optype = BINOP; + break; + case OPC_MUL_D: + check_cp1_registers(ctx, fs | ft | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_mul_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mul.d"; + optype = BINOP; + break; + case OPC_DIV_D: + check_cp1_registers(ctx, fs | ft | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_div_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "div.d"; + optype = BINOP; + break; + case OPC_SQRT_D: + check_cp1_registers(ctx, fs | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_sqrt_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "sqrt.d"; + break; + case OPC_ABS_D: + check_cp1_registers(ctx, fs | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_abs_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "abs.d"; + break; + case OPC_MOV_D: + check_cp1_registers(ctx, fs | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mov.d"; + break; + case OPC_NEG_D: + check_cp1_registers(ctx, fs | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_chs_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "neg.d"; + break; + case OPC_ROUND_L_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_roundl_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "round.l.d"; + break; + case OPC_TRUNC_L_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_truncl_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "trunc.l.d"; + break; + case OPC_CEIL_L_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_ceill_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "ceil.l.d"; + break; + case OPC_FLOOR_L_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_floorl_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "floor.l.d"; + break; + case OPC_ROUND_W_D: + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_roundw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "round.w.d"; + break; + case OPC_TRUNC_W_D: + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_truncw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "trunc.w.d"; + break; + case OPC_CEIL_W_D: + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_ceilw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "ceil.w.d"; + break; + case OPC_FLOOR_W_D: + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_floorw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "floor.w.d"; + break; + case OPC_MOVCF_D: + gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); + opn = "movcf.d"; + break; + case OPC_MOVZ_D: + { + int l1 = gen_new_label(); + TCGv_i64 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); + } + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); + } + opn = "movz.d"; + break; + case OPC_MOVN_D: + { + int l1 = gen_new_label(); + TCGv_i64 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); + } + } + opn = "movn.d"; + break; + case OPC_RECIP_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_recip_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip.d"; + break; + case OPC_RSQRT_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_rsqrt_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt.d"; + break; + case OPC_RECIP2_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_recip2_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip2.d"; + break; + case OPC_RECIP1_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_recip1_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip1.d"; + break; + case OPC_RSQRT1_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_rsqrt1_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt1.d"; + break; + case OPC_RSQRT2_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_rsqrt2_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt2.d"; + break; + case OPC_CMP_F_D: + case OPC_CMP_UN_D: + case OPC_CMP_EQ_D: + case OPC_CMP_UEQ_D: + case OPC_CMP_OLT_D: + case OPC_CMP_ULT_D: + case OPC_CMP_OLE_D: + case OPC_CMP_ULE_D: + case OPC_CMP_SF_D: + case OPC_CMP_NGLE_D: + case OPC_CMP_SEQ_D: + case OPC_CMP_NGL_D: + case OPC_CMP_LT_D: + case OPC_CMP_NGE_D: + case OPC_CMP_LE_D: + case OPC_CMP_NGT_D: + if (ctx->opcode & (1 << 6)) { + gen_cmpabs_d(ctx, func-48, ft, fs, cc); + opn = condnames_abs[func-48]; + } else { + gen_cmp_d(ctx, func-48, ft, fs, cc); + opn = condnames[func-48]; + } + break; + case OPC_CVT_S_D: + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_cvts_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "cvt.s.d"; + break; + case OPC_CVT_W_D: + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_cvtw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "cvt.w.d"; + break; + case OPC_CVT_L_D: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_cvtl_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "cvt.l.d"; + break; + case OPC_CVT_S_W: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_cvts_w(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "cvt.s.w"; + break; + case OPC_CVT_D_W: + check_cp1_registers(ctx, fd); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_cvtd_w(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "cvt.d.w"; + break; + case OPC_CVT_S_L: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_cvts_l(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "cvt.s.l"; + break; + case OPC_CVT_D_L: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_cvtd_l(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "cvt.d.l"; + break; + case OPC_CVT_PS_PW: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_cvtps_pw(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "cvt.ps.pw"; + break; + case OPC_ADD_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_add_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "add.ps"; + break; + case OPC_SUB_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_sub_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "sub.ps"; + break; + case OPC_MUL_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_mul_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mul.ps"; + break; + case OPC_ABS_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_abs_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "abs.ps"; + break; + case OPC_MOV_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mov.ps"; + break; + case OPC_NEG_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_chs_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "neg.ps"; + break; + case OPC_MOVCF_PS: + check_cp1_64bitmode(ctx); + gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1); + opn = "movcf.ps"; + break; + case OPC_MOVZ_PS: + check_cp1_64bitmode(ctx); + { + int l1 = gen_new_label(); + TCGv_i64 fp0; + + if (ft != 0) + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); + } + opn = "movz.ps"; + break; + case OPC_MOVN_PS: + check_cp1_64bitmode(ctx); + { + int l1 = gen_new_label(); + TCGv_i64 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); + } + } + opn = "movn.ps"; + break; + case OPC_ADDR_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, ft); + gen_load_fpr64(ctx, fp1, fs); + gen_helper_float_addr_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "addr.ps"; + break; + case OPC_MULR_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, ft); + gen_load_fpr64(ctx, fp1, fs); + gen_helper_float_mulr_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mulr.ps"; + break; + case OPC_RECIP2_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, fd); + gen_helper_float_recip2_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip2.ps"; + break; + case OPC_RECIP1_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_recip1_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip1.ps"; + break; + case OPC_RSQRT1_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_rsqrt1_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt1.ps"; + break; + case OPC_RSQRT2_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_rsqrt2_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt2.ps"; + break; + case OPC_CVT_S_PU: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, fs); + gen_helper_float_cvts_pu(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "cvt.s.pu"; + break; + case OPC_CVT_PW_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_cvtpw_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "cvt.pw.ps"; + break; + case OPC_CVT_S_PL: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_cvts_pl(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "cvt.s.pl"; + break; + case OPC_PLL_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_store_fpr32h(fp0, fd); + gen_store_fpr32(fp1, fd); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + } + opn = "pll.ps"; + break; + case OPC_PLU_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32h(fp1, ft); + gen_store_fpr32(fp1, fd); + gen_store_fpr32h(fp0, fd); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + } + opn = "plu.ps"; + break; + case OPC_PUL_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_store_fpr32(fp1, fd); + gen_store_fpr32h(fp0, fd); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + } + opn = "pul.ps"; + break; + case OPC_PUU_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, fs); + gen_load_fpr32h(fp1, ft); + gen_store_fpr32(fp1, fd); + gen_store_fpr32h(fp0, fd); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + } + opn = "puu.ps"; + break; + case OPC_CMP_F_PS: + case OPC_CMP_UN_PS: + case OPC_CMP_EQ_PS: + case OPC_CMP_UEQ_PS: + case OPC_CMP_OLT_PS: + case OPC_CMP_ULT_PS: + case OPC_CMP_OLE_PS: + case OPC_CMP_ULE_PS: + case OPC_CMP_SF_PS: + case OPC_CMP_NGLE_PS: + case OPC_CMP_SEQ_PS: + case OPC_CMP_NGL_PS: + case OPC_CMP_LT_PS: + case OPC_CMP_NGE_PS: + case OPC_CMP_LE_PS: + case OPC_CMP_NGT_PS: + if (ctx->opcode & (1 << 6)) { + gen_cmpabs_ps(ctx, func-48, ft, fs, cc); + opn = condnames_abs[func-48]; + } else { + gen_cmp_ps(ctx, func-48, ft, fs, cc); + opn = condnames[func-48]; + } + break; + default: + MIPS_INVAL(opn); + generate_exception (ctx, EXCP_RI); + return; + } + (void)opn; /* avoid a compiler warning */ + switch (optype) { + case BINOP: + MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]); + break; + case CMPOP: + MIPS_DEBUG("%s %s,%s", opn, fregnames[fs], fregnames[ft]); + break; + default: + MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]); + break; + } +} + +/* Coprocessor 3 (FPU) */ +static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, + int fd, int fs, int base, int index) +{ + const char *opn = "extended float load/store"; + int store = 0; + TCGv t0 = tcg_temp_new(); + + if (base == 0) { + gen_load_gpr(t0, index); + } else if (index == 0) { + gen_load_gpr(t0, base); + } else { + gen_load_gpr(t0, index); + gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); + } + /* Don't do NOP if destination is zero: we must perform the actual + memory access. */ + save_cpu_state(ctx, 0); + switch (opc) { + case OPC_LWXC1: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "lwxc1"; + break; + case OPC_LDXC1: + check_cop1x(ctx); + check_cp1_registers(ctx, fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "ldxc1"; + break; + case OPC_LUXC1: + check_cp1_64bitmode(ctx); + tcg_gen_andi_tl(t0, t0, ~0x7); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "luxc1"; + break; + case OPC_SWXC1: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv t1 = tcg_temp_new(); + + gen_load_fpr32(fp0, fs); + tcg_gen_extu_i32_tl(t1, fp0); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); + tcg_temp_free_i32(fp0); + tcg_temp_free(t1); + } + opn = "swxc1"; + store = 1; + break; + case OPC_SDXC1: + check_cop1x(ctx); + check_cp1_registers(ctx, fs); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); + tcg_temp_free_i64(fp0); + } + opn = "sdxc1"; + store = 1; + break; + case OPC_SUXC1: + check_cp1_64bitmode(ctx); + tcg_gen_andi_tl(t0, t0, ~0x7); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); + tcg_temp_free_i64(fp0); + } + opn = "suxc1"; + store = 1; + break; + } + tcg_temp_free(t0); + (void)opn; (void)store; /* avoid compiler warnings */ + MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd], + regnames[index], regnames[base]); +} + +static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, + int fd, int fr, int fs, int ft) +{ + const char *opn = "flt3_arith"; + + switch (opc) { + case OPC_ALNV_PS: + check_cp1_64bitmode(ctx); + { + TCGv t0 = tcg_temp_local_new(); + TCGv_i32 fp = tcg_temp_new_i32(); + TCGv_i32 fph = tcg_temp_new_i32(); + int l1 = gen_new_label(); + int l2 = gen_new_label(); + + gen_load_gpr(t0, fr); + tcg_gen_andi_tl(t0, t0, 0x7); + + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); + gen_load_fpr32(fp, fs); + gen_load_fpr32h(fph, fs); + gen_store_fpr32(fp, fd); + gen_store_fpr32h(fph, fd); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); + tcg_temp_free(t0); +#ifdef TARGET_WORDS_BIGENDIAN + gen_load_fpr32(fp, fs); + gen_load_fpr32h(fph, ft); + gen_store_fpr32h(fp, fd); + gen_store_fpr32(fph, fd); +#else + gen_load_fpr32h(fph, fs); + gen_load_fpr32(fp, ft); + gen_store_fpr32(fph, fd); + gen_store_fpr32h(fp, fd); +#endif + gen_set_label(l2); + tcg_temp_free_i32(fp); + tcg_temp_free_i32(fph); + } + opn = "alnv.ps"; + break; + case OPC_MADD_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + TCGv_i32 fp2 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_load_fpr32(fp2, fr); + gen_helper_float_muladd_s(fp2, fp0, fp1, fp2); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp2, fd); + tcg_temp_free_i32(fp2); + } + opn = "madd.s"; + break; + case OPC_MADD_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_muladd_d(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "madd.d"; + break; + case OPC_MADD_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_muladd_ps(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "madd.ps"; + break; + case OPC_MSUB_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + TCGv_i32 fp2 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_load_fpr32(fp2, fr); + gen_helper_float_mulsub_s(fp2, fp0, fp1, fp2); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp2, fd); + tcg_temp_free_i32(fp2); + } + opn = "msub.s"; + break; + case OPC_MSUB_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_mulsub_d(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "msub.d"; + break; + case OPC_MSUB_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_mulsub_ps(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "msub.ps"; + break; + case OPC_NMADD_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + TCGv_i32 fp2 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_load_fpr32(fp2, fr); + gen_helper_float_nmuladd_s(fp2, fp0, fp1, fp2); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp2, fd); + tcg_temp_free_i32(fp2); + } + opn = "nmadd.s"; + break; + case OPC_NMADD_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_nmuladd_d(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "nmadd.d"; + break; + case OPC_NMADD_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_nmuladd_ps(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "nmadd.ps"; + break; + case OPC_NMSUB_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + TCGv_i32 fp2 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_load_fpr32(fp2, fr); + gen_helper_float_nmulsub_s(fp2, fp0, fp1, fp2); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp2, fd); + tcg_temp_free_i32(fp2); + } + opn = "nmsub.s"; + break; + case OPC_NMSUB_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_nmulsub_d(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "nmsub.d"; + break; + case OPC_NMSUB_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_nmulsub_ps(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "nmsub.ps"; + break; + default: + MIPS_INVAL(opn); + generate_exception (ctx, EXCP_RI); + return; + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr], + fregnames[fs], fregnames[ft]); +} + +static void +gen_rdhwr (CPUState *env, DisasContext *ctx, int rt, int rd) +{ + TCGv t0; + + check_insn(env, ctx, ISA_MIPS32R2); + t0 = tcg_temp_new(); + + switch (rd) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_cpunum(t0); + gen_store_gpr(t0, rt); + break; + case 1: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_synci_step(t0); + gen_store_gpr(t0, rt); + break; + case 2: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_cc(t0); + gen_store_gpr(t0, rt); + break; + case 3: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_ccres(t0); + gen_store_gpr(t0, rt); + break; + case 29: +#if defined(CONFIG_USER_ONLY) + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value)); + gen_store_gpr(t0, rt); + break; +#else + /* XXX: Some CPUs implement this in hardware. + Not supported yet. */ +#endif + default: /* Invalid */ + MIPS_INVAL("rdhwr"); + generate_exception(ctx, EXCP_RI); + break; + } + tcg_temp_free(t0); +} + +static void handle_delay_slot (CPUState *env, DisasContext *ctx, + int insn_bytes) +{ + if (ctx->hflags & MIPS_HFLAG_BMASK) { + int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK; + /* Branches completion */ + ctx->hflags &= ~MIPS_HFLAG_BMASK; + ctx->bstate = BS_BRANCH; + save_cpu_state(ctx, 0); + /* FIXME: Need to clear can_do_io. */ + switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) { + case MIPS_HFLAG_B: + /* unconditional branch */ + MIPS_DEBUG("unconditional branch"); + if (proc_hflags & MIPS_HFLAG_BX) { + tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16); + } + gen_goto_tb(ctx, 0, ctx->btarget); + break; + case MIPS_HFLAG_BL: + /* blikely taken case */ + MIPS_DEBUG("blikely branch taken"); + gen_goto_tb(ctx, 0, ctx->btarget); + break; + case MIPS_HFLAG_BC: + /* Conditional branch */ + MIPS_DEBUG("conditional branch"); + { + int l1 = gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); + gen_goto_tb(ctx, 1, ctx->pc + insn_bytes); + gen_set_label(l1); + gen_goto_tb(ctx, 0, ctx->btarget); + } + break; + case MIPS_HFLAG_BR: + /* unconditional branch to register */ + MIPS_DEBUG("branch to register"); + if (env->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { + TCGv t0 = tcg_temp_new(); + TCGv_i32 t1 = tcg_temp_new_i32(); + + tcg_gen_andi_tl(t0, btarget, 0x1); + tcg_gen_trunc_tl_i32(t1, t0); + tcg_temp_free(t0); + tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16); + tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT); + tcg_gen_or_i32(hflags, hflags, t1); + tcg_temp_free_i32(t1); + + tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1); + } else { + tcg_gen_mov_tl(cpu_PC, btarget); + } + if (ctx->singlestep_enabled) { + save_cpu_state(ctx, 0); + gen_helper_0i(raise_exception, EXCP_DEBUG); + } + tcg_gen_exit_tb(0); + break; + default: + MIPS_DEBUG("unknown branch"); + break; + } + } +} + +/* ISA extensions (ASEs) */ +/* MIPS16 extension to MIPS32 */ + +/* MIPS16 major opcodes */ +enum { + M16_OPC_ADDIUSP = 0x00, + M16_OPC_ADDIUPC = 0x01, + M16_OPC_B = 0x02, + M16_OPC_JAL = 0x03, + M16_OPC_BEQZ = 0x04, + M16_OPC_BNEQZ = 0x05, + M16_OPC_SHIFT = 0x06, + M16_OPC_LD = 0x07, + M16_OPC_RRIA = 0x08, + M16_OPC_ADDIU8 = 0x09, + M16_OPC_SLTI = 0x0a, + M16_OPC_SLTIU = 0x0b, + M16_OPC_I8 = 0x0c, + M16_OPC_LI = 0x0d, + M16_OPC_CMPI = 0x0e, + M16_OPC_SD = 0x0f, + M16_OPC_LB = 0x10, + M16_OPC_LH = 0x11, + M16_OPC_LWSP = 0x12, + M16_OPC_LW = 0x13, + M16_OPC_LBU = 0x14, + M16_OPC_LHU = 0x15, + M16_OPC_LWPC = 0x16, + M16_OPC_LWU = 0x17, + M16_OPC_SB = 0x18, + M16_OPC_SH = 0x19, + M16_OPC_SWSP = 0x1a, + M16_OPC_SW = 0x1b, + M16_OPC_RRR = 0x1c, + M16_OPC_RR = 0x1d, + M16_OPC_EXTEND = 0x1e, + M16_OPC_I64 = 0x1f +}; + +/* I8 funct field */ +enum { + I8_BTEQZ = 0x0, + I8_BTNEZ = 0x1, + I8_SWRASP = 0x2, + I8_ADJSP = 0x3, + I8_SVRS = 0x4, + I8_MOV32R = 0x5, + I8_MOVR32 = 0x7 +}; + +/* RRR f field */ +enum { + RRR_DADDU = 0x0, + RRR_ADDU = 0x1, + RRR_DSUBU = 0x2, + RRR_SUBU = 0x3 +}; + +/* RR funct field */ +enum { + RR_JR = 0x00, + RR_SDBBP = 0x01, + RR_SLT = 0x02, + RR_SLTU = 0x03, + RR_SLLV = 0x04, + RR_BREAK = 0x05, + RR_SRLV = 0x06, + RR_SRAV = 0x07, + RR_DSRL = 0x08, + RR_CMP = 0x0a, + RR_NEG = 0x0b, + RR_AND = 0x0c, + RR_OR = 0x0d, + RR_XOR = 0x0e, + RR_NOT = 0x0f, + RR_MFHI = 0x10, + RR_CNVT = 0x11, + RR_MFLO = 0x12, + RR_DSRA = 0x13, + RR_DSLLV = 0x14, + RR_DSRLV = 0x16, + RR_DSRAV = 0x17, + RR_MULT = 0x18, + RR_MULTU = 0x19, + RR_DIV = 0x1a, + RR_DIVU = 0x1b, + RR_DMULT = 0x1c, + RR_DMULTU = 0x1d, + RR_DDIV = 0x1e, + RR_DDIVU = 0x1f +}; + +/* I64 funct field */ +enum { + I64_LDSP = 0x0, + I64_SDSP = 0x1, + I64_SDRASP = 0x2, + I64_DADJSP = 0x3, + I64_LDPC = 0x4, + I64_DADDIU5 = 0x5, + I64_DADDIUPC = 0x6, + I64_DADDIUSP = 0x7 +}; + +/* RR ry field for CNVT */ +enum { + RR_RY_CNVT_ZEB = 0x0, + RR_RY_CNVT_ZEH = 0x1, + RR_RY_CNVT_ZEW = 0x2, + RR_RY_CNVT_SEB = 0x4, + RR_RY_CNVT_SEH = 0x5, + RR_RY_CNVT_SEW = 0x6, +}; + +static int xlat (int r) +{ + static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + + return map[r]; +} + +static void gen_mips16_save (DisasContext *ctx, + int xsregs, int aregs, + int do_ra, int do_s0, int do_s1, + int framesize) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + int args, astatic; + + switch (aregs) { + case 0: + case 1: + case 2: + case 3: + case 11: + args = 0; + break; + case 4: + case 5: + case 6: + case 7: + args = 1; + break; + case 8: + case 9: + case 10: + args = 2; + break; + case 12: + case 13: + args = 3; + break; + case 14: + args = 4; + break; + default: + generate_exception(ctx, EXCP_RI); + return; + } + + switch (args) { + case 4: + gen_base_offset_addr(ctx, t0, 29, 12); + gen_load_gpr(t1, 7); + op_st_sw(t1, t0, ctx); + /* Fall through */ + case 3: + gen_base_offset_addr(ctx, t0, 29, 8); + gen_load_gpr(t1, 6); + op_st_sw(t1, t0, ctx); + /* Fall through */ + case 2: + gen_base_offset_addr(ctx, t0, 29, 4); + gen_load_gpr(t1, 5); + op_st_sw(t1, t0, ctx); + /* Fall through */ + case 1: + gen_base_offset_addr(ctx, t0, 29, 0); + gen_load_gpr(t1, 4); + op_st_sw(t1, t0, ctx); + } + + gen_load_gpr(t0, 29); + +#define DECR_AND_STORE(reg) do { \ + tcg_gen_subi_tl(t0, t0, 4); \ + gen_load_gpr(t1, reg); \ + op_st_sw(t1, t0, ctx); \ + } while (0) + + if (do_ra) { + DECR_AND_STORE(31); + } + + switch (xsregs) { + case 7: + DECR_AND_STORE(30); + /* Fall through */ + case 6: + DECR_AND_STORE(23); + /* Fall through */ + case 5: + DECR_AND_STORE(22); + /* Fall through */ + case 4: + DECR_AND_STORE(21); + /* Fall through */ + case 3: + DECR_AND_STORE(20); + /* Fall through */ + case 2: + DECR_AND_STORE(19); + /* Fall through */ + case 1: + DECR_AND_STORE(18); + } + + if (do_s1) { + DECR_AND_STORE(17); + } + if (do_s0) { + DECR_AND_STORE(16); + } + + switch (aregs) { + case 0: + case 4: + case 8: + case 12: + case 14: + astatic = 0; + break; + case 1: + case 5: + case 9: + case 13: + astatic = 1; + break; + case 2: + case 6: + case 10: + astatic = 2; + break; + case 3: + case 7: + astatic = 3; + break; + case 11: + astatic = 4; + break; + default: + generate_exception(ctx, EXCP_RI); + return; + } + + if (astatic > 0) { + DECR_AND_STORE(7); + if (astatic > 1) { + DECR_AND_STORE(6); + if (astatic > 2) { + DECR_AND_STORE(5); + if (astatic > 3) { + DECR_AND_STORE(4); + } + } + } + } +#undef DECR_AND_STORE + + tcg_gen_subi_tl(cpu_gpr[29], cpu_gpr[29], framesize); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_mips16_restore (DisasContext *ctx, + int xsregs, int aregs, + int do_ra, int do_s0, int do_s1, + int framesize) +{ + int astatic; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + tcg_gen_addi_tl(t0, cpu_gpr[29], framesize); + +#define DECR_AND_LOAD(reg) do { \ + tcg_gen_subi_tl(t0, t0, 4); \ + op_ld_lw(t1, t0, ctx); \ + gen_store_gpr(t1, reg); \ + } while (0) + + if (do_ra) { + DECR_AND_LOAD(31); + } + + switch (xsregs) { + case 7: + DECR_AND_LOAD(30); + /* Fall through */ + case 6: + DECR_AND_LOAD(23); + /* Fall through */ + case 5: + DECR_AND_LOAD(22); + /* Fall through */ + case 4: + DECR_AND_LOAD(21); + /* Fall through */ + case 3: + DECR_AND_LOAD(20); + /* Fall through */ + case 2: + DECR_AND_LOAD(19); + /* Fall through */ + case 1: + DECR_AND_LOAD(18); + } + + if (do_s1) { + DECR_AND_LOAD(17); + } + if (do_s0) { + DECR_AND_LOAD(16); + } + + switch (aregs) { + case 0: + case 4: + case 8: + case 12: + case 14: + astatic = 0; + break; + case 1: + case 5: + case 9: + case 13: + astatic = 1; + break; + case 2: + case 6: + case 10: + astatic = 2; + break; + case 3: + case 7: + astatic = 3; + break; + case 11: + astatic = 4; + break; + default: + generate_exception(ctx, EXCP_RI); + return; + } + + if (astatic > 0) { + DECR_AND_LOAD(7); + if (astatic > 1) { + DECR_AND_LOAD(6); + if (astatic > 2) { + DECR_AND_LOAD(5); + if (astatic > 3) { + DECR_AND_LOAD(4); + } + } + } + } +#undef DECR_AND_LOAD + + tcg_gen_addi_tl(cpu_gpr[29], cpu_gpr[29], framesize); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_addiupc (DisasContext *ctx, int rx, int imm, + int is_64_bit, int extended) +{ + TCGv t0; + + if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { + generate_exception(ctx, EXCP_RI); + return; + } + + t0 = tcg_temp_new(); + + tcg_gen_movi_tl(t0, pc_relative_pc(ctx)); + tcg_gen_addi_tl(cpu_gpr[rx], t0, imm); + if (!is_64_bit) { + tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); + } + + tcg_temp_free(t0); +} + +#if defined(TARGET_MIPS64) +static void decode_i64_mips16 (CPUState *env, DisasContext *ctx, + int ry, int funct, int16_t offset, + int extended) +{ + switch (funct) { + case I64_LDSP: + check_mips_64(ctx); + offset = extended ? offset : offset << 3; + gen_ld(env, ctx, OPC_LD, ry, 29, offset); + break; + case I64_SDSP: + check_mips_64(ctx); + offset = extended ? offset : offset << 3; + gen_st(ctx, OPC_SD, ry, 29, offset); + break; + case I64_SDRASP: + check_mips_64(ctx); + offset = extended ? offset : (ctx->opcode & 0xff) << 3; + gen_st(ctx, OPC_SD, 31, 29, offset); + break; + case I64_DADJSP: + check_mips_64(ctx); + offset = extended ? offset : ((int8_t)ctx->opcode) << 3; + gen_arith_imm(env, ctx, OPC_DADDIU, 29, 29, offset); + break; + case I64_LDPC: + if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { + generate_exception(ctx, EXCP_RI); + } else { + offset = extended ? offset : offset << 3; + gen_ld(env, ctx, OPC_LDPC, ry, 0, offset); + } + break; + case I64_DADDIU5: + check_mips_64(ctx); + offset = extended ? offset : ((int8_t)(offset << 3)) >> 3; + gen_arith_imm(env, ctx, OPC_DADDIU, ry, ry, offset); + break; + case I64_DADDIUPC: + check_mips_64(ctx); + offset = extended ? offset : offset << 2; + gen_addiupc(ctx, ry, offset, 1, extended); + break; + case I64_DADDIUSP: + check_mips_64(ctx); + offset = extended ? offset : offset << 2; + gen_arith_imm(env, ctx, OPC_DADDIU, ry, 29, offset); + break; + } +} +#endif + +static int decode_extended_mips16_opc (CPUState *env, DisasContext *ctx, + int *is_branch) +{ + int extend = lduw_code(ctx->pc + 2); + int op, rx, ry, funct, sa; + int16_t imm, offset; + + ctx->opcode = (ctx->opcode << 16) | extend; + op = (ctx->opcode >> 11) & 0x1f; + sa = (ctx->opcode >> 22) & 0x1f; + funct = (ctx->opcode >> 8) & 0x7; + rx = xlat((ctx->opcode >> 8) & 0x7); + ry = xlat((ctx->opcode >> 5) & 0x7); + offset = imm = (int16_t) (((ctx->opcode >> 16) & 0x1f) << 11 + | ((ctx->opcode >> 21) & 0x3f) << 5 + | (ctx->opcode & 0x1f)); + + /* The extended opcodes cleverly reuse the opcodes from their 16-bit + counterparts. */ + switch (op) { + case M16_OPC_ADDIUSP: + gen_arith_imm(env, ctx, OPC_ADDIU, rx, 29, imm); + break; + case M16_OPC_ADDIUPC: + gen_addiupc(ctx, rx, imm, 0, 1); + break; + case M16_OPC_B: + gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, offset << 1); + /* No delay slot, so just process as a normal instruction */ + break; + case M16_OPC_BEQZ: + gen_compute_branch(ctx, OPC_BEQ, 4, rx, 0, offset << 1); + /* No delay slot, so just process as a normal instruction */ + break; + case M16_OPC_BNEQZ: + gen_compute_branch(ctx, OPC_BNE, 4, rx, 0, offset << 1); + /* No delay slot, so just process as a normal instruction */ + break; + case M16_OPC_SHIFT: + switch (ctx->opcode & 0x3) { + case 0x0: + gen_shift_imm(env, ctx, OPC_SLL, rx, ry, sa); + break; + case 0x1: +#if defined(TARGET_MIPS64) + check_mips_64(ctx); + gen_shift_imm(env, ctx, OPC_DSLL, rx, ry, sa); +#else + generate_exception(ctx, EXCP_RI); +#endif + break; + case 0x2: + gen_shift_imm(env, ctx, OPC_SRL, rx, ry, sa); + break; + case 0x3: + gen_shift_imm(env, ctx, OPC_SRA, rx, ry, sa); + break; + } + break; +#if defined(TARGET_MIPS64) + case M16_OPC_LD: + check_mips_64(ctx); + gen_ld(env, ctx, OPC_LD, ry, rx, offset); + break; +#endif + case M16_OPC_RRIA: + imm = ctx->opcode & 0xf; + imm = imm | ((ctx->opcode >> 20) & 0x7f) << 4; + imm = imm | ((ctx->opcode >> 16) & 0xf) << 11; + imm = (int16_t) (imm << 1) >> 1; + if ((ctx->opcode >> 4) & 0x1) { +#if defined(TARGET_MIPS64) + check_mips_64(ctx); + gen_arith_imm(env, ctx, OPC_DADDIU, ry, rx, imm); +#else + generate_exception(ctx, EXCP_RI); +#endif + } else { + gen_arith_imm(env, ctx, OPC_ADDIU, ry, rx, imm); + } + break; + case M16_OPC_ADDIU8: + gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm); + break; + case M16_OPC_SLTI: + gen_slt_imm(env, OPC_SLTI, 24, rx, imm); + break; + case M16_OPC_SLTIU: + gen_slt_imm(env, OPC_SLTIU, 24, rx, imm); + break; + case M16_OPC_I8: + switch (funct) { + case I8_BTEQZ: + gen_compute_branch(ctx, OPC_BEQ, 4, 24, 0, offset << 1); + break; + case I8_BTNEZ: + gen_compute_branch(ctx, OPC_BNE, 4, 24, 0, offset << 1); + break; + case I8_SWRASP: + gen_st(ctx, OPC_SW, 31, 29, imm); + break; + case I8_ADJSP: + gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, imm); + break; + case I8_SVRS: + { + int xsregs = (ctx->opcode >> 24) & 0x7; + int aregs = (ctx->opcode >> 16) & 0xf; + int do_ra = (ctx->opcode >> 6) & 0x1; + int do_s0 = (ctx->opcode >> 5) & 0x1; + int do_s1 = (ctx->opcode >> 4) & 0x1; + int framesize = (((ctx->opcode >> 20) & 0xf) << 4 + | (ctx->opcode & 0xf)) << 3; + + if (ctx->opcode & (1 << 7)) { + gen_mips16_save(ctx, xsregs, aregs, + do_ra, do_s0, do_s1, + framesize); + } else { + gen_mips16_restore(ctx, xsregs, aregs, + do_ra, do_s0, do_s1, + framesize); + } + } + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } + break; + case M16_OPC_LI: + tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm); + break; + case M16_OPC_CMPI: + tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm); + break; +#if defined(TARGET_MIPS64) + case M16_OPC_SD: + gen_st(ctx, OPC_SD, ry, rx, offset); + break; +#endif + case M16_OPC_LB: + gen_ld(env, ctx, OPC_LB, ry, rx, offset); + break; + case M16_OPC_LH: + gen_ld(env, ctx, OPC_LH, ry, rx, offset); + break; + case M16_OPC_LWSP: + gen_ld(env, ctx, OPC_LW, rx, 29, offset); + break; + case M16_OPC_LW: + gen_ld(env, ctx, OPC_LW, ry, rx, offset); + break; + case M16_OPC_LBU: + gen_ld(env, ctx, OPC_LBU, ry, rx, offset); + break; + case M16_OPC_LHU: + gen_ld(env, ctx, OPC_LHU, ry, rx, offset); + break; + case M16_OPC_LWPC: + gen_ld(env, ctx, OPC_LWPC, rx, 0, offset); + break; +#if defined(TARGET_MIPS64) + case M16_OPC_LWU: + gen_ld(env, ctx, OPC_LWU, ry, rx, offset); + break; +#endif + case M16_OPC_SB: + gen_st(ctx, OPC_SB, ry, rx, offset); + break; + case M16_OPC_SH: + gen_st(ctx, OPC_SH, ry, rx, offset); + break; + case M16_OPC_SWSP: + gen_st(ctx, OPC_SW, rx, 29, offset); + break; + case M16_OPC_SW: + gen_st(ctx, OPC_SW, ry, rx, offset); + break; +#if defined(TARGET_MIPS64) + case M16_OPC_I64: + decode_i64_mips16(env, ctx, ry, funct, offset, 1); + break; +#endif + default: + generate_exception(ctx, EXCP_RI); + break; + } + + return 4; +} + +static int decode_mips16_opc (CPUState *env, DisasContext *ctx, + int *is_branch) +{ + int rx, ry; + int sa; + int op, cnvt_op, op1, offset; + int funct; + int n_bytes; + + op = (ctx->opcode >> 11) & 0x1f; + sa = (ctx->opcode >> 2) & 0x7; + sa = sa == 0 ? 8 : sa; + rx = xlat((ctx->opcode >> 8) & 0x7); + cnvt_op = (ctx->opcode >> 5) & 0x7; + ry = xlat((ctx->opcode >> 5) & 0x7); + op1 = offset = ctx->opcode & 0x1f; + + n_bytes = 2; + + switch (op) { + case M16_OPC_ADDIUSP: + { + int16_t imm = ((uint8_t) ctx->opcode) << 2; + + gen_arith_imm(env, ctx, OPC_ADDIU, rx, 29, imm); + } + break; + case M16_OPC_ADDIUPC: + gen_addiupc(ctx, rx, ((uint8_t) ctx->opcode) << 2, 0, 0); + break; + case M16_OPC_B: + offset = (ctx->opcode & 0x7ff) << 1; + offset = (int16_t)(offset << 4) >> 4; + gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, offset); + /* No delay slot, so just process as a normal instruction */ + break; + case M16_OPC_JAL: + offset = lduw_code(ctx->pc + 2); + offset = (((ctx->opcode & 0x1f) << 21) + | ((ctx->opcode >> 5) & 0x1f) << 16 + | offset) << 2; + op = ((ctx->opcode >> 10) & 0x1) ? OPC_JALXS : OPC_JALS; + gen_compute_branch(ctx, op, 4, rx, ry, offset); + n_bytes = 4; + *is_branch = 1; + break; + case M16_OPC_BEQZ: + gen_compute_branch(ctx, OPC_BEQ, 2, rx, 0, ((int8_t)ctx->opcode) << 1); + /* No delay slot, so just process as a normal instruction */ + break; + case M16_OPC_BNEQZ: + gen_compute_branch(ctx, OPC_BNE, 2, rx, 0, ((int8_t)ctx->opcode) << 1); + /* No delay slot, so just process as a normal instruction */ + break; + case M16_OPC_SHIFT: + switch (ctx->opcode & 0x3) { + case 0x0: + gen_shift_imm(env, ctx, OPC_SLL, rx, ry, sa); + break; + case 0x1: +#if defined(TARGET_MIPS64) + check_mips_64(ctx); + gen_shift_imm(env, ctx, OPC_DSLL, rx, ry, sa); +#else + generate_exception(ctx, EXCP_RI); +#endif + break; + case 0x2: + gen_shift_imm(env, ctx, OPC_SRL, rx, ry, sa); + break; + case 0x3: + gen_shift_imm(env, ctx, OPC_SRA, rx, ry, sa); + break; + } + break; +#if defined(TARGET_MIPS64) + case M16_OPC_LD: + check_mips_64(ctx); + gen_ld(env, ctx, OPC_LD, ry, rx, offset << 3); + break; +#endif + case M16_OPC_RRIA: + { + int16_t imm = (int8_t)((ctx->opcode & 0xf) << 4) >> 4; + + if ((ctx->opcode >> 4) & 1) { +#if defined(TARGET_MIPS64) + check_mips_64(ctx); + gen_arith_imm(env, ctx, OPC_DADDIU, ry, rx, imm); +#else + generate_exception(ctx, EXCP_RI); +#endif + } else { + gen_arith_imm(env, ctx, OPC_ADDIU, ry, rx, imm); + } + } + break; + case M16_OPC_ADDIU8: + { + int16_t imm = (int8_t) ctx->opcode; + + gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm); + } + break; + case M16_OPC_SLTI: + { + int16_t imm = (uint8_t) ctx->opcode; + + gen_slt_imm(env, OPC_SLTI, 24, rx, imm); + } + break; + case M16_OPC_SLTIU: + { + int16_t imm = (uint8_t) ctx->opcode; + + gen_slt_imm(env, OPC_SLTIU, 24, rx, imm); + } + break; + case M16_OPC_I8: + { + int reg32; + + funct = (ctx->opcode >> 8) & 0x7; + switch (funct) { + case I8_BTEQZ: + gen_compute_branch(ctx, OPC_BEQ, 2, 24, 0, + ((int8_t)ctx->opcode) << 1); + break; + case I8_BTNEZ: + gen_compute_branch(ctx, OPC_BNE, 2, 24, 0, + ((int8_t)ctx->opcode) << 1); + break; + case I8_SWRASP: + gen_st(ctx, OPC_SW, 31, 29, (ctx->opcode & 0xff) << 2); + break; + case I8_ADJSP: + gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, + ((int8_t)ctx->opcode) << 3); + break; + case I8_SVRS: + { + int do_ra = ctx->opcode & (1 << 6); + int do_s0 = ctx->opcode & (1 << 5); + int do_s1 = ctx->opcode & (1 << 4); + int framesize = ctx->opcode & 0xf; + + if (framesize == 0) { + framesize = 128; + } else { + framesize = framesize << 3; + } + + if (ctx->opcode & (1 << 7)) { + gen_mips16_save(ctx, 0, 0, + do_ra, do_s0, do_s1, framesize); + } else { + gen_mips16_restore(ctx, 0, 0, + do_ra, do_s0, do_s1, framesize); + } + } + break; + case I8_MOV32R: + { + int rz = xlat(ctx->opcode & 0x7); + + reg32 = (((ctx->opcode >> 3) & 0x3) << 3) | + ((ctx->opcode >> 5) & 0x7); + gen_arith(env, ctx, OPC_ADDU, reg32, rz, 0); + } + break; + case I8_MOVR32: + reg32 = ctx->opcode & 0x1f; + gen_arith(env, ctx, OPC_ADDU, ry, reg32, 0); + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } + } + break; + case M16_OPC_LI: + { + int16_t imm = (uint8_t) ctx->opcode; + + gen_arith_imm(env, ctx, OPC_ADDIU, rx, 0, imm); + } + break; + case M16_OPC_CMPI: + { + int16_t imm = (uint8_t) ctx->opcode; + + gen_logic_imm(env, OPC_XORI, 24, rx, imm); + } + break; +#if defined(TARGET_MIPS64) + case M16_OPC_SD: + check_mips_64(ctx); + gen_st(ctx, OPC_SD, ry, rx, offset << 3); + break; +#endif + case M16_OPC_LB: + gen_ld(env, ctx, OPC_LB, ry, rx, offset); + break; + case M16_OPC_LH: + gen_ld(env, ctx, OPC_LH, ry, rx, offset << 1); + break; + case M16_OPC_LWSP: + gen_ld(env, ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2); + break; + case M16_OPC_LW: + gen_ld(env, ctx, OPC_LW, ry, rx, offset << 2); + break; + case M16_OPC_LBU: + gen_ld(env, ctx, OPC_LBU, ry, rx, offset); + break; + case M16_OPC_LHU: + gen_ld(env, ctx, OPC_LHU, ry, rx, offset << 1); + break; + case M16_OPC_LWPC: + gen_ld(env, ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2); + break; +#if defined (TARGET_MIPS64) + case M16_OPC_LWU: + check_mips_64(ctx); + gen_ld(env, ctx, OPC_LWU, ry, rx, offset << 2); + break; +#endif + case M16_OPC_SB: + gen_st(ctx, OPC_SB, ry, rx, offset); + break; + case M16_OPC_SH: + gen_st(ctx, OPC_SH, ry, rx, offset << 1); + break; + case M16_OPC_SWSP: + gen_st(ctx, OPC_SW, rx, 29, ((uint8_t)ctx->opcode) << 2); + break; + case M16_OPC_SW: + gen_st(ctx, OPC_SW, ry, rx, offset << 2); + break; + case M16_OPC_RRR: + { + int rz = xlat((ctx->opcode >> 2) & 0x7); + int mips32_op; + + switch (ctx->opcode & 0x3) { + case RRR_ADDU: + mips32_op = OPC_ADDU; + break; + case RRR_SUBU: + mips32_op = OPC_SUBU; + break; +#if defined(TARGET_MIPS64) + case RRR_DADDU: + mips32_op = OPC_DADDU; + check_mips_64(ctx); + break; + case RRR_DSUBU: + mips32_op = OPC_DSUBU; + check_mips_64(ctx); + break; +#endif + default: + generate_exception(ctx, EXCP_RI); + goto done; + } + + gen_arith(env, ctx, mips32_op, rz, rx, ry); + done: + ; + } + break; + case M16_OPC_RR: + switch (op1) { + case RR_JR: + { + int nd = (ctx->opcode >> 7) & 0x1; + int link = (ctx->opcode >> 6) & 0x1; + int ra = (ctx->opcode >> 5) & 0x1; + + if (link) { + op = nd ? OPC_JALRC : OPC_JALRS; + } else { + op = OPC_JR; + } + + gen_compute_branch(ctx, op, 2, ra ? 31 : rx, 31, 0); + if (!nd) { + *is_branch = 1; + } + } + break; + case RR_SDBBP: + /* XXX: not clear which exception should be raised + * when in debug mode... + */ + check_insn(env, ctx, ISA_MIPS32); + if (!(ctx->hflags & MIPS_HFLAG_DM)) { + generate_exception(ctx, EXCP_DBp); + } else { + generate_exception(ctx, EXCP_DBp); + } + break; + case RR_SLT: + gen_slt(env, OPC_SLT, 24, rx, ry); + break; + case RR_SLTU: + gen_slt(env, OPC_SLTU, 24, rx, ry); + break; + case RR_BREAK: + generate_exception(ctx, EXCP_BREAK); + break; + case RR_SLLV: + gen_shift(env, ctx, OPC_SLLV, ry, rx, ry); + break; + case RR_SRLV: + gen_shift(env, ctx, OPC_SRLV, ry, rx, ry); + break; + case RR_SRAV: + gen_shift(env, ctx, OPC_SRAV, ry, rx, ry); + break; +#if defined (TARGET_MIPS64) + case RR_DSRL: + check_mips_64(ctx); + gen_shift_imm(env, ctx, OPC_DSRL, ry, ry, sa); + break; +#endif + case RR_CMP: + gen_logic(env, OPC_XOR, 24, rx, ry); + break; + case RR_NEG: + gen_arith(env, ctx, OPC_SUBU, rx, 0, ry); + break; + case RR_AND: + gen_logic(env, OPC_AND, rx, rx, ry); + break; + case RR_OR: + gen_logic(env, OPC_OR, rx, rx, ry); + break; + case RR_XOR: + gen_logic(env, OPC_XOR, rx, rx, ry); + break; + case RR_NOT: + gen_logic(env, OPC_NOR, rx, ry, 0); + break; + case RR_MFHI: + gen_HILO(ctx, OPC_MFHI, rx); + break; + case RR_CNVT: + switch (cnvt_op) { + case RR_RY_CNVT_ZEB: + tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]); + break; + case RR_RY_CNVT_ZEH: + tcg_gen_ext16u_tl(cpu_gpr[rx], cpu_gpr[rx]); + break; + case RR_RY_CNVT_SEB: + tcg_gen_ext8s_tl(cpu_gpr[rx], cpu_gpr[rx]); + break; + case RR_RY_CNVT_SEH: + tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]); + break; +#if defined (TARGET_MIPS64) + case RR_RY_CNVT_ZEW: + check_mips_64(ctx); + tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); + break; + case RR_RY_CNVT_SEW: + check_mips_64(ctx); + tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); + break; +#endif + default: + generate_exception(ctx, EXCP_RI); + break; + } + break; + case RR_MFLO: + gen_HILO(ctx, OPC_MFLO, rx); + break; +#if defined (TARGET_MIPS64) + case RR_DSRA: + check_mips_64(ctx); + gen_shift_imm(env, ctx, OPC_DSRA, ry, ry, sa); + break; + case RR_DSLLV: + check_mips_64(ctx); + gen_shift(env, ctx, OPC_DSLLV, ry, rx, ry); + break; + case RR_DSRLV: + check_mips_64(ctx); + gen_shift(env, ctx, OPC_DSRLV, ry, rx, ry); + break; + case RR_DSRAV: + check_mips_64(ctx); + gen_shift(env, ctx, OPC_DSRAV, ry, rx, ry); + break; +#endif + case RR_MULT: + gen_muldiv(ctx, OPC_MULT, rx, ry); + break; + case RR_MULTU: + gen_muldiv(ctx, OPC_MULTU, rx, ry); + break; + case RR_DIV: + gen_muldiv(ctx, OPC_DIV, rx, ry); + break; + case RR_DIVU: + gen_muldiv(ctx, OPC_DIVU, rx, ry); + break; +#if defined (TARGET_MIPS64) + case RR_DMULT: + check_mips_64(ctx); + gen_muldiv(ctx, OPC_DMULT, rx, ry); + break; + case RR_DMULTU: + check_mips_64(ctx); + gen_muldiv(ctx, OPC_DMULTU, rx, ry); + break; + case RR_DDIV: + check_mips_64(ctx); + gen_muldiv(ctx, OPC_DDIV, rx, ry); + break; + case RR_DDIVU: + check_mips_64(ctx); + gen_muldiv(ctx, OPC_DDIVU, rx, ry); + break; +#endif + default: + generate_exception(ctx, EXCP_RI); + break; + } + break; + case M16_OPC_EXTEND: + decode_extended_mips16_opc(env, ctx, is_branch); + n_bytes = 4; + break; +#if defined(TARGET_MIPS64) + case M16_OPC_I64: + funct = (ctx->opcode >> 8) & 0x7; + decode_i64_mips16(env, ctx, ry, funct, offset, 0); + break; +#endif + default: + generate_exception(ctx, EXCP_RI); + break; + } + + return n_bytes; +} + +/* microMIPS extension to MIPS32 */ + +/* microMIPS32 major opcodes */ + +enum { + POOL32A = 0x00, + POOL16A = 0x01, + LBU16 = 0x02, + MOVE16 = 0x03, + ADDI32 = 0x04, + LBU32 = 0x05, + SB32 = 0x06, + LB32 = 0x07, + + POOL32B = 0x08, + POOL16B = 0x09, + LHU16 = 0x0a, + ANDI16 = 0x0b, + ADDIU32 = 0x0c, + LHU32 = 0x0d, + SH32 = 0x0e, + LH32 = 0x0f, + + POOL32I = 0x10, + POOL16C = 0x11, + LWSP16 = 0x12, + POOL16D = 0x13, + ORI32 = 0x14, + POOL32F = 0x15, + POOL32S = 0x16, + DADDIU32 = 0x17, + + POOL32C = 0x18, + LWGP16 = 0x19, + LW16 = 0x1a, + POOL16E = 0x1b, + XORI32 = 0x1c, + JALS32 = 0x1d, + ADDIUPC = 0x1e, + POOL48A = 0x1f, + + /* 0x20 is reserved */ + RES_20 = 0x20, + POOL16F = 0x21, + SB16 = 0x22, + BEQZ16 = 0x23, + SLTI32 = 0x24, + BEQ32 = 0x25, + SWC132 = 0x26, + LWC132 = 0x27, + + /* 0x28 and 0x29 are reserved */ + RES_28 = 0x28, + RES_29 = 0x29, + SH16 = 0x2a, + BNEZ16 = 0x2b, + SLTIU32 = 0x2c, + BNE32 = 0x2d, + SDC132 = 0x2e, + LDC132 = 0x2f, + + /* 0x30 and 0x31 are reserved */ + RES_30 = 0x30, + RES_31 = 0x31, + SWSP16 = 0x32, + B16 = 0x33, + ANDI32 = 0x34, + J32 = 0x35, + SD32 = 0x36, + LD32 = 0x37, + + /* 0x38 and 0x39 are reserved */ + RES_38 = 0x38, + RES_39 = 0x39, + SW16 = 0x3a, + LI16 = 0x3b, + JALX32 = 0x3c, + JAL32 = 0x3d, + SW32 = 0x3e, + LW32 = 0x3f +}; + +/* POOL32A encoding of minor opcode field */ + +enum { + /* These opcodes are distinguished only by bits 9..6; those bits are + * what are recorded below. */ + SLL32 = 0x0, + SRL32 = 0x1, + SRA = 0x2, + ROTR = 0x3, + + SLLV = 0x0, + SRLV = 0x1, + SRAV = 0x2, + ROTRV = 0x3, + ADD = 0x4, + ADDU32 = 0x5, + SUB = 0x6, + SUBU32 = 0x7, + MUL = 0x8, + AND = 0x9, + OR32 = 0xa, + NOR = 0xb, + XOR32 = 0xc, + SLT = 0xd, + SLTU = 0xe, + + MOVN = 0x0, + MOVZ = 0x1, + LWXS = 0x4, + + /* The following can be distinguished by their lower 6 bits. */ + INS = 0x0c, + EXT = 0x2c, + POOL32AXF = 0x3c +}; + +/* POOL32AXF encoding of minor opcode field extension */ + +enum { + /* bits 11..6 */ + TEQ = 0x00, + TGE = 0x08, + TGEU = 0x10, + TLT = 0x20, + TLTU = 0x28, + TNE = 0x30, + + MFC0 = 0x03, + MTC0 = 0x0b, + + /* bits 13..12 for 0x01 */ + MFHI_ACC = 0x0, + MFLO_ACC = 0x1, + MTHI_ACC = 0x2, + MTLO_ACC = 0x3, + + /* bits 13..12 for 0x2a */ + MADD_ACC = 0x0, + MADDU_ACC = 0x1, + MSUB_ACC = 0x2, + MSUBU_ACC = 0x3, + + /* bits 13..12 for 0x32 */ + MULT_ACC = 0x0, + MULTU_ACC = 0x0, + + /* bits 15..12 for 0x2c */ + SEB = 0x2, + SEH = 0x3, + CLO = 0x4, + CLZ = 0x5, + RDHWR = 0x6, + WSBH = 0x7, + MULT = 0x8, + MULTU = 0x9, + DIV = 0xa, + DIVU = 0xb, + MADD = 0xc, + MADDU = 0xd, + MSUB = 0xe, + MSUBU = 0xf, + + /* bits 15..12 for 0x34 */ + MFC2 = 0x4, + MTC2 = 0x5, + MFHC2 = 0x8, + MTHC2 = 0x9, + CFC2 = 0xc, + CTC2 = 0xd, + + /* bits 15..12 for 0x3c */ + JALR = 0x0, + JR = 0x0, /* alias */ + JALR_HB = 0x1, + JALRS = 0x4, + JALRS_HB = 0x5, + + /* bits 15..12 for 0x05 */ + RDPGPR = 0xe, + WRPGPR = 0xf, + + /* bits 15..12 for 0x0d */ + TLBP = 0x0, + TLBR = 0x1, + TLBWI = 0x2, + TLBWR = 0x3, + WAIT = 0x9, + IRET = 0xd, + DERET = 0xe, + ERET = 0xf, + + /* bits 15..12 for 0x15 */ + DMT = 0x0, + DVPE = 0x1, + EMT = 0x2, + EVPE = 0x3, + + /* bits 15..12 for 0x1d */ + DI = 0x4, + EI = 0x5, + + /* bits 15..12 for 0x2d */ + SYNC = 0x6, + SYSCALL = 0x8, + SDBBP = 0xd, + + /* bits 15..12 for 0x35 */ + MFHI32 = 0x0, + MFLO32 = 0x1, + MTHI32 = 0x2, + MTLO32 = 0x3, +}; + +/* POOL32B encoding of minor opcode field (bits 15..12) */ + +enum { + LWC2 = 0x0, + LWP = 0x1, + LDP = 0x4, + LWM32 = 0x5, + CACHE = 0x6, + LDM = 0x7, + SWC2 = 0x8, + SWP = 0x9, + SDP = 0xc, + SWM32 = 0xd, + SDM = 0xf +}; + +/* POOL32C encoding of minor opcode field (bits 15..12) */ + +enum { + LWL = 0x0, + SWL = 0x8, + LWR = 0x1, + SWR = 0x9, + PREF = 0x2, + /* 0xa is reserved */ + LL = 0x3, + SC = 0xb, + LDL = 0x4, + SDL = 0xc, + LDR = 0x5, + SDR = 0xd, + /* 0x6 is reserved */ + LWU = 0xe, + LLD = 0x7, + SCD = 0xf +}; + +/* POOL32F encoding of minor opcode field (bits 5..0) */ + +enum { + /* These are the bit 7..6 values */ + ADD_FMT = 0x0, + MOVN_FMT = 0x0, + + SUB_FMT = 0x1, + MOVZ_FMT = 0x1, + + MUL_FMT = 0x2, + + DIV_FMT = 0x3, + + /* These are the bit 8..6 values */ + RSQRT2_FMT = 0x0, + MOVF_FMT = 0x0, + + LWXC1 = 0x1, + MOVT_FMT = 0x1, + + PLL_PS = 0x2, + SWXC1 = 0x2, + + PLU_PS = 0x3, + LDXC1 = 0x3, + + PUL_PS = 0x4, + SDXC1 = 0x4, + RECIP2_FMT = 0x4, + + PUU_PS = 0x5, + LUXC1 = 0x5, + + CVT_PS_S = 0x6, + SUXC1 = 0x6, + ADDR_PS = 0x6, + PREFX = 0x6, + + MULR_PS = 0x7, + + MADD_S = 0x01, + MADD_D = 0x09, + MADD_PS = 0x11, + ALNV_PS = 0x19, + MSUB_S = 0x21, + MSUB_D = 0x29, + MSUB_PS = 0x31, + + NMADD_S = 0x02, + NMADD_D = 0x0a, + NMADD_PS = 0x12, + NMSUB_S = 0x22, + NMSUB_D = 0x2a, + NMSUB_PS = 0x32, + + POOL32FXF = 0x3b, + + CABS_COND_FMT = 0x1c, /* MIPS3D */ + C_COND_FMT = 0x3c +}; + +/* POOL32Fxf encoding of minor opcode extension field */ + +enum { + CVT_L = 0x04, + RSQRT_FMT = 0x08, + FLOOR_L = 0x0c, + CVT_PW_PS = 0x1c, + CVT_W = 0x24, + SQRT_FMT = 0x28, + FLOOR_W = 0x2c, + CVT_PS_PW = 0x3c, + CFC1 = 0x40, + RECIP_FMT = 0x48, + CEIL_L = 0x4c, + CTC1 = 0x60, + CEIL_W = 0x6c, + MFC1 = 0x80, + CVT_S_PL = 0x84, + TRUNC_L = 0x8c, + MTC1 = 0xa0, + CVT_S_PU = 0xa4, + TRUNC_W = 0xac, + MFHC1 = 0xc0, + ROUND_L = 0xcc, + MTHC1 = 0xe0, + ROUND_W = 0xec, + + MOV_FMT = 0x01, + MOVF = 0x05, + ABS_FMT = 0x0d, + RSQRT1_FMT = 0x1d, + MOVT = 0x25, + NEG_FMT = 0x2d, + CVT_D = 0x4d, + RECIP1_FMT = 0x5d, + CVT_S = 0x6d +}; + +/* POOL32I encoding of minor opcode field (bits 25..21) */ + +enum { + BLTZ = 0x00, + BLTZAL = 0x01, + BGEZ = 0x02, + BGEZAL = 0x03, + BLEZ = 0x04, + BNEZC = 0x05, + BGTZ = 0x06, + BEQZC = 0x07, + TLTI = 0x08, + TGEI = 0x09, + TLTIU = 0x0a, + TGEIU = 0x0b, + TNEI = 0x0c, + LUI = 0x0d, + TEQI = 0x0e, + SYNCI = 0x10, + BLTZALS = 0x11, + BGEZALS = 0x13, + BC2F = 0x14, + BC2T = 0x15, + BPOSGE64 = 0x1a, + BPOSGE32 = 0x1b, + /* These overlap and are distinguished by bit16 of the instruction */ + BC1F = 0x1c, + BC1T = 0x1d, + BC1ANY2F = 0x1c, + BC1ANY2T = 0x1d, + BC1ANY4F = 0x1e, + BC1ANY4T = 0x1f +}; + +/* POOL16A encoding of minor opcode field */ + +enum { + ADDU16 = 0x0, + SUBU16 = 0x1 +}; + +/* POOL16B encoding of minor opcode field */ + +enum { + SLL16 = 0x0, + SRL16 = 0x1 +}; + +/* POOL16C encoding of minor opcode field */ + +enum { + NOT16 = 0x00, + XOR16 = 0x04, + AND16 = 0x08, + OR16 = 0x0c, + LWM16 = 0x10, + SWM16 = 0x14, + JR16 = 0x18, + JRC16 = 0x1a, + JALR16 = 0x1c, + JALR16S = 0x1e, + MFHI16 = 0x20, + MFLO16 = 0x24, + BREAK16 = 0x28, + SDBBP16 = 0x2c, + JRADDIUSP = 0x30 +}; + +/* POOL16D encoding of minor opcode field */ + +enum { + ADDIUS5 = 0x0, + ADDIUSP = 0x1 +}; + +/* POOL16E encoding of minor opcode field */ + +enum { + ADDIUR2 = 0x0, + ADDIUR1SP = 0x1 +}; + +static int mmreg (int r) +{ + static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + + return map[r]; +} + +/* Used for 16-bit store instructions. */ +static int mmreg2 (int r) +{ + static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; + + return map[r]; +} + +#define uMIPS_RD(op) ((op >> 7) & 0x7) +#define uMIPS_RS(op) ((op >> 4) & 0x7) +#define uMIPS_RS2(op) uMIPS_RS(op) +#define uMIPS_RS1(op) ((op >> 1) & 0x7) +#define uMIPS_RD5(op) ((op >> 5) & 0x1f) +#define uMIPS_RS5(op) (op & 0x1f) + +/* Signed immediate */ +#define SIMM(op, start, width) \ + ((int32_t)(((op >> start) & ((~0U) >> (32-width))) \ + << (32-width)) \ + >> (32-width)) +/* Zero-extended immediate */ +#define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width))) + +static void gen_addiur1sp (CPUState *env, DisasContext *ctx) +{ + int rd = mmreg(uMIPS_RD(ctx->opcode)); + + gen_arith_imm(env, ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2); +} + +static void gen_addiur2 (CPUState *env, DisasContext *ctx) +{ + static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 }; + int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rs = mmreg(uMIPS_RS(ctx->opcode)); + + gen_arith_imm(env, ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]); +} + +static void gen_addiusp (CPUState *env, DisasContext *ctx) +{ + int encoded = ZIMM(ctx->opcode, 1, 9); + int decoded; + + if (encoded <= 1) { + decoded = 256 + encoded; + } else if (encoded <= 255) { + decoded = encoded; + } else if (encoded <= 509) { + decoded = encoded - 512; + } else { + decoded = encoded - 768; + } + + gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, decoded << 2); +} + +static void gen_addius5 (CPUState *env, DisasContext *ctx) +{ + int imm = SIMM(ctx->opcode, 1, 4); + int rd = (ctx->opcode >> 5) & 0x1f; + + gen_arith_imm(env, ctx, OPC_ADDIU, rd, rd, imm); +} + +static void gen_andi16 (CPUState *env, DisasContext *ctx) +{ + static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16, + 31, 32, 63, 64, 255, 32768, 65535 }; + int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rs = mmreg(uMIPS_RS(ctx->opcode)); + int encoded = ZIMM(ctx->opcode, 0, 4); + + gen_logic_imm(env, OPC_ANDI, rd, rs, decoded_imm[encoded]); +} + +static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, + int base, int16_t offset) +{ + TCGv t0, t1; + TCGv_i32 t2; + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + generate_exception(ctx, EXCP_RI); + return; + } + + t0 = tcg_temp_new(); + + gen_base_offset_addr(ctx, t0, base, offset); + + t1 = tcg_const_tl(reglist); + t2 = tcg_const_i32(ctx->mem_idx); + + save_cpu_state(ctx, 1); + switch (opc) { + case LWM32: + gen_helper_lwm(t0, t1, t2); + break; + case SWM32: + gen_helper_swm(t0, t1, t2); + break; +#ifdef TARGET_MIPS64 + case LDM: + gen_helper_ldm(t0, t1, t2); + break; + case SDM: + gen_helper_sdm(t0, t1, t2); + break; +#endif + } + MIPS_DEBUG("%s, %x, %d(%s)", opn, reglist, offset, regnames[base]); + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free_i32(t2); +} + + +static void gen_pool16c_insn (CPUState *env, DisasContext *ctx, int *is_branch) +{ + int rd = mmreg((ctx->opcode >> 3) & 0x7); + int rs = mmreg(ctx->opcode & 0x7); + int opc; + + switch (((ctx->opcode) >> 4) & 0x3f) { + case NOT16 + 0: + case NOT16 + 1: + case NOT16 + 2: + case NOT16 + 3: + gen_logic(env, OPC_NOR, rd, rs, 0); + break; + case XOR16 + 0: + case XOR16 + 1: + case XOR16 + 2: + case XOR16 + 3: + gen_logic(env, OPC_XOR, rd, rd, rs); + break; + case AND16 + 0: + case AND16 + 1: + case AND16 + 2: + case AND16 + 3: + gen_logic(env, OPC_AND, rd, rd, rs); + break; + case OR16 + 0: + case OR16 + 1: + case OR16 + 2: + case OR16 + 3: + gen_logic(env, OPC_OR, rd, rd, rs); + break; + case LWM16 + 0: + case LWM16 + 1: + case LWM16 + 2: + case LWM16 + 3: + { + static const int lwm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; + int offset = ZIMM(ctx->opcode, 0, 4); + + gen_ldst_multiple(ctx, LWM32, lwm_convert[(ctx->opcode >> 4) & 0x3], + 29, offset << 2); + } + break; + case SWM16 + 0: + case SWM16 + 1: + case SWM16 + 2: + case SWM16 + 3: + { + static const int swm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; + int offset = ZIMM(ctx->opcode, 0, 4); + + gen_ldst_multiple(ctx, SWM32, swm_convert[(ctx->opcode >> 4) & 0x3], + 29, offset << 2); + } + break; + case JR16 + 0: + case JR16 + 1: + { + int reg = ctx->opcode & 0x1f; + + gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0); + } + *is_branch = 1; + break; + case JRC16 + 0: + case JRC16 + 1: + { + int reg = ctx->opcode & 0x1f; + + gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0); + /* Let normal delay slot handling in our caller take us + to the branch target. */ + } + break; + case JALR16 + 0: + case JALR16 + 1: + opc = OPC_JALR; + goto do_jalr; + case JALR16S + 0: + case JALR16S + 1: + opc = OPC_JALRS; + do_jalr: + { + int reg = ctx->opcode & 0x1f; + + gen_compute_branch(ctx, opc, 2, reg, 31, 0); + } + *is_branch = 1; + break; + case MFHI16 + 0: + case MFHI16 + 1: + gen_HILO(ctx, OPC_MFHI, uMIPS_RS5(ctx->opcode)); + break; + case MFLO16 + 0: + case MFLO16 + 1: + gen_HILO(ctx, OPC_MFLO, uMIPS_RS5(ctx->opcode)); + break; + case BREAK16: + generate_exception(ctx, EXCP_BREAK); + break; + case SDBBP16: + /* XXX: not clear which exception should be raised + * when in debug mode... + */ + check_insn(env, ctx, ISA_MIPS32); + if (!(ctx->hflags & MIPS_HFLAG_DM)) { + generate_exception(ctx, EXCP_DBp); + } else { + generate_exception(ctx, EXCP_DBp); + } + break; + case JRADDIUSP + 0: + case JRADDIUSP + 1: + { + int imm = ZIMM(ctx->opcode, 0, 5); + + gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0); + gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, imm << 2); + /* Let normal delay slot handling in our caller take us + to the branch target. */ + } + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } +} + +static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, base); + + if (index != 0) { + gen_load_gpr(t1, index); + tcg_gen_shli_tl(t1, t1, 2); + gen_op_addr_add(ctx, t0, t1, t0); + } + + save_cpu_state(ctx, 0); + op_ld_lw(t1, t0, ctx); + gen_store_gpr(t1, rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, + int base, int16_t offset) +{ + const char *opn = "ldst_pair"; + TCGv t0, t1; + + if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31 || rd == base) { + generate_exception(ctx, EXCP_RI); + return; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + gen_base_offset_addr(ctx, t0, base, offset); + + switch (opc) { + case LWP: + save_cpu_state(ctx, 0); + op_ld_lw(t1, t0, ctx); + gen_store_gpr(t1, rd); + tcg_gen_movi_tl(t1, 4); + gen_op_addr_add(ctx, t0, t0, t1); + op_ld_lw(t1, t0, ctx); + gen_store_gpr(t1, rd+1); + opn = "lwp"; + break; + case SWP: + save_cpu_state(ctx, 0); + gen_load_gpr(t1, rd); + op_st_sw(t1, t0, ctx); + tcg_gen_movi_tl(t1, 4); + gen_op_addr_add(ctx, t0, t0, t1); + gen_load_gpr(t1, rd+1); + op_st_sw(t1, t0, ctx); + opn = "swp"; + break; +#ifdef TARGET_MIPS64 + case LDP: + save_cpu_state(ctx, 0); + op_ld_ld(t1, t0, ctx); + gen_store_gpr(t1, rd); + tcg_gen_movi_tl(t1, 8); + gen_op_addr_add(ctx, t0, t0, t1); + op_ld_ld(t1, t0, ctx); + gen_store_gpr(t1, rd+1); + opn = "ldp"; + break; + case SDP: + save_cpu_state(ctx, 0); + gen_load_gpr(t1, rd); + op_st_sd(t1, t0, ctx); + tcg_gen_movi_tl(t1, 8); + gen_op_addr_add(ctx, t0, t0, t1); + gen_load_gpr(t1, rd+1); + op_st_sd(t1, t0, ctx); + opn = "sdp"; + break; +#endif + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s, %s, %d(%s)", opn, regnames[rd], offset, regnames[base]); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_pool32axf (CPUState *env, DisasContext *ctx, int rt, int rs, + int *is_branch) +{ + int extension = (ctx->opcode >> 6) & 0x3f; + int minor = (ctx->opcode >> 12) & 0xf; + uint32_t mips32_op; + + switch (extension) { + case TEQ: + mips32_op = OPC_TEQ; + goto do_trap; + case TGE: + mips32_op = OPC_TGE; + goto do_trap; + case TGEU: + mips32_op = OPC_TGEU; + goto do_trap; + case TLT: + mips32_op = OPC_TLT; + goto do_trap; + case TLTU: + mips32_op = OPC_TLTU; + goto do_trap; + case TNE: + mips32_op = OPC_TNE; + do_trap: + gen_trap(ctx, mips32_op, rs, rt, -1); + break; +#ifndef CONFIG_USER_ONLY + case MFC0: + case MFC0 + 32: + if (rt == 0) { + /* Treat as NOP. */ + break; + } + gen_mfc0(env, ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); + break; + case MTC0: + case MTC0 + 32: + { + TCGv t0 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_mtc0(env, ctx, t0, rs, (ctx->opcode >> 11) & 0x7); + tcg_temp_free(t0); + } + break; +#endif + case 0x2c: + switch (minor) { + case SEB: + gen_bshfl(ctx, OPC_SEB, rs, rt); + break; + case SEH: + gen_bshfl(ctx, OPC_SEH, rs, rt); + break; + case CLO: + mips32_op = OPC_CLO; + goto do_cl; + case CLZ: + mips32_op = OPC_CLZ; + do_cl: + check_insn(env, ctx, ISA_MIPS32); + gen_cl(ctx, mips32_op, rt, rs); + break; + case RDHWR: + gen_rdhwr(env, ctx, rt, rs); + break; + case WSBH: + gen_bshfl(ctx, OPC_WSBH, rs, rt); + break; + case MULT: + mips32_op = OPC_MULT; + goto do_muldiv; + case MULTU: + mips32_op = OPC_MULTU; + goto do_muldiv; + case DIV: + mips32_op = OPC_DIV; + goto do_muldiv; + case DIVU: + mips32_op = OPC_DIVU; + goto do_muldiv; + case MADD: + mips32_op = OPC_MADD; + goto do_muldiv; + case MADDU: + mips32_op = OPC_MADDU; + goto do_muldiv; + case MSUB: + mips32_op = OPC_MSUB; + goto do_muldiv; + case MSUBU: + mips32_op = OPC_MSUBU; + do_muldiv: + check_insn(env, ctx, ISA_MIPS32); + gen_muldiv(ctx, mips32_op, rs, rt); + break; + default: + goto pool32axf_invalid; + } + break; + case 0x34: + switch (minor) { + case MFC2: + case MTC2: + case MFHC2: + case MTHC2: + case CFC2: + case CTC2: + generate_exception_err(ctx, EXCP_CpU, 2); + break; + default: + goto pool32axf_invalid; + } + break; + case 0x3c: + switch (minor) { + case JALR: + case JALR_HB: + gen_compute_branch (ctx, OPC_JALR, 4, rs, rt, 0); + *is_branch = 1; + break; + case JALRS: + case JALRS_HB: + gen_compute_branch (ctx, OPC_JALRS, 4, rs, rt, 0); + *is_branch = 1; + break; + default: + goto pool32axf_invalid; + } + break; + case 0x05: + switch (minor) { + case RDPGPR: + check_insn(env, ctx, ISA_MIPS32R2); + gen_load_srsgpr(rt, rs); + break; + case WRPGPR: + check_insn(env, ctx, ISA_MIPS32R2); + gen_store_srsgpr(rt, rs); + break; + default: + goto pool32axf_invalid; + } + break; +#ifndef CONFIG_USER_ONLY + case 0x0d: + switch (minor) { + case TLBP: + mips32_op = OPC_TLBP; + goto do_cp0; + case TLBR: + mips32_op = OPC_TLBR; + goto do_cp0; + case TLBWI: + mips32_op = OPC_TLBWI; + goto do_cp0; + case TLBWR: + mips32_op = OPC_TLBWR; + goto do_cp0; + case WAIT: + mips32_op = OPC_WAIT; + goto do_cp0; + case DERET: + mips32_op = OPC_DERET; + goto do_cp0; + case ERET: + mips32_op = OPC_ERET; + do_cp0: + gen_cp0(env, ctx, mips32_op, rt, rs); + break; + default: + goto pool32axf_invalid; + } + break; + case 0x1d: + switch (minor) { + case DI: + { + TCGv t0 = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_helper_di(t0); + gen_store_gpr(t0, rs); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + tcg_temp_free(t0); + } + break; + case EI: + { + TCGv t0 = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_helper_ei(t0); + gen_store_gpr(t0, rs); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + tcg_temp_free(t0); + } + break; + default: + goto pool32axf_invalid; + } + break; +#endif + case 0x2d: + switch (minor) { + case SYNC: + /* NOP */ + break; + case SYSCALL: + generate_exception(ctx, EXCP_SYSCALL); + ctx->bstate = BS_STOP; + break; + case SDBBP: + check_insn(env, ctx, ISA_MIPS32); + if (!(ctx->hflags & MIPS_HFLAG_DM)) { + generate_exception(ctx, EXCP_DBp); + } else { + generate_exception(ctx, EXCP_DBp); + } + break; + default: + goto pool32axf_invalid; + } + break; + case 0x35: + switch (minor) { + case MFHI32: + gen_HILO(ctx, OPC_MFHI, rs); + break; + case MFLO32: + gen_HILO(ctx, OPC_MFLO, rs); + break; + case MTHI32: + gen_HILO(ctx, OPC_MTHI, rs); + break; + case MTLO32: + gen_HILO(ctx, OPC_MTLO, rs); + break; + default: + goto pool32axf_invalid; + } + break; + default: + pool32axf_invalid: + MIPS_INVAL("pool32axf"); + generate_exception(ctx, EXCP_RI); + break; + } +} + +/* Values for microMIPS fmt field. Variable-width, depending on which + formats the instruction supports. */ + +enum { + FMT_SD_S = 0, + FMT_SD_D = 1, + + FMT_SDPS_S = 0, + FMT_SDPS_D = 1, + FMT_SDPS_PS = 2, + + FMT_SWL_S = 0, + FMT_SWL_W = 1, + FMT_SWL_L = 2, + + FMT_DWL_D = 0, + FMT_DWL_W = 1, + FMT_DWL_L = 2 +}; + +static void gen_pool32fxf (CPUState *env, DisasContext *ctx, int rt, int rs) +{ + int extension = (ctx->opcode >> 6) & 0x3ff; + uint32_t mips32_op; + +#define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc +#define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc +#define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc + + switch (extension) { + case FLOAT_1BIT_FMT(CFC1, 0): + mips32_op = OPC_CFC1; + goto do_cp1; + case FLOAT_1BIT_FMT(CTC1, 0): + mips32_op = OPC_CTC1; + goto do_cp1; + case FLOAT_1BIT_FMT(MFC1, 0): + mips32_op = OPC_MFC1; + goto do_cp1; + case FLOAT_1BIT_FMT(MTC1, 0): + mips32_op = OPC_MTC1; + goto do_cp1; + case FLOAT_1BIT_FMT(MFHC1, 0): + mips32_op = OPC_MFHC1; + goto do_cp1; + case FLOAT_1BIT_FMT(MTHC1, 0): + mips32_op = OPC_MTHC1; + do_cp1: + gen_cp1(ctx, mips32_op, rt, rs); + break; + + /* Reciprocal square root */ + case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_S): + mips32_op = OPC_RSQRT_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_D): + mips32_op = OPC_RSQRT_D; + goto do_unaryfp; + + /* Square root */ + case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_S): + mips32_op = OPC_SQRT_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_D): + mips32_op = OPC_SQRT_D; + goto do_unaryfp; + + /* Reciprocal */ + case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_S): + mips32_op = OPC_RECIP_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_D): + mips32_op = OPC_RECIP_D; + goto do_unaryfp; + + /* Floor */ + case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_S): + mips32_op = OPC_FLOOR_L_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_D): + mips32_op = OPC_FLOOR_L_D; + goto do_unaryfp; + case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_S): + mips32_op = OPC_FLOOR_W_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_D): + mips32_op = OPC_FLOOR_W_D; + goto do_unaryfp; + + /* Ceiling */ + case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_S): + mips32_op = OPC_CEIL_L_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_D): + mips32_op = OPC_CEIL_L_D; + goto do_unaryfp; + case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_S): + mips32_op = OPC_CEIL_W_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_D): + mips32_op = OPC_CEIL_W_D; + goto do_unaryfp; + + /* Truncation */ + case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_S): + mips32_op = OPC_TRUNC_L_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_D): + mips32_op = OPC_TRUNC_L_D; + goto do_unaryfp; + case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_S): + mips32_op = OPC_TRUNC_W_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_D): + mips32_op = OPC_TRUNC_W_D; + goto do_unaryfp; + + /* Round */ + case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_S): + mips32_op = OPC_ROUND_L_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_D): + mips32_op = OPC_ROUND_L_D; + goto do_unaryfp; + case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_S): + mips32_op = OPC_ROUND_W_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_D): + mips32_op = OPC_ROUND_W_D; + goto do_unaryfp; + + /* Integer to floating-point conversion */ + case FLOAT_1BIT_FMT(CVT_L, FMT_SD_S): + mips32_op = OPC_CVT_L_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(CVT_L, FMT_SD_D): + mips32_op = OPC_CVT_L_D; + goto do_unaryfp; + case FLOAT_1BIT_FMT(CVT_W, FMT_SD_S): + mips32_op = OPC_CVT_W_S; + goto do_unaryfp; + case FLOAT_1BIT_FMT(CVT_W, FMT_SD_D): + mips32_op = OPC_CVT_W_D; + goto do_unaryfp; + + /* Paired-foo conversions */ + case FLOAT_1BIT_FMT(CVT_S_PL, 0): + mips32_op = OPC_CVT_S_PL; + goto do_unaryfp; + case FLOAT_1BIT_FMT(CVT_S_PU, 0): + mips32_op = OPC_CVT_S_PU; + goto do_unaryfp; + case FLOAT_1BIT_FMT(CVT_PW_PS, 0): + mips32_op = OPC_CVT_PW_PS; + goto do_unaryfp; + case FLOAT_1BIT_FMT(CVT_PS_PW, 0): + mips32_op = OPC_CVT_PS_PW; + goto do_unaryfp; + + /* Floating-point moves */ + case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_S): + mips32_op = OPC_MOV_S; + goto do_unaryfp; + case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_D): + mips32_op = OPC_MOV_D; + goto do_unaryfp; + case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_PS): + mips32_op = OPC_MOV_PS; + goto do_unaryfp; + + /* Absolute value */ + case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_S): + mips32_op = OPC_ABS_S; + goto do_unaryfp; + case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_D): + mips32_op = OPC_ABS_D; + goto do_unaryfp; + case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_PS): + mips32_op = OPC_ABS_PS; + goto do_unaryfp; + + /* Negation */ + case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_S): + mips32_op = OPC_NEG_S; + goto do_unaryfp; + case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_D): + mips32_op = OPC_NEG_D; + goto do_unaryfp; + case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_PS): + mips32_op = OPC_NEG_PS; + goto do_unaryfp; + + /* Reciprocal square root step */ + case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_S): + mips32_op = OPC_RSQRT1_S; + goto do_unaryfp; + case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_D): + mips32_op = OPC_RSQRT1_D; + goto do_unaryfp; + case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_PS): + mips32_op = OPC_RSQRT1_PS; + goto do_unaryfp; + + /* Reciprocal step */ + case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_S): + mips32_op = OPC_RECIP1_S; + goto do_unaryfp; + case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_D): + mips32_op = OPC_RECIP1_S; + goto do_unaryfp; + case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_PS): + mips32_op = OPC_RECIP1_PS; + goto do_unaryfp; + + /* Conversions from double */ + case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_S): + mips32_op = OPC_CVT_D_S; + goto do_unaryfp; + case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_W): + mips32_op = OPC_CVT_D_W; + goto do_unaryfp; + case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_L): + mips32_op = OPC_CVT_D_L; + goto do_unaryfp; + + /* Conversions from single */ + case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_D): + mips32_op = OPC_CVT_S_D; + goto do_unaryfp; + case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_W): + mips32_op = OPC_CVT_S_W; + goto do_unaryfp; + case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_L): + mips32_op = OPC_CVT_S_L; + do_unaryfp: + gen_farith(ctx, mips32_op, -1, rs, rt, 0); + break; + + /* Conditional moves on floating-point codes */ + case COND_FLOAT_MOV(MOVT, 0): + case COND_FLOAT_MOV(MOVT, 1): + case COND_FLOAT_MOV(MOVT, 2): + case COND_FLOAT_MOV(MOVT, 3): + case COND_FLOAT_MOV(MOVT, 4): + case COND_FLOAT_MOV(MOVT, 5): + case COND_FLOAT_MOV(MOVT, 6): + case COND_FLOAT_MOV(MOVT, 7): + gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1); + break; + case COND_FLOAT_MOV(MOVF, 0): + case COND_FLOAT_MOV(MOVF, 1): + case COND_FLOAT_MOV(MOVF, 2): + case COND_FLOAT_MOV(MOVF, 3): + case COND_FLOAT_MOV(MOVF, 4): + case COND_FLOAT_MOV(MOVF, 5): + case COND_FLOAT_MOV(MOVF, 6): + case COND_FLOAT_MOV(MOVF, 7): + gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0); + break; + default: + MIPS_INVAL("pool32fxf"); + generate_exception(ctx, EXCP_RI); + break; + } +} + +static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, + uint16_t insn_hw1, int *is_branch) +{ + int32_t offset; + uint16_t insn; + int rt, rs, rd, rr; + int16_t imm; + uint32_t op, minor, mips32_op; + uint32_t cond, fmt, cc; + + insn = lduw_code(ctx->pc + 2); + ctx->opcode = (ctx->opcode << 16) | insn; + + rt = (ctx->opcode >> 21) & 0x1f; + rs = (ctx->opcode >> 16) & 0x1f; + rd = (ctx->opcode >> 11) & 0x1f; + rr = (ctx->opcode >> 6) & 0x1f; + imm = (int16_t) ctx->opcode; + + op = (ctx->opcode >> 26) & 0x3f; + switch (op) { + case POOL32A: + minor = ctx->opcode & 0x3f; + switch (minor) { + case 0x00: + minor = (ctx->opcode >> 6) & 0xf; + switch (minor) { + case SLL32: + mips32_op = OPC_SLL; + goto do_shifti; + case SRA: + mips32_op = OPC_SRA; + goto do_shifti; + case SRL32: + mips32_op = OPC_SRL; + goto do_shifti; + case ROTR: + mips32_op = OPC_ROTR; + do_shifti: + gen_shift_imm(env, ctx, mips32_op, rt, rs, rd); + break; + default: + goto pool32a_invalid; + } + break; + case 0x10: + minor = (ctx->opcode >> 6) & 0xf; + switch (minor) { + /* Arithmetic */ + case ADD: + mips32_op = OPC_ADD; + goto do_arith; + case ADDU32: + mips32_op = OPC_ADDU; + goto do_arith; + case SUB: + mips32_op = OPC_SUB; + goto do_arith; + case SUBU32: + mips32_op = OPC_SUBU; + goto do_arith; + case MUL: + mips32_op = OPC_MUL; + do_arith: + gen_arith(env, ctx, mips32_op, rd, rs, rt); + break; + /* Shifts */ + case SLLV: + mips32_op = OPC_SLLV; + goto do_shift; + case SRLV: + mips32_op = OPC_SRLV; + goto do_shift; + case SRAV: + mips32_op = OPC_SRAV; + goto do_shift; + case ROTRV: + mips32_op = OPC_ROTRV; + do_shift: + gen_shift(env, ctx, mips32_op, rd, rs, rt); + break; + /* Logical operations */ + case AND: + mips32_op = OPC_AND; + goto do_logic; + case OR32: + mips32_op = OPC_OR; + goto do_logic; + case NOR: + mips32_op = OPC_NOR; + goto do_logic; + case XOR32: + mips32_op = OPC_XOR; + do_logic: + gen_logic(env, mips32_op, rd, rs, rt); + break; + /* Set less than */ + case SLT: + mips32_op = OPC_SLT; + goto do_slt; + case SLTU: + mips32_op = OPC_SLTU; + do_slt: + gen_slt(env, mips32_op, rd, rs, rt); + break; + default: + goto pool32a_invalid; + } + break; + case 0x18: + minor = (ctx->opcode >> 6) & 0xf; + switch (minor) { + /* Conditional moves */ + case MOVN: + mips32_op = OPC_MOVN; + goto do_cmov; + case MOVZ: + mips32_op = OPC_MOVZ; + do_cmov: + gen_cond_move(env, mips32_op, rd, rs, rt); + break; + case LWXS: + gen_ldxs(ctx, rs, rt, rd); + break; + default: + goto pool32a_invalid; + } + break; + case INS: + gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); + return; + case EXT: + gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd); + return; + case POOL32AXF: + gen_pool32axf(env, ctx, rt, rs, is_branch); + break; + case 0x07: + generate_exception(ctx, EXCP_BREAK); + break; + default: + pool32a_invalid: + MIPS_INVAL("pool32a"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case POOL32B: + minor = (ctx->opcode >> 12) & 0xf; + switch (minor) { + case CACHE: + /* Treat as no-op. */ + break; + case LWC2: + case SWC2: + /* COP2: Not implemented. */ + generate_exception_err(ctx, EXCP_CpU, 2); + break; + case LWP: + case SWP: +#ifdef TARGET_MIPS64 + case LDP: + case SDP: +#endif + gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); + break; + case LWM32: + case SWM32: +#ifdef TARGET_MIPS64 + case LDM: + case SDM: +#endif + gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); + break; + default: + MIPS_INVAL("pool32b"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case POOL32F: + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + minor = ctx->opcode & 0x3f; + check_cp1_enabled(ctx); + switch (minor) { + case ALNV_PS: + mips32_op = OPC_ALNV_PS; + goto do_madd; + case MADD_S: + mips32_op = OPC_MADD_S; + goto do_madd; + case MADD_D: + mips32_op = OPC_MADD_D; + goto do_madd; + case MADD_PS: + mips32_op = OPC_MADD_PS; + goto do_madd; + case MSUB_S: + mips32_op = OPC_MSUB_S; + goto do_madd; + case MSUB_D: + mips32_op = OPC_MSUB_D; + goto do_madd; + case MSUB_PS: + mips32_op = OPC_MSUB_PS; + goto do_madd; + case NMADD_S: + mips32_op = OPC_NMADD_S; + goto do_madd; + case NMADD_D: + mips32_op = OPC_NMADD_D; + goto do_madd; + case NMADD_PS: + mips32_op = OPC_NMADD_PS; + goto do_madd; + case NMSUB_S: + mips32_op = OPC_NMSUB_S; + goto do_madd; + case NMSUB_D: + mips32_op = OPC_NMSUB_D; + goto do_madd; + case NMSUB_PS: + mips32_op = OPC_NMSUB_PS; + do_madd: + gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt); + break; + case CABS_COND_FMT: + cond = (ctx->opcode >> 6) & 0xf; + cc = (ctx->opcode >> 13) & 0x7; + fmt = (ctx->opcode >> 10) & 0x3; + switch (fmt) { + case 0x0: + gen_cmpabs_s(ctx, cond, rt, rs, cc); + break; + case 0x1: + gen_cmpabs_d(ctx, cond, rt, rs, cc); + break; + case 0x2: + gen_cmpabs_ps(ctx, cond, rt, rs, cc); + break; + default: + goto pool32f_invalid; + } + break; + case C_COND_FMT: + cond = (ctx->opcode >> 6) & 0xf; + cc = (ctx->opcode >> 13) & 0x7; + fmt = (ctx->opcode >> 10) & 0x3; + switch (fmt) { + case 0x0: + gen_cmp_s(ctx, cond, rt, rs, cc); + break; + case 0x1: + gen_cmp_d(ctx, cond, rt, rs, cc); + break; + case 0x2: + gen_cmp_ps(ctx, cond, rt, rs, cc); + break; + default: + goto pool32f_invalid; + } + break; + case POOL32FXF: + gen_pool32fxf(env, ctx, rt, rs); + break; + case 0x00: + /* PLL foo */ + switch ((ctx->opcode >> 6) & 0x7) { + case PLL_PS: + mips32_op = OPC_PLL_PS; + goto do_ps; + case PLU_PS: + mips32_op = OPC_PLU_PS; + goto do_ps; + case PUL_PS: + mips32_op = OPC_PUL_PS; + goto do_ps; + case PUU_PS: + mips32_op = OPC_PUU_PS; + goto do_ps; + case CVT_PS_S: + mips32_op = OPC_CVT_PS_S; + do_ps: + gen_farith(ctx, mips32_op, rt, rs, rd, 0); + break; + default: + goto pool32f_invalid; + } + break; + case 0x08: + /* [LS][WDU]XC1 */ + switch ((ctx->opcode >> 6) & 0x7) { + case LWXC1: + mips32_op = OPC_LWXC1; + goto do_ldst_cp1; + case SWXC1: + mips32_op = OPC_SWXC1; + goto do_ldst_cp1; + case LDXC1: + mips32_op = OPC_LDXC1; + goto do_ldst_cp1; + case SDXC1: + mips32_op = OPC_SDXC1; + goto do_ldst_cp1; + case LUXC1: + mips32_op = OPC_LUXC1; + goto do_ldst_cp1; + case SUXC1: + mips32_op = OPC_SUXC1; + do_ldst_cp1: + gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs); + break; + default: + goto pool32f_invalid; + } + break; + case 0x18: + /* 3D insns */ + fmt = (ctx->opcode >> 9) & 0x3; + switch ((ctx->opcode >> 6) & 0x7) { + case RSQRT2_FMT: + switch (fmt) { + case FMT_SDPS_S: + mips32_op = OPC_RSQRT2_S; + goto do_3d; + case FMT_SDPS_D: + mips32_op = OPC_RSQRT2_D; + goto do_3d; + case FMT_SDPS_PS: + mips32_op = OPC_RSQRT2_PS; + goto do_3d; + default: + goto pool32f_invalid; + } + break; + case RECIP2_FMT: + switch (fmt) { + case FMT_SDPS_S: + mips32_op = OPC_RECIP2_S; + goto do_3d; + case FMT_SDPS_D: + mips32_op = OPC_RECIP2_D; + goto do_3d; + case FMT_SDPS_PS: + mips32_op = OPC_RECIP2_PS; + goto do_3d; + default: + goto pool32f_invalid; + } + break; + case ADDR_PS: + mips32_op = OPC_ADDR_PS; + goto do_3d; + case MULR_PS: + mips32_op = OPC_MULR_PS; + do_3d: + gen_farith(ctx, mips32_op, rt, rs, rd, 0); + break; + default: + goto pool32f_invalid; + } + break; + case 0x20: + /* MOV[FT].fmt and PREFX */ + cc = (ctx->opcode >> 13) & 0x7; + fmt = (ctx->opcode >> 9) & 0x3; + switch ((ctx->opcode >> 6) & 0x7) { + case MOVF_FMT: + switch (fmt) { + case FMT_SDPS_S: + gen_movcf_s(rs, rt, cc, 0); + break; + case FMT_SDPS_D: + gen_movcf_d(ctx, rs, rt, cc, 0); + break; + case FMT_SDPS_PS: + gen_movcf_ps(rs, rt, cc, 0); + break; + default: + goto pool32f_invalid; + } + break; + case MOVT_FMT: + switch (fmt) { + case FMT_SDPS_S: + gen_movcf_s(rs, rt, cc, 1); + break; + case FMT_SDPS_D: + gen_movcf_d(ctx, rs, rt, cc, 1); + break; + case FMT_SDPS_PS: + gen_movcf_ps(rs, rt, cc, 1); + break; + default: + goto pool32f_invalid; + } + break; + case PREFX: + break; + default: + goto pool32f_invalid; + } + break; +#define FINSN_3ARG_SDPS(prfx) \ + switch ((ctx->opcode >> 8) & 0x3) { \ + case FMT_SDPS_S: \ + mips32_op = OPC_##prfx##_S; \ + goto do_fpop; \ + case FMT_SDPS_D: \ + mips32_op = OPC_##prfx##_D; \ + goto do_fpop; \ + case FMT_SDPS_PS: \ + mips32_op = OPC_##prfx##_PS; \ + goto do_fpop; \ + default: \ + goto pool32f_invalid; \ + } + case 0x30: + /* regular FP ops */ + switch ((ctx->opcode >> 6) & 0x3) { + case ADD_FMT: + FINSN_3ARG_SDPS(ADD); + break; + case SUB_FMT: + FINSN_3ARG_SDPS(SUB); + break; + case MUL_FMT: + FINSN_3ARG_SDPS(MUL); + break; + case DIV_FMT: + fmt = (ctx->opcode >> 8) & 0x3; + if (fmt == 1) { + mips32_op = OPC_DIV_D; + } else if (fmt == 0) { + mips32_op = OPC_DIV_S; + } else { + goto pool32f_invalid; + } + goto do_fpop; + default: + goto pool32f_invalid; + } + break; + case 0x38: + /* cmovs */ + switch ((ctx->opcode >> 6) & 0x3) { + case MOVN_FMT: + FINSN_3ARG_SDPS(MOVN); + break; + case MOVZ_FMT: + FINSN_3ARG_SDPS(MOVZ); + break; + default: + goto pool32f_invalid; + } + break; + do_fpop: + gen_farith(ctx, mips32_op, rt, rs, rd, 0); + break; + default: + pool32f_invalid: + MIPS_INVAL("pool32f"); + generate_exception(ctx, EXCP_RI); + break; + } + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + case POOL32I: + minor = (ctx->opcode >> 21) & 0x1f; + switch (minor) { + case BLTZ: + mips32_op = OPC_BLTZ; + goto do_branch; + case BLTZAL: + mips32_op = OPC_BLTZAL; + goto do_branch; + case BLTZALS: + mips32_op = OPC_BLTZALS; + goto do_branch; + case BGEZ: + mips32_op = OPC_BGEZ; + goto do_branch; + case BGEZAL: + mips32_op = OPC_BGEZAL; + goto do_branch; + case BGEZALS: + mips32_op = OPC_BGEZALS; + goto do_branch; + case BLEZ: + mips32_op = OPC_BLEZ; + goto do_branch; + case BGTZ: + mips32_op = OPC_BGTZ; + do_branch: + gen_compute_branch(ctx, mips32_op, 4, rs, -1, imm << 1); + *is_branch = 1; + break; + + /* Traps */ + case TLTI: + mips32_op = OPC_TLTI; + goto do_trapi; + case TGEI: + mips32_op = OPC_TGEI; + goto do_trapi; + case TLTIU: + mips32_op = OPC_TLTIU; + goto do_trapi; + case TGEIU: + mips32_op = OPC_TGEIU; + goto do_trapi; + case TNEI: + mips32_op = OPC_TNEI; + goto do_trapi; + case TEQI: + mips32_op = OPC_TEQI; + do_trapi: + gen_trap(ctx, mips32_op, rs, -1, imm); + break; + + case BNEZC: + case BEQZC: + gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ, + 4, rs, 0, imm << 1); + /* Compact branches don't have a delay slot, so just let + the normal delay slot handling take us to the branch + target. */ + break; + case LUI: + gen_logic_imm(env, OPC_LUI, rs, -1, imm); + break; + case SYNCI: + break; + case BC2F: + case BC2T: + /* COP2: Not implemented. */ + generate_exception_err(ctx, EXCP_CpU, 2); + break; + case BC1F: + mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F; + goto do_cp1branch; + case BC1T: + mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T; + goto do_cp1branch; + case BC1ANY4F: + mips32_op = OPC_BC1FANY4; + goto do_cp1mips3d; + case BC1ANY4T: + mips32_op = OPC_BC1TANY4; + do_cp1mips3d: + check_cop1x(ctx); + check_insn(env, ctx, ASE_MIPS3D); + /* Fall through */ + do_cp1branch: + gen_compute_branch1(env, ctx, mips32_op, + (ctx->opcode >> 18) & 0x7, imm << 1); + *is_branch = 1; + break; + case BPOSGE64: + case BPOSGE32: + /* MIPS DSP: not implemented */ + /* Fall through */ + default: + MIPS_INVAL("pool32i"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case POOL32C: + minor = (ctx->opcode >> 12) & 0xf; + switch (minor) { + case LWL: + mips32_op = OPC_LWL; + goto do_ld_lr; + case SWL: + mips32_op = OPC_SWL; + goto do_st_lr; + case LWR: + mips32_op = OPC_LWR; + goto do_ld_lr; + case SWR: + mips32_op = OPC_SWR; + goto do_st_lr; +#if defined(TARGET_MIPS64) + case LDL: + mips32_op = OPC_LDL; + goto do_ld_lr; + case SDL: + mips32_op = OPC_SDL; + goto do_st_lr; + case LDR: + mips32_op = OPC_LDR; + goto do_ld_lr; + case SDR: + mips32_op = OPC_SDR; + goto do_st_lr; + case LWU: + mips32_op = OPC_LWU; + goto do_ld_lr; + case LLD: + mips32_op = OPC_LLD; + goto do_ld_lr; +#endif + case LL: + mips32_op = OPC_LL; + goto do_ld_lr; + do_ld_lr: + gen_ld(env, ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); + break; + do_st_lr: + gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); + break; + case SC: + gen_st_cond(ctx, OPC_SC, rt, rs, SIMM(ctx->opcode, 0, 12)); + break; +#if defined(TARGET_MIPS64) + case SCD: + gen_st_cond(ctx, OPC_SCD, rt, rs, SIMM(ctx->opcode, 0, 12)); + break; +#endif + case PREF: + /* Treat as no-op */ + break; + default: + MIPS_INVAL("pool32c"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case ADDI32: + mips32_op = OPC_ADDI; + goto do_addi; + case ADDIU32: + mips32_op = OPC_ADDIU; + do_addi: + gen_arith_imm(env, ctx, mips32_op, rt, rs, imm); + break; + + /* Logical operations */ + case ORI32: + mips32_op = OPC_ORI; + goto do_logici; + case XORI32: + mips32_op = OPC_XORI; + goto do_logici; + case ANDI32: + mips32_op = OPC_ANDI; + do_logici: + gen_logic_imm(env, mips32_op, rt, rs, imm); + break; + + /* Set less than immediate */ + case SLTI32: + mips32_op = OPC_SLTI; + goto do_slti; + case SLTIU32: + mips32_op = OPC_SLTIU; + do_slti: + gen_slt_imm(env, mips32_op, rt, rs, imm); + break; + case JALX32: + offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; + gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset); + *is_branch = 1; + break; + case JALS32: + offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 1; + gen_compute_branch(ctx, OPC_JALS, 4, rt, rs, offset); + *is_branch = 1; + break; + case BEQ32: + gen_compute_branch(ctx, OPC_BEQ, 4, rt, rs, imm << 1); + *is_branch = 1; + break; + case BNE32: + gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1); + *is_branch = 1; + break; + case J32: + gen_compute_branch(ctx, OPC_J, 4, rt, rs, + (int32_t)(ctx->opcode & 0x3FFFFFF) << 1); + *is_branch = 1; + break; + case JAL32: + gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, + (int32_t)(ctx->opcode & 0x3FFFFFF) << 1); + *is_branch = 1; + break; + /* Floating point (COP1) */ + case LWC132: + mips32_op = OPC_LWC1; + goto do_cop1; + case LDC132: + mips32_op = OPC_LDC1; + goto do_cop1; + case SWC132: + mips32_op = OPC_SWC1; + goto do_cop1; + case SDC132: + mips32_op = OPC_SDC1; + do_cop1: + gen_cop1_ldst(env, ctx, mips32_op, rt, rs, imm); + break; + case ADDIUPC: + { + int reg = mmreg(ZIMM(ctx->opcode, 23, 3)); + int offset = SIMM(ctx->opcode, 0, 23) << 2; + + gen_addiupc(ctx, reg, offset, 0, 0); + } + break; + /* Loads and stores */ + case LB32: + mips32_op = OPC_LB; + goto do_ld; + case LBU32: + mips32_op = OPC_LBU; + goto do_ld; + case LH32: + mips32_op = OPC_LH; + goto do_ld; + case LHU32: + mips32_op = OPC_LHU; + goto do_ld; + case LW32: + mips32_op = OPC_LW; + goto do_ld; +#ifdef TARGET_MIPS64 + case LD32: + mips32_op = OPC_LD; + goto do_ld; + case SD32: + mips32_op = OPC_SD; + goto do_st; +#endif + case SB32: + mips32_op = OPC_SB; + goto do_st; + case SH32: + mips32_op = OPC_SH; + goto do_st; + case SW32: + mips32_op = OPC_SW; + goto do_st; + do_ld: + gen_ld(env, ctx, mips32_op, rt, rs, imm); + break; + do_st: + gen_st(ctx, mips32_op, rt, rs, imm); + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } +} + +static int decode_micromips_opc (CPUState *env, DisasContext *ctx, int *is_branch) +{ + uint32_t op; + + /* make sure instructions are on a halfword boundary */ + if (ctx->pc & 0x1) { + env->CP0_BadVAddr = ctx->pc; + generate_exception(ctx, EXCP_AdEL); + ctx->bstate = BS_STOP; + return 2; + } + + op = (ctx->opcode >> 10) & 0x3f; + /* Enforce properly-sized instructions in a delay slot */ + if (ctx->hflags & MIPS_HFLAG_BMASK) { + int bits = ctx->hflags & MIPS_HFLAG_BMASK_EXT; + + switch (op) { + case POOL32A: + case POOL32B: + case POOL32I: + case POOL32C: + case ADDI32: + case ADDIU32: + case ORI32: + case XORI32: + case SLTI32: + case SLTIU32: + case ANDI32: + case JALX32: + case LBU32: + case LHU32: + case POOL32F: + case JALS32: + case BEQ32: + case BNE32: + case J32: + case JAL32: + case SB32: + case SH32: + case POOL32S: + case ADDIUPC: + case SWC132: + case SDC132: + case SD32: + case SW32: + case LB32: + case LH32: + case DADDIU32: + case POOL48A: /* ??? */ + case LWC132: + case LDC132: + case LD32: + case LW32: + if (bits & MIPS_HFLAG_BDS16) { + generate_exception(ctx, EXCP_RI); + /* Just stop translation; the user is confused. */ + ctx->bstate = BS_STOP; + return 2; + } + break; + case POOL16A: + case POOL16B: + case POOL16C: + case LWGP16: + case POOL16F: + case LBU16: + case LHU16: + case LWSP16: + case LW16: + case SB16: + case SH16: + case SWSP16: + case SW16: + case MOVE16: + case ANDI16: + case POOL16D: + case POOL16E: + case BEQZ16: + case BNEZ16: + case B16: + case LI16: + if (bits & MIPS_HFLAG_BDS32) { + generate_exception(ctx, EXCP_RI); + /* Just stop translation; the user is confused. */ + ctx->bstate = BS_STOP; + return 2; + } + break; + default: + break; + } + } + switch (op) { + case POOL16A: + { + int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rs1 = mmreg(uMIPS_RS1(ctx->opcode)); + int rs2 = mmreg(uMIPS_RS2(ctx->opcode)); + uint32_t opc = 0; + + switch (ctx->opcode & 0x1) { + case ADDU16: + opc = OPC_ADDU; + break; + case SUBU16: + opc = OPC_SUBU; + break; + } + + gen_arith(env, ctx, opc, rd, rs1, rs2); + } + break; + case POOL16B: + { + int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rs = mmreg(uMIPS_RS(ctx->opcode)); + int amount = (ctx->opcode >> 1) & 0x7; + uint32_t opc = 0; + amount = amount == 0 ? 8 : amount; + + switch (ctx->opcode & 0x1) { + case SLL16: + opc = OPC_SLL; + break; + case SRL16: + opc = OPC_SRL; + break; + } + + gen_shift_imm(env, ctx, opc, rd, rs, amount); + } + break; + case POOL16C: + gen_pool16c_insn(env, ctx, is_branch); + break; + case LWGP16: + { + int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rb = 28; /* GP */ + int16_t offset = SIMM(ctx->opcode, 0, 7) << 2; + + gen_ld(env, ctx, OPC_LW, rd, rb, offset); + } + break; + case POOL16F: + if (ctx->opcode & 1) { + generate_exception(ctx, EXCP_RI); + } else { + /* MOVEP */ + int enc_dest = uMIPS_RD(ctx->opcode); + int enc_rt = uMIPS_RS2(ctx->opcode); + int enc_rs = uMIPS_RS1(ctx->opcode); + int rd, rs, re, rt; + static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 }; + static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 }; + static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 }; + + rd = rd_enc[enc_dest]; + re = re_enc[enc_dest]; + rs = rs_rt_enc[enc_rs]; + rt = rs_rt_enc[enc_rt]; + + gen_arith_imm(env, ctx, OPC_ADDIU, rd, rs, 0); + gen_arith_imm(env, ctx, OPC_ADDIU, re, rt, 0); + } + break; + case LBU16: + { + int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rb = mmreg(uMIPS_RS(ctx->opcode)); + int16_t offset = ZIMM(ctx->opcode, 0, 4); + offset = (offset == 0xf ? -1 : offset); + + gen_ld(env, ctx, OPC_LBU, rd, rb, offset); + } + break; + case LHU16: + { + int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rb = mmreg(uMIPS_RS(ctx->opcode)); + int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; + + gen_ld(env, ctx, OPC_LHU, rd, rb, offset); + } + break; + case LWSP16: + { + int rd = (ctx->opcode >> 5) & 0x1f; + int rb = 29; /* SP */ + int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; + + gen_ld(env, ctx, OPC_LW, rd, rb, offset); + } + break; + case LW16: + { + int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rb = mmreg(uMIPS_RS(ctx->opcode)); + int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; + + gen_ld(env, ctx, OPC_LW, rd, rb, offset); + } + break; + case SB16: + { + int rd = mmreg2(uMIPS_RD(ctx->opcode)); + int rb = mmreg(uMIPS_RS(ctx->opcode)); + int16_t offset = ZIMM(ctx->opcode, 0, 4); + + gen_st(ctx, OPC_SB, rd, rb, offset); + } + break; + case SH16: + { + int rd = mmreg2(uMIPS_RD(ctx->opcode)); + int rb = mmreg(uMIPS_RS(ctx->opcode)); + int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; + + gen_st(ctx, OPC_SH, rd, rb, offset); + } + break; + case SWSP16: + { + int rd = (ctx->opcode >> 5) & 0x1f; + int rb = 29; /* SP */ + int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; + + gen_st(ctx, OPC_SW, rd, rb, offset); + } + break; + case SW16: + { + int rd = mmreg2(uMIPS_RD(ctx->opcode)); + int rb = mmreg(uMIPS_RS(ctx->opcode)); + int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; + + gen_st(ctx, OPC_SW, rd, rb, offset); + } + break; + case MOVE16: + { + int rd = uMIPS_RD5(ctx->opcode); + int rs = uMIPS_RS5(ctx->opcode); + + gen_arith_imm(env, ctx, OPC_ADDIU, rd, rs, 0); + } + break; + case ANDI16: + gen_andi16(env, ctx); + break; + case POOL16D: + switch (ctx->opcode & 0x1) { + case ADDIUS5: + gen_addius5(env, ctx); + break; + case ADDIUSP: + gen_addiusp(env, ctx); + break; + } + break; + case POOL16E: + switch (ctx->opcode & 0x1) { + case ADDIUR2: + gen_addiur2(env, ctx); + break; + case ADDIUR1SP: + gen_addiur1sp(env, ctx); + break; + } + break; + case B16: + gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, + SIMM(ctx->opcode, 0, 10) << 1); + *is_branch = 1; + break; + case BNEZ16: + case BEQZ16: + gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2, + mmreg(uMIPS_RD(ctx->opcode)), + 0, SIMM(ctx->opcode, 0, 7) << 1); + *is_branch = 1; + break; + case LI16: + { + int reg = mmreg(uMIPS_RD(ctx->opcode)); + int imm = ZIMM(ctx->opcode, 0, 7); + + imm = (imm == 0x7f ? -1 : imm); + tcg_gen_movi_tl(cpu_gpr[reg], imm); + } + break; + case RES_20: + case RES_28: + case RES_29: + case RES_30: + case RES_31: + case RES_38: + case RES_39: + generate_exception(ctx, EXCP_RI); + break; + default: + decode_micromips32_opc (env, ctx, op, is_branch); + return 4; + } + + return 2; +} + +/* SmartMIPS extension to MIPS32 */ + +#if defined(TARGET_MIPS64) + +/* MDMX extension to MIPS64 */ + +#endif + +static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch) +{ + int32_t offset; + int rs, rt, rd, sa; + uint32_t op, op1, op2; + int16_t imm; + + /* make sure instructions are on a word boundary */ + if (ctx->pc & 0x3) { + env->CP0_BadVAddr = ctx->pc; + generate_exception(ctx, EXCP_AdEL); + return; + } + + /* Handle blikely not taken case */ + if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) { + int l1 = gen_new_label(); + + MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4); + tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); + tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); + gen_goto_tb(ctx, 1, ctx->pc + 4); + gen_set_label(l1); + } + + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) + tcg_gen_debug_insn_start(ctx->pc); + + op = MASK_OP_MAJOR(ctx->opcode); + rs = (ctx->opcode >> 21) & 0x1f; + rt = (ctx->opcode >> 16) & 0x1f; + rd = (ctx->opcode >> 11) & 0x1f; + sa = (ctx->opcode >> 6) & 0x1f; + imm = (int16_t)ctx->opcode; + switch (op) { + case OPC_SPECIAL: + op1 = MASK_SPECIAL(ctx->opcode); + switch (op1) { + case OPC_SLL: /* Shift with immediate */ + case OPC_SRA: + gen_shift_imm(env, ctx, op1, rd, rt, sa); + break; + case OPC_SRL: + switch ((ctx->opcode >> 21) & 0x1f) { + case 1: + /* rotr is decoded as srl on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + op1 = OPC_ROTR; + } + /* Fallthrough */ + case 0: + gen_shift_imm(env, ctx, op1, rd, rt, sa); + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_MOVN: /* Conditional move */ + case OPC_MOVZ: + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32 | + INSN_LOONGSON2E | INSN_LOONGSON2F); + gen_cond_move(env, op1, rd, rs, rt); + break; + case OPC_ADD ... OPC_SUBU: + gen_arith(env, ctx, op1, rd, rs, rt); + break; + case OPC_SLLV: /* Shifts */ + case OPC_SRAV: + gen_shift(env, ctx, op1, rd, rs, rt); + break; + case OPC_SRLV: + switch ((ctx->opcode >> 6) & 0x1f) { + case 1: + /* rotrv is decoded as srlv on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + op1 = OPC_ROTRV; + } + /* Fallthrough */ + case 0: + gen_shift(env, ctx, op1, rd, rs, rt); + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_SLT: /* Set on less than */ + case OPC_SLTU: + gen_slt(env, op1, rd, rs, rt); + break; + case OPC_AND: /* Logic*/ + case OPC_OR: + case OPC_NOR: + case OPC_XOR: + gen_logic(env, op1, rd, rs, rt); + break; + case OPC_MULT ... OPC_DIVU: + if (sa) { + check_insn(env, ctx, INSN_VR54XX); + op1 = MASK_MUL_VR54XX(ctx->opcode); + gen_mul_vr54xx(ctx, op1, rd, rs, rt); + } else + gen_muldiv(ctx, op1, rs, rt); + break; + case OPC_JR ... OPC_JALR: + gen_compute_branch(ctx, op1, 4, rs, rd, sa); + *is_branch = 1; + break; + case OPC_TGE ... OPC_TEQ: /* Traps */ + case OPC_TNE: + gen_trap(ctx, op1, rs, rt, -1); + break; + case OPC_MFHI: /* Move from HI/LO */ + case OPC_MFLO: + gen_HILO(ctx, op1, rd); + break; + case OPC_MTHI: + case OPC_MTLO: /* Move to HI/LO */ + gen_HILO(ctx, op1, rs); + break; + case OPC_PMON: /* Pmon entry point, also R4010 selsl */ +#ifdef MIPS_STRICT_STANDARD + MIPS_INVAL("PMON / selsl"); + generate_exception(ctx, EXCP_RI); +#else + gen_helper_0i(pmon, sa); +#endif + break; + case OPC_SYSCALL: + generate_exception(ctx, EXCP_SYSCALL); + ctx->bstate = BS_STOP; + break; + case OPC_BREAK: + generate_exception(ctx, EXCP_BREAK); + break; + case OPC_SPIM: +#ifdef MIPS_STRICT_STANDARD + MIPS_INVAL("SPIM"); + generate_exception(ctx, EXCP_RI); +#else + /* Implemented as RI exception for now. */ + MIPS_INVAL("spim (unofficial)"); + generate_exception(ctx, EXCP_RI); +#endif + break; + case OPC_SYNC: + /* Treat as NOP. */ + break; + + case OPC_MOVCI: + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, + (ctx->opcode >> 16) & 1); + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + +#if defined(TARGET_MIPS64) + /* MIPS64 specific opcodes */ + case OPC_DSLL: + case OPC_DSRA: + case OPC_DSLL32: + case OPC_DSRA32: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_shift_imm(env, ctx, op1, rd, rt, sa); + break; + case OPC_DSRL: + switch ((ctx->opcode >> 21) & 0x1f) { + case 1: + /* drotr is decoded as dsrl on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + op1 = OPC_DROTR; + } + /* Fallthrough */ + case 0: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_shift_imm(env, ctx, op1, rd, rt, sa); + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_DSRL32: + switch ((ctx->opcode >> 21) & 0x1f) { + case 1: + /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + op1 = OPC_DROTR32; + } + /* Fallthrough */ + case 0: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_shift_imm(env, ctx, op1, rd, rt, sa); + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_DADD ... OPC_DSUBU: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_arith(env, ctx, op1, rd, rs, rt); + break; + case OPC_DSLLV: + case OPC_DSRAV: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_shift(env, ctx, op1, rd, rs, rt); + break; + case OPC_DSRLV: + switch ((ctx->opcode >> 6) & 0x1f) { + case 1: + /* drotrv is decoded as dsrlv on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + op1 = OPC_DROTRV; + } + /* Fallthrough */ + case 0: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_shift(env, ctx, op1, rd, rs, rt); + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_DMULT ... OPC_DDIVU: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_muldiv(ctx, op1, rs, rt); + break; +#endif + default: /* Invalid */ + MIPS_INVAL("special"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_SPECIAL2: + op1 = MASK_SPECIAL2(ctx->opcode); + switch (op1) { + case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */ + case OPC_MSUB ... OPC_MSUBU: + check_insn(env, ctx, ISA_MIPS32); + gen_muldiv(ctx, op1, rs, rt); + break; + case OPC_MUL: + gen_arith(env, ctx, op1, rd, rs, rt); + break; + case OPC_CLO: + case OPC_CLZ: + check_insn(env, ctx, ISA_MIPS32); + gen_cl(ctx, op1, rd, rs); + break; + case OPC_SDBBP: + /* XXX: not clear which exception should be raised + * when in debug mode... + */ + check_insn(env, ctx, ISA_MIPS32); + if (!(ctx->hflags & MIPS_HFLAG_DM)) { + generate_exception(ctx, EXCP_DBp); + } else { + generate_exception(ctx, EXCP_DBp); + } + /* Treat as NOP. */ + break; + case OPC_DIV_G_2F: + case OPC_DIVU_G_2F: + case OPC_MULT_G_2F: + case OPC_MULTU_G_2F: + case OPC_MOD_G_2F: + case OPC_MODU_G_2F: + check_insn(env, ctx, INSN_LOONGSON2F); + gen_loongson_integer(ctx, op1, rd, rs, rt); + break; +#if defined(TARGET_MIPS64) + case OPC_DCLO: + case OPC_DCLZ: + check_insn(env, ctx, ISA_MIPS64); + check_mips_64(ctx); + gen_cl(ctx, op1, rd, rs); + break; + case OPC_DMULT_G_2F: + case OPC_DMULTU_G_2F: + case OPC_DDIV_G_2F: + case OPC_DDIVU_G_2F: + case OPC_DMOD_G_2F: + case OPC_DMODU_G_2F: + check_insn(env, ctx, INSN_LOONGSON2F); + gen_loongson_integer(ctx, op1, rd, rs, rt); + break; +#endif + default: /* Invalid */ + MIPS_INVAL("special2"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_SPECIAL3: + op1 = MASK_SPECIAL3(ctx->opcode); + switch (op1) { + case OPC_EXT: + case OPC_INS: + check_insn(env, ctx, ISA_MIPS32R2); + gen_bitops(ctx, op1, rt, rs, sa, rd); + break; + case OPC_BSHFL: + check_insn(env, ctx, ISA_MIPS32R2); + op2 = MASK_BSHFL(ctx->opcode); + gen_bshfl(ctx, op2, rt, rd); + break; + case OPC_RDHWR: + gen_rdhwr(env, ctx, rt, rd); + break; + case OPC_FORK: + check_insn(env, ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + gen_helper_fork(t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + case OPC_YIELD: + check_insn(env, ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_load_gpr(t0, rs); + gen_helper_yield(t0, t0); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + break; + case OPC_DIV_G_2E ... OPC_DIVU_G_2E: + case OPC_MULT_G_2E ... OPC_MULTU_G_2E: + case OPC_MOD_G_2E ... OPC_MODU_G_2E: + check_insn(env, ctx, INSN_LOONGSON2E); + gen_loongson_integer(ctx, op1, rd, rs, rt); + break; +#if defined(TARGET_MIPS64) + case OPC_DEXTM ... OPC_DEXT: + case OPC_DINSM ... OPC_DINS: + check_insn(env, ctx, ISA_MIPS64R2); + check_mips_64(ctx); + gen_bitops(ctx, op1, rt, rs, sa, rd); + break; + case OPC_DBSHFL: + check_insn(env, ctx, ISA_MIPS64R2); + check_mips_64(ctx); + op2 = MASK_DBSHFL(ctx->opcode); + gen_bshfl(ctx, op2, rt, rd); + break; + case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E: + case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E: + case OPC_DMOD_G_2E ... OPC_DMODU_G_2E: + check_insn(env, ctx, INSN_LOONGSON2E); + gen_loongson_integer(ctx, op1, rd, rs, rt); + break; +#endif + default: /* Invalid */ + MIPS_INVAL("special3"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_REGIMM: + op1 = MASK_REGIMM(ctx->opcode); + switch (op1) { + case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */ + case OPC_BLTZAL ... OPC_BGEZALL: + gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2); + *is_branch = 1; + break; + case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */ + case OPC_TNEI: + gen_trap(ctx, op1, rs, -1, imm); + break; + case OPC_SYNCI: + check_insn(env, ctx, ISA_MIPS32R2); + /* Treat as NOP. */ + break; + default: /* Invalid */ + MIPS_INVAL("regimm"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_CP0: + check_cp0_enabled(ctx); + op1 = MASK_CP0(ctx->opcode); + switch (op1) { + case OPC_MFC0: + case OPC_MTC0: + case OPC_MFTR: + case OPC_MTTR: +#if defined(TARGET_MIPS64) + case OPC_DMFC0: + case OPC_DMTC0: +#endif +#ifndef CONFIG_USER_ONLY + gen_cp0(env, ctx, op1, rt, rd); +#endif /* !CONFIG_USER_ONLY */ + break; + case OPC_C0_FIRST ... OPC_C0_LAST: +#ifndef CONFIG_USER_ONLY + gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); +#endif /* !CONFIG_USER_ONLY */ + break; + case OPC_MFMC0: +#ifndef CONFIG_USER_ONLY + { + TCGv t0 = tcg_temp_new(); + + op2 = MASK_MFMC0(ctx->opcode); + switch (op2) { + case OPC_DMT: + check_insn(env, ctx, ASE_MT); + gen_helper_dmt(t0); + gen_store_gpr(t0, rt); + break; + case OPC_EMT: + check_insn(env, ctx, ASE_MT); + gen_helper_emt(t0); + gen_store_gpr(t0, rt); + break; + case OPC_DVPE: + check_insn(env, ctx, ASE_MT); + gen_helper_dvpe(t0); + gen_store_gpr(t0, rt); + break; + case OPC_EVPE: + check_insn(env, ctx, ASE_MT); + gen_helper_evpe(t0); + gen_store_gpr(t0, rt); + break; + case OPC_DI: + check_insn(env, ctx, ISA_MIPS32R2); + save_cpu_state(ctx, 1); + gen_helper_di(t0); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case OPC_EI: + check_insn(env, ctx, ISA_MIPS32R2); + save_cpu_state(ctx, 1); + gen_helper_ei(t0); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + default: /* Invalid */ + MIPS_INVAL("mfmc0"); + generate_exception(ctx, EXCP_RI); + break; + } + tcg_temp_free(t0); + } +#endif /* !CONFIG_USER_ONLY */ + break; + case OPC_RDPGPR: + check_insn(env, ctx, ISA_MIPS32R2); + gen_load_srsgpr(rt, rd); + break; + case OPC_WRPGPR: + check_insn(env, ctx, ISA_MIPS32R2); + gen_store_srsgpr(rt, rd); + break; + default: + MIPS_INVAL("cp0"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_ADDI: /* Arithmetic with immediate opcode */ + case OPC_ADDIU: + gen_arith_imm(env, ctx, op, rt, rs, imm); + break; + case OPC_SLTI: /* Set on less than with immediate opcode */ + case OPC_SLTIU: + gen_slt_imm(env, op, rt, rs, imm); + break; + case OPC_ANDI: /* Arithmetic with immediate opcode */ + case OPC_LUI: + case OPC_ORI: + case OPC_XORI: + gen_logic_imm(env, op, rt, rs, imm); + break; + case OPC_J ... OPC_JAL: /* Jump */ + offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; + gen_compute_branch(ctx, op, 4, rs, rt, offset); + *is_branch = 1; + break; + case OPC_BEQ ... OPC_BGTZ: /* Branch */ + case OPC_BEQL ... OPC_BGTZL: + gen_compute_branch(ctx, op, 4, rs, rt, imm << 2); + *is_branch = 1; + break; + case OPC_LB ... OPC_LWR: /* Load and stores */ + case OPC_LL: + gen_ld(env, ctx, op, rt, rs, imm); + break; + case OPC_SB ... OPC_SW: + case OPC_SWR: + gen_st(ctx, op, rt, rs, imm); + break; + case OPC_SC: + gen_st_cond(ctx, op, rt, rs, imm); + break; + case OPC_CACHE: + check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); + /* Treat as NOP. */ + break; + case OPC_PREF: + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + /* Treat as NOP. */ + break; + + /* Floating point (COP1). */ + case OPC_LWC1: + case OPC_LDC1: + case OPC_SWC1: + case OPC_SDC1: + gen_cop1_ldst(env, ctx, op, rt, rs, imm); + break; + + case OPC_CP1: + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + op1 = MASK_CP1(ctx->opcode); + switch (op1) { + case OPC_MFHC1: + case OPC_MTHC1: + check_insn(env, ctx, ISA_MIPS32R2); + case OPC_MFC1: + case OPC_CFC1: + case OPC_MTC1: + case OPC_CTC1: + gen_cp1(ctx, op1, rt, rd); + break; +#if defined(TARGET_MIPS64) + case OPC_DMFC1: + case OPC_DMTC1: + check_insn(env, ctx, ISA_MIPS3); + gen_cp1(ctx, op1, rt, rd); + break; +#endif + case OPC_BC1ANY2: + case OPC_BC1ANY4: + check_cop1x(ctx); + check_insn(env, ctx, ASE_MIPS3D); + /* fall through */ + case OPC_BC1: + gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), + (rt >> 2) & 0x7, imm << 2); + *is_branch = 1; + break; + case OPC_S_FMT: + case OPC_D_FMT: + case OPC_W_FMT: + case OPC_L_FMT: + case OPC_PS_FMT: + gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, + (imm >> 8) & 0x7); + break; + default: + MIPS_INVAL("cp1"); + generate_exception (ctx, EXCP_RI); + break; + } + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + + /* COP2. */ + case OPC_LWC2: + case OPC_LDC2: + case OPC_SWC2: + case OPC_SDC2: + case OPC_CP2: + /* COP2: Not implemented. */ + generate_exception_err(ctx, EXCP_CpU, 2); + break; + + case OPC_CP3: + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + op1 = MASK_CP3(ctx->opcode); + switch (op1) { + case OPC_LWXC1: + case OPC_LDXC1: + case OPC_LUXC1: + case OPC_SWXC1: + case OPC_SDXC1: + case OPC_SUXC1: + gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); + break; + case OPC_PREFX: + /* Treat as NOP. */ + break; + case OPC_ALNV_PS: + case OPC_MADD_S: + case OPC_MADD_D: + case OPC_MADD_PS: + case OPC_MSUB_S: + case OPC_MSUB_D: + case OPC_MSUB_PS: + case OPC_NMADD_S: + case OPC_NMADD_D: + case OPC_NMADD_PS: + case OPC_NMSUB_S: + case OPC_NMSUB_D: + case OPC_NMSUB_PS: + gen_flt3_arith(ctx, op1, sa, rs, rd, rt); + break; + default: + MIPS_INVAL("cp3"); + generate_exception (ctx, EXCP_RI); + break; + } + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + +#if defined(TARGET_MIPS64) + /* MIPS64 opcodes */ + case OPC_LWU: + case OPC_LDL ... OPC_LDR: + case OPC_LLD: + case OPC_LD: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_ld(env, ctx, op, rt, rs, imm); + break; + case OPC_SDL ... OPC_SDR: + case OPC_SD: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_st(ctx, op, rt, rs, imm); + break; + case OPC_SCD: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_st_cond(ctx, op, rt, rs, imm); + break; + case OPC_DADDI: + case OPC_DADDIU: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_arith_imm(env, ctx, op, rt, rs, imm); + break; +#endif + case OPC_JALX: + check_insn(env, ctx, ASE_MIPS16 | ASE_MICROMIPS); + offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; + gen_compute_branch(ctx, op, 4, rs, rt, offset); + *is_branch = 1; + break; + case OPC_MDMX: + check_insn(env, ctx, ASE_MDMX); + /* MDMX: Not implemented. */ + default: /* Invalid */ + MIPS_INVAL("major opcode"); + generate_exception(ctx, EXCP_RI); + break; + } +} + +static inline void +gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, + int search_pc) +{ + DisasContext ctx; + target_ulong pc_start; + uint16_t *gen_opc_end; + CPUBreakpoint *bp; + int j, lj = -1; + int num_insns; + int max_insns; + int insn_bytes; + int is_branch; + + if (search_pc) + qemu_log("search pc %d\n", search_pc); + + pc_start = tb->pc; + gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; + ctx.pc = pc_start; + ctx.saved_pc = -1; + ctx.singlestep_enabled = env->singlestep_enabled; + ctx.tb = tb; + ctx.bstate = BS_NONE; + /* Restore delay slot state from the tb context. */ + ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */ + restore_cpu_state(env, &ctx); +#ifdef CONFIG_USER_ONLY + ctx.mem_idx = MIPS_HFLAG_UM; +#else + ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU; +#endif + num_insns = 0; + max_insns = tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) + max_insns = CF_COUNT_MASK; + LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); + gen_icount_start(); + while (ctx.bstate == BS_NONE) { + if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { + QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (bp->pc == ctx.pc) { + save_cpu_state(&ctx, 1); + ctx.bstate = BS_BRANCH; + gen_helper_0i(raise_exception, EXCP_DEBUG); + /* Include the breakpoint location or the tb won't + * be flushed when it must be. */ + ctx.pc += 4; + goto done_generating; + } + } + } + + if (search_pc) { + j = gen_opc_ptr - gen_opc_buf; + if (lj < j) { + lj++; + while (lj < j) + gen_opc_instr_start[lj++] = 0; + } + gen_opc_pc[lj] = ctx.pc; + gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK; + gen_opc_instr_start[lj] = 1; + gen_opc_icount[lj] = num_insns; + } + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + gen_io_start(); + + is_branch = 0; + if (!(ctx.hflags & MIPS_HFLAG_M16)) { + ctx.opcode = ldl_code(ctx.pc); + insn_bytes = 4; + decode_opc(env, &ctx, &is_branch); + } else if (env->insn_flags & ASE_MICROMIPS) { + ctx.opcode = lduw_code(ctx.pc); + insn_bytes = decode_micromips_opc(env, &ctx, &is_branch); + } else if (env->insn_flags & ASE_MIPS16) { + ctx.opcode = lduw_code(ctx.pc); + insn_bytes = decode_mips16_opc(env, &ctx, &is_branch); + } else { + generate_exception(&ctx, EXCP_RI); + ctx.bstate = BS_STOP; + break; + } + if (!is_branch) { + handle_delay_slot(env, &ctx, insn_bytes); + } + ctx.pc += insn_bytes; + + num_insns++; + + /* Execute a branch and its delay slot as a single instruction. + This is what GDB expects and is consistent with what the + hardware does (e.g. if a delay slot instruction faults, the + reported PC is the PC of the branch). */ + if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) + break; + + if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) + break; + + if (gen_opc_ptr >= gen_opc_end) + break; + + if (num_insns >= max_insns) + break; + + if (singlestep) + break; + } + if (tb->cflags & CF_LAST_IO) + gen_io_end(); + if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) { + save_cpu_state(&ctx, ctx.bstate == BS_NONE); + gen_helper_0i(raise_exception, EXCP_DEBUG); + } else { + switch (ctx.bstate) { + case BS_STOP: + gen_goto_tb(&ctx, 0, ctx.pc); + break; + case BS_NONE: + save_cpu_state(&ctx, 0); + gen_goto_tb(&ctx, 0, ctx.pc); + break; + case BS_EXCP: + tcg_gen_exit_tb(0); + break; + case BS_BRANCH: + default: + break; + } + } +done_generating: + gen_icount_end(tb, num_insns); + *gen_opc_ptr = INDEX_op_end; + if (search_pc) { + j = gen_opc_ptr - gen_opc_buf; + lj++; + while (lj <= j) + gen_opc_instr_start[lj++] = 0; + } else { + tb->size = ctx.pc - pc_start; + tb->icount = num_insns; + } +#ifdef DEBUG_DISAS + LOG_DISAS("\n"); + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { + qemu_log("IN: %s\n", lookup_symbol(pc_start)); + log_target_disas(pc_start, ctx.pc - pc_start, 0); + qemu_log("\n"); + } +#endif +} + +void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) +{ + gen_intermediate_code_internal(env, tb, 0); +} + +void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) +{ + gen_intermediate_code_internal(env, tb, 1); +} + +static void fpu_dump_state(CPUState *env, FILE *f, fprintf_function fpu_fprintf, + int flags) +{ + int i; + int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); + +#define printfpr(fp) \ + do { \ + if (is_fpu64) \ + fpu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu: %13g\n", \ + (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ + (double)(fp)->fd, \ + (double)(fp)->fs[FP_ENDIAN_IDX], \ + (double)(fp)->fs[!FP_ENDIAN_IDX]); \ + else { \ + fpr_t tmp; \ + tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \ + tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \ + fpu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu:%13g\n", \ + tmp.w[FP_ENDIAN_IDX], tmp.d, \ + (double)tmp.fd, \ + (double)tmp.fs[FP_ENDIAN_IDX], \ + (double)tmp.fs[!FP_ENDIAN_IDX]); \ + } \ + } while(0) + + + fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, + get_float_exception_flags(&env->active_fpu.fp_status)); + for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { + fpu_fprintf(f, "%3s: ", fregnames[i]); + printfpr(&env->active_fpu.fpr[i]); + } + +#undef printfpr +} + +#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) +/* Debug help: The architecture requires 32bit code to maintain proper + sign-extended values on 64bit machines. */ + +#define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff)) + +static void +cpu_mips_check_sign_extensions (CPUState *env, FILE *f, + fprintf_function cpu_fprintf, + int flags) +{ + int i; + + if (!SIGN_EXT_P(env->active_tc.PC)) + cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->active_tc.PC); + if (!SIGN_EXT_P(env->active_tc.HI[0])) + cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->active_tc.HI[0]); + if (!SIGN_EXT_P(env->active_tc.LO[0])) + cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->active_tc.LO[0]); + if (!SIGN_EXT_P(env->btarget)) + cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget); + + for (i = 0; i < 32; i++) { + if (!SIGN_EXT_P(env->active_tc.gpr[i])) + cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->active_tc.gpr[i]); + } + + if (!SIGN_EXT_P(env->CP0_EPC)) + cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC); + if (!SIGN_EXT_P(env->lladdr)) + cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->lladdr); +} +#endif + +void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf, + int flags) +{ + int i; + + cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx + " LO=0x" TARGET_FMT_lx " ds %04x " + TARGET_FMT_lx " " TARGET_FMT_ld "\n", + env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], + env->hflags, env->btarget, env->bcond); + for (i = 0; i < 32; i++) { + if ((i & 3) == 0) + cpu_fprintf(f, "GPR%02d:", i); + cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]); + if ((i & 3) == 3) + cpu_fprintf(f, "\n"); + } + + cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n", + env->CP0_Status, env->CP0_Cause, env->CP0_EPC); + cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n", + env->CP0_Config0, env->CP0_Config1, env->lladdr); + if (env->hflags & MIPS_HFLAG_FPU) + fpu_dump_state(env, f, cpu_fprintf, flags); +#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) + cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags); +#endif +} + +static void mips_tcg_init(void) +{ + int i; + static int inited; + + /* Initialize various static tables. */ + if (inited) + return; + + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); + TCGV_UNUSED(cpu_gpr[0]); + for (i = 1; i < 32; i++) + cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.gpr[i]), + regnames[i]); + cpu_PC = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.PC), "PC"); + for (i = 0; i < MIPS_DSP_ACC; i++) { + cpu_HI[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.HI[i]), + regnames_HI[i]); + cpu_LO[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.LO[i]), + regnames_LO[i]); + cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.ACX[i]), + regnames_ACX[i]); + } + cpu_dspctrl = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.DSPControl), + "DSPControl"); + bcond = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, bcond), "bcond"); + btarget = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, btarget), "btarget"); + hflags = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, hflags), "hflags"); + + fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, active_fpu.fcr0), + "fcr0"); + fpu_fcr31 = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, active_fpu.fcr31), + "fcr31"); + + /* register helpers */ +#define GEN_HELPER 2 +#include "helper.h" + + inited = 1; +} + +#include "translate_init.c" + +CPUMIPSState *cpu_mips_init (const char *cpu_model) +{ + CPUMIPSState *env; + const mips_def_t *def; + + def = cpu_mips_find_by_name(cpu_model); + if (!def) + return NULL; + env = qemu_mallocz(sizeof(CPUMIPSState)); + env->cpu_model = def; + env->cpu_model_str = cpu_model; + + cpu_exec_init(env); +#ifndef CONFIG_USER_ONLY + mmu_init(env, def); +#endif + fpu_init(env, def); + mvp_init(env, def); + mips_tcg_init(); + cpu_reset(env); + qemu_init_vcpu(env); + return env; +} + +void cpu_reset (CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); + log_cpu_state(env, 0); + } + + memset(env, 0, offsetof(CPUMIPSState, breakpoints)); + tlb_flush(env, 1); + + /* Reset registers to their default values */ + env->CP0_PRid = env->cpu_model->CP0_PRid; + env->CP0_Config0 = env->cpu_model->CP0_Config0; +#ifdef TARGET_WORDS_BIGENDIAN + env->CP0_Config0 |= (1 << CP0C0_BE); +#endif + env->CP0_Config1 = env->cpu_model->CP0_Config1; + env->CP0_Config2 = env->cpu_model->CP0_Config2; + env->CP0_Config3 = env->cpu_model->CP0_Config3; + env->CP0_Config6 = env->cpu_model->CP0_Config6; + env->CP0_Config7 = env->cpu_model->CP0_Config7; + env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask + << env->cpu_model->CP0_LLAddr_shift; + env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; + env->SYNCI_Step = env->cpu_model->SYNCI_Step; + env->CCRes = env->cpu_model->CCRes; + env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; + env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; + env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; + env->current_tc = 0; + env->SEGBITS = env->cpu_model->SEGBITS; + env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); +#if defined(TARGET_MIPS64) + if (env->cpu_model->insn_flags & ISA_MIPS3) { + env->SEGMask |= 3ULL << 62; + } +#endif + env->PABITS = env->cpu_model->PABITS; + env->PAMask = (target_ulong)((1ULL << env->cpu_model->PABITS) - 1); + env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; + env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; + env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; + env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; + env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; + env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; + env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; + env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; + env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; + env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; + env->insn_flags = env->cpu_model->insn_flags; + +#if defined(CONFIG_USER_ONLY) + env->hflags = MIPS_HFLAG_UM; + /* Enable access to the SYNCI_Step register. */ + env->CP0_HWREna |= (1 << 1); + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + env->hflags |= MIPS_HFLAG_FPU; + } +#ifdef TARGET_MIPS64 + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { + env->hflags |= MIPS_HFLAG_F64; + } +#endif +#else + if (env->hflags & MIPS_HFLAG_BMASK) { + /* If the exception was raised from a delay slot, + come back to the jump. */ + env->CP0_ErrorEPC = env->active_tc.PC - 4; + } else { + env->CP0_ErrorEPC = env->active_tc.PC; + } + env->active_tc.PC = (int32_t)0xBFC00000; + env->CP0_Random = env->tlb->nb_tlb - 1; + env->tlb->tlb_in_use = env->tlb->nb_tlb; + env->CP0_Wired = 0; + env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF); + env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); + /* vectored interrupts not implemented, timer on int 7, + no performance counters. */ + env->CP0_IntCtl = 0xe0000000; + { + int i; + + for (i = 0; i < 7; i++) { + env->CP0_WatchLo[i] = 0; + env->CP0_WatchHi[i] = 0x80000000; + } + env->CP0_WatchLo[7] = 0; + env->CP0_WatchHi[7] = 0; + } + /* Count register increments in debug mode, EJTAG version 1 */ + env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); + env->hflags = MIPS_HFLAG_CP0; +#endif +#if defined(TARGET_MIPS64) + if (env->cpu_model->insn_flags & ISA_MIPS3) { + env->hflags |= MIPS_HFLAG_64; + } +#endif + env->exception_index = EXCP_NONE; +} + +void gen_pc_load(CPUState *env, TranslationBlock *tb, + unsigned long searched_pc, int pc_pos, void *puc) +{ + env->active_tc.PC = gen_opc_pc[pc_pos]; + env->hflags &= ~MIPS_HFLAG_BMASK; + env->hflags |= gen_opc_hflags[pc_pos]; +} diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c new file mode 100644 index 0000000..590e092 --- /dev/null +++ b/target-mips/translate_init.c @@ -0,0 +1,594 @@ +/* + * MIPS emulation for qemu: CPU initialisation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2007 Herve Poussineau + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +/* CPU / CPU family specific config register values. */ + +/* Have config1, uncached coherency */ +#define MIPS_CONFIG0 \ + ((1 << CP0C0_M) | (0x2 << CP0C0_K0)) + +/* Have config2, no coprocessor2 attached, no MDMX support attached, + no performance counters, watch registers present, + no code compression, EJTAG present, no FPU */ +#define MIPS_CONFIG1 \ +((1 << CP0C1_M) | \ + (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ + (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ + (0 << CP0C1_FP)) + +/* Have config3, no tertiary/secondary caches implemented */ +#define MIPS_CONFIG2 \ +((1 << CP0C2_M)) + +/* No config4, no DSP ASE, no large physaddr (PABITS), + no external interrupt controller, no vectored interupts, + no 1kb pages, no SmartMIPS ASE, no trace logic */ +#define MIPS_CONFIG3 \ +((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ + (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ + (0 << CP0C3_SM) | (0 << CP0C3_TL)) + +/* MMU types, the first four entries have the same layout as the + CP0C0_MT field. */ +enum mips_mmu_types { + MMU_TYPE_NONE, + MMU_TYPE_R4000, + MMU_TYPE_RESERVED, + MMU_TYPE_FMT, + MMU_TYPE_R3000, + MMU_TYPE_R6000, + MMU_TYPE_R8000 +}; + +struct mips_def_t { + const char *name; + int32_t CP0_PRid; + int32_t CP0_Config0; + int32_t CP0_Config1; + int32_t CP0_Config2; + int32_t CP0_Config3; + int32_t CP0_Config6; + int32_t CP0_Config7; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; + int32_t SYNCI_Step; + int32_t CCRes; + int32_t CP0_Status_rw_bitmask; + int32_t CP0_TCStatus_rw_bitmask; + int32_t CP0_SRSCtl; + int32_t CP1_fcr0; + int32_t SEGBITS; + int32_t PABITS; + int32_t CP0_SRSConf0_rw_bitmask; + int32_t CP0_SRSConf0; + int32_t CP0_SRSConf1_rw_bitmask; + int32_t CP0_SRSConf1; + int32_t CP0_SRSConf2_rw_bitmask; + int32_t CP0_SRSConf2; + int32_t CP0_SRSConf3_rw_bitmask; + int32_t CP0_SRSConf3; + int32_t CP0_SRSConf4_rw_bitmask; + int32_t CP0_SRSConf4; + int insn_flags; + enum mips_mmu_types mmu_type; +}; + +/*****************************************************************************/ +/* MIPS CPU definitions */ +static const mips_def_t mips_defs[] = +{ + { + .name = "4Kc", + .CP0_PRid = 0x00018000, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (0 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "4Km", + .CP0_PRid = 0x00018300, + /* Config1 implemented, fixed mapping MMU, + no virtual icache, uncached coherency. */ + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "4KEcR1", + .CP0_PRid = 0x00018400, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (0 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "4KEmR1", + .CP0_PRid = 0x00018500, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "4KEc", + .CP0_PRid = 0x00019000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (0 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "4KEm", + .CP0_PRid = 0x00019100, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "24Kc", + .CP0_PRid = 0x00019300, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + /* No DSP implemented. */ + .CP0_Status_rw_bitmask = 0x1278FF1F, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "24Kf", + .CP0_PRid = 0x00019300, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + /* No DSP implemented. */ + .CP0_Status_rw_bitmask = 0x3678FF1F, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "34Kf", + .CP0_PRid = 0x00019500, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + /* No DSP implemented. */ + .CP0_Status_rw_bitmask = 0x3678FF1F, + /* No DSP implemented. */ + .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | + (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | + (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | + (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | + (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | + (0xff << CP0TCSt_TASID), + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), + .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), + .CP0_SRSConf0_rw_bitmask = 0x3fffffff, + .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | + (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), + .CP0_SRSConf1_rw_bitmask = 0x3fffffff, + .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | + (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), + .CP0_SRSConf2_rw_bitmask = 0x3fffffff, + .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | + (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), + .CP0_SRSConf3_rw_bitmask = 0x3fffffff, + .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | + (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), + .CP0_SRSConf4_rw_bitmask = 0x3fffffff, + .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | + (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, + .mmu_type = MMU_TYPE_R4000, + }, +#if defined(TARGET_MIPS64) + { + .name = "R4000", + .CP0_PRid = 0x00000400, + /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ + .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), + /* Note: Config1 is only used internally, the R4000 has only Config0. */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3678FFFF, + /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 36, + .insn_flags = CPU_MIPS3, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "VR5432", + .CP0_PRid = 0x00005400, + /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ + .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3678FFFF, + /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 32, + .insn_flags = CPU_VR54XX, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "5Kc", + .CP0_PRid = 0x00018100, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x32F8FFFF, + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "5Kf", + .CP0_PRid = 0x00018100, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36F8FFFF, + /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | + (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "20Kc", + /* We emulate a later version of the 20Kc, earlier ones had a broken + WAIT instruction. */ + .CP0_PRid = 0x000182a0, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 1, + .CP0_Status_rw_bitmask = 0x36FBFFFF, + /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_D) | (1 << FCR0_S) | + (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 36, + .insn_flags = CPU_MIPS64 | ASE_MIPS3D, + .mmu_type = MMU_TYPE_R4000, + }, + { + /* A generic CPU providing MIPS64 Release 2 features. + FIXME: Eventually this should be replaced by a real CPU model. */ + .name = "MIPS64R2-generic", + .CP0_PRid = 0x00010000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36FBFFFF, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 42, + /* The architectural limit is 59, but we have hardcoded 36 bit + in some places... + .PABITS = 59, */ /* the architectural limit */ + .PABITS = 36, + .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "Loongson-2E", + .CP0_PRid = 0x6302, + /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ + .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | + (0x1<<4) | (0x1<<1), + /* Note: Config1 is only used internally, Loongson-2E has only Config0. */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x35D0FFFF, + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 40, + .insn_flags = CPU_LOONGSON2E, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "Loongson-2F", + .CP0_PRid = 0x6303, + /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ + .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | + (0x1<<4) | (0x1<<1), + /* Note: Config1 is only used internally, Loongson-2F has only Config0. */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writeable*/ + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 40, + .insn_flags = CPU_LOONGSON2F, + .mmu_type = MMU_TYPE_R4000, + }, + +#endif +}; + +static const mips_def_t *cpu_mips_find_by_name (const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { + if (strcasecmp(name, mips_defs[i].name) == 0) { + return &mips_defs[i]; + } + } + return NULL; +} + +void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { + (*cpu_fprintf)(f, "MIPS '%s'\n", + mips_defs[i].name); + } +} + +#ifndef CONFIG_USER_ONLY +static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &no_mmu_map_address; +} + +static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &fixed_mmu_map_address; +} + +static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); + env->tlb->map_address = &r4k_map_address; + env->tlb->helper_tlbwi = r4k_helper_tlbwi; + env->tlb->helper_tlbwr = r4k_helper_tlbwr; + env->tlb->helper_tlbp = r4k_helper_tlbp; + env->tlb->helper_tlbr = r4k_helper_tlbr; +} + +static void mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext)); + + switch (def->mmu_type) { + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env, "MMU type not supported\n"); + } +} +#endif /* CONFIG_USER_ONLY */ + +static void fpu_init (CPUMIPSState *env, const mips_def_t *def) +{ + int i; + + for (i = 0; i < MIPS_FPU_MAX; i++) + env->fpus[i].fcr0 = def->CP1_fcr0; + + memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); +} + +static void mvp_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext)); + + /* MVPConf1 implemented, TLB sharable, no gating storage support, + programmable cache partitioning implemented, number of allocatable + and sharable TLB entries, MVP has allocatable TCs, 2 VPEs + implemented, 5 TCs implemented. */ + env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | + (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | +// TODO: actually do 2 VPEs. +// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | +// (0x04 << CP0MVPC0_PTC); + (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | + (0x04 << CP0MVPC0_PTC); +#if !defined(CONFIG_USER_ONLY) + /* Usermode has no TLB support */ + env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); +#endif + + /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, + no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ + env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | + (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | + (0x1 << CP0MVPC1_PCP1); +} |