14238 Remove vestigial mcfg related pieces

Reviewed by: Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Rich Lowe <richlowe@richlowe.net>

5 files changed, 8 insertions, 69 deletions

diff --git a/usr/src/uts/common/sys/pcie_impl.h b/usr/src/uts/common/sys/pcie_impl.h
index 442c55043c..07eb6fee65 100644
--- a/usr/src/uts/common/sys/pcie_impl.h
+++ b/usr/src/uts/common/sys/pcie_impl.h
@@ -379,8 +379,6 @@ typedef struct pcie_bus {
 	void		*bus_hp_ctrl;		/* HP bus ctrl data */
 	int		bus_ari;		/* ARI device */
 
-	uint64_t	bus_cfgacc_base;	/* config space base address */
-
 	/* workaround for PCI/PCI-X devs behind PCIe2PCI Bridge */
 	pcie_req_id_t   bus_pcie2pci_secbus;
 
diff --git a/usr/src/uts/i86pc/io/pciex/npe.c b/usr/src/uts/i86pc/io/pciex/npe.c
index fcb68164ee..5543794b54 100644
--- a/usr/src/uts/i86pc/io/pciex/npe.c
+++ b/usr/src/uts/i86pc/io/pciex/npe.c
@@ -208,7 +208,6 @@ static int npe_initchild(dev_info_t *child);
 /*
  * External support routine
  */
-extern void	npe_query_acpi_mcfg(dev_info_t *dip);
 extern void	npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
 extern int	npe_disable_empty_bridges_workaround(dev_info_t *child);
 extern void	npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl);
@@ -395,7 +394,6 @@ npe_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
 	PCIE_DIP2PFD(devi) = kmem_zalloc(sizeof (pf_data_t), KM_SLEEP);
 	pcie_rc_init_pfd(devi, PCIE_DIP2PFD(devi));
 
-	npe_query_acpi_mcfg(devi);
 	ddi_report_dev(devi);
 	pcie_fab_init_bus(devi, PCIE_BUS_FINAL);
 
diff --git a/usr/src/uts/i86pc/io/pciex/npe_misc.c b/usr/src/uts/i86pc/io/pciex/npe_misc.c
index 03955325ce..57ae5dc892 100644
--- a/usr/src/uts/i86pc/io/pciex/npe_misc.c
+++ b/usr/src/uts/i86pc/io/pciex/npe_misc.c
@@ -31,9 +31,6 @@
 #include <sys/conf.h>
 #include <sys/pci.h>
 #include <sys/sunndi.h>
-#include <sys/acpi/acpi.h>
-#include <sys/acpi/acpi_pci.h>
-#include <sys/acpica.h>
 #include <sys/pci_cap.h>
 #include <sys/pcie_impl.h>
 #include <sys/x86_archext.h>
@@ -45,7 +42,6 @@
 /*
  * Prototype declaration
  */
-void	npe_query_acpi_mcfg(dev_info_t *dip);
 void	npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
 int	npe_disable_empty_bridges_workaround(dev_info_t *child);
 void	npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl);
@@ -59,54 +55,6 @@ int	npe_enable_htmsi_flag = 1;
 extern uint32_t npe_aer_uce_mask;
 
 /*
- * Query the MCFG table using ACPI.  If MCFG is found, setup the 'ecfg'
- * property accordingly.  If no table is found, the property remains unset; the
- * system will not make use of memory-mapped access to PCI Express
- * configuration space.
- */
-void
-npe_query_acpi_mcfg(dev_info_t *dip)
-{
-	MCFG_TABLE *mcfgp;
-	CFG_BASE_ADDR_ALLOC *cfg_baap;
-	char *cfg_baa_endp;
-	int64_t ecfginfo[4];
-
-	/* Query the MCFG table using ACPI */
-	if (AcpiGetTable(ACPI_SIG_MCFG, 1,
-	    (ACPI_TABLE_HEADER **)&mcfgp) == AE_OK) {
-
-		cfg_baap = (CFG_BASE_ADDR_ALLOC *)mcfgp->CfgBaseAddrAllocList;
-		cfg_baa_endp = ((char *)mcfgp) + mcfgp->Length;
-
-		while ((char *)cfg_baap < cfg_baa_endp) {
-			if (cfg_baap->base_addr != (uint64_t)0 &&
-			    cfg_baap->segment == 0) {
-				/*
-				 * Set up the 'ecfg' property to hold
-				 * base_addr, segment, and first/last bus.
-				 * We only do the first entry that maps
-				 * segment 0; nonzero segments are not yet
-				 * known, or handled.  If they appear,
-				 * we'll need to figure out which bus node
-				 * should have which entry by examining the
-				 * ACPI _SEG method on each bus node.
-				 */
-				ecfginfo[0] = cfg_baap->base_addr;
-				ecfginfo[1] = cfg_baap->segment;
-				ecfginfo[2] = cfg_baap->start_bno;
-				ecfginfo[3] = cfg_baap->end_bno;
-				(void) ndi_prop_update_int64_array(
-				    DDI_DEV_T_NONE, dip, "ecfg",
-				    ecfginfo, 4);
-				break;
-			}
-			cfg_baap++;
-		}
-	}
-}
-
-/*
  * Enable reporting of AER capability next pointer.
  * This needs to be done only for CK8-04 devices
  * by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13
@@ -150,7 +98,8 @@ npe_disable_empty_bridges_workaround(dev_info_t *child)
 }
 
 void
-npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl) {
+npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl)
+{
 	uint32_t regs;
 	uint16_t vendor_id = pci_config_get16(cfg_hdl, PCI_CONF_VENID);
 	uint16_t dev_id = pci_config_get16(cfg_hdl, PCI_CONF_DEVID);
@@ -170,7 +119,8 @@ npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl) {
 }
 
 void
-npe_intel_error_workaround(ddi_acc_handle_t cfg_hdl) {
+npe_intel_error_workaround(ddi_acc_handle_t cfg_hdl)
+{
 	uint32_t regs;
 	uint16_t vendor_id = pci_config_get16(cfg_hdl, PCI_CONF_VENID);
 	uint16_t dev_id = pci_config_get16(cfg_hdl, PCI_CONF_DEVID);
@@ -220,7 +170,8 @@ npe_intel_error_workaround(ddi_acc_handle_t cfg_hdl) {
  * RP is beneath.
  */
 boolean_t
-npe_child_is_pci(dev_info_t *dip) {
+npe_child_is_pci(dev_info_t *dip)
+{
 	char *dev_type;
 	boolean_t parent_is_pci, child_is_pciex;
 
diff --git a/usr/src/uts/i86pc/npe/Makefile b/usr/src/uts/i86pc/npe/Makefile
index 83f1974bee..82f23e0b64 100644
--- a/usr/src/uts/i86pc/npe/Makefile
+++ b/usr/src/uts/i86pc/npe/Makefile
@@ -56,13 +56,11 @@ ALL_TARGET	= $(BINARY)
 INSTALL_TARGET	= $(BINARY) $(ROOTMODULE)
 
 #
-# depends on misc/acpica and misc/pcie
-#
-# acpica supplies ACPI access routines
+# depends on misc/pcie
 #
 # pcie supplies PCI Express fabric error support
 #
-LDFLAGS	+= -Nmisc/acpica -Nmisc/pcie
+LDFLAGS	+= -Nmisc/pcie
 
 #
 # Name of the module is needed by the source, to distinguish from other
diff --git a/usr/src/uts/intel/io/pciex/pcie_nvidia.c b/usr/src/uts/intel/io/pciex/pcie_nvidia.c
index b792e6a564..0b521c954f 100644
--- a/usr/src/uts/intel/io/pciex/pcie_nvidia.c
+++ b/usr/src/uts/intel/io/pciex/pcie_nvidia.c
@@ -177,8 +177,6 @@ look_for_any_pciex_device(uchar_t bus)
 boolean_t
 create_pcie_root_bus(uchar_t bus, dev_info_t *dip)
 {
-	pcie_bus_t *bus_p;
-
 	/*
 	 * Currently this is being hard-coded.
 	 * We need to figure out if the root bus does indeed
@@ -199,10 +197,6 @@ create_pcie_root_bus(uchar_t bus, dev_info_t *dip)
 
 	pcie_rc_init_bus(dip);
 
-	/* save base addr in bus_t for pci_cfgacc_xxx() */
-	bus_p = PCIE_DIP2BUS(dip);
-	bus_p->bus_cfgacc_base = mcfg_mem_base;
-
 	return (B_TRUE);
 }