12450 Add support for BCM57765 family devices to bge

Reviewed by: Paul Winder <paul@winders.demon.co.uk>
Approved by: Dan McDonald <danmcd@joyent.com>

10 files changed, 247 insertions, 93 deletions

diff --git a/usr/src/pkg/manifests/driver-network-bge.mf b/usr/src/pkg/manifests/driver-network-bge.mf
index 6ac1368ea0..0dc0ff7a50 100644
--- a/usr/src/pkg/manifests/driver-network-bge.mf
+++ b/usr/src/pkg/manifests/driver-network-bge.mf
@@ -48,6 +48,16 @@ $(i386_ONLY)driver name=bge clone_perms="bge 0666 root sys" \
     alias=pci108e,1648 \
     alias=pci108e,16a7 \
     alias=pci108e,16a8 \
+    alias=pci14e4,0x1682 \
+    alias=pci14e4,0x1686 \
+    alias=pci14e4,0x16b0 \
+    alias=pci14e4,0x16b1 \
+    alias=pci14e4,0x16b2 \
+    alias=pci14e4,0x16b3 \
+    alias=pci14e4,0x16b4 \
+    alias=pci14e4,0x16b5 \
+    alias=pci14e4,0x16b6 \
+    alias=pci14e4,0x16b7 \
     alias=pci14e4,1600 \
     alias=pci14e4,1601 \
     alias=pci14e4,1644 \
@@ -77,6 +87,16 @@ $(i386_ONLY)driver name=bge clone_perms="bge 0666 root sys" \
     alias=pci14e4,16a7 \
     alias=pci14e4,16a8 \
     alias=pci14e4,16c7 \
+    alias=pciex14e4,0x1682 \
+    alias=pciex14e4,0x1686 \
+    alias=pciex14e4,0x16b0 \
+    alias=pciex14e4,0x16b1 \
+    alias=pciex14e4,0x16b2 \
+    alias=pciex14e4,0x16b3 \
+    alias=pciex14e4,0x16b4 \
+    alias=pciex14e4,0x16b5 \
+    alias=pciex14e4,0x16b6 \
+    alias=pciex14e4,0x16b7 \
     alias=pciex14e4,1643 \
     alias=pciex14e4,1655 \
     alias=pciex14e4,1656 \
@@ -106,6 +126,16 @@ $(sparc_ONLY)driver name=bge clone_perms="bge 0666 root sys" \
     alias=pci108e,1648 \
     alias=pci108e,16a7 \
     alias=pci108e,16a8 \
+    alias=pci14e4,0x1682 \
+    alias=pci14e4,0x1686 \
+    alias=pci14e4,0x16b0 \
+    alias=pci14e4,0x16b1 \
+    alias=pci14e4,0x16b2 \
+    alias=pci14e4,0x16b3 \
+    alias=pci14e4,0x16b4 \
+    alias=pci14e4,0x16b5 \
+    alias=pci14e4,0x16b6 \
+    alias=pci14e4,0x16b7 \
     alias=pci14e4,1645 \
     alias=pci14e4,1647 \
     alias=pci14e4,1648 \
@@ -118,6 +148,16 @@ $(sparc_ONLY)driver name=bge clone_perms="bge 0666 root sys" \
     alias=pci14e4,16a7 \
     alias=pci14e4,16a8 \
     alias=pci14e4,16c7 \
+    alias=pciex14e4,0x1682 \
+    alias=pciex14e4,0x1686 \
+    alias=pciex14e4,0x16b0 \
+    alias=pciex14e4,0x16b1 \
+    alias=pciex14e4,0x16b2 \
+    alias=pciex14e4,0x16b3 \
+    alias=pciex14e4,0x16b4 \
+    alias=pciex14e4,0x16b5 \
+    alias=pciex14e4,0x16b6 \
+    alias=pciex14e4,0x16b7 \
     alias=pciex14e4,1655 \
     alias=pciex14e4,1656 \
     alias=pciex14e4,1659 \
diff --git a/usr/src/uts/common/io/bge/bge_chip2.c b/usr/src/uts/common/io/bge/bge_chip2.c
index 0ceb070556..14797ac90f 100644
--- a/usr/src/uts/common/io/bge/bge_chip2.c
+++ b/usr/src/uts/common/io/bge/bge_chip2.c
@@ -243,7 +243,8 @@ bge_ind_get32(bge_t *bgep, bge_regno_t regno)
 
 #ifdef __sparc
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		regno = LE_32(regno);
 	}
 #endif
@@ -270,7 +271,8 @@ bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
 	val = LE_32(val);
 #ifdef __sparc
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		regno = LE_32(regno);
 	}
 #endif
@@ -366,7 +368,8 @@ bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
 	 */
 	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
 	}
 
@@ -378,6 +381,8 @@ bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
 		if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
 		    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
 			prodid = CHIP_ASIC_REV_PROD_ID_GEN2_REG;
+		} else if (DEVICE_57765_SERIES_CHIPSETS(bgep)) {
+			prodid = CHIP_ASIC_REV_PROD_ID_GEN15_REG;
 		}
 		cidp->asic_rev_prod_id = pci_config_get32(handle, prodid);
 	}
@@ -564,7 +569,8 @@ bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
 		} else if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-		           DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+		           DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+			   DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717,
 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
 		} else {
@@ -667,7 +673,8 @@ bge_reg_get64(bge_t *bgep, bge_regno_t regno)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    bge_get_em64t_type() ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
 		regval <<= 32;
 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
@@ -677,7 +684,8 @@ bge_reg_get64(bge_t *bgep, bge_regno_t regno)
 #elif defined(__sparc)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
 		regval <<= 32;
 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
@@ -715,7 +723,8 @@ bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    bge_get_em64t_type() ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		ddi_put32(bgep->io_handle,
 		    PIO_ADDR(bgep, regno), (uint32_t)data);
 		BGE_PCICHK(bgep);
@@ -728,7 +737,8 @@ bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
 #elif defined(__sparc)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		ddi_put32(bgep->io_handle,
 		    PIO_ADDR(bgep, regno + 4), (uint32_t)data);
 		BGE_PCICHK(bgep);
@@ -887,7 +897,8 @@ bge_nic_setwin(bge_t *bgep, bge_regno_t base)
 	}
 #ifdef __sparc
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		base = LE_32(base);
 	}
 #endif
@@ -949,7 +960,8 @@ bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
 
 #ifdef __sparc
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		addr = LE_32(addr);
 	}
 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
@@ -981,7 +993,8 @@ bge_nic_get64(bge_t *bgep, bge_regno_t addr)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    bge_get_em64t_type() ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		data = ddi_get32(bgep->io_handle,
 		    PIO_ADDR(bgep, addr + 4));
 		data <<= 32;
@@ -992,7 +1005,8 @@ bge_nic_get64(bge_t *bgep, bge_regno_t addr)
 #elif defined(__sparc)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep))) {
 		data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
 		data <<= 32;
 		data |= ddi_get32(bgep->io_handle,
@@ -1027,7 +1041,8 @@ bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    bge_get_em64t_type() ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		ddi_put32(bgep->io_handle,
 		    PIO_ADDR(bgep, addr + 4), (uint32_t)data);
 		BGE_PCICHK(bgep);
@@ -1039,7 +1054,8 @@ bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
 #elif defined(__sparc)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		ddi_put32(bgep->io_handle,
 		    PIO_ADDR(bgep, addr + 4), (uint32_t)data);
 		BGE_PCICHK(bgep);
@@ -1082,7 +1098,8 @@ bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    bge_get_em64t_type() ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
 		    (uint32_t)(*p));
 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
@@ -1099,7 +1116,8 @@ bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
 #elif defined(__sparc)
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
 		    (uint32_t)(*p));
 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
@@ -1801,7 +1819,8 @@ bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
 			    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
-			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
+			    DEVICE_5714_SERIES_CHIPSETS(bgep) ||
+			    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 				bge_reg_set32(bgep, NVM_ACCESS_REG,
 				    NVM_ACCESS_ENABLE);
 			}
@@ -1811,7 +1830,8 @@ bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
 			    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
-			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
+			    DEVICE_5714_SERIES_CHIPSETS(bgep) ||
+			    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
 				    NVM_ACCESS_ENABLE);
 			}
@@ -1822,7 +1842,8 @@ bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
 			    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
-			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
+			    DEVICE_5714_SERIES_CHIPSETS(bgep) ||
+			    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 				bge_reg_set32(bgep, NVM_ACCESS_REG,
 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
 			}
@@ -1834,7 +1855,8 @@ bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
 			    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
-			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
+			    DEVICE_5714_SERIES_CHIPSETS(bgep) ||
+			    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
 			}
@@ -2047,6 +2069,16 @@ bge_nvmem_id(bge_t *bgep)
 	case DEVICE_ID_5714S:
 	case DEVICE_ID_5715C:
 	case DEVICE_ID_5715S:
+	case DEVICE_ID_57761:
+	case DEVICE_ID_57762:
+	case DEVICE_ID_57765:
+	case DEVICE_ID_57766:
+	case DEVICE_ID_57781:
+	case DEVICE_ID_57782:
+	case DEVICE_ID_57785:
+	case DEVICE_ID_57786:
+	case DEVICE_ID_57791:
+	case DEVICE_ID_57795:
 		config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
 		if (config1 & NVM_CFG1_FLASH_MODE)
 			if (config1 & NVM_CFG1_BUFFERED_MODE)
@@ -2603,6 +2635,16 @@ bge_chip_id_init(bge_t *bgep)
 	case DEVICE_ID_5724:
 	case DEVICE_ID_5725:
 	case DEVICE_ID_5727:
+	case DEVICE_ID_57761:
+	case DEVICE_ID_57762:
+	case DEVICE_ID_57765:
+	case DEVICE_ID_57766:
+	case DEVICE_ID_57781:
+	case DEVICE_ID_57782:
+	case DEVICE_ID_57785:
+	case DEVICE_ID_57786:
+	case DEVICE_ID_57791:
+	case DEVICE_ID_57795:
 		if (cidp->device == DEVICE_ID_5717) {
 			cidp->chip_label = 5717;
 		} else if (cidp->device == DEVICE_ID_5718) {
@@ -2620,9 +2662,30 @@ bge_chip_id_init(bge_t *bgep)
 			cidp->chip_label = 5724;
 		} else if (cidp->device == DEVICE_ID_5725) {
 			cidp->chip_label = 5725;
-		} else /* (cidp->device == DEVICE_ID_5727) */ {
+		} else if (cidp->device == DEVICE_ID_5727) {
 			cidp->chip_label = 5727;
+		} else if (cidp->device == DEVICE_ID_57761) {
+			cidp->chip_label = 57761;
+		} else if (cidp->device == DEVICE_ID_57762) {
+			cidp->chip_label = 57762;
+		} else if (cidp->device == DEVICE_ID_57765) {
+			cidp->chip_label = 57765;
+		} else if (cidp->device == DEVICE_ID_57766) {
+			cidp->chip_label = 57766;
+		} else if (cidp->device == DEVICE_ID_57781) {
+			cidp->chip_label = 57781;
+		} else if (cidp->device == DEVICE_ID_57782) {
+			cidp->chip_label = 57782;
+		} else if (cidp->device == DEVICE_ID_57785) {
+			cidp->chip_label = 57785;
+		} else if (cidp->device == DEVICE_ID_57786) {
+			cidp->chip_label = 57786;
+		} else if (cidp->device == DEVICE_ID_57791) {
+			cidp->chip_label = 57791;
+		} else if (cidp->device == DEVICE_ID_57795) {
+			cidp->chip_label = 57795;
 		}
+
 		cidp->msi_enabled = bge_enable_msi;
 #ifdef __sparc
 		cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT);
@@ -2635,7 +2698,11 @@ bge_chip_id_init(bge_t *bgep)
 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
-		cidp->bge_mlcr_default = MLCR_DEFAULT_5717;
+		if (DEVICE_57765_SERIES_CHIPSETS(bgep)) {
+			cidp->bge_mlcr_default = MLCR_DEFAULT_57765;
+		} else {
+			cidp->bge_mlcr_default = MLCR_DEFAULT_5717;
+		}
 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
 		cidp->statistic_type = BGE_STAT_REG;
@@ -3048,7 +3115,8 @@ bge_chip_id_init(bge_t *bgep)
 	    (cidp->default_mtu > BGE_DEFAULT_MTU)) {
 		if (DEVICE_5714_SERIES_CHIPSETS(bgep) ||
 		    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-		    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+		    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+		    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 			cidp->mbuf_lo_water_rdma =
 			    RDMA_MBUF_LOWAT_5714_JUMBO;
 			cidp->mbuf_lo_water_rmac =
@@ -3210,7 +3278,8 @@ bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
 		    DEVICE_5721_SERIES_CHIPSETS(bgep) ||
 		    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 		    DEVICE_5714_SERIES_CHIPSETS(bgep) ||
-		    DEVICE_5906_SERIES_CHIPSETS(bgep)) {
+		    DEVICE_5906_SERIES_CHIPSETS(bgep) ||
+		    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 			regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
 			if (bgep->chipid.pci_type == BGE_PCI_E) {
 				if (bgep->chipid.asic_rev ==
@@ -3298,7 +3367,8 @@ bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
 			}
 
 			if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-			    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+			    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+			    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 				val16 = pci_config_get16(bgep->cfg_handle,
 				                         PCI_CONF_DEV_CTRL_5717);
 				val16 &= ~READ_REQ_SIZE_MASK;
@@ -3460,7 +3530,8 @@ bge_sync_mac_modes(bge_t *bgep)
 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) {
 		if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
 		    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
-		    DEVICE_5714_SERIES_CHIPSETS(bgep))
+		    DEVICE_5714_SERIES_CHIPSETS(bgep) ||
+		    DEVICE_57765_SERIES_CHIPSETS(bgep))
 			macmode |= ETHERNET_MODE_PORTMODE_GMII;
 		else
 			macmode |= ETHERNET_MODE_PORTMODE_TBI;
@@ -4023,7 +4094,8 @@ bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
 #endif
 
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		bge_reg_set32(bgep, FAST_BOOT_PC, 0);
 		if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
 			retval = DDI_FAILURE;
@@ -4055,6 +4127,18 @@ bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
 		bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
 
 	/*
+	 * In the 57765 family of devices we need to work around an apparent
+	 * transmit hang by dorking with the PCIe serdes training clocks.
+	 */
+	if (DEVICE_57765_SERIES_CHIPSETS(bgep) &&
+	    (CHIP_ASIC_REV_PROD_ID(bgep) >> 8) != CHIP_ASIC_REV_57765_AX) {
+		tmp = bge_reg_get32(bgep, CPMU_PADRNG_CTL_REG);
+		tmp |= CPMU_PADRNG_CTL_RDIV2;
+		bge_reg_set32(bgep, CPMU_PADRNG_CTL_REG, tmp);
+	}
+
+
+	/*
 	 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
 	 * not be changed.
 	 */
@@ -4353,7 +4437,8 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
 	    MODE_HOST_STACK_UP);
 
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)
 		          ? RDMA_RSRV_CTRL_REG2 : RDMA_RSRV_CTRL_REG;
 		regval = bge_reg_get32(bgep, reg);
@@ -4459,7 +4544,8 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
 	if (bgep->chipid.device == DEVICE_ID_5719)
 		regval |= BUFFER_MANAGER_MODE_NO_TX_UNDERRUN;
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep))
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep))
 		regval |= BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE;
 	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, regval))
 		retval = DDI_FAILURE;
@@ -4471,17 +4557,24 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
 	 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
 	 */
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING];
 		bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG,
 		    brp->desc.cookie.dmac_laddress);
 		bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8,
 		    (brp->desc.nslots) << 16 | brp->buf[0].size << 2);
-		bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
-		    NIC_MEM_SHADOW_BUFF_STD_5717);
-	} else
+		if (DEVICE_57765_SERIES_CHIPSETS(bgep)) {
+			bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
+			    NIC_MEM_SHADOW_BUFF_STD);
+		} else {
+			bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
+			    NIC_MEM_SHADOW_BUFF_STD_5717);
+		}
+	} else {
 		bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
 		    &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
+	}
 
 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
 		bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
@@ -4673,7 +4766,8 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
 	else
 		coalmode = 0;
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep))
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep))
 		coalmode = COALESCE_CLR_TICKS_RX;
 	if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
 		retval = DDI_FAILURE;
@@ -4753,6 +4847,10 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
 
 	drv_usecwait(40);
 
+	/*
+	 * These chipsets no longer use the rdprio logic (bits 31:30 are
+	 * reserved).
+	 */
 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
 	    DEVICE_5725_SERIES_CHIPSETS(bgep))
@@ -4797,7 +4895,8 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
 	 * Steps 89-90: enable Transmit & Receive MAC Engines
 	 */
 	regval = 0;
-	if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
+	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		regval |= TRANSMIT_MODE_MBUF_LOCKUP_FIX;
 	}
 	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, regval))
@@ -4911,7 +5010,8 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
 #endif
 
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717,
 		    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
 #if 0
@@ -5076,7 +5176,8 @@ bge_intr(caddr_t arg1, caddr_t arg2)
 		 */
 		regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
 		if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-		      DEVICE_5725_SERIES_CHIPSETS(bgep)) &&
+		      DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+		      DEVICE_57765_SERIES_CHIPSETS(bgep)) &&
 		    (regval & MLCR_INTA_STATE)) {
 			if (bge_check_acc_handle(bgep, bgep->io_handle)
 			    != DDI_FM_OK)
@@ -6413,7 +6514,8 @@ bge_nic_read32(bge_t *bgep, bge_regno_t addr)
 	}
 #else
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		addr = LE_32(addr);
 	}
 #endif
diff --git a/usr/src/uts/common/io/bge/bge_hw.h b/usr/src/uts/common/io/bge/bge_hw.h
index 506b97774e..7dfb86fb0d 100644
--- a/usr/src/uts/common/io/bge/bge_hw.h
+++ b/usr/src/uts/common/io/bge/bge_hw.h
@@ -109,6 +109,16 @@ extern "C" {
 #define	DEVICE_ID_5906			0x1712
 #define	DEVICE_ID_5906M			0x1713
 #define	DEVICE_ID_57780			0x1692
+#define	DEVICE_ID_57761			0x16b0
+#define	DEVICE_ID_57762			0x1682
+#define	DEVICE_ID_57765			0x16b4
+#define	DEVICE_ID_57766			0x1686
+#define	DEVICE_ID_57781			0x16b1
+#define	DEVICE_ID_57782			0x16b7
+#define	DEVICE_ID_57785			0x16b5
+#define	DEVICE_ID_57786			0x16b3
+#define	DEVICE_ID_57791			0x16b2
+#define	DEVICE_ID_57795			0x16b6
 
 #define	REVISION_ID_5700_B0		0x10
 #define	REVISION_ID_5700_B2		0x12
@@ -227,6 +237,23 @@ extern "C" {
 		(bgep->chipid.device == DEVICE_ID_5906M))
 
 /*
+ * Even though the hardware register calls this the 57785 family, all of the
+ * BSDs call this the 57765 series, so we call it that way to make it more
+ * similar.
+ */
+#define	DEVICE_57765_SERIES_CHIPSETS(bgep) \
+		((bgep->chipid.device == DEVICE_ID_57761) || \
+		(bgep->chipid.device == DEVICE_ID_57762) || \
+		(bgep->chipid.device == DEVICE_ID_57765) || \
+		(bgep->chipid.device == DEVICE_ID_57766) || \
+		(bgep->chipid.device == DEVICE_ID_57781) || \
+		(bgep->chipid.device == DEVICE_ID_57782) || \
+		(bgep->chipid.device == DEVICE_ID_57785) || \
+		(bgep->chipid.device == DEVICE_ID_57786) || \
+		(bgep->chipid.device == DEVICE_ID_57791) || \
+		(bgep->chipid.device == DEVICE_ID_57795))
+
+/*
  * Second section:
  *	Offsets of important registers & definitions for bits therein
  */
@@ -334,12 +361,12 @@ extern "C" {
 #define	MHCR_CHIP_ASIC_REV_5704		(0x2 << 28)
 #define	MHCR_CHIP_ASIC_REV_5705		(0x3 << 28)
 #define	MHCR_CHIP_ASIC_REV_5721_5751	(0x4 << 28)
-#define	MHCR_CHIP_ASIC_REV_5714 	(0x5 << 28)
+#define	MHCR_CHIP_ASIC_REV_5714		(0x5 << 28)
 #define	MHCR_CHIP_ASIC_REV_5752		(0x6 << 28)
 #define	MHCR_CHIP_ASIC_REV_5754		(0xb << 28)
 #define	MHCR_CHIP_ASIC_REV_5787		((uint32_t)0xb << 28)
 #define	MHCR_CHIP_ASIC_REV_5755		((uint32_t)0xa << 28)
-#define	MHCR_CHIP_ASIC_REV_5715 	((uint32_t)0x9 << 28)
+#define	MHCR_CHIP_ASIC_REV_5715		((uint32_t)0x9 << 28)
 #define	MHCR_CHIP_ASIC_REV_5906		((uint32_t)0xc << 28)
 /* (0xf << 28) touches all 5717 and 5725 series as well (OK) */
 #define	MHCR_CHIP_ASIC_REV_5723		((uint32_t)0xf << 28)
@@ -348,6 +375,7 @@ extern "C" {
 #define	CHIP_ASIC_REV_5761		0x5761
 #define	CHIP_ASIC_REV_5785		0x5785
 #define	CHIP_ASIC_REV_57780		0x57780
+#define	CHIP_ASIC_REV_57785		0x57785
 
 #define	CHIP_ASIC_REV_5717		0x5717
 #define	CHIP_ASIC_REV_5719		0x5719
@@ -356,6 +384,7 @@ extern "C" {
 
 #define	CHIP_ASIC_REV_PROD_ID_REG	0x000000bc
 #define	CHIP_ASIC_REV_PROD_ID_GEN2_REG	0x000000f4
+#define	CHIP_ASIC_REV_PROD_ID_GEN15_REG	0x000000fc
 
 #define	CHIP_ASIC_REV_5717_B0		0x05717100
 #define	CHIP_ASIC_REV_5717_C0		0x05717200
@@ -367,6 +396,11 @@ extern "C" {
 #define	CHIP_ASIC_REV_5727_B0		0x05762100
 
 /*
+ * Match any Metal Layer Revision.
+ */
+#define	CHIP_ASIC_REV_57765_AX		0x577850
+
+/*
  * PCI DMA read/write Control Register, in PCI config space
  *
  * Note that several fields previously defined here have been deleted
@@ -504,7 +538,7 @@ extern "C" {
 #define	PCI_CONF_DEV_CTRL_5717		0xb4
 #define	READ_REQ_SIZE_MASK		0x7000
 #define	READ_REQ_SIZE_MAX		0x5000
-#define	READ_REQ_SIZE_2K 		0x4000
+#define	READ_REQ_SIZE_2K		0x4000
 #define	DEV_CTRL_NO_SNOOP		0x0800
 #define	DEV_CTRL_RELAXED		0x0010
 
@@ -1144,15 +1178,17 @@ extern "C" {
 #define	JUMBO_RCV_BD_REPLENISH_DEFAULT	0x00000020	/* 32	*/
 
 /*
- * CPMU registers (5717/18/19/20 only)
+ * CPMU registers (5717/18/19/20/57765 only)
  */
 #define	CPMU_CLCK_ORIDE_REG		0x3624
 #define	CPMU_CLCK_ORIDE_MAC_ORIDE_EN	0x80000000
 #define	CPMU_STATUS_REG			0x362c
 #define	CPMU_STATUS_FUNC_NUM		0x20000000
 #define	CPMU_STATUS_FUNC_NUM_SHIFT	29
-#define	CPMU_STATUS_FUNC_NUM_5719 	0xc0000000
+#define	CPMU_STATUS_FUNC_NUM_5719	0xc0000000
 #define	CPMU_STATUS_FUNC_NUM_5719_SHIFT	30
+#define	CPMU_PADRNG_CTL_REG		0x3668
+#define	CPMU_PADRNG_CTL_RDIV2		0x00040000
 
 /*
  * EEE registers (5718/19/20 only)
@@ -1444,6 +1480,12 @@ extern "C" {
 #define	MLCR_DEFAULT_5717		(MLCR_AUTO_SEEPROM_ACCESS)
 
 /*
+ * MLCR_AUTO_SEEPROM_ACCESS is marked reserved in the 57765 family, so we don't
+ * try to enable it like on the 5717.
+ */
+#define	MLCR_DEFAULT_57765		0
+
+/*
  * Serial EEPROM Data/Address Registers (auto-access mode)
  */
 #define	SERIAL_EEPROM_DATA_REG		0x683c
@@ -1544,7 +1586,7 @@ extern "C" {
 
 /*
  * NVM access register
- * Applicable to BCM5721,BCM5751,BCM5752,BCM5714
+ * Applicable to BCM5721,BCM5751,BCM5752,BCM5714,BCM57725
  * and BCM5715 only.
  */
 #define	NVM_ACCESS_REG			0x7024
@@ -1731,7 +1773,7 @@ extern "C" {
 
 /*
  * Third section:
- * 	Hardware-defined data structures
+ *	Hardware-defined data structures
  *
  * Note that the chip is naturally BIG-endian, so, for a big-endian
  * host, the structures defined below match those described in the PRM.
diff --git a/usr/src/uts/common/io/bge/bge_impl.h b/usr/src/uts/common/io/bge/bge_impl.h
index 848f039359..37a927fce5 100644
--- a/usr/src/uts/common/io/bge/bge_impl.h
+++ b/usr/src/uts/common/io/bge/bge_impl.h
@@ -794,8 +794,8 @@ typedef struct bge {
 	/*
 	 * For the BCM5705/5788/5721/5751/5752/5714 and 5715,
 	 * the statistic block is not available,the statistic counter must
-	 * be gotten from statistic registers.And bge_statistics_reg_t record
-	 * the statistic registers value
+	 * be gotten from statistic registers. And bge_statistics_reg_t record
+	 * the statistic registers value.
 	 */
 	bge_statistics_reg_t	*pstats;
 
diff --git a/usr/src/uts/common/io/bge/bge_lint.c b/usr/src/uts/common/io/bge/bge_lint.c
deleted file mode 100644
index 2f51987068..0000000000
--- a/usr/src/uts/common/io/bge/bge_lint.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file and its contents are supplied under the terms of the
- * Common Development and Distribution License ("CDDL"), version 1.0.
- * You may only use this file in accordance with the terms of version
- * 1.0 of the CDDL.
- *
- * A full copy of the text of the CDDL should have accompanied this
- * source.  A copy of the CDDL is also available via the Internet at
- * http://www.illumos.org/license/CDDL.
- */
-
-/*
- * This is a dummy lint file to pacify lint for bge, which due to its upstream,
- * makes it, unfortunately, not realistic to lint. We have a dummy definition to
- * ensure that we don't trigger lint's empty translation unit.
- */
-
-extern int bge_lint;
diff --git a/usr/src/uts/common/io/bge/bge_main2.c b/usr/src/uts/common/io/bge/bge_main2.c
index dc0174c4a3..bc2087e01d 100644
--- a/usr/src/uts/common/io/bge/bge_main2.c
+++ b/usr/src/uts/common/io/bge/bge_main2.c
@@ -83,8 +83,8 @@ static ddi_dma_attr_t dma_attr = {
 	0x00000001,			/* dma_attr_minxfer	*/
 	0x000000000000FFFFull,		/* dma_attr_maxxfer	*/
 	0x00000000FFFFFFFFull,		/* dma_attr_seg		*/
-	1,				/* dma_attr_sgllen 	*/
-	0x00000001,			/* dma_attr_granular 	*/
+	1,				/* dma_attr_sgllen	*/
+	0x00000001,			/* dma_attr_granular	*/
 	DDI_DMA_FLAGERR			/* dma_attr_flags */
 };
 
@@ -2691,7 +2691,8 @@ bge_alloc_bufs(bge_t *bgep)
 	 * Enable PCI relaxed ordering only for RX/TX data buffers
 	 */
 	if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep))) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep))) {
 		if (bge_relaxed_ordering)
 			dma_attr.dma_attr_flags |= DDI_DMA_RELAXED_ORDERING;
 	}
@@ -2727,7 +2728,8 @@ bge_alloc_bufs(bge_t *bgep)
 	           txbuffsize));
 
 	if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep))) {
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep))) {
 		/* no relaxed ordering for descriptors rings? */
 		dma_attr.dma_attr_flags &= ~DDI_DMA_RELAXED_ORDERING;
 	}
@@ -3767,7 +3769,8 @@ bge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
 	 * byte-swapped value to it. So we just write zero first for simplicity.
 	 */
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5725_SERIES_CHIPSETS(bgep))
+	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep))
 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0);
 #else
 	mhcrValue = MHCR_ENABLE_INDIRECT_ACCESS |
diff --git a/usr/src/uts/common/io/bge/bge_mii.c b/usr/src/uts/common/io/bge/bge_mii.c
index 68823b3cba..30cd7c94d9 100644
--- a/usr/src/uts/common/io/bge/bge_mii.c
+++ b/usr/src/uts/common/io/bge/bge_mii.c
@@ -586,7 +586,7 @@ bge_restart_copper(bge_t *bgep, boolean_t powerdown)
 	case MHCR_CHIP_ASIC_REV_5906:
 	case MHCR_CHIP_ASIC_REV_5700:
 	case MHCR_CHIP_ASIC_REV_5701:
-	case MHCR_CHIP_ASIC_REV_5723: /* 5717 and 5725 series as well */
+	case MHCR_CHIP_ASIC_REV_5723: /* 5717, 5725, 57765 series as well */
 	case MHCR_CHIP_ASIC_REV_5721_5751:
 		/*
 		 * Just a plain reset; the "check" code breaks these chips
@@ -1333,7 +1333,8 @@ bge_restart_serdes(bge_t *bgep, boolean_t powerdown)
 	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
 	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
-	    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
+	    DEVICE_5714_SERIES_CHIPSETS(bgep) ||
+	    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 		macmode |= ETHERNET_MODE_PORTMODE_GMII;
 	} else {
 		macmode |= ETHERNET_MODE_PORTMODE_TBI;
@@ -1561,11 +1562,12 @@ bge_check_serdes(bge_t *bgep, boolean_t recheck)
 		 * Don't call function bge_autoneg_serdes() as
 		 * RX_1000BASEX_AUTONEG_REG (0x0448) is not applicable
 		 * to BCM5705, BCM5788, BCM5721, BCM5751, BCM5752,
-		 * BCM5714, and BCM5715 devices.
+		 * BCM5714, BCM5715, and BCM57765 family devices.
 		 */
 		if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
 		    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
-		    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
+		    DEVICE_5714_SERIES_CHIPSETS(bgep) ||
+		    DEVICE_57765_SERIES_CHIPSETS(bgep)) {
 			tx_status = bge_reg_get32(bgep,
 			    TRANSMIT_MAC_STATUS_REG);
 			linkup = BIS(tx_status, TRANSMIT_STATUS_LINK_UP);
diff --git a/usr/src/uts/common/io/bge/bge_send.c b/usr/src/uts/common/io/bge/bge_send.c
index 87e0c0105d..c00f8ac124 100644
--- a/usr/src/uts/common/io/bge/bge_send.c
+++ b/usr/src/uts/common/io/bge/bge_send.c
@@ -451,7 +451,8 @@ start_tx:
 			hw_sbd_p->flags |= SBD_FLAG_TCP_UDP_CKSUM;
 		if (!(bgep->chipid.flags & CHIP_FLAG_NO_JUMBO) &&
 		    (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
-		     DEVICE_5725_SERIES_CHIPSETS(bgep)) &&
+		     DEVICE_5725_SERIES_CHIPSETS(bgep) ||
+		     DEVICE_57765_SERIES_CHIPSETS(bgep)) &&
 		    (txbuf->copy_len > ETHERMAX))
 			hw_sbd_p->flags |= SBD_FLAG_JMB_PKT;
 		hw_sbd_p->flags |= SBD_FLAG_PACKET_END;
diff --git a/usr/src/uts/intel/bge/Makefile b/usr/src/uts/intel/bge/Makefile
index 456cbc9043..95527d4424 100644
--- a/usr/src/uts/intel/bge/Makefile
+++ b/usr/src/uts/intel/bge/Makefile
@@ -39,7 +39,6 @@ UTSBASE		= ../..
 #
 MODULE		= bge
 OBJECTS		= $(BGE_OBJS:%=$(OBJS_DIR)/%)
-LINTS		= $(LINTS_DIR)/bge_lint.ln
 ROOTMODULE	= $(ROOT_DRV_DIR)/$(MODULE)
 CONF_SRCDIR	= $(UTSBASE)/common/io/bge
 
@@ -52,7 +51,6 @@ include $(UTSBASE)/intel/Makefile.intel
 #	Define targets
 #
 ALL_TARGET	= $(BINARY)
-LINT_TARGET	= $(MODULE).lint
 INSTALL_TARGET	= $(BINARY) $(ROOTMODULE) $(ROOT_CONFFILE)
 
 #
@@ -63,7 +61,6 @@ INSTALL_TARGET	= $(BINARY) $(ROOTMODULE) $(ROOT_CONFFILE)
 # to investigate and remove these for maximum lint coverage.
 # Please do not carry these forward to new Makefiles.
 #
-LINTTAGS	+= -erroff=E_BAD_PTR_CAST_ALIGN
 
 CERRWARN	+= $(CNOWARN_UNINIT)
 CERRWARN	+= -_gcc=-Wno-switch
@@ -92,12 +89,6 @@ clean:		$(CLEAN_DEPS)
 
 clobber:	$(CLOBBER_DEPS)
 
-lint:		$(LINT_DEPS)
-
-modlintlib:	$(MODLINTLIB_DEPS)
-
-clean.lint:	$(CLEAN_LINT_DEPS)
-
 install:	$(INSTALL_DEPS)
 
 #
diff --git a/usr/src/uts/sparc/bge/Makefile b/usr/src/uts/sparc/bge/Makefile
index a0b56a51b0..0a8b2cabc4 100644
--- a/usr/src/uts/sparc/bge/Makefile
+++ b/usr/src/uts/sparc/bge/Makefile
@@ -39,7 +39,6 @@ UTSBASE		= ../..
 #
 MODULE		= bge
 OBJECTS		= $(BGE_OBJS:%=$(OBJS_DIR)/%)
-LINTS		= $(LINTS_DIR)/bge_lint.ln
 ROOTMODULE	= $(ROOT_DRV_DIR)/$(MODULE)
 CONF_SRCDIR	= $(UTSBASE)/common/io/bge
 
@@ -52,7 +51,6 @@ include $(UTSBASE)/sparc/Makefile.sparc
 #	Define targets
 #
 ALL_TARGET	= $(BINARY)
-LINT_TARGET	= $(MODULE).lint
 INSTALL_TARGET	= $(BINARY) $(ROOTMODULE) $(ROOT_CONFFILE)
 
 #
@@ -75,7 +73,6 @@ LDFLAGS		+= -dy -N misc/mac
 # to investigate and remove these for maximum lint coverage.
 # Please do not carry these forward to new Makefiles.
 #
-LINTTAGS	+= -erroff=E_BAD_PTR_CAST_ALIGN
 
 CERRWARN	+= $(CNOWARN_UNINIT)
 CERRWARN	+= -_gcc=-Wno-switch
@@ -96,12 +93,6 @@ clean:		$(CLEAN_DEPS)
 
 clobber:	$(CLOBBER_DEPS)
 
-lint:		$(LINT_DEPS)
-
-modlintlib:	$(MODLINTLIB_DEPS)
-
-clean.lint:	$(CLEAN_LINT_DEPS)
-
 install:	$(INSTALL_DEPS)
 
 #