diff options
| author | Robert Mustacchi <rm@joyent.com> | 2019-05-01 16:19:13 +0000 |
|---|---|---|
| committer | Robert Mustacchi <rm@joyent.com> | 2019-05-09 03:17:34 +0000 |
| commit | d0e58ef5d66890a3cd67c9c6eb8c823f9865a70f (patch) | |
| tree | 4ceb1df56c86753eb2548678b40e7ce33d96b5ba /usr/src/man/man3cpc | |
| parent | c18e9bc303e04175d63c5c51206b2ce6f6efe6a4 (diff) | |
| download | illumos-gate-d0e58ef5d66890a3cd67c9c6eb8c823f9865a70f.tar.gz | |
10896 Want support for AMD Zen CPC events
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
Reviewed by: Dan McDonald <danmcd@joyent.com>
Approved by: Richard Lowe <richlowe@richlowe.net>
Diffstat (limited to 'usr/src/man/man3cpc')
| -rw-r--r-- | usr/src/man/man3cpc/cpc.3cpc | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/usr/src/man/man3cpc/cpc.3cpc b/usr/src/man/man3cpc/cpc.3cpc index 9b5edbabb1..d25dc393f8 100644 --- a/usr/src/man/man3cpc/cpc.3cpc +++ b/usr/src/man/man3cpc/cpc.3cpc @@ -3,7 +3,7 @@ .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] .\" Copyright (c) 2019, Joyent, Inc. -.Dd January 8, 2019 +.Dd March 25, 2019 .Dt CPC 3CPC .Os .Sh NAME @@ -78,11 +78,10 @@ and .Xr cpc_walk_generic_events_pic 3CPC functions allow an application to determine the generic events supported on the underlying platform. -.Ss Processor Specific Events -Manual pages specific to events for recent Intel processors are -available. -The following manual pages cover the following Intel processor models -which are listed in hexadecimal: +.Ss Intel Processor Specific Events +The following manual pages provide more detailed information on the +events available for the specific Intel processor models. +The covered processor models are listed in hexadecimal. .Bl -tag -width Xr .It Xr bdw_de_events 3CPC Intel Broadwell-DE events; covers model 56h. @@ -127,6 +126,15 @@ Intel Westmere-EP-SP events; covers model 25h. .It Xr wsm_ex_events 3CPC Intel Westmere-EX events; covers model 2fh. .El +.Ss AMD Processor Specific Events +The following manual pages provide more detailed information on the +events available for the specific AMD processor models. +The covered processor families are listed in hexadecimal. +.Bl -tag -width Xr +.It Xr amd_f17h_events 3CPC +AMD Family 17h processors, including models 00-2fh. +Include Ryzen, ThreadRipper, and EPYC branded processors. +.El .Ss Using Attributes Some processors have advanced performance counter capabilities that are configured with attributes. |