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| author | eota <none@none> | 2007-09-20 14:16:47 -0700 |
|---|---|---|
| committer | eota <none@none> | 2007-09-20 14:16:47 -0700 |
| commit | dd4eeefdb8e4583c47e28a7f315db6087931ef06 (patch) | |
| tree | 42d484ac74ab436d78007be666c66d144c55890b /usr/src/uts/common/io/avintr.c | |
| parent | 55c4b5faaa3d3ff8bea0d08505e7ea0850b949e8 (diff) | |
| download | illumos-gate-dd4eeefdb8e4583c47e28a7f315db6087931ef06.tar.gz | |
PSARC 2007/402 Driver Periodic Timeouts
4977787 Official DDI interface is required for periodic timeout requests
Diffstat (limited to 'usr/src/uts/common/io/avintr.c')
| -rw-r--r-- | usr/src/uts/common/io/avintr.c | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/usr/src/uts/common/io/avintr.c b/usr/src/uts/common/io/avintr.c index 6f3549aa8b..4cf39ac851 100644 --- a/usr/src/uts/common/io/avintr.c +++ b/usr/src/uts/common/io/avintr.c @@ -88,10 +88,26 @@ struct autovec *nmivect = NULL; struct av_head autovect[MAX_VECT]; struct av_head softvect[LOCK_LEVEL + 1]; kmutex_t av_lock; +/* + * These are software interrupt handlers dedicated to ddi timer. + * The interrupt levels up to 10 are supported, but high interrupts + * must not be used there. + */ +ddi_softint_hdl_impl_t softlevel_hdl[DDI_IPL_10] = { + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 1 */ + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 2 */ + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 3 */ + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 4 */ + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 5 */ + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 6 */ + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 7 */ + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 8 */ + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 9 */ + {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}, /* level 10 */ +}; ddi_softint_hdl_impl_t softlevel1_hdl = {0, NULL, NULL, NULL, 0, NULL, NULL, NULL}; - /* * clear/check softint pending flag corresponding for * the current CPU @@ -578,10 +594,21 @@ kdi_siron(void) void siron(void) { + /* Level 1 software interrupt */ (*setsoftint)(1, softlevel1_hdl.ih_pending); } /* + * Trigger software interrupts dedicated to ddi timer. + */ +void +sir_on(int level) +{ + ASSERT(level >= DDI_IPL_1 && level <= DDI_IPL_10); + (*setsoftint)(level, softlevel_hdl[level-1].ih_pending); +} + +/* * The handler which is executed on the target CPU. */ /*ARGSUSED*/ |