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| author | Robert Mustacchi <rm@fingolfin.org> | 2021-12-21 15:02:21 +0000 |
|---|---|---|
| committer | Robert Mustacchi <rm@fingolfin.org> | 2022-01-05 21:47:29 +0000 |
| commit | e6d654cc98379582914881933e6f5d40c52b97d5 (patch) | |
| tree | c8445d1bf6d675d3fd133da44660223ed87508be /usr/src/uts/common | |
| parent | 9d6ca3965c3358c32eb68544fe91ff8ad9c3fcde (diff) | |
| download | illumos-gate-e6d654cc98379582914881933e6f5d40c52b97d5.tar.gz | |
14323 Note new PCIe caps from the PCI-SIG
Reviewed by: Andy Fiddaman <andy@omnios.org>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Dan McDonald <danmcd@joyent.com>
Diffstat (limited to 'usr/src/uts/common')
| -rw-r--r-- | usr/src/uts/common/sys/pcie.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/usr/src/uts/common/sys/pcie.h b/usr/src/uts/common/sys/pcie.h index 9c57d647e5..1901b200d8 100644 --- a/usr/src/uts/common/sys/pcie.h +++ b/usr/src/uts/common/sys/pcie.h @@ -24,6 +24,7 @@ */ /* * Copyright 2019 Joyent, Inc. + * Copyright 2021 Oxide Computer Company */ #ifndef _SYS_PCIE_H @@ -588,6 +589,10 @@ extern "C" { #define PCIE_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ #define PCIE_EXT_CAP_ID_DEV3 0x2F /* Device 3 */ #define PCIE_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encr. */ +#define PCIE_EXT_CAP_ID_PL64GT 0x31 /* Physical Layer 64.0 GT/s */ +#define PCIE_EXT_CAP_ID_FLIT_LOG 0x32 /* Flit Logging */ +#define PCIE_EXT_CAP_ID_FLIT_PERF 0x33 /* Flit Perf. Measurement */ +#define PCIE_EXT_CAP_ID_FLIT_ERR 0x34 /* Flit Error Injection */ /* * PCI-Express Advanced Error Reporting Extended Capability Offsets |