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| author | Keith M Wesolowski <wesolows@oxide.computer> | 2022-11-09 07:00:30 +0000 |
|---|---|---|
| committer | Robert Mustacchi <rm@fingolfin.org> | 2022-11-16 21:54:43 +0000 |
| commit | 4adf43b0b51d2123d4add8287f0e31facb0cbab1 (patch) | |
| tree | 2b2ed7ac807fd843c1a10d6178d9e08f982d3e16 /usr/src/uts/intel/sys/amdzen/umc.h | |
| parent | 3cfbf5be38df79575cc7d2705bb059b2feca1332 (diff) | |
| download | illumos-gate-4adf43b0b51d2123d4add8287f0e31facb0cbab1.tar.gz | |
15165 SMN accesses are size-sensitive
Reviewed by: Robert Mustacchi <rm@fingolin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Richard Lowe <richlowe@richlowe.net>
Diffstat (limited to 'usr/src/uts/intel/sys/amdzen/umc.h')
| -rw-r--r-- | usr/src/uts/intel/sys/amdzen/umc.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/usr/src/uts/intel/sys/amdzen/umc.h b/usr/src/uts/intel/sys/amdzen/umc.h index a06c2021eb..ca018c89af 100644 --- a/usr/src/uts/intel/sys/amdzen/umc.h +++ b/usr/src/uts/intel/sys/amdzen/umc.h @@ -76,7 +76,8 @@ extern "C" { * UMC Channel registers. These are in SMN Space. DDR4 and DDR5 based UMCs share * the same base address, somewhat surprisingly. This constructs the appropriate * offset and ensures that a caller doesn't exceed the number of known instances - * of the register. See smn.h for additional details on SMN addressing. + * of the register. See smn.h for additional details on SMN addressing. All + * UMC registers are 32 bits wide; we check for violations. */ static inline smn_reg_t @@ -93,6 +94,7 @@ amdzen_umc_smn_reg(const uint8_t umcno, const smn_reg_def_t def, const uint32_t nents = (def.srd_nents == 0) ? 1 : (const uint32_t)def.srd_nents; + ASSERT0(def.srd_size); ASSERT3S(def.srd_unit, ==, SMN_UNIT_UMC); ASSERT0(def.srd_reg & APERTURE_MASK); ASSERT3U(umc32, <, 12); |