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authorRobert Mustacchi <rm@fingolfin.org>2021-08-10 11:25:18 -0700
committerRobert Mustacchi <rm@fingolfin.org>2021-08-12 15:51:55 -0700
commitbdc24928e6e072b3224ad4bcd1769e68dc91f970 (patch)
treed0122d6b5b1a4e88bb8072984830dd5eecd18127 /usr/src/uts
parentf2047739583ce5779dd354aec92a3f683e1d1014 (diff)
downloadillumos-gate-bdc24928e6e072b3224ad4bcd1769e68dc91f970.tar.gz
14013 Update Zen 3 cpuid_subr.c info
Reviewed by: Andy Fiddaman <andy@omnios.org> Reviewed by: Toomas Soome <tsoome@me.com> Approved by: Richard Lowe <richlowe@richlowe.net>
Diffstat (limited to 'usr/src/uts')
-rw-r--r--usr/src/uts/i86pc/os/cpuid_subr.c17
-rw-r--r--usr/src/uts/intel/sys/x86_archext.h11
2 files changed, 27 insertions, 1 deletions
diff --git a/usr/src/uts/i86pc/os/cpuid_subr.c b/usr/src/uts/i86pc/os/cpuid_subr.c
index 934b5d547d..18d242eb55 100644
--- a/usr/src/uts/i86pc/os/cpuid_subr.c
+++ b/usr/src/uts/i86pc/os/cpuid_subr.c
@@ -34,7 +34,7 @@
* Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
* Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
* Copyright 2019 Joyent, Inc.
- * Copyright 2020 Oxide Computer Company
+ * Copyright 2021 Oxide Computer Company
*/
/*
@@ -656,6 +656,21 @@ static const struct amd_rev_mapent {
*/
{ 0x18, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_HYGON_18_DN_A1, "DN_A1",
A_SKTS_18 },
+
+ /*
+ * =============== AuthenticAMD Family 0x19 ===============
+ */
+ { 0x19, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_19_GN_A0, "GN-A0",
+ A_SKTS_19 },
+ { 0x19, 0x01, 0x01, 0x0, 0x0, X86_CHIPREV_AMD_19_GN_B0, "GN-B0",
+ A_SKTS_19 },
+ { 0x19, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_19_GN_B1, "GN-B1",
+ A_SKTS_19 },
+
+ { 0x19, 0x21, 0x21, 0x0, 0x0, X86_CHIPREV_AMD_19_VMR_B0, "VMR-B0",
+ A_SKTS_20 },
+ { 0x19, 0x21, 0x21, 0x2, 0x2, X86_CHIPREV_AMD_19_VMR_B1, "VMR-B1",
+ A_SKTS_20 },
};
/*
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h
index c7de3357db..1e63b80cab 100644
--- a/usr/src/uts/intel/sys/x86_archext.h
+++ b/usr/src/uts/intel/sys/x86_archext.h
@@ -979,6 +979,17 @@ extern "C" {
#define X86_CHIPREV_HYGON_18_DN_A1 \
_X86_CHIPREV_MKREV(X86_VENDOR_HYGON, 0x18, 0x0001)
+#define X86_CHIPREV_AMD_19_GN_A0 \
+ _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0000)
+#define X86_CHIPREV_AMD_19_GN_B0 \
+ _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0001)
+#define X86_CHIPREV_AMD_19_GN_B1 \
+ _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0002)
+#define X86_CHIPREV_AMD_19_VMR_B0 \
+ _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0003)
+#define X86_CHIPREV_AMD_19_VMR_B1 \
+ _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0004)
+
/*
* Various socket/package types, extended as the need to distinguish
* a new type arises. The top 8 byte identfies the vendor and the