6279871 need interim core level load balancing solution for Niagara

7 files changed, 58 insertions, 5 deletions

diff --git a/usr/src/uts/common/os/chip.c b/usr/src/uts/common/os/chip.c
index 80890234d8..df0eeca4f8 100644
--- a/usr/src/uts/common/os/chip.c
+++ b/usr/src/uts/common/os/chip.c
@@ -134,6 +134,17 @@ chip_kstat_create(chip_t *chp)
 	kstat_t		*chip_kstat;
 
 	ASSERT(MUTEX_HELD(&cpu_lock));
+	/*
+	 * Note: On sun4v systems, chip kstats don't currently
+	 * exist, since "chip" structures and policies are being
+	 * leveraged to implement core level balancing, and exporting
+	 * chip kstats in light of this would be both misleading
+	 * and confusing.
+	 */
+#ifdef	sun4v
+	return;
+	/*NOTREACHED*/
+#endif
 
 	if (chp->chip_kstat != NULL)
 		return;		/* already initialized */
@@ -200,8 +211,14 @@ chip_cpu_init(cpu_t *cp)
 
 	/*
 	 * Call into the platform to fetch this cpu's chipid
+	 * On sun4v platforms, the chip infrastructure is currently being
+	 * leveraged to implement core level load balancing.
 	 */
+#ifdef	sun4v
+	cid = chip_plat_get_pipeid(cp);
+#else
 	cid = chip_plat_get_chipid(cp);
+#endif /* sun4v */
 
 	chp = chip_find(cid);
 	if (chp == NULL) {
diff --git a/usr/src/uts/common/sys/chip.h b/usr/src/uts/common/sys/chip.h
index 98d702a54e..226efb74cd 100644
--- a/usr/src/uts/common/sys/chip.h
+++ b/usr/src/uts/common/sys/chip.h
@@ -42,6 +42,7 @@ extern "C" {
 #include <sys/processor.h>
 #include <sys/bitmap.h>
 #include <sys/atomic.h>
+#include <sys/types.h>
 
 /*
  * Chip types
@@ -181,6 +182,10 @@ void		chip_kstat_create(chip_t *);
  * Platform chip operations
  */
 chipid_t	chip_plat_get_chipid(cpu_t *);
+#ifdef	sun4v
+id_t		chip_plat_get_pipeid(cpu_t *);
+#endif /* sun4v */
+
 void		chip_plat_define_chip(cpu_t *, chip_def_t *);
 int		chip_plat_get_clogid(cpu_t *);
 
diff --git a/usr/src/uts/sun4/os/mp_startup.c b/usr/src/uts/sun4/os/mp_startup.c
index f34965baa6..2d9662e5f7 100644
--- a/usr/src/uts/sun4/os/mp_startup.c
+++ b/usr/src/uts/sun4/os/mp_startup.c
@@ -413,12 +413,10 @@ setup_cpu_common(int cpuid)
 	init_intr_threads(cp);
 
 	/*
-	 * Add CPU to list of available CPUs, and associate it
-	 * with a chip..  It'll be on the active list after it is
-	 * started.
+	 * Add CPU to list of available CPUs.
+	 * It'll be on the active list after it is started.
 	 */
 	cpu_add_unit(cp);
-	chip_cpu_init(cp);
 
 	/*
 	 * Allocate and init cpu module private data structures,
@@ -426,6 +424,11 @@ setup_cpu_common(int cpuid)
 	 */
 	cpu_init_private(cp);
 
+	/*
+	 * Associate this CPU with a physical processor
+	 */
+	chip_cpu_init(cp);
+
 	cpu_intrq_setup(cp);
 }
 
diff --git a/usr/src/uts/sun4v/cpu/generic.c b/usr/src/uts/sun4v/cpu/generic.c
index b56a51e0ce..8c29c18b42 100644
--- a/usr/src/uts/sun4v/cpu/generic.c
+++ b/usr/src/uts/sun4v/cpu/generic.c
@@ -215,6 +215,12 @@ dtrace_flush_sec(uintptr_t addr)
 void
 cpu_init_private(struct cpu *cp)
 {
+	/*
+	 * The cpu_ipipe field is initialized based on the execution
+	 * unit sharing information from the Machine Description table.
+	 * It defaults to the CPU id in the absence of such information.
+	 */
+	cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id);
 }
 
 void
diff --git a/usr/src/uts/sun4v/cpu/niagara.c b/usr/src/uts/sun4v/cpu/niagara.c
index 862215d3c5..3c697b5815 100644
--- a/usr/src/uts/sun4v/cpu/niagara.c
+++ b/usr/src/uts/sun4v/cpu/niagara.c
@@ -238,6 +238,15 @@ cpu_init_private(struct cpu *cp)
 {
 	extern int niagara_kstat_init(void);
 
+	/*
+	 * This code change assumes that the virtual cpu ids are identical
+	 * to the physical cpu ids which is true for ontario but not for
+	 * niagara in general.
+	 * This is a temporary fix which will later be modified to obtain
+	 * the execution unit sharing information from MD table.
+	 */
+	cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id / 4);
+
 	ASSERT(MUTEX_HELD(&cpu_lock));
 	if (niagara_cpucnt++ == 0) {
 		(void) niagara_kstat_init();
diff --git a/usr/src/uts/sun4v/os/cmp.c b/usr/src/uts/sun4v/os/cmp.c
index f8e8dfab6f..236af92900 100644
--- a/usr/src/uts/sun4v/os/cmp.c
+++ b/usr/src/uts/sun4v/os/cmp.c
@@ -104,7 +104,7 @@ chip_plat_get_chipid(cpu_t *cp)
 void
 chip_plat_define_chip(cpu_t *cp, chip_def_t *cd)
 {
-	cd->chipd_type = CHIP_DEFAULT;
+	cd->chipd_type = CHIP_CMP_SHARED_CACHE;
 
 	/*
 	 * Define any needed adjustment of rechoose_interval
@@ -113,3 +113,15 @@ chip_plat_define_chip(cpu_t *cp, chip_def_t *cd)
 	 */
 	cd->chipd_rechoose_adj = 0;
 }
+
+/*
+ * Return a pipeline "id" for the given cpu_t
+ * cpu_t's sharing the same instruction pipeline
+ * should map to the same "id"
+ */
+
+id_t
+chip_plat_get_pipeid(cpu_t *cp)
+{
+	return (cp->cpu_m.cpu_ipipe);
+}
diff --git a/usr/src/uts/sun4v/sys/machcpuvar.h b/usr/src/uts/sun4v/sys/machcpuvar.h
index ee0f7f7498..867c3894fe 100644
--- a/usr/src/uts/sun4v/sys/machcpuvar.h
+++ b/usr/src/uts/sun4v/sys/machcpuvar.h
@@ -151,6 +151,7 @@ struct	machcpu {
 	uint64_t	mondo_data_ra;		/* mono data pa */
 	uint16_t	*cpu_list;		/* uint16_t [NCPU] */
 	uint64_t	cpu_list_ra;		/* cpu list ra */
+	id_t		cpu_ipipe;		/* cpu exec unit id */
 };
 
 typedef	struct machcpu	machcpu_t;