6497789 IO box Linkup sequence is not compliant with Oberon HW spec 1.04

6510353 incorrect serialid format in apid for Sun IOboxes

3 files changed, 31 insertions, 20 deletions

diff --git a/usr/src/cmd/devfsadm/cfg_link.c b/usr/src/cmd/devfsadm/cfg_link.c
index 17ecf211e6..09c674ea5e 100644
--- a/usr/src/cmd/devfsadm/cfg_link.c
+++ b/usr/src/cmd/devfsadm/cfg_link.c
@@ -20,7 +20,7 @@
  */
 
 /*
- * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -541,7 +541,7 @@ DEF:
  *	3) <IOB_PRE string>
  *
  * PROP_SERID encoding <64-bit int: msb ... lsb>:
- * <24 bits: vendor id><40 bits: serial number>
+ * <24 bits: IEEE company id><40 bits: serial number>
  *
  * sun encoding of 40 bit serial number:
  * first byte = device type indicator (ignored in naming scheme)
@@ -553,27 +553,30 @@ pci_cfg_iob_name(di_minor_t minor, di_node_t node, di_prom_handle_t ph,
     char *buf, int bufsz)
 {
 	int64_t *seridp;
-	int64_t serid;
-	char *idstr;
+	uint64_t serid;
 
 	if (di_prop_lookup_int64(DDI_DEV_T_ANY, node, PROP_SERID,
 	    &seridp) < 1) {
 		(void) strlcpy(buf, IOB_PRE, bufsz);
 		return (1);
 	}
-	serid = *seridp;
+	serid = (uint64_t)*seridp;
 
-	if (serid >> 40 != VENDID_SUN) {
+	if ((serid >> 40) != (uint64_t)IEEE_SUN_ID) {
 		(void) snprintf(buf, bufsz, "%s%llx", IOB_PRE, serid);
 		return (1);
 	}
 
-	serid &= SIZE2MASK64(40);
-	idstr = (char *)&serid;
-	idstr[sizeof (serid) - 1] = '\0';
-	/* skip device type indicator */
-	idstr++;
-	(void) snprintf(buf, bufsz, "%s%s", IOB_PRE, idstr);
+	/*
+	 * skip 32 bits because the first 3 bytes are the company id and the
+	 * next byte is the PCIe or PCI-X indicator. The last 4 bytes
+	 * is being treated as raw unsigned integer instead of a string
+	 * because some of the bytes are 0x0 (NULL).
+	 */
+
+	(void) snprintf(buf, bufsz, "%s%08x", IOB_PRE,
+	    (uint32_t)(SIZE2MASK64(32) & serid));
+
 	return (1);
 }
 
diff --git a/usr/src/cmd/devfsadm/cfg_link.h b/usr/src/cmd/devfsadm/cfg_link.h
index e1a62b45e9..94efac89d0 100644
--- a/usr/src/cmd/devfsadm/cfg_link.h
+++ b/usr/src/cmd/devfsadm/cfg_link.h
@@ -19,7 +19,7 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -60,7 +60,7 @@ extern "C" {
 #define	IOB_PRE			"iob"
 #define	AP_PATH_SEP		":"
 #define	AP_PATH_IOB_SEP		"."
-#define	VENDID_SUN		0x108e
+#define	IEEE_SUN_ID		0x080020
 #define	APNODE_DEFNAME		0x1
 #define	PCIDEV_NIL		((minor_t)-1)
 
diff --git a/usr/src/uts/sun4u/io/px/px_hlib.c b/usr/src/uts/sun4u/io/px/px_hlib.c
index fdf96ed7da..1f39ca7d09 100644
--- a/usr/src/uts/sun4u/io/px/px_hlib.c
+++ b/usr/src/uts/sun4u/io/px/px_hlib.c
@@ -19,7 +19,7 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -165,9 +165,10 @@ static uint64_t	msiq_config_other_regs[] = {
 #define	MSIQ_MAPPING_SIZE	(MSI_MAPPING_ENTRIES * sizeof (uint64_t))
 
 /* OPL tuning variables for link unstable issue */
-int wait_perst = 500000; 	/* step 9, default: 500ms */
-int wait_enable_port = 45000;	/* step 11, default: 45ms */
+int wait_perst = 5000000; 	/* step 9, default: 5s */
+int wait_enable_port = 30000;	/* step 11, default: 30ms */
 int link_retry_count = 2; 	/* step 11, default: 2 */
+int link_status_check = 400000;	/* step 11, default: 400ms */
 
 static uint64_t msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
 static void msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p);
@@ -3008,6 +3009,13 @@ oberon_hp_pwron(caddr_t csr_base)
 		goto fail;
 	}
 
+	/* Check HP Capable */
+	if (!CSR_BR(csr_base, TLU_SLOT_CAPABILITIES, HP)) {
+		DBG(DBG_HP, NULL, "oberon_hp_pwron fails: leaf not "
+			"hotplugable\n");
+		goto fail;
+	}
+
 	/* Check Slot status */
 	reg = CSR_XR(csr_base, TLU_SLOT_STATUS);
 	if (!(reg & (1ull << TLU_SLOT_STATUS_PSD)) ||
@@ -3078,7 +3086,7 @@ oberon_hp_pwron(caddr_t csr_base)
 
 		/* wait for the link up */
 		for (i = 0; (i < 2) && (link_up == B_FALSE); i++) {
-			delay(drv_usectohz(100000));
+			delay(drv_usectohz(link_status_check));
 			reg = CSR_XR(csr_base, DLU_LINK_LAYER_STATUS);
 
 		    if ((((reg >> DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS) &
@@ -3128,8 +3136,8 @@ oberon_hp_pwron(caddr_t csr_base)
 	reg &= ~(TLU_SLOT_CAPABILITIES_SPLS_MASK <<
 	    TLU_SLOT_CAPABILITIES_SPLS);
 	reg &= ~(TLU_SLOT_CAPABILITIES_SPLV_MASK <<
-	    TLU_SLOT_CAPABILITIES_SPLS);
-	reg |= (0x19 << TLU_SLOT_CAPABILITIES_SPLS);
+	    TLU_SLOT_CAPABILITIES_SPLV);
+	reg |= (0x19 << TLU_SLOT_CAPABILITIES_SPLV);
 	CSR_XS(csr_base, TLU_SLOT_CAPABILITIES, reg);
 
 	/* Turn on Power LED */