6800049 can't set class-opt-****-*** parameters via nxge.conf

6800793 rxdma-intr-time and rxdma-intr-pkts should be on a per interface basis in nxge

5 files changed, 98 insertions, 33 deletions

diff --git a/usr/src/uts/common/io/nxge/nxge.conf b/usr/src/uts/common/io/nxge/nxge.conf
index 6d8fa8939b..6c82d34177 100644
--- a/usr/src/uts/common/io/nxge/nxge.conf
+++ b/usr/src/uts/common/io/nxge/nxge.conf
@@ -105,12 +105,9 @@
 #------- Classification and Load Distribution Configuration ------
 #
 # class-opt-****-***
-# 	These variables define how each IP class is configured.
-#	Configuration options range from whether TCAM lookup ie
-#	is enabled to flow hash generation.
-# 	This parameters also control how the flow template is
-#	 constructed and how packet is distributed within RDC
-#	groups.
+# 	These parameters define how each IP class is configured.
+# 	They control how the flow template is constructed and how
+#	packets are distributed within RDC groups.
 #
 #	supported classes:
 #	class-opt-ipv4-tcp class-opt-ipv4-udp class-opt-ipv4-sctp
@@ -129,7 +126,10 @@
 #	0400:		use Src Port (for flow key)
 #	0800:		use Dest Port (for flow key)	
 #
-# class-opt-ipv4-tcp = fe0;
+# The following uses L2DA, VLAN, IP proto, IP src and dest and TCP 
+# src and dest port for computing the flow key for IPv4 TCP packets.
+#
+# class-opt-ipv4-tcp = 0xfe0;
 #
 #------- Software LSO (large segment offload) support --------
 # To enable software LSO for all nxge interfaces,
diff --git a/usr/src/uts/common/io/nxge/nxge_main.c b/usr/src/uts/common/io/nxge/nxge_main.c
index 92c842cdc5..1c4c146a50 100644
--- a/usr/src/uts/common/io/nxge/nxge_main.c
+++ b/usr/src/uts/common/io/nxge/nxge_main.c
@@ -103,8 +103,6 @@ uint32_t 	nxge_dvma_thresh = TX_FASTDVMA_MIN;
 uint32_t 	nxge_dma_stream_thresh = TX_STREAM_MIN;
 uint32_t	nxge_jumbo_mtu	= TX_JUMBO_MTU;
 boolean_t	nxge_jumbo_enable = B_FALSE;
-uint16_t	nxge_rcr_timeout = NXGE_RDC_RCR_TIMEOUT;
-uint16_t	nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD;
 nxge_tx_mode_t	nxge_tx_scheme = NXGE_USE_SERIAL;
 
 /* MAX LSO size */
diff --git a/usr/src/uts/common/io/nxge/nxge_ndd.c b/usr/src/uts/common/io/nxge/nxge_ndd.c
index 79d8c09cc7..2fe67c81f6 100644
--- a/usr/src/uts/common/io/nxge/nxge_ndd.c
+++ b/usr/src/uts/common/io/nxge/nxge_ndd.c
@@ -114,6 +114,8 @@ static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *,
 	p_mblk_t, caddr_t);
 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *,
 	p_mblk_t, caddr_t);
+static int nxge_param_get_rx_intr_time(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
+static int nxge_param_get_rx_intr_pkts(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t);
 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
@@ -301,11 +303,13 @@ static nxge_param_t	nxge_param_arr[] = {
 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
 		0, 15, 0, 0, "default-port-rdc", "default_port_rdc"},
 
-	{ nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW,
+	{ nxge_param_get_rx_intr_time, nxge_param_rx_intr_time,
+		NXGE_PARAM_RXDMA_RW,
 		NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX,
 		NXGE_RDC_RCR_TIMEOUT, 0, "rxdma-intr-time", "rxdma_intr_time"},
 
-	{ nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW,
+	{ nxge_param_get_rx_intr_pkts, nxge_param_rx_intr_pkts,
+		NXGE_PARAM_RXDMA_RW,
 		NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX,
 		NXGE_RDC_RCR_THRESHOLD, 0,
 		"rxdma-intr-pkts", "rxdma_intr_pkts"},
@@ -954,6 +958,36 @@ nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
 }
 
 /* ARGSUSED */
+static int
+nxge_param_get_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
+{
+	p_nxge_param_t pa = (p_nxge_param_t)cp;
+
+	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_time"));
+
+	pa->value = (uint32_t)nxgep->intr_timeout;
+	(void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_timeout);
+
+	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_time"));
+	return (0);
+}
+
+/* ARGSUSED */
+static int
+nxge_param_get_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
+{
+	p_nxge_param_t pa = (p_nxge_param_t)cp;
+
+	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_pkts"));
+
+	pa->value = (uint32_t)nxgep->intr_threshold;
+	(void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_threshold);
+
+	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_pkts"));
+	return (0);
+}
+
+/* ARGSUSED */
 int
 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
 {
@@ -1833,6 +1867,13 @@ nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q,
 		if (class == -1)
 			return (EINVAL);
 
+		/* Filter out the allowed bits */
+		pa->value &= (NXGE_CLASS_FLOW_USE_PORTNUM |
+		    NXGE_CLASS_FLOW_USE_L2DA | NXGE_CLASS_FLOW_USE_VLAN |
+		    NXGE_CLASS_FLOW_USE_PROTO | NXGE_CLASS_FLOW_USE_IPSRC |
+		    NXGE_CLASS_FLOW_USE_IPDST | NXGE_CLASS_FLOW_USE_SRC_PORT |
+		    NXGE_CLASS_FLOW_USE_DST_PORT);
+
 		status = nxge_fflp_ip_class_config(nxgep, class, pa->value);
 		if (status != NXGE_OK)
 			return (EINVAL);
@@ -1863,6 +1904,12 @@ nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q,
 	if (status != NXGE_OK)
 		return (EINVAL);
 
+	/* Filter out the allowed bits */
+	cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA |
+	    NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO |
+	    NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST |
+	    NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT);
+
 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
 	    "nxge_param_get_ip_opt_get %x ", cfg_value));
 
@@ -2518,6 +2565,12 @@ nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp)
 	if (status != NXGE_OK)
 		return (EINVAL);
 
+	/* Filter out the allowed bits */
+	cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA |
+	    NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO |
+	    NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST |
+	    NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT);
+
 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
 	    "nxge_param_get_ip_opt_get %x ", cfg_value));
 
diff --git a/usr/src/uts/common/io/nxge/nxge_rxdma.c b/usr/src/uts/common/io/nxge/nxge_rxdma.c
index b495ca4b83..8b3eeb7eae 100644
--- a/usr/src/uts/common/io/nxge/nxge_rxdma.c
+++ b/usr/src/uts/common/io/nxge/nxge_rxdma.c
@@ -62,9 +62,6 @@ extern uint32_t nxge_mblks_pending;
 extern uint32_t nxge_max_rx_pkts;
 boolean_t nxge_jumbo_enable;
 
-extern uint16_t nxge_rcr_timeout;
-extern uint16_t nxge_rcr_threshold;
-
 /*
  * Tunables to manage the receive buffer blocks.
  *
@@ -3326,15 +3323,6 @@ nxge_map_rxdma(p_nxge_t nxgep, int channel)
 		return (NXGE_ERROR);
 
 	/*
-	 * Timeout should be set based on the system clock divider.
-	 * A timeout value of 1 assumes that the
-	 * granularity (1000) is 3 microseconds running at 300MHz.
-	 */
-
-	nxgep->intr_threshold = nxge_rcr_threshold;
-	nxgep->intr_timeout = nxge_rcr_timeout;
-
-	/*
 	 * Map descriptors from the buffer polls for each dma channel.
 	 */
 
diff --git a/usr/src/uts/common/io/nxge/nxge_virtual.c b/usr/src/uts/common/io/nxge/nxge_virtual.c
index 4a52dd415d..ed05c0b13c 100644
--- a/usr/src/uts/common/io/nxge/nxge_virtual.c
+++ b/usr/src/uts/common/io/nxge/nxge_virtual.c
@@ -52,9 +52,6 @@ uint32_t nxge_groups_per_port = 2;
 extern uint32_t nxge_use_partition;
 extern uint32_t nxge_dma_obp_props_only;
 
-extern uint16_t nxge_rcr_timeout;
-extern uint16_t nxge_rcr_threshold;
-
 extern uint_t nxge_rx_intr(void *, void *);
 extern uint_t nxge_tx_intr(void *, void *);
 extern uint_t nxge_mif_intr(void *, void *);
@@ -1966,6 +1963,30 @@ nxge_use_default_dma_config_n2(p_nxge_t nxgep)
 	    p_cfgp, p_cfgp->max_rdc_grpids,
 	    p_cfgp->def_mac_rxdma_grpid));
 
+	nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
+	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
+	    "rxdma-intr-time", (int **)&prop_val, &prop_len) ==
+	    DDI_PROP_SUCCESS) {
+		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
+			nxgep->intr_timeout = prop_val[0];
+			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
+			    nxgep->dip, "rxdma-intr-time", prop_val, prop_len);
+		}
+		ddi_prop_free(prop_val);
+	}
+
+	nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
+	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
+	    "rxdma-intr-pkts", (int **)&prop_val, &prop_len) ==
+	    DDI_PROP_SUCCESS) {
+		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
+			nxgep->intr_threshold = prop_val[0];
+			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
+			    nxgep->dip, "rxdma-intr-pkts", prop_val, prop_len);
+		}
+		ddi_prop_free(prop_val);
+	}
+
 	nxge_set_hw_dma_config(nxgep);
 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2"));
 	return (status);
@@ -2214,23 +2235,26 @@ nxge_use_cfg_dma_config(p_nxge_t nxgep)
 	    p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs,
 	    p_cfgp->def_mac_rxdma_grpid));
 
+	nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
 	prop = param_arr[param_rxdma_intr_time].fcode_name;
 
 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
 		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
-			nxge_rcr_timeout = prop_val[0];
+			nxgep->intr_timeout = prop_val[0];
 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
 			    nxgep->dip, prop, prop_val, prop_len);
 		}
 		ddi_prop_free(prop_val);
 	}
+
+	nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
 	prop = param_arr[param_rxdma_intr_pkts].fcode_name;
 
 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
 		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
-			nxge_rcr_threshold = prop_val[0];
+			nxgep->intr_threshold = prop_val[0];
 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
 			    nxgep->dip, prop, prop_val, prop_len);
 		}
@@ -2390,8 +2414,8 @@ nxge_set_rdc_intr_property(p_nxge_t nxgep)
 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
 
 	for (i = 0; i < NXGE_MAX_RDCS; i++) {
-		p_dma_cfgp->rcr_timeout[i] = nxge_rcr_timeout;
-		p_dma_cfgp->rcr_threshold[i] = nxge_rcr_threshold;
+		p_dma_cfgp->rcr_timeout[i] = nxgep->intr_timeout;
+		p_dma_cfgp->rcr_threshold[i] = nxgep->intr_threshold;
 	}
 
 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property"));
@@ -2777,15 +2801,17 @@ nxge_set_hw_class_config(p_nxge_t nxgep)
 	p_nxge_class_pt_cfg_t p_class_cfgp;
 	int start_prop, end_prop;
 	uint_t prop_cnt;
+	int start_class, j = 0;
 
 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config"));
 
 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
 	param_arr = nxgep->param_arr;
-	start_prop = param_class_opt_ip_usr4;
+	start_prop = param_class_opt_ipv4_tcp;
 	end_prop = param_class_opt_ipv6_sctp;
+	start_class = TCAM_CLASS_TCP_IPV4;
 
-	for (i = start_prop; i <= end_prop; i++) {
+	for (i = start_prop, j = 0; i <= end_prop; i++, j++) {
 		prop = param_arr[i].fcode_name;
 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip,
 		    0, prop, &int_prop_val,
@@ -2795,7 +2821,7 @@ nxge_set_hw_class_config(p_nxge_t nxgep)
 		} else {
 			cfg_value = (uint32_t)param_arr[i].value;
 		}
-		p_class_cfgp->class_cfg[i - start_prop] = cfg_value;
+		p_class_cfgp->class_cfg[start_class + j] = cfg_value;
 	}
 
 	prop = param_arr[param_h1_init_value].fcode_name;