6404710 Create #defines for 2's complement of -1 in pci cap library

6404990 Cleanup dead code in pci cap library

6 files changed, 29 insertions, 30 deletions

diff --git a/usr/src/uts/common/io/pci_cap.c b/usr/src/uts/common/io/pci_cap.c
index ef9ec04624..ee5b2d712a 100644
--- a/usr/src/uts/common/io/pci_cap.c
+++ b/usr/src/uts/common/io/pci_cap.c
@@ -62,7 +62,7 @@ pci_cap_probe(ddi_acc_handle_t h, uint16_t index,
 
 	status = pci_config_get16(h, PCI_CONF_STAT);
 
-	if (status == 0xffff || !(status & PCI_STAT_CAP))
+	if (status == PCI_CAP_EINVAL16 || !(status & PCI_STAT_CAP))
 		return (DDI_FAILURE);
 
 	/* PCIE and PCIX Version 2 contain Extended Config Space */
@@ -77,7 +77,7 @@ pci_cap_probe(ddi_acc_handle_t h, uint16_t index,
 			search_ext = 1;
 		else if (id == PCI_CAP_ID_PCIX) {
 			if ((pcix_cmd = pci_config_get16(h, base +
-				PCI_PCIX_COMMAND)) != 0xffff)
+				PCI_PCIX_COMMAND)) != PCI_CAP_EINVAL16)
 				continue;
 			if ((pcix_cmd & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_2)
 				search_ext = 1;
@@ -93,7 +93,7 @@ pci_cap_probe(ddi_acc_handle_t h, uint16_t index,
 		return (DDI_FAILURE);
 
 	for (base = PCIE_EXT_CAP; base && i < index; i++) {
-		if ((xcaps_hdr = pci_config_get32(h, base)) == 0xffffffff)
+		if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)
 			break;
 
 		id = (xcaps_hdr >> PCIE_EXT_CAP_ID_SHIFT)
@@ -105,7 +105,7 @@ pci_cap_probe(ddi_acc_handle_t h, uint16_t index,
 	if (!base || i < index)
 		return (DDI_FAILURE);
 
-	if ((xcaps_hdr = pci_config_get32(h, base)) == 0xffffffff)
+	if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)
 		return (DDI_FAILURE);
 
 	id = ((xcaps_hdr >> PCIE_EXT_CAP_ID_SHIFT) & PCIE_EXT_CAP_ID_MASK) |
@@ -130,7 +130,7 @@ pci_lcap_locate(ddi_acc_handle_t h, uint8_t id, uint16_t *base_p)
 
 	status = pci_config_get16(h, PCI_CONF_STAT);
 
-	if (status == 0xffff || !(status & PCI_STAT_CAP))
+	if (status == PCI_CAP_EINVAL16 || !(status & PCI_STAT_CAP))
 		return (DDI_FAILURE);
 
 	for (base = pci_config_get8(h, PCI_CONF_CAP_PTR); base;
@@ -158,13 +158,13 @@ pci_xcap_locate(ddi_acc_handle_t h, uint16_t id, uint16_t *base_p)
 
 	status = pci_config_get16(h, PCI_CONF_STAT);
 
-	if (status == 0xffff || !(status & PCI_STAT_CAP))
+	if (status == PCI_CAP_EINVAL16 || !(status & PCI_STAT_CAP))
 		return (DDI_FAILURE);
 
 	for (base = PCIE_EXT_CAP; base; base = (xcaps_hdr >>
 		PCIE_EXT_CAP_NEXT_PTR_SHIFT) & PCIE_EXT_CAP_NEXT_PTR_MASK) {
 
-		if ((xcaps_hdr = pci_config_get32(h, base)) == 0xffffffff)
+		if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)
 			break;
 
 		if (((xcaps_hdr >> PCIE_EXT_CAP_ID_SHIFT) &
@@ -191,7 +191,7 @@ pci_cap_get(ddi_acc_handle_t h, pci_config_size_t size,
 	uint32_t data;
 
 	if (PCI_CAP_BASE(h, id, &base) != DDI_SUCCESS)
-		return (0xffffffff);
+		return (PCI_CAP_EINVAL32);
 
 	/*
 	 * Each access to a PCI Configuration Space should be checked
@@ -212,7 +212,7 @@ pci_cap_get(ddi_acc_handle_t h, pci_config_size_t size,
 		data = pci_config_get32(h, offset);
 		break;
 	default:
-		data = 0xffffffff;
+		data = PCI_CAP_EINVAL32;
 	}
 
 	PCI_CAP_DBG("pci_cap_get: %p[x%x]=x%x\n", (void *)h, offset, data);
@@ -275,7 +275,7 @@ pci_cap_read(ddi_acc_handle_t h, uint32_t id, uint16_t base,
 		return (DDI_FAILURE);
 
 	for (ptr = buf_p, i = 0; i < nwords; i++, base += 4) {
-		if ((*ptr++ = pci_config_get32(h, base)) == 0xffffffff)
+		if ((*ptr++ = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)
 			return (DDI_FAILURE);
 	}
 
diff --git a/usr/src/uts/common/io/pci_intr_lib.c b/usr/src/uts/common/io/pci_intr_lib.c
index 2571b9ca6b..47b3e66a8a 100644
--- a/usr/src/uts/common/io/pci_intr_lib.c
+++ b/usr/src/uts/common/io/pci_intr_lib.c
@@ -104,7 +104,7 @@ pci_get_msi_ctrl(dev_info_t *dip, int type, ushort_t *msi_ctrl,
 	if ((PCI_CAP_LOCATE(*h, PCI_CAP_ID_MSI, caps_ptr) == DDI_SUCCESS) &&
 		(type == DDI_INTR_TYPE_MSI)) {
 		if ((*msi_ctrl = PCI_CAP_GET16(*h, NULL, *caps_ptr,
-			PCI_MSI_CTRL)) == 0xffff)
+			PCI_MSI_CTRL)) == PCI_CAP_EINVAL16)
 			goto done;
 
 		DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: MSI "
@@ -116,7 +116,7 @@ pci_get_msi_ctrl(dev_info_t *dip, int type, ushort_t *msi_ctrl,
 	if ((PCI_CAP_LOCATE(*h, PCI_CAP_ID_MSI_X, caps_ptr) == DDI_SUCCESS) &&
 		(type == DDI_INTR_TYPE_MSIX)) {
 		if ((*msi_ctrl = PCI_CAP_GET16(*h, NULL, *caps_ptr,
-			PCI_MSIX_CTRL)) == 0xffff)
+			PCI_MSIX_CTRL)) == PCI_CAP_EINVAL16)
 			goto done;
 
 		DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: MSI-X "
@@ -491,7 +491,7 @@ pci_msi_set_mask(dev_info_t *rdip, int type, int inum)
 		    PCI_MSI_64BIT_MASKBITS : PCI_MSI_32BIT_MASK;
 
 		if ((mask_bits = PCI_CAP_GET32(cfg_hdle, NULL, caps_ptr,
-			offset)) == 0xffffffff)
+			offset)) == PCI_CAP_EINVAL32)
 			goto done;
 
 		mask_bits |= (1 << inum);
@@ -554,7 +554,7 @@ pci_msi_clr_mask(dev_info_t *rdip, int type, int inum)
 		offset = (msi_ctrl &  PCI_MSI_64BIT_MASK) ?
 		    PCI_MSI_64BIT_MASKBITS : PCI_MSI_32BIT_MASK;
 		if ((mask_bits = PCI_CAP_GET32(cfg_hdle, NULL, caps_ptr,
-			offset)) == DDI_FAILURE)
+			offset)) == PCI_CAP_EINVAL32)
 			goto done;
 
 		mask_bits &= ~(1 << inum);
@@ -621,7 +621,7 @@ pci_msi_get_pending(dev_info_t *rdip, int type, int inum, int *pendingp)
 		    PCI_MSI_64BIT_PENDING : PCI_MSI_32BIT_PENDING;
 
 		if ((pending_bits = PCI_CAP_GET32(cfg_hdle, NULL, caps_ptr,
-			offset)) == DDI_FAILURE)
+			offset)) == PCI_CAP_EINVAL32)
 			goto done;
 
 		*pendingp = pending_bits & ~(1 >> inum);
diff --git a/usr/src/uts/common/io/pcie.c b/usr/src/uts/common/io/pcie.c
index 649f478825..b797f0508a 100644
--- a/usr/src/uts/common/io/pcie.c
+++ b/usr/src/uts/common/io/pcie.c
@@ -233,7 +233,7 @@ pcie_clear_errors(dev_info_t *dip, ddi_acc_handle_t config_handle)
 
 	/* 2. clear the PCIe Errors */
 	if ((device_sts = PCI_CAP_GET16(config_handle, NULL, cap_ptr,
-		PCIE_DEVSTS)) != 0xffff)
+		PCIE_DEVSTS)) != PCI_CAP_EINVAL16)
 		PCI_CAP_PUT16(config_handle, PCI_CAP_ID_PCI_E, cap_ptr,
 			PCIE_DEVSTS, device_sts);
 
@@ -273,7 +273,7 @@ pcie_enable_errors(dev_info_t *dip, ddi_acc_handle_t config_handle)
 	 * Enable PCI-Express Baseline Error Handling
 	 */
 	if ((device_ctl = PCI_CAP_GET16(config_handle, NULL, cap_ptr,
-		PCIE_DEVCTL)) != 0xffff) {
+		PCIE_DEVCTL)) != PCI_CAP_EINVAL16) {
 		PCI_CAP_PUT16(config_handle, NULL, cap_ptr, PCIE_DEVCTL,
 			pcie_base_err_default);
 
@@ -291,7 +291,7 @@ pcie_enable_errors(dev_info_t *dip, ddi_acc_handle_t config_handle)
 
 	/* Enable Uncorrectable errors */
 	if ((aer_reg = PCI_XCAP_GET32(config_handle, NULL, aer_ptr,
-		PCIE_AER_UCE_MASK)) != DDI_FAILURE) {
+		PCIE_AER_UCE_MASK)) != PCI_CAP_EINVAL32) {
 		PCI_XCAP_PUT32(config_handle, NULL, aer_ptr,
 			PCIE_AER_UCE_MASK, pcie_aer_uce_mask);
 		PCIE_DBG("%s: AER UCE=0x%x->0x%x\n", ddi_driver_name(dip),
@@ -301,7 +301,7 @@ pcie_enable_errors(dev_info_t *dip, ddi_acc_handle_t config_handle)
 
 	/* Enable Correctable errors */
 	if ((aer_reg = PCI_XCAP_GET32(config_handle, NULL, aer_ptr,
-		PCIE_AER_CE_MASK)) != DDI_FAILURE) {
+		PCIE_AER_CE_MASK)) != PCI_CAP_EINVAL32) {
 		PCI_XCAP_PUT32(config_handle, PCIE_EXT_CAP_ID_AER,
 			aer_ptr, PCIE_AER_CE_MASK, pcie_aer_ce_mask);
 		PCIE_DBG("%s: AER CE=0x%x->0x%x\n", ddi_driver_name(dip),
@@ -319,7 +319,7 @@ pcie_enable_errors(dev_info_t *dip, ddi_acc_handle_t config_handle)
 	 * Enable secondary bus errors
 	 */
 	if ((aer_reg = PCI_XCAP_GET32(config_handle, NULL, aer_ptr,
-		PCIE_AER_SUCE_MASK)) != DDI_FAILURE) {
+		PCIE_AER_SUCE_MASK)) != PCI_CAP_EINVAL32) {
 		PCI_XCAP_PUT32(config_handle, NULL, aer_ptr, PCIE_AER_SUCE_MASK,
 			pcie_aer_suce_mask);
 		PCIE_DBG("%s: AER SUCE=0x%x->0x%x\n", ddi_driver_name(dip),
diff --git a/usr/src/uts/common/sys/pci_cap.h b/usr/src/uts/common/sys/pci_cap.h
index a5127619a5..fafc5f1ab9 100644
--- a/usr/src/uts/common/sys/pci_cap.h
+++ b/usr/src/uts/common/sys/pci_cap.h
@@ -54,6 +54,11 @@ int pci_lcap_locate(ddi_acc_handle_t h, uint8_t id, uint16_t *base_p);
 #define PCI_CAP_DBG		_NOTE(CONSTANTCONDITION) if (0) printf
 #endif /* DEBUG */
 
+/* 2's complement of -1, added here to ameliorate testing for invalid data */
+#define	PCI_CAP_EINVAL8		0xff
+#define	PCI_CAP_EINVAL16	0xffff
+#define	PCI_CAP_EINVAL32	0xffffffff
+
 /*
  * Supported Config Size Reads/Writes
  */
@@ -111,12 +116,6 @@ extern int pci_cap_put(ddi_acc_handle_t h, pci_config_size_t size,
 extern int pci_cap_read(ddi_acc_handle_t h, uint32_t id, uint16_t base,
 		uint32_t *buf_p, uint32_t nwords);
 
-extern int pci_cap_count(ddi_acc_handle_t h);
-
-extern void pci_cap_print(ddi_acc_handle_t h);
-
-extern void pci_cap_dump(uint32_t *buf_p, uint32_t nwords);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/usr/src/uts/sun4u/io/pci/pci_pci.c b/usr/src/uts/sun4u/io/pci/pci_pci.c
index 5674c985b2..02abadc62e 100644
--- a/usr/src/uts/sun4u/io/pci/pci_pci.c
+++ b/usr/src/uts/sun4u/io/pci/pci_pci.c
@@ -1020,7 +1020,7 @@ ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *pdip)
 	pmcap = PCI_CAP_GET16(conf_hdl, NULL, ppb->ppb_pm_cap_ptr,
 		PCI_PMCAP);
 
-	if (pmcap == 0xffff || pmcsr_bse == 0xff) {
+	if (pmcap == PCI_CAP_EINVAL16 || pmcsr_bse == PCI_CAP_EINVAL8) {
 		pci_config_teardown(&conf_hdl);
 		return;
 	}
@@ -1178,7 +1178,7 @@ pci_pwr_current_lvl(pci_pwr_t *pwr_p)
 	    ddi_get_instance(pwr_p->pwr_dip));
 
 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL,
-		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == 0xffff)
+		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16)
 		return (DDI_FAILURE);
 
 	switch (pmcsr & PCI_PMCSR_STATE_MASK) {
@@ -1255,7 +1255,7 @@ ppb_pwr(dev_info_t *dip, int component, int lvl)
 	}
 
 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL,
-		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == 0xffff)
+		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16)
 		return (DDI_FAILURE);
 
 	/*
diff --git a/usr/src/uts/sun4u/io/pci/pcix.c b/usr/src/uts/sun4u/io/pci/pcix.c
index aa0fd24a6e..8264ac83d6 100644
--- a/usr/src/uts/sun4u/io/pci/pcix.c
+++ b/usr/src/uts/sun4u/io/pci/pcix.c
@@ -66,7 +66,7 @@ pcix_set_cmd_reg(dev_info_t *child, uint16_t value)
 	 * Read the PCI-X Command Register.
 	 */
 	if ((pcix_cmd = PCI_CAP_GET16(handle, NULL, pcix_cap_ptr, 2))
-		== 0xffff)
+		== PCI_CAP_EINVAL16)
 		goto teardown;
 
 	DEBUG1(DBG_INIT_CLD, child, "pcix_set_cmd_reg: PCI-X CMD Register "