6834787 Handle minor cpuid/revision changes for AMD processors

6839150 AMD Socket Identifications impact FMA on AMD Family 0xF topologies

3 files changed, 49 insertions, 26 deletions

diff --git a/usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c b/usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c
index 06405e4508..ebcf63ab40 100644
--- a/usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c
+++ b/usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c
@@ -20,12 +20,10 @@
  */
 
 /*
- * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * "Generic AMD" model-specific support.  If no more-specific support can
  * be found, or such modules declines to initialize, then for AuthenticAMD
@@ -76,16 +74,6 @@ int authamd_ms_support_disable = 0;
  */
 
 /*
- * Families that this module will provide some model-specific
- * support for (if no more-specific module claims it first).
- * We try to support whole families rather than differentiate down
- * to revision.
- */
-#define	AUTHAMD_SUPPORTED(fam) \
-	((fam) == AUTHAMD_FAMILY_6 || (fam) == AUTHAMD_FAMILY_F || \
-	(fam) == AUTHAMD_FAMILY_10)
-
-/*
  * Models that include an on-chip NorthBridge.
  */
 #define	AUTHAMD_NBONCHIP(rev) \
@@ -450,6 +438,40 @@ authamd_clear_ecccnt(authamd_data_t *authamd, boolean_t clrint)
 	}
 }
 
+
+/*
+ * Return
+ * 	1: supported
+ *	0: unsupported
+ */
+static int
+authamd_supported(uint_t family, uint32_t rev, uint_t chipid)
+{
+	uint32_t nbcap;
+
+	if (family == AUTHAMD_FAMILY_6)
+		return (1);
+
+	if (family == AUTHAMD_FAMILY_F)
+		return (1);
+
+	/*
+	 * On Family 10h, authamd is currently unsupported when there are
+	 * multiple nodes on a processor chip.
+	 */
+	if (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_D)) {
+		nbcap = authamd_pcicfg_read(chipid, MC_FUNC_MISCCTL,
+		    MC_CTL_REG_NBCAP);
+		if ((nbcap & MC_NBCAP_MULTINODECPU) == 0)
+			return (1);
+	} else {
+		if (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_A))
+			return (1);
+	}
+
+	return (0);
+}
+
 /*
  * cms_init entry point.
  *
@@ -463,10 +485,12 @@ authamd_init(cmi_hdl_t hdl, void **datap)
 	uint_t chipid = cmi_hdl_chipid(hdl);
 	struct authamd_chipshared *sp, *osp;
 	uint_t family = cmi_hdl_family(hdl);
+	uint32_t rev = cmi_hdl_chiprev(hdl);
 	authamd_data_t *authamd;
 	uint64_t cap;
 
-	if (authamd_ms_support_disable || !AUTHAMD_SUPPORTED(family))
+	if (authamd_ms_support_disable ||
+	    !authamd_supported(family, rev, chipid))
 		return (ENOTSUP);
 
 	if (!(x86_feature & X86_MCA))
diff --git a/usr/src/uts/intel/sys/mc_amd.h b/usr/src/uts/intel/sys/mc_amd.h
index 5b0315a099..ad317a2818 100644
--- a/usr/src/uts/intel/sys/mc_amd.h
+++ b/usr/src/uts/intel/sys/mc_amd.h
@@ -18,15 +18,13 @@
  *
  * CDDL HEADER END
  *
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef _MC_AMD_H
 #define	_MC_AMD_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/mc.h>
 #include <sys/isa_defs.h>
 #include <sys/x86_archext.h>
@@ -201,7 +199,8 @@ enum mc_funcnum {
 #define	MC_CTL_REG_SPARECTL	0xb0	/* On-line spare control register */
 #define	MC_CTL_REG_NBCAP	0xe8	/* NB Capabilities */
 
-#define	MC_NBCAP_L3CAPABLE	0x02000000
+#define	MC_NBCAP_L3CAPABLE	(1U << 25)
+#define	MC_NBCAP_MULTINODECPU	(1U << 29)
 
 /*
  * MC4_MISC MSR and MC4_MISCj MSRs
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h
index 46f4be3c07..f81804541b 100644
--- a/usr/src/uts/intel/sys/x86_archext.h
+++ b/usr/src/uts/intel/sys/x86_archext.h
@@ -513,7 +513,7 @@ extern "C" {
  * Definitions for AMD Family 0x11.
  */
 #define	X86_CHIPREV_AMD_11 \
-	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0003)
+	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0001)
 
 
 /*
@@ -532,7 +532,7 @@ extern "C" {
 
 #define	X86_SOCKET_MATCH(s, mask) \
 	(_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
-	(_X86_SOCKET_TYPE(s) == _X86_SOCKET_TYPE(mask)))
+	(_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
 
 #define	X86_SOCKET_UNKNOWN 0x0
 	/*
@@ -544,12 +544,12 @@ extern "C" {
 #define	X86_SOCKET_S1g1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
 #define	X86_SOCKET_AM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
 #define	X86_SOCKET_F1207	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
-#define	X86_SOCKET_S1g2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000030)
-#define	X86_SOCKET_S1g3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
-#define	X86_SOCKET_AM		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000050)
-#define	X86_SOCKET_AM2R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000060)
-#define	X86_SOCKET_AM3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000070)
-#define	X86_SOCKET_G34		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
+#define	X86_SOCKET_S1g2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
+#define	X86_SOCKET_S1g3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
+#define	X86_SOCKET_AM		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
+#define	X86_SOCKET_AM2R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
+#define	X86_SOCKET_AM3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
+#define	X86_SOCKET_G34		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
 
 #if !defined(_ASM)