diff options
Diffstat (limited to 'usr/src/lib/libc')
| -rw-r--r-- | usr/src/lib/libc/Makefile | 2 | ||||
| -rw-r--r-- | usr/src/lib/libc/inc/base_inlines.h | 67 | ||||
| -rw-r--r-- | usr/src/lib/libc/inc/thr_inlines.h | 237 | ||||
| -rw-r--r-- | usr/src/lib/libc/port/unwind/unwind.c | 10 | ||||
| -rw-r--r-- | usr/src/lib/libc/sparc/Makefile.com | 5 | ||||
| -rw-r--r-- | usr/src/lib/libc/sparc/crt/_rtboot.s | 2 | ||||
| -rw-r--r-- | usr/src/lib/libc/sparc/crt/_rtld.c | 2 | ||||
| -rw-r--r-- | usr/src/lib/libc/sparcv9/Makefile.com | 5 |
8 files changed, 171 insertions, 159 deletions
diff --git a/usr/src/lib/libc/Makefile b/usr/src/lib/libc/Makefile index b75390cbcc..93934954dd 100644 --- a/usr/src/lib/libc/Makefile +++ b/usr/src/lib/libc/Makefile @@ -127,7 +127,7 @@ $(ROOTVARIANTDIR64)/$(VAR1_DYNLIB64) := FILEMODE= 755 .KEEP_STATE: -all: lib32 $(BUILD64) .WAIT lib64 .WAIT etc THIRDPARTYLICENSE +all: all_h lib32 $(BUILD64) .WAIT lib64 .WAIT etc THIRDPARTYLICENSE THIRDPARTYLICENSE: extract-copyright $(RM) $@ diff --git a/usr/src/lib/libc/inc/base_inlines.h b/usr/src/lib/libc/inc/base_inlines.h index 1753a3e044..c9bf36a90c 100644 --- a/usr/src/lib/libc/inc/base_inlines.h +++ b/usr/src/lib/libc/inc/base_inlines.h @@ -27,8 +27,7 @@ #ifndef _BASE_INLINES_H #define _BASE_INLINES_H -#pragma ident "%Z%%M% %I% %E% SMI" - +#include <sys/ccompile.h> #include <sys/types.h> #if !defined(__lint) && defined(__GNUC__) @@ -41,7 +40,7 @@ */ #if defined(__sparc) -extern __inline__ double +extern __GNU_INLINE double __mul_set(double x, double y, int *pe) { double __result; @@ -49,19 +48,19 @@ __mul_set(double x, double y, int *pe) uint32_t *__addr = &__fsr; __asm__ __volatile__( - "fmuld %4, %5, %0\n\t" - "st %%fsr, %3\n\t" - "ld %3, %2\n\t" - "and %2, 1, %2\n\t" - "st %2, %1" - : "=&e" (__result), "=m" (*pe), "=r" (__fsr), "=m" (*__addr) - : "e" (x), "e" (y)); + "fmuld %4, %5, %0\n\t" + "st %%fsr, %3\n\t" + "ld %3, %2\n\t" + "and %2, 1, %2\n\t" + "st %2, %1" + : "=&e" (__result), "=m" (*pe), "=r" (__fsr), "=m" (*__addr) + : "e" (x), "e" (y)); return (__result); } #endif /* __sparc */ #if defined(__sparc) -extern __inline__ double +extern __GNU_INLINE double __div_set(double x, double y, int *pe) { double __result; @@ -69,37 +68,37 @@ __div_set(double x, double y, int *pe) uint32_t *__addr = &__fsr; __asm__ __volatile__( - "fdivd %4, %5, %0\n\t" - "st %%fsr, %3\n\t" - "ld %3, %2\n\t" - "and %2, 1, %2\n\t" - "st %2, %1" - : "=&e" (__result), "=m" (*pe), "=r" (__fsr), "=m" (*__addr) - : "e" (x), "e" (y)); + "fdivd %4, %5, %0\n\t" + "st %%fsr, %3\n\t" + "ld %3, %2\n\t" + "and %2, 1, %2\n\t" + "st %2, %1" + : "=&e" (__result), "=m" (*pe), "=r" (__fsr), "=m" (*__addr) + : "e" (x), "e" (y)); return (__result); } #endif /* __sparc */ #if defined(__sparc) -extern __inline__ double +extern __GNU_INLINE double __dabs(double *x) { double __result; __asm__ __volatile__( #if defined(__sparcv9) - "fabsd %1, %0" + "fabsd %1, %0" #else - "fabss %1, %0" + "fabss %1, %0" #endif - : "=e" (__result) - : "0" (*x)); + : "=e" (__result) + : "0" (*x)); return (__result); } #endif /* __sparc */ #if defined(__sparc) -extern __inline__ void +extern __GNU_INLINE void __get_ieee_flags(__ieee_flags_type *b) { uint32_t __fsr; @@ -109,16 +108,16 @@ __get_ieee_flags(__ieee_flags_type *b) * needed; however, it warns as it does so. Add them here for now. */ __asm__ __volatile__( - "st %%fsr, %0\n\t" - "st %%g0, %1\n\t" - "ld %1, %%fsr\n\t" - "nop; nop; nop" - : "=m" (*b), "=m" (__fsr)); + "st %%fsr, %0\n\t" + "st %%g0, %1\n\t" + "ld %1, %%fsr\n\t" + "nop; nop; nop" + : "=m" (*b), "=m" (__fsr)); } #endif /* __sparc */ #if defined(__sparc) -extern __inline__ void +extern __GNU_INLINE void __set_ieee_flags(__ieee_flags_type *b) { /* @@ -126,10 +125,10 @@ __set_ieee_flags(__ieee_flags_type *b) * needed; however, it warns as it does so. Add them here for now. */ __asm__ __volatile__( - "ld %0, %%fsr\n\t" - "nop; nop; nop" - : /* no outputs */ - : "m" (*b)); + "ld %0, %%fsr\n\t" + "nop; nop; nop" + : /* no outputs */ + : "m" (*b)); } #endif /* __sparc */ diff --git a/usr/src/lib/libc/inc/thr_inlines.h b/usr/src/lib/libc/inc/thr_inlines.h index 55bd645428..f7cdc6a6bd 100644 --- a/usr/src/lib/libc/inc/thr_inlines.h +++ b/usr/src/lib/libc/inc/thr_inlines.h @@ -27,13 +27,24 @@ #ifndef _THR_INLINES_H #define _THR_INLINES_H -#pragma ident "%Z%%M% %I% %E% SMI" +#include <sys/ccompile.h> #if !defined(__lint) && defined(__GNUC__) /* inlines for gcc */ -extern __inline__ ulwp_t * +/* + * ON-usable GCC 4.x emits register pseudo-ops declaring %g7 as ignored, rather + * than scratch, GCC 3 does the reverse. All uses, both ones it generated + * (_curthread) and ones it didn't (__curthread) must agree. + */ +#if __GNUC__ > 3 +#define SPARC_REG_SPEC "#ignore" +#else +#define SPARC_REG_SPEC "#scratch" +#endif + +extern __GNU_INLINE ulwp_t * _curthread(void) { #if defined(__amd64) @@ -50,31 +61,29 @@ _curthread(void) return (__value); } -extern __inline__ ulwp_t * +extern __GNU_INLINE ulwp_t * __curthread(void) { ulwp_t *__value; __asm__ __volatile__( #if defined(__amd64) - "movq %%fs:0, %0\n\t" + "movq %%fs:0, %0\n\t" #elif defined(__i386) - "movl %%gs:0, %0\n\t" + "movl %%gs:0, %0\n\t" #elif defined(__sparcv9) - ".register %%g7, #scratch\n\t" - "ldx [%%g7 + 80], %0\n\t" + ".register %%g7, " SPARC_REG_SPEC "\n\t" + "ldx [%%g7 + 80], %0\n\t" #elif defined(__sparc) - ".register %%g7, #scratch\n\t" - "ld [%%g7 + 80], %0\n\t" + ".register %%g7, " SPARC_REG_SPEC "\n\t" + "ld [%%g7 + 80], %0\n\t" #else #error "port me" #endif - "1:" - : "=r" (__value) - : : "cc"); + : "=r" (__value)); return (__value); } -extern __inline__ greg_t +extern __GNU_INLINE greg_t stkptr(void) { #if defined(__amd64) @@ -89,207 +98,207 @@ stkptr(void) return (__value); } -extern __inline__ hrtime_t +extern __GNU_INLINE hrtime_t gethrtime(void) /* note: caller-saved registers are trashed */ { #if defined(__amd64) hrtime_t __value; __asm__ __volatile__( - "movl $3, %%eax\n\t" - "int $0xd2" - : "=a" (__value) - : : "rcx", "rdx", "rsi", "rdi", "r8", "r9", "r10", "r11", "cc"); + "movl $3, %%eax\n\t" + "int $0xd2" + : "=a" (__value) + : : "rcx", "rdx", "rsi", "rdi", "r8", "r9", "r10", "r11", "cc"); #elif defined(__i386) hrtime_t __value; __asm__ __volatile__( - "movl $3, %%eax\n\t" - "int $0xd2" - : "=A" (__value) - : : "ecx", "cc"); + "movl $3, %%eax\n\t" + "int $0xd2" + : "=A" (__value) + : : "ecx", "cc"); #elif defined(__sparcv9) register hrtime_t __value __asm__("o0"); __asm__ __volatile__( - "ta 0x24\n\t" - "sllx %%o0, 32, %0\n\t" - "or %%o1, %0, %0" - : "=r" (__value) - : : "o1", "o2", "o3", "o4", "o5", "cc"); + "ta 0x24\n\t" + "sllx %%o0, 32, %0\n\t" + "or %%o1, %0, %0" + : "=r" (__value) + : : "o1", "o2", "o3", "o4", "o5", "cc"); #elif defined(__sparc) register hrtime_t __value __asm__("o0"); __asm__ __volatile__( - "ta 0x24" - : "=r" (__value) - : : "o2", "o3", "o4", "o5", "cc"); + "ta 0x24" + : "=r" (__value) + : : "o2", "o3", "o4", "o5", "cc"); #else #error "port me" #endif return (__value); } -extern __inline__ int +extern __GNU_INLINE int set_lock_byte(volatile uint8_t *__lockp) { int __value; #if defined(__x86) __asm__ __volatile__( - "movl $1, %0\n\t" - "xchgb %%dl, %1" - : "+d" (__value), "+m" (*__lockp)); + "movl $1, %0\n\t" + "xchgb %%dl, %1" + : "+d" (__value), "+m" (*__lockp)); #elif defined(__sparc) __asm__ __volatile__( - "ldstub %1, %0\n\t" - "membar #LoadLoad" - : "=r" (__value), "+m" (*__lockp)); + "ldstub %1, %0\n\t" + "membar #LoadLoad" + : "=r" (__value), "+m" (*__lockp)); #else #error "port me" #endif return (__value); } -extern __inline__ uint32_t +extern __GNU_INLINE uint32_t atomic_swap_32(volatile uint32_t *__memory, uint32_t __value) { #if defined(__x86) __asm__ __volatile__( - "xchgl %0, %1" - : "+q" (__value), "+m" (*__memory)); + "xchgl %0, %1" + : "+q" (__value), "+m" (*__memory)); return (__value); #elif defined(__sparc) uint32_t __tmp1, __tmp2; __asm__ __volatile__( - "ld [%3], %0\n\t" - "1:\n\t" - "mov %4, %1\n\t" - "cas [%3], %0, %1\n\t" - "cmp %0, %1\n\t" - "bne,a,pn %%icc, 1b\n\t" - " mov %1, %0" - : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) - : "r" (__memory), "r" (__value) - : "cc"); + "ld [%3], %0\n\t" + "1:\n\t" + "mov %4, %1\n\t" + "cas [%3], %0, %1\n\t" + "cmp %0, %1\n\t" + "bne,a,pn %%icc, 1b\n\t" + " mov %1, %0" + : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) + : "r" (__memory), "r" (__value) + : "cc"); return (__tmp2); #else #error "port me" #endif } -extern __inline__ uint32_t +extern __GNU_INLINE uint32_t atomic_cas_32(volatile uint32_t *__memory, uint32_t __cmp, uint32_t __newvalue) { uint32_t __oldvalue; #if defined(__x86) __asm__ __volatile__( - "lock; cmpxchgl %3, %0" - : "=m" (*__memory), "=a" (__oldvalue) - : "a" (__cmp), "r" (__newvalue)); + "lock; cmpxchgl %3, %0" + : "=m" (*__memory), "=a" (__oldvalue) + : "a" (__cmp), "r" (__newvalue)); #elif defined(__sparc) __asm__ __volatile__( - "cas [%2], %3, %1" - : "=m" (*__memory), "=&r" (__oldvalue) - : "r" (__memory), "r" (__cmp), "1" (__newvalue)); + "cas [%2], %3, %1" + : "=m" (*__memory), "=&r" (__oldvalue) + : "r" (__memory), "r" (__cmp), "1" (__newvalue)); #else #error "port me" #endif return (__oldvalue); } -extern __inline__ void +extern __GNU_INLINE void atomic_inc_32(volatile uint32_t *__memory) { #if defined(__x86) __asm__ __volatile__( - "lock; incl %0" - : "+m" (*__memory)); + "lock; incl %0" + : "+m" (*__memory)); #elif defined(__sparc) uint32_t __tmp1, __tmp2; __asm__ __volatile__( - "ld [%3], %0\n\t" - "1:\n\t" - "add %0, 1, %1\n\t" - "cas [%3], %0, %1\n\t" - "cmp %0, %1\n\t" - "bne,a,pn %%icc, 1b\n\t" - " mov %1, %0" - : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) - : "r" (__memory) - : "cc"); + "ld [%3], %0\n\t" + "1:\n\t" + "add %0, 1, %1\n\t" + "cas [%3], %0, %1\n\t" + "cmp %0, %1\n\t" + "bne,a,pn %%icc, 1b\n\t" + " mov %1, %0" + : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) + : "r" (__memory) + : "cc"); #else #error "port me" #endif } -extern __inline__ void +extern __GNU_INLINE void atomic_dec_32(volatile uint32_t *__memory) { #if defined(__x86) __asm__ __volatile__( - "lock; decl %0" - : "+m" (*__memory)); + "lock; decl %0" + : "+m" (*__memory)); #elif defined(__sparc) uint32_t __tmp1, __tmp2; __asm__ __volatile__( - "ld [%3], %0\n\t" - "1:\n\t" - "sub %0, 1, %1\n\t" - "cas [%3], %0, %1\n\t" - "cmp %0, %1\n\t" - "bne,a,pn %%icc, 1b\n\t" - " mov %1, %0" - : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) - : "r" (__memory) - : "cc"); + "ld [%3], %0\n\t" + "1:\n\t" + "sub %0, 1, %1\n\t" + "cas [%3], %0, %1\n\t" + "cmp %0, %1\n\t" + "bne,a,pn %%icc, 1b\n\t" + " mov %1, %0" + : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) + : "r" (__memory) + : "cc"); #else #error "port me" #endif } -extern __inline__ void +extern __GNU_INLINE void atomic_and_32(volatile uint32_t *__memory, uint32_t __bits) { #if defined(__x86) __asm__ __volatile__( - "lock; andl %1, %0" - : "+m" (*__memory) - : "r" (__bits)); + "lock; andl %1, %0" + : "+m" (*__memory) + : "r" (__bits)); #elif defined(__sparc) uint32_t __tmp1, __tmp2; __asm__ __volatile__( - "ld [%3], %0\n\t" - "1:\n\t" - "and %0, %4, %1\n\t" - "cas [%3], %0, %1\n\t" - "cmp %0, %1\n\t" - "bne,a,pn %%icc, 1b\n\t" - " mov %1, %0" - : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) - : "r" (__memory), "r" (__bits) - : "cc"); + "ld [%3], %0\n\t" + "1:\n\t" + "and %0, %4, %1\n\t" + "cas [%3], %0, %1\n\t" + "cmp %0, %1\n\t" + "bne,a,pn %%icc, 1b\n\t" + " mov %1, %0" + : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) + : "r" (__memory), "r" (__bits) + : "cc"); #else #error "port me" #endif } -extern __inline__ void +extern __GNU_INLINE void atomic_or_32(volatile uint32_t *__memory, uint32_t __bits) { #if defined(__x86) __asm__ __volatile__( - "lock; orl %1, %0" - : "+m" (*__memory) - : "r" (__bits)); + "lock; orl %1, %0" + : "+m" (*__memory) + : "r" (__bits)); #elif defined(__sparc) uint32_t __tmp1, __tmp2; __asm__ __volatile__( - "ld [%3], %0\n\t" - "1:\n\t" - "or %0, %4, %1\n\t" - "cas [%3], %0, %1\n\t" - "cmp %0, %1\n\t" - "bne,a,pn %%icc, 1b\n\t" - " mov %1, %0" - : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) - : "r" (__memory), "r" (__bits) - : "cc"); + "ld [%3], %0\n\t" + "1:\n\t" + "or %0, %4, %1\n\t" + "cas [%3], %0, %1\n\t" + "cmp %0, %1\n\t" + "bne,a,pn %%icc, 1b\n\t" + " mov %1, %0" + : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory) + : "r" (__memory), "r" (__bits) + : "cc"); #else #error "port me" #endif @@ -297,14 +306,14 @@ atomic_or_32(volatile uint32_t *__memory, uint32_t __bits) #if defined(__sparc) /* only needed on sparc */ -extern __inline__ ulong_t +extern __GNU_INLINE ulong_t caller(void) { register ulong_t __value __asm__("i7"); return (__value); } -extern __inline__ ulong_t +extern __GNU_INLINE ulong_t getfp(void) { register ulong_t __value __asm__("fp"); @@ -315,7 +324,7 @@ getfp(void) #if defined(__x86) /* only needed on x86 */ -extern __inline__ void +extern __GNU_INLINE void ht_pause(void) { __asm__ __volatile__("rep; nop"); diff --git a/usr/src/lib/libc/port/unwind/unwind.c b/usr/src/lib/libc/port/unwind/unwind.c index 2a7f0ccc0f..e457f8df5c 100644 --- a/usr/src/lib/libc/port/unwind/unwind.c +++ b/usr/src/lib/libc/port/unwind/unwind.c @@ -24,8 +24,6 @@ * Use is subject to license terms. */ -#pragma ident "%Z%%M% %I% %E% SMI" - #include "lint.h" #include "thr_uberdata.h" #include <dlfcn.h> @@ -40,9 +38,13 @@ * _ex_unwind() is provided by libC, but if libC is not loaded we * need to call a local version of _ex_unwind() which does exactly * the same thing except for calling C++ destructors. + * + * Note that neither of these literally "returns twice" as, for eg, setjmp + * does, but they induce unusual control flow which the compiler should treat + * in the same manner (make all registers dead, etc.). */ -extern void _ex_clnup_handler(void *, void (*)(void *)); -extern void _ex_unwind_local(void); +extern void _ex_clnup_handler(void *, void (*)(void *)) __RETURNS_TWICE; +extern void _ex_unwind_local(void) __RETURNS_TWICE; #pragma unknown_control_flow(_ex_clnup_handler) #pragma unknown_control_flow(_ex_unwind_local) diff --git a/usr/src/lib/libc/sparc/Makefile.com b/usr/src/lib/libc/sparc/Makefile.com index f1ed31ea41..b19adadaea 100644 --- a/usr/src/lib/libc/sparc/Makefile.com +++ b/usr/src/lib/libc/sparc/Makefile.com @@ -1204,8 +1204,9 @@ TIL= \ $(TIL:%=pics/%) := CFLAGS += $(LIBCBASE)/threads/sparc.il -# This hack is needed until the sparc gcc is fixed for TLS -pics/tls_data.o := CC = env 'CW_NO_SHADOW=1' $(ONBLD_TOOLS)/bin/$(MACH)/cw -_cc +# This hack is needed because sparc GCC3 generates DWARF data about TLS which +# The Sun assembler cannot process +$(__GNUC3)pics/tls_data.o := CTF_FLAGS += -_gcc=-g1 # special kludge for inlines with 'cas': pics/rwlock.o pics/synch.o pics/lwp.o pics/door_calls.o := \ diff --git a/usr/src/lib/libc/sparc/crt/_rtboot.s b/usr/src/lib/libc/sparc/crt/_rtboot.s index 7764d40507..3e4a2b72ef 100644 --- a/usr/src/lib/libc/sparc/crt/_rtboot.s +++ b/usr/src/lib/libc/sparc/crt/_rtboot.s @@ -74,7 +74,7 @@ .section ".text" .volatile .global __rtboot - .local __rtld + .global __rtld .local s.LDSO, s.ZERO .local f.PANIC, f.OPENAT, f.MMAP, f.FSTATAT, f.SYSCONFIG .local f.CLOSE, f.EXIT, f.MUNMAP diff --git a/usr/src/lib/libc/sparc/crt/_rtld.c b/usr/src/lib/libc/sparc/crt/_rtld.c index 132aad09c0..a9e9c6d98a 100644 --- a/usr/src/lib/libc/sparc/crt/_rtld.c +++ b/usr/src/lib/libc/sparc/crt/_rtld.c @@ -70,7 +70,7 @@ * order to maintain the "no bootstrapping" requirement -- it calls only * local functions, uses no intrinsics, etc. */ -static void * +void * __rtld(Elf32_Boot *ebp, const char *strings[], int (*funcs[])()) { int i, p; /* working */ diff --git a/usr/src/lib/libc/sparcv9/Makefile.com b/usr/src/lib/libc/sparcv9/Makefile.com index 226547fa6d..82438151c7 100644 --- a/usr/src/lib/libc/sparcv9/Makefile.com +++ b/usr/src/lib/libc/sparcv9/Makefile.com @@ -1136,8 +1136,9 @@ TIL= \ $(TIL:%=pics/%) := CFLAGS64 += $(LIBCBASE)/threads/sparcv9.il -# This hack is needed until the sparc gcc is fixed for TLS -pics/tls_data.o := CC = env 'CW_NO_SHADOW=1' $(ONBLD_TOOLS)/bin/$(MACH)/cw -_cc +# This hack is needed because sparc GCC3 generates DWARF data about TLS which +# The Sun assembler cannot process +$(__GNUC3)pics/tls_data.o := CTF_FLAGS += -_gcc=-g1 # Files in fp, port/fp subdirectories that need base.il inline template IL= \ |