diff options
Diffstat (limited to 'usr/src/man/man3cpc')
22 files changed, 416 insertions, 752 deletions
diff --git a/usr/src/man/man3cpc/cpc.3cpc b/usr/src/man/man3cpc/cpc.3cpc index c254e5a960..4083b9877c 100644 --- a/usr/src/man/man3cpc/cpc.3cpc +++ b/usr/src/man/man3cpc/cpc.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc 3CPC "8 Oct 2008" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC 3CPC "Oct 8, 2008" .SH NAME cpc \- hardware performance counters .SH DESCRIPTION @@ -39,47 +39,39 @@ cannot simultaneously be both shared and private. The following configuration interfaces are provided: .sp .ne 2 -.mk .na \fB\fBcpc_open\fR(3CPC)\fR .ad .RS 21n -.rt Check the version the application was compiled with against the version of the library. .RE .sp .ne 2 -.mk .na \fB\fBcpc_cciname\fR(3CPC)\fR .ad .RS 21n -.rt Return a printable string to describe the performance counters of the processor. .RE .sp .ne 2 -.mk .na \fB\fBcpc_npic\fR(3CPC)\fR .ad .RS 21n -.rt Return the number of performance counters on the processor. .RE .sp .ne 2 -.mk .na \fB\fBcpc_cpuref\fR(3CPC)\fR .ad .RS 21n -.rt Return a reference to documentation that should be consulted to understand how to use and interpret data from the performance counters. .RE diff --git a/usr/src/man/man3cpc/cpc_access.3cpc b/usr/src/man/man3cpc/cpc_access.3cpc index 86fe014b64..1579905f9a 100644 --- a/usr/src/man/man3cpc/cpc_access.3cpc +++ b/usr/src/man/man3cpc/cpc_access.3cpc @@ -4,7 +4,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_access 3CPC "28 Mar 2005" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_ACCESS 3CPC "Mar 28, 2005" .SH NAME cpc_access \- test access CPU performance counters .SH SYNOPSIS @@ -46,23 +46,19 @@ modified. The \fBcpc_access()\fR function will fail if: .sp .ne 2 -.mk .na \fB\fBEAGAIN\fR\fR .ad .RS 10n -.rt Another process may be sampling system-wide CPU statistics. .RE .sp .ne 2 -.mk .na \fB\fBENOSYS\fR\fR .ad .RS 10n -.rt CPU performance counters are inaccessible on this machine. This error can occur when the machine supports CPU performance counters, but some software components are missing. Check to see that all CPU Performance Counter packages @@ -77,15 +73,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -lw(2.75i) |lw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +l | l +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -MT-LevelMT-Safe +MT-Level MT-Safe _ -Interface StabilityObsolete +Interface Stability Obsolete .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_bind_curlwp.3cpc b/usr/src/man/man3cpc/cpc_bind_curlwp.3cpc index 66c7ab91e4..666bf6bb74 100644 --- a/usr/src/man/man3cpc/cpc_bind_curlwp.3cpc +++ b/usr/src/man/man3cpc/cpc_bind_curlwp.3cpc @@ -3,14 +3,14 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_bind_curlwp 3CPC "05 Mar 2007" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_BIND_CURLWP 3CPC "Mar 05, 2007" .SH NAME cpc_bind_curlwp, cpc_bind_pctx, cpc_bind_cpu, cpc_unbind, cpc_request_preset, cpc_set_restart \- bind request sets to hardware counters .SH SYNOPSIS .LP .nf -cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] +cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] #include <libcpc.h> \fBint\fR \fBcpc_bind_curlwp\fR(\fBcpc_t *\fR\fIcpc\fR, \fBcpc_set_t *\fR\fIset\fR, \fBuint_t\fR \fIflags\fR); @@ -141,12 +141,10 @@ specific error description to \fBstderr\fR. These functions will fail if: .sp .ne 2 -.mk .na \fB\fBEACCES\fR\fR .ad .RS 11n -.rt For \fBcpc_bind_curlwp()\fR, the system has Pentium 4 processors with HyperThreading and at least one physical processor has more than one hardware thread online. See NOTES. @@ -160,12 +158,10 @@ access to the requested hypervisor event was denied. .sp .ne 2 -.mk .na \fB\fBEAGAIN\fR\fR .ad .RS 11n -.rt For \fBcpc_bind_curlwp()\fR and \fBcpc_bind_pctx()\fR, the performance counters are not available for use by the application. .sp @@ -176,12 +172,10 @@ to a CPU at a time. .sp .ne 2 -.mk .na \fB\fBEINVAL\fR\fR .ad .RS 11n -.rt The set does not contain any requests or \fBcpc_set_add_request()\fR was not called. .sp @@ -205,23 +199,19 @@ For \fBcpc_request_preset()\fR and \fBcpc_set_restart()\fR, the calling .sp .ne 2 -.mk .na \fB\fBENOSYS\fR\fR .ad .RS 11n -.rt For \fBcpc_bind_cpu()\fR, the specified processor is not online. .RE .sp .ne 2 -.mk .na \fB\fBENOTSUP\fR\fR .ad .RS 11n -.rt The \fBcpc_bind_curlwp()\fR function was called with the \fBCPC_OVF_NOTIFY_EMT\fR flag, but the underlying processor is not capable of detecting counter overflow. @@ -229,12 +219,10 @@ detecting counter overflow. .sp .ne 2 -.mk .na \fB\fBESRCH\fR\fR .ad .RS 11n -.rt For \fBcpc_bind_pctx()\fR, the specified \fBLWP\fR in the target process does not exist. .RE @@ -314,14 +302,14 @@ for (iter = 1; iter <= 20; iter++) { break; /* ==> Computation to be measured goes here <== */ - + if (cpc_set_sample(cpc, set, after) == -1) break; - + cpc_buf_sub(cpc, diff, after, before); cpc_buf_get(cpc, diff, ind0, &val0); cpc_buf_get(cpc, diff, ind1, &val1); - + (void) printf("%3d: %" PRId64 " %" PRId64 "\en", iter, val0, val1); } @@ -367,7 +355,7 @@ emt_handler(int sig, siginfo_t *sip, void *arg) psignal(sig, "example"); psiginfo(sip, "example"); return; - } + } (void) printf("lwp%d - si_addr %p ucontext: %%pc %p %%sp %p\en", _lwp_self(), (void *)sip->si_addr, @@ -383,14 +371,14 @@ emt_handler(int sig, siginfo_t *sip, void *arg) (void) fflush(stdout); /* - * Update a request's preset and restart the counters. Counters which - * have not been preset with cpc_request_preset() will resume counting - * from their current value. + * Update a request's preset and restart the counters. Counters which + * have not been preset with cpc_request_preset() will resume counting + * from their current value. */ - (cpc_request_preset(cpc, ind1, val1) != 0) - error("cannot set preset for request %d: %s", ind1, - strerror(errno)); - if (cpc_set_restart(cpc, set) != 0) + (cpc_request_preset(cpc, ind1, val1) != 0) + error("cannot set preset for request %d: %s", ind1, + strerror(errno)); + if (cpc_set_restart(cpc, set) != 0) error("cannot restart lwp%d: %s", _lwp_self(), strerror(errno)); } .fi @@ -405,29 +393,29 @@ library and creates a set: .in +2 .nf #define PRESET (UINT64_MAX - 999ull) - + struct sigaction act; - ... + ... act.sa_sigaction = emt_handler; bzero(&act.sa_mask, sizeof (act.sa_mask)); act.sa_flags = SA_RESTART|SA_SIGINFO; if (sigaction(SIGEMT, &act, NULL) == -1) error("sigaction: %s", strerror(errno)); - + if ((index = cpc_set_add_request(cpc, set, event, PRESET, CPC_COUNT_USER | CPC_OVF_NOTIFY_EMT, 0, NULL)) != 0) error("cannot add request to set: %s", strerror(errno)); - + if ((buf = cpc_buf_create(cpc, set)) == NULL) error("cannot create buffer: %s", strerror(errno)); - + if (cpc_bind_curlwp(cpc, set, 0) == -1) error("cannot bind lwp%d: %s", _lwp_self(), strerror(errno)); - + for (iter = 1; iter <= 20; iter++) { /* ==> Computation to be measured goes here <== */ } - + cpc_unbind(cpc, set); /* done */ .fi .in -2 @@ -440,15 +428,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityEvolving +Interface Stability Evolving _ -MT-LevelSafe +MT-Level Safe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_bind_event.3cpc b/usr/src/man/man3cpc/cpc_bind_event.3cpc index 5030257344..cfc2878b25 100644 --- a/usr/src/man/man3cpc/cpc_bind_event.3cpc +++ b/usr/src/man/man3cpc/cpc_bind_event.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_bind_event 3CPC "02 Mar 2007" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_BIND_EVENT 3CPC "Mar 02, 2007" .SH NAME cpc_bind_event, cpc_take_sample, cpc_rele \- use CPU performance counters on lwps @@ -71,24 +71,20 @@ return \fB0\fR. Otherwise, these functions return \fB\(mi1\fR, and set The \fBcpc_bind_event()\fR and \fBcpc_take_sample()\fR functions will fail if: .sp .ne 2 -.mk .na \fB\fBEACCES\fR\fR .ad .RS 11n -.rt For \fBcpc_bind_event()\fR, access to the requested hypervisor event was denied. .RE .sp .ne 2 -.mk .na \fB\fBEAGAIN\fR\fR .ad .RS 11n -.rt Another process may be sampling system-wide CPU statistics. For \fBcpc_bind_event()\fR, this implies that no new contexts can be created. For \fBcpc_take_sample()\fR, this implies that the performance counter context has @@ -100,24 +96,20 @@ attempting to bind and sample the event once more. .sp .ne 2 -.mk .na \fB\fBEINVAL\fR\fR .ad .RS 11n -.rt The \fBcpc_take_sample()\fR function has been invoked before the context is bound. .RE .sp .ne 2 -.mk .na \fB\fBENOTSUP\fR\fR .ad .RS 11n -.rt The caller has attempted an operation that is illegal or not supported on the current platform, such as attempting to specify signal delivery on counter overflow on a CPU that doesn't generate an interrupt on counter overflow. @@ -198,7 +190,7 @@ for (iter = 1; iter <= 20; iter++) { } if (iter != 20) - error("can't sample '%s': %s", setting, strerror(errno)); + error("can't sample '%s': %s", setting, strerror(errno)); free(setting); return (0); @@ -301,15 +293,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -MT-LevelMT-Safe +MT-Level MT-Safe _ -Interface StabilityObsolete +Interface Stability Obsolete .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_buf_create.3cpc b/usr/src/man/man3cpc/cpc_buf_create.3cpc index 74400c8cf8..ca84c0739b 100644 --- a/usr/src/man/man3cpc/cpc_buf_create.3cpc +++ b/usr/src/man/man3cpc/cpc_buf_create.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_buf_create 3CPC "30 Jan 2004" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_BUF_CREATE 3CPC "Jan 30, 2004" .SH NAME cpc_buf_create, cpc_buf_destroy, cpc_set_sample, cpc_buf_get, cpc_buf_set, cpc_buf_hrtime, cpc_buf_tick, cpc_buf_sub, cpc_buf_add, cpc_buf_copy, @@ -11,7 +11,7 @@ cpc_buf_zero \- sample and manipulate CPC data .SH SYNOPSIS .LP .nf -cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] +cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] #include <libcpc.h> \fBcpc_buf_t *\fR\fBcpc_buf_create\fR(\fBcpc_t *\fR\fIcpc\fR, \fBcpc_set_t *\fR\fIset\fR); @@ -159,12 +159,10 @@ indicate the error. These functions will fail if: .sp .ne 2 -.mk .na \fB\fBEINVAL\fR\fR .ad .RS 10n -.rt For \fBcpc_set_sample()\fR, the set is not bound, the set and/or CPC buffer were not created with the given \fIcpc\fR handle, or the CPC buffer was not created with the supplied set. @@ -172,24 +170,20 @@ created with the supplied set. .sp .ne 2 -.mk .na \fB\fBEAGAIN\fR\fR .ad .RS 10n -.rt When using \fBcpc_set_sample()\fR to sample a CPU-bound set, the LWP has been unbound from the processor it is measuring. .RE .sp .ne 2 -.mk .na \fB\fBENOMEM\fR\fR .ad .RS 10n -.rt The library could not allocate enough memory for its internal data structures. .RE @@ -201,15 +195,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityEvolving +Interface Stability Evolving _ -MT-LevelSafe +MT-Level Safe .TE .SH SEE ALSO @@ -232,12 +225,10 @@ access is not possible, \fBcpc_set_sample()\fR must be used to read the counters. .sp .ne 2 -.mk .na \fBSPARC\fR .ad .RS 9n -.rt .sp .in +2 .nf @@ -250,12 +241,10 @@ wr %rN, %pic ! (All UltraSPARC, but see text) .sp .ne 2 -.mk .na \fBx86\fR .ad .RS 9n -.rt .sp .in +2 .nf diff --git a/usr/src/man/man3cpc/cpc_count_usr_events.3cpc b/usr/src/man/man3cpc/cpc_count_usr_events.3cpc index c369311f1c..36eaef55fb 100644 --- a/usr/src/man/man3cpc/cpc_count_usr_events.3cpc +++ b/usr/src/man/man3cpc/cpc_count_usr_events.3cpc @@ -4,7 +4,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_count_usr_events 3CPC "28 Mar 2005" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_COUNT_USR_EVENTS 3CPC "Mar 28, 2005" .SH NAME cpc_count_usr_events, cpc_count_sys_events \- enable and disable performance counters @@ -47,24 +47,20 @@ The \fBcpc_count_usr_events()\fR and \fBcpc_count_sys_events()\fR functions will fail if: .sp .ne 2 -.mk .na \fB\fBEAGAIN\fR \fR .ad .RS 11n -.rt The associated performance counter context has been invalidated by another process. .RE .sp .ne 2 -.mk .na \fB\fBEINVAL\fR \fR .ad .RS 11n -.rt No performance counter context has been created, or an attempt was made to enable system events while delivering counter overflow signals. .RE @@ -121,15 +117,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -MT-LevelMT-Safe +MT-Level MT-Safe _ -Interface StabilityObsolete +Interface Stability Obsolete .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_enable.3cpc b/usr/src/man/man3cpc/cpc_enable.3cpc index eebbd23911..34f549719d 100644 --- a/usr/src/man/man3cpc/cpc_enable.3cpc +++ b/usr/src/man/man3cpc/cpc_enable.3cpc @@ -3,13 +3,13 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_enable 3CPC "31 Jan 2005" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_ENABLE 3CPC "Jan 31, 2005" .SH NAME cpc_enable, cpc_disable \- enable and disable performance counters .SH SYNOPSIS .LP .nf -cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] +cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] #include <libcpc.h> \fBint\fR \fBcpc_enable\fR(\fBcpc_t *\fR\fIcpc\fR); @@ -39,24 +39,20 @@ Upon successful completion, \fBcpc_enable()\fR and \fBcpc_disable()\fR return These functions will fail if: .sp .ne 2 -.mk .na \fB\fBEAGAIN\fR\fR .ad .RS 10n -.rt The associated performance counter context has been invalidated by another process. .RE .sp .ne 2 -.mk .na \fB\fBEINVAL\fR\fR .ad .RS 10n -.rt No performance counter context has been created for the calling LWP. .RE @@ -87,15 +83,15 @@ main(int argc, char *argv[]) { cpc_t *cpc = cpc_open(CPC_VER_CURRENT); /* ... application code ... */ - + if (cpc != NULL) (void) cpc_enable(cpc); - + /* ==> Code to be measured goes here <== */ - + if (cpc != NULL) (void) cpc_disable(cpc); - + /* ... other application code */ } .fi @@ -109,15 +105,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityEvolving +Interface Stability Evolving _ -MT-LevelSafe +MT-Level Safe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_event.3cpc b/usr/src/man/man3cpc/cpc_event.3cpc index ad33e69146..ad56fa9336 100644 --- a/usr/src/man/man3cpc/cpc_event.3cpc +++ b/usr/src/man/man3cpc/cpc_event.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_event 3CPC "12 May 2003" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_EVENT 3CPC "May 12, 2003" .SH NAME cpc_event \- data structure to describe CPU performance counters .SH SYNOPSIS @@ -86,13 +86,12 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityEvolving +Interface Stability Evolving .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_event_diff.3cpc b/usr/src/man/man3cpc/cpc_event_diff.3cpc index 61525f7627..ff6cbd264f 100644 --- a/usr/src/man/man3cpc/cpc_event_diff.3cpc +++ b/usr/src/man/man3cpc/cpc_event_diff.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_event_diff 3CPC "28 Mar 2005" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_EVENT_DIFF 3CPC "Mar 28, 2005" .SH NAME cpc_event_diff, cpc_event_accum \- simple difference and accumulate operations .SH SYNOPSIS @@ -72,15 +72,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityObsolete +Interface Stability Obsolete _ -MT-LevelMT-Safe +MT-Level MT-Safe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_getcpuver.3cpc b/usr/src/man/man3cpc/cpc_getcpuver.3cpc index 4275d1ad4a..d51ba41301 100644 --- a/usr/src/man/man3cpc/cpc_getcpuver.3cpc +++ b/usr/src/man/man3cpc/cpc_getcpuver.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_getcpuver 3CPC "28 Mar 2005" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_GETCPUVER 3CPC "Mar 28, 2005" .SH NAME cpc_getcpuver, cpc_getcciname, cpc_getcpuref, cpc_getusage, cpc_getnpic, cpc_walk_names \- determine CPU performance counter configuration @@ -115,15 +115,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -MT-LevelMT-Safe +MT-Level MT-Safe _ -Interface StabilityObsolete +Interface Stability Obsolete .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_npic.3cpc b/usr/src/man/man3cpc/cpc_npic.3cpc index 15d35abc0b..eb835b5f00 100644 --- a/usr/src/man/man3cpc/cpc_npic.3cpc +++ b/usr/src/man/man3cpc/cpc_npic.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_npic 3CPC "8 Oct 2008" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_NPIC 3CPC "Oct 8, 2008" .SH NAME cpc_npic, cpc_caps, cpc_cciname, cpc_cpuref, cpc_walk_events_all, cpc_walk_generic_events_all, cpc_walk_events_pic, cpc_walk_generic_events_pic, @@ -11,7 +11,7 @@ cpc_walk_attrs \- determine CPU performance counter configuration .SH SYNOPSIS .LP .nf -cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] +cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] #include <libcpc.h> \fBuint_t\fR \fBcpc_npic\fR(\fBcpc_t *\fR\fIcpc\fR); @@ -52,7 +52,7 @@ cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|. .LP .nf -\fBvoid\fR \fBcpc_walk_generic_events_pic\fR(\fBcpc_t *\fR\fIcpc\fR, \fBuint_t\fR \fIpicno\fR, +\fBvoid\fR \fBcpc_walk_generic_events_pic\fR(\fBcpc_t *\fR\fIcpc\fR, \fBuint_t\fR \fIpicno\fR, \fBvoid *\fR\fIarg\fR, \fBvoid\fR (*\fIaction\fR)(\fBvoid *\fR\fIarg\fR, \fBuint_t\fR \fIpicno\fR, \fBconst char *\fR\fIevent\fR)); .fi @@ -172,12 +172,10 @@ The \fBcpc_walk_events_all()\fR, \fBcpc_walk_events_pic()\fR, \fBcpc_walk_generic_events_pic()\fR functions will fail if: .sp .ne 2 -.mk .na \fB\fBENOMEM\fR\fR .ad .RS 10n -.rt There is not enough memory available. .RE @@ -189,15 +187,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityCommitted +Interface Stability Committed _ -MT-LevelSafe +MT-Level Safe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_open.3cpc b/usr/src/man/man3cpc/cpc_open.3cpc index ae654cd8d8..0e7c335305 100644 --- a/usr/src/man/man3cpc/cpc_open.3cpc +++ b/usr/src/man/man3cpc/cpc_open.3cpc @@ -3,13 +3,13 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_open 3CPC "30 Jan 2004" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_OPEN 3CPC "Jan 30, 2004" .SH NAME cpc_open, cpc_close \- initialize the CPU Performance Counter library .SH SYNOPSIS .LP .nf -cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] +cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] #include <libcpc.h> \fBcpc_t *\fR\fBcpc_open\fR(\fBint\fR \fIvers\fR); @@ -54,12 +54,10 @@ The \fBcpc_close()\fR function always returns 0. These functions will fail if: .sp .ne 2 -.mk .na \fB\fBEINVAL\fR\fR .ad .RS 10n -.rt The version requested by the client is incompatible with the implementation. .RE @@ -71,15 +69,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityEvolving +Interface Stability Evolving _ -MT-LevelSafe +MT-Level Safe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_pctx_bind_event.3cpc b/usr/src/man/man3cpc/cpc_pctx_bind_event.3cpc index afcb0645ce..1916c82cbe 100644 --- a/usr/src/man/man3cpc/cpc_pctx_bind_event.3cpc +++ b/usr/src/man/man3cpc/cpc_pctx_bind_event.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_pctx_bind_event 3CPC "05 Mar 2007" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_PCTX_BIND_EVENT 3CPC "Mar 05, 2007" .SH NAME cpc_pctx_bind_event, cpc_pctx_take_sample, cpc_pctx_rele, cpc_pctx_invalidate \- access CPU performance counters in other processes @@ -68,24 +68,20 @@ analogous functions described on the \fBcpc_bind_event\fR(3CPC) manual page. In addition, these function may fail if: .sp .ne 2 -.mk .na \fB\fBEACCES\fR\fR .ad .RS 10n -.rt For \fBcpc_pctx_bind_event()\fR, access to the requested hypervisor event was denied. .RE .sp .ne 2 -.mk .na \fB\fBESRCH\fR\fR .ad .RS 10n -.rt The value of the \fIlwpid\fR argument is invalid in the context of the controlled process. .RE @@ -98,15 +94,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -MT-LevelUnsafe +MT-Level Unsafe _ -Interface StabilityEvolving +Interface Stability Evolving .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_set_create.3cpc b/usr/src/man/man3cpc/cpc_set_create.3cpc index 02dfa86aa9..71e691ab50 100644 --- a/usr/src/man/man3cpc/cpc_set_create.3cpc +++ b/usr/src/man/man3cpc/cpc_set_create.3cpc @@ -3,14 +3,14 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_set_create 3CPC "20 Aug 2007" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_SET_CREATE 3CPC "Aug 20, 2007" .SH NAME cpc_set_create, cpc_set_destroy, cpc_set_add_request, cpc_walk_requests \- manage sets of counter requests .SH SYNOPSIS .LP .nf -cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] +cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] #include <libcpc.h> \fBcpc_set_t *\fR\fBcpc_set_create\fR(\fBcpc_t *\fR\fIcpc\fR); @@ -64,12 +64,10 @@ The \fBcpc_set_add_request()\fR function specifies a configuration of a hardware counter. The arguments to \fBcpc_set_add_request()\fR are: .sp .ne 2 -.mk .na \fB\fIevent\fR\fR .ad .RS 17n -.rt A string containing the name of an event supported by the system's processor. The \fBcpc_walk_events_all()\fR and \fBcpc_walk_events_pic()\fR functions (both described on \fBcpc_npic\fR(3CPC)) can be used to query the processor for the @@ -80,28 +78,23 @@ in which case a string representation of an event code in a form acceptable to .sp .ne 2 -.mk .na \fB\fIpreset\fR\fR .ad .RS 17n -.rt The value with which the system initializes the counter. .RE .sp .ne 2 -.mk .na \fB\fIflags\fR\fR .ad .RS 17n -.rt Three flags are defined that modify the behavior of the counter acting on behalf of this request: .sp .ne 2 -.mk .na \fB\fBCPC_COUNT_USER\fR\fR .ad @@ -112,7 +105,6 @@ The counter should count events that occur while the processor is in user mode. .sp .ne 2 -.mk .na \fB\fBCPC_COUNT_SYSTEM\fR\fR .ad @@ -124,7 +116,6 @@ mode. .sp .ne 2 -.mk .na \fB\fBCPC_OVF_NOTIFY_EMT\fR\fR .ad @@ -143,12 +134,10 @@ specified to program the hardware for counting. .sp .ne 2 -.mk .na \fB\fInattrs\fR, \fIattrs\fR\fR .ad .RS 17n -.rt The \fInattrs\fR argument specifies the number of attributes pointed to by the \fIattrs\fR argument, which is an array of \fBcpc_attr_t\fR structures containing processor-specific attributes that modify the request's @@ -185,12 +174,10 @@ error. These functions will fail if: .sp .ne 2 -.mk .na \fB\fBEINVAL\fR\fR .ad .RS 10n -.rt An event, attribute, or flag passed to \fBcpc_set_add_request()\fR was invalid. .sp For \fBcpc_set_destroy()\fR and \fBcpc_set_add_request()\fR, the set parameter @@ -199,12 +186,10 @@ was not created with the given cpc_t. .sp .ne 2 -.mk .na \fB\fBENOMEM\fR\fR .ad .RS 10n -.rt There was not enough memory available to the process to create the library's data structures. .RE @@ -217,15 +202,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityCommitted +Interface Stability Committed _ -MT-LevelSafe +MT-Level Safe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_seterrfn.3cpc b/usr/src/man/man3cpc/cpc_seterrfn.3cpc index 5eaa568af0..1de489e904 100644 --- a/usr/src/man/man3cpc/cpc_seterrfn.3cpc +++ b/usr/src/man/man3cpc/cpc_seterrfn.3cpc @@ -4,7 +4,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_seterrfn 3CPC "28 Mar 2005" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_SETERRFN 3CPC "Mar 28, 2005" .SH NAME cpc_seterrfn \- control libcpc error reporting .SH SYNOPSIS @@ -73,15 +73,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -MT-LevelUnsafe +MT-Level Unsafe _ -Interface StabilityObsolete +Interface Stability Obsolete .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_seterrhndlr.3cpc b/usr/src/man/man3cpc/cpc_seterrhndlr.3cpc index 359198dd74..3ffb25daa7 100644 --- a/usr/src/man/man3cpc/cpc_seterrhndlr.3cpc +++ b/usr/src/man/man3cpc/cpc_seterrhndlr.3cpc @@ -3,13 +3,13 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_seterrhndlr 3CPC "30 Jan 2004" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_SETERRHNDLR 3CPC "Jan 30, 2004" .SH NAME cpc_seterrhndlr \- control libcpc error reporting .SH SYNOPSIS .LP .nf -cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] +cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ] #include <libcpc.h> \fBtypedef void(\fR\fBcpc_errhndlr_t\fR)(\fBcpc_t *\fR\fIcpc\fR, \fBconst char *\fR\fIfn\fR, \fBint\fR \fIsubcode\fR, @@ -47,7 +47,6 @@ conditions while using \fBlibcpc\fR. The \fIfmt\fR string is provided as a convenience for easy printing. The error subcodes are: .sp .ne 2 -.mk .na \fB\fBCPC_INVALID_EVENT\fR\fR .ad @@ -58,7 +57,6 @@ A specified event is not supported by the processor. .sp .ne 2 -.mk .na \fB\fBCPC_INVALID_PICNUM\fR\fR .ad @@ -69,7 +67,6 @@ The counter number does not fall in the range of available counters. .sp .ne 2 -.mk .na \fB\fBCPC_INVALID_ATTRIBUTE\fR\fR .ad @@ -80,7 +77,6 @@ A specified attribute is not supported by the processor. .sp .ne 2 -.mk .na \fB\fBCPC_ATTRIBUTE_OUT_OF_RANGE\fR\fR .ad @@ -91,7 +87,6 @@ The value of an attribute is outside the range supported by the processor. .sp .ne 2 -.mk .na \fB\fBCPC_RESOURCE_UNAVAIL\fR\fR .ad @@ -102,7 +97,6 @@ A hardware resource necessary for completing an operation was unavailable. .sp .ne 2 -.mk .na \fB\fBCPC_PIC_NOT_CAPABLE\fR\fR .ad @@ -113,7 +107,6 @@ The requested counter cannot count an assigned event. .sp .ne 2 -.mk .na \fB\fBCPC_REQ_INVALID_FLAGS\fR\fR .ad @@ -124,7 +117,6 @@ One or more requests has invalid flags. .sp .ne 2 -.mk .na \fB\fBCPC_CONFLICTING_REQS\fR\fR .ad @@ -135,7 +127,6 @@ The requests in a set cannot be programmed onto the hardware at the same time. .sp .ne 2 -.mk .na \fB\fBCPC_ATTR_REQUIRES_PRIVILEGE\fR\fR .ad @@ -182,15 +173,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityEvolving +Interface Stability Evolving _ -MT-LevelSafe +MT-Level Safe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_shared_open.3cpc b/usr/src/man/man3cpc/cpc_shared_open.3cpc index 74c483a63d..4520ea87a7 100644 --- a/usr/src/man/man3cpc/cpc_shared_open.3cpc +++ b/usr/src/man/man3cpc/cpc_shared_open.3cpc @@ -4,7 +4,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_shared_open 3CPC "28 Mar 2005" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_SHARED_OPEN 3CPC "Mar 28, 2005" .SH NAME cpc_shared_open, cpc_shared_bind_event, cpc_shared_take_sample, cpc_shared_rele, cpc_shared_close \- use CPU performance counters on processors @@ -93,24 +93,20 @@ failure, the functions return -1 and set \fBerrno\fR to indicate the reason. .SH ERRORS .sp .ne 2 -.mk .na \fB\fBEACCES\fR\fR .ad .RS 11n -.rt The caller does not have appropriate privilege to access the CPU performance counters system-wide. .RE .sp .ne 2 -.mk .na \fB\fBEAGAIN\fR\fR .ad .RS 11n -.rt For cpc_shared_open(\|), this value implies that the counters on the bound cpu are busy because they are already being used to measure system-wide events by some other caller. @@ -118,12 +114,10 @@ some other caller. .sp .ne 2 -.mk .na \fB\fBEAGAIN\fR\fR .ad .RS 11n -.rt Otherwise, this return value implies that the counters are not available because the thread has been unbound from the processor it was bound to at open time. Robust programs should be coded to expect this behavior, and should @@ -132,36 +126,30 @@ invoke \fBcpc_shared_close\fR(\|), before retrying the operation. .sp .ne 2 -.mk .na \fB\fBEINVAL\fR\fR .ad .RS 11n -.rt The counters cannot be accessed on the current CPU because the calling thread is not bound to that CPU using \fBprocessor_bind\fR(2). .RE .sp .ne 2 -.mk .na \fB\fBENOTSUP\fR\fR .ad .RS 11n -.rt The caller has attempted an operation that is illegal or not supported on the current platform. .RE .sp .ne 2 -.mk .na \fB\fBENXIO\fR\fR .ad .RS 11n -.rt The current machine either has no performance counters, or has been configured to disallow access to them system-wide. .RE @@ -174,15 +162,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -MT-LevelMT-Safe +MT-Level MT-Safe _ -Interface StabilityObsolete +Interface Stability Obsolete .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_strtoevent.3cpc b/usr/src/man/man3cpc/cpc_strtoevent.3cpc index afd1974a31..cc08a937f4 100644 --- a/usr/src/man/man3cpc/cpc_strtoevent.3cpc +++ b/usr/src/man/man3cpc/cpc_strtoevent.3cpc @@ -4,7 +4,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_strtoevent 3CPC "28 Mar 2005" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_STRTOEVENT 3CPC "Mar 28, 2005" .SH NAME cpc_strtoevent, cpc_eventtostr \- translate strings to and from events .SH SYNOPSIS @@ -86,7 +86,7 @@ On Pentium processors, the syntax for setting counter options is as follows: .in +2 .nf \fBpic0\fR=<eventspec>,\fBpic1\fR=<eventspec> [\fB,sys[[0|1]]]\fR [\fB,nouser[[0|1]]]\fR -[\fB,noedge[[0|1]]]\fR [\fB,pc[[0|1]]]\fR +[\fB,noedge[[0|1]]]\fR [\fB,pc[[0|1]]]\fR .fi .in -2 .sp @@ -153,15 +153,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityObsolete +Interface Stability Obsolete _ -MT-LevelMT-Safe +MT-Level MT-Safe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/cpc_version.3cpc b/usr/src/man/man3cpc/cpc_version.3cpc index 91b9b1d994..2df4e4cb6c 100644 --- a/usr/src/man/man3cpc/cpc_version.3cpc +++ b/usr/src/man/man3cpc/cpc_version.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH cpc_version 3CPC "28 Mar 2005" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH CPC_VERSION 3CPC "Mar 28, 2005" .SH NAME cpc_version \- coordinate CPC library and application versions .SH SYNOPSIS @@ -61,15 +61,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityEvolving +Interface Stability Evolving _ -MT-LevelUnsafe +MT-Level Unsafe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/generic_events.3cpc b/usr/src/man/man3cpc/generic_events.3cpc index 278c0b8db0..d3aee4e9ea 100644 --- a/usr/src/man/man3cpc/generic_events.3cpc +++ b/usr/src/man/man3cpc/generic_events.3cpc @@ -7,7 +7,7 @@ .\" OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. This open source software .\" license conforms to the BSD License template. .\" Portions Copyright (c) 2008, Sun Microsystems Inc. All Rights Reserved. -.TH generic_events 3CPC "8 Oct 2008" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH GENERIC_EVENTS 3CPC "Oct 8, 2008" .SH NAME generic_events \- generic performance counter events .SH DESCRIPTION @@ -22,1101 +22,901 @@ platform only need support a subset of the total set of generic events. The defined generic events are: .sp .ne 2 -.mk .na \fB\fBPAPI_br_cn\fR\fR .ad .RS 16n -.rt Conditional branch instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_br_ins\fR\fR .ad .RS 16n -.rt Branch instructions taken .RE .sp .ne 2 -.mk .na \fB\fBPAPI_br_msp\fR\fR .ad .RS 16n -.rt Conditional branch instructions mispredicted .RE .sp .ne 2 -.mk .na \fB\fBPAPI_br_ntk\fR\fR .ad .RS 16n -.rt Conditional branch instructions not taken .RE .sp .ne 2 -.mk .na \fB\fBPAPI_br_prc\fR\fR .ad .RS 16n -.rt Conditional branch instructions correctly predicted .RE .sp .ne 2 -.mk .na \fB\fBPAPI_br_ucn\fR\fR .ad .RS 16n -.rt Unconditional branch instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_bru_idl\fR\fR .ad .RS 16n -.rt Cycles branch units are idle .RE .sp .ne 2 -.mk .na \fB\fBPAPI_btac_m\fR\fR .ad .RS 16n -.rt Branch target address cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_ca_cln\fR\fR .ad .RS 16n -.rt Requests for exclusive access to clean cache line .RE .sp .ne 2 -.mk .na \fB\fBPAPI_ca_inv\fR\fR .ad .RS 16n -.rt Requests for cache invalidation .RE .sp .ne 2 -.mk .na \fB\fBPAPI_ca_itv\fR\fR .ad .RS 16n -.rt Requests for cache line intervention .RE .sp .ne 2 -.mk .na \fB\fBPAPI_ca_shr\fR\fR .ad .RS 16n -.rt Request for exclusive access to shared cache line .RE .sp .ne 2 -.mk .na \fB\fBPAPI_ca_snp\fR\fR .ad .RS 16n -.rt Request for cache snoop .RE .sp .ne 2 -.mk .na \fB\fBPAPI_csr_fal\fR\fR .ad .RS 16n -.rt Failed conditional store instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_csr_suc\fR\fR .ad .RS 16n -.rt Successful conditional store instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_csr_tot\fR\fR .ad .RS 16n -.rt Total conditional store instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fad_ins\fR\fR .ad .RS 16n -.rt Floating point add instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fdv_ins\fR\fR .ad .RS 16n -.rt Floating point divide instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fma_ins\fR\fR .ad .RS 16n -.rt Floating point multiply and add instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fml_ins\fR\fR .ad .RS 16n -.rt Floating point multiply instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fnv_ins\fR\fR .ad .RS 16n -.rt Floating point inverse instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fp_ops\fR\fR .ad .RS 16n -.rt Floating point operations .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fp_stal\fR\fR .ad .RS 16n -.rt Cycles the floating point unit stalled .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fpu_idl\fR\fR .ad .RS 16n -.rt Cycles the floating point units are idle .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fsq_ins\fR\fR .ad .RS 16n -.rt Floating point sqrt instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_ful_ccy\fR\fR .ad .RS 16n -.rt Cycles with maximum instructions completed .RE .sp .ne 2 -.mk .na \fB\fBPAPI_ful_icy\fR\fR .ad .RS 16n -.rt Cycles with maximum instruction issue .RE .sp .ne 2 -.mk .na \fB\fBPAPI_fxu_idl\fR\fR .ad .RS 16n -.rt Cycles when units are idle .RE .sp .ne 2 -.mk .na \fB\fBPAPI_hw_int\fR\fR .ad .RS 16n -.rt Hardware interrupts .RE .sp .ne 2 -.mk .na \fB\fBPAPI_int_ins\fR\fR .ad .RS 16n -.rt Integer instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_tot_cyc\fR\fR .ad .RS 16n -.rt Total cycles .RE .sp .ne 2 -.mk .na \fB\fBPAPI_tot_iis\fR\fR .ad .RS 16n -.rt Instructions issued .RE .sp .ne 2 -.mk .na \fB\fBPAPI_tot_ins\fR\fR .ad .RS 16n -.rt Instructions completed .RE .sp .ne 2 -.mk .na \fB\fBPAPI_vec_ins\fR\fR .ad .RS 16n -.rt VectorSIMD instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_dca\fR\fR .ad .RS 16n -.rt Level 1 data cache accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_dch\fR\fR .ad .RS 16n -.rt Level 1 data cache hits .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_dcm\fR\fR .ad .RS 16n -.rt Level 1 data cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_dcr\fR\fR .ad .RS 16n -.rt Level 1 data cache reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_dcw\fR\fR .ad .RS 16n -.rt Level 1 data cache writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_ica\fR\fR .ad .RS 16n -.rt Level 1 instruction cache accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_ich\fR\fR .ad .RS 16n -.rt Level 1 instruction cache hits .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_icm\fR\fR .ad .RS 16n -.rt Level 1 instruction cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_icr\fR\fR .ad .RS 16n -.rt Level 1 instruction cache reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_icw\fR\fR .ad .RS 16n -.rt Level 1 instruction cache writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_ldm\fR\fR .ad .RS 16n -.rt Level 1 cache load misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_stm\fR\fR .ad .RS 16n -.rt Level 1 cache store misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_tca\fR\fR .ad .RS 16n -.rt Level 1 cache accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_tch\fR\fR .ad .RS 16n -.rt Level 1 cache hits .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_tcm\fR\fR .ad .RS 16n -.rt Level 1 cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_tcr\fR\fR .ad .RS 16n -.rt Level 1 cache reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l1_tcw\fR\fR .ad .RS 16n -.rt Level 1 cache writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_dca\fR\fR .ad .RS 16n -.rt Level 2 data cache accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_dch\fR\fR .ad .RS 16n -.rt Level 2 data cache hits .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_dcm\fR\fR .ad .RS 16n -.rt Level 2 data cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_dcr\fR\fR .ad .RS 16n -.rt Level 2 data cache reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_dcw\fR\fR .ad .RS 16n -.rt Level 2 data cache writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_ica\fR\fR .ad .RS 16n -.rt Level 2 instruction cache accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_ich\fR\fR .ad .RS 16n -.rt Level 2 instruction cache hits .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_icm\fR\fR .ad .RS 16n -.rt Level 2 instruction cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_icr\fR\fR .ad .RS 16n -.rt Level 2 instruction cache reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_icw\fR\fR .ad .RS 16n -.rt Level 2 instruction cache writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_ldm\fR\fR .ad .RS 16n -.rt Level 2 cache load misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_stm\fR\fR .ad .RS 16n -.rt Level 2 cache store misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_tca\fR\fR .ad .RS 16n -.rt Level 2 cache accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_tch\fR\fR .ad .RS 16n -.rt Level 2 cache hits .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_tcm\fR\fR .ad .RS 16n -.rt Level 2 cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_tcr\fR\fR .ad .RS 16n -.rt Level 2 cache reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l2_tcw\fR\fR .ad .RS 16n -.rt Level 2 cache writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_dca\fR\fR .ad .RS 16n -.rt Level 3 data cache accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_dch\fR\fR .ad .RS 16n -.rt Level 3 data cache hits .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_dcm\fR\fR .ad .RS 16n -.rt Level 3 data cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_dcr\fR\fR .ad .RS 16n -.rt Level 3 data cache reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_dcw\fR\fR .ad .RS 16n -.rt Level 3 data cache writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_ica\fR\fR .ad .RS 16n -.rt Level 3 instruction cache accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_ich\fR\fR .ad .RS 16n -.rt Level 3 instruction cache hits .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_icm\fR\fR .ad .RS 16n -.rt Level 3 instruction cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_icr\fR\fR .ad .RS 16n -.rt Level 3 instruction cache reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_icw\fR\fR .ad .RS 16n -.rt Level 3 instruction cache writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_ldm\fR\fR .ad .RS 16n -.rt Level 3 cache load misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_stm\fR\fR .ad .RS 16n -.rt Level 3 cache store misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_tca\fR\fR .ad .RS 16n -.rt Level 3 cache accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_tch\fR\fR .ad .RS 16n -.rt Level 3 cache hits .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_tcm\fR\fR .ad .RS 16n -.rt Level 3 cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_tcr\fR\fR .ad .RS 16n -.rt Level 3 cache reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_l3_tcw\fR\fR .ad .RS 16n -.rt Level 3 cache writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_ld_ins\fR\fR .ad .RS 16n -.rt Load Instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_lst_ins\fR\fR .ad .RS 16n -.rt Loadstore Instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_lsu_idl\fR\fR .ad .RS 16n -.rt Cycles load store units are idle .RE .sp .ne 2 -.mk .na \fB\fBPAPI_mem_rcy\fR\fR .ad .RS 16n -.rt Cycles stalled waiting for memory reads .RE .sp .ne 2 -.mk .na \fB\fBPAPI_mem_scy\fR\fR .ad .RS 16n -.rt Cycles stalled waiting for memory accesses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_mem_wcy\fR\fR .ad .RS 16n -.rt Cycles stalled waiting for memory writes .RE .sp .ne 2 -.mk .na \fB\fBPAPI_prf_dm\fR\fR .ad .RS 16n -.rt Data prefetch cache misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_res_stl\fR\fR .ad .RS 16n -.rt Cycles stalled on any resource .RE .sp .ne 2 -.mk .na \fB\fBPAPI_sr_ins\fR\fR .ad .RS 16n -.rt Store Instructions .RE .sp .ne 2 -.mk .na \fB\fBPAPI_stl_ccy\fR\fR .ad .RS 16n -.rt Cycles with no instructions completed .RE .sp .ne 2 -.mk .na \fB\fBPAPI_syc_ins\fR\fR .ad .RS 16n -.rt Synchronization instructions completed .RE .sp .ne 2 -.mk .na \fB\fBPAPI_tlb_dm\fR\fR .ad .RS 16n -.rt Data TLB misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_tlb_im\fR\fR .ad .RS 16n -.rt Instruction TLB misses .RE .sp .ne 2 -.mk .na \fB\fBPAPI_tlb_sd\fR\fR .ad .RS 16n -.rt TLB shootdowns .RE .sp .ne 2 -.mk .na \fB\fBPAPI_tlb_tl\fR\fR .ad .RS 16n -.rt Total TLB misses .RE @@ -1129,43 +929,41 @@ associated attribute for all supported platforms. .sp .TS -tab(); -cw(1.81i) cw(2.32i) cw(1.36i) -lw(1.81i) lw(2.32i) lw(1.36i) -. -Generic EventPlatform EventUnit Mask +c c c +l l l . +Generic Event Platform Event Unit Mask _ -\fBPAPI_br_ins\fR\fBFR_retired_branches_w_excp_intr\fR0x0 -\fBPAPI_br_msp\fR\fBFR_retired_branches_mispred\fR0x0 -\fBPAPI_br_tkn\fR\fBFR_retired_taken_branches\fR0x0 -\fBPAPI_fp_ops\fR\fBFP_dispatched_fpu_ops\fR0x3 -\fBPAPI_fad_ins\fR\fBFP_dispatched_fpu_ops\fR0x1 -\fBPAPI_fml_ins\fR\fBFP_dispatched_fpu_ops\fR0x2 -\fBPAPI_fpu_idl\fR\fBFP_cycles_no_fpu_ops_retired\fR0x0 -\fBPAPI_tot_cyc\fR\fBBU_cpu_clk_unhalted\fR0x0 -\fBPAPI_tot_ins\fR\fBFR_retired_x86_instr_w_excp_intr\fR0x0 -\fBPAPI_l1_dca\fR\fBDC_access\fR0x0 -\fBPAPI_l1_dcm\fR\fBDC_miss\fR0x0 -\fBPAPI_l1_ldm\fR\fBDC_refill_from_L2\fR0xe -\fBPAPI_l1_stm\fR\fBDC_refill_from_L2\fR0x10 -\fBPAPI_l1_ica\fR\fBIC_fetch\fR0x0 -\fBPAPI_l1_icm\fR\fBIC_miss\fR0x0 -\fBPAPI_l1_icr\fR\fBIC_fetch\fR0x0 -\fBPAPI_l2_dch\fR\fBDC_refill_from_L2\fR0x1e -\fBPAPI_l2_dcm\fR\fBDC_refill_from_system\fR0x1e -\fBPAPI_l2_dcr\fR\fBDC_refill_from_L2\fR0xe -\fBPAPI_l2_dcw\fR\fBDC_refill_from_L2\fR0x10 -\fBPAPI_l2_ich\fR\fBIC_refill_from_L2\fR0x0 -\fBPAPI_l2_icm\fR\fBIC_refill_from_system\fR0x0 -\fBPAPI_l2_ldm\fR\fBDC_refill_from_system\fR0xe -\fBPAPI_l2_stm\fR\fBDC_refill_from_system\fR0x10 -\fBPAPI_res_stl\fR\fBFR_dispatch_stalls\fR0x0 -\fBPAPI_stl_icy\fR\fBFR_nothing_to_dispatch\fR0x0 -\fBPAPI_hw_int\fR\fBFR_taken_hardware_intrs\fR0x0 -\fBPAPI_tlb_dm\fR\fBDC_dtlb_L1_miss_L2_miss\fR0x0 -\fBPAPI_tlb_im\fR\fBIC_itlb_L1_miss_L2_miss\fR0x0 -\fBPAPI_fp_ins\fR\fBFR_retired_fpu_instr\fR0xd -\fBPAPI_vec_ins\fR\fBFR_retired_fpu_instr\fR0x4 +\fBPAPI_br_ins\fR \fBFR_retired_branches_w_excp_intr\fR 0x0 +\fBPAPI_br_msp\fR \fBFR_retired_branches_mispred\fR 0x0 +\fBPAPI_br_tkn\fR \fBFR_retired_taken_branches\fR 0x0 +\fBPAPI_fp_ops\fR \fBFP_dispatched_fpu_ops\fR 0x3 +\fBPAPI_fad_ins\fR \fBFP_dispatched_fpu_ops\fR 0x1 +\fBPAPI_fml_ins\fR \fBFP_dispatched_fpu_ops\fR 0x2 +\fBPAPI_fpu_idl\fR \fBFP_cycles_no_fpu_ops_retired\fR 0x0 +\fBPAPI_tot_cyc\fR \fBBU_cpu_clk_unhalted\fR 0x0 +\fBPAPI_tot_ins\fR \fBFR_retired_x86_instr_w_excp_intr\fR 0x0 +\fBPAPI_l1_dca\fR \fBDC_access\fR 0x0 +\fBPAPI_l1_dcm\fR \fBDC_miss\fR 0x0 +\fBPAPI_l1_ldm\fR \fBDC_refill_from_L2\fR 0xe +\fBPAPI_l1_stm\fR \fBDC_refill_from_L2\fR 0x10 +\fBPAPI_l1_ica\fR \fBIC_fetch\fR 0x0 +\fBPAPI_l1_icm\fR \fBIC_miss\fR 0x0 +\fBPAPI_l1_icr\fR \fBIC_fetch\fR 0x0 +\fBPAPI_l2_dch\fR \fBDC_refill_from_L2\fR 0x1e +\fBPAPI_l2_dcm\fR \fBDC_refill_from_system\fR 0x1e +\fBPAPI_l2_dcr\fR \fBDC_refill_from_L2\fR 0xe +\fBPAPI_l2_dcw\fR \fBDC_refill_from_L2\fR 0x10 +\fBPAPI_l2_ich\fR \fBIC_refill_from_L2\fR 0x0 +\fBPAPI_l2_icm\fR \fBIC_refill_from_system\fR 0x0 +\fBPAPI_l2_ldm\fR \fBDC_refill_from_system\fR 0xe +\fBPAPI_l2_stm\fR \fBDC_refill_from_system\fR 0x10 +\fBPAPI_res_stl\fR \fBFR_dispatch_stalls\fR 0x0 +\fBPAPI_stl_icy\fR \fBFR_nothing_to_dispatch\fR 0x0 +\fBPAPI_hw_int\fR \fBFR_taken_hardware_intrs\fR 0x0 +\fBPAPI_tlb_dm\fR \fBDC_dtlb_L1_miss_L2_miss\fR 0x0 +\fBPAPI_tlb_im\fR \fBIC_itlb_L1_miss_L2_miss\fR 0x0 +\fBPAPI_fp_ins\fR \fBFR_retired_fpu_instr\fR 0xd +\fBPAPI_vec_ins\fR \fBFR_retired_fpu_instr\fR 0x4 .TE .SS "AMD Opteron Family 0x10 Processors" @@ -1173,49 +971,47 @@ _ .sp .TS -tab(); -cw(1.81i) cw(2.32i) cw(1.36i) -lw(1.81i) lw(2.32i) lw(1.36i) -. -Generic EventPlatform EventEvent Mask +c c c +l l l . +Generic Event Platform Event Event Mask _ -\fBPAPI_br_ins\fR\fBFR_retired_branches_w_excp_intr\fR0x0 -\fBPAPI_br_msp\fR\fBFR_retired_branches_mispred\fR0x0 -\fBPAPI_br_tkn\fR\fBFR_retired_taken_branches\fR0x0 -\fBPAPI_fp_ops\fR\fBFP_dispatched_fpu_ops\fR0x3 -\fBPAPI_fad_ins\fR\fBFP_dispatched_fpu_ops\fR0x1 -\fBPAPI_fml_ins\fR\fBFP_dispatched_fpu_ops\fR0x2 -\fBPAPI_fpu_idl\fR\fBFP_cycles_no_fpu_ops_retired\fR0x0 -\fBPAPI_tot_cyc\fR\fBBU_cpu_clk_unhalted\fR0x0 -\fBPAPI_tot_ins\fR\fBFR_retired_x86_instr_w_excp_intr\fR0x0 -\fBPAPI_l1_dca\fR\fBDC_access\fR0x0 -\fBPAPI_l1_dcm\fR\fBDC_miss\fR0x0 -\fBPAPI_l1_ldm\fR\fBDC_refill_from_L2\fR0xe -\fBPAPI_l1_stm\fR\fBDC_refill_from_L2\fR0x10 -\fBPAPI_l1_ica\fR\fBIC_fetch\fR0x0 -\fBPAPI_l1_icm\fR\fBIC_miss\fR0x0 -\fBPAPI_l1_icr\fR\fBIC_fetch\fR0x0 -\fBPAPI_l2_dch\fR\fBDC_refill_from_L2\fR0x1e -\fBPAPI_l2_dcm\fR\fBDC_refill_from_system\fR0x1e -\fBPAPI_l2_dcr\fR\fBDC_refill_from_L2\fR0xe -\fBPAPI_l2_dcw\fR\fBDC_refill_from_L2\fR0x10 -\fBPAPI_l2_ich\fR\fBIC_refill_from_L2\fR0x0 -\fBPAPI_l2_icm\fR\fBIC_refill_from_system\fR0x0 -\fBPAPI_l2_ldm\fR\fBDC_refill_from_system\fR0xe -\fBPAPI_l2_stm\fR\fBDC_refill_from_system\fR0x10 -\fBPAPI_res_stl\fR\fBFR_dispatch_stalls\fR0x0 -\fBPAPI_stl_icy\fR\fBFR_nothing_to_dispatch\fR0x0 -\fBPAPI_hw_int\fR\fBFR_taken_hardware_intrs\fR0x0 -\fBPAPI_tlb_dm\fR\fBDC_dtlb_L1_miss_L2_miss\fR0x7 -\fBPAPI_tlb_im\fR\fBIC_itlb_L1_miss_L2_miss\fR0x3 -\fBPAPI_fp_ins\fR\fBFR_retired_fpu_instr\fR0xd -\fBPAPI_vec_ins\fR\fBFR_retired_fpu_instr\fR0x4 -\fBPAPI_l3_dcr\fR\fBL3_read_req\fR0xf1 -\fBPAPI_l3_icr\fR\fBL3_read_req\fR0xf2 -\fBPAPI_l3_tcr\fR\fBL3_read_req\fR0xf7 -\fBPAPI_l3_stm\fR\fBL3_miss\fR0xf4 -\fBPAPI_l3_ldm\fR\fBL3_miss\fR0xf3 -\fBPAPI_l3_tcm\fR\fBL3_miss\fR0xf7 +\fBPAPI_br_ins\fR \fBFR_retired_branches_w_excp_intr\fR 0x0 +\fBPAPI_br_msp\fR \fBFR_retired_branches_mispred\fR 0x0 +\fBPAPI_br_tkn\fR \fBFR_retired_taken_branches\fR 0x0 +\fBPAPI_fp_ops\fR \fBFP_dispatched_fpu_ops\fR 0x3 +\fBPAPI_fad_ins\fR \fBFP_dispatched_fpu_ops\fR 0x1 +\fBPAPI_fml_ins\fR \fBFP_dispatched_fpu_ops\fR 0x2 +\fBPAPI_fpu_idl\fR \fBFP_cycles_no_fpu_ops_retired\fR 0x0 +\fBPAPI_tot_cyc\fR \fBBU_cpu_clk_unhalted\fR 0x0 +\fBPAPI_tot_ins\fR \fBFR_retired_x86_instr_w_excp_intr\fR 0x0 +\fBPAPI_l1_dca\fR \fBDC_access\fR 0x0 +\fBPAPI_l1_dcm\fR \fBDC_miss\fR 0x0 +\fBPAPI_l1_ldm\fR \fBDC_refill_from_L2\fR 0xe +\fBPAPI_l1_stm\fR \fBDC_refill_from_L2\fR 0x10 +\fBPAPI_l1_ica\fR \fBIC_fetch\fR 0x0 +\fBPAPI_l1_icm\fR \fBIC_miss\fR 0x0 +\fBPAPI_l1_icr\fR \fBIC_fetch\fR 0x0 +\fBPAPI_l2_dch\fR \fBDC_refill_from_L2\fR 0x1e +\fBPAPI_l2_dcm\fR \fBDC_refill_from_system\fR 0x1e +\fBPAPI_l2_dcr\fR \fBDC_refill_from_L2\fR 0xe +\fBPAPI_l2_dcw\fR \fBDC_refill_from_L2\fR 0x10 +\fBPAPI_l2_ich\fR \fBIC_refill_from_L2\fR 0x0 +\fBPAPI_l2_icm\fR \fBIC_refill_from_system\fR 0x0 +\fBPAPI_l2_ldm\fR \fBDC_refill_from_system\fR 0xe +\fBPAPI_l2_stm\fR \fBDC_refill_from_system\fR 0x10 +\fBPAPI_res_stl\fR \fBFR_dispatch_stalls\fR 0x0 +\fBPAPI_stl_icy\fR \fBFR_nothing_to_dispatch\fR 0x0 +\fBPAPI_hw_int\fR \fBFR_taken_hardware_intrs\fR 0x0 +\fBPAPI_tlb_dm\fR \fBDC_dtlb_L1_miss_L2_miss\fR 0x7 +\fBPAPI_tlb_im\fR \fBIC_itlb_L1_miss_L2_miss\fR 0x3 +\fBPAPI_fp_ins\fR \fBFR_retired_fpu_instr\fR 0xd +\fBPAPI_vec_ins\fR \fBFR_retired_fpu_instr\fR 0x4 +\fBPAPI_l3_dcr\fR \fBL3_read_req\fR 0xf1 +\fBPAPI_l3_icr\fR \fBL3_read_req\fR 0xf2 +\fBPAPI_l3_tcr\fR \fBL3_read_req\fR 0xf7 +\fBPAPI_l3_stm\fR \fBL3_miss\fR 0xf4 +\fBPAPI_l3_ldm\fR \fBL3_miss\fR 0xf3 +\fBPAPI_l3_tcm\fR \fBL3_miss\fR 0xf7 .TE .SS "Intel Pentium IV Processor" @@ -1223,25 +1019,23 @@ _ .sp .TS -tab(); -cw(1.81i) cw(2.32i) cw(1.36i) -lw(1.81i) lw(2.32i) lw(1.36i) -. -Generic EventPlatform EventEvent Mask +c c c +l l l . +Generic Event Platform Event Event Mask _ -\fBPAPI_br_msp\fR\fBbranch_retired\fR0xa -\fBPAPI_br_ins\fR\fBbranch_retired\fR0xf -\fBPAPI_br_tkn\fR\fBbranch_retired\fR0xc -\fBPAPI_br_ntk\fR\fBbranch_retired\fR0x3 -\fBPAPI_br_prc\fR\fBbranch_retired\fR0x5 -\fBPAPI_tot_ins\fR\fBinstr_retired\fR0x3 -\fBPAPI_tot_cyc\fR\fBglobal_power_events\fR0x1 -\fBPAPI_tlb_dm\fR\fBpage_walk_type\fR0x1 -\fBPAPI_tlb_im\fR\fBpage_walk_type\fR0x2 -\fBPAPI_tlb_tm\fR\fBpage_walk_type\fR0x3 -\fBPAPI_l2_ldm\fR\fBBSQ_cache_reference\fR0x100 -\fBPAPI_l2_stm\fR\fBBSQ_cache_reference\fR0x400 -\fBPAPI_l2_tcm\fR\fBBSQ_cache_reference\fR0x500 +\fBPAPI_br_msp\fR \fBbranch_retired\fR 0xa +\fBPAPI_br_ins\fR \fBbranch_retired\fR 0xf +\fBPAPI_br_tkn\fR \fBbranch_retired\fR 0xc +\fBPAPI_br_ntk\fR \fBbranch_retired\fR 0x3 +\fBPAPI_br_prc\fR \fBbranch_retired\fR 0x5 +\fBPAPI_tot_ins\fR \fBinstr_retired\fR 0x3 +\fBPAPI_tot_cyc\fR \fBglobal_power_events\fR 0x1 +\fBPAPI_tlb_dm\fR \fBpage_walk_type\fR 0x1 +\fBPAPI_tlb_im\fR \fBpage_walk_type\fR 0x2 +\fBPAPI_tlb_tm\fR \fBpage_walk_type\fR 0x3 +\fBPAPI_l2_ldm\fR \fBBSQ_cache_reference\fR 0x100 +\fBPAPI_l2_stm\fR \fBBSQ_cache_reference\fR 0x400 +\fBPAPI_l2_tcm\fR \fBBSQ_cache_reference\fR 0x500 .TE .SS "Intel Pentium Pro/II/III Processor" @@ -1249,43 +1043,41 @@ _ .sp .TS -tab(); -cw(1.81i) cw(2.32i) cw(1.36i) -lw(1.81i) lw(2.32i) lw(1.36i) -. -Generic EventPlatform EventEvent Mask +c c c +l l l . +Generic Event Platform Event Event Mask _ -\fBPAPI_ca_shr\fR\fBl2_ifetch\fR0xf -\fBPAPI_ca_cln\fR\fBbus_tran_rfo\fR0x0 -\fBPAPI_ca_itv\fR\fBbus_tran_inval\fR0x0 -\fBPAPI_tlb_im\fR\fBitlb_miss\fR0x0 -\fBPAPI_btac_m\fR\fBbtb_misses\fR0x0 -\fBPAPI_hw_int\fR\fBhw_int_rx\fR0x0 -\fBPAPI_br_cn\fR\fBbr_inst_retired\fR0x0 -\fBPAPI_br_tkn\fR\fBbr_taken_retired\fR0x0 -\fBPAPI_br_msp\fR\fBbr_miss_pred_taken_ret\fR0x0 -\fBPAPI_br_ins\fR\fBbr_inst_retired\fR0x0 -\fBPAPI_res_stl\fR\fBresource_stalls\fR0x0 -\fBPAPI_tot_iis\fR\fBinst_decoder\fR0x0 -\fBPAPI_tot_ins\fR\fBinst_retired\fR0x0 -\fBPAPI_tot_cyc\fR\fBcpu_clk_unhalted\fR0x0 -\fBPAPI_l1_dcm\fR\fBdcu_lines_in\fR0x0 -\fBPAPI_l1_icm\fR\fBl2_ifetch\fR0xf -\fBPAPI_l1_tcm\fR\fBl2_rqsts\fR0xf -\fBPAPI_l1_dca\fR\fBdata_mem_refs\fR0x0 -\fBPAPI_l1_ldm\fR\fBl2_ld\fR0xf -\fBPAPI_l1_stm\fR\fBl2_st\fR0xf -\fBPAPI_l2_icm\fR\fBbus_tran_ifetch\fR0x0 -\fBPAPI_l2_dcr\fR\fBl2_ld\fR0xf -\fBPAPI_l2_dcw\fR\fBl2_st\fR0xf -\fBPAPI_l2_tcm\fR\fBl2_lines_in\fR0x0 -\fBPAPI_l2_tca\fR\fBl2_rqsts\fR0xf -\fBPAPI_l2_tcw\fR\fBl2_st\fR0xf -\fBPAPI_l2_stm\fR\fBl2_m_lines_inm\fR0x0 -\fBPAPI_fp_ins\fR\fBflops\fR0x0 -\fBPAPI_fp_ops\fR\fBflops\fR0x0 -\fBPAPI_fml_ins\fR\fBmul\fR0x0 -\fBPAPI_fdv_ins\fR\fBdiv\fR0x0 +\fBPAPI_ca_shr\fR \fBl2_ifetch\fR 0xf +\fBPAPI_ca_cln\fR \fBbus_tran_rfo\fR 0x0 +\fBPAPI_ca_itv\fR \fBbus_tran_inval\fR 0x0 +\fBPAPI_tlb_im\fR \fBitlb_miss\fR 0x0 +\fBPAPI_btac_m\fR \fBbtb_misses\fR 0x0 +\fBPAPI_hw_int\fR \fBhw_int_rx\fR 0x0 +\fBPAPI_br_cn\fR \fBbr_inst_retired\fR 0x0 +\fBPAPI_br_tkn\fR \fBbr_taken_retired\fR 0x0 +\fBPAPI_br_msp\fR \fBbr_miss_pred_taken_ret\fR 0x0 +\fBPAPI_br_ins\fR \fBbr_inst_retired\fR 0x0 +\fBPAPI_res_stl\fR \fBresource_stalls\fR 0x0 +\fBPAPI_tot_iis\fR \fBinst_decoder\fR 0x0 +\fBPAPI_tot_ins\fR \fBinst_retired\fR 0x0 +\fBPAPI_tot_cyc\fR \fBcpu_clk_unhalted\fR 0x0 +\fBPAPI_l1_dcm\fR \fBdcu_lines_in\fR 0x0 +\fBPAPI_l1_icm\fR \fBl2_ifetch\fR 0xf +\fBPAPI_l1_tcm\fR \fBl2_rqsts\fR 0xf +\fBPAPI_l1_dca\fR \fBdata_mem_refs\fR 0x0 +\fBPAPI_l1_ldm\fR \fBl2_ld\fR 0xf +\fBPAPI_l1_stm\fR \fBl2_st\fR 0xf +\fBPAPI_l2_icm\fR \fBbus_tran_ifetch\fR 0x0 +\fBPAPI_l2_dcr\fR \fBl2_ld\fR 0xf +\fBPAPI_l2_dcw\fR \fBl2_st\fR 0xf +\fBPAPI_l2_tcm\fR \fBl2_lines_in\fR 0x0 +\fBPAPI_l2_tca\fR \fBl2_rqsts\fR 0xf +\fBPAPI_l2_tcw\fR \fBl2_st\fR 0xf +\fBPAPI_l2_stm\fR \fBl2_m_lines_inm\fR 0x0 +\fBPAPI_fp_ins\fR \fBflops\fR 0x0 +\fBPAPI_fp_ops\fR \fBflops\fR 0x0 +\fBPAPI_fml_ins\fR \fBmul\fR 0x0 +\fBPAPI_fdv_ins\fR \fBdiv\fR 0x0 .TE .SS "UltraSPARC I/II Processor" @@ -1293,26 +1085,24 @@ _ .sp .TS -tab(); -cw(2.75i) cw(2.75i) -lw(2.75i) lw(2.75i) -. -Generic EventPlatform Event +c c +l l . +Generic Event Platform Event _ -\fBPAPI_tot_cyc\fR\fBCycle_cnt\fR -\fBPAPI_tot_ins\fR\fBInstr_cnt\fR -\fBPAPI_tot_iis\fR\fBInstr_cnt\fR -\fBPAPI_l1_dcr\fR\fBDC_rd\fR -\fBPAPI_l1_dcw\fR\fBDC_wr\fR -\fBPAPI_l1_ica\fR\fBIC_ref\fR -\fBPAPI_l1_ich\fR\fBIC_hit\fR -\fBPAPI_l2_tca\fR\fBEC_ref\fR -\fBPAPI_l2_dch\fR\fBEC_rd_hit\fR -\fBPAPI_l2_tch\fR\fBEC_hit\fR -\fBPAPI_l2_ich\fR\fBEC_ic_hit\fR -\fBPAPI_ca_inv\fR\fBEC_snoop_inv\fR -\fBPAPI_br_msp\fR\fBDispatch0_mispred\fR -\fBPAPI_ca_snp\fR\fBEC_snoop_cb\fR +\fBPAPI_tot_cyc\fR \fBCycle_cnt\fR +\fBPAPI_tot_ins\fR \fBInstr_cnt\fR +\fBPAPI_tot_iis\fR \fBInstr_cnt\fR +\fBPAPI_l1_dcr\fR \fBDC_rd\fR +\fBPAPI_l1_dcw\fR \fBDC_wr\fR +\fBPAPI_l1_ica\fR \fBIC_ref\fR +\fBPAPI_l1_ich\fR \fBIC_hit\fR +\fBPAPI_l2_tca\fR \fBEC_ref\fR +\fBPAPI_l2_dch\fR \fBEC_rd_hit\fR +\fBPAPI_l2_tch\fR \fBEC_hit\fR +\fBPAPI_l2_ich\fR \fBEC_ic_hit\fR +\fBPAPI_ca_inv\fR \fBEC_snoop_inv\fR +\fBPAPI_br_msp\fR \fBDispatch0_mispred\fR +\fBPAPI_ca_snp\fR \fBEC_snoop_cb\fR .TE .SS "UltraSPARC III/IIIi/IV Processor" @@ -1320,32 +1110,30 @@ _ .sp .TS -tab(); -cw(2.75i) cw(2.75i) -lw(2.75i) lw(2.75i) -. -Generic EventPlatform Event +c c +l l . +Generic Event Platform Event _ -\fBPAPI_tot_cyc\fR\fBCycle_cnt\fR -\fBPAPI_tot_ins\fR\fBInstr_cnt\fR -\fBPAPI_tot_iis\fR\fBInstr_cnt\fR -\fBPAPI_fma_ins\fR\fBFA_pipe_completion\fR -\fBPAPI_fml_ins\fR\fBFM_pipe_completion\fR -\fBPAPI_l1_dcr\fR\fBDC_rd\fR -\fBPAPI_l1_dcw\fR\fBDC_wr\fR -\fBPAPI_l1_ica\fR\fBIC_ref\fR -\fBPAPI_l1_icm\fR\fBIC_miss\fR -\fBPAPI_l2_tca\fR\fBEC_ref\fR -\fBPAPI_l2_ldm\fR\fBEC_rd_miss\fR -\fBPAPI_l2_tcm\fR\fBEC_misses\fR -\fBPAPI_l2_icm\fR\fBEC_ic_miss\fR -\fBPAPI_tlb_dm\fR\fBDTLB_miss\fR -\fBPAPI_tlb_im\fR\fBITLB_miss\fR -\fBPAPI_br_ntk\fR\fBIU_Stat_Br_count_untaken\fR -\fBPAPI_br_msp\fR\fBDispatch0_mispred\fR -\fBPAPI_br_tkn\fR\fBIU_Stat_Br_count_taken\fR -\fBPAPI_ca_inv\fR\fBEC_snoop_inv\fR -\fBPAPI_ca_snp\fR\fBEC_snoop_cb\fR +\fBPAPI_tot_cyc\fR \fBCycle_cnt\fR +\fBPAPI_tot_ins\fR \fBInstr_cnt\fR +\fBPAPI_tot_iis\fR \fBInstr_cnt\fR +\fBPAPI_fma_ins\fR \fBFA_pipe_completion\fR +\fBPAPI_fml_ins\fR \fBFM_pipe_completion\fR +\fBPAPI_l1_dcr\fR \fBDC_rd\fR +\fBPAPI_l1_dcw\fR \fBDC_wr\fR +\fBPAPI_l1_ica\fR \fBIC_ref\fR +\fBPAPI_l1_icm\fR \fBIC_miss\fR +\fBPAPI_l2_tca\fR \fBEC_ref\fR +\fBPAPI_l2_ldm\fR \fBEC_rd_miss\fR +\fBPAPI_l2_tcm\fR \fBEC_misses\fR +\fBPAPI_l2_icm\fR \fBEC_ic_miss\fR +\fBPAPI_tlb_dm\fR \fBDTLB_miss\fR +\fBPAPI_tlb_im\fR \fBITLB_miss\fR +\fBPAPI_br_ntk\fR \fBIU_Stat_Br_count_untaken\fR +\fBPAPI_br_msp\fR \fBDispatch0_mispred\fR +\fBPAPI_br_tkn\fR \fBIU_Stat_Br_count_taken\fR +\fBPAPI_ca_inv\fR \fBEC_snoop_inv\fR +\fBPAPI_ca_snp\fR \fBEC_snoop_cb\fR .TE .SS "UltraSPARC IV+ Processor" @@ -1353,35 +1141,33 @@ _ .sp .TS -tab(); -cw(2.75i) cw(2.75i) -lw(2.75i) lw(2.75i) -. -Generic EventPlatform Event +c c +l l . +Generic Event Platform Event _ -\fBPAPI_tot_cyc\fR\fBCycle_cnt\fR -\fBPAPI_tot_ins\fR\fBInstr_cnt\fR -\fBPAPI_tot_iis\fR\fBInstr_cnt\fR -\fBPAPI_fma_ins\fR\fBFA_pipe_completion\fR -\fBPAPI_fml_ins\fR\fBFM_pipe_completion\fR -\fBPAPI_l1_dcr\fR\fBDC_rd\fR -\fBPAPI_l1_stm\fR\fBDC_wr_miss\fR -\fBPAPI_l1_ica\fR\fBIC_ref\fR -\fBPAPI_l1_icm\fR\fBIC_L2_req\fR -\fBPAPI_l1_ldm\fR\fBDC_rd_miss\fR -\fBPAPI_l1_dcw\fR\fBDC_wr\fR -\fBPAPI_l2_tca\fR\fBL2_ref\fR -\fBPAPI_l2_ldm\fR\fBL2_rd_miss\fR -\fBPAPI_l2_icm\fR\fBL2_IC_miss\fR -\fBPAPI_l2_stm\fR\fBL2_write_miss\fR -\fBPAPI_l2_tcm\fR\fBL2_miss\fR -\fBPAPI_l3_tcm\fR\fBL3_miss\fR -\fBPAPI_l3_icm\fR\fBL3_IC_miss\fR -\fBPAPI_l3_ldm\fR\fBL3_rd_miss\fR -\fBPAPI_tlb_im\fR\fBITLB_miss\fR -\fBPAPI_tlb_dm\fR\fBDTLB_miss\fR -\fBPAPI_br_tkn\fR\fBIU_stat_br_count_taken\fR -\fBPAPI_br_ntk\fR\fBIU_stat_br_count_untaken\fR +\fBPAPI_tot_cyc\fR \fBCycle_cnt\fR +\fBPAPI_tot_ins\fR \fBInstr_cnt\fR +\fBPAPI_tot_iis\fR \fBInstr_cnt\fR +\fBPAPI_fma_ins\fR \fBFA_pipe_completion\fR +\fBPAPI_fml_ins\fR \fBFM_pipe_completion\fR +\fBPAPI_l1_dcr\fR \fBDC_rd\fR +\fBPAPI_l1_stm\fR \fBDC_wr_miss\fR +\fBPAPI_l1_ica\fR \fBIC_ref\fR +\fBPAPI_l1_icm\fR \fBIC_L2_req\fR +\fBPAPI_l1_ldm\fR \fBDC_rd_miss\fR +\fBPAPI_l1_dcw\fR \fBDC_wr\fR +\fBPAPI_l2_tca\fR \fBL2_ref\fR +\fBPAPI_l2_ldm\fR \fBL2_rd_miss\fR +\fBPAPI_l2_icm\fR \fBL2_IC_miss\fR +\fBPAPI_l2_stm\fR \fBL2_write_miss\fR +\fBPAPI_l2_tcm\fR \fBL2_miss\fR +\fBPAPI_l3_tcm\fR \fBL3_miss\fR +\fBPAPI_l3_icm\fR \fBL3_IC_miss\fR +\fBPAPI_l3_ldm\fR \fBL3_rd_miss\fR +\fBPAPI_tlb_im\fR \fBITLB_miss\fR +\fBPAPI_tlb_dm\fR \fBDTLB_miss\fR +\fBPAPI_br_tkn\fR \fBIU_stat_br_count_taken\fR +\fBPAPI_br_ntk\fR \fBIU_stat_br_count_untaken\fR .TE .SS "Niagara T1 Processor" @@ -1389,20 +1175,18 @@ _ .sp .TS -tab(); -cw(2.75i) cw(2.75i) -lw(2.75i) lw(2.75i) -. -Generic EventPlatform Event +c c +l l . +Generic Event Platform Event _ -\fBPAPI_tot_cyc\fR\fBCycle_cnt\fR -\fBPAPI_l2_icm\fR\fBL2_imiss\fR -\fBPAPI_l2_ldm\fR\fBL2_dmiss_ld\fR -\fBPAPI_fp_ops\fR\fBFP_instr_cnt\fR -\fBPAPI_l1_icm\fR\fBIC_miss\fR -\fBPAPI_l1_dcm\fR\fBDC_miss\fR -\fBPAPI_tlb_im\fR\fBITLB_miss\fR -\fBPAPI_tlb_dm\fR\fBDTLB_miss\fR +\fBPAPI_tot_cyc\fR \fBCycle_cnt\fR +\fBPAPI_l2_icm\fR \fBL2_imiss\fR +\fBPAPI_l2_ldm\fR \fBL2_dmiss_ld\fR +\fBPAPI_fp_ops\fR \fBFP_instr_cnt\fR +\fBPAPI_l1_icm\fR \fBIC_miss\fR +\fBPAPI_l1_dcm\fR \fBDC_miss\fR +\fBPAPI_tlb_im\fR \fBITLB_miss\fR +\fBPAPI_tlb_dm\fR \fBDTLB_miss\fR .TE .SS "Niagara T2 Processor" @@ -1410,24 +1194,22 @@ _ .sp .TS -tab(); -cw(2.75i) cw(2.75i) -lw(2.75i) lw(2.75i) -. -Generic EventPlatform Event +c c +l l . +Generic Event Platform Event _ -\fBPAPI_tot_ins\fR\fBInstr_cnt\fR -\fBPAPI_l1_dcm\fR\fBDC_miss\fR -\fBPAPI_l1_icm\fR\fBIC_miss\fR -\fBPAPI_l2_icm\fR\fBL2_imiss\fR -\fBPAPI_l2_ldm\fR\fBL2_dmiss_ld\fR -\fBPAPI_tlb_dm\fR\fBDTLB_miss\fR -\fBPAPI_tlb_im\fR\fBITLB_miss\fR -\fBPAPI_tlb_tm\fR\fBTLB_miss\fR -\fBPAPI_br_tkn\fR\fBBr_taken\fR -\fBPAPI_br_ins\fR\fBBr_completed\fR -\fBPAPI_ld_ins\fR\fBInstr_ld\fR -\fBPAPI_sr_ins\fR\fBInstr_st\fR +\fBPAPI_tot_ins\fR \fBInstr_cnt\fR +\fBPAPI_l1_dcm\fR \fBDC_miss\fR +\fBPAPI_l1_icm\fR \fBIC_miss\fR +\fBPAPI_l2_icm\fR \fBL2_imiss\fR +\fBPAPI_l2_ldm\fR \fBL2_dmiss_ld\fR +\fBPAPI_tlb_dm\fR \fBDTLB_miss\fR +\fBPAPI_tlb_im\fR \fBITLB_miss\fR +\fBPAPI_tlb_tm\fR \fBTLB_miss\fR +\fBPAPI_br_tkn\fR \fBBr_taken\fR +\fBPAPI_br_ins\fR \fBBr_completed\fR +\fBPAPI_ld_ins\fR \fBInstr_ld\fR +\fBPAPI_sr_ins\fR \fBInstr_st\fR .TE .SS "SPARC64 VI/VII Processor" @@ -1435,21 +1217,19 @@ _ .sp .TS -tab(); -cw(2.75i) cw(2.75i) -lw(2.75i) lw(2.75i) -. -Generic EventPlatform Event +c c +l l . +Generic Event Platform Event _ -\fBPAPI_tot_cyc\fR\fBcycle_counts\fR -\fBPAPI_tot_ins\fR\fBinstruction_counts\fR -\fBPAPI_br_tkn\fR\fBbranch_instructions\fR -\fBPAPI_fp_ops\fR\fBfloating_instructions\fR -\fBPAPI_fma_ins\fR\fBimpdep2_instructions\fR -\fBPAPI_l1_dcm\fR\fBop_r_iu_req_mi_go\fR -\fBPAPI_l1_icm\fR\fBif_r_iu_req_mi_go\fR -\fBPAPI_tlb_dm\fR\fBtrap_DMMU_miss\fR -\fBPAPI_tlb_im\fR\fBtrap_IMMU_miss\fR +\fBPAPI_tot_cyc\fR \fBcycle_counts\fR +\fBPAPI_tot_ins\fR \fBinstruction_counts\fR +\fBPAPI_br_tkn\fR \fBbranch_instructions\fR +\fBPAPI_fp_ops\fR \fBfloating_instructions\fR +\fBPAPI_fma_ins\fR \fBimpdep2_instructions\fR +\fBPAPI_l1_dcm\fR \fBop_r_iu_req_mi_go\fR +\fBPAPI_l1_icm\fR \fBif_r_iu_req_mi_go\fR +\fBPAPI_tlb_dm\fR \fBtrap_DMMU_miss\fR +\fBPAPI_tlb_im\fR \fBtrap_IMMU_miss\fR .TE .SH ATTRIBUTES @@ -1460,13 +1240,12 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityVolatile +Interface Stability Volatile .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/pctx_capture.3cpc b/usr/src/man/man3cpc/pctx_capture.3cpc index 949314ce93..6aa903669c 100644 --- a/usr/src/man/man3cpc/pctx_capture.3cpc +++ b/usr/src/man/man3cpc/pctx_capture.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH pctx_capture 3CPC "13 May 2003" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH PCTX_CAPTURE 3CPC "May 13, 2003" .SH NAME pctx_capture, pctx_create, pctx_run, pctx_release \- process context library .SH SYNOPSIS @@ -129,15 +129,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityEvolving +Interface Stability Evolving _ -MT-LevelUnsafe +MT-Level Unsafe .TE .SH SEE ALSO diff --git a/usr/src/man/man3cpc/pctx_set_events.3cpc b/usr/src/man/man3cpc/pctx_set_events.3cpc index dcab77aed4..81b009d439 100644 --- a/usr/src/man/man3cpc/pctx_set_events.3cpc +++ b/usr/src/man/man3cpc/pctx_set_events.3cpc @@ -3,7 +3,7 @@ .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH pctx_set_events 3CPC "13 May 2003" "SunOS 5.11" "CPU Performance Counters Library Functions" +.TH PCTX_SET_EVENTS 3CPC "May 13, 2003" .SH NAME pctx_set_events \- associate callbacks with process events .SH SYNOPSIS @@ -95,30 +95,29 @@ and the handlers executed by users of the library. .sp .TS -tab() box; -cw(1.02i) |cw(1.14i) |cw(3.34i) -cw(1.02i) |cw(1.14i) |cw(3.34i) -. +box; +c | c | c +c | c | c . System Calls and pctx Handlers _ -System callHandlerComments +System call Handler Comments _ -\fBexec\fR,\fBexecve\fR\fIfini_lwp\fRT{ +\fBexec\fR,\fBexecve\fR \fIfini_lwp\fR T{ Invoked serially on all lwps in the process. T} -\fIexec\fRT{ + \fIexec\fR T{ Only invoked if the \fBexec()\fR system call succeeded. T} -\fIinit_lwp\fRT{ + \fIinit_lwp\fR T{ If the exec succeeds, only invoked on lwp 1. If the exec fails, invoked serially on all lwps in the process. T} _ -\fBfork\fR, \fBvfork\fR, \fBfork1\fR\fIfork\fRT{ +\fBfork\fR, \fBvfork\fR, \fBfork1\fR \fIfork\fR T{ Only invoked if the \fBfork()\fR system call succeeded. T} _ -\fBexit\fR\fIfini_lwp\fRInvoked on all lwps in the process. -\fIexit\fRInvoked on the exiting lwp. +\fBexit\fR \fIfini_lwp\fR Invoked on all lwps in the process. + \fIexit\fR Invoked on the exiting lwp. .TE .sp @@ -178,15 +177,14 @@ See \fBattributes\fR(5) for descriptions of the following attributes: .sp .TS -tab() box; -cw(2.75i) |cw(2.75i) -lw(2.75i) |lw(2.75i) -. -ATTRIBUTE TYPEATTRIBUTE VALUE +box; +c | c +l | l . +ATTRIBUTE TYPE ATTRIBUTE VALUE _ -Interface StabilityEvolving +Interface Stability Evolving _ -MT-LevelUnsafe +MT-Level Unsafe .TE .SH SEE ALSO |