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path: root/usr/src/uts/intel/io/amdzen/zen_umc.c
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Diffstat (limited to 'usr/src/uts/intel/io/amdzen/zen_umc.c')
-rw-r--r--usr/src/uts/intel/io/amdzen/zen_umc.c72
1 files changed, 36 insertions, 36 deletions
diff --git a/usr/src/uts/intel/io/amdzen/zen_umc.c b/usr/src/uts/intel/io/amdzen/zen_umc.c
index 947c17b4ff..1a00ec29c3 100644
--- a/usr/src/uts/intel/io/amdzen/zen_umc.c
+++ b/usr/src/uts/intel/io/amdzen/zen_umc.c
@@ -1863,7 +1863,7 @@ zen_umc_fill_dimm_common(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
} else {
reg = UMC_DIMMCFG_DDR5(id, dimmno);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read DIMM "
"configuration register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -1939,7 +1939,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
const uint16_t reginst = i + dimmno * 2;
reg = UMC_BASE(id, reginst);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read base "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -1950,7 +1950,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
dimm->ud_cs[i].ucs_base.udb_valid = UMC_BASE_GET_EN(val);
reg = UMC_BASE_SEC(id, reginst);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"secondary base register %x: %d", SMN_REG_ADDR(reg),
ret);
@@ -1963,7 +1963,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_MASK_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read mask register "
"%x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -1979,7 +1979,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
cs1->ucs_base_mask = cs0->ucs_base_mask;
reg = UMC_MASK_SEC_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read secondary mask "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -1990,7 +1990,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
cs1->ucs_sec_mask = cs0->ucs_sec_mask;
reg = UMC_ADDRCFG_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read address config "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2026,7 +2026,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_ADDRSEL_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read bank address "
"select register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2051,7 +2051,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
sizeof (cs0->ucs_bank_bits));
reg = UMC_COLSEL_LO_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
"select low register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2062,7 +2062,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_COLSEL_HI_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
"select high register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2081,7 +2081,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
* zero.
*/
reg = UMC_RMSEL_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read rank address "
"select register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2097,7 +2097,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
bcopy(cs0->ucs_rm_bits, cs1->ucs_rm_bits, sizeof (cs0->ucs_rm_bits));
reg = UMC_RMSEL_SEC_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read secondary rank "
"address select register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2137,7 +2137,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
cs = &chan->chan_dimms[dimmno].ud_cs[rankno];
reg = UMC_BASE(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read base "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2149,7 +2149,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
reg = UMC_BASE_EXT_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"extended base register %x: %d", SMN_REG_ADDR(reg),
@@ -2163,7 +2163,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_BASE_SEC(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read secondary base "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2175,7 +2175,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
reg = UMC_BASE_EXT_SEC_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"extended secondary base register %x: %d",
@@ -2189,7 +2189,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_MASK_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read mask "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2201,7 +2201,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
reg = UMC_MASK_EXT_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"extended mask register %x: %d", SMN_REG_ADDR(reg),
@@ -2216,7 +2216,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
reg = UMC_MASK_SEC_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read secondary mask "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2228,7 +2228,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
reg = UMC_MASK_EXT_SEC_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"extended mask register %x: %d", SMN_REG_ADDR(reg),
@@ -2242,7 +2242,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_ADDRCFG_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read address config "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2263,7 +2263,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
cs->ucs_nbank_groups = UMC_ADDRCFG_GET_NBANKGRP_BITS(val);
reg = UMC_ADDRSEL_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read address select "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2283,7 +2283,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
UMC_ADDRSEL_BANK_BASE;
reg = UMC_COLSEL_LO_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
"select low register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2294,7 +2294,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_COLSEL_HI_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
"select high register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2311,7 +2311,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
* unless something actually points us there.
*/
reg = UMC_RMSEL_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read rank multiply "
"select register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2408,7 +2408,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_BANK_HASH_DDR5(id, i);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"bank hash register %x: %d",
@@ -2433,7 +2433,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_RANK_HASH_DDR5(id, i);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"rm hash register %x: %d",
@@ -2451,7 +2451,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
}
reg = UMC_RANK_HASH_EXT_DDR5(id, i);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"rm hash ext register %x: %d",
@@ -2474,7 +2474,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_PC_HASH_DDR5(id);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read pc hash "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2490,7 +2490,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_PC_HASH2_DDR5(id);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read pc hash "
"2 register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2510,7 +2510,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_CS_HASH_DDR5(id, i);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"cs hash register %x", SMN_REG_ADDR(reg));
@@ -2527,7 +2527,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
}
reg = UMC_CS_HASH_EXT_DDR5(id, i);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"cs hash ext register %x",
@@ -2573,7 +2573,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
}
reg = UMC_UMCCFG(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read UMC "
"configuration register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2596,7 +2596,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
* encrypting regions of memory.
*/
reg = UMC_DATACTL(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read data control "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2617,7 +2617,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
* cache it for future us and observability.
*/
reg = UMC_ECCCTL(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read ECC control "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2629,7 +2629,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
* future.
*/
reg = UMC_UMCCAP(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read UMC cap"
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2637,7 +2637,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
chan->chan_umccap_raw = val;
reg = UMC_UMCCAP_HI(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read UMC cap high "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-03 17:07:04 +0000