diff options
Diffstat (limited to 'usr/src/uts/intel/sys/mca_amd.h')
| -rw-r--r-- | usr/src/uts/intel/sys/mca_amd.h | 137 |
1 files changed, 96 insertions, 41 deletions
diff --git a/usr/src/uts/intel/sys/mca_amd.h b/usr/src/uts/intel/sys/mca_amd.h index 1b5b6b599f..6d45691c14 100644 --- a/usr/src/uts/intel/sys/mca_amd.h +++ b/usr/src/uts/intel/sys/mca_amd.h @@ -52,26 +52,31 @@ extern "C" { #define AMD_MSR_DC_MASK 0xc0010044 #define AMD_MSR_DC_STATUS 0x401 #define AMD_MSR_DC_ADDR 0x402 +#define AMD_MSR_DC_MISC 0x403 #define AMD_MSR_IC_CTL 0x404 #define AMD_MSR_IC_MASK 0xc0010045 #define AMD_MSR_IC_STATUS 0x405 #define AMD_MSR_IC_ADDR 0x406 +#define AMD_MSR_IC_MISC 0x407 #define AMD_MSR_BU_CTL 0x408 #define AMD_MSR_BU_MASK 0xc0010046 #define AMD_MSR_BU_STATUS 0x409 #define AMD_MSR_BU_ADDR 0x40a +#define AMD_MSR_BU_MISC 0x40b #define AMD_MSR_LS_CTL 0x40c #define AMD_MSR_LS_MASK 0xc0010047 #define AMD_MSR_LS_STATUS 0x40d #define AMD_MSR_LS_ADDR 0x40e +#define AMD_MSR_LS_MISC 0x40f #define AMD_MSR_NB_CTL 0x410 #define AMD_MSR_NB_MASK 0xc0010048 #define AMD_MSR_NB_STATUS 0x411 #define AMD_MSR_NB_ADDR 0x412 +#define AMD_MSR_NB_MISC 0x413 #define AMD_MCG_EN_DC 0x01 #define AMD_MCG_EN_IC 0x02 @@ -95,7 +100,7 @@ extern "C" { #define AMD_DC_EN_L1TP 0x00000020ULL #define AMD_DC_EN_L2TP 0x00000040ULL -#define AMD_DC_CTL_INIT \ +#define AMD_DC_CTL_INIT_CMN \ (AMD_DC_EN_ECCI | AMD_DC_EN_ECCM | AMD_DC_EN_DECC | AMD_DC_EN_DMTP | \ AMD_DC_EN_DSTP | AMD_DC_EN_L1TP | AMD_DC_EN_L2TP) @@ -116,7 +121,7 @@ extern "C" { #define AMD_IC_EN_L2TP 0x00000040ULL #define AMD_IC_EN_RDDE 0x00000200ULL -#define AMD_IC_CTL_INIT \ +#define AMD_IC_CTL_INIT_CMN \ (AMD_IC_EN_ECCI | AMD_IC_EN_ECCM | AMD_IC_EN_IDP | AMD_IC_EN_IMTP | \ AMD_IC_EN_ISTP | AMD_IC_EN_L1TP | AMD_IC_EN_L2TP) @@ -149,7 +154,7 @@ extern "C" { #define AMD_BU_EN_L2T_ECC1_SCR 0x00040000ULL #define AMD_BU_EN_L2T_ECCM_SCR 0x00080000ULL -#define AMD_BU_CTL_INIT \ +#define AMD_BU_CTL_INIT_CMN \ (AMD_BU_EN_S_ECC1_TLB | AMD_BU_EN_S_ECC1_HP | \ AMD_BU_EN_S_ECCM_TLB | AMD_BU_EN_S_ECCM_HP | \ AMD_BU_EN_L2T_PAR_ICDC | AMD_BU_EN_L2T_PAR_TLB | \ @@ -172,7 +177,19 @@ extern "C" { #define AMD_LS_EN_S_RDE_S 0x00000001ULL #define AMD_LS_EN_S_RDE_L 0x00000002ULL -#define AMD_LS_CTL_INIT 0ULL +#define AMD_LS_CTL_INIT_CMN 0ULL + +/* + * NorthBridge (NB) MCi_MISC - DRAM Errors Threshold Register. + */ +#define AMD_NB_MISC_VALID (0x1ULL << 63) +#define AMD_NB_MISC_CTRP (0x1ULL << 62) +#define AMD_NB_MISC_LOCKED (0x1ULL << 61) +#define AMD_NB_MISC_CNTEN (0x1ULL << 51) +#define AMD_NB_MISC_INTTYPE (0x1ULL << 49) +#define AMD_NB_MISC_INTTYPE_MASK (0x3ULL << 49) +#define AMD_NB_MISC_OVRFLW (0x1ULL << 48) +#define AMD_NB_MISC_ERRCOUNT_MASK (0xfffULL << 32) /* * The Northbridge (NB) is configured using both the standard MCA CTL register @@ -183,46 +200,80 @@ extern "C" { * The CTL register can be initialized statically, but portions of the NB CFG * register must be initialized based on the current machine's configuration. * - * The MCA NB Control Register maps to MC4_CTL[31:0]. + * The MCA NB Control Register maps to MC4_CTL[31:0], but we initialize it + * via and MSR write of 64 bits so define all as ULL. * */ -#define AMD_NB_EN_CORRECC 0x00000001 -#define AMD_NB_EN_UNCORRECC 0x00000002 -#define AMD_NB_EN_CRCERR0 0x00000004 -#define AMD_NB_EN_CRCERR1 0x00000008 -#define AMD_NB_EN_CRCERR2 0x00000010 -#define AMD_NB_EN_SYNCPKT0 0x00000020 -#define AMD_NB_EN_SYNCPKT1 0x00000040 -#define AMD_NB_EN_SYNCPKT2 0x00000080 -#define AMD_NB_EN_MSTRABRT 0x00000100 -#define AMD_NB_EN_TGTABRT 0x00000200 -#define AMD_NB_EN_GARTTBLWK 0x00000400 -#define AMD_NB_EN_ATOMICRMW 0x00000800 -#define AMD_NB_EN_WCHDOGTMR 0x00001000 - -#define AMD_NB_CTL_INIT /* All but GARTTBLWK */ \ +#define AMD_NB_EN_CORRECC 0x00000001ULL +#define AMD_NB_EN_UNCORRECC 0x00000002ULL +#define AMD_NB_EN_CRCERR0 0x00000004ULL +#define AMD_NB_EN_CRCERR1 0x00000008ULL +#define AMD_NB_EN_CRCERR2 0x00000010ULL +#define AMD_NB_EN_SYNCPKT0 0x00000020ULL +#define AMD_NB_EN_SYNCPKT1 0x00000040ULL +#define AMD_NB_EN_SYNCPKT2 0x00000080ULL +#define AMD_NB_EN_MSTRABRT 0x00000100ULL +#define AMD_NB_EN_TGTABRT 0x00000200ULL +#define AMD_NB_EN_GARTTBLWK 0x00000400ULL +#define AMD_NB_EN_ATOMICRMW 0x00000800ULL +#define AMD_NB_EN_WCHDOGTMR 0x00001000ULL +#define AMD_NB_EN_DRAMPAR 0x00040000ULL /* revs F and G */ + +#define AMD_NB_CTL_INIT_CMN /* Revs B to G; All but GARTTBLWK */ \ (AMD_NB_EN_CORRECC | AMD_NB_EN_UNCORRECC | \ AMD_NB_EN_CRCERR0 | AMD_NB_EN_CRCERR1 | AMD_NB_EN_CRCERR2 | \ AMD_NB_EN_SYNCPKT0 | AMD_NB_EN_SYNCPKT1 | AMD_NB_EN_SYNCPKT2 | \ AMD_NB_EN_MSTRABRT | AMD_NB_EN_TGTABRT | \ AMD_NB_EN_ATOMICRMW | AMD_NB_EN_WCHDOGTMR) -#define AMD_NB_CFG_CPUECCERREN 0x00000001 -#define AMD_NB_CFG_CPURDDATERREN 0x00000002 -#define AMD_NB_CFG_SYNCONUCECCEN 0x00000004 -#define AMD_NB_CFG_SYNCPKTGENDIS 0x00000008 -#define AMD_NB_CFG_SYNCPKTPROPDIS 0x00000010 -#define AMD_NB_CFG_IOMSTABORTDIS 0x00000020 -#define AMD_NB_CFG_CPUERRDIS 0x00000040 -#define AMD_NB_CFG_IOERRDIS 0x00000080 -#define AMD_NB_CFG_WDOGTMRDIS 0x00000100 -#define AMD_NB_CFG_SYNCONWDOGEN 0x00100000 -#define AMD_NB_CFG_SYNCONANYERREN 0x00200000 -#define AMD_NB_CFG_ECCEN 0x00400000 -#define AMD_NB_CFG_CHIPKILLECCEN 0x00800000 -#define AMD_NB_CFG_IORDDATERREN 0x01000000 -#define AMD_NB_CFG_DISPCICFGCPUERRRSP 0x02000000 -#define AMD_NB_CFG_NBMCATOMSTCPUEN 0x08000000 +#define AMD_NB_CTL_INIT_REV_FG /* Additional bits for revs F and G */ \ + AMD_NB_EN_DRAMPAR + +/* + * NB MCA Configuration register + */ +#define AMD_NB_CFG_CPUECCERREN 0x00000001 +#define AMD_NB_CFG_CPURDDATERREN 0x00000002 +#define AMD_NB_CFG_SYNCONUCECCEN 0x00000004 +#define AMD_NB_CFG_SYNCPKTGENDIS 0x00000008 +#define AMD_NB_CFG_SYNCPKTPROPDIS 0x00000010 +#define AMD_NB_CFG_IOMSTABORTDIS 0x00000020 +#define AMD_NB_CFG_CPUERRDIS 0x00000040 +#define AMD_NB_CFG_IOERRDIS 0x00000080 +#define AMD_NB_CFG_WDOGTMRDIS 0x00000100 +#define AMD_NB_CFG_SYNCONWDOGEN 0x00100000 +#define AMD_NB_CFG_SYNCONANYERREN 0x00200000 +#define AMD_NB_CFG_ECCEN 0x00400000 +#define AMD_NB_CFG_CHIPKILLECCEN 0x00800000 +#define AMD_NB_CFG_IORDDATERREN 0x01000000 +#define AMD_NB_CFG_DISPCICFGCPUERRRSP 0x02000000 +#define AMD_NB_CFG_NBMCATOMSTCPUEN 0x08000000 +#define AMD_NB_CFG_DISTGTABTCPUERRRSP 0x10000000 +#define AMD_NB_CFG_DISMSTABTCPUERRRSP 0x20000000 +#define AMD_NB_CFG_SYNCONDRAMADRPARERREN 0x40000000 /* Revs F & G */ + +/* + * We do not initialize the NB config with an absolute value; instead we + * selectively add some bits and remove others. Note that + * AMD_NB_CFG_{ADD,REMOVE}_{CMN,REV_FG} below are not the whole + * story here - additional config is performed regarding the watchdog (see + * ao_mca.c for details). + */ +#define AMD_NB_CFG_ADD_CMN /* Revs B to G */ \ + (AMD_NB_CFG_DISPCICFGCPUERRRSP | AMD_NB_CFG_SYNCONUCECCEN | \ + AMD_NB_CFG_CPUECCERREN) + +#define AMD_NB_CFG_REMOVE_CMN /* Revs B to G */ \ + (AMD_NB_CFG_NBMCATOMSTCPUEN | \ + AMD_NB_CFG_IORDDATERREN | AMD_NB_CFG_SYNCONANYERREN | \ + AMD_NB_CFG_SYNCONWDOGEN | AMD_NB_CFG_IOERRDIS | \ + AMD_NB_CFG_IOMSTABORTDIS | AMD_NB_CFG_SYNCPKTPROPDIS | \ + AMD_NB_CFG_SYNCPKTGENDIS) + +#define AMD_NB_CFG_ADD_REV_FG /* Revs F and G */ \ + AMD_NB_CFG_SYNCONDRAMADRPARERREN + +#define AMD_NB_CFG_REMOVE_REV_FG 0x0 /* Revs F and G */ #define AMD_NB_CFG_WDOGTMRCNTSEL_4095 0x00000000 #define AMD_NB_CFG_WDOGTMRCNTSEL_2047 0x00000200 @@ -283,10 +334,14 @@ extern "C" { #define AMD_NB_REG_SCRUBADDR_LO 0x5c #define AMD_NB_REG_SCRUBADDR_HI 0x60 -#define AMD_NB_STAT_LDTLINK_MASK 0x0000007000000000 +#define AMD_NB_REG_SPARECTL 0xb0 + +#define AMD_NB_STAT_DRAMCHANNEL 0x0000020000000000ULL +#define AMD_NB_STAT_LDTLINK_MASK 0x0000007000000000ULL #define AMD_NB_STAT_LDTLINK_SHIFT 4 -#define AMD_NB_STAT_ERRCPU1 0x0000000200000000 -#define AMD_NB_STAT_ERRCPU0 0x0000000100000000 +#define AMD_NB_STAT_ERRCPU1 0x0000000200000000ULL +#define AMD_NB_STAT_ERRCPU0 0x0000000100000000ULL + #define AMD_NB_STAT_CKSYND_MASK 0x00000000ff000000 /* syndrome[15:8] */ #define AMD_NB_STAT_CKSYND_SHIFT (24 - 8) /* shift [31:24] to [15:8] */ @@ -298,8 +353,8 @@ extern "C" { ((((uint64_t)(synd) << AMD_NB_STAT_CKSYND_SHIFT) & \ AMD_NB_STAT_CKSYND_MASK) | AMD_BANK_MKSYND(synd)) -#define AMD_ERRCODE_MASK 0x000000000000ffff -#define AMD_ERREXT_MASK 0x00000000000f0000 +#define AMD_ERRCODE_MASK 0x000000000000ffffULL +#define AMD_ERREXT_MASK 0x00000000000f0000ULL #define AMD_ERREXT_SHIFT 16 #define AMD_ERRCODE_TT_MASK 0x000c |