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-rw-r--r--usr/src/lib/efcode/engine/forth.c25
-rw-r--r--usr/src/uts/common/io/pcie.c15
-rw-r--r--usr/src/uts/common/sys/pcie_impl.h8
-rw-r--r--usr/src/uts/sun4/io/px/px_fdvma.c10
-rw-r--r--usr/src/uts/sun4/io/px/px_pci.c55
-rw-r--r--usr/src/uts/sun4/io/px/px_pci.h21
6 files changed, 63 insertions, 71 deletions
diff --git a/usr/src/lib/efcode/engine/forth.c b/usr/src/lib/efcode/engine/forth.c
index b0b8005342..33bd2c37d1 100644
--- a/usr/src/lib/efcode/engine/forth.c
+++ b/usr/src/lib/efcode/engine/forth.c
@@ -2,9 +2,8 @@
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License"). You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
@@ -20,8 +19,8 @@
* CDDL HEADER END
*/
/*
- * Copyright (c) 2000 by Sun Microsystems, Inc.
- * All rights reserved.
+ * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
+ * Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
@@ -444,23 +443,23 @@ less_equals(fcode_env_t *env)
void
between(fcode_env_t *env)
{
- s_lforth_t hi, lo;
+ u_lforth_t hi, lo;
CHECK_DEPTH(env, 3, "between");
- hi = (s_lforth_t)POP(DS);
- lo = (s_lforth_t)POP(DS);
- TOS = (((s_lforth_t)TOS >= lo) && ((s_lforth_t)TOS <= hi) ? -1 : 0);
+ hi = (u_lforth_t)POP(DS);
+ lo = (u_lforth_t)POP(DS);
+ TOS = (((u_lforth_t)TOS >= lo) && ((u_lforth_t)TOS <= hi) ? -1 : 0);
}
void
within(fcode_env_t *env)
{
- s_lforth_t lo, hi;
+ u_lforth_t lo, hi;
CHECK_DEPTH(env, 3, "within");
- hi = (s_lforth_t)POP(DS);
- lo = (s_lforth_t)POP(DS);
- TOS = ((((s_lforth_t)TOS >= lo) && ((s_lforth_t)TOS < hi)) ? -1 : 0);
+ hi = (u_lforth_t)POP(DS);
+ lo = (u_lforth_t)POP(DS);
+ TOS = ((((u_lforth_t)TOS >= lo) && ((u_lforth_t)TOS < hi)) ? -1 : 0);
}
void
diff --git a/usr/src/uts/common/io/pcie.c b/usr/src/uts/common/io/pcie.c
index 9b7374ba79..b5dda7dbf9 100644
--- a/usr/src/uts/common/io/pcie.c
+++ b/usr/src/uts/common/io/pcie.c
@@ -19,7 +19,7 @@
* CDDL HEADER END
*/
/*
- * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
+ * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
@@ -202,6 +202,8 @@ pcie_init_ppd(dev_info_t *cdip)
/* Save the Header Type */
ppd_p->ppd_hdr_type = pci_config_get8(eh, PCI_CONF_HEADER);
ppd_p->ppd_hdr_type &= PCI_HEADER_TYPE_M;
+ ppd_p->ppd_pcie2pci_secbus = ddi_prop_get_int(DDI_DEV_T_ANY, cdip, 0,
+ "pcie2pci-sec-bus", 0);
/* Save the Range information if device is a switch/bridge */
if (ppd_p->ppd_hdr_type == PCI_HEADER_ONE) {
@@ -237,16 +239,11 @@ pcie_init_ppd(dev_info_t *cdip)
ppd_p->ppd_pcie_off, PCIE_PCIECAP) &
PCIE_PCIECAP_DEV_TYPE_MASK;
- ppd_p->ppd_pcie_phfun = (pci_config_get8(eh,
- ppd_p->ppd_pcie_off + PCIE_DEVCAP) &
- PCIE_DEVCAP_PHTM_FUNC_MASK) >> 3;
-
if (PCI_CAP_LOCATE(eh, PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_AER),
&ppd_p->ppd_aer_off) != DDI_SUCCESS)
ppd_p->ppd_aer_off = NULL;
} else {
ppd_p->ppd_pcie_off = NULL;
- ppd_p->ppd_pcie_phfun = NULL;
ppd_p->ppd_dev_type = PCIE_PCIECAP_DEV_TYPE_PCI_DEV;
}
@@ -626,9 +623,11 @@ pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip)
/*
* For a given rdip, return the bdf value of dip's (px or px_pci)
* immediate child or secondary bus-id if dip is a PCIe2PCI bridge.
+ *
+ * XXX - For now, return bdf value of zero for all PCI and PCI-X devices
+ * since this needs more work.
*/
- return (PCI_GET_SEC_BUS(cdip) ?
- PCI_GET_SEC_BUS(cdip) : PCI_GET_BDF(cdip));
+ return (PCI_GET_PCIE2PCI_SECBUS(cdip) ? 0 : PCI_GET_BDF(cdip));
}
/*
diff --git a/usr/src/uts/common/sys/pcie_impl.h b/usr/src/uts/common/sys/pcie_impl.h
index 2ff32e9244..db833a5102 100644
--- a/usr/src/uts/common/sys/pcie_impl.h
+++ b/usr/src/uts/common/sys/pcie_impl.h
@@ -109,10 +109,10 @@ typedef struct pcie_ppd {
uint8_t ppd_hdr_type; /* pci header type, see pci.h */
uint8_t ppd_dev_type; /* PCI-E dev type, see pcie.h */
uint8_t ppd_bdg_secbus; /* Bridge secondary bus num */
+ pcie_req_id_t ppd_pcie2pci_secbus; /* PCIe2PCI Bridge secbus num */
uint16_t ppd_pcie_off; /* PCIe Capability Offset */
uint16_t ppd_aer_off; /* PCIe Advanced Error Offset */
uint16_t ppd_pcix_off; /* PCIx Capability Offset */
- uint8_t ppd_pcie_phfun; /* Phantom funs for pcix/pcie */
pci_bus_range_t ppd_bus_range; /* pci bus-range property */
ppb_ranges_t *ppd_addr_ranges; /* pci range property */
int ppd_addr_entries; /* number of range prop */
@@ -122,10 +122,10 @@ typedef struct pcie_ppd {
#define PCI_GET_BDF(dip) \
((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_bdf
-#define PCI_GET_SEC_BUS(dip) \
+#define PCI_GET_BDG_SECBUS(dip) \
((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_bdg_secbus
-#define PCI_GET_PHFUN(dip) \
- ((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_pcie_phfun
+#define PCI_GET_PCIE2PCI_SECBUS(dip) \
+ ((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_pcie2pci_secbus
/*
* The following flag is used for Broadcom 5714/5715 bridge prefetch issue.
diff --git a/usr/src/uts/sun4/io/px/px_fdvma.c b/usr/src/uts/sun4/io/px/px_fdvma.c
index 2e2b2e60a6..f2b999d402 100644
--- a/usr/src/uts/sun4/io/px/px_fdvma.c
+++ b/usr/src/uts/sun4/io/px/px_fdvma.c
@@ -19,7 +19,7 @@
* CDDL HEADER END
*/
/*
- * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
+ * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
@@ -204,6 +204,14 @@ px_fdvma_reserve(dev_info_t *dip, dev_info_t *rdip, px_t *px_p,
mp->dmai_size = npages * MMU_PAGE_SIZE;
mp->dmai_nwin = 0;
mp->dmai_fdvma = (caddr_t)fdvma_p;
+
+ /*
+ * For a given rdip, set mp->dmai_bdf with the bdf value of px's
+ * immediate child. As we move down the PCIe fabric, this field
+ * may be modified by switch and bridge drivers.
+ */
+ mp->dmai_bdf = pcie_get_bdf_for_dma_xfer(dip, rdip);
+
DBG(DBG_DMA_CTL, dip,
"DDI_DMA_RESERVE: mp=%p dvma=%x npages=%x private=%p\n",
mp, mp->dmai_mapping, npages, fdvma_p);
diff --git a/usr/src/uts/sun4/io/px/px_pci.c b/usr/src/uts/sun4/io/px/px_pci.c
index 8df0505d15..2d1a88d9df 100644
--- a/usr/src/uts/sun4/io/px/px_pci.c
+++ b/usr/src/uts/sun4/io/px/px_pci.c
@@ -93,11 +93,9 @@ static int pxb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *,
static int pxb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg,
ddi_dma_handle_t *handlep);
-#ifdef BCM_SW_WORKAROUNDS
static int pxb_dma_mctl(dev_info_t *dip, dev_info_t *rdip,
ddi_dma_handle_t handle, enum ddi_dma_ctlops cmd, off_t *offp,
size_t *lenp, caddr_t *objp, uint_t cache_flags);
-#endif /* BCM_SW_WORKAROUNDS */
static int pxb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t,
void *, void *);
static int pxb_intr_ops(dev_info_t *dip, dev_info_t *rdip,
@@ -134,11 +132,7 @@ static struct bus_ops pxb_bus_ops = {
ddi_dma_unbindhdl,
ddi_dma_flush,
ddi_dma_win,
-#ifdef BCM_SW_WORKAROUNDS
pxb_dma_mctl,
-#else
- ddi_dma_mctl,
-#endif /* BCM_SW_WORKAROUNDS */
pxb_ctlops,
ddi_bus_prop_op,
ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */
@@ -402,14 +396,14 @@ pxb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
if ((PCI_CAP_LOCATE(pxb->pxb_config_handle, PCI_CAP_ID_PCI_E,
&cap_ptr)) != DDI_FAILURE)
pxb->pxb_port_type = PCI_CAP_GET16(config_handle, NULL, cap_ptr,
- PX_CAP_REG) & PX_CAP_REG_DEV_TYPE_MASK;
+ PCIE_PCIECAP) & PCIE_PCIECAP_DEV_TYPE_MASK;
else
- pxb->pxb_port_type = PX_CAP_REG_DEV_TYPE_PCIE_DEV;
+ pxb->pxb_port_type = PCIE_PCIECAP_DEV_TYPE_PCIE_DEV;
- if ((pxb->pxb_port_type != PX_CAP_REG_DEV_TYPE_UP) &&
- (pxb->pxb_port_type != PX_CAP_REG_DEV_TYPE_DOWN) &&
- (pxb->pxb_port_type != PX_CAP_REG_DEV_TYPE_PCIE2PCI) &&
- (pxb->pxb_port_type != PX_CAP_REG_DEV_TYPE_PCI2PCIE)) {
+ if ((pxb->pxb_port_type != PCIE_PCIECAP_DEV_TYPE_UP) &&
+ (pxb->pxb_port_type != PCIE_PCIECAP_DEV_TYPE_DOWN) &&
+ (pxb->pxb_port_type != PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) &&
+ (pxb->pxb_port_type != PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) {
DBG(DBG_ATTACH, devi, "This is not a switch or bridge\n");
goto fail;
}
@@ -440,7 +434,7 @@ pxb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
* PCI and PCI-X device driver's parent private data structure
* as part of their init child function.
*/
- if (pxb->pxb_port_type == PX_CAP_REG_DEV_TYPE_PCIE2PCI) {
+ if (pxb->pxb_port_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) {
if (ndi_prop_update_int(DDI_DEV_T_NONE, pxb->pxb_dip,
"pcie2pci-sec-bus", pci_config_get8(config_handle,
PCI_BCNF_SECBUS)) != DDI_PROP_SUCCESS) {
@@ -488,9 +482,9 @@ pxb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
goto hotplug_done;
#endif /* PX_PLX */
- if ((pxb->pxb_port_type == PX_CAP_REG_DEV_TYPE_DOWN) ||
- (pxb->pxb_port_type == PX_CAP_REG_DEV_TYPE_PCIE2PCI) ||
- (pxb->pxb_port_type == PX_CAP_REG_DEV_TYPE_PCI2PCIE)) {
+ if ((pxb->pxb_port_type == PCIE_PCIECAP_DEV_TYPE_DOWN) ||
+ (pxb->pxb_port_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ||
+ (pxb->pxb_port_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) {
#ifdef PX_PLX
/*
* Workaround for a race condition between hotplug
@@ -1027,7 +1021,7 @@ pxb_initchild(dev_info_t *child)
for (i = 0; i < pxb_tlp_count; i += 1)
reg |= pci_config_get16(config_handle, PCI_CONF_VENID);
- if (pxb->pxb_port_type == PX_CAP_REG_DEV_TYPE_PCIE2PCI)
+ if (pxb->pxb_port_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI)
pxb_set_pci_perf_parameters(child, config_handle);
pci_config_teardown(&config_handle);
@@ -1313,14 +1307,14 @@ pxb_init_hotplug(pxb_devstate_t *pxb)
pxb->pxb_hpc_type = HPC_NONE;
- if (((pxb->pxb_port_type == PX_CAP_REG_DEV_TYPE_DOWN) ||
- (pxb->pxb_port_type == PX_CAP_REG_DEV_TYPE_PCI2PCIE)) &&
+ if (((pxb->pxb_port_type == PCIE_PCIECAP_DEV_TYPE_DOWN) ||
+ (pxb->pxb_port_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) &&
(pxb_pciehpc_probe(pxb->pxb_dip,
pxb->pxb_config_handle) == DDI_SUCCESS)) {
rv = pciehpc_init(pxb->pxb_dip, NULL);
if (rv == DDI_SUCCESS)
pxb->pxb_hpc_type = HPC_PCIE;
- } else if ((pxb->pxb_port_type == PX_CAP_REG_DEV_TYPE_PCIE2PCI) &&
+ } else if ((pxb->pxb_port_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) &&
(pxb_pcishpc_probe(pxb->pxb_dip,
pxb->pxb_config_handle) == DDI_SUCCESS)) {
rv = pcishpc_init(pxb->pxb_dip);
@@ -2064,7 +2058,6 @@ pxb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
return (ret);
}
-#ifdef BCM_SW_WORKAROUNDS
/*
* FDVMA feature is not supported for any child device of Broadcom 5714/5715
* PCIe-PCI bridge due to prefetch bug. Return failure immediately, so that
@@ -2076,13 +2069,27 @@ pxb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
uint_t cache_flags)
{
+ int ret;
+
+#ifdef BCM_SW_WORKAROUNDS
if (cmd == DDI_DMA_RESERVE)
return (DDI_FAILURE);
+#endif /* BCM_SW_WORKAROUNDS */
+
+ if (((ret = ddi_dma_mctl(dip, rdip, handle, cmd, offp, lenp, objp,
+ cache_flags)) == DDI_SUCCESS) && (cmd == DDI_DMA_RESERVE)) {
+ ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*objp;
- return (ddi_dma_mctl(dip, rdip, handle, cmd, offp, lenp, objp,
- cache_flags));
+ /*
+ * For a given rdip, update mp->dmai_bdf with the bdf value
+ * of px_pci's immediate child or secondary bus-id of the
+ * PCIe2PCI bridge.
+ */
+ mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip);
+ }
+
+ return (ret);
}
-#endif /* BCM_SW_WORKAROUNDS */
#ifdef DEBUG
static void
diff --git a/usr/src/uts/sun4/io/px/px_pci.h b/usr/src/uts/sun4/io/px/px_pci.h
index 5fbb55c080..ab460a13b4 100644
--- a/usr/src/uts/sun4/io/px/px_pci.h
+++ b/usr/src/uts/sun4/io/px/px_pci.h
@@ -39,29 +39,8 @@ extern "C" {
#define PXB_BRIDGE_CONF 0x40
/*
- * Generic - PCI Express Capability List Structure
- * XXX - Should be moved to a more PCI generic location
- */
-#define PX_CAP_REG 0x2
-
-/*
- * Generic - PCI Express Capabilities Register
- * XXX - Should be moved to a more PCI generic location
- */
-#define PX_CAP_REG_DEV_TYPE_PCIE_DEV 0x0000 /* PCI-E Endpont Device */
-#define PX_CAP_REG_DEV_TYPE_PCI_DEV 0x0010 /* Leg PCI Endpont Device */
-#define PX_CAP_REG_DEV_TYPE_ROOT 0x0040 /* Root Port of Root Complex */
-#define PX_CAP_REG_DEV_TYPE_UP 0x0050 /* Upstream Port of Switch */
-#define PX_CAP_REG_DEV_TYPE_DOWN 0x0060 /* Downstream Port of Switch */
-#define PX_CAP_REG_DEV_TYPE_PCIE2PCI 0x0070 /* PCI-E to PCI Bridge */
-#define PX_CAP_REG_DEV_TYPE_PCI2PCIE 0x0080 /* PCI to PCI-E Bridge */
-#define PX_CAP_REG_DEV_TYPE_MASK 0x00F0 /* Device/Port Type Mask */
-
-/*
* PCI/PCI-E Configuration register specific values.
*/
-
-
#define PX_PMODE 0x4000 /* PCI/PCIX Mode */
#define PX_PFREQ_66 0x200 /* PCI clock frequency */
#define PX_PFREQ_100 0x400
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-29 06:02:33 +0000