diff options
Diffstat (limited to 'usr/src')
| -rw-r--r-- | usr/src/data/perfmon/BDW/broadwell_core_v26.json (renamed from usr/src/data/perfmon/BDW/broadwell_core_v23.json) | 1948 | ||||
| -rw-r--r-- | usr/src/data/perfmon/BDW/broadwell_fp_arith_inst_v26.json (renamed from usr/src/data/perfmon/BDW/broadwell_fp_arith_inst_v23.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/BDW/broadwell_matrix_bit_definitions_v23.json | 326 | ||||
| -rw-r--r-- | usr/src/data/perfmon/BDW/broadwell_matrix_v26.json (renamed from usr/src/data/perfmon/BDW/broadwell_matrix_v23.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/BDW/broadwell_uncore_v26.json (renamed from usr/src/data/perfmon/BDW/broadwell_uncore_v23.json) | 14 | ||||
| -rw-r--r-- | usr/src/data/perfmon/BDX/broadwellx_core_v17.json (renamed from usr/src/data/perfmon/BDX/broadwellx_core_v14.json) | 135 | ||||
| -rw-r--r-- | usr/src/data/perfmon/BDX/broadwellx_matrix_bit_definitions_v14.json | 497 | ||||
| -rw-r--r-- | usr/src/data/perfmon/BDX/broadwellx_matrix_v17.json (renamed from usr/src/data/perfmon/BDX/broadwellx_matrix_v14.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/BDX/broadwellx_uncore_v17.json (renamed from usr/src/data/perfmon/BDX/broadwellx_uncore_v14.json) | 4 | ||||
| -rw-r--r-- | usr/src/data/perfmon/CLX/cascadelakex_core_v1.11.json (renamed from usr/src/data/perfmon/CLX/cascadelakex_core_v1.00.json) | 4632 | ||||
| -rw-r--r-- | usr/src/data/perfmon/CLX/cascadelakex_fp_arith_inst_v1.11.json (renamed from usr/src/data/perfmon/CLX/cascadelakex_fp_arith_inst_v1.00.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.11.json (renamed from usr/src/data/perfmon/SKX/skylakex_uncore_v1.12.json) | 568 | ||||
| -rw-r--r-- | usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.11_experimental.json (renamed from usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.00_experimental.json) | 1224 | ||||
| -rw-r--r-- | usr/src/data/perfmon/HSW/haswell_core_v30.json (renamed from usr/src/data/perfmon/HSW/haswell_core_v28.json) | 324 | ||||
| -rw-r--r-- | usr/src/data/perfmon/HSW/haswell_fp_arith_inst_v28.json | 1 | ||||
| -rw-r--r-- | usr/src/data/perfmon/HSW/haswell_matrix_bit_definitions_v28.json | 389 | ||||
| -rw-r--r-- | usr/src/data/perfmon/HSW/haswell_matrix_v30.json (renamed from usr/src/data/perfmon/HSW/haswell_matrix_v28.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/HSW/haswell_uncore_v30.json (renamed from usr/src/data/perfmon/HSW/haswell_uncore_v28.json) | 12 | ||||
| -rw-r--r-- | usr/src/data/perfmon/HSX/haswellx_core_v22.json (renamed from usr/src/data/perfmon/HSX/haswellx_core_v20.json) | 94 | ||||
| -rw-r--r-- | usr/src/data/perfmon/HSX/haswellx_matrix_bit_definitions_v20.json | 497 | ||||
| -rw-r--r-- | usr/src/data/perfmon/HSX/haswellx_matrix_v22.json (renamed from usr/src/data/perfmon/HSX/haswellx_matrix_v20.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/HSX/haswellx_uncore_v22.json (renamed from usr/src/data/perfmon/HSX/haswellx_uncore_v20.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/ICL/icelake_core_v1.09.json | 7385 | ||||
| -rw-r--r-- | usr/src/data/perfmon/ICL/icelake_uncore_v1.09.json | 38 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKL/skylake_core_v50.json (renamed from usr/src/data/perfmon/SKL/skylake_core_v42.json) | 1166 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKL/skylake_fp_arith_inst_v50.json (renamed from usr/src/data/perfmon/SKL/skylake_fp_arith_inst_v42.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKL/skylake_matrix_bit_definitions_v42.json | 200 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKL/skylake_matrix_v50.json (renamed from usr/src/data/perfmon/SKL/skylake_matrix_v42.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKL/skylake_uncore_v50.json (renamed from usr/src/data/perfmon/SKL/skylake_uncore_v42.json) | 16 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKX/skylakex_core_v1.24.json (renamed from usr/src/data/perfmon/SKX/skylakex_core_v1.12.json) | 1290 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKX/skylakex_fp_arith_inst_v1.24.json (renamed from usr/src/data/perfmon/SKX/skylakex_fp_arith_inst_v1.12.json) | 0 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKX/skylakex_matrix_bit_definitions_v1.12.json | 362 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKX/skylakex_matrix_v1.24.json (renamed from usr/src/data/perfmon/SKX/skylakex_matrix_v1.12.json) | 7 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKX/skylakex_uncore_v1.24.json (renamed from usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.00.json) | 542 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SKX/skylakex_uncore_v1.24_experimental.json (renamed from usr/src/data/perfmon/SKX/skylakex_uncore_v1.12_experimental.json) | 1270 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SNR/snowridgex_core_v1.10.json | 794 | ||||
| -rw-r--r-- | usr/src/data/perfmon/SNR/snowridgex_uncore_v1.10.json | 743 | ||||
| -rw-r--r-- | usr/src/data/perfmon/TGL/tigerlake_core_v1.00.json | 5172 | ||||
| -rw-r--r-- | usr/src/data/perfmon/THIRDPARTYLICENSE | 49 | ||||
| -rw-r--r-- | usr/src/data/perfmon/mapfile.csv | 110 | ||||
| -rw-r--r-- | usr/src/data/perfmon/readme.txt | 26 | ||||
| -rw-r--r-- | usr/src/man/man3cpc/cpc.3cpc | 13 | ||||
| -rw-r--r-- | usr/src/pkg/manifests/diagnostic-cpu-counters.mf | 16 | ||||
| -rw-r--r-- | usr/src/tools/cpcgen/cpcgen.c | 19 | ||||
| -rw-r--r-- | usr/src/uts/intel/core_pcbe/Makefile | 12 |
45 files changed, 20906 insertions, 8989 deletions
diff --git a/usr/src/data/perfmon/BDW/broadwell_core_v23.json b/usr/src/data/perfmon/BDW/broadwell_core_v26.json index 10c72afc03..6a64e7dd7a 100644 --- a/usr/src/data/perfmon/BDW/broadwell_core_v23.json +++ b/usr/src/data/perfmon/BDW/broadwell_core_v26.json @@ -1063,7 +1063,7 @@ "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1085,7 +1085,7 @@ "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1107,7 +1107,7 @@ "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1129,7 +1129,7 @@ "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1151,7 +1151,7 @@ "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1173,7 +1173,7 @@ "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -3370,7 +3370,7 @@ "UMask": "0x01", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", + "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -4448,7 +4448,7 @@ "UMask": "0x01", "EventName": "LSD.UOPS", "BriefDescription": "Number of Uops delivered by the LSD.", - "PublicDescription": "Number of Uops delivered by the LSD. ", + "PublicDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -4514,7 +4514,7 @@ "UMask": "0x02", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", - "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cycles.", + "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -4642,6 +4642,28 @@ "Offcore": "0" }, { + "EventCode": "0xb0", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "BriefDescription": "Any memory transaction that reached the SQ.", + "PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { "EventCode": "0xB1", "UMask": "0x01", "EventName": "UOPS_EXECUTED.THREAD", @@ -5196,7 +5218,7 @@ "UMask": "0x02", "EventName": "INST_RETIRED.X87", "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5207,7 +5229,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5217,8 +5239,8 @@ "EventCode": "0xC1", "UMask": "0x08", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable (Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -5229,7 +5251,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "BDM30", @@ -5239,8 +5261,8 @@ "EventCode": "0xC1", "UMask": "0x10", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "BriefDescription": "Number of transitions from legacy SSE to AVX-256 when penalty applicable (Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -5251,7 +5273,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "BDM30", @@ -5261,8 +5283,8 @@ "EventCode": "0xC1", "UMask": "0x40", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "BriefDescription": "tbd", - "PublicDescription": null, + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "PublicDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -5273,7 +5295,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5283,8 +5305,8 @@ "EventCode": "0xC2", "UMask": "0x01", "EventName": "UOPS_RETIRED.ALL", - "BriefDescription": "Actually retired uops. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "BriefDescription": "Actually retired uops.", + "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5296,7 +5318,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "1", - "Data_LA": "1", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" @@ -5305,8 +5327,8 @@ "EventCode": "0xC2", "UMask": "0x01", "EventName": "UOPS_RETIRED.STALL_CYCLES", - "BriefDescription": "Cycles no executable uops retired (Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts cycles without actually retired uops.", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "This event counts cycles without actually retired uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5317,7 +5339,7 @@ "Invert": "1", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5327,8 +5349,8 @@ "EventCode": "0xC2", "UMask": "0x01", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "BriefDescription": "Number of cycles using always true condition applied to PEBS uops retired event.", - "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to PEBS uops retired event. ", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5339,7 +5361,7 @@ "Invert": "1", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5349,8 +5371,8 @@ "EventCode": "0xC2", "UMask": "0x02", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "BriefDescription": "Retirement slots used. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.", + "BriefDescription": "Retirement slots used.", + "PublicDescription": "This event counts the number of retirement slots used.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5503,8 +5525,8 @@ "EventCode": "0xC4", "UMask": "0x01", "EventName": "BR_INST_RETIRED.CONDITIONAL", - "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.", + "BriefDescription": "Conditional branch instructions retired.", + "PublicDescription": "This event counts conditional branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -5525,8 +5547,8 @@ "EventCode": "0xC4", "UMask": "0x02", "EventName": "BR_INST_RETIRED.NEAR_CALL", - "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "This event counts both direct and indirect near call instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -5547,8 +5569,8 @@ "EventCode": "0xC4", "UMask": "0x02", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).", + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", + "PublicDescription": "This event counts both direct and indirect macro near call instructions retired (captured in ring 3).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -5591,8 +5613,8 @@ "EventCode": "0xC4", "UMask": "0x08", "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "BriefDescription": "Return instructions retired. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.", + "BriefDescription": "Return instructions retired.", + "PublicDescription": "This event counts return instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -5613,8 +5635,8 @@ "EventCode": "0xC4", "UMask": "0x10", "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "BriefDescription": "Counts all not taken macro branch instructions retired. (Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired.", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "This event counts not taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -5625,7 +5647,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5635,8 +5657,8 @@ "EventCode": "0xC4", "UMask": "0x20", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.", + "BriefDescription": "Taken branch instructions retired.", + "PublicDescription": "This event counts taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -5657,8 +5679,8 @@ "EventCode": "0xC4", "UMask": "0x40", "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "BriefDescription": "Counts the number of far branch instructions retired.(Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired.", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "This event counts far branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -5669,7 +5691,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "BDW98", @@ -5701,8 +5723,8 @@ "EventCode": "0xC5", "UMask": "0x01", "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -5745,8 +5767,8 @@ "EventCode": "0xC5", "UMask": "0x08", "EventName": "BR_MISP_RETIRED.RET", - "BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "PublicDescription": "This event counts mispredicted return instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -5767,8 +5789,8 @@ "EventCode": "0xC5", "UMask": "0x20", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).", - "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -5786,11 +5808,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x01", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5808,11 +5830,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x02", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5830,11 +5852,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x03", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", - "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)", - "PublicDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5852,11 +5874,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x04", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5874,11 +5896,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x08", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5896,11 +5918,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x10", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5918,11 +5940,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x15", "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", - "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000006", @@ -5943,8 +5965,8 @@ "EventCode": "0xc7", "UMask": "0x20", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5962,11 +5984,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", - "UMask": "0x2A", + "EventCode": "0xc7", + "UMask": "0x2a", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", - "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000005", @@ -5984,11 +6006,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", - "UMask": "0x3C", + "EventCode": "0xc7", + "UMask": "0x3c", "EventName": "FP_ARITH_INST_RETIRED.PACKED", - "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)", - "PublicDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)", + "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000004", @@ -6053,8 +6075,8 @@ "EventCode": "0xc8", "UMask": "0x04", "EventName": "HLE_RETIRED.ABORTED", - "BriefDescription": "Number of times HLE abort was triggered (PEBS)", - "PublicDescription": "Number of times HLE abort was triggered (PEBS).", + "BriefDescription": "Number of times HLE abort was triggered", + "PublicDescription": "Number of times HLE abort was triggered.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -6229,8 +6251,8 @@ "EventCode": "0xc9", "UMask": "0x04", "EventName": "RTM_RETIRED.ABORTED", - "BriefDescription": "Number of times RTM abort was triggered (PEBS)", - "PublicDescription": "Number of times RTM abort was triggered (PEBS).", + "BriefDescription": "Number of times RTM abort was triggered", + "PublicDescription": "Number of times RTM abort was triggered .", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6361,8 +6383,8 @@ "EventCode": "0xCA", "UMask": "0x02", "EventName": "FP_ASSIST.X87_OUTPUT", - "BriefDescription": "output - Numeric Overflow, Numeric Underflow, Inexact Result (Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", + "BriefDescription": "Number of X87 assists due to output value.", + "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -6373,7 +6395,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6383,8 +6405,8 @@ "EventCode": "0xCA", "UMask": "0x04", "EventName": "FP_ASSIST.X87_INPUT", - "BriefDescription": "input - Invalid Operation, Denormal Operand, SNaN Operand (Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", + "BriefDescription": "Number of X87 assists due to input value.", + "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -6395,7 +6417,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6405,8 +6427,8 @@ "EventCode": "0xCA", "UMask": "0x08", "EventName": "FP_ASSIST.SIMD_OUTPUT", - "BriefDescription": "SSE* FP micro-code assist when output value is invalid. (Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -6417,7 +6439,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6427,8 +6449,8 @@ "EventCode": "0xCA", "UMask": "0x10", "EventName": "FP_ASSIST.SIMD_INPUT", - "BriefDescription": "Any input SSE* FP Assist - (Precise Event)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts any input SSE* floating-point (FP) assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", + "BriefDescription": "Number of SIMD FP assists due to input values", + "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -6439,7 +6461,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6449,8 +6471,8 @@ "EventCode": "0xCA", "UMask": "0x1E", "EventName": "FP_ASSIST.ANY", - "BriefDescription": "Counts any FP_ASSIST umask was incrementing (Precise Event)", - "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. Uses PEBS.", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6461,7 +6483,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6490,7 +6512,7 @@ "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "BriefDescription": "Randomly selected loads with latency value being above 4", @@ -6506,13 +6528,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "BriefDescription": "Randomly selected loads with latency value being above 8", @@ -6528,13 +6550,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "BriefDescription": "Randomly selected loads with latency value being above 16", @@ -6550,13 +6572,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "BriefDescription": "Randomly selected loads with latency value being above 32", @@ -6572,13 +6594,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "BriefDescription": "Randomly selected loads with latency value being above 64", @@ -6594,13 +6616,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "BriefDescription": "Randomly selected loads with latency value being above 128", @@ -6616,13 +6638,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "BriefDescription": "Randomly selected loads with latency value being above 256", @@ -6638,13 +6660,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "BriefDescription": "Randomly selected loads with latency value being above 512", @@ -6660,7 +6682,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "Offcore": "0" @@ -6669,8 +6691,8 @@ "EventCode": "0xD0", "UMask": "0x11", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "BriefDescription": "Retired load uops that miss the STLB.", + "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6691,8 +6713,8 @@ "EventCode": "0xD0", "UMask": "0x12", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "BriefDescription": "Retired store uops that miss the STLB.", + "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6713,8 +6735,8 @@ "EventCode": "0xD0", "UMask": "0x21", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.", + "BriefDescription": "Retired load uops with locked access.", + "PublicDescription": "This event counts load uops with locked access retired to the architected path.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -6735,8 +6757,8 @@ "EventCode": "0xD0", "UMask": "0x41", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6757,8 +6779,8 @@ "EventCode": "0xD0", "UMask": "0x42", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6779,8 +6801,8 @@ "EventCode": "0xD0", "UMask": "0x81", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "BriefDescription": "All retired load uops. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "BriefDescription": "All retired load uops.", + "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6801,8 +6823,8 @@ "EventCode": "0xD0", "UMask": "0x82", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "BriefDescription": "All retired store uops.", + "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6823,8 +6845,8 @@ "EventCode": "0xD1", "UMask": "0x01", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "PublicDescription": "This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6845,8 +6867,8 @@ "EventCode": "0xD1", "UMask": "0x02", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "PublicDescription": "This event counts retired load uops which data sources were hits in the mid-level (L2) cache.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6867,8 +6889,8 @@ "EventCode": "0xD1", "UMask": "0x04", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "PublicDescription": "This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "50021", @@ -6889,8 +6911,8 @@ "EventCode": "0xD1", "UMask": "0x08", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "PublicDescription": "This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6911,8 +6933,8 @@ "EventCode": "0xD1", "UMask": "0x10", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "PublicDescription": "This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "50021", @@ -6933,8 +6955,8 @@ "EventCode": "0xD1", "UMask": "0x20", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).", - "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -6955,8 +6977,8 @@ "EventCode": "0xD1", "UMask": "0x40", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "PublicDescription": "This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6977,8 +6999,8 @@ "EventCode": "0xD2", "UMask": "0x01", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "PublicDescription": "This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "20011", @@ -6999,8 +7021,8 @@ "EventCode": "0xD2", "UMask": "0x02", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "PublicDescription": "This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "20011", @@ -7021,8 +7043,8 @@ "EventCode": "0xD2", "UMask": "0x04", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "PublicDescription": "This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "20011", @@ -7043,8 +7065,8 @@ "EventCode": "0xD2", "UMask": "0x08", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "PublicDescription": "This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -7065,8 +7087,8 @@ "EventCode": "0xD3", "UMask": "0x01", "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "BriefDescription": null, - "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -7422,7 +7444,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010001", "TakenAlone": "0", "CounterMask": "0", @@ -7432,7 +7454,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7444,7 +7466,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020001", "TakenAlone": "0", "CounterMask": "0", @@ -7454,7 +7476,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7466,7 +7488,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020001", "TakenAlone": "0", "CounterMask": "0", @@ -7476,7 +7498,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7488,7 +7510,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020001", "TakenAlone": "0", "CounterMask": "0", @@ -7498,7 +7520,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7510,7 +7532,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020001", "TakenAlone": "0", "CounterMask": "0", @@ -7520,7 +7542,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7532,7 +7554,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020001", "TakenAlone": "0", "CounterMask": "0", @@ -7542,7 +7564,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7554,7 +7576,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020001", "TakenAlone": "0", "CounterMask": "0", @@ -7564,7 +7586,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7576,7 +7598,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020001", "TakenAlone": "0", "CounterMask": "0", @@ -7586,7 +7608,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7598,7 +7620,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7608,7 +7630,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7620,7 +7642,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7630,7 +7652,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7642,7 +7664,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7652,7 +7674,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7664,7 +7686,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7674,7 +7696,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7686,7 +7708,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7696,7 +7718,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7708,7 +7730,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7718,7 +7740,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7730,7 +7752,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7740,7 +7762,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7752,7 +7774,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000001", "TakenAlone": "0", "CounterMask": "0", @@ -7762,7 +7784,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7774,7 +7796,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000001", "TakenAlone": "0", "CounterMask": "0", @@ -7784,7 +7806,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7796,7 +7818,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000001", "TakenAlone": "0", "CounterMask": "0", @@ -7806,7 +7828,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7818,7 +7840,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000001", "TakenAlone": "0", "CounterMask": "0", @@ -7828,7 +7850,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7840,7 +7862,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000001", "TakenAlone": "0", "CounterMask": "0", @@ -7850,7 +7872,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7862,7 +7884,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000001", "TakenAlone": "0", "CounterMask": "0", @@ -7872,7 +7894,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7884,7 +7906,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000001", "TakenAlone": "0", "CounterMask": "0", @@ -7894,7 +7916,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7906,7 +7928,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000001", "TakenAlone": "0", "CounterMask": "0", @@ -7916,7 +7938,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7928,7 +7950,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000001", "TakenAlone": "0", "CounterMask": "0", @@ -7938,7 +7960,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7950,7 +7972,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000001", "TakenAlone": "0", "CounterMask": "0", @@ -7960,7 +7982,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7972,7 +7994,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000001", "TakenAlone": "0", "CounterMask": "0", @@ -7982,7 +8004,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -7994,7 +8016,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010002", "TakenAlone": "0", "CounterMask": "0", @@ -8004,7 +8026,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8016,7 +8038,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0002", "TakenAlone": "0", "CounterMask": "0", @@ -8026,7 +8048,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8038,7 +8060,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -8048,7 +8070,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8060,7 +8082,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -8070,7 +8092,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8082,7 +8104,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -8092,7 +8114,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8104,7 +8126,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -8114,7 +8136,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8126,7 +8148,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -8136,7 +8158,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8148,7 +8170,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0002", "TakenAlone": "0", "CounterMask": "0", @@ -8158,7 +8180,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8170,7 +8192,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000002", "TakenAlone": "0", "CounterMask": "0", @@ -8180,7 +8202,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8192,7 +8214,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000002", "TakenAlone": "0", "CounterMask": "0", @@ -8202,7 +8224,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8214,7 +8236,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000002", "TakenAlone": "0", "CounterMask": "0", @@ -8224,7 +8246,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8236,7 +8258,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000002", "TakenAlone": "0", "CounterMask": "0", @@ -8246,7 +8268,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8258,7 +8280,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000002", "TakenAlone": "0", "CounterMask": "0", @@ -8268,7 +8290,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8280,7 +8302,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010004", "TakenAlone": "0", "CounterMask": "0", @@ -8290,7 +8312,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8302,7 +8324,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020004", "TakenAlone": "0", "CounterMask": "0", @@ -8312,7 +8334,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8324,7 +8346,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020004", "TakenAlone": "0", "CounterMask": "0", @@ -8334,7 +8356,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8346,7 +8368,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020004", "TakenAlone": "0", "CounterMask": "0", @@ -8356,7 +8378,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8368,7 +8390,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020004", "TakenAlone": "0", "CounterMask": "0", @@ -8378,7 +8400,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8390,7 +8412,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020004", "TakenAlone": "0", "CounterMask": "0", @@ -8400,7 +8422,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8412,7 +8434,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020004", "TakenAlone": "0", "CounterMask": "0", @@ -8422,7 +8444,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8434,7 +8456,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020004", "TakenAlone": "0", "CounterMask": "0", @@ -8444,7 +8466,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8456,7 +8478,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8466,7 +8488,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8478,7 +8500,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8488,7 +8510,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8500,7 +8522,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8510,7 +8532,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8522,7 +8544,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8532,7 +8554,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8544,7 +8566,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8554,7 +8576,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8566,7 +8588,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8576,7 +8598,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8588,7 +8610,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8598,7 +8620,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8610,7 +8632,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000004", "TakenAlone": "0", "CounterMask": "0", @@ -8620,7 +8642,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8632,7 +8654,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000004", "TakenAlone": "0", "CounterMask": "0", @@ -8642,7 +8664,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8654,7 +8676,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000004", "TakenAlone": "0", "CounterMask": "0", @@ -8664,7 +8686,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8676,7 +8698,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000004", "TakenAlone": "0", "CounterMask": "0", @@ -8686,7 +8708,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8698,7 +8720,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000004", "TakenAlone": "0", "CounterMask": "0", @@ -8708,7 +8730,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8720,7 +8742,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000004", "TakenAlone": "0", "CounterMask": "0", @@ -8730,7 +8752,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8742,7 +8764,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000004", "TakenAlone": "0", "CounterMask": "0", @@ -8752,7 +8774,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8764,7 +8786,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000004", "TakenAlone": "0", "CounterMask": "0", @@ -8774,7 +8796,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8786,7 +8808,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000004", "TakenAlone": "0", "CounterMask": "0", @@ -8796,7 +8818,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8808,7 +8830,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000004", "TakenAlone": "0", "CounterMask": "0", @@ -8818,7 +8840,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8830,7 +8852,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000004", "TakenAlone": "0", "CounterMask": "0", @@ -8840,7 +8862,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8852,7 +8874,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010008", "TakenAlone": "0", "CounterMask": "0", @@ -8862,7 +8884,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8874,7 +8896,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020008", "TakenAlone": "0", "CounterMask": "0", @@ -8884,7 +8906,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8896,7 +8918,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020008", "TakenAlone": "0", "CounterMask": "0", @@ -8906,7 +8928,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8918,7 +8940,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020008", "TakenAlone": "0", "CounterMask": "0", @@ -8928,7 +8950,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8940,7 +8962,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020008", "TakenAlone": "0", "CounterMask": "0", @@ -8950,7 +8972,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8962,7 +8984,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020008", "TakenAlone": "0", "CounterMask": "0", @@ -8972,7 +8994,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -8984,7 +9006,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020008", "TakenAlone": "0", "CounterMask": "0", @@ -8994,7 +9016,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9006,7 +9028,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020008", "TakenAlone": "0", "CounterMask": "0", @@ -9016,7 +9038,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9028,7 +9050,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0008", "TakenAlone": "0", "CounterMask": "0", @@ -9038,7 +9060,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9050,7 +9072,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0008", "TakenAlone": "0", "CounterMask": "0", @@ -9060,7 +9082,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9072,7 +9094,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0008", "TakenAlone": "0", "CounterMask": "0", @@ -9082,7 +9104,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9094,7 +9116,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0008", "TakenAlone": "0", "CounterMask": "0", @@ -9104,7 +9126,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9116,7 +9138,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0008", "TakenAlone": "0", "CounterMask": "0", @@ -9126,7 +9148,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9138,7 +9160,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0008", "TakenAlone": "0", "CounterMask": "0", @@ -9148,7 +9170,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9160,7 +9182,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0008", "TakenAlone": "0", "CounterMask": "0", @@ -9170,7 +9192,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9182,7 +9204,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000008", "TakenAlone": "0", "CounterMask": "0", @@ -9192,7 +9214,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9204,7 +9226,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000008", "TakenAlone": "0", "CounterMask": "0", @@ -9214,7 +9236,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9226,7 +9248,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000008", "TakenAlone": "0", "CounterMask": "0", @@ -9236,7 +9258,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9248,7 +9270,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000008", "TakenAlone": "0", "CounterMask": "0", @@ -9258,7 +9280,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9270,7 +9292,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000008", "TakenAlone": "0", "CounterMask": "0", @@ -9280,7 +9302,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9292,7 +9314,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000008", "TakenAlone": "0", "CounterMask": "0", @@ -9302,7 +9324,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9314,7 +9336,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000008", "TakenAlone": "0", "CounterMask": "0", @@ -9324,7 +9346,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9336,7 +9358,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000008", "TakenAlone": "0", "CounterMask": "0", @@ -9346,7 +9368,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9358,7 +9380,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000008", "TakenAlone": "0", "CounterMask": "0", @@ -9368,7 +9390,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9380,7 +9402,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000008", "TakenAlone": "0", "CounterMask": "0", @@ -9390,7 +9412,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9402,7 +9424,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000008", "TakenAlone": "0", "CounterMask": "0", @@ -9412,7 +9434,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9424,7 +9446,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010010", "TakenAlone": "0", "CounterMask": "0", @@ -9434,7 +9456,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9446,7 +9468,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020010", "TakenAlone": "0", "CounterMask": "0", @@ -9456,7 +9478,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9468,7 +9490,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020010", "TakenAlone": "0", "CounterMask": "0", @@ -9478,7 +9500,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9490,7 +9512,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020010", "TakenAlone": "0", "CounterMask": "0", @@ -9500,7 +9522,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9512,7 +9534,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020010", "TakenAlone": "0", "CounterMask": "0", @@ -9522,7 +9544,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9534,7 +9556,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020010", "TakenAlone": "0", "CounterMask": "0", @@ -9544,7 +9566,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9556,7 +9578,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020010", "TakenAlone": "0", "CounterMask": "0", @@ -9566,7 +9588,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9578,7 +9600,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020010", "TakenAlone": "0", "CounterMask": "0", @@ -9588,7 +9610,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9600,7 +9622,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0010", "TakenAlone": "0", "CounterMask": "0", @@ -9610,7 +9632,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9622,7 +9644,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0010", "TakenAlone": "0", "CounterMask": "0", @@ -9632,7 +9654,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9644,7 +9666,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0010", "TakenAlone": "0", "CounterMask": "0", @@ -9654,7 +9676,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9666,7 +9688,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0010", "TakenAlone": "0", "CounterMask": "0", @@ -9676,7 +9698,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9688,7 +9710,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0010", "TakenAlone": "0", "CounterMask": "0", @@ -9698,7 +9720,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9710,7 +9732,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0010", "TakenAlone": "0", "CounterMask": "0", @@ -9720,7 +9742,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9732,7 +9754,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0010", "TakenAlone": "0", "CounterMask": "0", @@ -9742,7 +9764,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9754,7 +9776,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000010", "TakenAlone": "0", "CounterMask": "0", @@ -9764,7 +9786,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9776,7 +9798,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000010", "TakenAlone": "0", "CounterMask": "0", @@ -9786,7 +9808,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9798,7 +9820,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000010", "TakenAlone": "0", "CounterMask": "0", @@ -9808,7 +9830,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9820,7 +9842,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000010", "TakenAlone": "0", "CounterMask": "0", @@ -9830,7 +9852,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9842,7 +9864,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000010", "TakenAlone": "0", "CounterMask": "0", @@ -9852,7 +9874,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9864,7 +9886,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000010", "TakenAlone": "0", "CounterMask": "0", @@ -9874,7 +9896,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9886,7 +9908,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000010", "TakenAlone": "0", "CounterMask": "0", @@ -9896,7 +9918,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9908,7 +9930,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000010", "TakenAlone": "0", "CounterMask": "0", @@ -9918,7 +9940,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9930,7 +9952,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000010", "TakenAlone": "0", "CounterMask": "0", @@ -9940,7 +9962,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9952,7 +9974,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000010", "TakenAlone": "0", "CounterMask": "0", @@ -9962,7 +9984,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9974,7 +9996,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000010", "TakenAlone": "0", "CounterMask": "0", @@ -9984,7 +10006,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -9996,7 +10018,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010020", "TakenAlone": "0", "CounterMask": "0", @@ -10006,7 +10028,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10018,7 +10040,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020020", "TakenAlone": "0", "CounterMask": "0", @@ -10028,7 +10050,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10040,7 +10062,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020020", "TakenAlone": "0", "CounterMask": "0", @@ -10050,7 +10072,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10062,7 +10084,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020020", "TakenAlone": "0", "CounterMask": "0", @@ -10072,7 +10094,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10084,7 +10106,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020020", "TakenAlone": "0", "CounterMask": "0", @@ -10094,7 +10116,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10106,7 +10128,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020020", "TakenAlone": "0", "CounterMask": "0", @@ -10116,7 +10138,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10128,7 +10150,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020020", "TakenAlone": "0", "CounterMask": "0", @@ -10138,7 +10160,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10150,7 +10172,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020020", "TakenAlone": "0", "CounterMask": "0", @@ -10160,7 +10182,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10172,7 +10194,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0020", "TakenAlone": "0", "CounterMask": "0", @@ -10182,7 +10204,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10194,7 +10216,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0020", "TakenAlone": "0", "CounterMask": "0", @@ -10204,7 +10226,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10216,7 +10238,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0020", "TakenAlone": "0", "CounterMask": "0", @@ -10226,7 +10248,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10238,7 +10260,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0020", "TakenAlone": "0", "CounterMask": "0", @@ -10248,7 +10270,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10260,7 +10282,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0020", "TakenAlone": "0", "CounterMask": "0", @@ -10270,7 +10292,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10282,7 +10304,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0020", "TakenAlone": "0", "CounterMask": "0", @@ -10292,7 +10314,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10304,7 +10326,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0020", "TakenAlone": "0", "CounterMask": "0", @@ -10314,7 +10336,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10326,7 +10348,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000020", "TakenAlone": "0", "CounterMask": "0", @@ -10336,7 +10358,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10348,7 +10370,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000020", "TakenAlone": "0", "CounterMask": "0", @@ -10358,7 +10380,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10370,7 +10392,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000020", "TakenAlone": "0", "CounterMask": "0", @@ -10380,7 +10402,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10392,7 +10414,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000020", "TakenAlone": "0", "CounterMask": "0", @@ -10402,7 +10424,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10414,7 +10436,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000020", "TakenAlone": "0", "CounterMask": "0", @@ -10424,7 +10446,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10436,7 +10458,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000020", "TakenAlone": "0", "CounterMask": "0", @@ -10446,7 +10468,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10458,7 +10480,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000020", "TakenAlone": "0", "CounterMask": "0", @@ -10468,7 +10490,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10480,7 +10502,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000020", "TakenAlone": "0", "CounterMask": "0", @@ -10490,7 +10512,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10502,7 +10524,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000020", "TakenAlone": "0", "CounterMask": "0", @@ -10512,7 +10534,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10524,7 +10546,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000020", "TakenAlone": "0", "CounterMask": "0", @@ -10534,7 +10556,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10546,7 +10568,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000020", "TakenAlone": "0", "CounterMask": "0", @@ -10556,7 +10578,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10568,7 +10590,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010040", "TakenAlone": "0", "CounterMask": "0", @@ -10578,7 +10600,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10590,7 +10612,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020040", "TakenAlone": "0", "CounterMask": "0", @@ -10600,7 +10622,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10612,7 +10634,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020040", "TakenAlone": "0", "CounterMask": "0", @@ -10622,7 +10644,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10634,7 +10656,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020040", "TakenAlone": "0", "CounterMask": "0", @@ -10644,7 +10666,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10656,7 +10678,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020040", "TakenAlone": "0", "CounterMask": "0", @@ -10666,7 +10688,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10678,7 +10700,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020040", "TakenAlone": "0", "CounterMask": "0", @@ -10688,7 +10710,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10700,7 +10722,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020040", "TakenAlone": "0", "CounterMask": "0", @@ -10710,7 +10732,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10722,7 +10744,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020040", "TakenAlone": "0", "CounterMask": "0", @@ -10732,7 +10754,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10744,7 +10766,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0040", "TakenAlone": "0", "CounterMask": "0", @@ -10754,7 +10776,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10766,7 +10788,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0040", "TakenAlone": "0", "CounterMask": "0", @@ -10776,7 +10798,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10788,7 +10810,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0040", "TakenAlone": "0", "CounterMask": "0", @@ -10798,7 +10820,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10810,7 +10832,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0040", "TakenAlone": "0", "CounterMask": "0", @@ -10820,7 +10842,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10832,7 +10854,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0040", "TakenAlone": "0", "CounterMask": "0", @@ -10842,7 +10864,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10854,7 +10876,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0040", "TakenAlone": "0", "CounterMask": "0", @@ -10864,7 +10886,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10876,7 +10898,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0040", "TakenAlone": "0", "CounterMask": "0", @@ -10886,7 +10908,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10898,7 +10920,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000040", "TakenAlone": "0", "CounterMask": "0", @@ -10908,7 +10930,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10920,7 +10942,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000040", "TakenAlone": "0", "CounterMask": "0", @@ -10930,7 +10952,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10942,7 +10964,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000040", "TakenAlone": "0", "CounterMask": "0", @@ -10952,7 +10974,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10964,7 +10986,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000040", "TakenAlone": "0", "CounterMask": "0", @@ -10974,7 +10996,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -10986,7 +11008,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000040", "TakenAlone": "0", "CounterMask": "0", @@ -10996,7 +11018,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11008,7 +11030,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000040", "TakenAlone": "0", "CounterMask": "0", @@ -11018,7 +11040,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11030,7 +11052,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000040", "TakenAlone": "0", "CounterMask": "0", @@ -11040,7 +11062,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11052,7 +11074,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000040", "TakenAlone": "0", "CounterMask": "0", @@ -11062,7 +11084,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11074,7 +11096,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000040", "TakenAlone": "0", "CounterMask": "0", @@ -11084,7 +11106,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11096,7 +11118,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000040", "TakenAlone": "0", "CounterMask": "0", @@ -11106,7 +11128,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11118,7 +11140,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000040", "TakenAlone": "0", "CounterMask": "0", @@ -11128,7 +11150,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11140,7 +11162,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010080", "TakenAlone": "0", "CounterMask": "0", @@ -11150,7 +11172,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11162,7 +11184,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020080", "TakenAlone": "0", "CounterMask": "0", @@ -11172,7 +11194,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11184,7 +11206,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020080", "TakenAlone": "0", "CounterMask": "0", @@ -11194,7 +11216,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11206,7 +11228,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020080", "TakenAlone": "0", "CounterMask": "0", @@ -11216,7 +11238,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11228,7 +11250,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020080", "TakenAlone": "0", "CounterMask": "0", @@ -11238,7 +11260,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11250,7 +11272,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020080", "TakenAlone": "0", "CounterMask": "0", @@ -11260,7 +11282,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11272,7 +11294,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020080", "TakenAlone": "0", "CounterMask": "0", @@ -11282,7 +11304,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11294,7 +11316,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020080", "TakenAlone": "0", "CounterMask": "0", @@ -11304,7 +11326,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11316,7 +11338,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0080", "TakenAlone": "0", "CounterMask": "0", @@ -11326,7 +11348,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11338,7 +11360,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0080", "TakenAlone": "0", "CounterMask": "0", @@ -11348,7 +11370,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11360,7 +11382,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0080", "TakenAlone": "0", "CounterMask": "0", @@ -11370,7 +11392,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11382,7 +11404,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0080", "TakenAlone": "0", "CounterMask": "0", @@ -11392,7 +11414,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11404,7 +11426,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0080", "TakenAlone": "0", "CounterMask": "0", @@ -11414,7 +11436,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11426,7 +11448,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0080", "TakenAlone": "0", "CounterMask": "0", @@ -11436,7 +11458,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11448,7 +11470,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0080", "TakenAlone": "0", "CounterMask": "0", @@ -11458,7 +11480,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11470,7 +11492,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000080", "TakenAlone": "0", "CounterMask": "0", @@ -11480,7 +11502,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11492,7 +11514,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000080", "TakenAlone": "0", "CounterMask": "0", @@ -11502,7 +11524,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11514,7 +11536,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000080", "TakenAlone": "0", "CounterMask": "0", @@ -11524,7 +11546,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11536,7 +11558,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000080", "TakenAlone": "0", "CounterMask": "0", @@ -11546,7 +11568,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11558,7 +11580,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000080", "TakenAlone": "0", "CounterMask": "0", @@ -11568,7 +11590,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11580,7 +11602,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000080", "TakenAlone": "0", "CounterMask": "0", @@ -11590,7 +11612,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11602,7 +11624,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000080", "TakenAlone": "0", "CounterMask": "0", @@ -11612,7 +11634,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11624,7 +11646,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000080", "TakenAlone": "0", "CounterMask": "0", @@ -11634,7 +11656,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11646,7 +11668,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000080", "TakenAlone": "0", "CounterMask": "0", @@ -11656,7 +11678,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11668,7 +11690,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000080", "TakenAlone": "0", "CounterMask": "0", @@ -11678,7 +11700,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11690,7 +11712,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000080", "TakenAlone": "0", "CounterMask": "0", @@ -11700,7 +11722,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11712,7 +11734,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010100", "TakenAlone": "0", "CounterMask": "0", @@ -11722,7 +11744,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11734,7 +11756,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020100", "TakenAlone": "0", "CounterMask": "0", @@ -11744,7 +11766,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11756,7 +11778,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020100", "TakenAlone": "0", "CounterMask": "0", @@ -11766,7 +11788,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11778,7 +11800,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020100", "TakenAlone": "0", "CounterMask": "0", @@ -11788,7 +11810,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11800,7 +11822,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020100", "TakenAlone": "0", "CounterMask": "0", @@ -11810,7 +11832,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11822,7 +11844,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020100", "TakenAlone": "0", "CounterMask": "0", @@ -11832,7 +11854,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11844,7 +11866,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020100", "TakenAlone": "0", "CounterMask": "0", @@ -11854,7 +11876,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11866,7 +11888,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020100", "TakenAlone": "0", "CounterMask": "0", @@ -11876,7 +11898,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11888,7 +11910,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0100", "TakenAlone": "0", "CounterMask": "0", @@ -11898,7 +11920,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11910,7 +11932,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0100", "TakenAlone": "0", "CounterMask": "0", @@ -11920,7 +11942,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11932,7 +11954,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0100", "TakenAlone": "0", "CounterMask": "0", @@ -11942,7 +11964,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11954,7 +11976,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0100", "TakenAlone": "0", "CounterMask": "0", @@ -11964,7 +11986,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11976,7 +11998,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0100", "TakenAlone": "0", "CounterMask": "0", @@ -11986,7 +12008,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -11998,7 +12020,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0100", "TakenAlone": "0", "CounterMask": "0", @@ -12008,7 +12030,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12020,7 +12042,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0100", "TakenAlone": "0", "CounterMask": "0", @@ -12030,7 +12052,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12042,7 +12064,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000100", "TakenAlone": "0", "CounterMask": "0", @@ -12052,7 +12074,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12064,7 +12086,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000100", "TakenAlone": "0", "CounterMask": "0", @@ -12074,7 +12096,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12086,7 +12108,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000100", "TakenAlone": "0", "CounterMask": "0", @@ -12096,7 +12118,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12108,7 +12130,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000100", "TakenAlone": "0", "CounterMask": "0", @@ -12118,7 +12140,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12130,7 +12152,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000100", "TakenAlone": "0", "CounterMask": "0", @@ -12140,7 +12162,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12152,7 +12174,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000100", "TakenAlone": "0", "CounterMask": "0", @@ -12162,7 +12184,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12174,7 +12196,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000100", "TakenAlone": "0", "CounterMask": "0", @@ -12184,7 +12206,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12196,7 +12218,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000100", "TakenAlone": "0", "CounterMask": "0", @@ -12206,7 +12228,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12218,7 +12240,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000100", "TakenAlone": "0", "CounterMask": "0", @@ -12228,7 +12250,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12240,7 +12262,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000100", "TakenAlone": "0", "CounterMask": "0", @@ -12250,7 +12272,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12262,7 +12284,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000100", "TakenAlone": "0", "CounterMask": "0", @@ -12272,7 +12294,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12284,7 +12306,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010200", "TakenAlone": "0", "CounterMask": "0", @@ -12294,7 +12316,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12306,7 +12328,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020200", "TakenAlone": "0", "CounterMask": "0", @@ -12316,7 +12338,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12328,7 +12350,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020200", "TakenAlone": "0", "CounterMask": "0", @@ -12338,7 +12360,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12350,7 +12372,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020200", "TakenAlone": "0", "CounterMask": "0", @@ -12360,7 +12382,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12372,7 +12394,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020200", "TakenAlone": "0", "CounterMask": "0", @@ -12382,7 +12404,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12394,7 +12416,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020200", "TakenAlone": "0", "CounterMask": "0", @@ -12404,7 +12426,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12416,7 +12438,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020200", "TakenAlone": "0", "CounterMask": "0", @@ -12426,7 +12448,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12438,7 +12460,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020200", "TakenAlone": "0", "CounterMask": "0", @@ -12448,7 +12470,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12460,7 +12482,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0200", "TakenAlone": "0", "CounterMask": "0", @@ -12470,7 +12492,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12482,7 +12504,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0200", "TakenAlone": "0", "CounterMask": "0", @@ -12492,7 +12514,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12504,7 +12526,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0200", "TakenAlone": "0", "CounterMask": "0", @@ -12514,7 +12536,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12526,7 +12548,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0200", "TakenAlone": "0", "CounterMask": "0", @@ -12536,7 +12558,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12548,7 +12570,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0200", "TakenAlone": "0", "CounterMask": "0", @@ -12558,7 +12580,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12570,7 +12592,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0200", "TakenAlone": "0", "CounterMask": "0", @@ -12580,7 +12602,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12592,7 +12614,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0200", "TakenAlone": "0", "CounterMask": "0", @@ -12602,7 +12624,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12614,7 +12636,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000200", "TakenAlone": "0", "CounterMask": "0", @@ -12624,7 +12646,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12636,7 +12658,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000200", "TakenAlone": "0", "CounterMask": "0", @@ -12646,7 +12668,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12658,7 +12680,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000200", "TakenAlone": "0", "CounterMask": "0", @@ -12668,7 +12690,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12680,7 +12702,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000200", "TakenAlone": "0", "CounterMask": "0", @@ -12690,7 +12712,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12702,7 +12724,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000200", "TakenAlone": "0", "CounterMask": "0", @@ -12712,7 +12734,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12724,7 +12746,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000200", "TakenAlone": "0", "CounterMask": "0", @@ -12734,7 +12756,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12746,7 +12768,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000200", "TakenAlone": "0", "CounterMask": "0", @@ -12756,7 +12778,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12768,7 +12790,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000200", "TakenAlone": "0", "CounterMask": "0", @@ -12778,7 +12800,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12790,7 +12812,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000200", "TakenAlone": "0", "CounterMask": "0", @@ -12800,7 +12822,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12812,7 +12834,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000200", "TakenAlone": "0", "CounterMask": "0", @@ -12822,7 +12844,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12834,7 +12856,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000200", "TakenAlone": "0", "CounterMask": "0", @@ -12844,7 +12866,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12856,7 +12878,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000018000", "TakenAlone": "0", "CounterMask": "0", @@ -12866,7 +12888,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12878,7 +12900,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080028000", "TakenAlone": "0", "CounterMask": "0", @@ -12888,7 +12910,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12900,7 +12922,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100028000", "TakenAlone": "0", "CounterMask": "0", @@ -12910,7 +12932,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12922,7 +12944,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200028000", "TakenAlone": "0", "CounterMask": "0", @@ -12932,7 +12954,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12944,7 +12966,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400028000", "TakenAlone": "0", "CounterMask": "0", @@ -12954,7 +12976,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12966,7 +12988,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000028000", "TakenAlone": "0", "CounterMask": "0", @@ -12976,7 +12998,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -12988,7 +13010,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000028000", "TakenAlone": "0", "CounterMask": "0", @@ -12998,7 +13020,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13010,7 +13032,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80028000", "TakenAlone": "0", "CounterMask": "0", @@ -13020,7 +13042,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13032,7 +13054,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C8000", "TakenAlone": "0", "CounterMask": "0", @@ -13042,7 +13064,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13054,7 +13076,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C8000", "TakenAlone": "0", "CounterMask": "0", @@ -13064,7 +13086,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13076,7 +13098,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C8000", "TakenAlone": "0", "CounterMask": "0", @@ -13086,7 +13108,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13098,7 +13120,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C8000", "TakenAlone": "0", "CounterMask": "0", @@ -13108,7 +13130,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13120,7 +13142,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C8000", "TakenAlone": "0", "CounterMask": "0", @@ -13130,7 +13152,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13142,7 +13164,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C8000", "TakenAlone": "0", "CounterMask": "0", @@ -13152,7 +13174,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13164,7 +13186,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C8000", "TakenAlone": "0", "CounterMask": "0", @@ -13174,7 +13196,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13186,7 +13208,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084008000", "TakenAlone": "0", "CounterMask": "0", @@ -13196,7 +13218,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13208,7 +13230,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104008000", "TakenAlone": "0", "CounterMask": "0", @@ -13218,7 +13240,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13230,7 +13252,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204008000", "TakenAlone": "0", "CounterMask": "0", @@ -13240,7 +13262,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13252,7 +13274,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404008000", "TakenAlone": "0", "CounterMask": "0", @@ -13262,7 +13284,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13274,7 +13296,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004008000", "TakenAlone": "0", "CounterMask": "0", @@ -13284,7 +13306,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13296,7 +13318,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004008000", "TakenAlone": "0", "CounterMask": "0", @@ -13306,7 +13328,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13318,7 +13340,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84008000", "TakenAlone": "0", "CounterMask": "0", @@ -13328,7 +13350,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13340,7 +13362,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC008000", "TakenAlone": "0", "CounterMask": "0", @@ -13350,7 +13372,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13362,7 +13384,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C008000", "TakenAlone": "0", "CounterMask": "0", @@ -13372,7 +13394,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13384,7 +13406,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C008000", "TakenAlone": "0", "CounterMask": "0", @@ -13394,7 +13416,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13406,7 +13428,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C008000", "TakenAlone": "0", "CounterMask": "0", @@ -13416,7 +13438,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13428,7 +13450,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010090", "TakenAlone": "0", "CounterMask": "0", @@ -13438,7 +13460,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13450,7 +13472,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020090", "TakenAlone": "0", "CounterMask": "0", @@ -13460,7 +13482,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13472,7 +13494,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020090", "TakenAlone": "0", "CounterMask": "0", @@ -13482,7 +13504,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13494,7 +13516,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020090", "TakenAlone": "0", "CounterMask": "0", @@ -13504,7 +13526,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13516,7 +13538,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020090", "TakenAlone": "0", "CounterMask": "0", @@ -13526,7 +13548,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13538,7 +13560,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020090", "TakenAlone": "0", "CounterMask": "0", @@ -13548,7 +13570,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13560,7 +13582,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020090", "TakenAlone": "0", "CounterMask": "0", @@ -13570,7 +13592,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13582,7 +13604,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020090", "TakenAlone": "0", "CounterMask": "0", @@ -13592,7 +13614,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13604,7 +13626,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0090", "TakenAlone": "0", "CounterMask": "0", @@ -13614,7 +13636,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13626,7 +13648,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0090", "TakenAlone": "0", "CounterMask": "0", @@ -13636,7 +13658,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13648,7 +13670,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0090", "TakenAlone": "0", "CounterMask": "0", @@ -13658,7 +13680,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13670,7 +13692,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0090", "TakenAlone": "0", "CounterMask": "0", @@ -13680,7 +13702,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13692,7 +13714,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0090", "TakenAlone": "0", "CounterMask": "0", @@ -13702,7 +13724,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13714,7 +13736,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0090", "TakenAlone": "0", "CounterMask": "0", @@ -13724,7 +13746,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13736,7 +13758,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0090", "TakenAlone": "0", "CounterMask": "0", @@ -13746,7 +13768,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13758,7 +13780,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000090", "TakenAlone": "0", "CounterMask": "0", @@ -13768,7 +13790,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13780,7 +13802,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000090", "TakenAlone": "0", "CounterMask": "0", @@ -13790,7 +13812,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13802,7 +13824,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000090", "TakenAlone": "0", "CounterMask": "0", @@ -13812,7 +13834,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13824,7 +13846,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000090", "TakenAlone": "0", "CounterMask": "0", @@ -13834,7 +13856,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13846,7 +13868,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000090", "TakenAlone": "0", "CounterMask": "0", @@ -13856,7 +13878,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13868,7 +13890,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000090", "TakenAlone": "0", "CounterMask": "0", @@ -13878,7 +13900,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13890,7 +13912,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000090", "TakenAlone": "0", "CounterMask": "0", @@ -13900,7 +13922,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13912,7 +13934,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000090", "TakenAlone": "0", "CounterMask": "0", @@ -13922,7 +13944,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13934,7 +13956,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000090", "TakenAlone": "0", "CounterMask": "0", @@ -13944,7 +13966,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13956,7 +13978,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000090", "TakenAlone": "0", "CounterMask": "0", @@ -13966,7 +13988,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -13978,7 +14000,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000090", "TakenAlone": "0", "CounterMask": "0", @@ -13988,7 +14010,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14000,7 +14022,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010120", "TakenAlone": "0", "CounterMask": "0", @@ -14010,7 +14032,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14022,7 +14044,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020120", "TakenAlone": "0", "CounterMask": "0", @@ -14032,7 +14054,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14044,7 +14066,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020120", "TakenAlone": "0", "CounterMask": "0", @@ -14054,7 +14076,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14066,7 +14088,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020120", "TakenAlone": "0", "CounterMask": "0", @@ -14076,7 +14098,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14088,7 +14110,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020120", "TakenAlone": "0", "CounterMask": "0", @@ -14098,7 +14120,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14110,7 +14132,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020120", "TakenAlone": "0", "CounterMask": "0", @@ -14120,7 +14142,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14132,7 +14154,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020120", "TakenAlone": "0", "CounterMask": "0", @@ -14142,7 +14164,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14154,7 +14176,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020120", "TakenAlone": "0", "CounterMask": "0", @@ -14164,7 +14186,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14176,7 +14198,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0120", "TakenAlone": "0", "CounterMask": "0", @@ -14186,7 +14208,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14198,7 +14220,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0120", "TakenAlone": "0", "CounterMask": "0", @@ -14208,7 +14230,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14220,7 +14242,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0120", "TakenAlone": "0", "CounterMask": "0", @@ -14230,7 +14252,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14242,7 +14264,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0120", "TakenAlone": "0", "CounterMask": "0", @@ -14252,7 +14274,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14264,7 +14286,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0120", "TakenAlone": "0", "CounterMask": "0", @@ -14274,7 +14296,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14286,7 +14308,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0120", "TakenAlone": "0", "CounterMask": "0", @@ -14296,7 +14318,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14308,7 +14330,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0120", "TakenAlone": "0", "CounterMask": "0", @@ -14318,7 +14340,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14330,7 +14352,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000120", "TakenAlone": "0", "CounterMask": "0", @@ -14340,7 +14362,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14352,7 +14374,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000120", "TakenAlone": "0", "CounterMask": "0", @@ -14362,7 +14384,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14374,7 +14396,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000120", "TakenAlone": "0", "CounterMask": "0", @@ -14384,7 +14406,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14396,7 +14418,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000120", "TakenAlone": "0", "CounterMask": "0", @@ -14406,7 +14428,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14418,7 +14440,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000120", "TakenAlone": "0", "CounterMask": "0", @@ -14428,7 +14450,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14440,7 +14462,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000120", "TakenAlone": "0", "CounterMask": "0", @@ -14450,7 +14472,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14462,7 +14484,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000120", "TakenAlone": "0", "CounterMask": "0", @@ -14472,7 +14494,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14484,7 +14506,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000120", "TakenAlone": "0", "CounterMask": "0", @@ -14494,7 +14516,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14506,7 +14528,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000120", "TakenAlone": "0", "CounterMask": "0", @@ -14516,7 +14538,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14528,7 +14550,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000120", "TakenAlone": "0", "CounterMask": "0", @@ -14538,7 +14560,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14550,7 +14572,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000120", "TakenAlone": "0", "CounterMask": "0", @@ -14560,7 +14582,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14572,7 +14594,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010240", "TakenAlone": "0", "CounterMask": "0", @@ -14582,7 +14604,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14594,7 +14616,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020240", "TakenAlone": "0", "CounterMask": "0", @@ -14604,7 +14626,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14616,7 +14638,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020240", "TakenAlone": "0", "CounterMask": "0", @@ -14626,7 +14648,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14638,7 +14660,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020240", "TakenAlone": "0", "CounterMask": "0", @@ -14648,7 +14670,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14660,7 +14682,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020240", "TakenAlone": "0", "CounterMask": "0", @@ -14670,7 +14692,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14682,7 +14704,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020240", "TakenAlone": "0", "CounterMask": "0", @@ -14692,7 +14714,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14704,7 +14726,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020240", "TakenAlone": "0", "CounterMask": "0", @@ -14714,7 +14736,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14726,7 +14748,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020240", "TakenAlone": "0", "CounterMask": "0", @@ -14736,7 +14758,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14748,7 +14770,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0240", "TakenAlone": "0", "CounterMask": "0", @@ -14758,7 +14780,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14770,7 +14792,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0240", "TakenAlone": "0", "CounterMask": "0", @@ -14780,7 +14802,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14792,7 +14814,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0240", "TakenAlone": "0", "CounterMask": "0", @@ -14802,7 +14824,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14814,7 +14836,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0240", "TakenAlone": "0", "CounterMask": "0", @@ -14824,7 +14846,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14836,7 +14858,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0240", "TakenAlone": "0", "CounterMask": "0", @@ -14846,7 +14868,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14858,7 +14880,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0240", "TakenAlone": "0", "CounterMask": "0", @@ -14868,7 +14890,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14880,7 +14902,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0240", "TakenAlone": "0", "CounterMask": "0", @@ -14890,7 +14912,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14902,7 +14924,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000240", "TakenAlone": "0", "CounterMask": "0", @@ -14912,7 +14934,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14924,7 +14946,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000240", "TakenAlone": "0", "CounterMask": "0", @@ -14934,7 +14956,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14946,7 +14968,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000240", "TakenAlone": "0", "CounterMask": "0", @@ -14956,7 +14978,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14968,7 +14990,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000240", "TakenAlone": "0", "CounterMask": "0", @@ -14978,7 +15000,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -14990,7 +15012,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000240", "TakenAlone": "0", "CounterMask": "0", @@ -15000,7 +15022,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15012,7 +15034,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000240", "TakenAlone": "0", "CounterMask": "0", @@ -15022,7 +15044,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15034,7 +15056,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000240", "TakenAlone": "0", "CounterMask": "0", @@ -15044,7 +15066,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15056,7 +15078,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000240", "TakenAlone": "0", "CounterMask": "0", @@ -15066,7 +15088,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15078,7 +15100,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000240", "TakenAlone": "0", "CounterMask": "0", @@ -15088,7 +15110,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15100,7 +15122,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000240", "TakenAlone": "0", "CounterMask": "0", @@ -15110,7 +15132,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15122,7 +15144,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000240", "TakenAlone": "0", "CounterMask": "0", @@ -15132,7 +15154,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15144,7 +15166,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010091", "TakenAlone": "0", "CounterMask": "0", @@ -15154,7 +15176,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15166,7 +15188,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020091", "TakenAlone": "0", "CounterMask": "0", @@ -15176,7 +15198,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15188,7 +15210,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020091", "TakenAlone": "0", "CounterMask": "0", @@ -15198,7 +15220,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15210,7 +15232,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020091", "TakenAlone": "0", "CounterMask": "0", @@ -15220,7 +15242,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15232,7 +15254,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020091", "TakenAlone": "0", "CounterMask": "0", @@ -15242,7 +15264,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15254,7 +15276,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020091", "TakenAlone": "0", "CounterMask": "0", @@ -15264,7 +15286,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15276,7 +15298,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020091", "TakenAlone": "0", "CounterMask": "0", @@ -15286,7 +15308,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15298,7 +15320,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020091", "TakenAlone": "0", "CounterMask": "0", @@ -15308,7 +15330,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15320,7 +15342,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0091", "TakenAlone": "0", "CounterMask": "0", @@ -15330,7 +15352,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15342,7 +15364,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0091", "TakenAlone": "0", "CounterMask": "0", @@ -15352,7 +15374,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15364,7 +15386,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0091", "TakenAlone": "0", "CounterMask": "0", @@ -15374,7 +15396,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15386,7 +15408,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0091", "TakenAlone": "0", "CounterMask": "0", @@ -15396,7 +15418,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15408,7 +15430,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0091", "TakenAlone": "0", "CounterMask": "0", @@ -15418,7 +15440,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15430,7 +15452,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0091", "TakenAlone": "0", "CounterMask": "0", @@ -15440,7 +15462,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15452,7 +15474,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0091", "TakenAlone": "0", "CounterMask": "0", @@ -15462,7 +15484,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15474,7 +15496,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000091", "TakenAlone": "0", "CounterMask": "0", @@ -15484,7 +15506,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15496,7 +15518,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000091", "TakenAlone": "0", "CounterMask": "0", @@ -15506,7 +15528,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15518,7 +15540,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000091", "TakenAlone": "0", "CounterMask": "0", @@ -15528,7 +15550,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15540,7 +15562,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000091", "TakenAlone": "0", "CounterMask": "0", @@ -15550,7 +15572,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15562,7 +15584,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000091", "TakenAlone": "0", "CounterMask": "0", @@ -15572,7 +15594,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15584,7 +15606,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000091", "TakenAlone": "0", "CounterMask": "0", @@ -15594,7 +15616,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15606,7 +15628,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000091", "TakenAlone": "0", "CounterMask": "0", @@ -15616,7 +15638,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15628,7 +15650,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000091", "TakenAlone": "0", "CounterMask": "0", @@ -15638,7 +15660,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15650,7 +15672,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000091", "TakenAlone": "0", "CounterMask": "0", @@ -15660,7 +15682,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15672,7 +15694,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000091", "TakenAlone": "0", "CounterMask": "0", @@ -15682,7 +15704,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15694,7 +15716,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000091", "TakenAlone": "0", "CounterMask": "0", @@ -15704,7 +15726,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15716,7 +15738,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010122", "TakenAlone": "0", "CounterMask": "0", @@ -15726,7 +15748,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15738,7 +15760,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020122", "TakenAlone": "0", "CounterMask": "0", @@ -15748,7 +15770,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15760,7 +15782,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020122", "TakenAlone": "0", "CounterMask": "0", @@ -15770,7 +15792,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15782,7 +15804,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020122", "TakenAlone": "0", "CounterMask": "0", @@ -15792,7 +15814,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15804,7 +15826,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020122", "TakenAlone": "0", "CounterMask": "0", @@ -15814,7 +15836,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15826,7 +15848,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020122", "TakenAlone": "0", "CounterMask": "0", @@ -15836,7 +15858,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15848,7 +15870,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020122", "TakenAlone": "0", "CounterMask": "0", @@ -15858,7 +15880,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15870,7 +15892,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F80020122", "TakenAlone": "0", "CounterMask": "0", @@ -15880,7 +15902,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15892,7 +15914,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00803C0122", "TakenAlone": "0", "CounterMask": "0", @@ -15902,7 +15924,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15914,7 +15936,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -15924,7 +15946,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15936,7 +15958,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -15946,7 +15968,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15958,7 +15980,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -15968,7 +15990,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -15980,7 +16002,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -15990,7 +16012,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16002,7 +16024,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -16012,7 +16034,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16024,7 +16046,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0122", "TakenAlone": "0", "CounterMask": "0", @@ -16034,7 +16056,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16046,7 +16068,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000122", "TakenAlone": "0", "CounterMask": "0", @@ -16056,7 +16078,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16068,7 +16090,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000122", "TakenAlone": "0", "CounterMask": "0", @@ -16078,7 +16100,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16090,7 +16112,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000122", "TakenAlone": "0", "CounterMask": "0", @@ -16100,7 +16122,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16112,7 +16134,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000122", "TakenAlone": "0", "CounterMask": "0", @@ -16122,7 +16144,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16134,7 +16156,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000122", "TakenAlone": "0", "CounterMask": "0", @@ -16144,7 +16166,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16156,7 +16178,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000122", "TakenAlone": "0", "CounterMask": "0", @@ -16166,7 +16188,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16178,7 +16200,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F84000122", "TakenAlone": "0", "CounterMask": "0", @@ -16188,7 +16210,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16200,7 +16222,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC000122", "TakenAlone": "0", "CounterMask": "0", @@ -16210,7 +16232,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16222,7 +16244,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C000122", "TakenAlone": "0", "CounterMask": "0", @@ -16232,7 +16254,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16244,7 +16266,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C000122", "TakenAlone": "0", "CounterMask": "0", @@ -16254,7 +16276,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" }, { @@ -16266,7 +16288,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C000122", "TakenAlone": "0", "CounterMask": "0", @@ -16276,7 +16298,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "null", + "Errata": "0", "Offcore": "1" } ]
\ No newline at end of file diff --git a/usr/src/data/perfmon/BDW/broadwell_fp_arith_inst_v23.json b/usr/src/data/perfmon/BDW/broadwell_fp_arith_inst_v26.json index 72100df126..72100df126 100644 --- a/usr/src/data/perfmon/BDW/broadwell_fp_arith_inst_v23.json +++ b/usr/src/data/perfmon/BDW/broadwell_fp_arith_inst_v26.json diff --git a/usr/src/data/perfmon/BDW/broadwell_matrix_bit_definitions_v23.json b/usr/src/data/perfmon/BDW/broadwell_matrix_bit_definitions_v23.json deleted file mode 100644 index 0747416988..0000000000 --- a/usr/src/data/perfmon/BDW/broadwell_matrix_bit_definitions_v23.json +++ /dev/null @@ -1,326 +0,0 @@ -[ - { - "BitName": "DEMAND_DATA_RD", - "BitIndex": "0", - "Type": "1", - "Description": "Counts demand data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "DEMAND_RFO", - "BitIndex": "1", - "Type": "1", - "Description": "Counts all demand data writes (RFOs)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "BDM115" - }, - { - "BitName": "DEMAND_CODE_RD", - "BitIndex": "2", - "Type": "1", - "Description": "Counts all demand code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "COREWB", - "BitIndex": "3", - "Type": "1", - "Description": "Counts writebacks (modified to exclusive)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_DATA_RD", - "BitIndex": "4", - "Type": "1", - "Description": "Counts prefetch (that bring data to L2) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_RFO", - "BitIndex": "5", - "Type": "1", - "Description": "Counts all prefetch (that bring data to L2) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "BDM115" - }, - { - "BitName": "PF_L2_CODE_RD", - "BitIndex": "6", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_DATA_RD", - "BitIndex": "7", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_RFO", - "BitIndex": "8", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_CODE_RD", - "BitIndex": "9", - "Type": "1", - "Description": "Counts prefetch (that bring data to LLC only) code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "OTHER", - "BitIndex": "15", - "Type": "1", - "Description": "Counts any other requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_DATA_RD", - "BitIndex": "4,7", - "Type": "1", - "Description": "Counts all prefetch data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_RFO", - "BitIndex": "5,8", - "Type": "1", - "Description": "Counts prefetch RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_CODE_RD", - "BitIndex": "6,9", - "Type": "1", - "Description": "Counts all prefetch code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_DATA_RD", - "BitIndex": "0,4,7", - "Type": "1", - "Description": "Counts all demand & prefetch data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_RFO", - "BitIndex": "1,5,8", - "Type": "1", - "Description": "Counts all demand & prefetch RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "BDM115" - }, - { - "BitName": "ALL_CODE_RD", - "BitIndex": "2,6,9", - "Type": "1", - "Description": "Counts all demand & prefetch code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_READS", - "BitIndex": "0,1,2,4,5,6,7,8,9", - "Type": "1", - "Description": "Counts all data/code/rfo reads (demand & prefetch)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_REQUESTS", - "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15", - "Type": "1", - "Description": "Counts all requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ANY_RESPONSE", - "BitIndex": "16", - "Type": "2", - "Description": "have any response type.", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SUPPLIER_NONE", - "BitIndex": "17", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "BDM115" - }, - { - "BitName": "L3_HIT_M", - "BitIndex": "18", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "163,164,165,166,167,168,169,170,171", - "Errata": "na" - }, - { - "BitName": "L3_HIT_E", - "BitIndex": "19", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "163,164,165,166,167,168,169,170,171", - "Errata": "na" - }, - { - "BitName": "L3_HIT_S", - "BitIndex": "20", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "163,164,165,166,167,168,169,170,171", - "Errata": "na" - }, - { - "BitName": "L3_HIT_F", - "BitIndex": "21", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "163,164,165,166,167,168,169,170,171", - "Errata": "na" - }, - { - "BitName": "L3_HIT", - "BitIndex": "18,19,20,21", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_MISS_LOCAL_DRAM", - "BitIndex": "26", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "BDM115" - }, - { - "BitName": "L3_MISS", - "BitIndex": "26,27,28,29", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "169,170,171", - "Errata": "na" - }, - { - "BitName": "SNOOP_NONE", - "BitIndex": "31", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NOT_NEEDED", - "BitIndex": "32", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_MISS", - "BitIndex": "33", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_NO_FWD", - "BitIndex": "34", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_WITH_FWD", - "BitIndex": "35", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_HITM", - "BitIndex": "36", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NON_DRAM", - "BitIndex": "37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ANY_SNOOP", - "BitIndex": "31,32,33,34,35,36,37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - } -]
\ No newline at end of file diff --git a/usr/src/data/perfmon/BDW/broadwell_matrix_v23.json b/usr/src/data/perfmon/BDW/broadwell_matrix_v26.json index cf52fb5b6f..cf52fb5b6f 100644 --- a/usr/src/data/perfmon/BDW/broadwell_matrix_v23.json +++ b/usr/src/data/perfmon/BDW/broadwell_matrix_v26.json diff --git a/usr/src/data/perfmon/BDW/broadwell_uncore_v23.json b/usr/src/data/perfmon/BDW/broadwell_uncore_v26.json index 6dfc58adb9..7fc21796f9 100644 --- a/usr/src/data/perfmon/BDW/broadwell_uncore_v23.json +++ b/usr/src/data/perfmon/BDW/broadwell_uncore_v26.json @@ -192,7 +192,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x80", "UMask": "0x01", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", @@ -204,7 +204,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x80", "UMask": "0x02", "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT", @@ -216,7 +216,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x81", "UMask": "0x01", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", @@ -228,7 +228,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x81", "UMask": "0x02", "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", @@ -240,7 +240,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x81", "UMask": "0x20", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", @@ -252,7 +252,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x84", "UMask": "0x01", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", @@ -264,7 +264,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x80", "UMask": "0x01", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", diff --git a/usr/src/data/perfmon/BDX/broadwellx_core_v14.json b/usr/src/data/perfmon/BDX/broadwellx_core_v17.json index f31f70e5ff..3d002aa261 100644 --- a/usr/src/data/perfmon/BDX/broadwellx_core_v14.json +++ b/usr/src/data/perfmon/BDX/broadwellx_core_v17.json @@ -1111,7 +1111,7 @@ "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1134,7 +1134,7 @@ "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1157,7 +1157,7 @@ "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1180,7 +1180,7 @@ "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1203,7 +1203,7 @@ "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1226,7 +1226,7 @@ "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -4853,6 +4853,29 @@ "Offcore": "0" }, { + "EventCode": "0xb0", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "BriefDescription": "Any memory transaction that reached the SQ.", + "PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "ELLC": "0", + "Offcore": "0" + }, + { "EventCode": "0xB1", "UMask": "0x01", "EventName": "UOPS_EXECUTED.THREAD", @@ -5536,7 +5559,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "1", - "Data_LA": "1", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6049,11 +6072,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x01", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6072,11 +6095,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x02", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6095,11 +6118,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x03", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", - "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)", - "PublicDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6118,11 +6141,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x04", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6141,11 +6164,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x08", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6164,11 +6187,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x10", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6187,11 +6210,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", + "EventCode": "0xc7", "UMask": "0x15", "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", - "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000006", @@ -6213,8 +6236,8 @@ "EventCode": "0xc7", "UMask": "0x20", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6233,11 +6256,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", - "UMask": "0x2A", + "EventCode": "0xc7", + "UMask": "0x2a", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", - "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000005", @@ -6256,11 +6279,11 @@ "Offcore": "0" }, { - "EventCode": "0xC7", - "UMask": "0x3C", + "EventCode": "0xc7", + "UMask": "0x3c", "EventName": "FP_ARITH_INST_RETIRED.PACKED", - "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)", - "PublicDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)", + "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000004", @@ -6785,7 +6808,7 @@ "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "BriefDescription": "Randomly selected loads with latency value being above 4", @@ -6801,14 +6824,14 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "ELLC": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "BriefDescription": "Randomly selected loads with latency value being above 8", @@ -6824,14 +6847,14 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "ELLC": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "BriefDescription": "Randomly selected loads with latency value being above 16", @@ -6847,14 +6870,14 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "ELLC": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "BriefDescription": "Randomly selected loads with latency value being above 32", @@ -6870,14 +6893,14 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "ELLC": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "BriefDescription": "Randomly selected loads with latency value being above 64", @@ -6893,14 +6916,14 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "ELLC": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "BriefDescription": "Randomly selected loads with latency value being above 128", @@ -6916,14 +6939,14 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "ELLC": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "BriefDescription": "Randomly selected loads with latency value being above 256", @@ -6939,14 +6962,14 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "ELLC": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "BriefDescription": "Randomly selected loads with latency value being above 512", @@ -6962,7 +6985,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "BDM100, BDM35", "ELLC": "0", @@ -7938,8 +7961,8 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram ", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch)miss the L3 and the data is returned from local dram ", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch)miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", diff --git a/usr/src/data/perfmon/BDX/broadwellx_matrix_bit_definitions_v14.json b/usr/src/data/perfmon/BDX/broadwellx_matrix_bit_definitions_v14.json deleted file mode 100644 index 4db5d1a167..0000000000 --- a/usr/src/data/perfmon/BDX/broadwellx_matrix_bit_definitions_v14.json +++ /dev/null @@ -1,497 +0,0 @@ -[ - { - "BitName": "DEMAND_DATA_RD", - "BitIndex": "0", - "Type": "1", - "Description": "Counts demand data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "DEMAND_RFO", - "BitIndex": "1", - "Type": "1", - "Description": "Counts all demand data writes (RFOs)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "DEMAND_CODE_RD", - "BitIndex": "2", - "Type": "1", - "Description": "Counts all demand code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "COREWB", - "BitIndex": "3", - "Type": "1", - "Description": "Counts writebacks (modified to exclusive)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_DATA_RD", - "BitIndex": "4", - "Type": "1", - "Description": "Counts prefetch (that bring data to L2) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_RFO", - "BitIndex": "5", - "Type": "1", - "Description": "Counts all prefetch (that bring data to L2) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_CODE_RD", - "BitIndex": "6", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_DATA_RD", - "BitIndex": "7", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_RFO", - "BitIndex": "8", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_CODE_RD", - "BitIndex": "9", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SPLIT_LOCK_UC_LOCK", - "BitIndex": "10", - "Type": "1", - "Description": "Counts all locks that are either split across cache line boundaries or to uncacheable addresses", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "STREAMING_STORES", - "BitIndex": "11", - "Type": "1", - "Description": "Counts all non-temporal stores", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "OTHER", - "BitIndex": "15", - "Type": "1", - "Description": "Counts any other requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_DATA_RD", - "BitIndex": "4,7", - "Type": "1", - "Description": "Counts all prefetch data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_RFO", - "BitIndex": "5,8", - "Type": "1", - "Description": "Counts prefetch RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_CODE_RD", - "BitIndex": "6,9", - "Type": "1", - "Description": "Counts all prefetch code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_DATA_RD", - "BitIndex": "0,4,7", - "Type": "1", - "Description": "Counts all demand & prefetch data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_RFO", - "BitIndex": "1,5,8", - "Type": "1", - "Description": "Counts all demand & prefetch RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_CODE_RD", - "BitIndex": "2,6,9", - "Type": "1", - "Description": "Counts all demand & prefetch code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_READS", - "BitIndex": "0,1,2,4,5,6,7,8,9,10", - "Type": "1", - "Description": "Counts all data/code/rfo reads (demand & prefetch)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_REQUESTS", - "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15", - "Type": "1", - "Description": "Counts all requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ANY_RESPONSE", - "BitIndex": "16", - "Type": "2", - "Description": "have any response type.", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SUPPLIER_NONE", - "BitIndex": "17", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_HIT_M", - "BitIndex": "18", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_HIT_E", - "BitIndex": "19", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_HIT_S", - "BitIndex": "20", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_HIT_F", - "BitIndex": "21", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_HIT", - "BitIndex": "18,19,20,21", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_MISS_LOCAL_DRAM", - "BitIndex": "26", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_MISS_REMOTE_HOP0_DRAM", - "BitIndex": "27", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_MISS_REMOTE_HOP1_DRAM", - "BitIndex": "28", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_MISS_REMOTE_HOP2P_DRAM", - "BitIndex": "29", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_MISS", - "BitIndex": "26,27,28,29", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NONE", - "BitIndex": "31", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NOT_NEEDED", - "BitIndex": "32", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_MISS", - "BitIndex": "33", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_NO_FWD", - "BitIndex": "34", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_WITH_FWD", - "BitIndex": "35", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "18,19,20,21", - "Errata": "na" - }, - { - "BitName": "SNOOP_HITM", - "BitIndex": "36", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NON_DRAM", - "BitIndex": "37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ANY_SNOOP", - "BitIndex": "31,32,33,34,35,36,37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.ANY_RESPONSE", - "BitIndex": "18,19,20,21,31,32,33,34,35,36,37", - "Type": "2", - "Description": "hit in the L3", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.NO_SNOOP_NEEDED", - "BitIndex": "18,19,20,21,32", - "Type": "2", - "Description": "hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.SNOOP_MISS", - "BitIndex": "18,19,20,21,33", - "Type": "2", - "Description": "hit in the L3 and the snoops sent to sibling cores return clean response", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "BitIndex": "18,19,20,21,34", - "Type": "2", - "Description": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.HITM_OTHER_CORE", - "BitIndex": "18,19,20,21,36", - "Type": "2", - "Description": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.ANY_RESPONSE", - "BitIndex": "22,23,24,25,26,27,28,29,31,32,33,34,35,36,37", - "Type": "2", - "Description": "miss in the L3", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.LOCAL_DRAM", - "BitIndex": "26,33,34", - "Type": "2", - "Description": "miss the L3 and the data is returned from local dram", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.REMOTE_DRAM", - "BitIndex": "22,23,24,25,27,28,29,33,34", - "Type": "2", - "Description": "miss the L3 and the data is returned from remote dram", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.ANY_DRAM", - "BitIndex": "22,23,24,25,26,27,28,29,33,34", - "Type": "2", - "Description": "miss the L3 and the data is returned from local or remote dram", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.REMOTE_HITM", - "BitIndex": "22,23,24,25,26,27,28,29,36", - "Type": "2", - "Description": "miss the L3 and the modified data is transferred from remote cache", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.REMOTE_HIT_FORWARD", - "BitIndex": "22,23,24,25,26,27,28,29,30,35", - "Type": "2", - "Description": "miss the L3 and clean or shared data is transferred from remote cache", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_LLC_DATA_RD", - "BitIndex": "7", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_LLC_RFO", - "BitIndex": "8", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_LLC_CODE_RD", - "BitIndex": "9", - "Type": "1", - "Description": "Counts prefetch (that bring data to LLC only) code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - } -]
\ No newline at end of file diff --git a/usr/src/data/perfmon/BDX/broadwellx_matrix_v14.json b/usr/src/data/perfmon/BDX/broadwellx_matrix_v17.json index 0667a19153..0667a19153 100644 --- a/usr/src/data/perfmon/BDX/broadwellx_matrix_v14.json +++ b/usr/src/data/perfmon/BDX/broadwellx_matrix_v17.json diff --git a/usr/src/data/perfmon/BDX/broadwellx_uncore_v14.json b/usr/src/data/perfmon/BDX/broadwellx_uncore_v17.json index 9fa6affd0a..4ffc603aa9 100644 --- a/usr/src/data/perfmon/BDX/broadwellx_uncore_v14.json +++ b/usr/src/data/perfmon/BDX/broadwellx_uncore_v17.json @@ -8077,8 +8077,8 @@ "EventCode": "0x3", "UMask": "0x2", "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", - "BriefDescription": "CRC Errors Detected; Normal Operations", - "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.", + "BriefDescription": "tbd", + "PublicDescription": "tbd", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", diff --git a/usr/src/data/perfmon/CLX/cascadelakex_core_v1.00.json b/usr/src/data/perfmon/CLX/cascadelakex_core_v1.11.json index 6d5955770f..e1f0d83d48 100644 --- a/usr/src/data/perfmon/CLX/cascadelakex_core_v1.00.json +++ b/usr/src/data/perfmon/CLX/cascadelakex_core_v1.11.json @@ -99,8 +99,8 @@ "EventCode": "0x03", "UMask": "0x02", "EventName": "LD_BLOCKS.STORE_FORWARD", - "BriefDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded .", - "PublicDescription": "Counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations,c. preceding lock RMW operations are not forwarded,d. store has the no-forward bit set (uncacheable/page-split/masked stores),e. all-blocking stores are used (mostly, fences and port I/O), and others.The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide.", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -196,7 +196,7 @@ "UMask": "0x02", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "BriefDescription": "Page walk completed due to a demand data load to a 4K page", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -220,7 +220,7 @@ "UMask": "0x04", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -244,7 +244,7 @@ "UMask": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "BriefDescription": "Page walk completed due to a demand data load to a 1G page", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -265,10 +265,10 @@ }, { "EventCode": "0x08", - "UMask": "0x0E", + "UMask": "0x0e", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -360,30 +360,6 @@ "Deprecated": "0" }, { - "EventCode": "0x09", - "UMask": "0x01", - "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", - "BriefDescription": "tbd", - "PublicDescription": "tbd", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", - "MSRIndex": "0", - "MSRValue": "0", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "0", - "ELLC": "0", - "Offcore": "0", - "Deprecated": "0" - }, - { "EventCode": "0x0D", "UMask": "0x01", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -1540,7 +1516,7 @@ "UMask": "0x02", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "BriefDescription": "Page walk completed due to a demand data store to a 4K page", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1564,7 +1540,7 @@ "UMask": "0x04", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1588,7 +1564,7 @@ "UMask": "0x08", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "BriefDescription": "Page walk completed due to a demand data store to a 1G page", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1609,10 +1585,10 @@ }, { "EventCode": "0x49", - "UMask": "0x0E", + "UMask": "0x0e", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1728,7 +1704,7 @@ "Deprecated": "0" }, { - "EventCode": "0x4F", + "EventCode": "0x4f", "UMask": "0x10", "EventName": "EPT.WALK_PENDING", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", @@ -2860,7 +2836,7 @@ "UMask": "0x02", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", - "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2884,7 +2860,7 @@ "UMask": "0x04", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2908,7 +2884,7 @@ "UMask": "0x08", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", - "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2929,10 +2905,10 @@ }, { "EventCode": "0x85", - "UMask": "0x0E", + "UMask": "0x0e", "EventName": "ITLB_MISSES.WALK_COMPLETED", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -3865,6 +3841,30 @@ }, { "EventCode": "0xAB", + "UMask": "0x01", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "ELLC": "0", + "Offcore": "0", + "Deprecated": "0" + }, + { + "EventCode": "0xAB", "UMask": "0x02", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", @@ -4632,6 +4632,30 @@ "Deprecated": "0" }, { + "EventCode": "0xc2", + "UMask": "0x04", + "EventName": "UOPS_RETIRED.MACRO_FUSED", + "BriefDescription": "Number of macro-fused uops retired. (non precise)", + "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "ELLC": "0", + "Offcore": "0", + "Deprecated": "0" + }, + { "EventCode": "0xC3", "UMask": "0x01", "EventName": "MACHINE_CLEARS.COUNT", @@ -4848,6 +4872,30 @@ "Deprecated": "0" }, { + "EventCode": "0xc4", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "This event counts not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SKL091", + "ELLC": "0", + "Offcore": "0", + "Deprecated": "0" + }, + { "EventCode": "0xC4", "UMask": "0x20", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", @@ -5424,11 +5472,35 @@ "Deprecated": "0" }, { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x400106", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "ELLC": "0", + "Offcore": "0", + "Deprecated": "0" + }, + { "EventCode": "0xC7", "UMask": "0x01", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5451,8 +5523,8 @@ "EventCode": "0xC7", "UMask": "0x02", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5499,8 +5571,8 @@ "EventCode": "0xC7", "UMask": "0x08", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5523,8 +5595,8 @@ "EventCode": "0xC7", "UMask": "0x10", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5547,8 +5619,8 @@ "EventCode": "0xC7", "UMask": "0x20", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5571,8 +5643,8 @@ "EventCode": "0xC7", "UMask": "0x40", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5595,8 +5667,8 @@ "EventCode": "0xC7", "UMask": "0x80", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -6096,7 +6168,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", @@ -6112,7 +6184,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6120,7 +6192,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", @@ -6136,7 +6208,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6144,7 +6216,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", @@ -6160,7 +6232,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6168,7 +6240,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", @@ -6184,7 +6256,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6192,7 +6264,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", @@ -6208,7 +6280,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6216,7 +6288,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", @@ -6232,7 +6304,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6240,7 +6312,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", @@ -6256,7 +6328,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6264,7 +6336,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", @@ -6280,7 +6352,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -7299,7 +7371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7323,7 +7395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7347,7 +7419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7371,7 +7443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7395,7 +7467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7419,7 +7491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7443,7 +7515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7467,7 +7539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7491,7 +7563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7515,7 +7587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7539,7 +7611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7563,7 +7635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7587,7 +7659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7611,7 +7683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7635,7 +7707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7659,7 +7731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7683,7 +7755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7707,7 +7779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7731,7 +7803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7755,7 +7827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7779,7 +7851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7803,7 +7875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7827,7 +7899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7851,7 +7923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7875,7 +7947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7899,7 +7971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7923,7 +7995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7947,7 +8019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7971,7 +8043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -7995,7 +8067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8019,7 +8091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8043,7 +8115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8067,7 +8139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8091,7 +8163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8115,7 +8187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8139,7 +8211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8163,7 +8235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8187,7 +8259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8211,7 +8283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8235,7 +8307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8259,7 +8331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8283,7 +8355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8307,7 +8379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8331,7 +8403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8355,7 +8427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8379,7 +8451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8403,7 +8475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8427,7 +8499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8451,7 +8523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8475,7 +8547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8499,7 +8571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8523,7 +8595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8547,7 +8619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8571,7 +8643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8595,7 +8667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8619,7 +8691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8643,7 +8715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8667,7 +8739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8691,7 +8763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8715,7 +8787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8739,7 +8811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8763,7 +8835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8787,7 +8859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8811,7 +8883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8835,7 +8907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8859,7 +8931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8883,7 +8955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8907,7 +8979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8931,7 +9003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8955,7 +9027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -8979,7 +9051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9003,7 +9075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9027,7 +9099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9051,7 +9123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9075,7 +9147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9099,7 +9171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9123,7 +9195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9147,7 +9219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9171,7 +9243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9195,7 +9267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9219,7 +9291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9243,7 +9315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9267,7 +9339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9291,7 +9363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9315,7 +9387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9339,7 +9411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9363,7 +9435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9387,7 +9459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9411,7 +9483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9435,7 +9507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9459,7 +9531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9483,7 +9555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9507,7 +9579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9531,7 +9603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9555,7 +9627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9579,7 +9651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9603,7 +9675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9627,7 +9699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9651,7 +9723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9675,7 +9747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9699,7 +9771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9723,7 +9795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9747,7 +9819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9771,7 +9843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9795,7 +9867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9819,7 +9891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9843,7 +9915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9867,7 +9939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9891,7 +9963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9915,7 +9987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9939,7 +10011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9963,7 +10035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -9987,7 +10059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10011,7 +10083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10035,7 +10107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10059,7 +10131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10083,7 +10155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10107,7 +10179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10131,7 +10203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10155,7 +10227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10179,7 +10251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10203,7 +10275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10227,7 +10299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10251,7 +10323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10275,7 +10347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10299,7 +10371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10323,7 +10395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10347,7 +10419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10371,7 +10443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10395,7 +10467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10419,7 +10491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10443,7 +10515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10467,7 +10539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10491,7 +10563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10515,7 +10587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10539,7 +10611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10563,7 +10635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10587,7 +10659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10611,7 +10683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10635,7 +10707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10659,7 +10731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10683,7 +10755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10707,7 +10779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10731,7 +10803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10755,7 +10827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10779,7 +10851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10803,7 +10875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10827,7 +10899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10851,7 +10923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10875,7 +10947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10899,7 +10971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10923,7 +10995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10947,7 +11019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10971,7 +11043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -10995,7 +11067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11019,7 +11091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11043,7 +11115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11067,7 +11139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11091,7 +11163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11115,7 +11187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11139,7 +11211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11163,7 +11235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11187,7 +11259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11211,7 +11283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11235,7 +11307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11259,7 +11331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11283,7 +11355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11307,7 +11379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11331,7 +11403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11355,7 +11427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11379,7 +11451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11403,7 +11475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11427,7 +11499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11451,7 +11523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11475,7 +11547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11499,7 +11571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11523,7 +11595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11547,7 +11619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11571,7 +11643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11595,7 +11667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11619,7 +11691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11643,7 +11715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11667,7 +11739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11691,7 +11763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11715,7 +11787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11739,7 +11811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11763,7 +11835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11787,7 +11859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11811,7 +11883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11835,7 +11907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11859,7 +11931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11883,7 +11955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11907,7 +11979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11931,7 +12003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11955,7 +12027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -11979,7 +12051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12003,7 +12075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12027,7 +12099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12051,7 +12123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12075,7 +12147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12099,7 +12171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12123,7 +12195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12147,7 +12219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12171,7 +12243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12195,7 +12267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12219,7 +12291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12243,7 +12315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12267,7 +12339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12291,7 +12363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12315,7 +12387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12339,7 +12411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12363,7 +12435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12387,7 +12459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12411,7 +12483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12435,7 +12507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12459,7 +12531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12483,7 +12555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12507,7 +12579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12531,7 +12603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12555,7 +12627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12579,7 +12651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12603,7 +12675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12627,7 +12699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12651,7 +12723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12675,7 +12747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12699,7 +12771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12723,7 +12795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12747,7 +12819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12771,7 +12843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12795,7 +12867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12819,7 +12891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12843,7 +12915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12867,7 +12939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12891,7 +12963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12915,7 +12987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12939,7 +13011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12963,7 +13035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -12987,7 +13059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13011,7 +13083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13035,7 +13107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13059,7 +13131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13083,7 +13155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13107,7 +13179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13131,7 +13203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13155,7 +13227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13179,7 +13251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13203,7 +13275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13227,7 +13299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13251,7 +13323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13275,7 +13347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13299,7 +13371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13323,7 +13395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13347,7 +13419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13371,7 +13443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13395,7 +13467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13419,7 +13491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13443,7 +13515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13467,7 +13539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13491,7 +13563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13515,7 +13587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13539,7 +13611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13563,7 +13635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13587,7 +13659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13611,7 +13683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13635,7 +13707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13659,7 +13731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13683,7 +13755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13707,7 +13779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13731,7 +13803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13755,7 +13827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13779,7 +13851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13803,7 +13875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13827,7 +13899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13851,7 +13923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13875,7 +13947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13899,7 +13971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13923,7 +13995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13947,7 +14019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13971,7 +14043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -13995,7 +14067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14019,7 +14091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14043,7 +14115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14067,7 +14139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14091,7 +14163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14115,7 +14187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14139,7 +14211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14163,7 +14235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14187,7 +14259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14211,7 +14283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14235,7 +14307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14259,7 +14331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14283,7 +14355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14307,7 +14379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14331,7 +14403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14355,7 +14427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14379,7 +14451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14403,7 +14475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14427,7 +14499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14451,7 +14523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14475,7 +14547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14499,7 +14571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14523,7 +14595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14547,7 +14619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14571,7 +14643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14595,7 +14667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14619,7 +14691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14643,7 +14715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14667,7 +14739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14691,7 +14763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14715,7 +14787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14739,7 +14811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14763,7 +14835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14787,7 +14859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14811,7 +14883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14835,7 +14907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14859,7 +14931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14883,7 +14955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14907,7 +14979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14931,7 +15003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14955,7 +15027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -14979,7 +15051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15003,7 +15075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15027,7 +15099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15051,7 +15123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15075,7 +15147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15099,7 +15171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15123,7 +15195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15147,7 +15219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15171,7 +15243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15195,7 +15267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15219,7 +15291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15243,7 +15315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15267,7 +15339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15291,7 +15363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15315,7 +15387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15339,7 +15411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15363,7 +15435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15387,7 +15459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15411,7 +15483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15435,7 +15507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15459,7 +15531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15483,7 +15555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15507,7 +15579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15531,7 +15603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15555,7 +15627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15579,7 +15651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15603,7 +15675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15627,7 +15699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15651,7 +15723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15675,7 +15747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15699,7 +15771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15723,7 +15795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15747,7 +15819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15771,7 +15843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15795,7 +15867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15819,7 +15891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15843,7 +15915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15867,7 +15939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15891,7 +15963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15915,7 +15987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15939,7 +16011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15963,7 +16035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -15987,7 +16059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16011,7 +16083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16035,7 +16107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16059,7 +16131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16083,7 +16155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16107,7 +16179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16131,7 +16203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16155,7 +16227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16179,7 +16251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16203,7 +16275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16227,7 +16299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16251,7 +16323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16275,7 +16347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16299,7 +16371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16323,7 +16395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16347,7 +16419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16371,7 +16443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16395,7 +16467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16419,7 +16491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16443,7 +16515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16467,7 +16539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16491,7 +16563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16515,7 +16587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16539,7 +16611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16563,7 +16635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16587,7 +16659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16611,7 +16683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16635,7 +16707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16659,7 +16731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16683,7 +16755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16707,7 +16779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16731,7 +16803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16755,7 +16827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16779,7 +16851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16803,7 +16875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16827,7 +16899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16851,7 +16923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16875,7 +16947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16899,7 +16971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16923,7 +16995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16947,7 +17019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16971,7 +17043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -16995,7 +17067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17019,7 +17091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17043,7 +17115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17067,7 +17139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17091,7 +17163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17115,7 +17187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17139,7 +17211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17163,7 +17235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17187,7 +17259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17211,7 +17283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17235,7 +17307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17259,7 +17331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17283,7 +17355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17307,7 +17379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17331,7 +17403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17355,7 +17427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17379,7 +17451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17403,7 +17475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17427,7 +17499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17451,7 +17523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17475,7 +17547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17499,7 +17571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17523,7 +17595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17547,7 +17619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17571,7 +17643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17595,7 +17667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17619,7 +17691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17643,7 +17715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17667,7 +17739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17691,7 +17763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17715,7 +17787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17739,7 +17811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17763,7 +17835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17787,7 +17859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17811,7 +17883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17835,7 +17907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17859,7 +17931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17883,7 +17955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17907,7 +17979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17931,7 +18003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17955,7 +18027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -17979,7 +18051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18003,7 +18075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18027,7 +18099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18051,7 +18123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18075,7 +18147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18099,7 +18171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18123,7 +18195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18147,7 +18219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18171,7 +18243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18195,7 +18267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18219,7 +18291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18243,7 +18315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18267,7 +18339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18291,7 +18363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18315,7 +18387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18339,7 +18411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18363,7 +18435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18387,7 +18459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18411,7 +18483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18435,7 +18507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18459,7 +18531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18483,7 +18555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18507,7 +18579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18531,7 +18603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18555,7 +18627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18579,7 +18651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18603,7 +18675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18627,7 +18699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18651,7 +18723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18675,7 +18747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18699,7 +18771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18723,7 +18795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18747,7 +18819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18771,7 +18843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18795,7 +18867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18819,7 +18891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18843,7 +18915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18867,7 +18939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18891,7 +18963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18915,7 +18987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18939,7 +19011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18963,7 +19035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -18987,7 +19059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19011,7 +19083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19035,7 +19107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19059,7 +19131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19083,7 +19155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19107,7 +19179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19131,7 +19203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19155,7 +19227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19179,7 +19251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19203,7 +19275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19227,7 +19299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19251,7 +19323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19275,7 +19347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19299,7 +19371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19323,7 +19395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19347,7 +19419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19371,7 +19443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19395,7 +19467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19419,7 +19491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19443,7 +19515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19467,7 +19539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19491,7 +19563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19515,7 +19587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19539,7 +19611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19563,7 +19635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19587,7 +19659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19611,7 +19683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19635,7 +19707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19659,7 +19731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19683,7 +19755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19707,7 +19779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19731,7 +19803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19755,7 +19827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19779,7 +19851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19803,7 +19875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19827,7 +19899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19851,7 +19923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19875,7 +19947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19899,7 +19971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19923,7 +19995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19947,7 +20019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19971,7 +20043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -19995,7 +20067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20019,7 +20091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20043,7 +20115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20067,7 +20139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20091,7 +20163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20115,7 +20187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20139,7 +20211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20163,7 +20235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20187,7 +20259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20211,7 +20283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20235,7 +20307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20259,7 +20331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20283,7 +20355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20307,7 +20379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20331,7 +20403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20355,7 +20427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20379,7 +20451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20403,7 +20475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20427,7 +20499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20451,7 +20523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20475,7 +20547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20499,7 +20571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20523,7 +20595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20547,7 +20619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20571,7 +20643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20595,7 +20667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20619,7 +20691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20643,7 +20715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20667,7 +20739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20691,7 +20763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20715,7 +20787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20739,7 +20811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20763,7 +20835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20787,7 +20859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20811,7 +20883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20835,7 +20907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20859,7 +20931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20883,7 +20955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20907,7 +20979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20931,7 +21003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20955,7 +21027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -20979,7 +21051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21003,7 +21075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21027,7 +21099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21051,7 +21123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21075,7 +21147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21099,7 +21171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21123,7 +21195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21147,7 +21219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21171,7 +21243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21195,7 +21267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21219,7 +21291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21243,7 +21315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21267,7 +21339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21291,7 +21363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21315,7 +21387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21339,7 +21411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21363,7 +21435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21387,7 +21459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21411,7 +21483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21435,7 +21507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21459,7 +21531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21483,7 +21555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21507,7 +21579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21531,7 +21603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21555,7 +21627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21579,7 +21651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21603,7 +21675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21627,7 +21699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21651,7 +21723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21675,7 +21747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21699,7 +21771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21723,7 +21795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21747,7 +21819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21771,7 +21843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21795,7 +21867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21819,7 +21891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21843,7 +21915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21867,7 +21939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21891,7 +21963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21915,7 +21987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21939,7 +22011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21963,7 +22035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -21987,7 +22059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22011,7 +22083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22035,7 +22107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22059,7 +22131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22083,7 +22155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22107,7 +22179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22131,7 +22203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22155,7 +22227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22179,7 +22251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22203,7 +22275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22227,7 +22299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22251,7 +22323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22275,7 +22347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22299,7 +22371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22323,7 +22395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22347,7 +22419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22371,7 +22443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22395,7 +22467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22419,7 +22491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22443,7 +22515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22467,7 +22539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22491,7 +22563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22515,7 +22587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22539,7 +22611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22563,7 +22635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22587,7 +22659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22611,7 +22683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22635,7 +22707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22659,7 +22731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22683,7 +22755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22707,7 +22779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22731,7 +22803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22755,7 +22827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22779,7 +22851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22803,7 +22875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22827,7 +22899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22851,7 +22923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22875,7 +22947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22899,7 +22971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22923,7 +22995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22947,7 +23019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22971,7 +23043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -22995,7 +23067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23019,7 +23091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23043,7 +23115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23067,7 +23139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23091,7 +23163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23115,7 +23187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23139,7 +23211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23163,7 +23235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23187,7 +23259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23211,7 +23283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23235,7 +23307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23259,7 +23331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23283,7 +23355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23307,7 +23379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23331,7 +23403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23355,7 +23427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23379,7 +23451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23403,7 +23475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23427,7 +23499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23451,7 +23523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23475,7 +23547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23499,7 +23571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23523,7 +23595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23547,7 +23619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23571,7 +23643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23595,7 +23667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23619,7 +23691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23643,7 +23715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23667,7 +23739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23691,7 +23763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23715,7 +23787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23739,7 +23811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23763,7 +23835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23787,7 +23859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23811,7 +23883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23835,7 +23907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23859,7 +23931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23883,7 +23955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23907,7 +23979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23931,7 +24003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23955,7 +24027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -23979,7 +24051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24003,7 +24075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24027,7 +24099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24051,7 +24123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24075,7 +24147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24099,7 +24171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24123,7 +24195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24147,7 +24219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24171,7 +24243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24195,7 +24267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24219,7 +24291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24243,7 +24315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24267,7 +24339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24291,7 +24363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24315,7 +24387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24339,7 +24411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24363,7 +24435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24387,7 +24459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24411,7 +24483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24435,7 +24507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24459,7 +24531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24483,7 +24555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24507,7 +24579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24531,7 +24603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24555,7 +24627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24579,7 +24651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24603,7 +24675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24627,7 +24699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24651,7 +24723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24675,7 +24747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24699,7 +24771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24723,7 +24795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24747,7 +24819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24771,7 +24843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24795,7 +24867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24819,7 +24891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24843,7 +24915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24867,7 +24939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24891,7 +24963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24915,7 +24987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24939,7 +25011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24963,7 +25035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -24987,7 +25059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25011,7 +25083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25035,7 +25107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25059,7 +25131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25083,7 +25155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25107,7 +25179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25131,7 +25203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25155,7 +25227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25179,7 +25251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25203,7 +25275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25227,7 +25299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25251,7 +25323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25275,7 +25347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25299,7 +25371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25323,7 +25395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25347,7 +25419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25371,7 +25443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25395,7 +25467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25419,7 +25491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25443,7 +25515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25467,7 +25539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25491,7 +25563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25515,7 +25587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25539,7 +25611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25563,7 +25635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25587,7 +25659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25611,7 +25683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25635,7 +25707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25659,7 +25731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25683,7 +25755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25707,7 +25779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25731,7 +25803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25755,7 +25827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25779,7 +25851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25803,7 +25875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25827,7 +25899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25851,7 +25923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25875,7 +25947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25899,7 +25971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25923,7 +25995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25947,7 +26019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25971,7 +26043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -25995,7 +26067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26019,7 +26091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26043,7 +26115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26067,7 +26139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26091,7 +26163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26115,7 +26187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26139,7 +26211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26163,7 +26235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26187,7 +26259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26211,7 +26283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26235,7 +26307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26259,7 +26331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26283,7 +26355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26307,7 +26379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26331,7 +26403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26355,7 +26427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26379,7 +26451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26403,7 +26475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26427,7 +26499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26451,7 +26523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26475,7 +26547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26499,7 +26571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26523,7 +26595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26547,7 +26619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26571,7 +26643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26595,7 +26667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26619,7 +26691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26643,7 +26715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26667,7 +26739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26691,7 +26763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26715,7 +26787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26739,7 +26811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26763,7 +26835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26787,7 +26859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26811,7 +26883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26835,7 +26907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26859,7 +26931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26883,7 +26955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26907,7 +26979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26931,7 +27003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26955,7 +27027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -26979,7 +27051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27003,7 +27075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27027,7 +27099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27051,7 +27123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27075,7 +27147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27099,7 +27171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27123,7 +27195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_M.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27147,7 +27219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27171,7 +27243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_M.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27195,7 +27267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27219,7 +27291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27243,7 +27315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27267,7 +27339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_M.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27291,7 +27363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_E.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27315,7 +27387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27339,7 +27411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_E.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27363,7 +27435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27387,7 +27459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27411,7 +27483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27435,7 +27507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_E.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27459,7 +27531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_S.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27483,7 +27555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27507,7 +27579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_S.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27531,7 +27603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27555,7 +27627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27579,7 +27651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27603,7 +27675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_S.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27627,7 +27699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_F.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27651,7 +27723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27675,7 +27747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_F.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27699,7 +27771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27723,7 +27795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27747,7 +27819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27771,7 +27843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT_F.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27795,7 +27867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27819,7 +27891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27843,7 +27915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27867,7 +27939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27891,7 +27963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27915,7 +27987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27939,7 +28011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27963,7 +28035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -27987,7 +28059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28011,7 +28083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28035,7 +28107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28059,7 +28131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28083,7 +28155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28107,7 +28179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28131,7 +28203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28155,7 +28227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28179,7 +28251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28203,7 +28275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28227,7 +28299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28251,7 +28323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28275,7 +28347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28299,7 +28371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28323,7 +28395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28347,7 +28419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.SNOOP_MISS", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28371,7 +28443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28395,7 +28467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28419,7 +28491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28443,7 +28515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28467,7 +28539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28491,7 +28563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28515,7 +28587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28538,32 +28610,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28587,7 +28635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28611,7 +28659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28635,7 +28683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28658,32 +28706,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28707,7 +28731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28731,7 +28755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28755,7 +28779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28778,32 +28802,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28827,7 +28827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28851,7 +28851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28875,7 +28875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28898,32 +28898,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28947,7 +28923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28971,7 +28947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -28995,7 +28971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29018,32 +28994,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29067,7 +29019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29091,7 +29043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29115,7 +29067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29138,32 +29090,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29187,7 +29115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29211,7 +29139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29235,7 +29163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29258,32 +29186,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29307,7 +29211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29331,7 +29235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29355,7 +29259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29378,32 +29282,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29427,7 +29307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29451,7 +29331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29475,7 +29355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29498,32 +29378,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29547,7 +29403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29571,7 +29427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29595,7 +29451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29618,32 +29474,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0490", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29667,7 +29499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29691,7 +29523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29715,7 +29547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29738,32 +29570,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29787,7 +29595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29811,7 +29619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29835,7 +29643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29858,32 +29666,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0491", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29907,7 +29691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29931,7 +29715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29955,7 +29739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -29978,32 +29762,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30027,7 +29787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=ANY_RESPONSE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30051,7 +29811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30075,7 +29835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30098,32 +29858,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C07F7", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30147,7 +29883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30171,7 +29907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30195,7 +29931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30219,7 +29955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30243,7 +29979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30267,7 +30003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30291,7 +30027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30315,7 +30051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30339,7 +30075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30363,7 +30099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30387,7 +30123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30411,7 +30147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30435,7 +30171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30459,7 +30195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.REMOTE_HITM", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30483,7 +30219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30507,7 +30243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30531,7 +30267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30555,7 +30291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30579,7 +30315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30603,7 +30339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30627,7 +30363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30651,7 +30387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30675,7 +30411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30699,7 +30435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30723,7 +30459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30747,7 +30483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30771,7 +30507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30795,7 +30531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30819,7 +30555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30843,7 +30579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30867,7 +30603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30891,7 +30627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30915,7 +30651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30939,7 +30675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30963,7 +30699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -30987,7 +30723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31011,7 +30747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31035,7 +30771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31059,7 +30795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31083,7 +30819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31107,7 +30843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31131,7 +30867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31155,7 +30891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31179,7 +30915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31203,7 +30939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31227,7 +30963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31251,7 +30987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31275,7 +31011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31299,7 +31035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31323,7 +31059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31347,7 +31083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31371,7 +31107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31395,7 +31131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31419,7 +31155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31443,7 +31179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31467,7 +31203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31491,7 +31227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31515,7 +31251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31539,7 +31275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31563,7 +31299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31587,7 +31323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31611,7 +31347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31635,7 +31371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31659,7 +31395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31683,7 +31419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=OTHER:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31707,7 +31443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31731,7 +31467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31755,7 +31491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31779,7 +31515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31803,7 +31539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31851,7 +31587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31899,7 +31635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31923,7 +31659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31947,7 +31683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -31971,7 +31707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32019,7 +31755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32067,7 +31803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32091,7 +31827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32115,7 +31851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32139,7 +31875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32187,7 +31923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32235,7 +31971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32259,7 +31995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32283,7 +32019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32307,7 +32043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32355,7 +32091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32403,7 +32139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32427,7 +32163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32451,7 +32187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32475,7 +32211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32523,7 +32259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32571,7 +32307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32595,7 +32331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32619,7 +32355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32643,7 +32379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32667,7 +32403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32691,7 +32427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32715,7 +32451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32739,7 +32475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32763,7 +32499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32787,7 +32523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32811,7 +32547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32859,7 +32595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32907,7 +32643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32931,7 +32667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32955,7 +32691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -32979,7 +32715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33027,7 +32763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33075,7 +32811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33099,7 +32835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33123,7 +32859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33147,7 +32883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33171,7 +32907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33195,7 +32931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33219,7 +32955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33243,7 +32979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33267,7 +33003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33291,7 +33027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33315,7 +33051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33363,7 +33099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33411,7 +33147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33435,7 +33171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33459,7 +33195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33483,7 +33219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33531,7 +33267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33579,7 +33315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33603,7 +33339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33627,7 +33363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33651,7 +33387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33699,7 +33435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33747,7 +33483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33771,7 +33507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33795,7 +33531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33819,7 +33555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33867,7 +33603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33915,7 +33651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33939,7 +33675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33963,7 +33699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -33987,7 +33723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34035,7 +33771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34083,7 +33819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34107,7 +33843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34131,7 +33867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34155,7 +33891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34179,7 +33915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34203,7 +33939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34227,7 +33963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34251,7 +33987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34275,7 +34011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34299,7 +34035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34323,7 +34059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34371,7 +34107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34419,7 +34155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34443,7 +34179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34467,7 +34203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34491,7 +34227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34539,7 +34275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34587,7 +34323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34611,7 +34347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34635,7 +34371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34659,7 +34395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34683,7 +34419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34707,7 +34443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34731,7 +34467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34755,7 +34491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34779,7 +34515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34803,7 +34539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34827,7 +34563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34875,7 +34611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34923,7 +34659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34947,7 +34683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34971,7 +34707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -34995,7 +34731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35043,7 +34779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35091,7 +34827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35115,7 +34851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35139,7 +34875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35163,7 +34899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35211,7 +34947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35259,7 +34995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35283,7 +35019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35307,7 +35043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35331,7 +35067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35379,7 +35115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35427,7 +35163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35451,7 +35187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35475,7 +35211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35499,7 +35235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35547,7 +35283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35595,7 +35331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35619,7 +35355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35643,7 +35379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35667,7 +35403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35691,7 +35427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35715,7 +35451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35739,7 +35475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35763,7 +35499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35787,7 +35523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35811,7 +35547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35835,7 +35571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35883,7 +35619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35931,7 +35667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35955,7 +35691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -35979,7 +35715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36003,7 +35739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36051,7 +35787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36099,7 +35835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36123,7 +35859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36147,7 +35883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36171,7 +35907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36195,7 +35931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36219,7 +35955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36243,7 +35979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36267,7 +36003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36291,7 +36027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36315,7 +36051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36339,7 +36075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36387,7 +36123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36435,7 +36171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36459,7 +36195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36483,7 +36219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36507,7 +36243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36555,7 +36291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36603,7 +36339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36627,7 +36363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36651,7 +36387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36675,7 +36411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36723,7 +36459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36771,7 +36507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36795,7 +36531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36819,7 +36555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36843,7 +36579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36891,7 +36627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36939,7 +36675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36963,7 +36699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -36987,7 +36723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37011,7 +36747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37059,7 +36795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37107,7 +36843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37131,7 +36867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37155,7 +36891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37179,7 +36915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37203,7 +36939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37227,7 +36963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37251,7 +36987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37275,7 +37011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37299,7 +37035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37323,7 +37059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37347,7 +37083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37395,7 +37131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37443,7 +37179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37467,7 +37203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37491,7 +37227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37515,7 +37251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37563,7 +37299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37611,7 +37347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37635,7 +37371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37659,7 +37395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37683,7 +37419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37707,7 +37443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37731,7 +37467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37755,7 +37491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37779,7 +37515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37803,7 +37539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37827,7 +37563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37851,7 +37587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37899,7 +37635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37947,7 +37683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37971,7 +37707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -37995,7 +37731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38019,7 +37755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38067,7 +37803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38115,7 +37851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38139,7 +37875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38163,7 +37899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38187,7 +37923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38235,7 +37971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38283,7 +38019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38307,7 +38043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38331,7 +38067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38355,7 +38091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38403,7 +38139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38451,7 +38187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38475,7 +38211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38499,7 +38235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38523,7 +38259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38571,7 +38307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38619,7 +38355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38643,7 +38379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38667,7 +38403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38691,7 +38427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38715,7 +38451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38739,7 +38475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38763,7 +38499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38787,7 +38523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38811,7 +38547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38835,7 +38571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38859,7 +38595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38907,7 +38643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38955,7 +38691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -38979,7 +38715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39003,7 +38739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39027,7 +38763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39075,7 +38811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39123,7 +38859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39147,7 +38883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39171,7 +38907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39195,7 +38931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39219,7 +38955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39243,7 +38979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39267,7 +39003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39291,7 +39027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39315,7 +39051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39339,7 +39075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39363,7 +39099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39411,7 +39147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39459,7 +39195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39483,7 +39219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39507,7 +39243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39531,7 +39267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39579,7 +39315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39627,7 +39363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39651,7 +39387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39675,7 +39411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39699,7 +39435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39747,7 +39483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39795,7 +39531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39819,7 +39555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39843,7 +39579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39867,7 +39603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39915,7 +39651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39963,7 +39699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -39987,7 +39723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40011,7 +39747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40035,7 +39771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40083,7 +39819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40131,7 +39867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40155,7 +39891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40179,7 +39915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40203,7 +39939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40227,7 +39963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40251,7 +39987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40275,7 +40011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40299,7 +40035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40323,7 +40059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40347,7 +40083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40371,7 +40107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40419,7 +40155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40467,7 +40203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40491,7 +40227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40515,7 +40251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40539,7 +40275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40587,7 +40323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40635,7 +40371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40659,7 +40395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40683,7 +40419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40707,7 +40443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40731,7 +40467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40755,7 +40491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40779,7 +40515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40803,7 +40539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40827,7 +40563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40851,7 +40587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40875,7 +40611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40923,7 +40659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40971,7 +40707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -40995,7 +40731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41019,7 +40755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41043,7 +40779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41091,7 +40827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41139,7 +40875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41163,7 +40899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41187,7 +40923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41211,7 +40947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41259,7 +40995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41307,7 +41043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41331,7 +41067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41355,7 +41091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41379,7 +41115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41427,7 +41163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41475,7 +41211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41499,7 +41235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41523,7 +41259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41547,7 +41283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41595,7 +41331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41643,7 +41379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41667,7 +41403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41691,7 +41427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41715,7 +41451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41739,7 +41475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41763,7 +41499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41787,7 +41523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41811,7 +41547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41835,7 +41571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41859,7 +41595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41883,7 +41619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41931,7 +41667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -41979,7 +41715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42003,7 +41739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42027,7 +41763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42051,7 +41787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42099,7 +41835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42147,7 +41883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42171,7 +41907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42195,7 +41931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42219,7 +41955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42243,7 +41979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42267,7 +42003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42291,7 +42027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42315,7 +42051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42339,7 +42075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42363,7 +42099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42387,7 +42123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42435,7 +42171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42483,7 +42219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42507,7 +42243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42531,7 +42267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42555,7 +42291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42603,7 +42339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42651,7 +42387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42675,7 +42411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42699,7 +42435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42723,7 +42459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42771,7 +42507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42819,7 +42555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42843,7 +42579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42867,7 +42603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42891,7 +42627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42939,7 +42675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -42987,7 +42723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43011,7 +42747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43035,7 +42771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43059,7 +42795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43107,7 +42843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43155,7 +42891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43179,7 +42915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43203,7 +42939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43227,7 +42963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43251,7 +42987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43275,7 +43011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43299,7 +43035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43323,7 +43059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43347,7 +43083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43371,7 +43107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43395,7 +43131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43443,7 +43179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43491,7 +43227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43515,7 +43251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43539,7 +43275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43563,7 +43299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43611,7 +43347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43659,7 +43395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43683,7 +43419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43707,7 +43443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43731,7 +43467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43755,7 +43491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43779,7 +43515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43803,7 +43539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43827,7 +43563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43851,7 +43587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43875,7 +43611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43899,7 +43635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43947,7 +43683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -43995,7 +43731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44019,7 +43755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44043,7 +43779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44067,7 +43803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44115,7 +43851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44163,7 +43899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44187,7 +43923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44211,7 +43947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44235,7 +43971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44283,7 +44019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44331,7 +44067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44355,7 +44091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44379,7 +44115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44403,7 +44139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44451,7 +44187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44499,7 +44235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44523,7 +44259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44547,7 +44283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44571,7 +44307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44619,7 +44355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44667,7 +44403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44691,7 +44427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44715,7 +44451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44739,7 +44475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44763,7 +44499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44787,7 +44523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44811,7 +44547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44835,7 +44571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44859,7 +44595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44883,7 +44619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44907,7 +44643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -44955,7 +44691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45003,7 +44739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45027,7 +44763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45051,7 +44787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45075,7 +44811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45123,7 +44859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45171,7 +44907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45195,7 +44931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45219,7 +44955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45243,7 +44979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45267,7 +45003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45291,7 +45027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45315,7 +45051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45339,7 +45075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45363,7 +45099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45387,7 +45123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45411,7 +45147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45435,7 +45171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45459,7 +45195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45483,7 +45219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45507,7 +45243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45531,7 +45267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45555,7 +45291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45579,7 +45315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45603,7 +45339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45627,7 +45363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45651,7 +45387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45675,7 +45411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45699,7 +45435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45723,7 +45459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45747,7 +45483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45771,7 +45507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45795,7 +45531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45819,7 +45555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45843,7 +45579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45867,7 +45603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45891,7 +45627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45915,7 +45651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45939,7 +45675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45963,7 +45699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -45987,7 +45723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46011,7 +45747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46035,7 +45771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46059,7 +45795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46083,7 +45819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46107,7 +45843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46131,7 +45867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46155,7 +45891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46179,7 +45915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46203,7 +45939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46227,7 +45963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46251,7 +45987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46275,7 +46011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46299,7 +46035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46323,7 +46059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46347,7 +46083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46371,7 +46107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46395,7 +46131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46419,7 +46155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46443,7 +46179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46467,7 +46203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46491,7 +46227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46515,7 +46251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46539,7 +46275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46563,7 +46299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46587,7 +46323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46611,7 +46347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46635,7 +46371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46659,7 +46395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46683,7 +46419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46707,7 +46443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46731,7 +46467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46755,7 +46491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46779,7 +46515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46803,7 +46539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46827,7 +46563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46851,7 +46587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46875,7 +46611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46899,7 +46635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46923,7 +46659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46947,7 +46683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46971,7 +46707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -46995,7 +46731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47019,7 +46755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47043,7 +46779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47067,7 +46803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47091,7 +46827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47115,7 +46851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47139,7 +46875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47163,7 +46899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47187,7 +46923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47211,7 +46947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47235,7 +46971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47259,7 +46995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47283,7 +47019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47307,7 +47043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47331,7 +47067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47355,7 +47091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47379,7 +47115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47403,7 +47139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47427,7 +47163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47451,7 +47187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47475,7 +47211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47499,7 +47235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47523,7 +47259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47547,7 +47283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47571,7 +47307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47595,7 +47331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47619,7 +47355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47643,7 +47379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47667,7 +47403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47691,7 +47427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47715,7 +47451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47739,7 +47475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47763,7 +47499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47787,7 +47523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47811,7 +47547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47835,7 +47571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47859,7 +47595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47883,7 +47619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47907,7 +47643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47931,7 +47667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47955,7 +47691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -47979,7 +47715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48003,7 +47739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48027,7 +47763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48051,7 +47787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48075,7 +47811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48099,7 +47835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48123,7 +47859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48147,7 +47883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48171,7 +47907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48195,7 +47931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48219,7 +47955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48243,7 +47979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48267,7 +48003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48291,7 +48027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48315,7 +48051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48339,7 +48075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48363,7 +48099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48387,7 +48123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48411,7 +48147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48435,7 +48171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48459,7 +48195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48483,7 +48219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48507,7 +48243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48531,7 +48267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48555,7 +48291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48579,7 +48315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48603,7 +48339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48627,7 +48363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48651,7 +48387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48675,7 +48411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48699,7 +48435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48723,7 +48459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48747,7 +48483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48771,7 +48507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48795,7 +48531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48819,7 +48555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48843,7 +48579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48867,7 +48603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48891,7 +48627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48915,7 +48651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48939,7 +48675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48963,7 +48699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -48987,7 +48723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49011,7 +48747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49035,7 +48771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49059,7 +48795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49083,7 +48819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49107,7 +48843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49131,7 +48867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49155,7 +48891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49179,7 +48915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49203,7 +48939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49227,7 +48963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49251,7 +48987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49275,7 +49011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49299,7 +49035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49323,7 +49059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49347,7 +49083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49371,7 +49107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49395,7 +49131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49419,7 +49155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49443,7 +49179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49467,7 +49203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49491,7 +49227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49515,7 +49251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49539,7 +49275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49563,7 +49299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49587,7 +49323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49611,7 +49347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49635,7 +49371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49659,7 +49395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49683,7 +49419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49707,7 +49443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49731,7 +49467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49755,7 +49491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49779,7 +49515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49803,7 +49539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49827,7 +49563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49851,7 +49587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49875,7 +49611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49899,7 +49635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49923,7 +49659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49947,7 +49683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49971,7 +49707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -49995,7 +49731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50019,7 +49755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50043,7 +49779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50067,7 +49803,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50091,7 +49827,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50115,7 +49851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50139,7 +49875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50163,7 +49899,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50187,7 +49923,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50211,7 +49947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50235,7 +49971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50259,7 +49995,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50283,7 +50019,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50307,7 +50043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50331,7 +50067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50355,7 +50091,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50379,7 +50115,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50403,7 +50139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50427,7 +50163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50451,7 +50187,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50475,7 +50211,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50499,7 +50235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50523,7 +50259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50547,7 +50283,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50571,7 +50307,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50595,7 +50331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50619,7 +50355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50643,7 +50379,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50667,7 +50403,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50691,7 +50427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50715,7 +50451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50739,7 +50475,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50763,7 +50499,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50787,7 +50523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50811,7 +50547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50835,7 +50571,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50859,7 +50595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50883,7 +50619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50907,7 +50643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50931,7 +50667,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50955,7 +50691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -50979,7 +50715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51003,7 +50739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51027,7 +50763,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51051,7 +50787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51075,7 +50811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51099,7 +50835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51123,7 +50859,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51147,7 +50883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51171,7 +50907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51195,7 +50931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51219,7 +50955,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51243,7 +50979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51267,7 +51003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51291,7 +51027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51315,7 +51051,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51339,7 +51075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51363,7 +51099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51387,7 +51123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51411,7 +51147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51435,7 +51171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51459,7 +51195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51483,7 +51219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51507,7 +51243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51531,7 +51267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51555,7 +51291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51579,7 +51315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51603,7 +51339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51627,7 +51363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51651,7 +51387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51675,7 +51411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51699,7 +51435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51723,7 +51459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51747,7 +51483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51771,7 +51507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51795,7 +51531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51819,7 +51555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51843,7 +51579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51867,7 +51603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51891,7 +51627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51915,7 +51651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51939,7 +51675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51963,7 +51699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -51987,7 +51723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52011,7 +51747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52035,7 +51771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52059,7 +51795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52083,7 +51819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52107,7 +51843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52131,7 +51867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52155,7 +51891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52179,7 +51915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52203,7 +51939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52227,7 +51963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52251,7 +51987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52275,7 +52011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52299,7 +52035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52323,7 +52059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52347,7 +52083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52371,7 +52107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52395,7 +52131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52419,7 +52155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52443,7 +52179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52467,7 +52203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52491,7 +52227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52515,7 +52251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52539,7 +52275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52563,7 +52299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52587,7 +52323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52611,7 +52347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52635,7 +52371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52659,7 +52395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52683,7 +52419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52707,7 +52443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52731,7 +52467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52755,7 +52491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52779,7 +52515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52803,7 +52539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52827,7 +52563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52851,7 +52587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52875,7 +52611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52899,7 +52635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52923,7 +52659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52947,7 +52683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -52971,7 +52707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53019,7 +52755,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53043,7 +52779,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53066,30 +52802,6 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "Counts demand data reads", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -53139,7 +52851,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53163,7 +52875,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53186,30 +52898,6 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "Counts all demand data writes (RFOs)", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -53259,7 +52947,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53283,7 +52971,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53306,30 +52994,6 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand code reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "Counts all demand code reads", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -53379,7 +53043,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53403,7 +53067,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53426,30 +53090,6 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -53499,7 +53139,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53523,7 +53163,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53546,30 +53186,6 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -53619,7 +53235,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53643,7 +53259,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53666,30 +53282,6 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -53739,7 +53331,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53763,7 +53355,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53786,30 +53378,6 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -53859,7 +53427,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53883,7 +53451,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -53906,30 +53474,6 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -53979,7 +53523,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54003,7 +53547,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54026,30 +53570,6 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts any other requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "Counts any other requests", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -54075,7 +53595,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", - "BriefDescription": "TBD have any response type.", + "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54099,7 +53619,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54123,7 +53643,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54146,32 +53666,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0490", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54195,7 +53691,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", - "BriefDescription": "TBD have any response type.", + "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54219,7 +53715,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54243,7 +53739,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54266,32 +53762,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54315,7 +53787,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE", - "BriefDescription": "TBD have any response type.", + "BriefDescription": "OCR.ALL_DATA_RD.ANY_RESPONSE have any response type.", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54339,7 +53811,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54363,7 +53835,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54386,32 +53858,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0491", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54435,7 +53883,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.ANY_RESPONSE", - "BriefDescription": "TBD have any response type.", + "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54459,7 +53907,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54483,7 +53931,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54506,32 +53954,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54555,7 +53979,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.ANY_RESPONSE", - "BriefDescription": "TBD have any response type.", + "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54579,7 +54003,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54603,7 +54027,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54626,32 +54050,8 @@ { "EventCode": "0xB7, 0xBB", "UMask": "0x01", - "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C07F7", - "TakenAlone": "0", - "CounterMask": "0", - "Invert": "0", - "AnyThread": "0", - "EdgeDetect": "0", - "PEBS": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", - "Errata": "null", - "ELLC": "0", - "Offcore": "1", - "Deprecated": "0" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "TBD", + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54675,7 +54075,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54699,7 +54099,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54723,7 +54123,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54747,7 +54147,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54771,7 +54171,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54795,7 +54195,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54819,7 +54219,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54843,7 +54243,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54867,7 +54267,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54891,7 +54291,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54915,7 +54315,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54939,7 +54339,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54963,7 +54363,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -54987,7 +54387,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HITM", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITM", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55011,7 +54411,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55035,7 +54435,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55059,7 +54459,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55083,7 +54483,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55107,7 +54507,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55131,7 +54531,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55155,7 +54555,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55179,7 +54579,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55203,7 +54603,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55227,7 +54627,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55251,7 +54651,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55275,7 +54675,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55299,7 +54699,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55323,7 +54723,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55347,7 +54747,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55371,7 +54771,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55395,7 +54795,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55419,7 +54819,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55443,7 +54843,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55467,7 +54867,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55491,7 +54891,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55515,7 +54915,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55539,7 +54939,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55563,7 +54963,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55587,7 +54987,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55611,7 +55011,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55635,7 +55035,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55659,7 +55059,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55683,7 +55083,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55707,7 +55107,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55731,7 +55131,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55755,7 +55155,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55779,7 +55179,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55803,7 +55203,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55827,7 +55227,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55851,7 +55251,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55875,7 +55275,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55899,7 +55299,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55923,7 +55323,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55947,7 +55347,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55971,7 +55371,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -55995,7 +55395,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56019,7 +55419,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56043,7 +55443,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56067,7 +55467,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "Counts all demand code reads TBD", + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56091,7 +55491,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56115,7 +55515,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56139,7 +55539,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56163,7 +55563,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56187,7 +55587,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56211,7 +55611,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "Counts any other requests TBD", + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56235,7 +55635,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56259,7 +55659,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56283,7 +55683,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56307,7 +55707,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -56331,7 +55731,7 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", - "BriefDescription": "TBD TBD", + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", diff --git a/usr/src/data/perfmon/CLX/cascadelakex_fp_arith_inst_v1.00.json b/usr/src/data/perfmon/CLX/cascadelakex_fp_arith_inst_v1.11.json index 755a67d136..755a67d136 100644 --- a/usr/src/data/perfmon/CLX/cascadelakex_fp_arith_inst_v1.00.json +++ b/usr/src/data/perfmon/CLX/cascadelakex_fp_arith_inst_v1.11.json diff --git a/usr/src/data/perfmon/SKX/skylakex_uncore_v1.12.json b/usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.11.json index 502173b27c..d65182d29a 100644 --- a/usr/src/data/perfmon/SKX/skylakex_uncore_v1.12.json +++ b/usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.11.json @@ -1609,8 +1609,8 @@ "FCMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", - "BriefDescription": "tbd", - "PublicDescription": "tbd", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -1825,8 +1825,8 @@ "FCMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "BriefDescription": "tbd", - "PublicDescription": "tbd", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "Counter": "0", "MSRValue": "0x00", "ELLC": "0", @@ -3240,6 +3240,258 @@ "FILTER_VALUE": "0" }, { + "Unit": "IIO", + "EventCode": "0xC2", + "UMask": "0x03", + "PortMask": "0x01", + "FCMask": "0x4", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xC2", + "UMask": "0x03", + "PortMask": "0x02", + "FCMask": "0x4", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xC2", + "UMask": "0x03", + "PortMask": "0x04", + "FCMask": "0x4", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xC2", + "UMask": "0x03", + "PortMask": "0x08", + "FCMask": "0x4", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xD5", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", + "Counter": "2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xD5", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", + "Counter": "2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xD5", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", + "Counter": "2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xD5", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", + "Counter": "2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0xF", + "UMask": "0x4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "BriefDescription": "Total IRP occupancy of inbound read and write requests.", + "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x10", + "UMask": "0x8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", + "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x10", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", + "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x18", + "UMask": "0x0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", + "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x19", + "UMask": "0x0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_FAF_OCCUPANCY", + "BriefDescription": "Occupancy of the IRP FAF queue.", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x11", + "UMask": "0x8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { "Unit": "UPI LL", "EventCode": "0x1", "UMask": "0x0", @@ -3601,24 +3853,6 @@ }, { "Unit": "UPI LL", - "EventCode": "0x2", - "UMask": "0x8", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_UPI_TxL_FLITS.DATA", - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_DATA", - "PublicDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_DATA", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "1", - "FILTER_VALUE": "0" - }, - { - "Unit": "UPI LL", "EventCode": "0x12", "UMask": "0x2", "PortMask": "0x00", @@ -4248,6 +4482,96 @@ "FILTER_VALUE": "0" }, { + "Unit": "M2M", + "EventCode": "0x2C", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode", + "PublicDescription": "Tag Hit; Read Hit from NearMem, Dirty Line", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "M2M", + "EventCode": "0x2C", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", + "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode", + "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Clean Line", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "M2M", + "EventCode": "0x2C", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode", + "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Dirty Line", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "M2M", + "EventCode": "0x37", + "UMask": "0x8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M", + "PublicDescription": "M2M Reads Issued to iMC; All, regardless of priority.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "M2M", + "EventCode": "0x38", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M", + "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { "Unit": "M3UPI", "EventCode": "0x29", "UMask": "0x0", @@ -4257,7 +4581,7 @@ "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.", "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -4519,6 +4843,60 @@ }, { "Unit": "iMC", + "EventCode": "0xD3", + "UMask": "0x1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TAGCHK.HIT", + "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode", + "PublicDescription": "Tag Check; Hit", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xD3", + "UMask": "0x2", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TAGCHK.MISS_CLEAN", + "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode", + "PublicDescription": "Tag Check; Clean", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xD3", + "UMask": "0x4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TAGCHK.MISS_DIRTY", + "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode", + "PublicDescription": "Tag Check; Dirty", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", "EventCode": "0x20", "UMask": "0x0", "PortMask": "0x00", @@ -4552,5 +4930,149 @@ "ExtSel": "0", "Deprecated": "0", "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xE0", + "UMask": "0x1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", + "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory", + "PublicDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xE3", + "UMask": "0x0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_RPQ_INSERTS", + "BriefDescription": "Read requests allocated in the PMM Read Pending Queue for Intel Optane DC persistent memory", + "PublicDescription": "Read requests allocated in the PMM Read Pending Queue for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xEA", + "UMask": "0x1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_CMD1.ALL", + "BriefDescription": "All commands for Intel Optane DC persistent memory", + "PublicDescription": "All commands for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xEA", + "UMask": "0x2", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_CMD1.RD", + "BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory", + "PublicDescription": "All Reads - RPQ or Ufill", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xEA", + "UMask": "0x4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_CMD1.WR", + "BriefDescription": "Write commands for Intel Optane DC persistent memory", + "PublicDescription": "Writes", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xEA", + "UMask": "0x8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_CMD1.UFILL_RD", + "BriefDescription": "Underfill read commands for Intel Optane DC persistent memory", + "PublicDescription": "Underfill reads", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xE7", + "UMask": "0x0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_WPQ_INSERTS", + "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", + "PublicDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "iMC", + "EventCode": "0xE4", + "UMask": "0x1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", + "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", + "PublicDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" } ]
\ No newline at end of file diff --git a/usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.00_experimental.json b/usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.11_experimental.json index e0cca8da45..4cd57cfe84 100644 --- a/usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.00_experimental.json +++ b/usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.11_experimental.json @@ -19452,10 +19452,10 @@ "Counter": "0", "MSRValue": "0x00", "ELLC": "0", - "Filter": "CHAfilter1", + "Filter": "CHAFilter1[31:0]", "ExtSel": "0", "Deprecated": "0", - "FILTER_VALUE": "0" + "FILTER_VALUE": "" }, { "Unit": "CHA", @@ -19537,7 +19537,7 @@ "FCMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", - "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", + "BriefDescription": "TOR Occupancy; RDCUR isses from Local IO", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.", "Counter": "0", "MSRValue": "0x00", @@ -25237,24 +25237,6 @@ }, { "Unit": "IRP", - "EventCode": "0xF", - "UMask": "0x4", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", - "BriefDescription": "Total Write Cache Occupancy; Mem", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", "EventCode": "0x1", "UMask": "0x0", "PortMask": "0x00", @@ -25328,42 +25310,6 @@ { "Unit": "IRP", "EventCode": "0x10", - "UMask": "0x8", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_COHERENT_OPS.RFO", - "BriefDescription": "Coherent Ops; RFO", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", - "EventCode": "0x10", - "UMask": "0x10", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", - "BriefDescription": "Coherent Ops; PCIItoM", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", - "EventCode": "0x10", "UMask": "0x20", "PortMask": "0x00", "FCMask": "0x00", @@ -25435,42 +25381,6 @@ }, { "Unit": "IRP", - "EventCode": "0x18", - "UMask": "0x0", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_FAF_INSERTS", - "BriefDescription": "FAF - request insert from TC.", - "PublicDescription": "FAF - request insert from TC.", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", - "EventCode": "0x19", - "UMask": "0x0", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_FAF_OCCUPANCY", - "BriefDescription": "FAF occupancy", - "PublicDescription": "FAF occupancy", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", "EventCode": "0x16", "UMask": "0x0", "PortMask": "0x00", @@ -26156,24 +26066,6 @@ { "Unit": "IRP", "EventCode": "0x11", - "UMask": "0x8", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "BriefDescription": "Inbound Transaction Count; Write Prefetches", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", - "EventCode": "0x11", "UMask": "0x10", "PortMask": "0x00", "FCMask": "0x00", @@ -36405,7 +36297,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", "BriefDescription": "UPI0 AD Credits Empty; VNA", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36423,7 +36315,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36441,7 +36333,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36459,7 +36351,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36477,7 +36369,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36495,7 +36387,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36513,7 +36405,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36531,7 +36423,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", "BriefDescription": "UPI0 BL Credits Empty; VNA", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36549,7 +36441,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36567,7 +36459,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36585,7 +36477,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36603,7 +36495,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36621,7 +36513,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36639,7 +36531,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36729,7 +36621,7 @@ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", "BriefDescription": "CBox AD Credits Empty; VNA Messages", "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36747,7 +36639,7 @@ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", "BriefDescription": "CBox AD Credits Empty; Writebacks", "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36765,7 +36657,7 @@ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", "BriefDescription": "CBox AD Credits Empty; Requests", "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36783,7 +36675,7 @@ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", "BriefDescription": "CBox AD Credits Empty; Snoops", "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36801,7 +36693,7 @@ "EventName": "UNC_M3UPI_CLOCKTICKS", "BriefDescription": "Number of uclks in domain", "PublicDescription": "Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36819,7 +36711,7 @@ "EventName": "UNC_M3UPI_D2U_SENT", "BriefDescription": "D2U Sent", "PublicDescription": "Cases where SMI3 sends D2U command", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36837,7 +36729,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36855,7 +36747,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", "BriefDescription": "M2 BL Credits Empty; IIO2", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36873,7 +36765,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", "BriefDescription": "M2 BL Credits Empty; IIO3", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36891,7 +36783,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", "BriefDescription": "M2 BL Credits Empty; IIO4", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36909,7 +36801,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", "BriefDescription": "M2 BL Credits Empty; IIO5", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36927,7 +36819,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36945,7 +36837,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36963,7 +36855,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36981,7 +36873,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36999,7 +36891,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37017,7 +36909,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37035,7 +36927,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37053,7 +36945,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37071,7 +36963,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37089,7 +36981,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37107,7 +36999,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37125,7 +37017,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", "BriefDescription": "Failed ARB for AD; VN0 WB Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37143,7 +37035,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37161,7 +37053,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37179,7 +37071,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37197,7 +37089,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", "BriefDescription": "Failed ARB for AD; VN1 WB Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37215,7 +37107,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", "BriefDescription": "AD FlowQ Bypass", "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37233,7 +37125,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", "BriefDescription": "AD FlowQ Bypass", "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37251,7 +37143,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", "BriefDescription": "AD FlowQ Bypass", "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37269,7 +37161,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", "BriefDescription": "AD FlowQ Bypass", "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37287,7 +37179,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37305,7 +37197,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37323,7 +37215,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37341,7 +37233,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37359,7 +37251,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37377,7 +37269,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37395,7 +37287,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37413,7 +37305,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37431,7 +37323,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37449,7 +37341,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37467,7 +37359,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37485,7 +37377,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37503,7 +37395,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37521,7 +37413,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37539,7 +37431,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37683,7 +37575,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37701,7 +37593,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37719,7 +37611,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37737,7 +37629,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37755,7 +37647,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37773,7 +37665,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37791,7 +37683,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37809,7 +37701,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37827,7 +37719,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37845,7 +37737,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37863,7 +37755,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37881,7 +37773,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37899,7 +37791,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37917,7 +37809,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37935,7 +37827,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37953,7 +37845,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37971,7 +37863,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37989,7 +37881,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38007,7 +37899,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38025,7 +37917,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38043,7 +37935,7 @@ "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", "BriefDescription": "AK Flow Q Inserts", "PublicDescription": "AK Flow Q Inserts", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38079,7 +37971,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38097,7 +37989,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", "BriefDescription": "Failed ARB for BL; VN0 WB Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38115,7 +38007,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38133,7 +38025,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38151,7 +38043,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38169,7 +38061,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", "BriefDescription": "Failed ARB for BL; VN1 WB Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38187,7 +38079,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38205,7 +38097,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38223,7 +38115,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38241,7 +38133,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38259,7 +38151,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38277,7 +38169,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38295,7 +38187,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38313,7 +38205,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38331,7 +38223,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38349,7 +38241,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38367,7 +38259,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38385,7 +38277,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38403,7 +38295,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38421,7 +38313,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38439,7 +38331,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38457,7 +38349,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38475,7 +38367,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38493,7 +38385,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38655,7 +38547,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38673,7 +38565,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38691,7 +38583,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38709,7 +38601,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38727,7 +38619,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38745,7 +38637,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38763,7 +38655,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38781,7 +38673,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38799,7 +38691,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38817,7 +38709,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38835,7 +38727,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38853,7 +38745,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38871,7 +38763,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38889,7 +38781,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38907,7 +38799,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", "BriefDescription": "VN0 Credit Used; REQ on AD", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38925,7 +38817,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", "BriefDescription": "VN0 Credit Used; SNP on AD", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38943,7 +38835,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", "BriefDescription": "VN0 Credit Used; RSP on AD", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38961,7 +38853,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", "BriefDescription": "VN0 Credit Used; RSP on BL", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38979,7 +38871,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", "BriefDescription": "VN0 Credit Used; WB on BL", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38997,7 +38889,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", "BriefDescription": "VN0 Credit Used; NCB on BL", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39015,7 +38907,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", "BriefDescription": "VN0 No Credits; REQ on AD", "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39033,7 +38925,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", "BriefDescription": "VN0 No Credits; SNP on AD", "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39051,7 +38943,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", "BriefDescription": "VN0 No Credits; RSP on AD", "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39069,7 +38961,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", "BriefDescription": "VN0 No Credits; RSP on BL", "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39087,7 +38979,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", "BriefDescription": "VN0 No Credits; WB on BL", "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39105,7 +38997,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", "BriefDescription": "VN0 No Credits; NCB on BL", "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39123,7 +39015,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", "BriefDescription": "VN1 Credit Used; REQ on AD", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39141,7 +39033,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", "BriefDescription": "VN1 Credit Used; SNP on AD", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39159,7 +39051,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", "BriefDescription": "VN1 Credit Used; RSP on AD", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39177,7 +39069,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", "BriefDescription": "VN1 Credit Used; RSP on BL", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39195,7 +39087,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", "BriefDescription": "VN1 Credit Used; WB on BL", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39213,7 +39105,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", "BriefDescription": "VN1 Credit Used; NCB on BL", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39231,7 +39123,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", "BriefDescription": "VN1 No Credits; REQ on AD", "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39249,7 +39141,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", "BriefDescription": "VN1 No Credits; SNP on AD", "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39267,7 +39159,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", "BriefDescription": "VN1 No Credits; RSP on AD", "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39285,7 +39177,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", "BriefDescription": "VN1 No Credits; RSP on BL", "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39303,7 +39195,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", "BriefDescription": "VN1 No Credits; WB on BL", "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39321,7 +39213,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", "BriefDescription": "VN1 No Credits; NCB on BL", "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39411,7 +39303,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", "BriefDescription": "Snoop Arbitration; FlowQ Won", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39429,7 +39321,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", "BriefDescription": "Snoop Arbitration; FlowQ Won", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39447,7 +39339,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39465,7 +39357,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39483,7 +39375,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39501,7 +39393,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39519,7 +39411,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39537,7 +39429,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39555,7 +39447,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39573,7 +39465,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39591,7 +39483,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39609,7 +39501,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39627,7 +39519,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39645,7 +39537,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39663,7 +39555,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39681,7 +39573,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39699,7 +39591,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39717,7 +39609,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39735,7 +39627,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39753,7 +39645,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39771,7 +39663,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39789,7 +39681,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39807,7 +39699,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39825,7 +39717,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39843,7 +39735,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39861,7 +39753,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39879,7 +39771,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39897,7 +39789,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39915,7 +39807,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39933,7 +39825,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39951,7 +39843,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39969,7 +39861,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39987,7 +39879,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40005,7 +39897,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40023,7 +39915,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40041,7 +39933,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40059,7 +39951,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40077,7 +39969,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40095,7 +39987,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40113,7 +40005,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40239,7 +40131,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40257,7 +40149,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40275,7 +40167,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40293,7 +40185,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40311,7 +40203,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40329,7 +40221,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40347,7 +40239,7 @@ "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", "BriefDescription": "CMS Clockticks", "PublicDescription": "CMS Clockticks", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40365,7 +40257,7 @@ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", "BriefDescription": "Egress Blocking due to Ordering requirements; Up", "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40383,7 +40275,7 @@ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", "BriefDescription": "Egress Blocking due to Ordering requirements; Down", "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40401,7 +40293,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", "BriefDescription": "Horizontal AD Ring In Use; Left and Even", "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40419,7 +40311,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40437,7 +40329,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "BriefDescription": "Horizontal AD Ring In Use; Right and Even", "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40455,7 +40347,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40473,7 +40365,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", "BriefDescription": "Horizontal AK Ring In Use; Left and Even", "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40491,7 +40383,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40509,7 +40401,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "BriefDescription": "Horizontal AK Ring In Use; Right and Even", "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40527,7 +40419,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40545,7 +40437,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", "BriefDescription": "Horizontal BL Ring in Use; Left and Even", "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40563,7 +40455,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40581,7 +40473,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "BriefDescription": "Horizontal BL Ring in Use; Right and Even", "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40599,7 +40491,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40617,7 +40509,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", "BriefDescription": "Horizontal IV Ring in Use; Left", "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40635,7 +40527,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", "BriefDescription": "Horizontal IV Ring in Use; Right", "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40653,7 +40545,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40671,7 +40563,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40689,7 +40581,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40707,7 +40599,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40725,7 +40617,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40743,7 +40635,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40761,7 +40653,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40779,7 +40671,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40797,7 +40689,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", "BriefDescription": "Sink Starvation on Horizontal Ring; AD", "PublicDescription": "Sink Starvation on Horizontal Ring; AD", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40815,7 +40707,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", "BriefDescription": "Sink Starvation on Horizontal Ring; AK", "PublicDescription": "Sink Starvation on Horizontal Ring; AK", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40833,7 +40725,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", "BriefDescription": "Sink Starvation on Horizontal Ring; BL", "PublicDescription": "Sink Starvation on Horizontal Ring; BL", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40851,7 +40743,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", "BriefDescription": "Sink Starvation on Horizontal Ring; IV", "PublicDescription": "Sink Starvation on Horizontal Ring; IV", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40869,7 +40761,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", "PublicDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40887,7 +40779,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", "BriefDescription": "Sink Starvation on Vertical Ring; AD", "PublicDescription": "Sink Starvation on Vertical Ring; AD", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40905,7 +40797,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", "PublicDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40923,7 +40815,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", "PublicDescription": "Sink Starvation on Vertical Ring; Data Responses to core", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40941,7 +40833,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", "PublicDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40959,7 +40851,7 @@ "EventName": "UNC_M3UPI_RING_SRC_THRTL", "BriefDescription": "Source Throttle", "PublicDescription": "Source Throttle", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40977,7 +40869,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", "BriefDescription": "Lost Arb for VN0; REQ on AD", "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40995,7 +40887,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", "BriefDescription": "Lost Arb for VN0; SNP on AD", "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41013,7 +40905,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", "BriefDescription": "Lost Arb for VN0; RSP on AD", "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41031,7 +40923,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", "BriefDescription": "Lost Arb for VN0; RSP on BL", "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41049,7 +40941,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", "BriefDescription": "Lost Arb for VN0; WB on BL", "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41067,7 +40959,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", "BriefDescription": "Lost Arb for VN0; NCB on BL", "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41085,7 +40977,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", "BriefDescription": "Lost Arb for VN0; NCS on BL", "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41103,7 +40995,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", "BriefDescription": "Lost Arb for VN1; REQ on AD", "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41121,7 +41013,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", "BriefDescription": "Lost Arb for VN1; SNP on AD", "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41139,7 +41031,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", "BriefDescription": "Lost Arb for VN1; RSP on AD", "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41157,7 +41049,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", "BriefDescription": "Lost Arb for VN1; RSP on BL", "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41175,7 +41067,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", "BriefDescription": "Lost Arb for VN1; WB on BL", "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41193,7 +41085,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", "BriefDescription": "Lost Arb for VN1; NCB on BL", "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41211,7 +41103,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", "BriefDescription": "Lost Arb for VN1; NCS on BL", "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41229,7 +41121,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41247,7 +41139,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41265,7 +41157,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0", "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41283,7 +41175,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1", "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41301,7 +41193,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0", "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41319,7 +41211,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1", "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41337,7 +41229,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41355,7 +41247,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", "BriefDescription": "Can't Arb for VN0; REQ on AD", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41373,7 +41265,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", "BriefDescription": "Can't Arb for VN0; SNP on AD", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41391,7 +41283,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", "BriefDescription": "Can't Arb for VN0; RSP on AD", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41409,7 +41301,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", "BriefDescription": "Can't Arb for VN0; RSP on BL", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41427,7 +41319,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", "BriefDescription": "Can't Arb for VN0; WB on BL", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41445,7 +41337,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", "BriefDescription": "Can't Arb for VN0; NCB on BL", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41463,7 +41355,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", "BriefDescription": "Can't Arb for VN0; NCS on BL", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41481,7 +41373,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", "BriefDescription": "Can't Arb for VN1; REQ on AD", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41499,7 +41391,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", "BriefDescription": "Can't Arb for VN1; SNP on AD", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41517,7 +41409,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", "BriefDescription": "Can't Arb for VN1; RSP on AD", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41535,7 +41427,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", "BriefDescription": "Can't Arb for VN1; RSP on BL", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41553,7 +41445,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", "BriefDescription": "Can't Arb for VN1; WB on BL", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41571,7 +41463,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", "BriefDescription": "Can't Arb for VN1; NCB on BL", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41589,7 +41481,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", "BriefDescription": "Can't Arb for VN1; NCS on BL", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41607,7 +41499,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", "BriefDescription": "No Credits to Arb for VN0; REQ on AD", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41625,7 +41517,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", "BriefDescription": "No Credits to Arb for VN0; SNP on AD", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41643,7 +41535,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", "BriefDescription": "No Credits to Arb for VN0; RSP on AD", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41661,7 +41553,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", "BriefDescription": "No Credits to Arb for VN0; RSP on BL", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41679,7 +41571,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", "BriefDescription": "No Credits to Arb for VN0; WB on BL", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41697,7 +41589,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", "BriefDescription": "No Credits to Arb for VN0; NCB on BL", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41715,7 +41607,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", "BriefDescription": "No Credits to Arb for VN0; NCS on BL", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41733,7 +41625,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", "BriefDescription": "No Credits to Arb for VN1; REQ on AD", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41751,7 +41643,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", "BriefDescription": "No Credits to Arb for VN1; SNP on AD", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41769,7 +41661,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", "BriefDescription": "No Credits to Arb for VN1; RSP on AD", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41787,7 +41679,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", "BriefDescription": "No Credits to Arb for VN1; RSP on BL", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41805,7 +41697,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", "BriefDescription": "No Credits to Arb for VN1; WB on BL", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41823,7 +41715,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", "BriefDescription": "No Credits to Arb for VN1; NCB on BL", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41841,7 +41733,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", "BriefDescription": "No Credits to Arb for VN1; NCS on BL", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42183,7 +42075,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42201,7 +42093,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42219,7 +42111,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42237,7 +42129,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", "BriefDescription": "Credit Occupancy; VNA In Use", "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42255,7 +42147,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42273,7 +42165,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", "BriefDescription": "Credit Occupancy; Packets in BGF Path", "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42291,7 +42183,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", "BriefDescription": "Credit Occupancy; Transmit Credits", "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42309,7 +42201,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", "BriefDescription": "Credit Occupancy; D2K Credits", "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42327,7 +42219,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", "BriefDescription": "Credit Occupancy", "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42345,7 +42237,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", "BriefDescription": "Credit Occupancy", "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42363,7 +42255,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42381,7 +42273,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42399,7 +42291,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42417,7 +42309,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42435,7 +42327,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42453,7 +42345,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42471,7 +42363,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42489,7 +42381,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42507,7 +42399,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42525,7 +42417,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42543,7 +42435,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42561,7 +42453,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42579,7 +42471,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42597,7 +42489,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42615,7 +42507,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", "BriefDescription": "Data Flit Not Sent; All", "PublicDescription": "Data flit is ready for transmission but could not be sent", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42633,7 +42525,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", "BriefDescription": "Data Flit Not Sent; No BGF Credits", "PublicDescription": "Data flit is ready for transmission but could not be sent", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42651,7 +42543,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", "BriefDescription": "Data Flit Not Sent; No TxQ Credits", "PublicDescription": "Data flit is ready for transmission but could not be sent", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42669,7 +42561,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0", "PublicDescription": "generating bl data flit sequence; waiting for data pump 0", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42687,7 +42579,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1", "PublicDescription": "generating bl data flit sequence; waiting for data pump 1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42705,7 +42597,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42723,7 +42615,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "pump-1-pending logic is tracking at least one message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42741,7 +42633,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42759,7 +42651,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42777,7 +42669,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "pump-1-pending completion fifo is full", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42795,7 +42687,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_MISC", "BriefDescription": "tbd", "PublicDescription": "tbd", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42813,7 +42705,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", "BriefDescription": "Sent Header Flit; One Message", "PublicDescription": "One message in flit; VNA or non-VNA flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42831,7 +42723,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", "BriefDescription": "Sent Header Flit; Two Messages", "PublicDescription": "Two messages in flit; VNA flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42849,7 +42741,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", "BriefDescription": "Sent Header Flit; Three Messages", "PublicDescription": "Three messages in flit; VNA flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42867,7 +42759,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", "BriefDescription": "Sent Header Flit; One Message in non-VNA", "PublicDescription": "One message in flit; non-VNA flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42885,7 +42777,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", "BriefDescription": "Slotting BL Message Into Header Flit; All", "PublicDescription": "Slotting BL Message Into Header Flit; All", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42903,7 +42795,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit", "PublicDescription": "BL message requires data flit sequence", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42921,7 +42813,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0", "PublicDescription": "Waiting for header pump 0", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42939,7 +42831,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1", "PublicDescription": "Waiting for header pump 1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42957,7 +42849,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1", "PublicDescription": "Header pump 1 is not required for flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42975,7 +42867,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble", "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42993,7 +42885,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail", "PublicDescription": "Header pump 1 is not required for flit and not available", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43011,7 +42903,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", "BriefDescription": "Flit Gen - Header 1; Acumullate", "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43029,7 +42921,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43047,7 +42939,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43065,7 +42957,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43083,7 +42975,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43101,7 +42993,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", "BriefDescription": "Flit Gen - Header 1; Parallel Ok", "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43119,7 +43011,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", "BriefDescription": "Flit Gen - Header 1; Parallel Message", "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43137,7 +43029,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43155,7 +43047,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43173,7 +43065,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message", "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43191,7 +43083,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", "BriefDescription": "Header Not Sent; All", "PublicDescription": "header flit is ready for transmission but could not be sent", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43209,7 +43101,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", "BriefDescription": "Header Not Sent; No BGF Credits", "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43227,7 +43119,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", "BriefDescription": "Header Not Sent; No TxQ Credits", "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43245,7 +43137,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted", "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43263,7 +43155,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted", "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43281,7 +43173,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", "BriefDescription": "Header Not Sent; Sent - One Slot Taken", "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43299,7 +43191,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43317,7 +43209,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43479,7 +43371,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43497,7 +43389,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43515,7 +43407,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43533,7 +43425,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43551,7 +43443,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43569,7 +43461,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43587,7 +43479,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43605,7 +43497,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43623,7 +43515,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43641,7 +43533,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43659,7 +43551,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43677,7 +43569,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43695,7 +43587,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43713,7 +43605,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43731,7 +43623,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43749,7 +43641,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43767,7 +43659,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43785,7 +43677,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43803,7 +43695,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43821,7 +43713,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43839,7 +43731,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43857,7 +43749,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43875,7 +43767,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43893,7 +43785,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43911,7 +43803,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43929,7 +43821,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43947,7 +43839,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43965,7 +43857,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44235,7 +44127,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", "BriefDescription": "SMI3 Prefetch Messages; Arrived", "PublicDescription": "SMI3 Prefetch Messages; Arrived", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44253,7 +44145,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", "PublicDescription": "SMI3 Prefetch Messages; Lost Arbitration", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44271,7 +44163,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", "BriefDescription": "SMI3 Prefetch Messages; Slotted", "PublicDescription": "SMI3 Prefetch Messages; Slotted", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44289,7 +44181,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", "PublicDescription": "SMI3 Prefetch Messages; Dropped - Old", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44307,7 +44199,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44325,7 +44217,7 @@ "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", "BriefDescription": "Remote VNA Credits; Used", "PublicDescription": "Number of remote vna credits consumed per cycle", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44343,7 +44235,7 @@ "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", "BriefDescription": "Remote VNA Credits; Corrected", "PublicDescription": "Number of remote vna credits corrected (local return) per cycle", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44361,7 +44253,7 @@ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", "BriefDescription": "Remote VNA Credits; Level < 1", "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44379,7 +44271,7 @@ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", "BriefDescription": "Remote VNA Credits; Level < 4", "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44397,7 +44289,7 @@ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", "BriefDescription": "Remote VNA Credits; Level < 5", "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44415,7 +44307,7 @@ "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", "BriefDescription": "Remote VNA Credits; Any In Use", "PublicDescription": "At least one remote vna credit is in use", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44433,7 +44325,7 @@ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", "BriefDescription": "Transgress Injection Starvation; AD - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44451,7 +44343,7 @@ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", "BriefDescription": "Transgress Injection Starvation; BL - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44469,7 +44361,7 @@ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", "BriefDescription": "Transgress Injection Starvation; AD - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44487,7 +44379,7 @@ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", "BriefDescription": "Transgress Injection Starvation; BL - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44505,7 +44397,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44523,7 +44415,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44541,7 +44433,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44559,7 +44451,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44577,7 +44469,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", "BriefDescription": "Transgress Ingress Bypass; AD - Credit", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44595,7 +44487,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", "BriefDescription": "Transgress Ingress Bypass; BL - Credit", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44613,7 +44505,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", "BriefDescription": "Transgress Injection Starvation; AD - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44631,7 +44523,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", "BriefDescription": "Transgress Injection Starvation; AK - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44649,7 +44541,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", "BriefDescription": "Transgress Injection Starvation; BL - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44667,7 +44559,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", "BriefDescription": "Transgress Injection Starvation; IV - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44685,7 +44577,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", "BriefDescription": "Transgress Injection Starvation; AD - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44703,7 +44595,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", "BriefDescription": "Transgress Injection Starvation; BL - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44721,7 +44613,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", "BriefDescription": "Transgress Injection Starvation; IFV - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44739,7 +44631,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44757,7 +44649,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44775,7 +44667,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44793,7 +44685,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44811,7 +44703,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", "BriefDescription": "Transgress Ingress Allocations; AD - Credit", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44829,7 +44721,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", "BriefDescription": "Transgress Ingress Allocations; BL - Credit", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44847,7 +44739,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44865,7 +44757,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44883,7 +44775,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44901,7 +44793,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44919,7 +44811,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44937,7 +44829,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44955,7 +44847,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44973,7 +44865,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44991,7 +44883,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45009,7 +44901,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45027,7 +44919,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45045,7 +44937,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45063,7 +44955,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45081,7 +44973,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45099,7 +44991,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45117,7 +45009,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45135,7 +45027,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45153,7 +45045,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45171,7 +45063,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45189,7 +45081,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45207,7 +45099,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45225,7 +45117,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45243,7 +45135,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45261,7 +45153,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45279,7 +45171,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45297,7 +45189,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45315,7 +45207,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45333,7 +45225,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45351,7 +45243,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45369,7 +45261,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45387,7 +45279,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45405,7 +45297,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45423,7 +45315,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45441,7 +45333,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45459,7 +45351,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45477,7 +45369,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45495,7 +45387,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45513,7 +45405,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45531,7 +45423,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45549,7 +45441,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45567,7 +45459,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45585,7 +45477,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45603,7 +45495,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45621,7 +45513,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45639,7 +45531,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45657,7 +45549,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45675,7 +45567,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45693,7 +45585,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45711,7 +45603,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45729,7 +45621,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45747,7 +45639,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45765,7 +45657,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45783,7 +45675,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45801,7 +45693,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45819,7 +45711,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45837,7 +45729,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45855,7 +45747,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45873,7 +45765,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45891,7 +45783,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45909,7 +45801,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45927,7 +45819,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45945,7 +45837,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45963,7 +45855,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45981,7 +45873,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45999,7 +45891,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46017,7 +45909,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46035,7 +45927,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46053,7 +45945,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46071,7 +45963,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46089,7 +45981,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46107,7 +45999,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46125,7 +46017,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46143,7 +46035,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46161,7 +46053,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46179,7 +46071,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46197,7 +46089,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46215,7 +46107,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46233,7 +46125,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46251,7 +46143,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46269,7 +46161,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46287,7 +46179,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46305,7 +46197,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46323,7 +46215,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46341,7 +46233,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46359,7 +46251,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", "BriefDescription": "CMS Vertical ADS Used; IV", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46377,7 +46269,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46395,7 +46287,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46413,7 +46305,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46431,7 +46323,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46449,7 +46341,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46467,7 +46359,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46485,7 +46377,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46503,7 +46395,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46521,7 +46413,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46539,7 +46431,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transfering writeback data to the cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46557,7 +46449,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46575,7 +46467,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46593,7 +46485,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46611,7 +46503,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46629,7 +46521,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46647,7 +46539,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46665,7 +46557,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transfering writeback data to the cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46683,7 +46575,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46701,7 +46593,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46719,7 +46611,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46737,7 +46629,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", "BriefDescription": "CMS Vert Egress Allocations; IV", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46755,7 +46647,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46773,7 +46665,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46791,7 +46683,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transfering writeback data to the cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46809,7 +46701,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46827,7 +46719,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46845,7 +46737,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46863,7 +46755,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46881,7 +46773,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46899,7 +46791,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46917,7 +46809,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46935,7 +46827,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46953,7 +46845,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46971,7 +46863,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", "BriefDescription": "CMS Vert Egress Occupancy; IV", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46989,7 +46881,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47007,7 +46899,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47025,7 +46917,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transfering writeback data to the cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47043,7 +46935,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47061,7 +46953,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47079,7 +46971,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47097,7 +46989,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47115,7 +47007,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47133,7 +47025,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47151,7 +47043,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", "BriefDescription": "Vertical AD Ring In Use; Up and Even", "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47169,7 +47061,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", "BriefDescription": "Vertical AD Ring In Use; Up and Odd", "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47187,7 +47079,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", "BriefDescription": "Vertical AD Ring In Use; Down and Even", "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47205,7 +47097,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", "BriefDescription": "Vertical AD Ring In Use; Down and Odd", "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47223,7 +47115,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", "BriefDescription": "Vertical AK Ring In Use; Up and Even", "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47241,7 +47133,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", "BriefDescription": "Vertical AK Ring In Use; Up and Odd", "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47259,7 +47151,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", "BriefDescription": "Vertical AK Ring In Use; Down and Even", "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47277,7 +47169,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", "BriefDescription": "Vertical AK Ring In Use; Down and Odd", "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47295,7 +47187,7 @@ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", "BriefDescription": "Vertical BL Ring in Use; Up and Even", "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47313,7 +47205,7 @@ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", "BriefDescription": "Vertical BL Ring in Use; Up and Odd", "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47331,7 +47223,7 @@ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", "BriefDescription": "Vertical BL Ring in Use; Down and Even", "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47349,7 +47241,7 @@ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", "BriefDescription": "Vertical BL Ring in Use; Down and Odd", "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47367,7 +47259,7 @@ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", "BriefDescription": "Vertical IV Ring in Use; Up", "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47385,7 +47277,7 @@ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", "BriefDescription": "Vertical IV Ring in Use; Down", "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47403,7 +47295,7 @@ "EventName": "UNC_M3UPI_D2C_SENT", "BriefDescription": "D2C Sent", "PublicDescription": "Count cases BL sends direct to core", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47421,7 +47313,7 @@ "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", "BriefDescription": "FaST wire asserted; Vertical", "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47439,7 +47331,7 @@ "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", "BriefDescription": "FaST wire asserted; Horizontal", "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47457,7 +47349,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", "BriefDescription": "Sent Header Flit", "PublicDescription": "Sent Header Flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47475,7 +47367,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", "BriefDescription": "Sent Header Flit", "PublicDescription": "Sent Header Flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47493,7 +47385,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", "BriefDescription": "Sent Header Flit", "PublicDescription": "Sent Header Flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47511,7 +47403,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", "BriefDescription": "CMS Vertical Egress NACKs; IV", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47529,7 +47421,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47547,7 +47439,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", "BriefDescription": "UPI0 BL Credits Empty; VNA", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47565,7 +47457,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47583,7 +47475,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47601,7 +47493,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47619,7 +47511,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47637,7 +47529,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", diff --git a/usr/src/data/perfmon/HSW/haswell_core_v28.json b/usr/src/data/perfmon/HSW/haswell_core_v30.json index dff834cb8d..8b9aa9733d 100644 --- a/usr/src/data/perfmon/HSW/haswell_core_v28.json +++ b/usr/src/data/perfmon/HSW/haswell_core_v30.json @@ -634,7 +634,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "Offcore": "0" }, { @@ -700,7 +700,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "Offcore": "0" }, { @@ -727,7 +727,7 @@ }, { "EventCode": "0x24", - "UMask": "0x3F", + "UMask": "0x3f", "EventName": "L2_RQSTS.MISS", "BriefDescription": "All requests that miss L2 cache", "PublicDescription": "All requests that missed L2.", @@ -744,7 +744,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "Offcore": "0" }, { @@ -766,7 +766,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "Offcore": "0" }, { @@ -837,7 +837,7 @@ }, { "EventCode": "0x24", - "UMask": "0xE1", + "UMask": "0xe1", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "BriefDescription": "Demand Data Read requests", "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", @@ -854,7 +854,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "Offcore": "0" }, { @@ -920,7 +920,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "Offcore": "0" }, { @@ -947,7 +947,7 @@ }, { "EventCode": "0x24", - "UMask": "0xFF", + "UMask": "0xff", "EventName": "L2_RQSTS.REFERENCES", "BriefDescription": "All L2 requests", "PublicDescription": "All requests to L2 cache.", @@ -964,7 +964,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "Offcore": "0" }, { @@ -1085,7 +1085,7 @@ "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1107,7 +1107,7 @@ "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1129,7 +1129,7 @@ "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1151,7 +1151,7 @@ "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1173,7 +1173,7 @@ "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1195,7 +1195,7 @@ "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -2108,7 +2108,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78, HSD62, HSD61", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "Offcore": "0" }, { @@ -2130,7 +2130,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78, HSD62, HSD61", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "Offcore": "0" }, { @@ -2152,7 +2152,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78, HSD62, HSD61", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "Offcore": "0" }, { @@ -2174,7 +2174,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "Offcore": "0" }, { @@ -2196,7 +2196,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "Offcore": "0" }, { @@ -2218,7 +2218,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "Offcore": "0" }, { @@ -2240,7 +2240,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "Offcore": "0" }, { @@ -2262,7 +2262,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "Offcore": "0" }, { @@ -4224,7 +4224,7 @@ "Offcore": "0" }, { - "EventCode": "0xA3", + "EventCode": "0xa3", "UMask": "0x01", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", "BriefDescription": "Cycles with pending L2 cache miss loads.", @@ -4242,7 +4242,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM63, HSM80", "Offcore": "0" }, { @@ -4290,7 +4290,7 @@ "Offcore": "0" }, { - "EventCode": "0xA3", + "EventCode": "0xa3", "UMask": "0x05", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", "BriefDescription": "Execution stalls due to L2 cache misses.", @@ -4308,7 +4308,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "0", + "Errata": "HSM63, HSM80", "Offcore": "0" }, { @@ -4488,7 +4488,7 @@ "Offcore": "0" }, { - "EventCode": "0xB0", + "EventCode": "0xb0", "UMask": "0x01", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "BriefDescription": "Demand Data Read requests sent to uncore", @@ -4506,7 +4506,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "Offcore": "0" }, { @@ -5306,7 +5306,7 @@ "UMask": "0x02", "EventName": "INST_RETIRED.X87", "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5317,7 +5317,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5327,8 +5327,8 @@ "EventCode": "0xC1", "UMask": "0x08", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable", - "PublicDescription": "", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "PublicDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -5339,7 +5339,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "HSD56, HSM57", @@ -5349,8 +5349,8 @@ "EventCode": "0xC1", "UMask": "0x10", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "BriefDescription": "Number of transitions from legacy SSE to AVX-256 when penalty applicable ", - "PublicDescription": "", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "PublicDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -5361,7 +5361,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "HSD56, HSM57", @@ -5371,8 +5371,8 @@ "EventCode": "0xC1", "UMask": "0x40", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "BriefDescription": "tbd", - "PublicDescription": "", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -5383,7 +5383,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5394,7 +5394,7 @@ "UMask": "0x01", "EventName": "UOPS_RETIRED.ALL", "BriefDescription": "Actually retired uops.", - "PublicDescription": "Actually retired uops.", + "PublicDescription": "Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5406,7 +5406,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "1", - "Data_LA": "1", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" @@ -5415,8 +5415,8 @@ "EventCode": "0xC2", "UMask": "0x01", "EventName": "UOPS_RETIRED.STALL_CYCLES", - "BriefDescription": "Cycles no executable uops retired", - "PublicDescription": "", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5427,7 +5427,7 @@ "Invert": "1", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5437,8 +5437,8 @@ "EventCode": "0xC2", "UMask": "0x01", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "BriefDescription": "Number of cycles using always true condition applied to PEBS uops retired event.", - "PublicDescription": "", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "PublicDescription": "Cycles with less than 10 actually retired uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5449,7 +5449,7 @@ "Invert": "1", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5459,8 +5459,8 @@ "EventCode": "0xC2", "UMask": "0x01", "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", - "BriefDescription": "Cycles no executable uops retired on core", - "PublicDescription": "", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5471,7 +5471,7 @@ "Invert": "1", "AnyThread": "1", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5482,7 +5482,7 @@ "UMask": "0x02", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "BriefDescription": "Retirement slots used.", - "PublicDescription": "Retirement slots used.", + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5636,7 +5636,7 @@ "UMask": "0x01", "EventName": "BR_INST_RETIRED.CONDITIONAL", "BriefDescription": "Conditional branch instructions retired.", - "PublicDescription": "Conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -5724,7 +5724,7 @@ "UMask": "0x08", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "BriefDescription": "Return instructions retired.", - "PublicDescription": "Return instructions retired.", + "PublicDescription": "Counts the number of near return instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -5745,8 +5745,8 @@ "EventCode": "0xC4", "UMask": "0x10", "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "BriefDescription": "Counts all not taken macro branch instructions retired.", - "PublicDescription": "", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "Counts the number of not taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -5757,7 +5757,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5768,7 +5768,7 @@ "UMask": "0x20", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "BriefDescription": "Taken branch instructions retired.", - "PublicDescription": "Taken branch instructions retired.", + "PublicDescription": "Number of near taken branches retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -5789,8 +5789,8 @@ "EventCode": "0xC4", "UMask": "0x40", "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "BriefDescription": "Counts the number of far branch instructions retired.", - "PublicDescription": "", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "Number of far branches retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -5801,7 +5801,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -5855,7 +5855,7 @@ "EventCode": "0xC5", "UMask": "0x04", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "BriefDescription": "Mispredicted macro branch instructions retired. ", + "BriefDescription": "Mispredicted macro branch instructions retired.", "PublicDescription": "This event counts all mispredicted branch instructions retired. This is a precise event.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -5878,7 +5878,7 @@ "UMask": "0x20", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", - "PublicDescription": "number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Number of near branch instructions retired that were taken but mispredicted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -6273,8 +6273,8 @@ "EventCode": "0xCA", "UMask": "0x02", "EventName": "FP_ASSIST.X87_OUTPUT", - "BriefDescription": "output - Numeric Overflow, Numeric Underflow, Inexact Result ", - "PublicDescription": "", + "BriefDescription": "Number of X87 assists due to output value.", + "PublicDescription": "Number of X87 FP assists due to output values.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -6285,7 +6285,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6295,8 +6295,8 @@ "EventCode": "0xCA", "UMask": "0x04", "EventName": "FP_ASSIST.X87_INPUT", - "BriefDescription": "input - Invalid Operation, Denormal Operand, SNaN Operand ", - "PublicDescription": "", + "BriefDescription": "Number of X87 assists due to input value.", + "PublicDescription": "Number of X87 FP assists due to input values.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -6307,7 +6307,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6317,8 +6317,8 @@ "EventCode": "0xCA", "UMask": "0x08", "EventName": "FP_ASSIST.SIMD_OUTPUT", - "BriefDescription": "SSE* FP micro-code assist when output value is invalid. ", - "PublicDescription": "", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "PublicDescription": "Number of SIMD FP assists due to output values.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -6329,7 +6329,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6339,8 +6339,8 @@ "EventCode": "0xCA", "UMask": "0x10", "EventName": "FP_ASSIST.SIMD_INPUT", - "BriefDescription": "Any input SSE* FP Assist ", - "PublicDescription": "", + "BriefDescription": "Number of SIMD FP assists due to input values", + "PublicDescription": "Number of SIMD FP assists due to input values.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -6351,7 +6351,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6361,8 +6361,8 @@ "EventCode": "0xCA", "UMask": "0x1E", "EventName": "FP_ASSIST.ANY", - "BriefDescription": "Counts any FP_ASSIST umask was incrementing ", - "PublicDescription": "", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6373,7 +6373,7 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", @@ -6402,7 +6402,7 @@ "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "BriefDescription": "Randomly selected loads with latency value being above 4.", @@ -6418,13 +6418,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "BriefDescription": "Randomly selected loads with latency value being above 8.", @@ -6440,13 +6440,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "BriefDescription": "Randomly selected loads with latency value being above 16.", @@ -6462,13 +6462,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "BriefDescription": "Randomly selected loads with latency value being above 32.", @@ -6484,13 +6484,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "BriefDescription": "Randomly selected loads with latency value being above 64.", @@ -6506,13 +6506,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "BriefDescription": "Randomly selected loads with latency value being above 128.", @@ -6528,13 +6528,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "BriefDescription": "Randomly selected loads with latency value being above 256.", @@ -6550,13 +6550,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "BriefDescription": "Randomly selected loads with latency value being above 512.", @@ -6572,7 +6572,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "Offcore": "0" @@ -6581,8 +6581,8 @@ "EventCode": "0xD0", "UMask": "0x11", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "BriefDescription": "Retired load uops that miss the STLB. (precise Event)", - "PublicDescription": "Retired load uops that miss the STLB. (precise Event)", + "BriefDescription": "Retired load uops that miss the STLB.", + "PublicDescription": "Retired load uops that miss the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6603,8 +6603,8 @@ "EventCode": "0xD0", "UMask": "0x12", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "BriefDescription": "Retired store uops that miss the STLB. (precise Event)", - "PublicDescription": "Retired store uops that miss the STLB. (precise Event)", + "BriefDescription": "Retired store uops that miss the STLB.", + "PublicDescription": "Retired store uops that miss the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6625,8 +6625,8 @@ "EventCode": "0xD0", "UMask": "0x21", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "BriefDescription": "Retired load uops with locked access. (precise Event)", - "PublicDescription": "Retired load uops with locked access. (precise Event)", + "BriefDescription": "Retired load uops with locked access.", + "PublicDescription": "Retired load uops with locked access.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6647,8 +6647,8 @@ "EventCode": "0xD0", "UMask": "0x41", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "BriefDescription": "Retired load uops that split across a cacheline boundary. (precise Event)", - "PublicDescription": "This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "PublicDescription": "Retired load uops that split across a cacheline boundary.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6669,8 +6669,8 @@ "EventCode": "0xD0", "UMask": "0x42", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (precise Event)", - "PublicDescription": "This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "PublicDescription": "Retired store uops that split across a cacheline boundary.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6691,8 +6691,8 @@ "EventCode": "0xD0", "UMask": "0x81", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "BriefDescription": "All retired load uops. (precise Event)", - "PublicDescription": "All retired load uops. (precise Event)", + "BriefDescription": "All retired load uops.", + "PublicDescription": "All retired load uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6713,8 +6713,8 @@ "EventCode": "0xD0", "UMask": "0x82", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "BriefDescription": "All retired store uops. (precise Event)", - "PublicDescription": "This event counts all store uops retired. This is a precise event.", + "BriefDescription": "All retired store uops.", + "PublicDescription": "All retired store uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6779,8 +6779,8 @@ "EventCode": "0xD1", "UMask": "0x04", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", - "PublicDescription": "This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "PublicDescription": "Retired load uops with L3 cache hits as data sources.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "50021", @@ -6802,7 +6802,7 @@ "UMask": "0x08", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "BriefDescription": "Retired load uops misses in L1 cache as data sources.", - "PublicDescription": "This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.", + "PublicDescription": "Retired load uops missed L1 cache as data sources.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6823,8 +6823,8 @@ "EventCode": "0xD1", "UMask": "0x10", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "BriefDescription": "Retired load uops with L2 cache misses as data sources.", - "PublicDescription": "Retired load uops with L2 cache misses as data sources.", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "50021", @@ -6846,7 +6846,7 @@ "UMask": "0x20", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", - "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6911,8 +6911,8 @@ "EventCode": "0xD2", "UMask": "0x02", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. ", - "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "PublicDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "20011", @@ -6933,8 +6933,8 @@ "EventCode": "0xD2", "UMask": "0x04", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. ", - "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "PublicDescription": "Retired load uops which data sources were HitM responses from shared L3.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "20011", @@ -6977,8 +6977,8 @@ "EventCode": "0xD3", "UMask": "0x01", "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "BriefDescription": "tbd", - "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -7356,7 +7356,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC08FFF", "TakenAlone": "0", "CounterMask": "0", @@ -7378,7 +7378,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C8FFF", "TakenAlone": "0", "CounterMask": "0", @@ -7400,7 +7400,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01004007F7", "TakenAlone": "0", "CounterMask": "0", @@ -7422,7 +7422,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC007F7", "TakenAlone": "0", "CounterMask": "0", @@ -7444,7 +7444,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C07F7", "TakenAlone": "0", "CounterMask": "0", @@ -7466,7 +7466,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C07F7", "TakenAlone": "0", "CounterMask": "0", @@ -7488,7 +7488,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100400244", "TakenAlone": "0", "CounterMask": "0", @@ -7510,7 +7510,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00244", "TakenAlone": "0", "CounterMask": "0", @@ -7532,7 +7532,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0244", "TakenAlone": "0", "CounterMask": "0", @@ -7554,7 +7554,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100400122", "TakenAlone": "0", "CounterMask": "0", @@ -7576,7 +7576,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00122", "TakenAlone": "0", "CounterMask": "0", @@ -7598,7 +7598,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -7620,7 +7620,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -7642,7 +7642,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100400091", "TakenAlone": "0", "CounterMask": "0", @@ -7664,7 +7664,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00091", "TakenAlone": "0", "CounterMask": "0", @@ -7686,7 +7686,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0091", "TakenAlone": "0", "CounterMask": "0", @@ -7708,7 +7708,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0091", "TakenAlone": "0", "CounterMask": "0", @@ -7730,7 +7730,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00200", "TakenAlone": "0", "CounterMask": "0", @@ -7752,7 +7752,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0200", "TakenAlone": "0", "CounterMask": "0", @@ -7774,7 +7774,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00100", "TakenAlone": "0", "CounterMask": "0", @@ -7796,7 +7796,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0100", "TakenAlone": "0", "CounterMask": "0", @@ -7818,7 +7818,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00080", "TakenAlone": "0", "CounterMask": "0", @@ -7840,7 +7840,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0080", "TakenAlone": "0", "CounterMask": "0", @@ -7862,7 +7862,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00040", "TakenAlone": "0", "CounterMask": "0", @@ -7884,7 +7884,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0040", "TakenAlone": "0", "CounterMask": "0", @@ -7906,7 +7906,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00020", "TakenAlone": "0", "CounterMask": "0", @@ -7928,7 +7928,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0020", "TakenAlone": "0", "CounterMask": "0", @@ -7950,7 +7950,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00010", "TakenAlone": "0", "CounterMask": "0", @@ -7972,7 +7972,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0010", "TakenAlone": "0", "CounterMask": "0", @@ -7994,7 +7994,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100400004", "TakenAlone": "0", "CounterMask": "0", @@ -8016,7 +8016,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00004", "TakenAlone": "0", "CounterMask": "0", @@ -8038,7 +8038,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8060,7 +8060,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8082,7 +8082,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100400002", "TakenAlone": "0", "CounterMask": "0", @@ -8104,7 +8104,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00002", "TakenAlone": "0", "CounterMask": "0", @@ -8126,7 +8126,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -8148,7 +8148,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -8170,7 +8170,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100400001", "TakenAlone": "0", "CounterMask": "0", @@ -8192,7 +8192,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00001", "TakenAlone": "0", "CounterMask": "0", @@ -8214,7 +8214,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0001", "TakenAlone": "0", "CounterMask": "0", @@ -8236,7 +8236,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0001", "TakenAlone": "0", "CounterMask": "0", diff --git a/usr/src/data/perfmon/HSW/haswell_fp_arith_inst_v28.json b/usr/src/data/perfmon/HSW/haswell_fp_arith_inst_v28.json deleted file mode 100644 index 0637a088a0..0000000000 --- a/usr/src/data/perfmon/HSW/haswell_fp_arith_inst_v28.json +++ /dev/null @@ -1 +0,0 @@ -[]
\ No newline at end of file diff --git a/usr/src/data/perfmon/HSW/haswell_matrix_bit_definitions_v28.json b/usr/src/data/perfmon/HSW/haswell_matrix_bit_definitions_v28.json deleted file mode 100644 index d0f926ad55..0000000000 --- a/usr/src/data/perfmon/HSW/haswell_matrix_bit_definitions_v28.json +++ /dev/null @@ -1,389 +0,0 @@ -[ - { - "BitName": "DEMAND_DATA_RD", - "BitIndex": "0", - "Type": "1", - "Description": "Counts demand data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "DEMAND_RFO", - "BitIndex": "1", - "Type": "1", - "Description": "Counts all demand data writes (RFOs)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "DEMAND_CODE_RD", - "BitIndex": "2", - "Type": "1", - "Description": "Counts all demand code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "COREWB", - "BitIndex": "3", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "PF_L2_DATA_RD", - "BitIndex": "4", - "Type": "1", - "Description": "Counts prefetch (that bring data to L2) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_RFO", - "BitIndex": "5", - "Type": "1", - "Description": "Counts all prefetch (that bring data to L2) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_CODE_RD", - "BitIndex": "6", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_DATA_RD", - "BitIndex": "7", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "PF_L3_RFO", - "BitIndex": "8", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "PF_L3_CODE_RD", - "BitIndex": "9", - "Type": "1", - "Description": "Counts prefetch (that bring data to LLC only) code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "SPLIT_LOCK_UC_LOCK", - "BitIndex": "10", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "STREAMING_STORES", - "BitIndex": "11", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "OTHER", - "BitIndex": "15", - "Type": "1", - "Description": "Counts any other requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_DATA_RD", - "BitIndex": "4,7", - "Type": "1", - "Description": "Counts all prefetch data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "ALL_PF_RFO", - "BitIndex": "5,8", - "Type": "1", - "Description": "Counts prefetch RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "ALL_PF_CODE_RD", - "BitIndex": "6,9", - "Type": "1", - "Description": "Counts all prefetch code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "ALL_DATA_RD", - "BitIndex": "0,4,7", - "Type": "1", - "Description": "Counts all demand & prefetch data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "ALL_RFO", - "BitIndex": "1,5,8", - "Type": "1", - "Description": "Counts all demand & prefetch RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "ALL_CODE_RD", - "BitIndex": "2,6,9", - "Type": "1", - "Description": "Counts all demand & prefetch code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "ALL_READS", - "BitIndex": "0,1,2,4,5,6,7,8,9,10", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "ALL_REQUESTS", - "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15", - "Type": "1", - "Description": "Counts all requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "HSD150" - }, - { - "BitName": "ANY_RESPONSE", - "BitIndex": "16", - "Type": "2", - "Description": "have any response type.", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SUPPLIER_NONE", - "BitIndex": "17", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124", - "Errata": "na" - }, - { - "BitName": "L3_HIT_M", - "BitIndex": "18", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124", - "Errata": "na" - }, - { - "BitName": "L3_HIT_E", - "BitIndex": "19", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124", - "Errata": "na" - }, - { - "BitName": "L3_HIT_S", - "BitIndex": "20", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124", - "Errata": "na" - }, - { - "BitName": "L3_HIT", - "BitIndex": "18,19,20", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124", - "Errata": "na" - }, - { - "BitName": "L3_MISS_LOCAL_DRAM", - "BitIndex": "22", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124", - "Errata": "na" - }, - { - "BitName": "SNOOP_NONE", - "BitIndex": "31", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_NOT_NEEDED", - "BitIndex": "32", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_MISS", - "BitIndex": "33", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_NO_FWD", - "BitIndex": "34", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_WITH_FWD", - "BitIndex": "35", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_HITM", - "BitIndex": "36", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_NON_DRAM", - "BitIndex": "37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "ANY_SNOOP", - "BitIndex": "31,32,33,34,35,36,37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.NO_SNOOP_NEEDED", - "BitIndex": "18,19,20,21,32", - "Type": "2", - "Description": "hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BitIndex": "18,19,20,21,34", - "Type": "2", - "Description": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.HITM_OTHER_CORE", - "BitIndex": "18,19,20,21,36", - "Type": "2", - "Description": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_MISS.LOCAL_DRAM", - "BitIndex": "22,32", - "Type": "2", - "Description": "miss the L3 and the data is returned from local dram", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_MISS.ANY_DRAM", - "BitIndex": "22,23,24,25,26,27,28,29,30,33,34", - "Type": "2", - "Description": "miss the L3 and the data is returned from local or remote dram", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.ANY_RESPONSE", - "BitIndex": "18,19,20,21,31,32,33,34,35,36,37", - "Type": "2", - "Description": "hit in the L3", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_MISS.ANY_RESPONSE", - "BitIndex": "22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37", - "Type": "2", - "Description": "miss in the L3", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - } -]
\ No newline at end of file diff --git a/usr/src/data/perfmon/HSW/haswell_matrix_v28.json b/usr/src/data/perfmon/HSW/haswell_matrix_v30.json index c944cb5cf8..c944cb5cf8 100644 --- a/usr/src/data/perfmon/HSW/haswell_matrix_v28.json +++ b/usr/src/data/perfmon/HSW/haswell_matrix_v30.json diff --git a/usr/src/data/perfmon/HSW/haswell_uncore_v28.json b/usr/src/data/perfmon/HSW/haswell_uncore_v30.json index 55fc10c211..9f5141de47 100644 --- a/usr/src/data/perfmon/HSW/haswell_uncore_v28.json +++ b/usr/src/data/perfmon/HSW/haswell_uncore_v30.json @@ -312,7 +312,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x80", "UMask": "0x01", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", @@ -324,7 +324,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x81", "UMask": "0x01", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", @@ -336,7 +336,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x81", "UMask": "0x20", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", @@ -348,7 +348,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x83", "UMask": "0x01", "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All", @@ -360,7 +360,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x84", "UMask": "0x01", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", @@ -372,7 +372,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x80", "UMask": "0x01", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", diff --git a/usr/src/data/perfmon/HSX/haswellx_core_v20.json b/usr/src/data/perfmon/HSX/haswellx_core_v22.json index 0c0d6f7d6f..affc2b4b6d 100644 --- a/usr/src/data/perfmon/HSX/haswellx_core_v20.json +++ b/usr/src/data/perfmon/HSX/haswellx_core_v22.json @@ -690,7 +690,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -762,7 +762,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -793,7 +793,7 @@ }, { "EventCode": "0x24", - "UMask": "0x3F", + "UMask": "0x3f", "EventName": "L2_RQSTS.MISS", "BriefDescription": "All requests that miss L2 cache", "PublicDescription": "All requests that missed L2.", @@ -810,7 +810,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -834,7 +834,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -913,7 +913,7 @@ }, { "EventCode": "0x24", - "UMask": "0xE1", + "UMask": "0xe1", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "BriefDescription": "Demand Data Read requests", "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", @@ -930,7 +930,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -1002,7 +1002,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -1033,7 +1033,7 @@ }, { "EventCode": "0x24", - "UMask": "0xFF", + "UMask": "0xff", "EventName": "L2_RQSTS.REFERENCES", "BriefDescription": "All L2 requests", "PublicDescription": "All requests to L2 cache.", @@ -1050,7 +1050,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -1183,7 +1183,7 @@ "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1207,7 +1207,7 @@ "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1231,7 +1231,7 @@ "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1255,7 +1255,7 @@ "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1279,7 +1279,7 @@ "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1303,7 +1303,7 @@ "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -2298,7 +2298,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78, HSD62, HSD61", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -2322,7 +2322,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78, HSD62, HSD61", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -2346,7 +2346,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78, HSD62, HSD61", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -2370,7 +2370,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -2394,7 +2394,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -2418,7 +2418,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -2442,7 +2442,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -2466,7 +2466,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD62, HSD61", + "Errata": "HSD62, HSD61, HSM63", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -4608,7 +4608,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xA3", + "EventCode": "0xa3", "UMask": "0x01", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", "BriefDescription": "Cycles with pending L2 cache miss loads.", @@ -4626,7 +4626,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM63, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -4680,7 +4680,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xA3", + "EventCode": "0xa3", "UMask": "0x05", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", "BriefDescription": "Execution stalls due to L2 cache misses.", @@ -4698,7 +4698,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "0", + "Errata": "HSM63, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -4896,7 +4896,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xB0", + "EventCode": "0xb0", "UMask": "0x01", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "BriefDescription": "Demand Data Read requests sent to uncore", @@ -4914,7 +4914,7 @@ "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", - "Errata": "HSD78", + "Errata": "HSD78, HSM80", "ELLC": "0", "Offcore": "0", "EVENT_STATUS": "0" @@ -5896,7 +5896,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "1", - "Data_LA": "1", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6984,7 +6984,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "BriefDescription": "Randomly selected loads with latency value being above 4.", @@ -7000,7 +7000,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "ELLC": "0", @@ -7008,7 +7008,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "BriefDescription": "Randomly selected loads with latency value being above 8.", @@ -7024,7 +7024,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "ELLC": "0", @@ -7032,7 +7032,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "BriefDescription": "Randomly selected loads with latency value being above 16.", @@ -7048,7 +7048,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "ELLC": "0", @@ -7056,7 +7056,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "BriefDescription": "Randomly selected loads with latency value being above 32.", @@ -7072,7 +7072,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "ELLC": "0", @@ -7080,7 +7080,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "BriefDescription": "Randomly selected loads with latency value being above 64.", @@ -7096,7 +7096,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "ELLC": "0", @@ -7104,7 +7104,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "BriefDescription": "Randomly selected loads with latency value being above 128.", @@ -7120,7 +7120,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "ELLC": "0", @@ -7128,7 +7128,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "BriefDescription": "Randomly selected loads with latency value being above 256.", @@ -7144,7 +7144,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "ELLC": "0", @@ -7152,7 +7152,7 @@ "EVENT_STATUS": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "BriefDescription": "Randomly selected loads with latency value being above 512.", @@ -7168,7 +7168,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "HSD76, HSD25, HSM26", "ELLC": "0", diff --git a/usr/src/data/perfmon/HSX/haswellx_matrix_bit_definitions_v20.json b/usr/src/data/perfmon/HSX/haswellx_matrix_bit_definitions_v20.json deleted file mode 100644 index 7aaaf18a10..0000000000 --- a/usr/src/data/perfmon/HSX/haswellx_matrix_bit_definitions_v20.json +++ /dev/null @@ -1,497 +0,0 @@ -[ - { - "BitName": "DEMAND_DATA_RD", - "BitIndex": "0", - "Type": "1", - "Description": "Counts demand data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "DEMAND_RFO", - "BitIndex": "1", - "Type": "1", - "Description": "Counts all demand data writes (RFOs)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "DEMAND_CODE_RD", - "BitIndex": "2", - "Type": "1", - "Description": "Counts all demand code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "COREWB", - "BitIndex": "3", - "Type": "1", - "Description": "Counts writebacks (modified to exclusive)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_DATA_RD", - "BitIndex": "4", - "Type": "1", - "Description": "Counts prefetch (that bring data to L2) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_RFO", - "BitIndex": "5", - "Type": "1", - "Description": "Counts all prefetch (that bring data to L2) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L2_CODE_RD", - "BitIndex": "6", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_DATA_RD", - "BitIndex": "7", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_RFO", - "BitIndex": "8", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "PF_L3_CODE_RD", - "BitIndex": "9", - "Type": "1", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SPLIT_LOCK_UC_LOCK", - "BitIndex": "10", - "Type": "1", - "Description": "Counts all locks that are either split across cache line boundaries or to uncacheable addresses", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "STREAMING_STORES", - "BitIndex": "11", - "Type": "1", - "Description": "Counts all non-temporal stores", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "OTHER", - "BitIndex": "15", - "Type": "1", - "Description": "Counts any other requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_DATA_RD", - "BitIndex": "4,7", - "Type": "1", - "Description": "Counts all prefetch data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_RFO", - "BitIndex": "5,8", - "Type": "1", - "Description": "Counts prefetch RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_PF_CODE_RD", - "BitIndex": "6,9", - "Type": "1", - "Description": "Counts all prefetch code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_DATA_RD", - "BitIndex": "0,4,7", - "Type": "1", - "Description": "Counts all demand & prefetch data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_RFO", - "BitIndex": "1,5,8", - "Type": "1", - "Description": "Counts all demand & prefetch RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_CODE_RD", - "BitIndex": "2,6,9", - "Type": "1", - "Description": "Counts all demand & prefetch code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_READS", - "BitIndex": "0,1,2,4,5,6,7,8,9,10", - "Type": "1", - "Description": "Counts all data/code/rfo reads (demand & prefetch)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ALL_REQUESTS", - "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15", - "Type": "1", - "Description": "Counts all requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ANY_RESPONSE", - "BitIndex": "16", - "Type": "2", - "Description": "have any response type.", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SUPPLIER_NONE", - "BitIndex": "17", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_HIT_M", - "BitIndex": "18", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_HIT_E", - "BitIndex": "19", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_HIT_S", - "BitIndex": "20", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_HIT_F", - "BitIndex": "21", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_HIT", - "BitIndex": "18,19,20,21", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_MISS_LOCAL_DRAM", - "BitIndex": "22", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_MISS_REMOTE_HOP0", - "BitIndex": "27", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_MISS_REMOTE_HOP1", - "BitIndex": "28", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_MISS_REMOTE_HOP2P", - "BitIndex": "29", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "L3_MISS", - "BitIndex": "22,27,28,29", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "317,334,335,336,337,338,339,340,341,342", - "Errata": "na" - }, - { - "BitName": "SNOOP_NONE", - "BitIndex": "31", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NOT_NEEDED", - "BitIndex": "32", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_MISS", - "BitIndex": "33", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_NO_FWD", - "BitIndex": "34", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_WITH_FWD", - "BitIndex": "35", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_HITM", - "BitIndex": "36", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NON_DRAM", - "BitIndex": "37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ANY_SNOOP", - "BitIndex": "31,32,33,34,35,36,37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.ANY_RESPONSE", - "BitIndex": "18,19,20,21,31,32,33,34,35,36,37", - "Type": "2", - "Description": "hit in the L3", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.NO_SNOOP_NEEDED", - "BitIndex": "18,19,20,21,32", - "Type": "2", - "Description": "hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.SNOOP_MISS", - "BitIndex": "18,19,20,21,33", - "Type": "2", - "Description": "hit in the L3 and the snoops sent to sibling cores return clean response", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "BitIndex": "18,19,20,21,34", - "Type": "2", - "Description": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_HIT.HITM_OTHER_CORE", - "BitIndex": "18,19,20,21,36", - "Type": "2", - "Description": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.ANY_RESPONSE", - "BitIndex": "22,23,24,25,26,27,28,29,31,32,33,34,35,36,37", - "Type": "2", - "Description": "miss in the L3", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.LOCAL_DRAM", - "BitIndex": "22,33,34", - "Type": "2", - "Description": "miss the L3 and the data is returned from local dram", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.REMOTE_DRAM", - "BitIndex": "23,24,25,26,27,28,29,33,34", - "Type": "2", - "Description": "miss the L3 and the data is returned from remote dram", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.ANY_DRAM", - "BitIndex": "22,23,24,25,26,27,28,29,33,34", - "Type": "2", - "Description": "miss the L3 and the data is returned from local or remote dram", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.REMOTE_HITM", - "BitIndex": "22,23,24,25,26,27,28,29,36", - "Type": "2", - "Description": "miss the L3 and the modified data is transferred from remote cache", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "LLC_MISS.REMOTE_HIT_FORWARD", - "BitIndex": "22,23,24,25,26,27,28,29,35", - "Type": "2", - "Description": "miss the L3 and clean or shared data is transferred from remote cache", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_LLC_DATA_RD", - "BitIndex": "7", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_LLC_RFO", - "BitIndex": "8", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_LLC_CODE_RD", - "BitIndex": "9", - "Type": "1", - "Description": "Counts prefetch (that bring data to LLC only) code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - } -]
\ No newline at end of file diff --git a/usr/src/data/perfmon/HSX/haswellx_matrix_v20.json b/usr/src/data/perfmon/HSX/haswellx_matrix_v22.json index 17ce9ca824..17ce9ca824 100644 --- a/usr/src/data/perfmon/HSX/haswellx_matrix_v20.json +++ b/usr/src/data/perfmon/HSX/haswellx_matrix_v22.json diff --git a/usr/src/data/perfmon/HSX/haswellx_uncore_v20.json b/usr/src/data/perfmon/HSX/haswellx_uncore_v22.json index 77ad08fcbc..77ad08fcbc 100644 --- a/usr/src/data/perfmon/HSX/haswellx_uncore_v20.json +++ b/usr/src/data/perfmon/HSX/haswellx_uncore_v22.json diff --git a/usr/src/data/perfmon/ICL/icelake_core_v1.09.json b/usr/src/data/perfmon/ICL/icelake_core_v1.09.json new file mode 100644 index 0000000000..f1ea9df784 --- /dev/null +++ b/usr/src/data/perfmon/ICL/icelake_core_v1.09.json @@ -0,0 +1,7385 @@ +[ + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.ANY", + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "32", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", + "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", + "Counter": "32", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Core cycles when the thread is not in halt state", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "Counter": "33", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x03", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "34", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x04", + "EventName": "TOPDOWN.SLOTS", + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "Counter": "35", + "PEBScounters": "35", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x02", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x08", + "EventName": "LD_BLOCKS.NO_SR", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x07", + "UMask": "0x01", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x02", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x04", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x0e", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0D", + "UMask": "0x01", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0D", + "UMask": "0x03", + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", + "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0d", + "UMask": "0x10", + "EventName": "INT_MISC.UOP_DROPPING", + "BriefDescription": "TMA slots where uops got dropped", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0d", + "UMask": "0x80", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0e", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Uops that RAT issues to RS", + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0E", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", + "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x14", + "UMask": "0x09", + "EventName": "ARITH.DIVIDER_ACTIVE", + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x21", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "BriefDescription": "Demand Data Read miss L2, no rejects", + "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x22", + "EventName": "L2_RQSTS.RFO_MISS", + "BriefDescription": "RFO requests that miss L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "BriefDescription": "L2 cache misses when fetching instructions", + "PublicDescription": "Counts L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x27", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "BriefDescription": "Demand requests that miss L2 cache", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x28", + "EventName": "L2_RQSTS.SWPF_MISS", + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc2", + "EventName": "L2_RQSTS.RFO_HIT", + "BriefDescription": "RFO requests that hit L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc4", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc8", + "EventName": "L2_RQSTS.SWPF_HIT", + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xE1", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests", + "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xE2", + "EventName": "L2_RQSTS.ALL_RFO", + "BriefDescription": "RFO requests to L2 cache", + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xE4", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "BriefDescription": "L2 code requests", + "PublicDescription": "Counts the total number of L2 code requests.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xE7", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "BriefDescription": "Demand requests to L2 cache", + "PublicDescription": "Counts demand requests to L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x28", + "UMask": "0x07", + "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x28", + "UMask": "0x18", + "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x28", + "UMask": "0x20", + "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x01", + "EventName": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x32", + "UMask": "0x01", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x32", + "UMask": "0x02", + "EventName": "SW_PREFETCH_ACCESS.T0", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x32", + "UMask": "0x04", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x32", + "UMask": "0x08", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "BriefDescription": "Number of PREFETCHW instructions executed.", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3C", + "UMask": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "BriefDescription": "Thread cycles when thread is not in halt state", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3C", + "UMask": "0x01", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3C", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x08", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING", + "BriefDescription": "Number of L1D misses that are outstanding", + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", + "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x04", + "EventName": "L1D_PEND_MISS.L2_STALL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x02", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x04", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x0e", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x4c", + "UMask": "0x01", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x51", + "UMask": "0x01", + "EventName": "L1D.REPLACEMENT", + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", + "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x01", + "EventName": "TX_MEM.ABORT_CONFLICT", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x02", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x04", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x08", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x10", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x20", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x40", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", + "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x80", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x5d", + "UMask": "0x02", + "EventName": "TX_EXEC.MISC2", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", + "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x5d", + "UMask": "0x04", + "EventName": "TX_EXEC.MISC3", + "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", + "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x5e", + "UMask": "0x01", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x5E", + "UMask": "0x01", + "EventName": "RS_EVENTS.EMPTY_END", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read transactions pending for off-core. Highly correlated.", + "PublicDescription": "Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.", + "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.", + "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_OK", + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_ANY", + "BriefDescription": "Cycles MITE is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_OK", + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_ANY", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "EventName": "IDQ.MS_SWITCHES", + "BriefDescription": "Number of switches from DSB or MITE to the MS", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "BriefDescription": "Uops delivered to IDQ while MS is busy", + "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES_ANY", + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_16B.IFDATA_STALL", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x01", + "EventName": "ICACHE_64B.IFTAG_HIT", + "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x02", + "EventName": "ICACHE_64B.IFTAG_MISS", + "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x04", + "EventName": "ICACHE_64B.IFTAG_STALL", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x02", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x04", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x0e", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x01", + "EventName": "ILD_STALL.LCP", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9C", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x01", + "EventName": "UOPS_DISPATCHED.PORT_0", + "BriefDescription": "Number of uops executed on port 0", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x02", + "EventName": "UOPS_DISPATCHED.PORT_1", + "BriefDescription": "Number of uops executed on port 1", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x04", + "EventName": "UOPS_DISPATCHED.PORT_2_3", + "BriefDescription": "Number of uops executed on port 2 and 3", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x10", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "BriefDescription": "Number of uops executed on port 4 and 9", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x20", + "EventName": "UOPS_DISPATCHED.PORT_5", + "BriefDescription": "Number of uops executed on port 5", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED.PORT_6", + "BriefDescription": "Number of uops executed on port 6", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "BriefDescription": "Number of uops executed on port 7 and 8", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x02", + "EventName": "RESOURCE_STALLS.SCOREBOARD", + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "PublicDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x08", + "EventName": "RESOURCE_STALLS.SB", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA3", + "UMask": "0x01", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA3", + "UMask": "0x02", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L3 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x04", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "BriefDescription": "Total execution stalls.", + "PublicDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x05", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x06", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA3", + "UMask": "0x08", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA3", + "UMask": "0x0C", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "12", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA3", + "UMask": "0x10", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "PublicDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "16", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x14", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "20", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x01", + "EventName": "TOPDOWN.SLOTS_P", + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x02", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x08", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x02", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x04", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x08", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x10", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA6", + "UMask": "0x40", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x80", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.", + "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.UOPS", + "BriefDescription": "Number of Uops delivered by the LSD.", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_ACTIVE", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_OK", + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xab", + "UMask": "0x02", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xab", + "UMask": "0x02", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", + "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests sent to uncore", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB0", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "BriefDescription": "Demand and prefetch data reads", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests who miss L3 cache", + "PublicDescription": "Demand Data Read requests who miss L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB0", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "BriefDescription": "Any memory transaction that reached the SQ.", + "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.THREAD", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE", + "BriefDescription": "Number of uops executed on the core.", + "PublicDescription": "Counts the number of uops executed from any thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x10", + "EventName": "UOPS_EXECUTED.X87", + "BriefDescription": "Counts the number of x87 uops dispatched.", + "PublicDescription": "Counts the number of x87 uops executed.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xBD", + "UMask": "0x01", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xBD", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "BriefDescription": "STLB flush attempts", + "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x01", + "EventName": "INST_RETIRED.STALL_CYCLES", + "BriefDescription": "Cycles without actually retired instructions.", + "PublicDescription": "This event counts cycles without actually retired instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x02", + "EventName": "ASSISTS.FP", + "BriefDescription": "Counts all microcode FP assists.", + "PublicDescription": "Counts all microcode Floating Point assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x07", + "EventName": "ASSISTS.ANY", + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "This event counts cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "10", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.SLOTS", + "BriefDescription": "Retirement slots used.", + "PublicDescription": "Counts the retirement slots used each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x01", + "EventName": "MACHINE_CLEARS.COUNT", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x02", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x04", + "EventName": "MACHINE_CLEARS.SMC", + "BriefDescription": "Self-modifying code (SMC) detected.", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "BriefDescription": "All branch instructions retired.", + "PublicDescription": "Counts all branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x01", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Taken conditional branch instructions retired.", + "PublicDescription": "Counts taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x02", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x08", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "BriefDescription": "Return instructions retired.", + "PublicDescription": "Counts return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "Counts not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x11", + "EventName": "BR_INST_RETIRED.COND", + "BriefDescription": "Conditional branch instructions retired.", + "PublicDescription": "Counts conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Taken branch instructions retired.", + "PublicDescription": "Counts taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "Counts far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "EventName": "BR_INST_RETIRED.INDIRECT", + "BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch).", + "PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "All mispredicted branch instructions retired.", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x02", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Mispredicted indirect CALL instructions retired.", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x10", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x11", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x80", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500206", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500406", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500806", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x501006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x502006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x504006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x508006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x510006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x520006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500106", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x40", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x80", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x01", + "EventName": "HLE_RETIRED.START", + "BriefDescription": "Number of times an HLE execution started.", + "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x02", + "EventName": "HLE_RETIRED.COMMIT", + "BriefDescription": "Number of times an HLE execution successfully committed", + "PublicDescription": "Counts the number of times HLE commit succeeded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x04", + "EventName": "HLE_RETIRED.ABORTED", + "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", + "PublicDescription": "Counts the number of times HLE abort was triggered.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x08", + "EventName": "HLE_RETIRED.ABORTED_MEM", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x20", + "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x80", + "EventName": "HLE_RETIRED.ABORTED_EVENTS", + "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", + "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x01", + "EventName": "RTM_RETIRED.START", + "BriefDescription": "Number of times an RTM execution started.", + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x02", + "EventName": "RTM_RETIRED.COMMIT", + "BriefDescription": "Number of times an RTM execution successfully committed", + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x04", + "EventName": "RTM_RETIRED.ABORTED", + "BriefDescription": "Number of times an RTM execution aborted.", + "PublicDescription": "Counts the number of times RTM abort was triggered.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x08", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x80", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcc", + "UMask": "0x20", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcc", + "UMask": "0x40", + "EventName": "MISC_RETIRED.PAUSE_INST", + "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0", + "MSRValue": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20011", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2003", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1009", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "503", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "101", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x11", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "BriefDescription": "Retired load instructions that miss the STLB.", + "PublicDescription": "Counts retired load instructions that true miss the STLB.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x12", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "BriefDescription": "Retired store instructions that miss the STLB.", + "PublicDescription": "Counts retired store instructions that true miss the STLB.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x21", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "BriefDescription": "Retired load instructions with locked access.", + "PublicDescription": "Counts retired load instructions with locked access.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x41", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x42", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "BriefDescription": "All retired load instructions.", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x82", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "BriefDescription": "All retired store instructions.", + "PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x01", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x02", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x08", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x20", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", + "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", + "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe6", + "UMask": "0x01", + "EventName": "BACLEARS.ANY", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xF0", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "BriefDescription": "L2 writebacks that access L2 cache", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xF1", + "UMask": "0x1F", + "EventName": "L2_LINES_IN.ALL", + "BriefDescription": "L2 cache lines filling L2", + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xF2", + "UMask": "0x01", + "EventName": "L2_LINES_OUT.SILENT", + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xF2", + "UMask": "0x02", + "EventName": "L2_LINES_OUT.NON_SILENT", + "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", + "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xf2", + "UMask": "0x04", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", + "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xf4", + "UMask": "0x04", + "EventName": "SQ_MISC.SQ_FULL", + "BriefDescription": "Cycles the superQ cannot take any more entries.", + "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0400", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0400", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0400", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", + "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0800", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C8000", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C8000", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C8000", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_HIT.ANY", + "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C2380", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand data reads that have any type of response.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010400", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "BriefDescription": "Counts streaming stores that have any type of response.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010800", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.ANY_RESPONSE", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000018000", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C8000", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.DRAM", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000400", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.DRAM", + "BriefDescription": "Counts streaming stores that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000800", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.DRAM", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184008000", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.L3_MISS", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00400", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00800", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.L3_MISS", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC08000", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000001", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000002", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000004", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000010", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000020", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000400", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", + "BriefDescription": "Counts streaming stores that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184000800", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.LOCAL_DRAM", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0184008000", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "1", + "Speculative": "1" + } +]
\ No newline at end of file diff --git a/usr/src/data/perfmon/ICL/icelake_uncore_v1.09.json b/usr/src/data/perfmon/ICL/icelake_uncore_v1.09.json new file mode 100644 index 0000000000..5e067ed8bc --- /dev/null +++ b/usr/src/data/perfmon/ICL/icelake_uncore_v1.09.json @@ -0,0 +1,38 @@ +[ + { + "Unit": "NCU", + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "UNC_CLOCK.SOCKET", + "BriefDescription": "tbd", + "PublicDescription": "tbd", + "Counter": "FIXED", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x81", + "UMask": "0x01", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", + "PublicDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", + "Counter": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x84", + "UMask": "0x01", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.", + "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.", + "Counter": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + } +]
\ No newline at end of file diff --git a/usr/src/data/perfmon/SKL/skylake_core_v42.json b/usr/src/data/perfmon/SKL/skylake_core_v50.json index f540d7064a..a351fd534f 100644 --- a/usr/src/data/perfmon/SKL/skylake_core_v42.json +++ b/usr/src/data/perfmon/SKL/skylake_core_v50.json @@ -91,8 +91,8 @@ "EventCode": "0x03", "UMask": "0x02", "EventName": "LD_BLOCKS.STORE_FORWARD", - "BriefDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded .", - "PublicDescription": "Counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations,c. preceding lock RMW operations are not forwarded,d. store has the no-forward bit set (uncacheable/page-split/masked stores),e. all-blocking stores are used (mostly, fences and port I/O), and others.The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide.", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -180,7 +180,7 @@ "UMask": "0x02", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "BriefDescription": "Page walk completed due to a demand data load to a 4K page", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -202,7 +202,7 @@ "UMask": "0x04", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -224,7 +224,7 @@ "UMask": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "BriefDescription": "Page walk completed due to a demand data load to a 1G page", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -243,10 +243,10 @@ }, { "EventCode": "0x08", - "UMask": "0x0E", + "UMask": "0x0e", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -267,8 +267,8 @@ "EventCode": "0x08", "UMask": "0x10", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", - "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ", - "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture. ", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", + "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -289,7 +289,7 @@ "EventCode": "0x08", "UMask": "0x10", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -330,6 +330,28 @@ "Offcore": "0" }, { + "EventCode": "0x09", + "UMask": "0x01", + "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", + "BriefDescription": "tbd", + "PublicDescription": "tbd", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { "EventCode": "0x0D", "UMask": "0x01", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -444,7 +466,7 @@ "UMask": "0x02", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", - "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to “Mixing Intel AVX and Intel SSE Code” section of the Optimization Guide.", + "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -862,7 +884,7 @@ "UMask": "0x41", "EventName": "LONGEST_LAT_CACHE.MISS", "BriefDescription": "Core-originated cacheable demand requests missed L3", - "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.\r\n", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -884,7 +906,7 @@ "UMask": "0x4F", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "BriefDescription": "Core-originated cacheable demand requests that refer to L3", - "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3.\r\n", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1063,7 +1085,7 @@ "PublicDescription": "Core crystal clock cycles when the thread is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1085,7 +1107,7 @@ "PublicDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1107,7 +1129,7 @@ "PublicDescription": "Core crystal clock cycles when the thread is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1129,7 +1151,7 @@ "PublicDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1151,7 +1173,7 @@ "PublicDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1173,7 +1195,7 @@ "PublicDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1302,7 +1324,7 @@ "UMask": "0x02", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "BriefDescription": "Page walk completed due to a demand data store to a 4K page", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1324,7 +1346,7 @@ "UMask": "0x04", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1346,7 +1368,7 @@ "UMask": "0x08", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "BriefDescription": "Page walk completed due to a demand data store to a 1G page", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1365,10 +1387,10 @@ }, { "EventCode": "0x49", - "UMask": "0x0E", + "UMask": "0x0e", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1389,8 +1411,8 @@ "EventCode": "0x49", "UMask": "0x10", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", - "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ", - "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture. ", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", + "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -1411,7 +1433,7 @@ "EventCode": "0x49", "UMask": "0x10", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -1474,7 +1496,7 @@ "Offcore": "0" }, { - "EventCode": "0x4F", + "EventCode": "0x4f", "UMask": "0x10", "EventName": "EPT.WALK_PENDING", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", @@ -1917,7 +1939,7 @@ "EventCode": "0x60", "UMask": "0x02", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle. ", + "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.", "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -2512,7 +2534,7 @@ "UMask": "0x02", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", - "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2534,7 +2556,7 @@ "UMask": "0x04", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2556,7 +2578,7 @@ "UMask": "0x08", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", - "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2575,10 +2597,10 @@ }, { "EventCode": "0x85", - "UMask": "0x0E", + "UMask": "0x0e", "EventName": "ITLB_MISSES.WALK_COMPLETED", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2599,8 +2621,8 @@ "EventCode": "0x85", "UMask": "0x10", "EventName": "ITLB_MISSES.WALK_PENDING", - "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake. ", - "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture. ", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", + "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2688,7 +2710,7 @@ "UMask": "0x01", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.", + "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -3433,10 +3455,32 @@ }, { "EventCode": "0xAB", + "UMask": "0x01", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xAB", "UMask": "0x02", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", - "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cycles.", + "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -4136,10 +4180,32 @@ "Offcore": "0" }, { + "EventCode": "0xc2", + "UMask": "0x04", + "EventName": "UOPS_RETIRED.MACRO_FUSED", + "BriefDescription": "Number of macro-fused uops retired. (non precise)", + "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { "EventCode": "0xC3", "UMask": "0x01", "EventName": "MACHINE_CLEARS.COUNT", - "BriefDescription": "Number of machine clears (nukes) of any type. ", + "BriefDescription": "Number of machine clears (nukes) of any type.", "PublicDescription": "Number of machine clears (nukes) of any type.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -4228,7 +4294,7 @@ "UMask": "0x01", "EventName": "BR_INST_RETIRED.CONDITIONAL", "BriefDescription": "Conditional branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.", + "PublicDescription": "This event counts conditional branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4250,7 +4316,7 @@ "UMask": "0x02", "EventName": "BR_INST_RETIRED.NEAR_CALL", "BriefDescription": "Direct and indirect near call instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.", + "PublicDescription": "This event counts both direct and indirect near call instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -4271,7 +4337,7 @@ "EventCode": "0xC4", "UMask": "0x04", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "BriefDescription": "All (macro) branch instructions retired. ", + "BriefDescription": "All (macro) branch instructions retired.", "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -4294,7 +4360,7 @@ "UMask": "0x08", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "BriefDescription": "Return instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.", + "PublicDescription": "This event counts return instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -4315,8 +4381,8 @@ "EventCode": "0xC4", "UMask": "0x10", "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "BriefDescription": "Counts all not taken macro branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired.", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "This event counts not taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4327,7 +4393,29 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SKL091", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "This event counts not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "SKL091", @@ -4338,7 +4426,7 @@ "UMask": "0x20", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "BriefDescription": "Taken branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.", + "PublicDescription": "This event counts taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4359,8 +4447,8 @@ "EventCode": "0xC4", "UMask": "0x40", "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "BriefDescription": "Counts the number of far branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired.", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "This event counts far branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -4404,7 +4492,7 @@ "UMask": "0x01", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "BriefDescription": "Mispredicted conditional branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.", + "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4426,7 +4514,7 @@ "UMask": "0x02", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "BriefDescription": "Mispredicted direct and indirect near call instructions retired.", - "PublicDescription": "This event counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.", + "PublicDescription": "Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4447,7 +4535,7 @@ "EventCode": "0xC5", "UMask": "0x04", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "BriefDescription": "Mispredicted macro branch instructions retired. ", + "BriefDescription": "Mispredicted macro branch instructions retired.", "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -4469,7 +4557,7 @@ "EventCode": "0xC5", "UMask": "0x20", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken. ", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -4491,8 +4579,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.DSB_MISS", - "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss. Precise Event.", - "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. \r\n", + "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss.", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4513,8 +4601,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.L1I_MISS", - "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event.", - "PublicDescription": "Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event.", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "PublicDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4535,8 +4623,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.L2_MISS", - "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event.", - "PublicDescription": "Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event.", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "PublicDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4557,7 +4645,7 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.ITLB_MISS", - "BriefDescription": "Retired Instructions who experienced iTLB true miss. Precise Event.", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -4579,8 +4667,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.STLB_MISS", - "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss. Precise Event.", - "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4601,8 +4689,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4623,8 +4711,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4645,8 +4733,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4668,7 +4756,7 @@ "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. \r\n", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4689,8 +4777,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.\r\n", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4711,8 +4799,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.\r\n", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4733,8 +4821,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4755,8 +4843,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4777,8 +4865,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4799,8 +4887,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4821,8 +4909,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.\r\n", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4843,8 +4931,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -4862,11 +4950,33 @@ "Offcore": "0" }, { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x400106", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { "EventCode": "0xC7", "UMask": "0x01", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -4887,8 +4997,8 @@ "EventCode": "0xC7", "UMask": "0x02", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -4909,8 +5019,8 @@ "EventCode": "0xC7", "UMask": "0x04", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -4931,8 +5041,8 @@ "EventCode": "0xC7", "UMask": "0x08", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -4953,8 +5063,8 @@ "EventCode": "0xC7", "UMask": "0x10", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -4975,8 +5085,8 @@ "EventCode": "0xC7", "UMask": "0x20", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5042,7 +5152,7 @@ "UMask": "0x04", "EventName": "HLE_RETIRED.ABORTED", "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ", - "PublicDescription": "Number of times HLE abort was triggered. (PEBS)", + "PublicDescription": "Number of times HLE abort was triggered.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5107,7 +5217,7 @@ "EventCode": "0xC8", "UMask": "0x20", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.). ", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -5218,7 +5328,7 @@ "UMask": "0x04", "EventName": "RTM_RETIRED.ABORTED", "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ", - "PublicDescription": "Number of times RTM abort was triggered. (PEBS)", + "PublicDescription": "Number of times RTM abort was triggered.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5434,7 +5544,7 @@ "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", @@ -5450,13 +5560,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", @@ -5472,13 +5582,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", @@ -5494,13 +5604,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", @@ -5516,13 +5626,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", @@ -5538,13 +5648,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", @@ -5560,13 +5670,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", @@ -5582,13 +5692,13 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", @@ -5604,7 +5714,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "Offcore": "0" @@ -5613,7 +5723,7 @@ "EventCode": "0xD0", "UMask": "0x11", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", - "BriefDescription": "Retired load instructions that miss the STLB. (Precise Event)", + "BriefDescription": "Retired load instructions that miss the STLB.", "PublicDescription": "Retired load instructions that miss the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -5635,7 +5745,7 @@ "EventCode": "0xD0", "UMask": "0x12", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", - "BriefDescription": "Retired store instructions that miss the STLB. (Precise Event)", + "BriefDescription": "Retired store instructions that miss the STLB.", "PublicDescription": "Retired store instructions that miss the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -5657,8 +5767,8 @@ "EventCode": "0xD0", "UMask": "0x21", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", - "BriefDescription": "Retired load instructions with locked access. (Precise Event)", - "PublicDescription": "Retired load instructions with locked access. (Precise Event)", + "BriefDescription": "Retired load instructions with locked access.", + "PublicDescription": "Retired load instructions with locked access.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5679,8 +5789,8 @@ "EventCode": "0xD0", "UMask": "0x41", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", - "BriefDescription": "Retired load instructions that split across a cacheline boundary. (Precise Event)", - "PublicDescription": "Retired load instructions that split across a cacheline boundary. (Precise Event)", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -5701,8 +5811,8 @@ "EventCode": "0xD0", "UMask": "0x42", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", - "BriefDescription": "Retired store instructions that split across a cacheline boundary. (Precise Event)", - "PublicDescription": "Retired store instructions that split across a cacheline boundary. (Precise Event)", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -5723,8 +5833,8 @@ "EventCode": "0xD0", "UMask": "0x81", "EventName": "MEM_INST_RETIRED.ALL_LOADS", - "BriefDescription": "All retired load instructions. (Precise Event)", - "PublicDescription": "All retired load instructions. (Precise Event)", + "BriefDescription": "All retired load instructions.", + "PublicDescription": "All retired load instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5745,7 +5855,7 @@ "EventCode": "0xD0", "UMask": "0x82", "EventName": "MEM_INST_RETIRED.ALL_STORES", - "BriefDescription": "All retired store instructions. (Precise Event)", + "BriefDescription": "All retired store instructions.", "PublicDescription": "All retired store instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -5768,7 +5878,7 @@ "UMask": "0x01", "EventName": "MEM_LOAD_RETIRED.L1_HIT", "BriefDescription": "Retired load instructions with L1 cache hits as data sources", - "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.\r\n", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -5812,7 +5922,7 @@ "UMask": "0x04", "EventName": "MEM_LOAD_RETIRED.L3_HIT", "BriefDescription": "Retired load instructions with L3 cache hits as data sources", - "PublicDescription": "Retired load instructions with L3 cache hits as data sources.", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "50021", @@ -5878,7 +5988,7 @@ "UMask": "0x20", "EventName": "MEM_LOAD_RETIRED.L3_MISS", "BriefDescription": "Retired load instructions missed L3 cache as data sources", - "PublicDescription": "Retired load instructions missed L3 cache as data sources.", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5900,7 +6010,7 @@ "UMask": "0x40", "EventName": "MEM_LOAD_RETIRED.FB_HIT", "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready", - "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. \r\n", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -6141,7 +6251,7 @@ "EventCode": "0xF2", "UMask": "0x04", "EventName": "L2_LINES_OUT.USELESS_PREF", - "BriefDescription": "\nThis event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", + "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", "PublicDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -6212,7 +6322,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFC408000", "TakenAlone": "0", "CounterMask": "0", @@ -6234,7 +6344,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x203C408000", "TakenAlone": "0", "CounterMask": "0", @@ -6256,7 +6366,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103C408000", "TakenAlone": "0", "CounterMask": "0", @@ -6278,7 +6388,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C408000", "TakenAlone": "0", "CounterMask": "0", @@ -6300,7 +6410,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C408000", "TakenAlone": "0", "CounterMask": "0", @@ -6322,7 +6432,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C408000", "TakenAlone": "0", "CounterMask": "0", @@ -6344,7 +6454,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC408000", "TakenAlone": "0", "CounterMask": "0", @@ -6366,7 +6476,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x007C408000", "TakenAlone": "0", "CounterMask": "0", @@ -6388,7 +6498,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC4008000", "TakenAlone": "0", "CounterMask": "0", @@ -6410,7 +6520,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004008000", "TakenAlone": "0", "CounterMask": "0", @@ -6432,7 +6542,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004008000", "TakenAlone": "0", "CounterMask": "0", @@ -6454,7 +6564,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404008000", "TakenAlone": "0", "CounterMask": "0", @@ -6476,7 +6586,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204008000", "TakenAlone": "0", "CounterMask": "0", @@ -6498,7 +6608,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104008000", "TakenAlone": "0", "CounterMask": "0", @@ -6520,7 +6630,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084008000", "TakenAlone": "0", "CounterMask": "0", @@ -6542,7 +6652,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0044008000", "TakenAlone": "0", "CounterMask": "0", @@ -6564,7 +6674,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0408000", "TakenAlone": "0", "CounterMask": "0", @@ -6586,7 +6696,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000408000", "TakenAlone": "0", "CounterMask": "0", @@ -6608,7 +6718,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000408000", "TakenAlone": "0", "CounterMask": "0", @@ -6630,7 +6740,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400408000", "TakenAlone": "0", "CounterMask": "0", @@ -6652,7 +6762,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200408000", "TakenAlone": "0", "CounterMask": "0", @@ -6674,7 +6784,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100408000", "TakenAlone": "0", "CounterMask": "0", @@ -6696,7 +6806,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080408000", "TakenAlone": "0", "CounterMask": "0", @@ -6718,7 +6828,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040408000", "TakenAlone": "0", "CounterMask": "0", @@ -6740,7 +6850,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC01C8000", "TakenAlone": "0", "CounterMask": "0", @@ -6762,7 +6872,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20001C8000", "TakenAlone": "0", "CounterMask": "0", @@ -6784,7 +6894,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001C8000", "TakenAlone": "0", "CounterMask": "0", @@ -6806,7 +6916,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04001C8000", "TakenAlone": "0", "CounterMask": "0", @@ -6828,7 +6938,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02001C8000", "TakenAlone": "0", "CounterMask": "0", @@ -6850,7 +6960,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01001C8000", "TakenAlone": "0", "CounterMask": "0", @@ -6872,7 +6982,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00801C8000", "TakenAlone": "0", "CounterMask": "0", @@ -6894,7 +7004,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00401C8000", "TakenAlone": "0", "CounterMask": "0", @@ -6916,7 +7026,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0108000", "TakenAlone": "0", "CounterMask": "0", @@ -6938,7 +7048,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000108000", "TakenAlone": "0", "CounterMask": "0", @@ -6960,7 +7070,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000108000", "TakenAlone": "0", "CounterMask": "0", @@ -6982,7 +7092,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400108000", "TakenAlone": "0", "CounterMask": "0", @@ -7004,7 +7114,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200108000", "TakenAlone": "0", "CounterMask": "0", @@ -7026,7 +7136,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100108000", "TakenAlone": "0", "CounterMask": "0", @@ -7048,7 +7158,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080108000", "TakenAlone": "0", "CounterMask": "0", @@ -7070,7 +7180,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040108000", "TakenAlone": "0", "CounterMask": "0", @@ -7092,7 +7202,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0088000", "TakenAlone": "0", "CounterMask": "0", @@ -7114,7 +7224,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000088000", "TakenAlone": "0", "CounterMask": "0", @@ -7136,7 +7246,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000088000", "TakenAlone": "0", "CounterMask": "0", @@ -7158,7 +7268,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400088000", "TakenAlone": "0", "CounterMask": "0", @@ -7180,7 +7290,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200088000", "TakenAlone": "0", "CounterMask": "0", @@ -7202,7 +7312,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100088000", "TakenAlone": "0", "CounterMask": "0", @@ -7224,7 +7334,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080088000", "TakenAlone": "0", "CounterMask": "0", @@ -7246,7 +7356,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040088000", "TakenAlone": "0", "CounterMask": "0", @@ -7268,7 +7378,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0048000", "TakenAlone": "0", "CounterMask": "0", @@ -7290,7 +7400,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000048000", "TakenAlone": "0", "CounterMask": "0", @@ -7312,7 +7422,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000048000", "TakenAlone": "0", "CounterMask": "0", @@ -7334,7 +7444,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400048000", "TakenAlone": "0", "CounterMask": "0", @@ -7356,7 +7466,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200048000", "TakenAlone": "0", "CounterMask": "0", @@ -7378,7 +7488,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100048000", "TakenAlone": "0", "CounterMask": "0", @@ -7400,7 +7510,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080048000", "TakenAlone": "0", "CounterMask": "0", @@ -7422,7 +7532,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040048000", "TakenAlone": "0", "CounterMask": "0", @@ -7444,7 +7554,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0028000", "TakenAlone": "0", "CounterMask": "0", @@ -7466,7 +7576,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000028000", "TakenAlone": "0", "CounterMask": "0", @@ -7488,7 +7598,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000028000", "TakenAlone": "0", "CounterMask": "0", @@ -7510,7 +7620,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400028000", "TakenAlone": "0", "CounterMask": "0", @@ -7532,7 +7642,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200028000", "TakenAlone": "0", "CounterMask": "0", @@ -7554,7 +7664,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100028000", "TakenAlone": "0", "CounterMask": "0", @@ -7576,7 +7686,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080028000", "TakenAlone": "0", "CounterMask": "0", @@ -7598,7 +7708,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040028000", "TakenAlone": "0", "CounterMask": "0", @@ -7615,12 +7725,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", - "BriefDescription": "Counts any other requests have any response type. ", - "PublicDescription": "Counts any other requests have any response type.", + "BriefDescription": "Counts any other requestshave any response type. ", + "PublicDescription": "Counts any other requestshave any response type.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000018000", "TakenAlone": "0", "CounterMask": "0", @@ -7637,12 +7747,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFC400004", "TakenAlone": "0", "CounterMask": "0", @@ -7659,12 +7769,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x203C400004", "TakenAlone": "0", "CounterMask": "0", @@ -7681,12 +7791,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103C400004", "TakenAlone": "0", "CounterMask": "0", @@ -7703,12 +7813,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C400004", "TakenAlone": "0", "CounterMask": "0", @@ -7725,12 +7835,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C400004", "TakenAlone": "0", "CounterMask": "0", @@ -7747,12 +7857,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C400004", "TakenAlone": "0", "CounterMask": "0", @@ -7769,12 +7879,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC400004", "TakenAlone": "0", "CounterMask": "0", @@ -7791,12 +7901,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x007C400004", "TakenAlone": "0", "CounterMask": "0", @@ -7813,12 +7923,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC4000004", "TakenAlone": "0", "CounterMask": "0", @@ -7835,12 +7945,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000004", "TakenAlone": "0", "CounterMask": "0", @@ -7857,12 +7967,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000004", "TakenAlone": "0", "CounterMask": "0", @@ -7879,12 +7989,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000004", "TakenAlone": "0", "CounterMask": "0", @@ -7901,12 +8011,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000004", "TakenAlone": "0", "CounterMask": "0", @@ -7923,12 +8033,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000004", "TakenAlone": "0", "CounterMask": "0", @@ -7945,12 +8055,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000004", "TakenAlone": "0", "CounterMask": "0", @@ -7967,12 +8077,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0044000004", "TakenAlone": "0", "CounterMask": "0", @@ -7989,12 +8099,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0400004", "TakenAlone": "0", "CounterMask": "0", @@ -8011,12 +8121,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000400004", "TakenAlone": "0", "CounterMask": "0", @@ -8033,12 +8143,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000400004", "TakenAlone": "0", "CounterMask": "0", @@ -8055,12 +8165,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400400004", "TakenAlone": "0", "CounterMask": "0", @@ -8077,12 +8187,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200400004", "TakenAlone": "0", "CounterMask": "0", @@ -8099,12 +8209,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100400004", "TakenAlone": "0", "CounterMask": "0", @@ -8121,12 +8231,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080400004", "TakenAlone": "0", "CounterMask": "0", @@ -8143,12 +8253,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040400004", "TakenAlone": "0", "CounterMask": "0", @@ -8165,12 +8275,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC01C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8187,12 +8297,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20001C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8209,12 +8319,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8231,12 +8341,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04001C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8253,12 +8363,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02001C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8275,12 +8385,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01001C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8297,12 +8407,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00801C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8319,12 +8429,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00401C0004", "TakenAlone": "0", "CounterMask": "0", @@ -8341,12 +8451,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0100004", "TakenAlone": "0", "CounterMask": "0", @@ -8363,12 +8473,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000100004", "TakenAlone": "0", "CounterMask": "0", @@ -8385,12 +8495,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000100004", "TakenAlone": "0", "CounterMask": "0", @@ -8407,12 +8517,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400100004", "TakenAlone": "0", "CounterMask": "0", @@ -8429,12 +8539,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200100004", "TakenAlone": "0", "CounterMask": "0", @@ -8451,12 +8561,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100100004", "TakenAlone": "0", "CounterMask": "0", @@ -8473,12 +8583,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080100004", "TakenAlone": "0", "CounterMask": "0", @@ -8495,12 +8605,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040100004", "TakenAlone": "0", "CounterMask": "0", @@ -8517,12 +8627,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0080004", "TakenAlone": "0", "CounterMask": "0", @@ -8539,12 +8649,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000080004", "TakenAlone": "0", "CounterMask": "0", @@ -8561,12 +8671,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000080004", "TakenAlone": "0", "CounterMask": "0", @@ -8583,12 +8693,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400080004", "TakenAlone": "0", "CounterMask": "0", @@ -8605,12 +8715,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200080004", "TakenAlone": "0", "CounterMask": "0", @@ -8627,12 +8737,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100080004", "TakenAlone": "0", "CounterMask": "0", @@ -8649,12 +8759,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080080004", "TakenAlone": "0", "CounterMask": "0", @@ -8671,12 +8781,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040080004", "TakenAlone": "0", "CounterMask": "0", @@ -8693,12 +8803,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0040004", "TakenAlone": "0", "CounterMask": "0", @@ -8715,12 +8825,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000040004", "TakenAlone": "0", "CounterMask": "0", @@ -8737,12 +8847,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000040004", "TakenAlone": "0", "CounterMask": "0", @@ -8759,12 +8869,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400040004", "TakenAlone": "0", "CounterMask": "0", @@ -8781,12 +8891,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200040004", "TakenAlone": "0", "CounterMask": "0", @@ -8803,12 +8913,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100040004", "TakenAlone": "0", "CounterMask": "0", @@ -8825,12 +8935,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080040004", "TakenAlone": "0", "CounterMask": "0", @@ -8847,12 +8957,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040040004", "TakenAlone": "0", "CounterMask": "0", @@ -8869,12 +8979,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0020004", "TakenAlone": "0", "CounterMask": "0", @@ -8891,12 +9001,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020004", "TakenAlone": "0", "CounterMask": "0", @@ -8913,12 +9023,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020004", "TakenAlone": "0", "CounterMask": "0", @@ -8935,12 +9045,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020004", "TakenAlone": "0", "CounterMask": "0", @@ -8957,12 +9067,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020004", "TakenAlone": "0", "CounterMask": "0", @@ -8979,12 +9089,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020004", "TakenAlone": "0", "CounterMask": "0", @@ -9001,12 +9111,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020004", "TakenAlone": "0", "CounterMask": "0", @@ -9023,12 +9133,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "Counts all demand code reads ", + "PublicDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040020004", "TakenAlone": "0", "CounterMask": "0", @@ -9045,12 +9155,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any response type. ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any response type.", + "BriefDescription": "Counts all demand code readshave any response type. ", + "PublicDescription": "Counts all demand code readshave any response type.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010004", "TakenAlone": "0", "CounterMask": "0", @@ -9072,7 +9182,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFC400002", "TakenAlone": "0", "CounterMask": "0", @@ -9094,7 +9204,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x203C400002", "TakenAlone": "0", "CounterMask": "0", @@ -9116,7 +9226,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103C400002", "TakenAlone": "0", "CounterMask": "0", @@ -9138,7 +9248,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C400002", "TakenAlone": "0", "CounterMask": "0", @@ -9160,7 +9270,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C400002", "TakenAlone": "0", "CounterMask": "0", @@ -9182,7 +9292,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C400002", "TakenAlone": "0", "CounterMask": "0", @@ -9204,7 +9314,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC400002", "TakenAlone": "0", "CounterMask": "0", @@ -9226,7 +9336,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x007C400002", "TakenAlone": "0", "CounterMask": "0", @@ -9248,7 +9358,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC4000002", "TakenAlone": "0", "CounterMask": "0", @@ -9270,7 +9380,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000002", "TakenAlone": "0", "CounterMask": "0", @@ -9292,7 +9402,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000002", "TakenAlone": "0", "CounterMask": "0", @@ -9314,7 +9424,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000002", "TakenAlone": "0", "CounterMask": "0", @@ -9336,7 +9446,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000002", "TakenAlone": "0", "CounterMask": "0", @@ -9358,7 +9468,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000002", "TakenAlone": "0", "CounterMask": "0", @@ -9380,7 +9490,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000002", "TakenAlone": "0", "CounterMask": "0", @@ -9402,7 +9512,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0044000002", "TakenAlone": "0", "CounterMask": "0", @@ -9424,7 +9534,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0400002", "TakenAlone": "0", "CounterMask": "0", @@ -9446,7 +9556,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000400002", "TakenAlone": "0", "CounterMask": "0", @@ -9468,7 +9578,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000400002", "TakenAlone": "0", "CounterMask": "0", @@ -9490,7 +9600,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400400002", "TakenAlone": "0", "CounterMask": "0", @@ -9512,7 +9622,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200400002", "TakenAlone": "0", "CounterMask": "0", @@ -9534,7 +9644,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100400002", "TakenAlone": "0", "CounterMask": "0", @@ -9556,7 +9666,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080400002", "TakenAlone": "0", "CounterMask": "0", @@ -9578,7 +9688,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040400002", "TakenAlone": "0", "CounterMask": "0", @@ -9600,7 +9710,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC01C0002", "TakenAlone": "0", "CounterMask": "0", @@ -9622,7 +9732,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20001C0002", "TakenAlone": "0", "CounterMask": "0", @@ -9644,7 +9754,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001C0002", "TakenAlone": "0", "CounterMask": "0", @@ -9666,7 +9776,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04001C0002", "TakenAlone": "0", "CounterMask": "0", @@ -9688,7 +9798,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02001C0002", "TakenAlone": "0", "CounterMask": "0", @@ -9710,7 +9820,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01001C0002", "TakenAlone": "0", "CounterMask": "0", @@ -9732,7 +9842,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00801C0002", "TakenAlone": "0", "CounterMask": "0", @@ -9754,7 +9864,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00401C0002", "TakenAlone": "0", "CounterMask": "0", @@ -9776,7 +9886,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0100002", "TakenAlone": "0", "CounterMask": "0", @@ -9798,7 +9908,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000100002", "TakenAlone": "0", "CounterMask": "0", @@ -9820,7 +9930,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000100002", "TakenAlone": "0", "CounterMask": "0", @@ -9842,7 +9952,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400100002", "TakenAlone": "0", "CounterMask": "0", @@ -9864,7 +9974,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200100002", "TakenAlone": "0", "CounterMask": "0", @@ -9886,7 +9996,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100100002", "TakenAlone": "0", "CounterMask": "0", @@ -9908,7 +10018,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080100002", "TakenAlone": "0", "CounterMask": "0", @@ -9930,7 +10040,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040100002", "TakenAlone": "0", "CounterMask": "0", @@ -9952,7 +10062,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0080002", "TakenAlone": "0", "CounterMask": "0", @@ -9974,7 +10084,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000080002", "TakenAlone": "0", "CounterMask": "0", @@ -9996,7 +10106,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000080002", "TakenAlone": "0", "CounterMask": "0", @@ -10018,7 +10128,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400080002", "TakenAlone": "0", "CounterMask": "0", @@ -10040,7 +10150,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200080002", "TakenAlone": "0", "CounterMask": "0", @@ -10062,7 +10172,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100080002", "TakenAlone": "0", "CounterMask": "0", @@ -10084,7 +10194,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080080002", "TakenAlone": "0", "CounterMask": "0", @@ -10106,7 +10216,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040080002", "TakenAlone": "0", "CounterMask": "0", @@ -10128,7 +10238,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0040002", "TakenAlone": "0", "CounterMask": "0", @@ -10150,7 +10260,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000040002", "TakenAlone": "0", "CounterMask": "0", @@ -10172,7 +10282,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000040002", "TakenAlone": "0", "CounterMask": "0", @@ -10194,7 +10304,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400040002", "TakenAlone": "0", "CounterMask": "0", @@ -10216,7 +10326,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200040002", "TakenAlone": "0", "CounterMask": "0", @@ -10238,7 +10348,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100040002", "TakenAlone": "0", "CounterMask": "0", @@ -10260,7 +10370,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080040002", "TakenAlone": "0", "CounterMask": "0", @@ -10282,7 +10392,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040040002", "TakenAlone": "0", "CounterMask": "0", @@ -10304,7 +10414,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0020002", "TakenAlone": "0", "CounterMask": "0", @@ -10326,7 +10436,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020002", "TakenAlone": "0", "CounterMask": "0", @@ -10348,7 +10458,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020002", "TakenAlone": "0", "CounterMask": "0", @@ -10370,7 +10480,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020002", "TakenAlone": "0", "CounterMask": "0", @@ -10392,7 +10502,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020002", "TakenAlone": "0", "CounterMask": "0", @@ -10414,7 +10524,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020002", "TakenAlone": "0", "CounterMask": "0", @@ -10436,7 +10546,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020002", "TakenAlone": "0", "CounterMask": "0", @@ -10458,7 +10568,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040020002", "TakenAlone": "0", "CounterMask": "0", @@ -10475,12 +10585,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "BriefDescription": "Counts all demand data writes (RFOs) have any response type. ", - "PublicDescription": "Counts all demand data writes (RFOs) have any response type.", + "BriefDescription": "Counts all demand data writes (RFOs)have any response type. ", + "PublicDescription": "Counts all demand data writes (RFOs)have any response type.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010002", "TakenAlone": "0", "CounterMask": "0", @@ -10502,7 +10612,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFC400001", "TakenAlone": "0", "CounterMask": "0", @@ -10524,7 +10634,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x203C400001", "TakenAlone": "0", "CounterMask": "0", @@ -10546,7 +10656,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103C400001", "TakenAlone": "0", "CounterMask": "0", @@ -10568,7 +10678,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x043C400001", "TakenAlone": "0", "CounterMask": "0", @@ -10590,7 +10700,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x023C400001", "TakenAlone": "0", "CounterMask": "0", @@ -10612,7 +10722,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x013C400001", "TakenAlone": "0", "CounterMask": "0", @@ -10634,7 +10744,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00BC400001", "TakenAlone": "0", "CounterMask": "0", @@ -10656,7 +10766,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x007C400001", "TakenAlone": "0", "CounterMask": "0", @@ -10678,7 +10788,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC4000001", "TakenAlone": "0", "CounterMask": "0", @@ -10700,7 +10810,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000001", "TakenAlone": "0", "CounterMask": "0", @@ -10722,7 +10832,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000001", "TakenAlone": "0", "CounterMask": "0", @@ -10744,7 +10854,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0404000001", "TakenAlone": "0", "CounterMask": "0", @@ -10766,7 +10876,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0204000001", "TakenAlone": "0", "CounterMask": "0", @@ -10788,7 +10898,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0104000001", "TakenAlone": "0", "CounterMask": "0", @@ -10810,7 +10920,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0084000001", "TakenAlone": "0", "CounterMask": "0", @@ -10832,7 +10942,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0044000001", "TakenAlone": "0", "CounterMask": "0", @@ -10854,7 +10964,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0400001", "TakenAlone": "0", "CounterMask": "0", @@ -10876,7 +10986,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000400001", "TakenAlone": "0", "CounterMask": "0", @@ -10898,7 +11008,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000400001", "TakenAlone": "0", "CounterMask": "0", @@ -10920,7 +11030,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400400001", "TakenAlone": "0", "CounterMask": "0", @@ -10942,7 +11052,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200400001", "TakenAlone": "0", "CounterMask": "0", @@ -10964,7 +11074,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100400001", "TakenAlone": "0", "CounterMask": "0", @@ -10986,7 +11096,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080400001", "TakenAlone": "0", "CounterMask": "0", @@ -11008,7 +11118,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040400001", "TakenAlone": "0", "CounterMask": "0", @@ -11030,7 +11140,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC01C0001", "TakenAlone": "0", "CounterMask": "0", @@ -11052,7 +11162,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20001C0001", "TakenAlone": "0", "CounterMask": "0", @@ -11074,7 +11184,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001C0001", "TakenAlone": "0", "CounterMask": "0", @@ -11096,7 +11206,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04001C0001", "TakenAlone": "0", "CounterMask": "0", @@ -11118,7 +11228,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x02001C0001", "TakenAlone": "0", "CounterMask": "0", @@ -11140,7 +11250,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01001C0001", "TakenAlone": "0", "CounterMask": "0", @@ -11162,7 +11272,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00801C0001", "TakenAlone": "0", "CounterMask": "0", @@ -11184,7 +11294,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x00401C0001", "TakenAlone": "0", "CounterMask": "0", @@ -11206,7 +11316,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0100001", "TakenAlone": "0", "CounterMask": "0", @@ -11228,7 +11338,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000100001", "TakenAlone": "0", "CounterMask": "0", @@ -11250,7 +11360,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000100001", "TakenAlone": "0", "CounterMask": "0", @@ -11272,7 +11382,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400100001", "TakenAlone": "0", "CounterMask": "0", @@ -11294,7 +11404,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200100001", "TakenAlone": "0", "CounterMask": "0", @@ -11316,7 +11426,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100100001", "TakenAlone": "0", "CounterMask": "0", @@ -11338,7 +11448,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080100001", "TakenAlone": "0", "CounterMask": "0", @@ -11360,7 +11470,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040100001", "TakenAlone": "0", "CounterMask": "0", @@ -11382,7 +11492,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0080001", "TakenAlone": "0", "CounterMask": "0", @@ -11404,7 +11514,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000080001", "TakenAlone": "0", "CounterMask": "0", @@ -11426,7 +11536,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000080001", "TakenAlone": "0", "CounterMask": "0", @@ -11448,7 +11558,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400080001", "TakenAlone": "0", "CounterMask": "0", @@ -11470,7 +11580,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200080001", "TakenAlone": "0", "CounterMask": "0", @@ -11492,7 +11602,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100080001", "TakenAlone": "0", "CounterMask": "0", @@ -11514,7 +11624,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080080001", "TakenAlone": "0", "CounterMask": "0", @@ -11536,7 +11646,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040080001", "TakenAlone": "0", "CounterMask": "0", @@ -11558,7 +11668,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0040001", "TakenAlone": "0", "CounterMask": "0", @@ -11580,7 +11690,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000040001", "TakenAlone": "0", "CounterMask": "0", @@ -11602,7 +11712,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000040001", "TakenAlone": "0", "CounterMask": "0", @@ -11624,7 +11734,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400040001", "TakenAlone": "0", "CounterMask": "0", @@ -11646,7 +11756,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200040001", "TakenAlone": "0", "CounterMask": "0", @@ -11668,7 +11778,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100040001", "TakenAlone": "0", "CounterMask": "0", @@ -11690,7 +11800,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080040001", "TakenAlone": "0", "CounterMask": "0", @@ -11712,7 +11822,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040040001", "TakenAlone": "0", "CounterMask": "0", @@ -11734,7 +11844,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0020001", "TakenAlone": "0", "CounterMask": "0", @@ -11756,7 +11866,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020001", "TakenAlone": "0", "CounterMask": "0", @@ -11778,7 +11888,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020001", "TakenAlone": "0", "CounterMask": "0", @@ -11800,7 +11910,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400020001", "TakenAlone": "0", "CounterMask": "0", @@ -11822,7 +11932,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200020001", "TakenAlone": "0", "CounterMask": "0", @@ -11844,7 +11954,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0100020001", "TakenAlone": "0", "CounterMask": "0", @@ -11866,7 +11976,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080020001", "TakenAlone": "0", "CounterMask": "0", @@ -11888,7 +11998,7 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0040020001", "TakenAlone": "0", "CounterMask": "0", @@ -11905,12 +12015,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "BriefDescription": "Counts demand data reads have any response type. ", - "PublicDescription": "Counts demand data reads have any response type.", + "BriefDescription": "Counts demand data readshave any response type. ", + "PublicDescription": "Counts demand data readshave any response type.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010001", "TakenAlone": "0", "CounterMask": "0", diff --git a/usr/src/data/perfmon/SKL/skylake_fp_arith_inst_v42.json b/usr/src/data/perfmon/SKL/skylake_fp_arith_inst_v50.json index a806200f07..a806200f07 100644 --- a/usr/src/data/perfmon/SKL/skylake_fp_arith_inst_v42.json +++ b/usr/src/data/perfmon/SKL/skylake_fp_arith_inst_v50.json diff --git a/usr/src/data/perfmon/SKL/skylake_matrix_bit_definitions_v42.json b/usr/src/data/perfmon/SKL/skylake_matrix_bit_definitions_v42.json deleted file mode 100644 index 96809143d1..0000000000 --- a/usr/src/data/perfmon/SKL/skylake_matrix_bit_definitions_v42.json +++ /dev/null @@ -1,200 +0,0 @@ -[ - { - "BitName": "DEMAND_DATA_RD", - "BitIndex": "0", - "Type": "1", - "Description": "Counts demand data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "DEMAND_RFO", - "BitIndex": "1", - "Type": "1", - "Description": "Counts all demand data writes (RFOs)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "DEMAND_CODE_RD", - "BitIndex": "2", - "Type": "1", - "Description": "Counts all demand code reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "OTHER", - "BitIndex": "15", - "Type": "1", - "Description": "Counts any other requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ANY_RESPONSE", - "BitIndex": "16", - "Type": "2", - "Description": "have any response type.", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SUPPLIER_NONE", - "BitIndex": "17", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_HIT_M", - "BitIndex": "18", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_HIT_E", - "BitIndex": "19", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_HIT_S", - "BitIndex": "20", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_HIT", - "BitIndex": "18,19,20", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L4_HIT_LOCAL_L4", - "BitIndex": "22", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_MISS_LOCAL_DRAM", - "BitIndex": "26", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "L3_MISS", - "BitIndex": "26,27,28,29", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SPL_HIT", - "BitIndex": "30", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NONE", - "BitIndex": "31", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NOT_NEEDED", - "BitIndex": "32", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_MISS", - "BitIndex": "33", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_NO_FWD", - "BitIndex": "34", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_HIT_WITH_FWD", - "BitIndex": "35", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "18,19,20,21", - "Errata": "na" - }, - { - "BitName": "SNOOP_HITM", - "BitIndex": "36", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "SNOOP_NON_DRAM", - "BitIndex": "37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - }, - { - "BitName": "ANY_SNOOP", - "BitIndex": "30,31,32,33,34,35,36,37", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "", - "Errata": "na" - } -]
\ No newline at end of file diff --git a/usr/src/data/perfmon/SKL/skylake_matrix_v42.json b/usr/src/data/perfmon/SKL/skylake_matrix_v50.json index 2986da7200..2986da7200 100644 --- a/usr/src/data/perfmon/SKL/skylake_matrix_v42.json +++ b/usr/src/data/perfmon/SKL/skylake_matrix_v50.json diff --git a/usr/src/data/perfmon/SKL/skylake_uncore_v42.json b/usr/src/data/perfmon/SKL/skylake_uncore_v50.json index f5a0d2a5e0..70e8d38285 100644 --- a/usr/src/data/perfmon/SKL/skylake_uncore_v42.json +++ b/usr/src/data/perfmon/SKL/skylake_uncore_v50.json @@ -180,7 +180,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x80", "UMask": "0x01", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", @@ -192,7 +192,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x81", "UMask": "0x01", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", @@ -204,7 +204,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x81", "UMask": "0x02", "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", @@ -216,7 +216,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x81", "UMask": "0x20", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", @@ -228,7 +228,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x84", "UMask": "0x01", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", @@ -240,7 +240,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x80", "UMask": "0x01", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", @@ -252,7 +252,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x80", "UMask": "0x02", "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ", @@ -264,7 +264,7 @@ "EdgeDetect": "0" }, { - "Unit": "iMPH-U", + "Unit": "ARB", "EventCode": "0x81", "UMask": "0x02", "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ", diff --git a/usr/src/data/perfmon/SKX/skylakex_core_v1.12.json b/usr/src/data/perfmon/SKX/skylakex_core_v1.24.json index 55e5302906..012d9e9bae 100644 --- a/usr/src/data/perfmon/SKX/skylakex_core_v1.12.json +++ b/usr/src/data/perfmon/SKX/skylakex_core_v1.24.json @@ -99,8 +99,8 @@ "EventCode": "0x03", "UMask": "0x02", "EventName": "LD_BLOCKS.STORE_FORWARD", - "BriefDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded .", - "PublicDescription": "Counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations,c. preceding lock RMW operations are not forwarded,d. store has the no-forward bit set (uncacheable/page-split/masked stores),e. all-blocking stores are used (mostly, fences and port I/O), and others.The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide.", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -196,7 +196,7 @@ "UMask": "0x02", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "BriefDescription": "Page walk completed due to a demand data load to a 4K page", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -220,7 +220,7 @@ "UMask": "0x04", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -244,7 +244,7 @@ "UMask": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "BriefDescription": "Page walk completed due to a demand data load to a 1G page", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -265,10 +265,10 @@ }, { "EventCode": "0x08", - "UMask": "0x0E", + "UMask": "0x0e", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -291,8 +291,8 @@ "EventCode": "0x08", "UMask": "0x10", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", - "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ", - "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture. ", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", + "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -315,7 +315,7 @@ "EventCode": "0x08", "UMask": "0x10", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -360,6 +360,30 @@ "Deprecated": "0" }, { + "EventCode": "0x09", + "UMask": "0x01", + "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", + "BriefDescription": "tbd", + "PublicDescription": "tbd", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "ELLC": "0", + "Offcore": "0", + "Deprecated": "0" + }, + { "EventCode": "0x0D", "UMask": "0x01", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -484,7 +508,7 @@ "UMask": "0x02", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", - "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to “Mixing Intel AVX and Intel SSE Code” section of the Optimization Guide.", + "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -1036,7 +1060,7 @@ "UMask": "0x41", "EventName": "LONGEST_LAT_CACHE.MISS", "BriefDescription": "Core-originated cacheable demand requests missed L3", - "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.\r\n", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1060,7 +1084,7 @@ "UMask": "0x4F", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "BriefDescription": "Core-originated cacheable demand requests that refer to L3", - "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3.\r\n", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1255,7 +1279,7 @@ "PublicDescription": "Core crystal clock cycles when the thread is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1279,7 +1303,7 @@ "PublicDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1303,7 +1327,7 @@ "PublicDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1327,7 +1351,7 @@ "PublicDescription": "Core crystal clock cycles when the thread is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1351,7 +1375,7 @@ "PublicDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "25003", "MSRIndex": "0", "MSRValue": "0", "TakenAlone": "0", @@ -1375,7 +1399,7 @@ "PublicDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2503", + "SampleAfterValue": "25003", "MSRIndex": "0x00", "MSRValue": "0x00", "TakenAlone": "0", @@ -1516,7 +1540,7 @@ "UMask": "0x02", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "BriefDescription": "Page walk completed due to a demand data store to a 4K page", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1540,7 +1564,7 @@ "UMask": "0x04", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1564,7 +1588,7 @@ "UMask": "0x08", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "BriefDescription": "Page walk completed due to a demand data store to a 1G page", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages. The page walks can end with or without a page fault.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1585,10 +1609,10 @@ }, { "EventCode": "0x49", - "UMask": "0x0E", + "UMask": "0x0e", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -1611,8 +1635,8 @@ "EventCode": "0x49", "UMask": "0x10", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", - "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ", - "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture. ", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", + "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -1635,7 +1659,7 @@ "EventCode": "0x49", "UMask": "0x10", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -1704,7 +1728,7 @@ "Deprecated": "0" }, { - "EventCode": "0x4F", + "EventCode": "0x4f", "UMask": "0x10", "EventName": "EPT.WALK_PENDING", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", @@ -2187,7 +2211,7 @@ "EventCode": "0x60", "UMask": "0x02", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle. ", + "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.", "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -2836,7 +2860,7 @@ "UMask": "0x02", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", - "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2860,7 +2884,7 @@ "UMask": "0x04", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2884,7 +2908,7 @@ "UMask": "0x08", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", - "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2905,10 +2929,10 @@ }, { "EventCode": "0x85", - "UMask": "0x0E", + "UMask": "0x0e", "EventName": "ITLB_MISSES.WALK_COMPLETED", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -2931,8 +2955,8 @@ "EventCode": "0x85", "UMask": "0x10", "EventName": "ITLB_MISSES.WALK_PENDING", - "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake. ", - "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture. ", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", + "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -3148,7 +3172,7 @@ "UMask": "0x01", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.", + "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -3841,10 +3865,34 @@ }, { "EventCode": "0xAB", + "UMask": "0x01", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "ELLC": "0", + "Offcore": "0", + "Deprecated": "0" + }, + { + "EventCode": "0xAB", "UMask": "0x02", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", - "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cycles.", + "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -4608,10 +4656,34 @@ "Deprecated": "0" }, { + "EventCode": "0xc2", + "UMask": "0x04", + "EventName": "UOPS_RETIRED.MACRO_FUSED", + "BriefDescription": "Number of macro-fused uops retired. (non precise)", + "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "ELLC": "0", + "Offcore": "0", + "Deprecated": "0" + }, + { "EventCode": "0xC3", "UMask": "0x01", "EventName": "MACHINE_CLEARS.COUNT", - "BriefDescription": "Number of machine clears (nukes) of any type. ", + "BriefDescription": "Number of machine clears (nukes) of any type.", "PublicDescription": "Number of machine clears (nukes) of any type.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -4708,7 +4780,7 @@ "UMask": "0x01", "EventName": "BR_INST_RETIRED.CONDITIONAL", "BriefDescription": "Conditional branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.", + "PublicDescription": "This event counts conditional branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4732,7 +4804,7 @@ "UMask": "0x02", "EventName": "BR_INST_RETIRED.NEAR_CALL", "BriefDescription": "Direct and indirect near call instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.", + "PublicDescription": "This event counts both direct and indirect near call instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -4755,7 +4827,7 @@ "EventCode": "0xC4", "UMask": "0x04", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "BriefDescription": "All (macro) branch instructions retired. ", + "BriefDescription": "All (macro) branch instructions retired.", "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -4780,7 +4852,7 @@ "UMask": "0x08", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "BriefDescription": "Return instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.", + "PublicDescription": "This event counts return instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -4803,8 +4875,8 @@ "EventCode": "0xC4", "UMask": "0x10", "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "BriefDescription": "Counts all not taken macro branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired.", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "This event counts not taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4815,7 +4887,31 @@ "Invert": "0", "AnyThread": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SKL091", + "ELLC": "0", + "Offcore": "0", + "Deprecated": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "This event counts not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0", + "MSRValue": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "SKL091", @@ -4828,7 +4924,7 @@ "UMask": "0x20", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "BriefDescription": "Taken branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.", + "PublicDescription": "This event counts taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4851,8 +4947,8 @@ "EventCode": "0xC4", "UMask": "0x40", "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "BriefDescription": "Counts the number of far branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired.", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "This event counts far branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100007", @@ -4900,7 +4996,7 @@ "UMask": "0x01", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "BriefDescription": "Mispredicted conditional branch instructions retired.", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.", + "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4924,7 +5020,7 @@ "UMask": "0x02", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "BriefDescription": "Mispredicted direct and indirect near call instructions retired.", - "PublicDescription": "This event counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.", + "PublicDescription": "Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", @@ -4947,7 +5043,7 @@ "EventCode": "0xC5", "UMask": "0x04", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "BriefDescription": "Mispredicted macro branch instructions retired. ", + "BriefDescription": "Mispredicted macro branch instructions retired.", "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -4971,7 +5067,7 @@ "EventCode": "0xC5", "UMask": "0x20", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken. ", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -4995,8 +5091,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5019,8 +5115,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5043,8 +5139,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5067,8 +5163,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.STLB_MISS", - "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss. Precise Event.", - "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5091,7 +5187,7 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.ITLB_MISS", - "BriefDescription": "Retired Instructions who experienced iTLB true miss. Precise Event.", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -5115,8 +5211,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.L2_MISS", - "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event.", - "PublicDescription": "Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event.", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "PublicDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5139,8 +5235,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.L1I_MISS", - "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event.", - "PublicDescription": "Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event.", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "PublicDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5163,8 +5259,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.DSB_MISS", - "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss. Precise Event.", - "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. \r\n", + "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss.", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5187,8 +5283,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5211,8 +5307,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.\r\n", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5235,8 +5331,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5259,8 +5355,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5283,8 +5379,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5307,8 +5403,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5331,8 +5427,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.\r\n", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5355,8 +5451,8 @@ "EventCode": "0xC6", "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall. Precise Event.", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.\r\n", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5380,7 +5476,7 @@ "UMask": "0x01", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. \r\n", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -5400,11 +5496,35 @@ "Deprecated": "0" }, { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x400106", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "ELLC": "0", + "Offcore": "0", + "Deprecated": "0" + }, + { "EventCode": "0xC7", "UMask": "0x01", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5427,8 +5547,8 @@ "EventCode": "0xC7", "UMask": "0x02", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5451,8 +5571,8 @@ "EventCode": "0xC7", "UMask": "0x04", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5475,8 +5595,8 @@ "EventCode": "0xC7", "UMask": "0x08", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5499,8 +5619,8 @@ "EventCode": "0xC7", "UMask": "0x10", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5523,8 +5643,8 @@ "EventCode": "0xC7", "UMask": "0x20", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5547,8 +5667,8 @@ "EventCode": "0xC7", "UMask": "0x40", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", - "BriefDescription": "Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8)", - "PublicDescription": "Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8)", + "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5571,8 +5691,8 @@ "EventCode": "0xC7", "UMask": "0x80", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", - "BriefDescription": "Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16)", - "PublicDescription": "Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16)", + "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5644,7 +5764,7 @@ "UMask": "0x04", "EventName": "HLE_RETIRED.ABORTED", "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ", - "PublicDescription": "Number of times HLE abort was triggered. (PEBS)", + "PublicDescription": "Number of times HLE abort was triggered.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -5715,7 +5835,7 @@ "EventCode": "0xC8", "UMask": "0x20", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.). ", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -5836,7 +5956,7 @@ "UMask": "0x04", "EventName": "RTM_RETIRED.ABORTED", "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ", - "PublicDescription": "Number of times RTM abort was triggered. (PEBS)", + "PublicDescription": "Number of times RTM abort was triggered.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -6072,7 +6192,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", @@ -6088,7 +6208,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6096,7 +6216,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", @@ -6112,7 +6232,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6120,7 +6240,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", @@ -6136,7 +6256,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6144,7 +6264,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", @@ -6160,7 +6280,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6168,7 +6288,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", @@ -6184,7 +6304,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6192,7 +6312,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", @@ -6208,7 +6328,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6216,7 +6336,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", @@ -6232,7 +6352,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6240,7 +6360,7 @@ "Deprecated": "0" }, { - "EventCode": "0xCD", + "EventCode": "0xcd", "UMask": "0x01", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", @@ -6256,7 +6376,7 @@ "AnyThread": "0", "EdgeDetect": "0", "PEBS": "2", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "0", "ELLC": "0", @@ -6267,7 +6387,7 @@ "EventCode": "0xD0", "UMask": "0x11", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", - "BriefDescription": "Retired load instructions that miss the STLB. (Precise Event)", + "BriefDescription": "Retired load instructions that miss the STLB.", "PublicDescription": "Retired load instructions that miss the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -6291,7 +6411,7 @@ "EventCode": "0xD0", "UMask": "0x12", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", - "BriefDescription": "Retired store instructions that miss the STLB. (Precise Event)", + "BriefDescription": "Retired store instructions that miss the STLB.", "PublicDescription": "Retired store instructions that miss the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -6315,8 +6435,8 @@ "EventCode": "0xD0", "UMask": "0x21", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", - "BriefDescription": "Retired load instructions with locked access. (Precise Event)", - "PublicDescription": "Retired load instructions with locked access. (Precise Event)", + "BriefDescription": "Retired load instructions with locked access.", + "PublicDescription": "Retired load instructions with locked access.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -6339,8 +6459,8 @@ "EventCode": "0xD0", "UMask": "0x41", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", - "BriefDescription": "Retired load instructions that split across a cacheline boundary. (Precise Event)", - "PublicDescription": "Retired load instructions that split across a cacheline boundary. (Precise Event)", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6363,8 +6483,8 @@ "EventCode": "0xD0", "UMask": "0x42", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", - "BriefDescription": "Retired store instructions that split across a cacheline boundary. (Precise Event)", - "PublicDescription": "Retired store instructions that split across a cacheline boundary. (Precise Event)", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", @@ -6387,8 +6507,8 @@ "EventCode": "0xD0", "UMask": "0x81", "EventName": "MEM_INST_RETIRED.ALL_LOADS", - "BriefDescription": "All retired load instructions. (Precise Event)", - "PublicDescription": "All retired load instructions. (Precise Event)", + "BriefDescription": "All retired load instructions.", + "PublicDescription": "All retired load instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6411,7 +6531,7 @@ "EventCode": "0xD0", "UMask": "0x82", "EventName": "MEM_INST_RETIRED.ALL_STORES", - "BriefDescription": "All retired store instructions. (Precise Event)", + "BriefDescription": "All retired store instructions.", "PublicDescription": "All retired store instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", @@ -6436,7 +6556,7 @@ "UMask": "0x01", "EventName": "MEM_LOAD_RETIRED.L1_HIT", "BriefDescription": "Retired load instructions with L1 cache hits as data sources", - "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.\r\n", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "2000003", @@ -6484,7 +6604,7 @@ "UMask": "0x04", "EventName": "MEM_LOAD_RETIRED.L3_HIT", "BriefDescription": "Retired load instructions with L3 cache hits as data sources", - "PublicDescription": "Retired load instructions with L3 cache hits as data sources.", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "50021", @@ -6556,7 +6676,7 @@ "UMask": "0x20", "EventName": "MEM_LOAD_RETIRED.L3_MISS", "BriefDescription": "Retired load instructions missed L3 cache as data sources", - "PublicDescription": "Retired load instructions missed L3 cache as data sources.", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -6580,7 +6700,7 @@ "UMask": "0x40", "EventName": "MEM_LOAD_RETIRED.FB_HIT", "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready", - "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. \r\n", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -6700,7 +6820,7 @@ "UMask": "0x01", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", - "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", + "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -6748,7 +6868,7 @@ "UMask": "0x04", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", "BriefDescription": "Retired load instructions whose data sources was remote HITM", - "PublicDescription": "Retired load instructions whose data sources was remote HITM", + "PublicDescription": "Retired load instructions whose data sources was remote HITM.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -6772,7 +6892,7 @@ "UMask": "0x08", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache", - "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache", + "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100007", @@ -7060,7 +7180,7 @@ "UMask": "0x01", "EventName": "L2_LINES_OUT.SILENT", "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.", - "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", @@ -7084,7 +7204,7 @@ "UMask": "0x02", "EventName": "L2_LINES_OUT.NON_SILENT", "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped", - "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", + "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", @@ -7107,7 +7227,7 @@ "EventCode": "0xF2", "UMask": "0x04", "EventName": "L2_LINES_OUT.USELESS_PREF", - "BriefDescription": "\nThis event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", + "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", "PublicDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -7227,12 +7347,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "BriefDescription": "Counts demand data reads have any response type. ", - "PublicDescription": "Counts demand data reads have any response type.", + "BriefDescription": "Counts demand data reads that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010001", "TakenAlone": "0", "CounterMask": "0", @@ -7251,12 +7371,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand data reads TBD TBD ", - "PublicDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7275,12 +7395,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand data reads TBD TBD ", - "PublicDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7299,12 +7419,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts demand data reads TBD TBD ", - "PublicDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7323,12 +7443,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD TBD ", - "PublicDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0001", "TakenAlone": "0", "CounterMask": "0", @@ -7347,12 +7467,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts demand data reads TBD TBD ", - "PublicDescription": "Counts demand data reads TBD TBD", + "BriefDescription": "Counts demand data reads that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000001", "TakenAlone": "0", "CounterMask": "0", @@ -7371,12 +7491,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts demand data reads TBD ", - "PublicDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00001", "TakenAlone": "0", "CounterMask": "0", @@ -7395,12 +7515,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts demand data reads TBD ", - "PublicDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00001", "TakenAlone": "0", "CounterMask": "0", @@ -7419,12 +7539,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts demand data reads TBD ", - "PublicDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00001", "TakenAlone": "0", "CounterMask": "0", @@ -7443,12 +7563,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts demand data reads TBD ", - "PublicDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800001", "TakenAlone": "0", "CounterMask": "0", @@ -7467,12 +7587,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts demand data reads TBD ", - "PublicDescription": "Counts demand data reads TBD", + "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000001", "TakenAlone": "0", "CounterMask": "0", @@ -7491,12 +7611,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "BriefDescription": "Counts all demand data writes (RFOs) have any response type. ", - "PublicDescription": "Counts all demand data writes (RFOs) have any response type.", + "BriefDescription": "Counts all demand data writes (RFOs) that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010002", "TakenAlone": "0", "CounterMask": "0", @@ -7515,12 +7635,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -7539,12 +7659,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -7563,12 +7683,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0002", "TakenAlone": "0", "CounterMask": "0", @@ -7587,12 +7707,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0002", "TakenAlone": "0", "CounterMask": "0", @@ -7611,12 +7731,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000002", "TakenAlone": "0", "CounterMask": "0", @@ -7635,12 +7755,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00002", "TakenAlone": "0", "CounterMask": "0", @@ -7659,12 +7779,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts all demand data writes (RFOs) TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00002", "TakenAlone": "0", "CounterMask": "0", @@ -7683,12 +7803,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00002", "TakenAlone": "0", "CounterMask": "0", @@ -7707,12 +7827,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800002", "TakenAlone": "0", "CounterMask": "0", @@ -7731,12 +7851,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) TBD ", - "PublicDescription": "Counts all demand data writes (RFOs) TBD", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000002", "TakenAlone": "0", "CounterMask": "0", @@ -7755,12 +7875,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any response type. ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any response type.", + "BriefDescription": "Counts all demand code reads that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010004", "TakenAlone": "0", "CounterMask": "0", @@ -7779,12 +7899,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD", + "BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -7803,12 +7923,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -7827,12 +7947,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0004", "TakenAlone": "0", "CounterMask": "0", @@ -7851,12 +7971,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD", + "BriefDescription": "Counts all demand code reads that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0004", "TakenAlone": "0", "CounterMask": "0", @@ -7875,12 +7995,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD", + "BriefDescription": "Counts all demand code reads that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000004", "TakenAlone": "0", "CounterMask": "0", @@ -7899,12 +8019,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00004", "TakenAlone": "0", "CounterMask": "0", @@ -7923,12 +8043,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00004", "TakenAlone": "0", "CounterMask": "0", @@ -7947,12 +8067,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00004", "TakenAlone": "0", "CounterMask": "0", @@ -7971,12 +8091,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800004", "TakenAlone": "0", "CounterMask": "0", @@ -7995,12 +8115,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000004", "TakenAlone": "0", "CounterMask": "0", @@ -8019,12 +8139,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type. ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010010", "TakenAlone": "0", "CounterMask": "0", @@ -8043,12 +8163,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0010", "TakenAlone": "0", "CounterMask": "0", @@ -8067,12 +8187,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0010", "TakenAlone": "0", "CounterMask": "0", @@ -8091,12 +8211,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0010", "TakenAlone": "0", "CounterMask": "0", @@ -8115,12 +8235,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0010", "TakenAlone": "0", "CounterMask": "0", @@ -8139,12 +8259,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000010", "TakenAlone": "0", "CounterMask": "0", @@ -8163,12 +8283,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00010", "TakenAlone": "0", "CounterMask": "0", @@ -8187,12 +8307,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00010", "TakenAlone": "0", "CounterMask": "0", @@ -8211,12 +8331,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00010", "TakenAlone": "0", "CounterMask": "0", @@ -8235,12 +8355,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800010", "TakenAlone": "0", "CounterMask": "0", @@ -8259,12 +8379,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000010", "TakenAlone": "0", "CounterMask": "0", @@ -8283,12 +8403,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type. ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010020", "TakenAlone": "0", "CounterMask": "0", @@ -8307,12 +8427,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0020", "TakenAlone": "0", "CounterMask": "0", @@ -8331,12 +8451,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0020", "TakenAlone": "0", "CounterMask": "0", @@ -8355,12 +8475,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0020", "TakenAlone": "0", "CounterMask": "0", @@ -8379,12 +8499,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0020", "TakenAlone": "0", "CounterMask": "0", @@ -8403,12 +8523,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000020", "TakenAlone": "0", "CounterMask": "0", @@ -8427,12 +8547,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00020", "TakenAlone": "0", "CounterMask": "0", @@ -8451,12 +8571,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00020", "TakenAlone": "0", "CounterMask": "0", @@ -8475,12 +8595,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00020", "TakenAlone": "0", "CounterMask": "0", @@ -8499,12 +8619,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800020", "TakenAlone": "0", "CounterMask": "0", @@ -8523,12 +8643,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000020", "TakenAlone": "0", "CounterMask": "0", @@ -8547,12 +8667,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type. ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010080", "TakenAlone": "0", "CounterMask": "0", @@ -8571,12 +8691,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0080", "TakenAlone": "0", "CounterMask": "0", @@ -8595,12 +8715,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0080", "TakenAlone": "0", "CounterMask": "0", @@ -8619,12 +8739,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0080", "TakenAlone": "0", "CounterMask": "0", @@ -8643,12 +8763,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0080", "TakenAlone": "0", "CounterMask": "0", @@ -8667,12 +8787,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000080", "TakenAlone": "0", "CounterMask": "0", @@ -8691,12 +8811,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00080", "TakenAlone": "0", "CounterMask": "0", @@ -8715,12 +8835,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00080", "TakenAlone": "0", "CounterMask": "0", @@ -8739,12 +8859,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00080", "TakenAlone": "0", "CounterMask": "0", @@ -8763,12 +8883,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800080", "TakenAlone": "0", "CounterMask": "0", @@ -8787,12 +8907,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000080", "TakenAlone": "0", "CounterMask": "0", @@ -8811,12 +8931,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type. ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010100", "TakenAlone": "0", "CounterMask": "0", @@ -8835,12 +8955,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0100", "TakenAlone": "0", "CounterMask": "0", @@ -8859,12 +8979,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0100", "TakenAlone": "0", "CounterMask": "0", @@ -8883,12 +9003,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0100", "TakenAlone": "0", "CounterMask": "0", @@ -8907,12 +9027,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0100", "TakenAlone": "0", "CounterMask": "0", @@ -8931,12 +9051,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000100", "TakenAlone": "0", "CounterMask": "0", @@ -8955,12 +9075,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00100", "TakenAlone": "0", "CounterMask": "0", @@ -8979,12 +9099,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00100", "TakenAlone": "0", "CounterMask": "0", @@ -9003,12 +9123,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00100", "TakenAlone": "0", "CounterMask": "0", @@ -9027,12 +9147,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800100", "TakenAlone": "0", "CounterMask": "0", @@ -9051,12 +9171,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000100", "TakenAlone": "0", "CounterMask": "0", @@ -9075,12 +9195,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type. ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010400", "TakenAlone": "0", "CounterMask": "0", @@ -9099,12 +9219,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0400", "TakenAlone": "0", "CounterMask": "0", @@ -9123,12 +9243,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0400", "TakenAlone": "0", "CounterMask": "0", @@ -9147,12 +9267,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0400", "TakenAlone": "0", "CounterMask": "0", @@ -9171,12 +9291,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0400", "TakenAlone": "0", "CounterMask": "0", @@ -9195,12 +9315,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000400", "TakenAlone": "0", "CounterMask": "0", @@ -9219,12 +9339,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00400", "TakenAlone": "0", "CounterMask": "0", @@ -9243,12 +9363,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00400", "TakenAlone": "0", "CounterMask": "0", @@ -9267,12 +9387,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00400", "TakenAlone": "0", "CounterMask": "0", @@ -9291,12 +9411,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800400", "TakenAlone": "0", "CounterMask": "0", @@ -9315,12 +9435,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000400", "TakenAlone": "0", "CounterMask": "0", @@ -9339,12 +9459,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", - "BriefDescription": "TBD have any response type. ", - "PublicDescription": "TBD have any response type.", + "BriefDescription": "Counts all prefetch data reads that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010490", "TakenAlone": "0", "CounterMask": "0", @@ -9363,12 +9483,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0490", "TakenAlone": "0", "CounterMask": "0", @@ -9387,12 +9507,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0490", "TakenAlone": "0", "CounterMask": "0", @@ -9411,12 +9531,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0490", "TakenAlone": "0", "CounterMask": "0", @@ -9435,12 +9555,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all prefetch data reads that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0490", "TakenAlone": "0", "CounterMask": "0", @@ -9459,12 +9579,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all prefetch data reads that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000490", "TakenAlone": "0", "CounterMask": "0", @@ -9483,12 +9603,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00490", "TakenAlone": "0", "CounterMask": "0", @@ -9507,12 +9627,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00490", "TakenAlone": "0", "CounterMask": "0", @@ -9531,12 +9651,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00490", "TakenAlone": "0", "CounterMask": "0", @@ -9555,12 +9675,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800490", "TakenAlone": "0", "CounterMask": "0", @@ -9579,12 +9699,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000490", "TakenAlone": "0", "CounterMask": "0", @@ -9603,12 +9723,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", - "BriefDescription": "TBD have any response type. ", - "PublicDescription": "TBD have any response type.", + "BriefDescription": "Counts prefetch RFOs that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010120", "TakenAlone": "0", "CounterMask": "0", @@ -9627,12 +9747,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0120", "TakenAlone": "0", "CounterMask": "0", @@ -9651,12 +9771,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0120", "TakenAlone": "0", "CounterMask": "0", @@ -9675,12 +9795,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0120", "TakenAlone": "0", "CounterMask": "0", @@ -9699,12 +9819,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts prefetch RFOs that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0120", "TakenAlone": "0", "CounterMask": "0", @@ -9723,12 +9843,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts prefetch RFOs that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000120", "TakenAlone": "0", "CounterMask": "0", @@ -9747,12 +9867,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00120", "TakenAlone": "0", "CounterMask": "0", @@ -9771,12 +9891,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00120", "TakenAlone": "0", "CounterMask": "0", @@ -9795,12 +9915,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00120", "TakenAlone": "0", "CounterMask": "0", @@ -9819,12 +9939,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800120", "TakenAlone": "0", "CounterMask": "0", @@ -9843,12 +9963,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000120", "TakenAlone": "0", "CounterMask": "0", @@ -9867,12 +9987,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", - "BriefDescription": "TBD have any response type. ", - "PublicDescription": "TBD have any response type.", + "BriefDescription": "Counts all demand & prefetch data reads that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010491", "TakenAlone": "0", "CounterMask": "0", @@ -9891,12 +10011,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0491", "TakenAlone": "0", "CounterMask": "0", @@ -9915,12 +10035,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0491", "TakenAlone": "0", "CounterMask": "0", @@ -9939,12 +10059,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0491", "TakenAlone": "0", "CounterMask": "0", @@ -9963,12 +10083,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0491", "TakenAlone": "0", "CounterMask": "0", @@ -9987,12 +10107,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000491", "TakenAlone": "0", "CounterMask": "0", @@ -10011,12 +10131,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00491", "TakenAlone": "0", "CounterMask": "0", @@ -10035,12 +10155,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00491", "TakenAlone": "0", "CounterMask": "0", @@ -10059,12 +10179,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00491", "TakenAlone": "0", "CounterMask": "0", @@ -10083,12 +10203,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800491", "TakenAlone": "0", "CounterMask": "0", @@ -10107,12 +10227,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000491", "TakenAlone": "0", "CounterMask": "0", @@ -10131,12 +10251,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", - "BriefDescription": "TBD have any response type. ", - "PublicDescription": "TBD have any response type.", + "BriefDescription": "Counts all demand & prefetch RFOs that have any response type.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010122", "TakenAlone": "0", "CounterMask": "0", @@ -10155,12 +10275,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x01003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -10179,12 +10299,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x04003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -10203,12 +10323,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0122", "TakenAlone": "0", "CounterMask": "0", @@ -10227,12 +10347,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0122", "TakenAlone": "0", "CounterMask": "0", @@ -10251,12 +10371,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", - "BriefDescription": "TBD TBD TBD ", - "PublicDescription": "TBD TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000122", "TakenAlone": "0", "CounterMask": "0", @@ -10275,12 +10395,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x083FC00122", "TakenAlone": "0", "CounterMask": "0", @@ -10299,12 +10419,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00122", "TakenAlone": "0", "CounterMask": "0", @@ -10323,12 +10443,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063FC00122", "TakenAlone": "0", "CounterMask": "0", @@ -10347,12 +10467,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x063B800122", "TakenAlone": "0", "CounterMask": "0", @@ -10371,12 +10491,12 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BriefDescription": "TBD TBD ", - "PublicDescription": "TBD TBD", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0604000122", "TakenAlone": "0", "CounterMask": "0", @@ -10395,13 +10515,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "Counts demand data reads ", - "PublicDescription": "Counts demand data reads", + "BriefDescription": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0001", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0001", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10419,13 +10539,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "Counts all demand data writes (RFOs) ", - "PublicDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0002", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0002", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10443,13 +10563,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that", + "BriefDescription": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0004", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0004", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10467,13 +10587,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads ", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads", + "BriefDescription": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0010", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0010", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10491,13 +10611,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs ", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", + "BriefDescription": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0020", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0020", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10515,13 +10635,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "BriefDescription": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0080", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0080", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10539,13 +10659,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs ", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "BriefDescription": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0100", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0100", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10563,13 +10683,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests ", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "BriefDescription": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0400", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0400", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10587,13 +10707,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "TBD ", - "PublicDescription": "TBD", + "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0490", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0490", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10611,13 +10731,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "TBD ", - "PublicDescription": "TBD", + "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0120", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0120", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10635,13 +10755,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "TBD ", - "PublicDescription": "TBD", + "BriefDescription": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0491", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0491", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -10659,13 +10779,13 @@ "EventCode": "0xB7, 0xBB", "UMask": "0x01", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "BriefDescription": "TBD ", - "PublicDescription": "TBD", + "BriefDescription": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "SampleAfterValue": "100003", - "MSRIndex": "0", - "MSRValue": "0x08007C0122", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08003C0122", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", diff --git a/usr/src/data/perfmon/SKX/skylakex_fp_arith_inst_v1.12.json b/usr/src/data/perfmon/SKX/skylakex_fp_arith_inst_v1.24.json index 755a67d136..755a67d136 100644 --- a/usr/src/data/perfmon/SKX/skylakex_fp_arith_inst_v1.12.json +++ b/usr/src/data/perfmon/SKX/skylakex_fp_arith_inst_v1.24.json diff --git a/usr/src/data/perfmon/SKX/skylakex_matrix_bit_definitions_v1.12.json b/usr/src/data/perfmon/SKX/skylakex_matrix_bit_definitions_v1.12.json deleted file mode 100644 index 3ef29a082f..0000000000 --- a/usr/src/data/perfmon/SKX/skylakex_matrix_bit_definitions_v1.12.json +++ /dev/null @@ -1,362 +0,0 @@ -[ - { - "BitName": "DEMAND_DATA_RD", - "BitIndex": "0", - "Type": "1", - "Description": "Counts demand data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "DEMAND_RFO", - "BitIndex": "1", - "Type": "1", - "Description": "Counts all demand data writes (RFOs)", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "DEMAND_CODE_RD", - "BitIndex": "2", - "Type": "1", - "Description": "Counts demand instruction fetches and L1 instruction cache prefetches that", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_L2_DATA_RD", - "BitIndex": "4", - "Type": "1", - "Description": "Counts prefetch (that bring data to L2) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_L2_RFO", - "BitIndex": "5", - "Type": "1", - "Description": "Counts all prefetch (that bring data to L2) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_L3_DATA_RD", - "BitIndex": "7", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) data reads", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_L3_RFO", - "BitIndex": "8", - "Type": "1", - "Description": "Counts all prefetch (that bring data to LLC only) RFOs", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "PF_L1D_AND_SW", - "BitIndex": "10", - "Type": "1", - "Description": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "OTHER", - "BitIndex": "15", - "Type": "1", - "Description": "Counts any other requests", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "ALL_PF_DATA_RD", - "BitIndex": "4,7,10", - "Type": "1", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "ALL_PF_RFO", - "BitIndex": "5,8", - "Type": "1", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "ALL_DATA_RD", - "BitIndex": "0,4,7,10", - "Type": "1", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "ALL_RFO", - "BitIndex": "1,5,8", - "Type": "1", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "ALL_READS", - "BitIndex": "0,1,2,4,5,6,7,8,9,10", - "Type": "1", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "ANY_RESPONSE", - "BitIndex": "16", - "Type": "2", - "Description": "have any response type.", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SUPPLIER_NONE", - "BitIndex": "17", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT_M", - "BitIndex": "18", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT_E", - "BitIndex": "19", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT_S", - "BitIndex": "20", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT_F", - "BitIndex": "21", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT", - "BitIndex": "18,19,20,21", - "Type": "3", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_MISS_LOCAL_DRAM", - "BitIndex": "26", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_MISS_REMOTE_HOP1_DRAM", - "BitIndex": "28", - "Type": "3", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_MISS", - "BitIndex": "26,27,28,29", - "Type": "3", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_NONE", - "BitIndex": "31", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "NO_SNOOP_NEEDED", - "BitIndex": "32", - "Type": "4", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "SNOOP_MISS", - "BitIndex": "33", - "Type": "4", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "HIT_OTHER_CORE_NO_FWD", - "BitIndex": "34", - "Type": "4", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "HIT_OTHER_CORE_FWD", - "BitIndex": "35", - "Type": "4", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "18,19,20,21", - "Errata": "na" - }, - { - "BitName": "HITM_OTHER_CORE", - "BitIndex": "36", - "Type": "4", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "ANY_SNOOP", - "BitIndex": "31,32,33,34,35,36,37", - "Type": "4", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "BitIndex": "23,24,25,27,28,29,33,34", - "Type": "2", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "BitIndex": "26,33,34", - "Type": "2", - "Description": "TBD", - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.NO_SNOOP_NEEDED", - "BitIndex": "18,19,20,21,32", - "Type": "2", - "Description": "hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "MATRIX_REG": "tbd", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.HIT_OTHER_CORE_NO_FWD", - "BitIndex": "18,19,20,21,34", - "Type": "2", - "Description": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "MATRIX_REG": "tbd", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.HIT_OTHER_CORE_FWD", - "BitIndex": "18,19,20,21,35", - "Type": "2", - "Description": "hit in the L3 and the snoop to one of the sibling cores hits the line in E/S/F state and the line is forwarded.", - "MATRIX_REG": "tbd", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.HITM_OTHER_CORE", - "BitIndex": "18,19,20,21,36", - "Type": "2", - "Description": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "MATRIX_REG": "tbd", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.ANY_SNOOP", - "BitIndex": "18,19,20,21,31,32,33,34,35,36,37", - "Type": "2", - "Description": "hit in the L3.", - "MATRIX_REG": "tbd", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_MISS.ANY_SNOOP", - "BitIndex": "26,27,28,29,31,32,33,34,35,36,37", - "Type": "2", - "Description": "miss in the L3.", - "MATRIX_REG": "tbd", - "BitsNotCombinedWith": "na", - "Errata": "na" - }, - { - "BitName": "L3_HIT.SNOOP_HIT_WITH_FWD", - "BitIndex": "18, 19, 20, 21, 22, 35", - "Type": "2", - "Description": null, - "MATRIX_REG": "0,1", - "BitsNotCombinedWith": "18,19,20,21", - "Errata": "na" - } -]
\ No newline at end of file diff --git a/usr/src/data/perfmon/SKX/skylakex_matrix_v1.12.json b/usr/src/data/perfmon/SKX/skylakex_matrix_v1.24.json index 1fa06d8334..8e7a99e83b 100644 --- a/usr/src/data/perfmon/SKX/skylakex_matrix_v1.12.json +++ b/usr/src/data/perfmon/SKX/skylakex_matrix_v1.24.json @@ -180,5 +180,12 @@ "MATRIX_VALUE": "0x060400", "MATRIX_REGISTER": "0,1", "DESCRIPTION": "miss the L3 and the data is returned from local dram." + }, + { + "MATRIX_REQUEST": "Null", + "MATRIX_RESPONSE": "L3_HIT.SNOOP_HIT_WITH_FWD", + "MATRIX_VALUE": "0x08003c ", + "MATRIX_REGISTER": "0,1", + "DESCRIPTION": "hit in the L3 and the snoop to one of the sibling cores hits the line in E/S/F state and the line is forwarded." } ]
\ No newline at end of file diff --git a/usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.00.json b/usr/src/data/perfmon/SKX/skylakex_uncore_v1.24.json index 229a08bbd8..76a74fcdcf 100644 --- a/usr/src/data/perfmon/CLX/cascadelakex_uncore_v1.00.json +++ b/usr/src/data/perfmon/SKX/skylakex_uncore_v1.24.json @@ -3240,6 +3240,258 @@ "FILTER_VALUE": "0" }, { + "Unit": "IIO", + "EventCode": "0xC2", + "UMask": "0x03", + "PortMask": "0x01", + "FCMask": "0x4", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xC2", + "UMask": "0x03", + "PortMask": "0x02", + "FCMask": "0x4", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xC2", + "UMask": "0x03", + "PortMask": "0x04", + "FCMask": "0x4", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xC2", + "UMask": "0x03", + "PortMask": "0x08", + "FCMask": "0x4", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xD5", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", + "Counter": "2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xD5", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", + "Counter": "2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xD5", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", + "Counter": "2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IIO", + "EventCode": "0xD5", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", + "Counter": "2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0xF", + "UMask": "0x4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "BriefDescription": "Total IRP occupancy of inbound read and write requests.", + "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x10", + "UMask": "0x8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", + "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x10", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", + "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x18", + "UMask": "0x0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", + "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x19", + "UMask": "0x0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_FAF_OCCUPANCY", + "BriefDescription": "Occupancy of the IRP FAF queue.", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "IRP", + "EventCode": "0x11", + "UMask": "0x8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { "Unit": "UPI LL", "EventCode": "0x1", "UMask": "0x0", @@ -4230,96 +4482,6 @@ "FILTER_VALUE": "0" }, { - "Unit": "M2M", - "EventCode": "0x2C", - "UMask": "0x02", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", - "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode", - "PublicDescription": "Tag Hit; Read Hit from NearMem, Dirty Line", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "M2M", - "EventCode": "0x2C", - "UMask": "0x04", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", - "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode", - "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Clean Line", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "M2M", - "EventCode": "0x2C", - "UMask": "0x08", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", - "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode", - "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Dirty Line", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "M2M", - "EventCode": "0x37", - "UMask": "0x8", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M2M_IMC_READS.TO_PMM", - "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M", - "PublicDescription": "M2M Reads Issued to iMC; All, regardless of priority.", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "M2M", - "EventCode": "0x38", - "UMask": "0x20", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", - "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M", - "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { "Unit": "M3UPI", "EventCode": "0x29", "UMask": "0x0", @@ -4329,7 +4491,7 @@ "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.", "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -4591,60 +4753,6 @@ }, { "Unit": "iMC", - "EventCode": "0xD3", - "UMask": "0x1", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_TAGCHK.HIT", - "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode", - "PublicDescription": "Tag Check; Hit", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xD3", - "UMask": "0x2", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_TAGCHK.MISS_CLEAN", - "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode", - "PublicDescription": "Tag Check; Clean", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xD3", - "UMask": "0x4", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_TAGCHK.MISS_DIRTY", - "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode", - "PublicDescription": "Tag Check; Dirty", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", "EventCode": "0x20", "UMask": "0x0", "PortMask": "0x00", @@ -4678,149 +4786,5 @@ "ExtSel": "0", "Deprecated": "0", "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xE0", - "UMask": "0x1", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", - "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory", - "PublicDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xE3", - "UMask": "0x0", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_PMM_RPQ_INSERTS", - "BriefDescription": "Read requests allocated in the PMM Read Pending Queue for Intel Optane DC persistent memory", - "PublicDescription": "Read requests allocated in the PMM Read Pending Queue for Intel Optane DC persistent memory", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xEA", - "UMask": "0x1", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_PMM_CMD1.ALL", - "BriefDescription": "All commands for Intel Optane DC persistent memory", - "PublicDescription": "All commands for Intel Optane DC persistent memory", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xEA", - "UMask": "0x2", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_PMM_CMD1.RD", - "BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory", - "PublicDescription": "All Reads - RPQ or Ufill", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xEA", - "UMask": "0x4", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_PMM_CMD1.WR", - "BriefDescription": "Write commands for Intel Optane DC persistent memory", - "PublicDescription": "Writes", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xEA", - "UMask": "0x8", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_PMM_CMD1.UFILL_RD", - "BriefDescription": "Underfill read commands for Intel Optane DC persistent memory", - "PublicDescription": "Underfill reads", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xE7", - "UMask": "0x0", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_PMM_WPQ_INSERTS", - "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", - "PublicDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "iMC", - "EventCode": "0xE4", - "UMask": "0x1", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", - "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", - "PublicDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", - "Counter": "0,1,2,3", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" } ]
\ No newline at end of file diff --git a/usr/src/data/perfmon/SKX/skylakex_uncore_v1.12_experimental.json b/usr/src/data/perfmon/SKX/skylakex_uncore_v1.24_experimental.json index 8498b145c5..22cd8cd927 100644 --- a/usr/src/data/perfmon/SKX/skylakex_uncore_v1.12_experimental.json +++ b/usr/src/data/perfmon/SKX/skylakex_uncore_v1.24_experimental.json @@ -19416,10 +19416,10 @@ "Counter": "0", "MSRValue": "0x00", "ELLC": "0", - "Filter": "CHAfilter1", + "Filter": "CHAFilter1[31:0]", "ExtSel": "0", "Deprecated": "0", - "FILTER_VALUE": "0" + "FILTER_VALUE": "" }, { "Unit": "CHA", @@ -19501,7 +19501,7 @@ "FCMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", - "BriefDescription": "TOR Occupancy; RDCUR isses from Local IO", + "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.", "Counter": "0", "MSRValue": "0x00", @@ -25111,24 +25111,6 @@ }, { "Unit": "IRP", - "EventCode": "0xF", - "UMask": "0x4", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", - "BriefDescription": "Total Write Cache Occupancy; Mem", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", "EventCode": "0x1", "UMask": "0x0", "PortMask": "0x00", @@ -25202,42 +25184,6 @@ { "Unit": "IRP", "EventCode": "0x10", - "UMask": "0x8", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_COHERENT_OPS.RFO", - "BriefDescription": "Coherent Ops; RFO", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", - "EventCode": "0x10", - "UMask": "0x10", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", - "BriefDescription": "Coherent Ops; PCIItoM", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", - "EventCode": "0x10", "UMask": "0x20", "PortMask": "0x00", "FCMask": "0x00", @@ -25309,42 +25255,6 @@ }, { "Unit": "IRP", - "EventCode": "0x18", - "UMask": "0x0", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_FAF_INSERTS", - "BriefDescription": "FAF - request insert from TC.", - "PublicDescription": "FAF - request insert from TC.", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", - "EventCode": "0x19", - "UMask": "0x0", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_FAF_OCCUPANCY", - "BriefDescription": "FAF occupancy", - "PublicDescription": "FAF occupancy", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", "EventCode": "0x16", "UMask": "0x0", "PortMask": "0x00", @@ -26030,24 +25940,6 @@ { "Unit": "IRP", "EventCode": "0x11", - "UMask": "0x8", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "BriefDescription": "Inbound Transaction Count; Write Prefetches", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.", - "Counter": "0,1", - "MSRValue": "0x00", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0" - }, - { - "Unit": "IRP", - "EventCode": "0x11", "UMask": "0x10", "PortMask": "0x00", "FCMask": "0x00", @@ -26821,6 +26713,42 @@ }, { "Unit": "UPI LL", + "EventCode": "0xB", + "UMask": "0x0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "BriefDescription": "CRC Errors Detected", + "PublicDescription": "Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "UPI LL", + "EventCode": "0x8", + "UMask": "0x0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "BriefDescription": "LLR Requests Sent", + "PublicDescription": "Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0" + }, + { + "Unit": "UPI LL", "EventCode": "0x39", "UMask": "0x0", "PortMask": "0x00", @@ -36153,7 +36081,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", "BriefDescription": "UPI0 AD Credits Empty; VNA", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36171,7 +36099,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36189,7 +36117,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36207,7 +36135,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36225,7 +36153,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36243,7 +36171,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36261,7 +36189,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36279,7 +36207,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", "BriefDescription": "UPI0 BL Credits Empty; VNA", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36297,7 +36225,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36315,7 +36243,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36333,7 +36261,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36351,7 +36279,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36369,7 +36297,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36387,7 +36315,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36477,7 +36405,7 @@ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", "BriefDescription": "CBox AD Credits Empty; VNA Messages", "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36495,7 +36423,7 @@ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", "BriefDescription": "CBox AD Credits Empty; Writebacks", "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36513,7 +36441,7 @@ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", "BriefDescription": "CBox AD Credits Empty; Requests", "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36531,7 +36459,7 @@ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", "BriefDescription": "CBox AD Credits Empty; Snoops", "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36549,7 +36477,7 @@ "EventName": "UNC_M3UPI_CLOCKTICKS", "BriefDescription": "Number of uclks in domain", "PublicDescription": "Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36567,7 +36495,7 @@ "EventName": "UNC_M3UPI_D2U_SENT", "BriefDescription": "D2U Sent", "PublicDescription": "Cases where SMI3 sends D2U command", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36585,7 +36513,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36603,7 +36531,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", "BriefDescription": "M2 BL Credits Empty; IIO2", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36621,7 +36549,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", "BriefDescription": "M2 BL Credits Empty; IIO3", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36639,7 +36567,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", "BriefDescription": "M2 BL Credits Empty; IIO4", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36657,7 +36585,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", "BriefDescription": "M2 BL Credits Empty; IIO5", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36675,7 +36603,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36693,7 +36621,7 @@ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits", "PublicDescription": "No vn0 and vna credits available to send to M2", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36711,7 +36639,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36729,7 +36657,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36747,7 +36675,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36765,7 +36693,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36783,7 +36711,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36801,7 +36729,7 @@ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36819,7 +36747,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36837,7 +36765,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36855,7 +36783,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36873,7 +36801,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", "BriefDescription": "Failed ARB for AD; VN0 WB Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36891,7 +36819,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36909,7 +36837,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36927,7 +36855,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36945,7 +36873,7 @@ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", "BriefDescription": "Failed ARB for AD; VN1 WB Messages", "PublicDescription": "AD arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36963,7 +36891,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", "BriefDescription": "AD FlowQ Bypass", "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36981,7 +36909,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", "BriefDescription": "AD FlowQ Bypass", "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -36999,7 +36927,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", "BriefDescription": "AD FlowQ Bypass", "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37017,7 +36945,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", "BriefDescription": "AD FlowQ Bypass", "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37035,7 +36963,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37053,7 +36981,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37071,7 +36999,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37089,7 +37017,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37107,7 +37035,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37125,7 +37053,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37143,7 +37071,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37161,7 +37089,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37179,7 +37107,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37197,7 +37125,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37215,7 +37143,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37233,7 +37161,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37251,7 +37179,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37269,7 +37197,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37287,7 +37215,7 @@ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37431,7 +37359,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37449,7 +37377,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37467,7 +37395,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37485,7 +37413,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37503,7 +37431,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37521,7 +37449,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages", "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37539,7 +37467,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37557,7 +37485,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37575,7 +37503,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37593,7 +37521,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37611,7 +37539,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37629,7 +37557,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages", "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37647,7 +37575,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37665,7 +37593,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37683,7 +37611,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37701,7 +37629,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37719,7 +37647,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37737,7 +37665,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37755,7 +37683,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37773,7 +37701,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages", "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37791,7 +37719,7 @@ "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", "BriefDescription": "AK Flow Q Inserts", "PublicDescription": "AK Flow Q Inserts", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37827,7 +37755,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37845,7 +37773,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", "BriefDescription": "Failed ARB for BL; VN0 WB Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37863,7 +37791,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37881,7 +37809,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37899,7 +37827,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37917,7 +37845,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", "BriefDescription": "Failed ARB for BL; VN1 WB Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37935,7 +37863,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37953,7 +37881,7 @@ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", "PublicDescription": "BL arb but no win; arb request asserted but not won", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37971,7 +37899,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -37989,7 +37917,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38007,7 +37935,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38025,7 +37953,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38043,7 +37971,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38061,7 +37989,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38079,7 +38007,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38097,7 +38025,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38115,7 +38043,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38133,7 +38061,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38151,7 +38079,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38169,7 +38097,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38187,7 +38115,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38205,7 +38133,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38223,7 +38151,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38241,7 +38169,7 @@ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38403,7 +38331,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38421,7 +38349,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38439,7 +38367,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38457,7 +38385,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38475,7 +38403,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38493,7 +38421,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages", "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38511,7 +38439,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38529,7 +38457,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38547,7 +38475,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38565,7 +38493,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38583,7 +38511,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38601,7 +38529,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38619,7 +38547,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38637,7 +38565,7 @@ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages", "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38655,7 +38583,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", "BriefDescription": "VN0 Credit Used; REQ on AD", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38673,7 +38601,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", "BriefDescription": "VN0 Credit Used; SNP on AD", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38691,7 +38619,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", "BriefDescription": "VN0 Credit Used; RSP on AD", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38709,7 +38637,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", "BriefDescription": "VN0 Credit Used; RSP on BL", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38727,7 +38655,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", "BriefDescription": "VN0 Credit Used; WB on BL", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38745,7 +38673,7 @@ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", "BriefDescription": "VN0 Credit Used; NCB on BL", "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38763,7 +38691,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", "BriefDescription": "VN0 No Credits; REQ on AD", "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38781,7 +38709,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", "BriefDescription": "VN0 No Credits; SNP on AD", "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38799,7 +38727,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", "BriefDescription": "VN0 No Credits; RSP on AD", "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38817,7 +38745,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", "BriefDescription": "VN0 No Credits; RSP on BL", "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38835,7 +38763,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", "BriefDescription": "VN0 No Credits; WB on BL", "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38853,7 +38781,7 @@ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", "BriefDescription": "VN0 No Credits; NCB on BL", "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38871,7 +38799,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", "BriefDescription": "VN1 Credit Used; REQ on AD", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38889,7 +38817,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", "BriefDescription": "VN1 Credit Used; SNP on AD", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38907,7 +38835,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", "BriefDescription": "VN1 Credit Used; RSP on AD", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38925,7 +38853,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", "BriefDescription": "VN1 Credit Used; RSP on BL", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38943,7 +38871,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", "BriefDescription": "VN1 Credit Used; WB on BL", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38961,7 +38889,7 @@ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", "BriefDescription": "VN1 Credit Used; NCB on BL", "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38979,7 +38907,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", "BriefDescription": "VN1 No Credits; REQ on AD", "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -38997,7 +38925,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", "BriefDescription": "VN1 No Credits; SNP on AD", "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39015,7 +38943,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", "BriefDescription": "VN1 No Credits; RSP on AD", "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39033,7 +38961,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", "BriefDescription": "VN1 No Credits; RSP on BL", "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39051,7 +38979,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", "BriefDescription": "VN1 No Credits; WB on BL", "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39069,7 +38997,7 @@ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", "BriefDescription": "VN1 No Credits; NCB on BL", "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39159,7 +39087,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", "BriefDescription": "Snoop Arbitration; FlowQ Won", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39177,7 +39105,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", "BriefDescription": "Snoop Arbitration; FlowQ Won", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39195,7 +39123,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39213,7 +39141,7 @@ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39231,7 +39159,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39249,7 +39177,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39267,7 +39195,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39285,7 +39213,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39303,7 +39231,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39321,7 +39249,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39339,7 +39267,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39357,7 +39285,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39375,7 +39303,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39393,7 +39321,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39411,7 +39339,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39429,7 +39357,7 @@ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39447,7 +39375,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39465,7 +39393,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39483,7 +39411,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39501,7 +39429,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39519,7 +39447,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39537,7 +39465,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39555,7 +39483,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39573,7 +39501,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39591,7 +39519,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39609,7 +39537,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39627,7 +39555,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39645,7 +39573,7 @@ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39663,7 +39591,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39681,7 +39609,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39699,7 +39627,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39717,7 +39645,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39735,7 +39663,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39753,7 +39681,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39771,7 +39699,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39789,7 +39717,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39807,7 +39735,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39825,7 +39753,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39843,7 +39771,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39861,7 +39789,7 @@ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -39987,7 +39915,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40005,7 +39933,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40023,7 +39951,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40041,7 +39969,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40059,7 +39987,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40077,7 +40005,7 @@ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40095,7 +40023,7 @@ "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", "BriefDescription": "CMS Clockticks", "PublicDescription": "CMS Clockticks", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40113,7 +40041,7 @@ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", "BriefDescription": "Egress Blocking due to Ordering requirements; Up", "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40131,7 +40059,7 @@ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", "BriefDescription": "Egress Blocking due to Ordering requirements; Down", "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40149,7 +40077,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", "BriefDescription": "Horizontal AD Ring In Use; Left and Even", "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40167,7 +40095,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40185,7 +40113,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "BriefDescription": "Horizontal AD Ring In Use; Right and Even", "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40203,7 +40131,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40221,7 +40149,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", "BriefDescription": "Horizontal AK Ring In Use; Left and Even", "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40239,7 +40167,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40257,7 +40185,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "BriefDescription": "Horizontal AK Ring In Use; Right and Even", "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40275,7 +40203,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40293,7 +40221,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", "BriefDescription": "Horizontal BL Ring in Use; Left and Even", "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40311,7 +40239,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40329,7 +40257,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "BriefDescription": "Horizontal BL Ring in Use; Right and Even", "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40347,7 +40275,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40365,7 +40293,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", "BriefDescription": "Horizontal IV Ring in Use; Left", "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40383,7 +40311,7 @@ "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", "BriefDescription": "Horizontal IV Ring in Use; Right", "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40401,7 +40329,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40419,7 +40347,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40437,7 +40365,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40455,7 +40383,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40473,7 +40401,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40491,7 +40419,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40509,7 +40437,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40527,7 +40455,7 @@ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40545,7 +40473,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", "BriefDescription": "Sink Starvation on Horizontal Ring; AD", "PublicDescription": "Sink Starvation on Horizontal Ring; AD", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40563,7 +40491,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", "BriefDescription": "Sink Starvation on Horizontal Ring; AK", "PublicDescription": "Sink Starvation on Horizontal Ring; AK", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40581,7 +40509,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", "BriefDescription": "Sink Starvation on Horizontal Ring; BL", "PublicDescription": "Sink Starvation on Horizontal Ring; BL", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40599,7 +40527,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", "BriefDescription": "Sink Starvation on Horizontal Ring; IV", "PublicDescription": "Sink Starvation on Horizontal Ring; IV", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40617,7 +40545,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", "PublicDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40635,7 +40563,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", "BriefDescription": "Sink Starvation on Vertical Ring; AD", "PublicDescription": "Sink Starvation on Vertical Ring; AD", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40653,7 +40581,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", "PublicDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40671,7 +40599,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", "PublicDescription": "Sink Starvation on Vertical Ring; Data Responses to core", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40689,7 +40617,7 @@ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", "PublicDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40707,7 +40635,7 @@ "EventName": "UNC_M3UPI_RING_SRC_THRTL", "BriefDescription": "Source Throttle", "PublicDescription": "Source Throttle", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40725,7 +40653,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", "BriefDescription": "Lost Arb for VN0; REQ on AD", "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40743,7 +40671,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", "BriefDescription": "Lost Arb for VN0; SNP on AD", "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40761,7 +40689,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", "BriefDescription": "Lost Arb for VN0; RSP on AD", "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40779,7 +40707,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", "BriefDescription": "Lost Arb for VN0; RSP on BL", "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40797,7 +40725,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", "BriefDescription": "Lost Arb for VN0; WB on BL", "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40815,7 +40743,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", "BriefDescription": "Lost Arb for VN0; NCB on BL", "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40833,7 +40761,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", "BriefDescription": "Lost Arb for VN0; NCS on BL", "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40851,7 +40779,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", "BriefDescription": "Lost Arb for VN1; REQ on AD", "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40869,7 +40797,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", "BriefDescription": "Lost Arb for VN1; SNP on AD", "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40887,7 +40815,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", "BriefDescription": "Lost Arb for VN1; RSP on AD", "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40905,7 +40833,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", "BriefDescription": "Lost Arb for VN1; RSP on BL", "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40923,7 +40851,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", "BriefDescription": "Lost Arb for VN1; WB on BL", "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40941,7 +40869,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", "BriefDescription": "Lost Arb for VN1; NCB on BL", "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40959,7 +40887,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", "BriefDescription": "Lost Arb for VN1; NCS on BL", "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40977,7 +40905,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -40995,7 +40923,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41013,7 +40941,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0", "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41031,7 +40959,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1", "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41049,7 +40977,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0", "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41067,7 +40995,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1", "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41085,7 +41013,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41103,7 +41031,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", "BriefDescription": "Can't Arb for VN0; REQ on AD", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41121,7 +41049,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", "BriefDescription": "Can't Arb for VN0; SNP on AD", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41139,7 +41067,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", "BriefDescription": "Can't Arb for VN0; RSP on AD", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41157,7 +41085,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", "BriefDescription": "Can't Arb for VN0; RSP on BL", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41175,7 +41103,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", "BriefDescription": "Can't Arb for VN0; WB on BL", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41193,7 +41121,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", "BriefDescription": "Can't Arb for VN0; NCB on BL", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41211,7 +41139,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", "BriefDescription": "Can't Arb for VN0; NCS on BL", "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41229,7 +41157,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", "BriefDescription": "Can't Arb for VN1; REQ on AD", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41247,7 +41175,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", "BriefDescription": "Can't Arb for VN1; SNP on AD", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41265,7 +41193,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", "BriefDescription": "Can't Arb for VN1; RSP on AD", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41283,7 +41211,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", "BriefDescription": "Can't Arb for VN1; RSP on BL", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41301,7 +41229,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", "BriefDescription": "Can't Arb for VN1; WB on BL", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41319,7 +41247,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", "BriefDescription": "Can't Arb for VN1; NCB on BL", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41337,7 +41265,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", "BriefDescription": "Can't Arb for VN1; NCS on BL", "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41355,7 +41283,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", "BriefDescription": "No Credits to Arb for VN0; REQ on AD", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41373,7 +41301,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", "BriefDescription": "No Credits to Arb for VN0; SNP on AD", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41391,7 +41319,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", "BriefDescription": "No Credits to Arb for VN0; RSP on AD", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41409,7 +41337,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", "BriefDescription": "No Credits to Arb for VN0; RSP on BL", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41427,7 +41355,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", "BriefDescription": "No Credits to Arb for VN0; WB on BL", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41445,7 +41373,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", "BriefDescription": "No Credits to Arb for VN0; NCB on BL", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41463,7 +41391,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", "BriefDescription": "No Credits to Arb for VN0; NCS on BL", "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41481,7 +41409,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", "BriefDescription": "No Credits to Arb for VN1; REQ on AD", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41499,7 +41427,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", "BriefDescription": "No Credits to Arb for VN1; SNP on AD", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41517,7 +41445,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", "BriefDescription": "No Credits to Arb for VN1; RSP on AD", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41535,7 +41463,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", "BriefDescription": "No Credits to Arb for VN1; RSP on BL", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41553,7 +41481,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", "BriefDescription": "No Credits to Arb for VN1; WB on BL", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41571,7 +41499,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", "BriefDescription": "No Credits to Arb for VN1; NCB on BL", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41589,7 +41517,7 @@ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", "BriefDescription": "No Credits to Arb for VN1; NCS on BL", "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41931,7 +41859,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41949,7 +41877,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41967,7 +41895,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -41985,7 +41913,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", "BriefDescription": "Credit Occupancy; VNA In Use", "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42002,8 +41930,8 @@ "UMaskExt": "0x00", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", - "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", - "Counter": "0,1,2,3", + "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42020,8 +41948,8 @@ "UMaskExt": "0x00", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", "BriefDescription": "Credit Occupancy; Packets in BGF Path", - "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", - "Counter": "0,1,2,3", + "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42039,7 +41967,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", "BriefDescription": "Credit Occupancy; Transmit Credits", "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42057,7 +41985,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", "BriefDescription": "Credit Occupancy; D2K Credits", "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42075,7 +42003,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", "BriefDescription": "Credit Occupancy", "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42093,7 +42021,7 @@ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", "BriefDescription": "Credit Occupancy", "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42111,7 +42039,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42129,7 +42057,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42147,7 +42075,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42165,7 +42093,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42183,7 +42111,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42201,7 +42129,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42219,7 +42147,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42237,7 +42165,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42255,7 +42183,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42273,7 +42201,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42291,7 +42219,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42309,7 +42237,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42327,7 +42255,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42345,7 +42273,7 @@ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42363,7 +42291,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", "BriefDescription": "Data Flit Not Sent; All", "PublicDescription": "Data flit is ready for transmission but could not be sent", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42381,7 +42309,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", "BriefDescription": "Data Flit Not Sent; No BGF Credits", "PublicDescription": "Data flit is ready for transmission but could not be sent", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42399,7 +42327,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", "BriefDescription": "Data Flit Not Sent; No TxQ Credits", "PublicDescription": "Data flit is ready for transmission but could not be sent", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42417,7 +42345,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0", "PublicDescription": "generating bl data flit sequence; waiting for data pump 0", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42435,7 +42363,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1", "PublicDescription": "generating bl data flit sequence; waiting for data pump 1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42453,7 +42381,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42471,7 +42399,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "pump-1-pending logic is tracking at least one message", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42489,7 +42417,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42507,7 +42435,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42525,7 +42453,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", "BriefDescription": "Generating BL Data Flit Sequence", "PublicDescription": "pump-1-pending completion fifo is full", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42543,7 +42471,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_MISC", "BriefDescription": "tbd", "PublicDescription": "tbd", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42561,7 +42489,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", "BriefDescription": "Sent Header Flit; One Message", "PublicDescription": "One message in flit; VNA or non-VNA flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42579,7 +42507,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", "BriefDescription": "Sent Header Flit; Two Messages", "PublicDescription": "Two messages in flit; VNA flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42597,7 +42525,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", "BriefDescription": "Sent Header Flit; Three Messages", "PublicDescription": "Three messages in flit; VNA flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42615,7 +42543,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", "BriefDescription": "Sent Header Flit; One Message in non-VNA", "PublicDescription": "One message in flit; non-VNA flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42633,7 +42561,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", "BriefDescription": "Slotting BL Message Into Header Flit; All", "PublicDescription": "Slotting BL Message Into Header Flit; All", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42651,7 +42579,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit", "PublicDescription": "BL message requires data flit sequence", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42669,7 +42597,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0", "PublicDescription": "Waiting for header pump 0", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42687,7 +42615,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1", "PublicDescription": "Waiting for header pump 1", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42705,7 +42633,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1", "PublicDescription": "Header pump 1 is not required for flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42723,7 +42651,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble", "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42741,7 +42669,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail", "PublicDescription": "Header pump 1 is not required for flit and not available", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42759,7 +42687,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", "BriefDescription": "Flit Gen - Header 1; Acumullate", "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42777,7 +42705,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42795,7 +42723,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42813,7 +42741,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42831,7 +42759,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42849,7 +42777,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", "BriefDescription": "Flit Gen - Header 1; Parallel Ok", "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42867,7 +42795,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", "BriefDescription": "Flit Gen - Header 1; Parallel Message", "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42885,7 +42813,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42903,7 +42831,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42921,7 +42849,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message", "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42939,7 +42867,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", "BriefDescription": "Header Not Sent; All", "PublicDescription": "header flit is ready for transmission but could not be sent", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42957,7 +42885,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", "BriefDescription": "Header Not Sent; No BGF Credits", "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42975,7 +42903,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", "BriefDescription": "Header Not Sent; No TxQ Credits", "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -42993,7 +42921,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted", "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43011,7 +42939,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted", "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43029,7 +42957,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", "BriefDescription": "Header Not Sent; Sent - One Slot Taken", "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43047,7 +42975,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43065,7 +42993,7 @@ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43227,7 +43155,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43245,7 +43173,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43263,7 +43191,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43281,7 +43209,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43299,7 +43227,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43317,7 +43245,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43335,7 +43263,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL", "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43353,7 +43281,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43371,7 +43299,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43389,7 +43317,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43407,7 +43335,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43425,7 +43353,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43443,7 +43371,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43461,7 +43389,7 @@ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL", "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43479,7 +43407,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43497,7 +43425,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43515,7 +43443,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43533,7 +43461,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43551,7 +43479,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43569,7 +43497,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43587,7 +43515,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43605,7 +43533,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43623,7 +43551,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43641,7 +43569,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43659,7 +43587,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43677,7 +43605,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43695,7 +43623,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43713,7 +43641,7 @@ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL", "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -43983,7 +43911,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", "BriefDescription": "SMI3 Prefetch Messages; Arrived", "PublicDescription": "SMI3 Prefetch Messages; Arrived", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44001,7 +43929,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", "PublicDescription": "SMI3 Prefetch Messages; Lost Arbitration", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44019,7 +43947,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", "BriefDescription": "SMI3 Prefetch Messages; Slotted", "PublicDescription": "SMI3 Prefetch Messages; Slotted", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44037,7 +43965,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", "PublicDescription": "SMI3 Prefetch Messages; Dropped - Old", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44055,7 +43983,7 @@ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44073,7 +44001,7 @@ "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", "BriefDescription": "Remote VNA Credits; Used", "PublicDescription": "Number of remote vna credits consumed per cycle", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44091,7 +44019,7 @@ "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", "BriefDescription": "Remote VNA Credits; Corrected", "PublicDescription": "Number of remote vna credits corrected (local return) per cycle", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44107,9 +44035,9 @@ "FCMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", - "BriefDescription": "Remote VNA Credits; Level < 1", + "BriefDescription": "Remote VNA Credits; Level < 1", "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44125,9 +44053,9 @@ "FCMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", - "BriefDescription": "Remote VNA Credits; Level < 4", + "BriefDescription": "Remote VNA Credits; Level < 4", "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44143,9 +44071,9 @@ "FCMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", - "BriefDescription": "Remote VNA Credits; Level < 5", + "BriefDescription": "Remote VNA Credits; Level < 5", "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44163,7 +44091,7 @@ "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", "BriefDescription": "Remote VNA Credits; Any In Use", "PublicDescription": "At least one remote vna credit is in use", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44181,7 +44109,7 @@ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", "BriefDescription": "Transgress Injection Starvation; AD - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44199,7 +44127,7 @@ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", "BriefDescription": "Transgress Injection Starvation; BL - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44217,7 +44145,7 @@ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", "BriefDescription": "Transgress Injection Starvation; AD - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44235,7 +44163,7 @@ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", "BriefDescription": "Transgress Injection Starvation; BL - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44253,7 +44181,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44271,7 +44199,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44289,7 +44217,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44307,7 +44235,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44325,7 +44253,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", "BriefDescription": "Transgress Ingress Bypass; AD - Credit", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44343,7 +44271,7 @@ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", "BriefDescription": "Transgress Ingress Bypass; BL - Credit", "PublicDescription": "Number of packets bypassing the CMS Ingress", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44361,7 +44289,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", "BriefDescription": "Transgress Injection Starvation; AD - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44379,7 +44307,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", "BriefDescription": "Transgress Injection Starvation; AK - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44397,7 +44325,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", "BriefDescription": "Transgress Injection Starvation; BL - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44415,7 +44343,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", "BriefDescription": "Transgress Injection Starvation; IV - Bounce", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44433,7 +44361,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", "BriefDescription": "Transgress Injection Starvation; AD - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44451,7 +44379,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", "BriefDescription": "Transgress Injection Starvation; BL - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44469,7 +44397,7 @@ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", "BriefDescription": "Transgress Injection Starvation; IFV - Credit", "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44487,7 +44415,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44505,7 +44433,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44523,7 +44451,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44541,7 +44469,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44559,7 +44487,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", "BriefDescription": "Transgress Ingress Allocations; AD - Credit", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44577,7 +44505,7 @@ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", "BriefDescription": "Transgress Ingress Allocations; BL - Credit", "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44595,7 +44523,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44613,7 +44541,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44631,7 +44559,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44649,7 +44577,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44667,7 +44595,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44685,7 +44613,7 @@ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44703,7 +44631,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44721,7 +44649,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44739,7 +44667,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44757,7 +44685,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44775,7 +44703,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44793,7 +44721,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44811,7 +44739,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44829,7 +44757,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44847,7 +44775,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44865,7 +44793,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44883,7 +44811,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44901,7 +44829,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44919,7 +44847,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44937,7 +44865,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44955,7 +44883,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44973,7 +44901,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -44991,7 +44919,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45009,7 +44937,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45027,7 +44955,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45045,7 +44973,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45063,7 +44991,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45081,7 +45009,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45099,7 +45027,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45117,7 +45045,7 @@ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45135,7 +45063,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45153,7 +45081,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45171,7 +45099,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45189,7 +45117,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45207,7 +45135,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45225,7 +45153,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45243,7 +45171,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45261,7 +45189,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45279,7 +45207,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45297,7 +45225,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45315,7 +45243,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45333,7 +45261,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45351,7 +45279,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45369,7 +45297,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45387,7 +45315,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45405,7 +45333,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45423,7 +45351,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45441,7 +45369,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45459,7 +45387,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45477,7 +45405,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45495,7 +45423,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45513,7 +45441,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45531,7 +45459,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45549,7 +45477,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45567,7 +45495,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45585,7 +45513,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45603,7 +45531,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45621,7 +45549,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45639,7 +45567,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45657,7 +45585,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45675,7 +45603,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45693,7 +45621,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45711,7 +45639,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45729,7 +45657,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45747,7 +45675,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45765,7 +45693,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45783,7 +45711,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45801,7 +45729,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45819,7 +45747,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45837,7 +45765,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45855,7 +45783,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45873,7 +45801,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45891,7 +45819,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45909,7 +45837,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45927,7 +45855,7 @@ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45945,7 +45873,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45963,7 +45891,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45981,7 +45909,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -45999,7 +45927,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46017,7 +45945,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46035,7 +45963,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46053,7 +45981,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46071,7 +45999,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46089,7 +46017,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46107,7 +46035,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", "BriefDescription": "CMS Vertical ADS Used; IV", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46125,7 +46053,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46143,7 +46071,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46161,7 +46089,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46179,7 +46107,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46197,7 +46125,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46215,7 +46143,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46233,7 +46161,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46251,7 +46179,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46269,7 +46197,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46287,7 +46215,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transfering writeback data to the cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46305,7 +46233,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46323,7 +46251,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46341,7 +46269,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46359,7 +46287,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46377,7 +46305,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46395,7 +46323,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46413,7 +46341,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transfering writeback data to the cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46431,7 +46359,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46449,7 +46377,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46467,7 +46395,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46485,7 +46413,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", "BriefDescription": "CMS Vert Egress Allocations; IV", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46503,7 +46431,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46521,7 +46449,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46539,7 +46467,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transfering writeback data to the cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46557,7 +46485,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46575,7 +46503,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46593,7 +46521,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46611,7 +46539,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46629,7 +46557,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46647,7 +46575,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46665,7 +46593,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46683,7 +46611,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46701,7 +46629,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46719,7 +46647,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", "BriefDescription": "CMS Vert Egress Occupancy; IV", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46737,7 +46665,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46755,7 +46683,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46773,7 +46701,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transfering writeback data to the cache.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46791,7 +46719,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46809,7 +46737,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46827,7 +46755,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46845,7 +46773,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46863,7 +46791,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46881,7 +46809,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46899,7 +46827,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", "BriefDescription": "Vertical AD Ring In Use; Up and Even", "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46917,7 +46845,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", "BriefDescription": "Vertical AD Ring In Use; Up and Odd", "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46935,7 +46863,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", "BriefDescription": "Vertical AD Ring In Use; Down and Even", "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46953,7 +46881,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", "BriefDescription": "Vertical AD Ring In Use; Down and Odd", "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46971,7 +46899,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", "BriefDescription": "Vertical AK Ring In Use; Up and Even", "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -46989,7 +46917,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", "BriefDescription": "Vertical AK Ring In Use; Up and Odd", "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47007,7 +46935,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", "BriefDescription": "Vertical AK Ring In Use; Down and Even", "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47025,7 +46953,7 @@ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", "BriefDescription": "Vertical AK Ring In Use; Down and Odd", "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47043,7 +46971,7 @@ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", "BriefDescription": "Vertical BL Ring in Use; Up and Even", "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47061,7 +46989,7 @@ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", "BriefDescription": "Vertical BL Ring in Use; Up and Odd", "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47079,7 +47007,7 @@ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", "BriefDescription": "Vertical BL Ring in Use; Down and Even", "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47097,7 +47025,7 @@ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", "BriefDescription": "Vertical BL Ring in Use; Down and Odd", "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47115,7 +47043,7 @@ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", "BriefDescription": "Vertical IV Ring in Use; Up", "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47133,7 +47061,7 @@ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", "BriefDescription": "Vertical IV Ring in Use; Down", "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47151,7 +47079,7 @@ "EventName": "UNC_M3UPI_D2C_SENT", "BriefDescription": "D2C Sent", "PublicDescription": "Count cases BL sends direct to core", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47169,7 +47097,7 @@ "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", "BriefDescription": "FaST wire asserted; Vertical", "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47187,7 +47115,7 @@ "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", "BriefDescription": "FaST wire asserted; Horizontal", "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47205,7 +47133,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", "BriefDescription": "Sent Header Flit", "PublicDescription": "Sent Header Flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47223,7 +47151,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", "BriefDescription": "Sent Header Flit", "PublicDescription": "Sent Header Flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47241,7 +47169,7 @@ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", "BriefDescription": "Sent Header Flit", "PublicDescription": "Sent Header Flit", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47259,7 +47187,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", "BriefDescription": "CMS Vertical Egress NACKs; IV", "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47277,7 +47205,7 @@ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47295,7 +47223,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", "BriefDescription": "UPI0 BL Credits Empty; VNA", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47313,7 +47241,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47331,7 +47259,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47349,7 +47277,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47367,7 +47295,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", @@ -47385,7 +47313,7 @@ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "Counter": "0,1,2,3", + "Counter": "0,1,2", "MSRValue": "0x00", "ELLC": "0", "Filter": "na", diff --git a/usr/src/data/perfmon/SNR/snowridgex_core_v1.10.json b/usr/src/data/perfmon/SNR/snowridgex_core_v1.10.json new file mode 100644 index 0000000000..e862f2f710 --- /dev/null +++ b/usr/src/data/perfmon/SNR/snowridgex_core_v1.10.json @@ -0,0 +1,794 @@ +[ + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.ANY", + "BriefDescription": "Counts the number of instructions retired. (Fixed event)", + "PublicDescription": "Counts the number of instructions that retire. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.", + "Counter": "32", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.CORE", + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", + "Counter": "33", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x00", + "UMask": "0x03", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time. This event is not affected by core frequency changes and at a fixed frequency. This event uses fixed counter 2.", + "Counter": "34", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x08", + "UMask": "0x02", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of completed page walks due to a demand load DTLB miss to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x08", + "UMask": "0x04", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Counts the number of completed page walks due to a demand load DTLB miss to a 2M or 4M page.", + "PublicDescription": "Counts the number of completed page walks due to a demand load (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x2e", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Counts the number of memory requests that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 cache. Counts on a per core basis.", + "PublicDescription": "Counts the number of memory requests that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 cache. Counts on a per core basis.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x2e", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "BriefDescription": "Counts the number of memory requests that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 cache. Counts on a per core basis.", + "PublicDescription": "Counts cacheable memory requests that access the Last Level Cache. Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "BriefDescription": "Counts the number of unhalted core clock cycles.", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x3c", + "UMask": "0x01", + "EventName": "CPU_CLK_UNHALTED.REF", + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", + "PublicDescription": "Counts reference cycles (at TSC frequency) when core is not halted. This event uses a programmable general purpose perfmon counter.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x49", + "UMask": "0x02", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to a demand data store to a 4K page.", + "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x49", + "UMask": "0x04", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Counts the number of page walks completed due to a demand data store to a 2M or 4M page.", + "PublicDescription": "Counts the number of page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x71", + "UMask": "0x00", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls", + "PublicDescription": "tbd", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x73", + "UMask": "0x06", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to Fast Nukes such as MOnukes are counted. Other nukes are not accounted for.", + "PublicDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the IQ. Also, includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x74", + "UMask": "0x00", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls", + "PublicDescription": "tbd", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x80", + "UMask": "0x02", + "EventName": "ICACHE.MISSES", + "BriefDescription": "Counts the number of requests to the Instruction Cache (ICache) for one or more bytes in a cache line that do not hit in the ICache (miss).", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x80", + "UMask": "0x03", + "EventName": "ICACHE.ACCESSES", + "BriefDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes cache Line.", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x81", + "UMask": "0x04", + "EventName": "ITLB.FILLS", + "BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.", + "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x85", + "UMask": "0x02", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page.", + "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0x85", + "UMask": "0x04", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page.", + "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Counts the number of instructions retired.", + "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a Programmable general purpose perfmon counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x00", + "EventName": "TOPDOWN_RETIRING.ALL", + "BriefDescription": "Count the number of uops retired", + "PublicDescription": "Count the number of uops retired", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x00", + "EventName": "MACHINE_CLEARS.ANY", + "BriefDescription": "Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist.", + "PublicDescription": "Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "BriefDescription": "Counts the number of branch instructions retired for all branch types.", + "PublicDescription": "Counts branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "Counts the number of mispredicted branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x00", + "EventName": "CYCLES_DIV_BUSY.ANY", + "BriefDescription": "Counts cycles the floating point divider or integer divider or both are busy. Does not imply a stall waiting for either divider.", + "PublicDescription": "Counts cycles the floating point divider or integer divider or both are busy. Does not imply a stall waiting for either divider.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "na" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "BriefDescription": "Counts the number of load uops retired.", + "PublicDescription": "Counts the number of load uops retired. This event is Precise Event capable", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x82", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "Counts the number of store uops retired.", + "PublicDescription": "Counts the number of store uops retired. This event is Precise Event capable", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x01", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "BriefDescription": "Counts the number of load uops retired that hit the level 1 data cache", + "PublicDescription": "Counts the number of load uops retired that hit the level 1 data cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x02", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "BriefDescription": "Counts the number of load uops retired that hit in the level 2 cache", + "PublicDescription": "Counts the number of load uops retired that hit in the level 2 cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "BriefDescription": "Counts the number of load uops retired that miss in the level 3 cache", + "PublicDescription": "Counts the number of load uops retired that miss in the level 3 cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x08", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "BriefDescription": "Counts the number of load uops retired that miss in the level 1 data cache", + "PublicDescription": "Counts the number of load uops retired that miss in the level 1 data cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x10", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "BriefDescription": "Counts the number of load uops retired that miss in the level 2 cache", + "PublicDescription": "Counts the number of load uops retired that miss in the level 2 cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "Errata": "0", + "Offcore": "0", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0XB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000000000010001", + "CollectPEBSRecord": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "null", + "Offcore": "1", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0XB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000003F04000001", + "CollectPEBSRecord": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "null", + "Offcore": "1", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0XB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000000000010002", + "CollectPEBSRecord": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "null", + "Offcore": "1", + "PDIR_COUNTER": "0" + }, + { + "EventCode": "0XB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000003F04000002", + "CollectPEBSRecord": "0", + "CounterMask": "0", + "Invert": "0", + "AnyThread": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "Errata": "null", + "Offcore": "1", + "PDIR_COUNTER": "0" + } +]
\ No newline at end of file diff --git a/usr/src/data/perfmon/SNR/snowridgex_uncore_v1.10.json b/usr/src/data/perfmon/SNR/snowridgex_uncore_v1.10.json new file mode 100644 index 0000000000..d7cc423fba --- /dev/null +++ b/usr/src/data/perfmon/SNR/snowridgex_uncore_v1.10.json @@ -0,0 +1,743 @@ +[ + { + "Unit": "CHA", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_CLOCKTICKS", + "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)", + "PublicDescription": "Clockticks of the uncore caching and home agent (CHA)", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC80FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC807FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC88FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC827FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8A7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC887FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC86FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC867FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", + "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_CLOCKTICKS", + "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", + "PublicDescription": "Clockticks of the IO coherency tracker (IRP)", + "Counter": "0,1", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT.RD", + "BriefDescription": "DRAM Precharge commands. : Precharge due to read", + "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT.WR", + "BriefDescription": "DRAM Precharge commands. : Precharge due to write", + "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x04", + "UMask": "0x0f", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_CAS_COUNT.RD", + "BriefDescription": "All DRAM read CAS commands issued (including underfills)", + "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x04", + "UMask": "0x30", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_CAS_COUNT.WR", + "BriefDescription": "All DRAM write CAS commands issued", + "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT.PGT", + "BriefDescription": "DRAM Precharge commands. : Precharge due to page table", + "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "DRAM Clockticks", + "PublicDescription": "Clockticks of the integrated memory controller (IMC)", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x1C", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT.ALL", + "BriefDescription": "DRAM Precharge commands.", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_CLOCKTICKS", + "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "PublicDescription": "Clockticks of the mesh to memory (M2M)", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2PCIe", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2P_CLOCKTICKS", + "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "PublicDescription": "Clockticks of the mesh to PCI (M2P)", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UBOX", + "EventCode": "0x00", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_U_CLOCKTICKS", + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "PublicDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "Counter": "FIXED", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "FIXED" + }, + { + "Unit": "PCU", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_P_CLOCKTICKS", + "BriefDescription": "Clockticks of the power control unit (PCU)", + "PublicDescription": "Clockticks of the power control unit (PCU)", + "Counter": "0,1,2,3", + "MSRValue": "0x00", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + } +]
\ No newline at end of file diff --git a/usr/src/data/perfmon/TGL/tigerlake_core_v1.00.json b/usr/src/data/perfmon/TGL/tigerlake_core_v1.00.json new file mode 100644 index 0000000000..4b48aae594 --- /dev/null +++ b/usr/src/data/perfmon/TGL/tigerlake_core_v1.00.json @@ -0,0 +1,5172 @@ +[ + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.ANY", + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "32", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", + "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", + "Counter": "32", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Core cycles when the thread is not in halt state", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "Counter": "33", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x03", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "34", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x04", + "EventName": "TOPDOWN.SLOTS", + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "Counter": "35", + "PEBScounters": "35", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x03", + "UMask": "0x02", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x03", + "UMask": "0x08", + "EventName": "LD_BLOCKS.NO_SR", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x07", + "UMask": "0x01", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x08", + "UMask": "0x02", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x08", + "UMask": "0x04", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x08", + "UMask": "0x0E", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x08", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x0D", + "UMask": "0x01", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x0d", + "UMask": "0x03", + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", + "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x0d", + "UMask": "0x10", + "EventName": "INT_MISC.UOP_DROPPING", + "BriefDescription": "TMA slots where uops got dropped", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x0d", + "UMask": "0x80", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x0E", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Uops that RAT issues to RS", + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x0E", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", + "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x14", + "UMask": "0x09", + "EventName": "ARITH.DIVIDER_ACTIVE", + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x24", + "UMask": "0x22", + "EventName": "L2_RQSTS.RFO_MISS", + "BriefDescription": "RFO requests that miss L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x24", + "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "BriefDescription": "L2 cache misses when fetching instructions", + "PublicDescription": "Counts L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x24", + "UMask": "0x28", + "EventName": "L2_RQSTS.SWPF_MISS", + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "EventName": "L2_RQSTS.MISS", + "BriefDescription": "All requests that miss L2 cache", + "PublicDescription": "Counts all requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x24", + "UMask": "0xc2", + "EventName": "L2_RQSTS.RFO_HIT", + "BriefDescription": "RFO requests that hit L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x24", + "UMask": "0xc4", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x24", + "UMask": "0xc8", + "EventName": "L2_RQSTS.SWPF_HIT", + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x24", + "UMask": "0xE2", + "EventName": "L2_RQSTS.ALL_RFO", + "BriefDescription": "RFO requests to L2 cache", + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x24", + "UMask": "0xE4", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "BriefDescription": "L2 code requests", + "PublicDescription": "Counts the total number of L2 code requests.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x28", + "UMask": "0x07", + "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x28", + "UMask": "0x18", + "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x28", + "UMask": "0x20", + "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x32", + "UMask": "0x01", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x32", + "UMask": "0x02", + "EventName": "SW_PREFETCH_ACCESS.T0", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x32", + "UMask": "0x04", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x32", + "UMask": "0x08", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "BriefDescription": "Number of PREFETCHW instructions executed.", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x3C", + "UMask": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "BriefDescription": "Thread cycles when thread is not in halt state", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x3c", + "UMask": "0x01", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x3C", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x3c", + "UMask": "0x08", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING", + "BriefDescription": "Number of L1D misses that are outstanding", + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", + "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x48", + "UMask": "0x04", + "EventName": "L1D_PEND_MISS.L2_STALL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x49", + "UMask": "0x02", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x49", + "UMask": "0x04", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x49", + "UMask": "0x0E", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x49", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x4c", + "UMask": "0x01", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x51", + "UMask": "0x01", + "EventName": "L1D.REPLACEMENT", + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", + "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x54", + "UMask": "0x01", + "EventName": "TX_MEM.ABORT_CONFLICT", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x54", + "UMask": "0x02", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x54", + "UMask": "0x80", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x5d", + "UMask": "0x02", + "EventName": "TX_EXEC.MISC2", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", + "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x5d", + "UMask": "0x04", + "EventName": "TX_EXEC.MISC3", + "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", + "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x5E", + "UMask": "0x01", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x5E", + "UMask": "0x01", + "EventName": "RS_EVENTS.EMPTY_END", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x60", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read transactions pending for off-core. Highly correlated.", + "PublicDescription": "Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x60", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x60", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x60", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.", + "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x60", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x60", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x60", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x63", + "UMask": "0x02", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "BriefDescription": "Cycles when L1D is locked", + "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_OK", + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_ANY", + "BriefDescription": "Cycles MITE is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_OK", + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_ANY", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "EventName": "IDQ.MS_SWITCHES", + "BriefDescription": "Number of switches from DSB or MITE to the MS", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "BriefDescription": "Uops delivered to IDQ while MS is busy", + "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES_ANY", + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_16B.IFDATA_STALL", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x83", + "UMask": "0x01", + "EventName": "ICACHE_64B.IFTAG_HIT", + "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x83", + "UMask": "0x02", + "EventName": "ICACHE_64B.IFTAG_MISS", + "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x83", + "UMask": "0x04", + "EventName": "ICACHE_64B.IFTAG_STALL", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x85", + "UMask": "0x02", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x85", + "UMask": "0x04", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x85", + "UMask": "0x0e", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x85", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x87", + "UMask": "0x01", + "EventName": "ILD_STALL.LCP", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x9C", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0x9C", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa1", + "UMask": "0x01", + "EventName": "UOPS_DISPATCHED.PORT_0", + "BriefDescription": "Number of uops executed on port 0", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa1", + "UMask": "0x02", + "EventName": "UOPS_DISPATCHED.PORT_1", + "BriefDescription": "Number of uops executed on port 1", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa1", + "UMask": "0x04", + "EventName": "UOPS_DISPATCHED.PORT_2_3", + "BriefDescription": "Number of uops executed on port 2 and 3", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa1", + "UMask": "0x10", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "BriefDescription": "Number of uops executed on port 4 and 9", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa1", + "UMask": "0x20", + "EventName": "UOPS_DISPATCHED.PORT_5", + "BriefDescription": "Number of uops executed on port 5", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa1", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED.PORT_6", + "BriefDescription": "Number of uops executed on port 6", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa1", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "BriefDescription": "Number of uops executed on port 7 and 8", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa2", + "UMask": "0x02", + "EventName": "RESOURCE_STALLS.SCOREBOARD", + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "PublicDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA2", + "UMask": "0x08", + "EventName": "RESOURCE_STALLS.SB", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA3", + "UMask": "0x01", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA3", + "UMask": "0x04", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "BriefDescription": "Total execution stalls.", + "PublicDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA3", + "UMask": "0x05", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA3", + "UMask": "0x06", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA3", + "UMask": "0x08", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA3", + "UMask": "0x0C", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "12", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA3", + "UMask": "0x10", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "PublicDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "16", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA3", + "UMask": "0x14", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "20", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa4", + "UMask": "0x01", + "EventName": "TOPDOWN.SLOTS_P", + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa4", + "UMask": "0x02", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa4", + "UMask": "0x08", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa6", + "UMask": "0x02", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa6", + "UMask": "0x04", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa6", + "UMask": "0x08", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa6", + "UMask": "0x10", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa6", + "UMask": "0x21", + "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", + "BriefDescription": "Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle.", + "PublicDescription": "Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA6", + "UMask": "0x40", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa6", + "UMask": "0x80", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.", + "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA8", + "UMask": "0x01", + "EventName": "LSD.UOPS", + "BriefDescription": "Number of Uops delivered by the LSD.", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xA8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_ACTIVE", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_OK", + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xAB", + "UMask": "0x02", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xab", + "UMask": "0x02", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", + "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb0", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests sent to uncore", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xB0", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb0", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "BriefDescription": "Demand and prefetch data reads", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb0", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests who miss L3 cache", + "PublicDescription": "Demand Data Read requests who miss L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb0", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "BriefDescription": "Any memory transaction that reached the SQ.", + "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xB1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.THREAD", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xB1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE", + "BriefDescription": "Number of uops executed on the core.", + "PublicDescription": "Counts the number of uops executed from any thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xB1", + "UMask": "0x10", + "EventName": "UOPS_EXECUTED.X87", + "BriefDescription": "Counts the number of x87 uops dispatched.", + "PublicDescription": "Counts the number of x87 uops executed.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xBD", + "UMask": "0x01", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xbd", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "BriefDescription": "STLB flush attempts", + "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xC1", + "UMask": "0x01", + "EventName": "ASSISTS.PAGE_A_D", + "BriefDescription": "Page access/dirty assists.", + "PublicDescription": "Counts page access/dirty assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc1", + "UMask": "0x02", + "EventName": "ASSISTS.FP", + "BriefDescription": "Counts all microcode FP assists.", + "PublicDescription": "Counts all microcode Floating Point assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc1", + "UMask": "0x07", + "EventName": "ASSISTS.ANY", + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "This event counts cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "10", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.SLOTS", + "BriefDescription": "Retirement slots used.", + "PublicDescription": "Counts the retirement slots used each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xC3", + "UMask": "0x01", + "EventName": "MACHINE_CLEARS.COUNT", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x02", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xC3", + "UMask": "0x04", + "EventName": "MACHINE_CLEARS.SMC", + "BriefDescription": "Self-modifying code (SMC) detected.", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "BriefDescription": "All branch instructions retired.", + "PublicDescription": "Counts all branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x01", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Taken conditional branch instructions retired.", + "PublicDescription": "Counts taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x02", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x08", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "BriefDescription": "Return instructions retired.", + "PublicDescription": "Counts return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "Counts not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x11", + "EventName": "BR_INST_RETIRED.COND", + "BriefDescription": "Conditional branch instructions retired.", + "PublicDescription": "Counts conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Taken branch instructions retired.", + "PublicDescription": "Counts taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "Counts far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "EventName": "BR_INST_RETIRED.INDIRECT", + "BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch).", + "PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "All mispredicted branch instructions retired.", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x02", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Mispredicted indirect CALL instructions retired.", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x10", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x11", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x80", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500206", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500406", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500806", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x501006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x502006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x504006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x508006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x510006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x520006", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500106", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x40", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x80", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x01", + "EventName": "RTM_RETIRED.START", + "BriefDescription": "Number of times an RTM execution started.", + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x02", + "EventName": "RTM_RETIRED.COMMIT", + "BriefDescription": "Number of times an RTM execution successfully committed", + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x04", + "EventName": "RTM_RETIRED.ABORTED", + "BriefDescription": "Number of times an RTM execution aborted.", + "PublicDescription": "Counts the number of times RTM abort was triggered.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x08", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x80", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcc", + "UMask": "0x20", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcc", + "UMask": "0x40", + "EventName": "MISC_RETIRED.PAUSE_INST", + "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20011", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2003", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1009", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "503", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "101", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x11", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "BriefDescription": "Retired load instructions that miss the STLB.", + "PublicDescription": "Counts retired load instructions that true miss the STLB.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x12", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "BriefDescription": "Retired store instructions that miss the STLB.", + "PublicDescription": "Counts retired store instructions that true miss the STLB.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x21", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "BriefDescription": "Retired load instructions with locked access.", + "PublicDescription": "Counts retired load instructions with locked access.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x41", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x42", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "BriefDescription": "All retired load instructions.", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x82", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "BriefDescription": "All retired store instructions.", + "PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x01", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x02", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x08", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x20", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "TBD", + "PublicDescription": "TBD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "BriefDescription": "TBD", + "PublicDescription": "TBD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", + "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xE6", + "UMask": "0x01", + "EventName": "BACLEARS.ANY", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xec", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xF0", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "BriefDescription": "L2 writebacks that access L2 cache", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xf1", + "UMask": "0x1f", + "EventName": "L2_LINES_IN.ALL", + "BriefDescription": "L2 cache lines filling L2", + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xf2", + "UMask": "0x01", + "EventName": "L2_LINES_OUT.SILENT", + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xf2", + "UMask": "0x02", + "EventName": "L2_LINES_OUT.NON_SILENT", + "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", + "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + }, + { + "EventCode": "0xf4", + "UMask": "0x04", + "EventName": "SQ_MISC.SQ_FULL", + "BriefDescription": "Cycles the superQ cannot take any more entries.", + "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "0", + "Offcore": "0" + } +]
\ No newline at end of file diff --git a/usr/src/data/perfmon/THIRDPARTYLICENSE b/usr/src/data/perfmon/THIRDPARTYLICENSE index 77d6183a28..f01d80466b 100644 --- a/usr/src/data/perfmon/THIRDPARTYLICENSE +++ b/usr/src/data/perfmon/THIRDPARTYLICENSE @@ -1,28 +1,33 @@ -Copyright (c) 2001-2015, Intel Corporation -All rights reserved. +The following files are distributed under the terms of the 3-clause BSD license: -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: +- Mapfile.csv +- All .tsv files +- All .json files - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. +Copyright (C) 2018 Intel Corporation - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. +1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. +3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +SPDX-License-Identifier: BSD-3-Clause diff --git a/usr/src/data/perfmon/mapfile.csv b/usr/src/data/perfmon/mapfile.csv index af0f905e2d..6ead625ca7 100644 --- a/usr/src/data/perfmon/mapfile.csv +++ b/usr/src/data/perfmon/mapfile.csv @@ -33,62 +33,76 @@ GenuineIntel-6-3A,V21,/IVB/ivybridge_uncore_v21.json,uncore GenuineIntel-6-3E,V20,/IVT/ivytown_core_v20.json,core GenuineIntel-6-3E,V20,/IVT/ivytown_matrix_v20.json,offcore GenuineIntel-6-3E,V20,/IVT/ivytown_uncore_v20.json,uncore -GenuineIntel-6-3C,V28,/HSW/haswell_core_v28.json,core -GenuineIntel-6-45,V28,/HSW/haswell_core_v28.json,core -GenuineIntel-6-46,V28,/HSW/haswell_core_v28.json,core -GenuineIntel-6-3C,V28,/HSW/haswell_matrix_v28.json,offcore -GenuineIntel-6-45,V28,/HSW/haswell_matrix_v28.json,offcore -GenuineIntel-6-46,V28,/HSW/haswell_matrix_v28.json,offcore -GenuineIntel-6-3C,V28,/HSW/haswell_uncore_v28.json,uncore -GenuineIntel-6-45,V28,/HSW/haswell_uncore_v28.json,uncore -GenuineIntel-6-46,V28,/HSW/haswell_uncore_v28.json,uncore -GenuineIntel-6-3F,V20,/HSX/haswellx_core_v20.json,core -GenuineIntel-6-3F,V20,/HSX/haswellx_matrix_v20.json,offcore -GenuineIntel-6-3F,V20,/HSX/haswellx_uncore_v20.json,uncore -GenuineIntel-6-3D,V23,/BDW/broadwell_core_v23.json,core -GenuineIntel-6-3D,V23,/BDW/broadwell_matrix_v23.json,offcore -GenuineIntel-6-3D,V23,/BDW/broadwell_uncore_v23.json,uncore -GenuineIntel-6-3D,V23,/BDW/broadwell_fp_arith_inst_v23.json,fp_arith_inst -GenuineIntel-6-47,V23,/BDW/broadwell_core_v23.json,core -GenuineIntel-6-47,V23,/BDW/broadwell_matrix_v23.json,offcore -GenuineIntel-6-47,V23,/BDW/broadwell_uncore_v23.json,uncore -GenuineIntel-6-47,V23,/BDW/broadwell_fp_arith_inst_v23.json,fp_arith_inst -GenuineIntel-6-4F,V14,/BDX/broadwellx_core_v14.json,core -GenuineIntel-6-4F,V14,/BDX/broadwellx_matrix_v14.json,offcore -GenuineIntel-6-4F,V14,/BDX/broadwellx_uncore_v14.json,uncore +GenuineIntel-6-3C,V30,/HSW/haswell_core_v30.json,core +GenuineIntel-6-45,V30,/HSW/haswell_core_v30.json,core +GenuineIntel-6-46,V30,/HSW/haswell_core_v30.json,core +GenuineIntel-6-3C,V30,/HSW/haswell_matrix_v30.json,offcore +GenuineIntel-6-45,V30,/HSW/haswell_matrix_v30.json,offcore +GenuineIntel-6-46,V30,/HSW/haswell_matrix_v30.json,offcore +GenuineIntel-6-3C,V30,/HSW/haswell_uncore_v30.json,uncore +GenuineIntel-6-45,V30,/HSW/haswell_uncore_v30.json,uncore +GenuineIntel-6-46,V30,/HSW/haswell_uncore_v30.json,uncore +GenuineIntel-6-3F,V22,/HSX/haswellx_core_v22.json,core +GenuineIntel-6-3F,V22,/HSX/haswellx_matrix_v22.json,offcore +GenuineIntel-6-3F,V22,/HSX/haswellx_uncore_v22.json,uncore +GenuineIntel-6-3D,V26,/BDW/broadwell_core_v26.json,core +GenuineIntel-6-3D,V26,/BDW/broadwell_matrix_v26.json,offcore +GenuineIntel-6-3D,V26,/BDW/broadwell_uncore_v26.json,uncore +GenuineIntel-6-3D,V26,/BDW/broadwell_fp_arith_inst_v26.json,fp_arith_inst +GenuineIntel-6-47,V26,/BDW/broadwell_core_v26.json,core +GenuineIntel-6-47,V26,/BDW/broadwell_matrix_v26.json,offcore +GenuineIntel-6-47,V26,/BDW/broadwell_uncore_v26.json,uncore +GenuineIntel-6-47,V26,/BDW/broadwell_fp_arith_inst_v26.json,fp_arith_inst +GenuineIntel-6-4F,V17,/BDX/broadwellx_core_v17.json,core +GenuineIntel-6-4F,V17,/BDX/broadwellx_matrix_v17.json,offcore +GenuineIntel-6-4F,V17,/BDX/broadwellx_uncore_v17.json,uncore GenuineIntel-6-56,V23,/BDW-DE/broadwellde_core_v7.json,core GenuineIntel-6-56,V23,/BDW-DE/broadwellde_uncore_v7.json,uncore -GenuineIntel-6-4E,V42,/SKL/skylake_core_v42.json,core -GenuineIntel-6-5E,V42,/SKL/skylake_core_v42.json,core -GenuineIntel-6-4E,V42,/SKL/skylake_matrix_v42.json,offcore -GenuineIntel-6-5E,V42,/SKL/skylake_matrix_v42.json,offcore -GenuineIntel-6-4E,V42,/SKL/skylake_uncore_v42.json,uncore -GenuineIntel-6-5E,V42,/SKL/skylake_uncore_v42.json,uncore -GenuineIntel-6-4E,V42,/SKL/skylake_fp_arith_inst_v42.json,fp_arith_inst -GenuineIntel-6-5E,V42,/SKL/skylake_fp_arith_inst_v42.json,fp_arith_inst -GenuineIntel-6-8E,V42,/SKL/skylake_core_v42.json,core -GenuineIntel-6-9E,V42,/SKL/skylake_core_v42.json,core -GenuineIntel-6-8E,V42,/SKL/skylake_matrix_v42.json,offcore -GenuineIntel-6-9E,V42,/SKL/skylake_matrix_v42.json,offcore -GenuineIntel-6-8E,V42,/SKL/skylake_uncore_v42.json,uncore -GenuineIntel-6-9E,V42,/SKL/skylake_uncore_v42.json,uncore -GenuineIntel-6-8E,V42,/SKL/skylake_fp_arith_inst_v42.json,fp_arith_inst -GenuineIntel-6-9E,V42,/SKL/skylake_fp_arith_inst_v42.json,fp_arith_inst +GenuineIntel-6-4E,V50,/SKL/skylake_core_v50.json,core +GenuineIntel-6-5E,V50,/SKL/skylake_core_v50.json,core +GenuineIntel-6-4E,V50,/SKL/skylake_matrix_v50.json,offcore +GenuineIntel-6-5E,V50,/SKL/skylake_matrix_v50.json,offcore +GenuineIntel-6-4E,V50,/SKL/skylake_uncore_v50.json,uncore +GenuineIntel-6-5E,V50,/SKL/skylake_uncore_v50.json,uncore +GenuineIntel-6-4E,V50,/SKL/skylake_fp_arith_inst_v50.json,fp_arith_inst +GenuineIntel-6-5E,V50,/SKL/skylake_fp_arith_inst_v50.json,fp_arith_inst +GenuineIntel-6-8E,V50,/SKL/skylake_core_v50.json,core +GenuineIntel-6-9E,V50,/SKL/skylake_core_v50.json,core +GenuineIntel-6-8E,V50,/SKL/skylake_matrix_v50.json,offcore +GenuineIntel-6-9E,V50,/SKL/skylake_matrix_v50.json,offcore +GenuineIntel-6-8E,V50,/SKL/skylake_uncore_v50.json,uncore +GenuineIntel-6-9E,V50,/SKL/skylake_uncore_v50.json,uncore +GenuineIntel-6-8E,V50,/SKL/skylake_fp_arith_inst_v50.json,fp_arith_inst +GenuineIntel-6-9E,V50,/SKL/skylake_fp_arith_inst_v50.json,fp_arith_inst +GenuineIntel-6-A5,V50,/SKL/skylake_core_v50.json,core +GenuineIntel-6-A6,V50,/SKL/skylake_core_v50.json,core +GenuineIntel-6-A5,V50,/SKL/skylake_matrix_v50.json,offcore +GenuineIntel-6-A6,V50,/SKL/skylake_matrix_v50.json,offcore +GenuineIntel-6-A5,V50,/SKL/skylake_uncore_v50.json,uncore +GenuineIntel-6-A6,V50,/SKL/skylake_uncore_v50.json,uncore +GenuineIntel-6-A5,V50,/SKL/skylake_fp_arith_inst_v50.json,fp_arith_inst +GenuineIntel-6-A6,V50,/SKL/skylake_fp_arith_inst_v50.json,fp_arith_inst GenuineIntel-6-57,V9,/KNL/KnightsLanding_core_V9.json,core GenuineIntel-6-57,V9,/KNL/KnightsLanding_matrix_V9.json,offcore GenuineIntel-6-57,V9,/KNL/KnightsLanding_uncore_V9.json,uncore GenuineIntel-6-85,V9,/KNM/KnightsLanding_core_V9.json,core GenuineIntel-6-85,V9,/KNM/KnightsLanding_matrix_V9.json,offcore GenuineIntel-6-85,V9,/KNM/KnightsLanding_uncore_V9.json,uncore -GenuineIntel-6-55-[01234],V1.12,/SKX/skylakex_core_v1.12.json,core -GenuineIntel-6-55-[01234],V1.12,/SKX/skylakex_matrix_v1.12.json,offcore -GenuineIntel-6-55-[01234],V1.12,/SKX/skylakex_fp_arith_inst_v1.12.json,fp_arith_inst -GenuineIntel-6-55-[01234],V1.12,/SKX/skylakex_uncore_v1.12.json,uncore -GenuineIntel-6-55-[01234],V1.12,/SKX/skylakex_uncore_v1.12_experimental.json,uncore experimental -GenuineIntel-6-55-[56789ABCDEF],V1.00,/CLX/cascadelakex_core_v1.00.json,core -GenuineIntel-6-55-[56789ABCDEF],V1.00,/CLX/cascadelakex_fp_arith_inst_v1.00.json,fp_arith_inst -GenuineIntel-6-55-[56789ABCDEF],V1.00,/CLX/cascadelakex_uncore_v1.00.json,uncore -GenuineIntel-6-55-[56789ABCDEF],V1.00,/CLX/cascadelakex_uncore_v1.00_experimental.json,uncore experimental +GenuineIntel-6-55-[01234],V1.24,/SKX/skylakex_core_v1.24.json,core +GenuineIntel-6-55-[01234],V1.24,/SKX/skylakex_matrix_v1.24.json,offcore +GenuineIntel-6-55-[01234],V1.24,/SKX/skylakex_fp_arith_inst_v1.24.json,fp_arith_inst +GenuineIntel-6-55-[01234],V1.24,/SKX/skylakex_uncore_v1.24.json,uncore +GenuineIntel-6-55-[01234],V1.24,/SKX/skylakex_uncore_v1.24_experimental.json,uncore experimental +GenuineIntel-6-55-[56789ABCDEF],V1.11,/CLX/cascadelakex_core_v1.11.json,core +GenuineIntel-6-55-[56789ABCDEF],V1.11,/CLX/cascadelakex_fp_arith_inst_v1.11.json,fp_arith_inst +GenuineIntel-6-55-[56789ABCDEF],V1.11,/CLX/cascadelakex_uncore_v1.11.json,uncore +GenuineIntel-6-55-[56789ABCDEF],V1.11,/CLX/cascadelakex_uncore_v1.11_experimental.json,uncore experimental GenuineIntel-6-7A,V1.01,/GLP/goldmontplus_core_v1.01.json,core GenuineIntel-6-7A,V1.01,/GLP/goldmontplus_fp_arith_inst_v1.01.json,fp_arith_inst GenuineIntel-6-7A,V1.01,/GLP/goldmontplus_matrix_v1.01.json,offcore +GenuineIntel-6-7E,V1.09,/ICL/icelake_core_v1.09.json,core +GenuineIntel-6-7E,V1.09,/ICL/icelake_uncore_v1.09.json,uncore +GenuineIntel-6-86,V1.10,/SNR/snowridgex_core_v1.10.json,core +GenuineIntel-6-86,V1.10,/SNR/snowridgex_uncore_v1.10.json,uncore +GenuineIntel-6-8C,V1.00,/TGL/tigerlake_core_v1.00.json,core +GenuineIntel-6-8D,V1.00,/TGL/tigerlake_core_v1.00.json,core diff --git a/usr/src/data/perfmon/readme.txt b/usr/src/data/perfmon/readme.txt index ba20a6404b..e671bf872d 100644 --- a/usr/src/data/perfmon/readme.txt +++ b/usr/src/data/perfmon/readme.txt @@ -25,30 +25,30 @@ of events may vary. --------------------- Licensing Information --------------------- -The following files are distributed under the terms of the 3-clause BSD license: +The following files are distributed under the terms of the 3-clause BSD license: - Mapfile.csv - All .tsv files -- All .json files +- All .json files Copyright (C) 2018 Intel Corporation - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - + 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. + this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software - without specific prior written permission. - + may be used to endorse or promote products derived from this software + without specific prior written permission. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; @@ -56,7 +56,7 @@ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - + SPDX-License-Identifier: BSD-3-Clause @@ -230,4 +230,4 @@ Contact your local Intel sales office or your distributor to obtain the latest s Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm -Copyright 2014 Intel Corporation. All rights reserved. +Copyright 2014 Intel Corporation. All rights reserved.
\ No newline at end of file diff --git a/usr/src/man/man3cpc/cpc.3cpc b/usr/src/man/man3cpc/cpc.3cpc index 3a4e86819f..6dba6eba44 100644 --- a/usr/src/man/man3cpc/cpc.3cpc +++ b/usr/src/man/man3cpc/cpc.3cpc @@ -3,7 +3,8 @@ .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] .\" Copyright (c) 2019, Joyent, Inc. -.Dd March 27, 2020 +.\" Copyright 2021 Oxide Computer Company +.Dd January 22, 2021 .Dt CPC 3CPC .Os .Sh NAME @@ -101,6 +102,8 @@ Intel Goldmont Plus SoC events; covers model 7ah. Intel Haswell client events; covers models 46h, 45h, and 3ch. .It Xr hsx_events 3CPC Intel Haswell server events; covers model 3fh. +.It xr icl_events 3CPC +Intel Ice Lake client events; covers model 7eh. .It Xr ivb_events 3CPC Intel Ivy Bridge client events; covers model 3ah. .It Xr ivt_events 3CPC @@ -112,13 +115,17 @@ Intel Nehalem-EP events; covers models, 1ah, 1fh, and 1eh. .It Xr nhm_ex_events 3CPC Intel Sandy Bridge server events; covers model 23h. .It Xr skl_events 3CPC -Intel Skylake client events; covers model 9eh, 8eh, 5e, and 4eh. +Intel Skylake client events; covers model a6h, a5h, 9eh, 8eh, 5e, and 4eh. .It Xr skx_events 3CPC Intel Skylake server events; covers model 55h, steppings 0-4h. .It Xr slm_events 3CPC Intel Atom Silvermont events; covers models 4ch, 4dh, and 37h. +.It Xr snr_Events 3CPC +Intel Atom Snow Ridge events; covers model 86h. .It Xr snb_events 3CPC -Intel Sandy Bridge Client events; covers model 2ah. +Intel Sandy Bridge client events; covers model 2ah. +.It Xr tgl_events 3CPC +Intel Tiger Lake client events; covers models 8ch and 8dh. .It Xr wsm_ep_dp_events 3CPC Intel Westmere-EP-DP events; covers model 2ch. .It Xr wsm_ep_sp_events 3CPC diff --git a/usr/src/pkg/manifests/diagnostic-cpu-counters.mf b/usr/src/pkg/manifests/diagnostic-cpu-counters.mf index 3c4f3cb233..7f43507bbf 100644 --- a/usr/src/pkg/manifests/diagnostic-cpu-counters.mf +++ b/usr/src/pkg/manifests/diagnostic-cpu-counters.mf @@ -23,6 +23,7 @@ # Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. # Copyright 2012 Nexenta Systems, Inc. All rights reserved. # Copyright 2019 OmniOS Community Edition (OmniOSce) Association. +# Copyright 2021 Oxide Computer Company # set name=pkg.fmri value=pkg:/diagnostic/cpu-counters@$(PKGVERS) @@ -97,6 +98,7 @@ $(i386_ONLY)file path=usr/share/man/man3cpc/glm_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/glp_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/hsw_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/hsx_events.3cpc +$(i386_ONLY)file path=usr/share/man/man3cpc/icl_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/ivb_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/ivt_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/jkt_events.3cpc @@ -108,6 +110,8 @@ $(i386_ONLY)file path=usr/share/man/man3cpc/skl_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/skx_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/slm_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/snb_events.3cpc +$(i386_ONLY)file path=usr/share/man/man3cpc/snr_events.3cpc +$(i386_ONLY)file path=usr/share/man/man3cpc/tgl_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/wsm_ep_dp_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/wsm_ep_sp_events.3cpc $(i386_ONLY)file path=usr/share/man/man3cpc/wsm_ex_events.3cpc @@ -146,10 +150,22 @@ $(i386_ONLY)link path=usr/kernel/pcbe/$(ARCH64)/pcbe.GenuineIntel.6.47 \ target=pcbe.GenuineIntel.6.15 $(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.122 \ target=pcbe.GenuineIntel.6.15 +$(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.126 \ + target=pcbe.GenuineIntel.6.15 +$(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.134 \ + target=pcbe.GenuineIntel.6.15 +$(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.140 \ + target=pcbe.GenuineIntel.6.15 +$(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.141 \ + target=pcbe.GenuineIntel.6.15 $(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.142 \ target=pcbe.GenuineIntel.6.15 $(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.158 \ target=pcbe.GenuineIntel.6.15 +$(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.165 \ + target=pcbe.GenuineIntel.6.15 +$(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.166 \ + target=pcbe.GenuineIntel.6.15 $(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.38 \ target=pcbe.GenuineIntel.6.15 $(i386_ONLY)link path=usr/kernel/pcbe/amd64/pcbe.GenuineIntel.6.39 \ diff --git a/usr/src/tools/cpcgen/cpcgen.c b/usr/src/tools/cpcgen/cpcgen.c index 967081dd12..bbc1126610 100644 --- a/usr/src/tools/cpcgen/cpcgen.c +++ b/usr/src/tools/cpcgen/cpcgen.c @@ -11,6 +11,7 @@ /* * Copyright 2019, Joyent, Inc. + * Copyright 2021 Oxide Computer Company */ /* @@ -109,11 +110,16 @@ static cpc_whitelist_t cpcgen_intel_whitelist[] = { { "SKX", "skx", CPC_FILE_CORE }, /* Cascade Lake */ { "CLX", "clx", CPC_FILE_CORE }, + /* Ice Lake */ + { "ICL", "icl", CPC_FILE_CORE }, + /* Tiger Lake */ + { "TGL", "tgl", CPC_FILE_CORE }, /* Atom */ { "BNL", "bnl", CPC_FILE_CORE }, { "SLM", "slm", CPC_FILE_CORE }, { "GLM", "glm", CPC_FILE_CORE }, { "GLP", "glp", CPC_FILE_CORE }, + { "SNR", "snr", CPC_FILE_CORE }, { NULL } }; @@ -1068,6 +1074,13 @@ cpcgen_cfile_intel_event(FILE *f, nvlist_t *nvl, const char *path, uint_t ent) cmask = "C0|C1|C2"; } else if (strcmp(counter, "0,1,2,3") == 0) { cmask = "C0|C1|C2|C3"; + } else if (strcmp(counter, "0,1,2,3,4,5,6,7") == 0) { + /* + * We don't support the larger number of counters on some + * platforms right now, so just truncate it to the supported + * set. + */ + cmask = "C0|C1|C2|C3"; } else if (strcmp(counter, "0,2,3") == 0) { cmask = "C0|C2|C3"; } else if (strcmp(counter, "1,2,3") == 0) { @@ -1345,7 +1358,8 @@ cpcgen_common_intel_files(int dirfd) * another field. * - Offcore is one, indicating that it is off the core and we need to figure * out if we can support this. - * - If the counter is fixed, don't use it for now. + * - If the counter is fixed, don't use it for now. "32"-"35" is another name + * for the fixed counters. * - If more than one value is specified in the EventCode or UMask values */ static boolean_t @@ -1398,6 +1412,9 @@ cpcgen_skip_intel_entry(nvlist_t *nvl, const char *path, uint_t ent) if (strncasecmp(counter, "fixed", strlen("fixed")) == 0) return (B_TRUE); + if (strcmp(counter, "32") == 0 || strcmp(counter, "33") == 0 || + strcmp(counter, "34") == 0 || strcmp(counter, "35") == 0) + return (B_TRUE); return (B_FALSE); } diff --git a/usr/src/uts/intel/core_pcbe/Makefile b/usr/src/uts/intel/core_pcbe/Makefile index 572fd7b212..abb2713efc 100644 --- a/usr/src/uts/intel/core_pcbe/Makefile +++ b/usr/src/uts/intel/core_pcbe/Makefile @@ -22,6 +22,7 @@ # Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. # # Copyright 2019, Joyent, Inc. +# Copyright 2021 Oxide Computer Company # # This Makefile builds # the Intel Core Architecture Performance Counter BackEnd (PCBE). @@ -43,6 +44,7 @@ CPCGEN_OBJS = \ core_pcbe_glp.o \ core_pcbe_hsw.o \ core_pcbe_hsx.o \ + core_pcbe_icl.o \ core_pcbe_ivb.o \ core_pcbe_ivt.o \ core_pcbe_jkt.o \ @@ -52,6 +54,8 @@ CPCGEN_OBJS = \ core_pcbe_skx.o \ core_pcbe_slm.o \ core_pcbe_snb.o \ + core_pcbe_snr.o \ + core_pcbe_tgl.o \ core_pcbe_wsm_ep_dp.o \ core_pcbe_wsm_ep_sp.o \ core_pcbe_wsm_ex.o @@ -98,6 +102,8 @@ SOFTLINKS = \ pcbe.GenuineIntel.6.94 \ pcbe.GenuineIntel.6.142 \ pcbe.GenuineIntel.6.158 \ + pcbe.GenuineIntel.6.165 \ + pcbe.GenuineIntel.6.166 \ pcbe.GenuineIntel.6.28 \ pcbe.GenuineIntel.6.38 \ pcbe.GenuineIntel.6.39 \ @@ -108,7 +114,11 @@ SOFTLINKS = \ pcbe.GenuineIntel.6.76 \ pcbe.GenuineIntel.6.92 \ pcbe.GenuineIntel.6.95 \ - pcbe.GenuineIntel.6.122 + pcbe.GenuineIntel.6.122 \ + pcbe.GenuineIntel.6.126 \ + pcbe.GenuineIntel.6.134 \ + pcbe.GenuineIntel.6.140 \ + pcbe.GenuineIntel.6.141 ROOTSOFTLINKS = $(SOFTLINKS:%=$(USR_PCBE_DIR)/%) |