diff options
Diffstat (limited to 'usr/src')
| -rw-r--r-- | usr/src/uts/sun4/io/px/px_dma.c | 4 | ||||
| -rw-r--r-- | usr/src/uts/sun4/io/px/px_ib.c | 10 | ||||
| -rw-r--r-- | usr/src/uts/sun4/io/px/px_intr.c | 4 | ||||
| -rw-r--r-- | usr/src/uts/sun4/io/px/px_lib.h | 13 | ||||
| -rw-r--r-- | usr/src/uts/sun4/io/px/px_mmu.c | 4 | ||||
| -rw-r--r-- | usr/src/uts/sun4/io/px/px_util.c | 5 | ||||
| -rw-r--r-- | usr/src/uts/sun4/io/px/px_var.h | 7 | ||||
| -rw-r--r-- | usr/src/uts/sun4u/io/px/px_hlib.c | 45 | ||||
| -rw-r--r-- | usr/src/uts/sun4u/io/px/px_lib4u.c | 31 | ||||
| -rw-r--r-- | usr/src/uts/sun4u/io/px/px_lib4u.h | 15 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/Makefile.files | 2 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/io/px/px_asm_4v.h | 42 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/io/px/px_asm_4v.s | 82 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/io/px/px_hcall.s | 723 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/io/px/px_lib4v.c | 69 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/io/px/px_lib4v.h | 31 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/io/px/px_tools_4v.c | 8 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/ml/hcall.s | 653 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/os/hsvc.c | 3 |
19 files changed, 860 insertions, 891 deletions
diff --git a/usr/src/uts/sun4/io/px/px_dma.c b/usr/src/uts/sun4/io/px/px_dma.c index 1462ae5c3e..6451a9b32c 100644 --- a/usr/src/uts/sun4/io/px/px_dma.c +++ b/usr/src/uts/sun4/io/px/px_dma.c @@ -703,7 +703,7 @@ px_dvma_map_fast(px_mmu_t *mmu_p, ddi_dma_impl_t *mp) dvma_pg = mmu_p->dvma_base_pg + i; if (px_lib_iommu_map(dip, PCI_TSBID(0, i), npages, attr, - (void *)mp, 0, MMU_MAP_MP) != DDI_SUCCESS) { + (void *)mp, 0, MMU_MAP_PFN) != DDI_SUCCESS) { DBG(DBG_MAP_WIN, dip, "px_dvma_map_fast: " "px_lib_iommu_map failed\n"); @@ -718,7 +718,7 @@ px_dvma_map_fast(px_mmu_t *mmu_p, ddi_dma_impl_t *mp) ASSERT(PX_HAS_REDZONE(mp)); if (px_lib_iommu_map(dip, PCI_TSBID(0, i + npages), 1, attr, - (void *)mp, npages - 1, MMU_MAP_MP) != DDI_SUCCESS) { + (void *)mp, npages - 1, MMU_MAP_PFN) != DDI_SUCCESS) { DBG(DBG_MAP_WIN, dip, "px_dvma_map_fast: " "mapping REDZONE page failed\n"); diff --git a/usr/src/uts/sun4/io/px/px_ib.c b/usr/src/uts/sun4/io/px/px_ib.c index bb9300b04f..e995025edc 100644 --- a/usr/src/uts/sun4/io/px/px_ib.c +++ b/usr/src/uts/sun4/io/px/px_ib.c @@ -2,9 +2,8 @@ * CDDL HEADER START * * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. @@ -20,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * Copyright 2006 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -795,7 +794,8 @@ pxtool_ib_get_ino_devs( } -void px_ib_log_new_cpu(px_ib_t *ib_p, uint32_t old_cpu_id, uint32_t new_cpu_id, +void +px_ib_log_new_cpu(px_ib_t *ib_p, uint32_t old_cpu_id, uint32_t new_cpu_id, uint32_t ino) { px_ib_ino_info_t *ino_p; diff --git a/usr/src/uts/sun4/io/px/px_intr.c b/usr/src/uts/sun4/io/px/px_intr.c index f9123bf2fd..87296e216e 100644 --- a/usr/src/uts/sun4/io/px/px_intr.c +++ b/usr/src/uts/sun4/io/px/px_intr.c @@ -398,8 +398,8 @@ px_class_val_t px_default_pil [] = { {0x020000, 0xff0000, 0x6}, /* Network Controller */ {0x030000, 0xff0000, 0x9}, /* Display Controller */ {0x040000, 0xff0000, 0x9}, /* Multimedia Controller */ - {0x050000, 0xff0000, 0xb}, /* Memory Controller */ - {0x060000, 0xff0000, 0xb}, /* Bridge Controller */ + {0x050000, 0xff0000, 0x9}, /* Memory Controller */ + {0x060000, 0xff0000, 0x9}, /* Bridge Controller */ {0x0c0000, 0xffff00, 0x9}, /* Serial Bus, FireWire (IEEE 1394) */ {0x0c0100, 0xffff00, 0x4}, /* Serial Bus, ACCESS.bus */ {0x0c0200, 0xffff00, 0x4}, /* Serial Bus, SSA */ diff --git a/usr/src/uts/sun4/io/px/px_lib.h b/usr/src/uts/sun4/io/px/px_lib.h index b07540e501..e8eead3807 100644 --- a/usr/src/uts/sun4/io/px/px_lib.h +++ b/usr/src/uts/sun4/io/px/px_lib.h @@ -51,8 +51,8 @@ extern "C" { #define MMU_BTOPR(x) MMU_BTOP((x) + MMU_PAGE_OFFSET) /* MMU map flags */ -#define MMU_MAP_MP 0 -#define MMU_MAP_BUF 1 +#define MMU_MAP_PFN 1 +#define MMU_MAP_BUF 2 typedef struct px px_t; typedef struct px_msiq px_msiq_t; @@ -62,6 +62,7 @@ extern int px_lib_dev_fini(dev_info_t *dip); extern int px_lib_map_vconfig(dev_info_t *dip, ddi_map_req_t *mp, pci_config_offset_t off, pci_regspec_t *rp, caddr_t *addrp); extern void px_lib_map_attr_check(ddi_map_req_t *mp); + extern int px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, sysino_t *sysino); extern int px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, @@ -84,14 +85,14 @@ extern void px_fill_rc_status(px_fault_t *px_fault_p, #endif extern int px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, - io_attributes_t io_attributes, void *addr, size_t pfn_index, int flag); + io_attributes_t attr, void *addr, size_t pfn_index, int flags); extern int px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages); extern int px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, - io_attributes_t *attributes_p, r_addr_t *r_addr_p); -extern int px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, + io_attributes_t *attr_p, r_addr_t *r_addr_p); +extern int px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attr_p, uint64_t *lo_p, uint64_t *hi_p); extern int px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, - io_attributes_t io_attributes, io_addr_t *io_addr_p); + io_attributes_t attr, io_addr_t *io_addr_p); extern int px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, off_t off, size_t len, uint_t cache_flags); diff --git a/usr/src/uts/sun4/io/px/px_mmu.c b/usr/src/uts/sun4/io/px/px_mmu.c index 82607e2557..6fd0785592 100644 --- a/usr/src/uts/sun4/io/px/px_mmu.c +++ b/usr/src/uts/sun4/io/px/px_mmu.c @@ -172,7 +172,7 @@ px_mmu_map_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_dvma_addr_t dvma_pg, (uint_t)pg_index, dvma_pg, (uint_t)npages, (uint_t)pfn_index); if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index), npages, attr, - (void *)mp, pfn_index, MMU_MAP_MP) != DDI_SUCCESS) { + (void *)mp, pfn_index, MMU_MAP_PFN) != DDI_SUCCESS) { DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: " "px_lib_iommu_map failed\n"); @@ -188,7 +188,7 @@ px_mmu_map_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_dvma_addr_t dvma_pg, ASSERT(PX_HAS_REDZONE(mp)); if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index + npages), 1, attr, - (void *)mp, pfn_index + npages - 1, MMU_MAP_MP) != DDI_SUCCESS) { + (void *)mp, pfn_index + npages - 1, MMU_MAP_PFN) != DDI_SUCCESS) { DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: mapping " "REDZONE page failed\n"); diff --git a/usr/src/uts/sun4/io/px/px_util.c b/usr/src/uts/sun4/io/px/px_util.c index 3d61fc1c18..39db52034a 100644 --- a/usr/src/uts/sun4/io/px/px_util.c +++ b/usr/src/uts/sun4/io/px/px_util.c @@ -108,11 +108,6 @@ px_get_props(px_t *px_p, dev_info_t *dip) return (DDI_FAILURE); } - px_p->px_thermal_interrupt = - ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, - "thermal-interrupt", -1); - DBG(DBG_ATTACH, dip, "get_px_properties: thermal_interrupt=%d\n", - px_p->px_thermal_interrupt); return (DDI_SUCCESS); } diff --git a/usr/src/uts/sun4/io/px/px_var.h b/usr/src/uts/sun4/io/px/px_var.h index 15812d2af1..87441e074c 100644 --- a/usr/src/uts/sun4/io/px/px_var.h +++ b/usr/src/uts/sun4/io/px/px_var.h @@ -115,13 +115,6 @@ struct px { int px_ranges_length; devino_t *px_inos; /* inos from "interrupts" prop */ int px_inos_len; /* "interrupts" length */ - int pci_numproxy; /* upa interrupt proxies */ - int px_thermal_interrupt; /* node has thermal interrupt */ - - /* Interrupt support */ - int intr_map_size; - struct intr_map *intr_map; - struct intr_map_mask *intr_map_mask; /* Error handling */ px_fault_t px_fault; diff --git a/usr/src/uts/sun4u/io/px/px_hlib.c b/usr/src/uts/sun4u/io/px/px_hlib.c index db951a52a9..90368735d7 100644 --- a/usr/src/uts/sun4u/io/px/px_hlib.c +++ b/usr/src/uts/sun4u/io/px/px_hlib.c @@ -2,9 +2,8 @@ * CDDL HEADER START * * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. @@ -20,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * Copyright 2006 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -1600,34 +1599,27 @@ hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p) /* ARGSUSED */ uint64_t -hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, - pages_t pages, io_attributes_t io_attributes, - void *addr, size_t pfn_index, int flag) +hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, pages_t pages, + io_attributes_t io_attr, void *addr, size_t pfn_index, int flags) { tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); uint64_t attr = MMU_TTE_V; int i; - if (io_attributes & PCI_MAP_ATTR_WRITE) + if (io_attr & PCI_MAP_ATTR_WRITE) attr |= MMU_TTE_W; - if (flag == MMU_MAP_MP) { - ddi_dma_impl_t *mp = (ddi_dma_impl_t *)addr; - + if (flags & MMU_MAP_PFN) { + ddi_dma_impl_t *mp = (ddi_dma_impl_t *)addr; for (i = 0; i < pages; i++, pfn_index++, tsb_index++) { - px_iopfn_t pfn = PX_GET_MP_PFN(mp, pfn_index); - - pxu_p->tsb_vaddr[tsb_index] = - MMU_PTOB(pfn) | attr; + px_iopfn_t pfn = PX_GET_MP_PFN(mp, pfn_index); + pxu_p->tsb_vaddr[tsb_index] = MMU_PTOB(pfn) | attr; } } else { - caddr_t a = (caddr_t)addr; - + caddr_t a = (caddr_t)addr; for (i = 0; i < pages; i++, a += MMU_PAGE_SIZE, tsb_index++) { px_iopfn_t pfn = hat_getpfnum(kas.a_hat, a); - - pxu_p->tsb_vaddr[tsb_index] = - MMU_PTOB(pfn) | attr; + pxu_p->tsb_vaddr[tsb_index] = MMU_PTOB(pfn) | attr; } } @@ -1642,9 +1634,8 @@ hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); int i; - for (i = 0; i < pages; i++, tsb_index++) { + for (i = 0; i < pages; i++, tsb_index++) pxu_p->tsb_vaddr[tsb_index] = MMU_INVALID_TTE; - } return (H_EOK); } @@ -1652,7 +1643,7 @@ hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, /* ARGSUSED */ uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, - io_attributes_t *attributes_p, r_addr_t *r_addr_p) + io_attributes_t *attr_p, r_addr_t *r_addr_p) { tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); uint64_t *tte_addr; @@ -1662,11 +1653,11 @@ hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, if (*tte_addr & MMU_TTE_V) { *r_addr_p = MMU_TTETOPA(*tte_addr); - *attributes_p = (*tte_addr & MMU_TTE_W) ? + *attr_p = (*tte_addr & MMU_TTE_W) ? PCI_MAP_ATTR_WRITE:PCI_MAP_ATTR_READ; } else { *r_addr_p = 0; - *attributes_p = 0; + *attr_p = 0; ret = H_ENOMAP; } @@ -1675,8 +1666,8 @@ hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, /* ARGSUSED */ uint64_t -hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, - io_attributes_t io_attributes, io_addr_t *io_addr_p) +hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr, + io_addr_t *io_addr_p) { uint64_t pfn = MMU_BTOP(ra); diff --git a/usr/src/uts/sun4u/io/px/px_lib4u.c b/usr/src/uts/sun4u/io/px/px_lib4u.c index 479a54b0e0..898b816668 100644 --- a/usr/src/uts/sun4u/io/px/px_lib4u.c +++ b/usr/src/uts/sun4u/io/px/px_lib4u.c @@ -454,19 +454,18 @@ px_lib_intr_reset(dev_info_t *dip) /*ARGSUSED*/ int px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, - io_attributes_t io_attributes, void *addr, size_t pfn_index, - int flag) + io_attributes_t attr, void *addr, size_t pfn_index, int flags) { px_t *px_p = DIP_TO_STATE(dip); pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; uint64_t ret; DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " - "pages 0x%x atrr 0x%x addr 0x%p pfn_index 0x%llx, flag 0x%x\n", - dip, tsbid, pages, io_attributes, addr, pfn_index, flag); + "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", + dip, tsbid, pages, attr, addr, pfn_index, flags); if ((ret = hvio_iommu_map(px_p->px_dev_hdl, pxu_p, tsbid, pages, - io_attributes, addr, pfn_index, flag)) != H_EOK) { + attr, addr, pfn_index, flags)) != H_EOK) { DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map failed, ret 0x%lx\n", ret); return (DDI_FAILURE); @@ -499,8 +498,8 @@ px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) /*ARGSUSED*/ int -px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, - io_attributes_t *attributes_p, r_addr_t *r_addr_p) +px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, + r_addr_t *r_addr_p) { px_t *px_p = DIP_TO_STATE(dip); pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; @@ -510,7 +509,7 @@ px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, dip, tsbid); if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), pxu_p, tsbid, - attributes_p, r_addr_p)) != H_EOK) { + attr_p, r_addr_p)) != H_EOK) { DBG(DBG_LIB_DMA, dip, "hvio_iommu_getmap failed, ret 0x%lx\n", ret); @@ -518,7 +517,7 @@ px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, } DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", - *attributes_p, *r_addr_p); + *attr_p, *r_addr_p); return (DDI_SUCCESS); } @@ -531,7 +530,7 @@ px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, */ /*ARGSUSED*/ int -px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, uint64_t *hi_p) +px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attr_p, uint64_t *lo_p, uint64_t *hi_p) { *lo_p = MMU_BYPASS_BASE; *hi_p = MMU_BYPASS_END; @@ -542,16 +541,16 @@ px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, uint64_t *hi_p) /*ARGSUSED*/ int -px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, - io_attributes_t io_attributes, io_addr_t *io_addr_p) +px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, + io_addr_t *io_addr_p) { uint64_t ret; DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " - "attr 0x%x\n", dip, ra, io_attributes); + "attr 0x%x\n", dip, ra, attr); - if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, - io_attributes, io_addr_p)) != H_EOK) { + if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, attr, + io_addr_p)) != H_EOK) { DBG(DBG_LIB_DMA, dip, "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); return (DDI_FAILURE); @@ -569,7 +568,7 @@ px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, /*ARGSUSED*/ int px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, - off_t off, size_t len, uint_t cache_flags) + off_t off, size_t len, uint_t cache_flags) { ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; diff --git a/usr/src/uts/sun4u/io/px/px_lib4u.h b/usr/src/uts/sun4u/io/px/px_lib4u.h index b9e56dd7e3..908d29e5a0 100644 --- a/usr/src/uts/sun4u/io/px/px_lib4u.h +++ b/usr/src/uts/sun4u/io/px/px_lib4u.h @@ -2,9 +2,8 @@ * CDDL HEADER START * * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. @@ -20,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * Copyright 2006 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -270,14 +269,14 @@ extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, sysino_t sysino, cpuid_t cpuid); extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, - pages_t pages, io_attributes_t io_attributes, - void *addr, size_t pfn_index, int flag); + pages_t pages, io_attributes_t attr, void *addr, size_t pfn_index, + int flags); extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, pages_t pages); extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, - tsbid_t tsbid, io_attributes_t *attributes_p, r_addr_t *r_addr_p); + tsbid_t tsbid, io_attributes_t *attr_p, r_addr_t *r_addr_p); extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, - io_attributes_t io_attributes, io_addr_t *io_addr_p); + io_attributes_t attr, io_addr_t *io_addr_p); /* * MSIQ Functions: diff --git a/usr/src/uts/sun4v/Makefile.files b/usr/src/uts/sun4v/Makefile.files index 0a5931a024..8b6b89aca1 100644 --- a/usr/src/uts/sun4v/Makefile.files +++ b/usr/src/uts/sun4v/Makefile.files @@ -93,7 +93,7 @@ SPECIAL_OBJS += intrq.o # driver modules # ROOTNEX_OBJS += mach_rootnex.o -PX_OBJS += px_asm_4v.o px_err.o px_lib4v.o px_tools_4v.o +PX_OBJS += px_lib4v.o px_err.o px_tools_4v.o px_hcall.o FPC_OBJS += fpc-impl-4v.o fpc-asm-4v.o TRAPSTAT_OBJS += trapstat.o diff --git a/usr/src/uts/sun4v/io/px/px_asm_4v.h b/usr/src/uts/sun4v/io/px/px_asm_4v.h deleted file mode 100644 index 12f4516da2..0000000000 --- a/usr/src/uts/sun4v/io/px/px_asm_4v.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * CDDL HEADER START - * - * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. - * - * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE - * or http://www.opensolaris.org/os/licensing. - * See the License for the specific language governing permissions - * and limitations under the License. - * - * When distributing Covered Code, include this CDDL HEADER in each - * file and include the License file at usr/src/OPENSOLARIS.LICENSE. - * If applicable, add the following below this CDDL HEADER, with the - * fields enclosed by brackets "[]" replaced with your own identifying - * information: Portions Copyright [yyyy] [name of copyright owner] - * - * CDDL HEADER END - */ -/* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. - */ - -#ifndef _SYS_PX_ASM_4V_H -#define _SYS_PX_ASM_4V_H - -#pragma ident "%Z%%M% %I% %E% SMI" - -#ifdef __cplusplus -extern "C" { -#endif - -extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYS_PX_ASM_4V_H */ diff --git a/usr/src/uts/sun4v/io/px/px_asm_4v.s b/usr/src/uts/sun4v/io/px/px_asm_4v.s deleted file mode 100644 index 9f710fa149..0000000000 --- a/usr/src/uts/sun4v/io/px/px_asm_4v.s +++ /dev/null @@ -1,82 +0,0 @@ -/* - * CDDL HEADER START - * - * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. - * - * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE - * or http://www.opensolaris.org/os/licensing. - * See the License for the specific language governing permissions - * and limitations under the License. - * - * When distributing Covered Code, include this CDDL HEADER in each - * file and include the License file at usr/src/OPENSOLARIS.LICENSE. - * If applicable, add the following below this CDDL HEADER, with the - * fields enclosed by brackets "[]" replaced with your own identifying - * information: Portions Copyright [yyyy] [name of copyright owner] - * - * CDDL HEADER END - */ -/* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. - */ - -#pragma ident "%Z%%M% %I% %E% SMI" - -/* - * Assembly language support for sun4v px driver - */ - -#include <sys/asm_linkage.h> -#include <sys/machthread.h> -#include <sys/privregs.h> - -/*LINTLIBRARY*/ - -#if defined(lint) - -/* - * First arg to both of these functions is a dummy, to accomodate how - * hv_hpriv() works. - */ - -/*ARGSUSED*/ -int -px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr) -{ return (0); } - -#else /* lint */ - -#define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3 - -! px_phys_acc_4v: Do physical address read. -! -! After SHIFT_REGS: -! %o0 is "from" address -! %o1 is "to" address -! -! Assumes 8 byte data and that alignment is correct. -! -! Always returns success (0) in %o0 - - ! px_phys_acc_4v must not be split across pages. - ! - ! ATTN: Be sure that the alignment value is larger than the size of - ! the px_phys_acc_4v function. - ! - .align 0x40 - - ENTRY(px_phys_acc_4v) - - SHIFT_REGS - ldx [%o0], %g1 - stx %g1, [%o1] - membar #Sync ! Make sure the loads take - mov %g0, %o0 - done - SET_SIZE(px_phys_acc_4v) - -#endif diff --git a/usr/src/uts/sun4v/io/px/px_hcall.s b/usr/src/uts/sun4v/io/px/px_hcall.s new file mode 100644 index 0000000000..e336fbe725 --- /dev/null +++ b/usr/src/uts/sun4v/io/px/px_hcall.s @@ -0,0 +1,723 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE + * or http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at usr/src/OPENSOLARIS.LICENSE. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ +/* + * Copyright 2006 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms. + */ + +#pragma ident "%Z%%M% %I% %E% SMI" + +/* + * Hypervisor calls called by px nexus driver. +*/ + +#include <sys/asm_linkage.h> +#include <sys/hypervisor_api.h> +#include <px_ioapi.h> + +#if defined(lint) || defined(__lint) + +/*ARGSUSED*/ +uint64_t +hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, + pci_config_size_t size, pci_cfg_data_t *data_p) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, + pci_config_size_t size, pci_cfg_data_t data) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, + io_attributes_t attr, io_page_list_t *io_page_list_p, + pages_t *pages_mapped) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, + pages_t *pages_demapped) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p, + r_addr_t *r_addr_p) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr, + io_addr_t *io_addr_p) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, + uint64_t *data_p) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, + r_addr_t ra2, uint32_t *rdbk_status) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, + int io_sync_direction, size_t *bytes_synched) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, + uint_t msiq_rec_cnt) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, + uint_t *msiq_rec_cnt_p) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, + pci_msiq_valid_state_t *msiq_valid_state) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, + pci_msiq_valid_state_t msiq_valid_state) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, + pci_msiq_state_t *msiq_state) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, + pci_msiq_state_t msiq_state) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, + msiqhead_t *msiq_head) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, + msiqhead_t msiq_head) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, + msiqtail_t *msiq_tail) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, + msiqid_t *msiq_id) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, + msiqid_t msiq_id, msi_type_t msitype) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, + pci_msi_valid_state_t *msi_valid_state) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, + pci_msi_valid_state_t msi_valid_state) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, + pci_msi_state_t *msi_state) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, + pci_msi_state_t msi_state) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, + msiqid_t *msiq_id) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, + msiqid_t msiq_id) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, + pcie_msg_valid_state_t *msg_valid_state) +{ return (0); } + +/*ARGSUSED*/ +uint64_t +hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, + pcie_msg_valid_state_t msg_valid_state) +{ return (0); } + +/* + * First arg to both of these functions is a dummy, to accomodate how + * hv_hpriv() works. + */ +/*ARGSUSED*/ +int +px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr) +{ return (0); } + +#else /* lint || __lint */ + + /* + * arg0 - devhandle + * arg1 - pci_device + * arg2 - pci_config_offset + * arg3 - pci_config_size + * + * ret0 - status + * ret1 - error_flag + * ret2 - pci_cfg_data + */ + ENTRY(hvio_config_get) + mov HVIO_CONFIG_GET, %o5 + ta FAST_TRAP + brnz %o0, 1f + movrnz %o1, -1, %o2 + brz,a %o1, 1f + stuw %o2, [%o4] +1: retl + nop + SET_SIZE(hvio_config_get) + + /* + * arg0 - devhandle + * arg1 - pci_device + * arg2 - pci_config_offset + * arg3 - pci_config_size + * arg4 - pci_cfg_data + * + * ret0 - status + * ret1 - error_flag + */ + ENTRY(hvio_config_put) + mov HVIO_CONFIG_PUT, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_config_put) + + /* + * arg0 - devhandle + * arg1 - tsbid + * arg2 - pages + * arg3 - io_attributes + * arg4 - io_page_list_p + * + * ret1 - pages_mapped + */ + ENTRY(hvio_iommu_map) + save %sp, -SA(MINFRAME64), %sp + mov %i0, %o0 + mov %i1, %o1 + mov %i2, %o2 + mov %i3, %o3 + mov %i4, %o4 + mov HVIO_IOMMU_MAP, %o5 + ta FAST_TRAP + brnz %o0, 1f + mov %o0, %i0 + stuw %o1, [%i5] +1: + ret + restore + SET_SIZE(hvio_iommu_map) + + /* + * arg0 - devhandle + * arg1 - tsbid + * arg2 - pages + * + * ret1 - pages_demapped + */ + ENTRY(hvio_iommu_demap) + mov HVIO_IOMMU_DEMAP, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stuw %o1, [%o3] +1: retl + nop + SET_SIZE(hvio_iommu_demap) + + /* + * arg0 - devhandle + * arg1 - tsbid + * + * + * ret0 - status + * ret1 - io_attributes + * ret2 - r_addr + */ + ENTRY(hvio_iommu_getmap) + mov %o2, %o4 + mov HVIO_IOMMU_GETMAP, %o5 + ta FAST_TRAP + brnz %o0, 1f + nop + stx %o2, [%o3] + st %o1, [%o4] +1: + retl + nop + SET_SIZE(hvio_iommu_getmap) + + /* + * arg0 - devhandle + * arg1 - r_addr + * arg2 - io_attributes + * + * + * ret0 - status + * ret1 - io_addr + */ + ENTRY(hvio_iommu_getbypass) + mov HVIO_IOMMU_GETBYPASS, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stx %o1, [%o3] +1: retl + nop + SET_SIZE(hvio_iommu_getbypass) + + /* + * arg0 - devhandle + * arg1 - r_addr + * arg2 - size + * + * ret1 - error_flag + * ret2 - data + */ + ENTRY(hvio_peek) + mov HVIO_PEEK, %o5 + ta FAST_TRAP + brnz %o0, 1f + nop + stx %o2, [%o4] + st %o1, [%o3] +1: + retl + nop + SET_SIZE(hvio_peek) + + /* + * arg0 - devhandle + * arg1 - r_addr + * arg2 - sizes + * arg3 - data + * arg4 - r_addr2 + * + * ret1 - error_flag + */ + ENTRY(hvio_poke) + save %sp, -SA(MINFRAME64), %sp + mov %i0, %o0 + mov %i1, %o1 + mov %i2, %o2 + mov %i3, %o3 + mov %i4, %o4 + mov HVIO_POKE, %o5 + ta FAST_TRAP + brnz %o0, 1f + mov %o0, %i0 + stuw %o1, [%i5] +1: + ret + restore + SET_SIZE(hvio_poke) + + /* + * arg0 - devhandle + * arg1 - r_addr + * arg2 - num_bytes + * arg3 - io_sync_direction + * + * ret0 - status + * ret1 - bytes_synched + */ + ENTRY(hvio_dma_sync) + mov HVIO_DMA_SYNC, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stx %o1, [%o4] +1: retl + nop + SET_SIZE(hvio_dma_sync) + + /* + * arg0 - devhandle + * arg1 - msiq_id + * arg2 - r_addr + * arg3 - nentries + * + * ret0 - status + */ + ENTRY(hvio_msiq_conf) + mov HVIO_MSIQ_CONF, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_msiq_conf) + + /* + * arg0 - devhandle + * arg1 - msiq_id + * + * ret0 - status + * ret1 - r_addr + * ret1 - nentries + */ + ENTRY(hvio_msiq_info) + mov %o2, %o4 + mov HVIO_MSIQ_INFO, %o5 + ta FAST_TRAP + brnz 1f + nop + stx %o1, [%o4] + stuw %o2, [%o3] +1: retl + nop + SET_SIZE(hvio_msiq_info) + + /* + * arg0 - devhandle + * arg1 - msiq_id + * + * ret0 - status + * ret1 - msiq_valid_state + */ + ENTRY(hvio_msiq_getvalid) + mov HVIO_MSIQ_GETVALID, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stuw %o1, [%o2] +1: retl + nop + SET_SIZE(hvio_msiq_getvalid) + + /* + * arg0 - devhandle + * arg1 - msiq_id + * arg2 - msiq_valid_state + * + * ret0 - status + */ + ENTRY(hvio_msiq_setvalid) + mov HVIO_MSIQ_SETVALID, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_msiq_setvalid) + + /* + * arg0 - devhandle + * arg1 - msiq_id + * + * ret0 - status + * ret1 - msiq_state + */ + ENTRY(hvio_msiq_getstate) + mov HVIO_MSIQ_GETSTATE, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stuw %o1, [%o2] +1: retl + nop + SET_SIZE(hvio_msiq_getstate) + + /* + * arg0 - devhandle + * arg1 - msiq_id + * arg2 - msiq_state + * + * ret0 - status + */ + ENTRY(hvio_msiq_setstate) + mov HVIO_MSIQ_SETSTATE, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_msiq_setstate) + + /* + * arg0 - devhandle + * arg1 - msiq_id + * + * ret0 - status + * ret1 - msiq_head + */ + ENTRY(hvio_msiq_gethead) + mov HVIO_MSIQ_GETHEAD, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stx %o1, [%o2] +1: retl + nop + SET_SIZE(hvio_msiq_gethead) + + /* + * arg0 - devhandle + * arg1 - msiq_id + * arg2 - msiq_head + * + * ret0 - status + */ + ENTRY(hvio_msiq_sethead) + mov HVIO_MSIQ_SETHEAD, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_msiq_sethead) + + /* + * arg0 - devhandle + * arg1 - msiq_id + * + * ret0 - status + * ret1 - msiq_tail + */ + ENTRY(hvio_msiq_gettail) + mov HVIO_MSIQ_GETTAIL, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stx %o1, [%o2] +1: retl + nop + SET_SIZE(hvio_msiq_gettail) + + /* + * arg0 - devhandle + * arg1 - msi_num + * + * ret0 - status + * ret1 - msiq_id + */ + ENTRY(hvio_msi_getmsiq) + mov HVIO_MSI_GETMSIQ, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stuw %o1, [%o2] +1: retl + nop + SET_SIZE(hvio_msi_getmsiq) + + /* + * arg0 - devhandle + * arg1 - msi_num + * arg2 - msiq_id + * arg2 - msitype + * + * ret0 - status + */ + ENTRY(hvio_msi_setmsiq) + mov HVIO_MSI_SETMSIQ, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_msi_setmsiq) + + /* + * arg0 - devhandle + * arg1 - msi_num + * + * ret0 - status + * ret1 - msi_valid_state + */ + ENTRY(hvio_msi_getvalid) + mov HVIO_MSI_GETVALID, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stuw %o1, [%o2] +1: retl + nop + SET_SIZE(hvio_msi_getvalid) + + /* + * arg0 - devhandle + * arg1 - msi_num + * arg2 - msi_valid_state + * + * ret0 - status + */ + ENTRY(hvio_msi_setvalid) + mov HVIO_MSI_SETVALID, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_msi_setvalid) + + /* + * arg0 - devhandle + * arg1 - msi_num + * + * ret0 - status + * ret1 - msi_state + */ + ENTRY(hvio_msi_getstate) + mov HVIO_MSI_GETSTATE, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stuw %o1, [%o2] +1: retl + nop + SET_SIZE(hvio_msi_getstate) + + /* + * arg0 - devhandle + * arg1 - msi_num + * arg2 - msi_state + * + * ret0 - status + */ + ENTRY(hvio_msi_setstate) + mov HVIO_MSI_SETSTATE, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_msi_setstate) + + /* + * arg0 - devhandle + * arg1 - msg_type + * + * ret0 - status + * ret1 - msiq_id + */ + ENTRY(hvio_msg_getmsiq) + mov HVIO_MSG_GETMSIQ, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stuw %o1, [%o2] +1: retl + nop + SET_SIZE(hvio_msg_getmsiq) + + /* + * arg0 - devhandle + * arg1 - msg_type + * arg2 - msiq_id + * + * ret0 - status + */ + ENTRY(hvio_msg_setmsiq) + mov HVIO_MSG_SETMSIQ, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_msg_setmsiq) + + /* + * arg0 - devhandle + * arg1 - msg_type + * + * ret0 - status + * ret1 - msg_valid_state + */ + ENTRY(hvio_msg_getvalid) + mov HVIO_MSG_GETVALID, %o5 + ta FAST_TRAP + brz,a %o0, 1f + stuw %o1, [%o2] +1: retl + nop + SET_SIZE(hvio_msg_getvalid) + + /* + * arg0 - devhandle + * arg1 - msg_type + * arg2 - msg_valid_state + * + * ret0 - status + */ + ENTRY(hvio_msg_setvalid) + mov HVIO_MSG_SETVALID, %o5 + ta FAST_TRAP + retl + nop + SET_SIZE(hvio_msg_setvalid) + +#define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3 + +! px_phys_acc_4v: Do physical address read. +! +! After SHIFT_REGS: +! %o0 is "from" address +! %o1 is "to" address +! +! Assumes 8 byte data and that alignment is correct. +! +! Always returns success (0) in %o0 + + ! px_phys_acc_4v must not be split across pages. + ! + ! ATTN: Be sure that the alignment value is larger than the size of + ! the px_phys_acc_4v function. + ! + .align 0x40 + + ENTRY(px_phys_acc_4v) + + SHIFT_REGS + ldx [%o0], %g1 + stx %g1, [%o1] + membar #Sync ! Make sure the loads take + mov %g0, %o0 + done + SET_SIZE(px_phys_acc_4v) + +#endif /* lint || __lint */ diff --git a/usr/src/uts/sun4v/io/px/px_lib4v.c b/usr/src/uts/sun4v/io/px/px_lib4v.c index 0407d00580..1798f0562b 100644 --- a/usr/src/uts/sun4v/io/px/px_lib4v.c +++ b/usr/src/uts/sun4v/io/px/px_lib4v.c @@ -37,6 +37,7 @@ #include <sys/ivintr.h> #include <sys/errno.h> #include <sys/hypervisor_api.h> +#include <sys/hsvc.h> #include <px_obj.h> #include <sys/machsystm.h> #include <sys/hotplug/pci/pcihp.h> @@ -46,6 +47,17 @@ /* mask for the ranges property in calculating the real PFN range */ uint_t px_ranges_phi_mask = ((1 << 28) -1); +/* + * Hypervisor VPCI services information for the px nexus driver. + */ +static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ +static uint_t px_vpci_users = 0; /* VPCI API users */ + +static hsvc_info_t px_hsvc = { + HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, + PX_VPCI_MINOR_VER, "PX" +}; + int px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) { @@ -69,7 +81,6 @@ px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) * defined by the SUN4V Bus Binding to Open Firmware. */ *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); - ddi_prop_free(rp); /* @@ -82,6 +93,24 @@ px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); + /* + * Negotiate the API version for VPCI hypervisor services. + */ + if (px_vpci_users++) + return (DDI_SUCCESS); + + if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { + cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " + "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", + px_hsvc.hsvc_modname, px_hsvc.hsvc_group, + px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); + + return (DDI_FAILURE); + } + + DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " + "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); + return (DDI_SUCCESS); } @@ -95,6 +124,9 @@ px_lib_dev_fini(dev_info_t *dip) PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, PCI_BUS_CONF_MAP_PROP); + if (--px_vpci_users == 0) + (void) hsvc_unregister(&px_hsvc); + return (DDI_SUCCESS); } @@ -269,8 +301,7 @@ px_lib_intr_reset(dev_info_t *dip) /*ARGSUSED*/ int px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, - io_attributes_t io_attr, void *addr, size_t pfn_index, - int flag) + io_attributes_t attr, void *addr, size_t pfn_index, int flags) { tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); @@ -279,8 +310,8 @@ px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, int i, err = DDI_SUCCESS; DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " - "pages 0x%x atrr 0x%x addr 0x%p pfn_index 0x%llx, flag 0x%x\n", - dip, tsbid, pages, io_attr, addr, pfn_index, flag); + "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", + dip, tsbid, pages, attr, addr, pfn_index, flags); if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), KM_NOSLEEP)) == NULL) { @@ -289,7 +320,7 @@ px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, } for (i = 0; i < pages; i++) - pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flag, i)); + pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); while ((ttes_mapped = pfn_p - pfns) < pages) { uintptr_t ra = va_to_pa(pfn_p); @@ -305,7 +336,7 @@ px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, ttes_mapped = 0; if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), - ttes2map, io_attr, (io_page_list_t *)(ra | + ttes2map, attr, (io_page_list_t *)(ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), &ttes_mapped)) != H_EOK) { DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " @@ -319,7 +350,7 @@ px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " "ra 0x%p ttes_mapped 0x%x\n", tsb_num, - tsb_index + (pfn_p - pfns), ttes2map, io_attr, + tsb_index + (pfn_p - pfns), ttes2map, attr, ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), ttes_mapped); } @@ -366,8 +397,8 @@ px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) /*ARGSUSED*/ int -px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, - io_attributes_t *attributes_p, r_addr_t *r_addr_p) +px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, + r_addr_t *r_addr_p) { uint64_t ret; @@ -375,7 +406,7 @@ px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, dip, tsbid); if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, - attributes_p, r_addr_p)) != H_EOK) { + attr_p, r_addr_p)) != H_EOK) { DBG(DBG_LIB_DMA, dip, "hvio_iommu_getmap failed, ret 0x%lx\n", ret); @@ -383,7 +414,7 @@ px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, } DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", - *attributes_p, *r_addr_p); + *attr_p, *r_addr_p); return (DDI_SUCCESS); } @@ -396,10 +427,10 @@ px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, */ /*ARGSUSED*/ int -px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, uint64_t *hi_p) +px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attr_p, uint64_t *lo_p, uint64_t *hi_p) { - if ((attrp->dma_attr_addr_lo != 0ull) || - (attrp->dma_attr_addr_hi != UINT64_MAX)) { + if ((attr_p->dma_attr_addr_lo != 0ull) || + (attr_p->dma_attr_addr_hi != UINT64_MAX)) { return (DDI_DMA_BADATTR); } @@ -413,16 +444,16 @@ px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, uint64_t *hi_p) /*ARGSUSED*/ int -px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, - io_attributes_t io_attributes, io_addr_t *io_addr_p) +px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, + io_addr_t *io_addr_p) { uint64_t ret; DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " - "attr 0x%x\n", dip, ra, io_attributes); + "attr 0x%x\n", dip, ra, attr); if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, - io_attributes, io_addr_p)) != H_EOK) { + attr, io_addr_p)) != H_EOK) { DBG(DBG_LIB_DMA, dip, "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); diff --git a/usr/src/uts/sun4v/io/px/px_lib4v.h b/usr/src/uts/sun4v/io/px/px_lib4v.h index 5658edd286..4930f6a1d7 100644 --- a/usr/src/uts/sun4v/io/px/px_lib4v.h +++ b/usr/src/uts/sun4v/io/px/px_lib4v.h @@ -2,9 +2,8 @@ * CDDL HEADER START * * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. @@ -20,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * Copyright 2006 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -48,25 +47,36 @@ extern "C" { /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ #define PX_RA_BDF_SHIFT 8 -#define PX_ADDR2PFN(addr, index, flag, i) \ - ((flag == MMU_MAP_MP) ? \ +#define PX_ADDR2PFN(addr, index, flags, i) \ + ((flags & MMU_MAP_PFN) ? \ PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \ hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i)))) +/* + * VPCI API versioning. + * + * Currently PX nexus driver supports VPCI API version 1.0. + */ +#define PX_VPCI_MAJOR_VER_1 0x1ull +#define PX_VPCI_MAJOR_VER PX_VPCI_MAJOR_VER_1 + +#define PX_VPCI_MINOR_VER_0 0x0ull +#define PX_VPCI_MINOR_VER PX_VPCI_MINOR_VER_0 + extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p); extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data); extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, - pages_t pages, io_attributes_t io_attributes, - io_page_list_t *io_page_list_p, pages_t *pages_mapped); + pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p, + pages_t *pages_mapped); extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, pages_t *pages_demapped); extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, - io_attributes_t *attributes_p, r_addr_t *r_addr_p); + io_attributes_t *attr_p, r_addr_t *r_addr_p); extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, - io_attributes_t io_attributes, io_addr_t *io_addr_p); + io_attributes_t attr, io_addr_t *io_addr_p); extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, io_sync_direction_t io_sync_direction, size_t *bytes_synched); @@ -142,6 +152,7 @@ extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, extern uint64_t hv_ra2pa(uint64_t ra); extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3); +extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr); #ifdef __cplusplus } diff --git a/usr/src/uts/sun4v/io/px/px_tools_4v.c b/usr/src/uts/sun4v/io/px/px_tools_4v.c index b9f87a17b9..00470ad90c 100644 --- a/usr/src/uts/sun4v/io/px/px_tools_4v.c +++ b/usr/src/uts/sun4v/io/px/px_tools_4v.c @@ -2,9 +2,8 @@ * CDDL HEADER START * * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. @@ -20,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * Copyright 2006 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -34,7 +33,6 @@ #include <px_obj.h> #include <sys/pci_tools.h> #include <px_tools_var.h> -#include "px_asm_4v.h" #include "px_lib4v.h" #include <px_tools_ext.h> diff --git a/usr/src/uts/sun4v/ml/hcall.s b/usr/src/uts/sun4v/ml/hcall.s index b19d439338..4ad798d4bf 100644 --- a/usr/src/uts/sun4v/ml/hcall.s +++ b/usr/src/uts/sun4v/ml/hcall.s @@ -2,9 +2,8 @@ * CDDL HEADER START * * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. @@ -20,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * Copyright 2006 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -34,7 +33,6 @@ #include <sys/machasi.h> #include <sys/machparam.h> #include <sys/hypervisor_api.h> -#include <io/px/px_ioapi.h> #if defined(lint) || defined(__lint) @@ -92,18 +90,6 @@ hv_cpu_qconf(int queue, uint64_t paddr, int size) /*ARGSUSED*/ uint64_t -hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, - pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, - pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data) -{ return (0); } - -/*ARGSUSED*/ -uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) { return (0); } @@ -137,163 +123,6 @@ uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) { return (0); } -/*ARGSUSED*/ -uint64_t -hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, - pages_t pages, io_attributes_t io_attributes, - io_page_list_t *io_page_list_p, pages_t *pages_mapped) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, - pages_t pages, pages_t *pages_demapped) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, - io_attributes_t *attributes_p, r_addr_t *r_addr_p) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, - io_attributes_t io_attributes, io_addr_t *io_addr_p) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, - uint64_t *data_p) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, - r_addr_t ra2, uint32_t *rdbk_status) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, - int io_sync_direction, size_t *bytes_synched) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, - uint_t msiq_rec_cnt) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, - uint_t *msiq_rec_cnt_p) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, - pci_msiq_valid_state_t *msiq_valid_state) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, - pci_msiq_valid_state_t msiq_valid_state) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, - pci_msiq_state_t *msiq_state) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, - pci_msiq_state_t msiq_state) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, - msiqhead_t *msiq_head) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, - msiqhead_t msiq_head) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, - msiqtail_t *msiq_tail) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, - msiqid_t *msiq_id) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, - msiqid_t msiq_id, msi_type_t msitype) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, - pci_msi_valid_state_t *msi_valid_state) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, - pci_msi_valid_state_t msi_valid_state) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, - pci_msi_state_t *msi_state) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, - pci_msi_state_t msi_state) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, - msiqid_t *msiq_id) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, - msiqid_t msiq_id) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, - pcie_msg_valid_state_t *msg_valid_state) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, - pcie_msg_valid_state_t msg_valid_state) -{ return (0); } - uint64_t hv_cpu_yield(void) { return (0); } @@ -519,44 +348,6 @@ hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) /* * arg0 - devhandle - * arg1 - pci_device - * arg2 - pci_config_offset - * arg3 - pci_config_size - * - * ret0 - status - * ret1 - error_flag - * ret2 - pci_cfg_data - */ - ENTRY(hvio_config_get) - mov HVIO_CONFIG_GET, %o5 - ta FAST_TRAP - brnz %o0, 1f - movrnz %o1, -1, %o2 - brz,a %o1, 1f - stuw %o2, [%o4] -1: retl - nop - SET_SIZE(hvio_config_get) - - /* - * arg0 - devhandle - * arg1 - pci_device - * arg2 - pci_config_offset - * arg3 - pci_config_size - * arg4 - pci_cfg_data - * - * ret0 - status - * ret1 - error_flag - */ - ENTRY(hvio_config_put) - mov HVIO_CONFIG_PUT, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_config_put) - - /* - * arg0 - devhandle * arg1 - devino * * ret0 - status @@ -659,444 +450,6 @@ hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) SET_SIZE(hvio_intr_settarget) /* - * arg0 - devhandle - * arg1 - tsbid - * arg2 - pages - * arg3 - io_attributes - * arg4 - io_page_list_p - * - * ret1 - pages_mapped - */ - ENTRY(hvio_iommu_map) - save %sp, -SA(MINFRAME64), %sp - mov %i0, %o0 - mov %i1, %o1 - mov %i2, %o2 - mov %i3, %o3 - mov %i4, %o4 - mov HVIO_IOMMU_MAP, %o5 - ta FAST_TRAP - brnz %o0, 1f - mov %o0, %i0 - stuw %o1, [%i5] -1: - ret - restore - SET_SIZE(hvio_iommu_map) - - /* - * arg0 - devhandle - * arg1 - tsbid - * arg2 - pages - * - * ret1 - pages_demapped - */ - ENTRY(hvio_iommu_demap) - mov HVIO_IOMMU_DEMAP, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stuw %o1, [%o3] -1: retl - nop - SET_SIZE(hvio_iommu_demap) - - /* - * arg0 - devhandle - * arg1 - tsbid - * - * - * ret0 - status - * ret1 - io_attributes - * ret2 - r_addr - */ - ENTRY(hvio_iommu_getmap) - mov %o2, %o4 - mov HVIO_IOMMU_GETMAP, %o5 - ta FAST_TRAP - brnz %o0, 1f - nop - stx %o2, [%o3] - st %o1, [%o4] -1: - retl - nop - SET_SIZE(hvio_iommu_getmap) - - /* - * arg0 - devhandle - * arg1 - r_addr - * arg2 - io_attributes - * - * - * ret0 - status - * ret1 - io_addr - */ - ENTRY(hvio_iommu_getbypass) - mov HVIO_IOMMU_GETBYPASS, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stx %o1, [%o3] -1: retl - nop - SET_SIZE(hvio_iommu_getbypass) - - /* - * arg0 - devhandle - * arg1 - r_addr - * arg2 - size - * - * ret1 - error_flag - * ret2 - data - */ - ENTRY(hvio_peek) - mov HVIO_PEEK, %o5 - ta FAST_TRAP - brnz %o0, 1f - nop - stx %o2, [%o4] - st %o1, [%o3] -1: - retl - nop - SET_SIZE(hvio_peek) - - /* - * arg0 - devhandle - * arg1 - r_addr - * arg2 - sizes - * arg3 - data - * arg4 - r_addr2 - * - * ret1 - error_flag - */ - ENTRY(hvio_poke) - save %sp, -SA(MINFRAME64), %sp - mov %i0, %o0 - mov %i1, %o1 - mov %i2, %o2 - mov %i3, %o3 - mov %i4, %o4 - mov HVIO_POKE, %o5 - ta FAST_TRAP - brnz %o0, 1f - mov %o0, %i0 - stuw %o1, [%i5] -1: - ret - restore - SET_SIZE(hvio_poke) - - /* - * arg0 - devhandle - * arg1 - r_addr - * arg2 - num_bytes - * arg3 - io_sync_direction - * - * ret0 - status - * ret1 - bytes_synched - */ - ENTRY(hvio_dma_sync) - mov HVIO_DMA_SYNC, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stx %o1, [%o4] -1: retl - nop - SET_SIZE(hvio_dma_sync) - - /* - * arg0 - devhandle - * arg1 - msiq_id - * arg2 - r_addr - * arg3 - nentries - * - * ret0 - status - */ - ENTRY(hvio_msiq_conf) - mov HVIO_MSIQ_CONF, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_msiq_conf) - - /* - * arg0 - devhandle - * arg1 - msiq_id - * - * ret0 - status - * ret1 - r_addr - * ret1 - nentries - */ - ENTRY(hvio_msiq_info) - mov %o2, %o4 - mov HVIO_MSIQ_INFO, %o5 - ta FAST_TRAP - brnz 1f - nop - stx %o1, [%o4] - stuw %o2, [%o3] -1: retl - nop - SET_SIZE(hvio_msiq_info) - - /* - * arg0 - devhandle - * arg1 - msiq_id - * - * ret0 - status - * ret1 - msiq_valid_state - */ - ENTRY(hvio_msiq_getvalid) - mov HVIO_MSIQ_GETVALID, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stuw %o1, [%o2] -1: retl - nop - SET_SIZE(hvio_msiq_getvalid) - - /* - * arg0 - devhandle - * arg1 - msiq_id - * arg2 - msiq_valid_state - * - * ret0 - status - */ - ENTRY(hvio_msiq_setvalid) - mov HVIO_MSIQ_SETVALID, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_msiq_setvalid) - - /* - * arg0 - devhandle - * arg1 - msiq_id - * - * ret0 - status - * ret1 - msiq_state - */ - ENTRY(hvio_msiq_getstate) - mov HVIO_MSIQ_GETSTATE, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stuw %o1, [%o2] -1: retl - nop - SET_SIZE(hvio_msiq_getstate) - - /* - * arg0 - devhandle - * arg1 - msiq_id - * arg2 - msiq_state - * - * ret0 - status - */ - ENTRY(hvio_msiq_setstate) - mov HVIO_MSIQ_SETSTATE, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_msiq_setstate) - - /* - * arg0 - devhandle - * arg1 - msiq_id - * - * ret0 - status - * ret1 - msiq_head - */ - ENTRY(hvio_msiq_gethead) - mov HVIO_MSIQ_GETHEAD, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stx %o1, [%o2] -1: retl - nop - SET_SIZE(hvio_msiq_gethead) - - /* - * arg0 - devhandle - * arg1 - msiq_id - * arg2 - msiq_head - * - * ret0 - status - */ - ENTRY(hvio_msiq_sethead) - mov HVIO_MSIQ_SETHEAD, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_msiq_sethead) - - /* - * arg0 - devhandle - * arg1 - msiq_id - * - * ret0 - status - * ret1 - msiq_tail - */ - ENTRY(hvio_msiq_gettail) - mov HVIO_MSIQ_GETTAIL, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stx %o1, [%o2] -1: retl - nop - SET_SIZE(hvio_msiq_gettail) - - /* - * arg0 - devhandle - * arg1 - msi_num - * - * ret0 - status - * ret1 - msiq_id - */ - ENTRY(hvio_msi_getmsiq) - mov HVIO_MSI_GETMSIQ, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stuw %o1, [%o2] -1: retl - nop - SET_SIZE(hvio_msi_getmsiq) - - /* - * arg0 - devhandle - * arg1 - msi_num - * arg2 - msiq_id - * arg2 - msitype - * - * ret0 - status - */ - ENTRY(hvio_msi_setmsiq) - mov HVIO_MSI_SETMSIQ, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_msi_setmsiq) - - /* - * arg0 - devhandle - * arg1 - msi_num - * - * ret0 - status - * ret1 - msi_valid_state - */ - ENTRY(hvio_msi_getvalid) - mov HVIO_MSI_GETVALID, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stuw %o1, [%o2] -1: retl - nop - SET_SIZE(hvio_msi_getvalid) - - /* - * arg0 - devhandle - * arg1 - msi_num - * arg2 - msi_valid_state - * - * ret0 - status - */ - ENTRY(hvio_msi_setvalid) - mov HVIO_MSI_SETVALID, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_msi_setvalid) - - /* - * arg0 - devhandle - * arg1 - msi_num - * - * ret0 - status - * ret1 - msi_state - */ - ENTRY(hvio_msi_getstate) - mov HVIO_MSI_GETSTATE, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stuw %o1, [%o2] -1: retl - nop - SET_SIZE(hvio_msi_getstate) - - /* - * arg0 - devhandle - * arg1 - msi_num - * arg2 - msi_state - * - * ret0 - status - */ - ENTRY(hvio_msi_setstate) - mov HVIO_MSI_SETSTATE, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_msi_setstate) - - /* - * arg0 - devhandle - * arg1 - msg_type - * - * ret0 - status - * ret1 - msiq_id - */ - ENTRY(hvio_msg_getmsiq) - mov HVIO_MSG_GETMSIQ, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stuw %o1, [%o2] -1: retl - nop - SET_SIZE(hvio_msg_getmsiq) - - /* - * arg0 - devhandle - * arg1 - msg_type - * arg2 - msiq_id - * - * ret0 - status - */ - ENTRY(hvio_msg_setmsiq) - mov HVIO_MSG_SETMSIQ, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_msg_setmsiq) - - /* - * arg0 - devhandle - * arg1 - msg_type - * - * ret0 - status - * ret1 - msg_valid_state - */ - ENTRY(hvio_msg_getvalid) - mov HVIO_MSG_GETVALID, %o5 - ta FAST_TRAP - brz,a %o0, 1f - stuw %o1, [%o2] -1: retl - nop - SET_SIZE(hvio_msg_getvalid) - - /* - * arg0 - devhandle - * arg1 - msg_type - * arg2 - msg_valid_state - * - * ret0 - status - */ - ENTRY(hvio_msg_setvalid) - mov HVIO_MSG_SETVALID, %o5 - ta FAST_TRAP - retl - nop - SET_SIZE(hvio_msg_setvalid) - - /* * hv_cpu_yield(void) */ ENTRY(hv_cpu_yield) diff --git a/usr/src/uts/sun4v/os/hsvc.c b/usr/src/uts/sun4v/os/hsvc.c index c414bf3d81..4736ed42c8 100644 --- a/usr/src/uts/sun4v/os/hsvc.c +++ b/usr/src/uts/sun4v/os/hsvc.c @@ -654,7 +654,7 @@ hsvc_init(void) * group only for itself. * * Rest of the API groups are currently negotiated on behalf - * of the px, pcitool, glvc and Niagara crypto support. In + * of the pcitool, glvc and Niagara crypto support. In * future, when these drivers are modified to do the negotiation * themselves, corresponding entry should be removed from the * table below. @@ -662,7 +662,6 @@ hsvc_init(void) static hsvc_info_t hsvcinfo_unix[] = { {HSVC_REV_1, NULL, HSVC_GROUP_SUN4V, 1, 0, NULL}, {HSVC_REV_1, NULL, HSVC_GROUP_CORE, 1, 0, NULL}, - {HSVC_REV_1, NULL, HSVC_GROUP_VPCI, 1, 0, NULL}, {HSVC_REV_1, NULL, HSVC_GROUP_VSC, 1, 0, NULL}, {HSVC_REV_1, NULL, HSVC_GROUP_DIAG, 1, 0, NULL}, {HSVC_REV_1, NULL, HSVC_GROUP_NCS, 1, 0, NULL} |