1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
|
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include <hxge_impl.h>
#include <hpi_vmac.h>
#define HXGE_VMAC_RX_STAT_CLEAR 0x1ffULL
#define HXGE_VMAC_TX_STAT_CLEAR 0x7ULL
#define HXGE_VMAC_RX_MASK_OVERFLOW 0x1fe
#define HXGE_VMAC_RX_MASK_FRAME 0x1
hpi_status_t
hpi_tx_vmac_reset(hpi_handle_t handle)
{
vmac_rst_t reset;
HXGE_REG_RD64(handle, VMAC_RST, &(reset.value));
reset.bits.tx_reset = 1;
HXGE_REG_WR64(handle, VMAC_RST, reset.value);
return (HPI_SUCCESS);
}
hpi_status_t
hpi_rx_vmac_reset(hpi_handle_t handle)
{
vmac_rst_t reset;
HXGE_REG_RD64(handle, VMAC_RST, &(reset.value));
reset.bits.rx_reset = 1;
HXGE_REG_WR64(handle, VMAC_RST, reset.value);
return (HPI_SUCCESS);
}
hpi_status_t
hpi_vmac_tx_config(hpi_handle_t handle, config_op_t op, uint64_t config,
uint16_t max_frame_length)
{
vmac_tx_cfg_t cfg;
if (config == 0) {
HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
" hpi_vmac_tx_config Invalid Input: config <0x%x>",
config));
return (HPI_FAILURE);
}
HXGE_REG_RD64(handle, VMAC_TX_CFG, &cfg.value);
switch (op) {
case ENABLE:
if (config & CFG_VMAC_TX_EN)
cfg.bits.tx_en = 1;
if (config & CFG_VMAC_TX_CRC_INSERT)
cfg.bits.crc_insert = 1;
if (config & CFG_VMAC_TX_PAD)
cfg.bits.tx_pad = 1;
if (max_frame_length)
cfg.bits.tx_max_frame_length = max_frame_length;
break;
case DISABLE:
if (config & CFG_VMAC_TX_EN)
cfg.bits.tx_en = 0;
if (config & CFG_VMAC_TX_CRC_INSERT)
cfg.bits.crc_insert = 0;
if (config & CFG_VMAC_TX_PAD)
cfg.bits.tx_pad = 0;
break;
case INIT:
if (config & CFG_VMAC_TX_EN)
cfg.bits.tx_en = 1;
else
cfg.bits.tx_en = 0;
if (config & CFG_VMAC_TX_CRC_INSERT)
cfg.bits.crc_insert = 1;
else
cfg.bits.crc_insert = 0;
if (config & CFG_VMAC_TX_PAD)
cfg.bits.tx_pad = 1;
else
cfg.bits.tx_pad = 0;
if (max_frame_length)
cfg.bits.tx_max_frame_length = max_frame_length;
break;
default:
HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
" hpi_vmac_tx_config Invalid Input: op <0x%x>", op));
return (HPI_FAILURE);
}
HXGE_REG_WR64(handle, VMAC_TX_CFG, cfg.value);
return (HPI_SUCCESS);
}
hpi_status_t
hpi_vmac_rx_set_framesize(hpi_handle_t handle, uint16_t max_frame_length)
{
vmac_rx_cfg_t cfg;
uint16_t fsize;
HXGE_REG_RD64(handle, VMAC_RX_CFG, &cfg.value);
/*
* HW team not sure setting framesize to 0 is problematic
* or not.
*/
if (max_frame_length == 0)
fsize = 1;
else
fsize = max_frame_length;
cfg.bits.rx_max_frame_length = fsize;
HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value);
return (HPI_SUCCESS);
}
hpi_status_t
hpi_vmac_rx_config(hpi_handle_t handle, config_op_t op, uint64_t config,
uint16_t max_frame_length)
{
vmac_rx_cfg_t cfg;
if (config == 0) {
HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
" hpi_vmac_rx_config Invalid Input: config <0x%x>",
config));
return (HPI_FAILURE);
}
HXGE_REG_RD64(handle, VMAC_RX_CFG, &cfg.value);
switch (op) {
case ENABLE:
if (config & CFG_VMAC_RX_EN)
cfg.bits.rx_en = 1;
if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE)
cfg.bits.crc_check_disable = 1;
if (config & CFG_VMAC_RX_STRIP_CRC)
cfg.bits.strip_crc = 1;
if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR)
cfg.bits.pass_flow_ctrl_fr = 1;
if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP)
cfg.bits.promiscuous_group = 1;
if (config & CFG_VMAC_RX_PROMISCUOUS_MODE)
cfg.bits.promiscuous_mode = 1;
if (config & CFG_VMAC_RX_LOOP_BACK)
cfg.bits.loopback = 1;
break;
case DISABLE:
if (config & CFG_VMAC_RX_EN)
cfg.bits.rx_en = 0;
if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE)
cfg.bits.crc_check_disable = 0;
if (config & CFG_VMAC_RX_STRIP_CRC)
cfg.bits.strip_crc = 0;
if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR)
cfg.bits.pass_flow_ctrl_fr = 0;
if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP)
cfg.bits.promiscuous_group = 0;
if (config & CFG_VMAC_RX_PROMISCUOUS_MODE)
cfg.bits.promiscuous_mode = 0;
if (config & CFG_VMAC_RX_LOOP_BACK)
cfg.bits.loopback = 0;
break;
case INIT:
if (config & CFG_VMAC_RX_EN)
cfg.bits.rx_en = 1;
else
cfg.bits.rx_en = 0;
if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE)
cfg.bits.crc_check_disable = 1;
else
cfg.bits.crc_check_disable = 0;
if (config & CFG_VMAC_RX_STRIP_CRC)
cfg.bits.strip_crc = 1;
else
cfg.bits.strip_crc = 0;
if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR)
cfg.bits.pass_flow_ctrl_fr = 1;
else
cfg.bits.pass_flow_ctrl_fr = 0;
if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP)
cfg.bits.promiscuous_group = 1;
else
cfg.bits.promiscuous_group = 0;
if (config & CFG_VMAC_RX_PROMISCUOUS_MODE)
cfg.bits.promiscuous_mode = 1;
else
cfg.bits.promiscuous_mode = 0;
if (config & CFG_VMAC_RX_LOOP_BACK)
cfg.bits.loopback = 1;
else
cfg.bits.loopback = 0;
break;
default:
HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
" hpi_vmac_rx_config Invalid Input: op <0x%x>", op));
return (HPI_FAILURE);
}
if (max_frame_length)
cfg.bits.rx_max_frame_length = max_frame_length;
HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value);
return (HPI_SUCCESS);
}
hpi_status_t
hpi_vmac_clear_rx_int_stat(hpi_handle_t handle)
{
uint64_t offset;
offset = VMAC_RX_STAT;
REG_PIO_WRITE64(handle, offset, HXGE_VMAC_RX_STAT_CLEAR);
return (HPI_SUCCESS);
}
hpi_status_t
hpi_vmac_clear_tx_int_stat(hpi_handle_t handle)
{
uint64_t offset;
offset = VMAC_TX_STAT;
REG_PIO_WRITE64(handle, offset, HXGE_VMAC_TX_STAT_CLEAR);
return (HPI_SUCCESS);
}
hpi_status_t
hpi_pfc_set_rx_int_stat_mask(hpi_handle_t handle, boolean_t overflow_cnt,
boolean_t frame_cnt)
{
uint64_t offset;
uint64_t value = 0;
if (overflow_cnt)
value |= HXGE_VMAC_RX_MASK_OVERFLOW;
if (frame_cnt)
value |= HXGE_VMAC_RX_MASK_FRAME;
offset = VMAC_RX_MSK;
REG_PIO_WRITE64(handle, offset, value);
return (HPI_SUCCESS);
}
hpi_status_t
hpi_pfc_set_tx_int_stat_mask(hpi_handle_t handle, boolean_t overflow_cnt,
boolean_t frame_cnt)
{
uint64_t offset;
uint64_t value = 0;
uint64_t overflow_mask = 0x6;
uint64_t frame_mask = 0x1;
if (overflow_cnt)
value |= overflow_mask;
if (frame_cnt)
value |= frame_mask;
offset = VMAC_TX_MSK;
REG_PIO_WRITE64(handle, offset, value);
return (HPI_SUCCESS);
}
|
