Add code to enumerate NVME bays, fix usb topodenseshrimp

3 files changed, 75 insertions, 40 deletions

diff --git a/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-disk-hc-topology.xml b/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-disk-hc-topology.xml
index da41b21921..975b318751 100644
--- a/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-disk-hc-topology.xml
+++ b/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-disk-hc-topology.xml
@@ -11,12 +11,15 @@
  source.  A copy of the CDDL is also available via the Internet at
  http://www.illumos.org/license/CDDL.
 
- Copyright (c) 2019, Joyent, Inc.
+ Copyright 2020 Joyent, Inc.
 
 -->
 
 <topology name='disk' scheme='hc'>
-  <range name='bay' min='0' max='1'>
+  <range name='bay' min='0' max='3'>
+   <!--
+     There are two, rear-facing SFF SATA bays on this platform.
+   -->
     <node instance='0'>
       <facility name='fail' type='indicator' provider='fac_prov_ahci' >
         <propgroup name='facility' version='1' name-stability='Private'
@@ -53,6 +56,11 @@
           value='/devices/pci@0,0/pci15d9,99d@17:devctl' />
         <propval name='port' type='uint32' value='4' />
       </propgroup>
+      <dependents grouping='children'>
+      <range name='disk' min='0' max='0'>
+        <enum-method name='disk' version='1' />
+      </range>
+      </dependents>
     </node>
     <node instance='1'>
       <facility name='fail' type='indicator' provider='fac_prov_ahci' >
@@ -90,11 +98,60 @@
           value='/devices/pci@0,0/pci15d9,99d@17:devctl' />
         <propval name='port' type='uint32' value='5' />
       </propgroup>
-    </node>
-    <dependents grouping='children'>
+      <dependents grouping='children'>
       <range name='disk' min='0' max='0'>
         <enum-method name='disk' version='1' />
       </range>
-    </dependents>
-   </range>
+      </dependents>
+    </node>
+
+   <!--
+     There are actually 6 U.2 NVME bays on this platform.  But
+     because we don't have a unit with all six bays populated we're
+     not able to determine what their parent devices would be.  We
+     could guess because we know the parent would be a PCI express
+     root port, but we wouldn't know which root ports are associated
+     with which physical bays without actually populating the bays.
+
+     For now we add the data for the first two bays, which are the
+     only ones that would be populated accoridng to our BOM
+     specification.
+   -->
+    <node instance='2'>
+      <propgroup name='protocol' version='1' name-stability='Private'
+        data-stability='Private'>
+        <propval name='label' type='string' value='NVME 0' />
+      </propgroup>
+          <propgroup name='binding' version='1'
+              name-stability='Private' data-stability='Private' >
+              <propval name='driver' type='string' value='nvme' />
+              <propval name='parent-device' type='string'
+                value='/pci@14,0/pci8086,2030@0' />
+      </propgroup>
+      <dependents grouping='children'>
+      <range name='nvme' min='0' max='0'>
+          <enum-method name='disk' version='1' />
+        </range>
+      </dependents>
+    </node>
+
+    <node instance='3'>
+      <propgroup name='protocol' version='1' name-stability='Private'
+        data-stability='Private'>
+        <propval name='label' type='string' value='NVME 1' />
+      </propgroup>
+          <propgroup name='binding' version='1'
+              name-stability='Private' data-stability='Private' >
+              <propval name='driver' type='string' value='nvme' />
+              <propval name='parent-device' type='string'
+                value='/pci@14,0/pci8086,2031@1' />
+      </propgroup>
+      <dependents grouping='children'>
+        <range name='nvme' min='0' max='0'>
+          <enum-method name='disk' version='1' />
+        </range>
+      </dependents>
+    </node>
+
+  </range>  <!-- bay -->
 </topology>
diff --git a/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-hc-topology.xml b/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-hc-topology.xml
index 55621b4ef3..f35ce548d8 100644
--- a/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-hc-topology.xml
+++ b/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-hc-topology.xml
@@ -10,7 +10,7 @@
  source.  A copy of the CDDL is also available via the Internet at
  http://www.illumos.org/license/CDDL.
 
- Copyright (c) 2019, Joyent, Inc.
+ Copyright 2020 Joyent, Inc.
 -->
 
 <topology name='i86pc' scheme='hc'>
@@ -94,7 +94,7 @@
        <range name='fan' min='0' max='100'>
           <enum-method name='ipmi' version='1' />
        </range>
-       <range name='bay' min='0' max='1'>
+       <range name='bay' min='0' max='3'>
           <propmap name='SSG-6049P-E1CR60L-JI006-disk' />
        </range>
       <range name='usb-chassis' min='0' max='256'>
diff --git a/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-usb.usbtopo b/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-usb.usbtopo
index 1e50d0f021..78066db448 100644
--- a/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-usb.usbtopo
+++ b/usr/src/lib/fm/topo/maps/SMCI,SSG-6049P-E1CR60L-JI006/SSG-6049P-E1CR60L-JI006-usb.usbtopo
@@ -10,19 +10,22 @@
 #
 
 #
-# Copyright (c) 2018, Joyent, Inc.
+# Copyright 2020 Joyent, Inc.
 #
 
 #
 # This file describes the USB topology for the SuperMicro
-# SSG-6049P-E1CR36L product. For more information on the format see
-# topo_usb_file.c.
+# SSG-6049P-E1CR36L product, which uses the Super X11DSC+ motherboard.  The
+# board contains two type-A USB 3.0 ports that are exposed externally.  It also
+# has an internal type-A USB 3.0 port on the motherboard.
+#
+# For more information on the format see topo_usb_metadata.c.
 #
 
 enable-acpi-match
 port
 	label
-		Rear Upper Left USB
+		Rear Upper USB
 	chassis
 	external
 	port-type
@@ -35,7 +38,7 @@ end-port
 
 port
 	label
-		Rear Lower Left USB
+		Rear Lower USB
 	chassis
 	external
 	port-type
@@ -48,22 +51,9 @@ end-port
 
 port
 	label
-		Rear Upper Right USB
-	chassis
-	external
-	port-type
-		0x3
-	acpi-path
-		\_SB_.PC00.XHCI.RHUB.HS04
-	acpi-path
-		\_SB_.PC00.XHCI.RHUB.SS04
-end-port
+		Internal USB
 
-port
-	label
-		Rear Lower Right USB
-	chassis
-	external
+	internal
 	port-type
 		0x3
 	acpi-path
@@ -71,15 +61,3 @@ port
 	acpi-path
 		\_SB_.PC00.XHCI.RHUB.SS03
 end-port
-
-port
-	label
-		Internal USB
-	internal
-	port-type
-		0x3
-	acpi-path
-		\_SB_.PC00.XHCI.RHUB.HS10
-	acpi-path
-		\_SB_.PC00.XHCI.RHUB.SS07
-end-port