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authoraf <none@none>2008-04-04 14:41:42 -0700
committeraf <none@none>2008-04-04 14:41:42 -0700
commit5f28a8273cda869edd1af63f0b8cca5b7af42541 (patch)
tree7150df81b0b51510ffd5b7818bcd85fd29bceaa2
parentb13be141d51afb6eefef0d4050031b7e6b8f714f (diff)
downloadillumos-joyent-5f28a8273cda869edd1af63f0b8cca5b7af42541.tar.gz
PSARC/2008/233 Intel 5400 chipset Memory Controller Hub
6656577 FMA for Intel 5400 memory controller 6672458 intel_nb5000 exposes incorrect DIMM size property 6684515 intel_nb5000 driver does not correctly detect last 4 dimms when greater than 4 dimms on channel
Diffstat
-rw-r--r--usr/src/cmd/fm/dicts/INTEL.dict3
-rw-r--r--usr/src/cmd/fm/dicts/INTEL.po18
-rw-r--r--usr/src/cmd/fm/eversholt/files/i386/i86pc/intel.esc11
-rw-r--r--usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c3
-rw-r--r--usr/src/uts/i86pc/io/intel_nb5000/intel_nb5000.c528
-rw-r--r--usr/src/uts/i86pc/io/intel_nb5000/intel_nbdrv.c12
-rw-r--r--usr/src/uts/i86pc/io/intel_nb5000/nb5000.h708
-rw-r--r--usr/src/uts/i86pc/io/intel_nb5000/nb5000_init.c204
-rw-r--r--usr/src/uts/i86pc/io/intel_nb5000/nb_log.h36
-rw-r--r--usr/src/uts/intel/io/pciex/pcie_nb5000.h6
-rw-r--r--usr/src/uts/intel/os/driver_aliases3
-rw-r--r--usr/src/uts/intel/sys/mc_intel.h18
12 files changed, 1290 insertions, 260 deletions
diff --git a/usr/src/cmd/fm/dicts/INTEL.dict b/usr/src/cmd/fm/dicts/INTEL.dict
index 18032bb0da..4a188da541 100644
--- a/usr/src/cmd/fm/dicts/INTEL.dict
+++ b/usr/src/cmd/fm/dicts/INTEL.dict
@@ -1,5 +1,5 @@
#
-# Copyright 2007 Sun Microsystems, Inc. All rights reserved.
+# Copyright 2008 Sun Microsystems, Inc. All rights reserved.
# Use is subject to license terms.
#
# CDDL HEADER START
@@ -70,3 +70,4 @@ fault.memory.intel.page_ce=39
fault.memory.intel.page_ue=40
fault.memory.intel.dimm_ce=41
fault.memory.intel.dimm_ue=42
+fault.cpu.intel.nb.otf=43
diff --git a/usr/src/cmd/fm/dicts/INTEL.po b/usr/src/cmd/fm/dicts/INTEL.po
index 6ec25c676c..63f0c5a8f5 100644
--- a/usr/src/cmd/fm/dicts/INTEL.po
+++ b/usr/src/cmd/fm/dicts/INTEL.po
@@ -1,5 +1,5 @@
#
-# Copyright 2007 Sun Microsystems, Inc. All rights reserved.
+# Copyright 2008 Sun Microsystems, Inc. All rights reserved.
# Use is subject to license terms.
#
# CDDL HEADER START
@@ -697,3 +697,19 @@ msgid "INTEL-8001-AQ.impact"
msgstr "Total system memory capacity will be reduced as pages are retired."
msgid "INTEL-8001-AQ.action"
msgstr "Schedule a repair procedure to replace the affected memory module. Use fmdump -v -u to identify the module."
+#
+# code: INTEL-8001-CC
+# keys: fault.cpu.intel.nb.otf
+#
+msgid "INTEL-8001-CC.type"
+msgstr "Fault"
+msgid "INTEL-8001-CC.severity"
+msgstr "Major"
+msgid "INTEL-8001-CC.description"
+msgstr "Northbridge detected over temperature Refer to %s for more information."
+msgid "INTEL-8001-CC.response"
+msgstr "System panic or reset by BIOS"
+msgid "INTEL-8001-CC.impact"
+msgstr "System may be unexpectedly reset"
+msgid "INTEL-8001-CC.action"
+msgstr "Supply more cooling"
diff --git a/usr/src/cmd/fm/eversholt/files/i386/i86pc/intel.esc b/usr/src/cmd/fm/eversholt/files/i386/i86pc/intel.esc
index 65d09f0418..6f180e4905 100644
--- a/usr/src/cmd/fm/eversholt/files/i386/i86pc/intel.esc
+++ b/usr/src/cmd/fm/eversholt/files/i386/i86pc/intel.esc
@@ -619,8 +619,10 @@ prop fault.memory.intel.fbd.ch@
event ereport.cpu.intel.nb.fbd.otf@motherboard/memory-controller/dram-channel
{within(12s)};
+event ereport.cpu.intel.nb.otf@motherboard {within(12s)};
event fault.memory.intel.fbd.otf@motherboard/memory-controller/dram-channel,
FITrate=100, ASRU=motherboard/memory-controller/dram-channel;
+event fault.cpu.intel.nb.otf@motherboard, FITrate=100, ASRU=motherboard;
event upset.cpu.intel.nb.fbd_otf@motherboard/memory-controller/dram-channel,
engine=serd.cpu.intel.nb.fbd_otf@motherboard/memory-controller/dram-channel;
event ereport.cpu.intel.nb.fbd_otf@motherboard/memory-controller/dram-channel
@@ -638,14 +640,20 @@ prop fault.memory.intel.fbd.otf@
motherboard/memory-controller/dram-channel (1)->
ereport.cpu.intel.nb.fbd_otf@motherboard/memory-controller/dram-channel;
+prop fault.cpu.intel.nb.otf@ motherboard (1)->
+ ereport.cpu.intel.nb.otf@motherboard;
+
event ereport.cpu.intel.nb.unknown@motherboard/memory-controller {within(12s)};
event ereport.cpu.intel.nb.unknown@motherboard/memory-controller/dram-channel
{within(12s)};
+event ereport.cpu.intel.nb.spd@motherboard/memory-controller/dram-channel
+ {within(12s)};
event upset.discard@motherboard/memory-controller;
prop upset.discard@motherboard/memory-controller (0)->
ereport.cpu.intel.nb.unknown@motherboard/memory-controller,
- ereport.cpu.intel.nb.unknown@motherboard/memory-controller/dram-channel;
+ ereport.cpu.intel.nb.unknown@motherboard/memory-controller/dram-channel,
+ ereport.cpu.intel.nb.spd@motherboard/memory-controller/dram-channel;
event ereport.cpu.intel.nb.mem_ds@motherboard/memory-controller{within(30s)};
@@ -731,4 +739,3 @@ prop upset.discard@motherboard/memory-controller/dram-channel/dimm/rank (0)->
ereport.cpu.intel.bus_interconnect_memory@chip/cpu,
ereport.cpu.intel.bus_interconnect@chip/cpu,
ereport.cpu.intel.external@chip/cpu;
-
diff --git a/usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c b/usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c
index 11d6af2523..b954fe2d23 100644
--- a/usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c
+++ b/usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c
@@ -63,6 +63,9 @@ gintel_init(cmi_hdl_t hdl, void **datap)
case INTEL_NB_5000X:
case INTEL_NB_5000V:
case INTEL_NB_5000Z:
+ case INTEL_NB_5400:
+ case INTEL_NB_5400A:
+ case INTEL_NB_5400B:
if (!gintel_ms_unconstrained)
gintel_error_action_return |= CMS_ERRSCOPE_POISONED;
break;
diff --git a/usr/src/uts/i86pc/io/intel_nb5000/intel_nb5000.c b/usr/src/uts/i86pc/io/intel_nb5000/intel_nb5000.c
index 8c0313eb27..894b95deac 100644
--- a/usr/src/uts/i86pc/io/intel_nb5000/intel_nb5000.c
+++ b/usr/src/uts/i86pc/io/intel_nb5000/intel_nb5000.c
@@ -48,7 +48,10 @@
#include "dimm_phys.h"
static uint32_t uerrcnt[2];
-static uint32_t cerrcnt[2];
+static uint32_t cerrcnta[2][2];
+static uint32_t cerrcntb[2][2];
+static uint32_t cerrcntc[2][2];
+static uint32_t cerrcntd[2][2];
static nb_logout_t nb_log;
struct mch_error_code {
@@ -95,7 +98,7 @@ fat_memory_error(const nb_regs_t *rp, void *data)
{
int channel;
uint32_t ferr_fat_fbd, nrecmemb;
- uint16_t nrecmema;
+ uint32_t nrecmema;
char *intr = "nb.unknown";
nb_mem_scatchpad_t *sp = &((nb_scatchpad_t *)data)->ms;
@@ -154,16 +157,19 @@ fat_memory_error(const nb_regs_t *rp, void *data)
static struct mch_error_code nf_fbd_error_code[] = {
+ { 29, EMASK_FBD_M29, ERR_NF_FBD_M29 },
{ 28, EMASK_FBD_M28, ERR_NF_FBD_M28 },
{ 27, EMASK_FBD_M27, ERR_NF_FBD_M27 },
{ 26, EMASK_FBD_M26, ERR_NF_FBD_M26 },
{ 25, EMASK_FBD_M25, ERR_NF_FBD_M25 },
+ { 24, EMASK_FBD_M24, ERR_NF_FBD_M24 },
{ 22, EMASK_FBD_M22, ERR_NF_FBD_M22 },
{ 21, EMASK_FBD_M21, ERR_NF_FBD_M21 },
{ 20, EMASK_FBD_M20, ERR_NF_FBD_M20 },
{ 19, EMASK_FBD_M19, ERR_NF_FBD_M19 },
{ 18, EMASK_FBD_M18, ERR_NF_FBD_M18 },
{ 17, EMASK_FBD_M17, ERR_NF_FBD_M17 },
+ { 16, EMASK_FBD_M16, ERR_NF_FBD_M16 },
{ 15, EMASK_FBD_M15, ERR_NF_FBD_M15 },
{ 14, EMASK_FBD_M14, ERR_NF_FBD_M14 },
{ 13, EMASK_FBD_M13, ERR_NF_FBD_M13 },
@@ -207,7 +213,7 @@ static char *
nf_memory_error(const nb_regs_t *rp, void *data)
{
uint32_t ferr_nf_fbd, recmemb, redmemb;
- uint16_t recmema;
+ uint32_t recmema;
int branch, channel, ecc_locator;
char *intr = "nb.unknown";
nb_mem_scatchpad_t *sp = &((nb_scatchpad_t *)data)->ms;
@@ -290,6 +296,8 @@ nf_memory_error(const nb_regs_t *rp, void *data)
nb_used_spare_rank(sp->branch, sp->rank);
nb_config_gen++;
}
+ } else if ((ferr_nf_fbd & ERR_NF_FBD_M22) != 0) {
+ intr = "nb.spd"; /* SPD protocol */
}
}
if (sp->ras != -1) {
@@ -302,6 +310,11 @@ nf_memory_error(const nb_regs_t *rp, void *data)
}
static struct mch_error_code fat_int_error_code[] = {
+ { 14, EMASK_INT_B14, ERR_FAT_INT_B14 },
+ { 12, EMASK_INT_B12, ERR_FAT_INT_B12 },
+ { 25, EMASK_INT_B25, ERR_FAT_INT_B25 },
+ { 23, EMASK_INT_B23, ERR_FAT_INT_B23 },
+ { 21, EMASK_INT_B21, ERR_FAT_INT_B21 },
{ 7, EMASK_INT_B7, ERR_FAT_INT_B7 },
{ 4, EMASK_INT_B4, ERR_FAT_INT_B4 },
{ 3, EMASK_INT_B3, ERR_FAT_INT_B3 },
@@ -310,17 +323,28 @@ static struct mch_error_code fat_int_error_code[] = {
};
static struct mch_error_code nf_int_error_code[] = {
+ { 27, 0, ERR_NF_INT_B27 },
+ { 24, 0, ERR_NF_INT_B24 },
+ { 22, EMASK_INT_B22, ERR_NF_INT_B22 },
+ { 20, EMASK_INT_B20, ERR_NF_INT_B20 },
+ { 19, EMASK_INT_B19, ERR_NF_INT_B19 },
+ { 18, 0, ERR_NF_INT_B18 },
+ { 17, 0, ERR_NF_INT_B17 },
+ { 16, 0, ERR_NF_INT_B16 },
+ { 11, EMASK_INT_B11, ERR_NF_INT_B11 },
+ { 10, EMASK_INT_B10, ERR_NF_INT_B10 },
+ { 9, EMASK_INT_B9, ERR_NF_INT_B9 },
{ 8, EMASK_INT_B8, ERR_NF_INT_B8 },
{ 6, EMASK_INT_B6, ERR_NF_INT_B6 },
{ 5, EMASK_INT_B5, ERR_NF_INT_B5 }
};
static int
-intel_int_err(uint8_t err_fat_int, uint8_t err_nf_int)
+intel_int_err(uint16_t err_fat_int, uint16_t err_nf_int)
{
int rt = -1;
int nerr = 0;
- uint8_t emask_int = 0;
+ uint32_t emask_int = 0;
int i;
int sz;
@@ -334,6 +358,13 @@ intel_int_err(uint8_t err_fat_int, uint8_t err_nf_int)
}
}
+ if (nb_chipset == INTEL_NB_5400 &&
+ (err_nf_int & NERR_NF_5400_INT_B26) != 0) {
+ err_nf_int &= ~NERR_NF_5400_INT_B26;
+ rt = 26;
+ nerr++;
+ }
+
sz = sizeof (nf_int_error_code) / sizeof (struct mch_error_code);
for (i = 0; i < sz; i++) {
@@ -387,17 +418,43 @@ log_int_err(nb_regs_t *rp, int *interpose)
}
static void
+log_thermal_err(nb_regs_t *rp, int *interpose)
+{
+ int t = 0;
+
+ rp->flag = NB_REG_LOG_THR;
+ rp->nb.thr_regs.ferr_fat_thr = FERR_FAT_THR_RD(interpose);
+ rp->nb.thr_regs.nerr_fat_thr = NERR_FAT_THR_RD(&t);
+ *interpose |= t;
+ rp->nb.thr_regs.ferr_nf_thr = FERR_NF_THR_RD(&t);
+ *interpose |= t;
+ rp->nb.thr_regs.nerr_nf_thr = NERR_NF_THR_RD(&t);
+ *interpose |= t;
+ rp->nb.thr_regs.ctsts = CTSTS_RD();
+ rp->nb.thr_regs.thrtsts = THRTSTS_RD();
+
+ if (rp->nb.thr_regs.ferr_fat_thr || *interpose)
+ FERR_FAT_THR_WR(rp->nb.thr_regs.ferr_fat_thr);
+ if (rp->nb.thr_regs.nerr_fat_thr || *interpose)
+ NERR_FAT_THR_WR(rp->nb.thr_regs.nerr_fat_thr);
+ if (rp->nb.thr_regs.ferr_nf_thr || *interpose)
+ FERR_NF_THR_WR(rp->nb.thr_regs.ferr_nf_thr);
+ if (rp->nb.thr_regs.nerr_nf_thr || *interpose)
+ NERR_NF_THR_WR(rp->nb.thr_regs.nerr_nf_thr);
+
+ if (*interpose) {
+ CTSTS_WR(rp->nb.thr_regs.ctsts);
+ THRTSTS_WR(rp->nb.thr_regs.thrtsts);
+ }
+}
+
+static void
log_dma_err(nb_regs_t *rp, int *interpose)
{
rp->flag = NB_REG_LOG_DMA;
rp->nb.dma_regs.pcists = PCISTS_RD(interpose);
rp->nb.dma_regs.pexdevsts = PCIDEVSTS_RD();
-
- if (rp->nb.dma_regs.pcists)
- PCISTS_WR(rp->nb.dma_regs.pcists);
- if (rp->nb.dma_regs.pexdevsts)
- PCIDEVSTS_WR(rp->nb.dma_regs.pexdevsts);
}
static struct mch_error_code fat_fsb_error_code[] = {
@@ -495,6 +552,37 @@ static struct mch_error_code fat_pex_error_code[] = {
{ 0, EMASK_UNCOR_PEX_IO0, PEX_FAT_IO0 }
};
+static struct mch_error_code fat_unit_pex_5400_error_code[] = {
+ { 32, EMASK_UNIT_PEX_IO32, PEX_5400_FAT_IO32 },
+ { 31, EMASK_UNIT_PEX_IO31, PEX_5400_FAT_IO31 },
+ { 30, EMASK_UNIT_PEX_IO30, PEX_5400_FAT_IO30 },
+ { 29, EMASK_UNIT_PEX_IO29, PEX_5400_FAT_IO29 },
+ { 27, EMASK_UNIT_PEX_IO27, PEX_5400_FAT_IO27 },
+ { 26, EMASK_UNIT_PEX_IO26, PEX_5400_FAT_IO26 },
+ { 25, EMASK_UNIT_PEX_IO25, PEX_5400_FAT_IO25 },
+ { 24, EMASK_UNIT_PEX_IO24, PEX_5400_FAT_IO24 },
+ { 23, EMASK_UNIT_PEX_IO23, PEX_5400_FAT_IO23 },
+ { 22, EMASK_UNIT_PEX_IO22, PEX_5400_FAT_IO22 },
+};
+
+static struct mch_error_code fat_pex_5400_error_code[] = {
+ { 19, EMASK_UNCOR_PEX_IO19, PEX_5400_FAT_IO19 },
+ { 18, EMASK_UNCOR_PEX_IO18, PEX_5400_FAT_IO18 },
+ { 10, EMASK_UNCOR_PEX_IO10, PEX_5400_FAT_IO10 },
+ { 9, EMASK_UNCOR_PEX_IO9, PEX_5400_FAT_IO9 },
+ { 8, EMASK_UNCOR_PEX_IO8, PEX_5400_FAT_IO8 },
+ { 7, EMASK_UNCOR_PEX_IO7, PEX_5400_FAT_IO7 },
+ { 6, EMASK_UNCOR_PEX_IO6, PEX_5400_FAT_IO6 },
+ { 5, EMASK_UNCOR_PEX_IO5, PEX_5400_FAT_IO5 },
+ { 4, EMASK_UNCOR_PEX_IO4, PEX_5400_FAT_IO4 },
+ { 2, EMASK_UNCOR_PEX_IO2, PEX_5400_FAT_IO2 },
+ { 0, EMASK_UNCOR_PEX_IO0, PEX_5400_FAT_IO0 }
+};
+
+static struct mch_error_code fat_rp_5400_error_code[] = {
+ { 1, EMASK_RP_PEX_IO1, PEX_5400_FAT_IO1 }
+};
+
static struct mch_error_code fat_rp_error_code[] = {
{ 1, EMASK_RP_PEX_IO1, PEX_FAT_IO1 }
};
@@ -511,7 +599,22 @@ static struct mch_error_code uncor_pex_error_code[] = {
{ 0, EMASK_UNCOR_PEX_IO0, PEX_NF_IO0 }
};
+static struct mch_error_code uncor_pex_5400_error_code[] = {
+ { 33, EMASK_UNIT_PEX_IO33, PEX_5400_NF_IO33 },
+ { 32, EMASK_UNIT_PEX_IO32, PEX_5400_NF_IO32 },
+ { 31, EMASK_UNIT_PEX_IO31, PEX_5400_NF_IO31 },
+ { 30, EMASK_UNIT_PEX_IO30, PEX_5400_NF_IO30 },
+ { 29, EMASK_UNIT_PEX_IO29, PEX_5400_NF_IO29 },
+ { 28, EMASK_UNIT_PEX_IO28, PEX_5400_NF_IO28 },
+ { 27, EMASK_UNIT_PEX_IO27, PEX_5400_NF_IO27 },
+ { 26, EMASK_UNIT_PEX_IO26, PEX_5400_NF_IO26 },
+ { 25, EMASK_UNIT_PEX_IO25, PEX_5400_NF_IO25 },
+ { 24, EMASK_UNIT_PEX_IO24, PEX_5400_NF_IO24 },
+ { 23, EMASK_UNIT_PEX_IO23, PEX_5400_NF_IO23 },
+};
+
static struct mch_error_code cor_pex_error_code[] = {
+ { 20, EMASK_COR_PEX_IO20, PEX_5400_NF_IO20 },
{ 16, EMASK_COR_PEX_IO16, PEX_NF_IO16 },
{ 15, EMASK_COR_PEX_IO15, PEX_NF_IO15 },
{ 14, EMASK_COR_PEX_IO14, PEX_NF_IO14 },
@@ -521,6 +624,47 @@ static struct mch_error_code cor_pex_error_code[] = {
{ 2, 0, PEX_NF_IO2 }
};
+static struct mch_error_code rp_pex_5400_error_code[] = {
+ { 17, EMASK_RP_PEX_IO17, PEX_5400_NF_IO17 },
+ { 11, EMASK_RP_PEX_IO11, PEX_5400_NF_IO11 }
+};
+
+static struct mch_error_code cor_pex_5400_error_code1[] = {
+ { 19, EMASK_UNCOR_PEX_IO19, PEX_5400_NF_IO19 },
+ { 10, EMASK_UNCOR_PEX_IO10, PEX_5400_NF_IO10 },
+ { 9, EMASK_UNCOR_PEX_IO9, PEX_5400_NF_IO9 },
+ { 8, EMASK_UNCOR_PEX_IO8, PEX_5400_NF_IO8 },
+ { 7, EMASK_UNCOR_PEX_IO7, PEX_5400_NF_IO7 },
+ { 6, EMASK_UNCOR_PEX_IO6, PEX_5400_NF_IO6 },
+ { 5, EMASK_UNCOR_PEX_IO5, PEX_5400_NF_IO5 },
+ { 4, EMASK_UNCOR_PEX_IO4, PEX_5400_NF_IO4 },
+ { 2, EMASK_UNCOR_PEX_IO2, PEX_5400_NF_IO2 },
+ { 0, EMASK_UNCOR_PEX_IO0, PEX_5400_NF_IO0 }
+};
+
+static struct mch_error_code cor_pex_5400_error_code2[] = {
+ { 20, EMASK_COR_PEX_IO20, PEX_5400_NF_IO20 },
+ { 16, EMASK_COR_PEX_IO16, PEX_5400_NF_IO16 },
+ { 15, EMASK_COR_PEX_IO15, PEX_5400_NF_IO15 },
+ { 14, EMASK_COR_PEX_IO14, PEX_5400_NF_IO14 },
+ { 13, EMASK_COR_PEX_IO13, PEX_5400_NF_IO13 },
+ { 12, EMASK_COR_PEX_IO12, PEX_5400_NF_IO12 }
+};
+
+static struct mch_error_code cor_pex_5400_error_code3[] = {
+ { 33, EMASK_UNIT_PEX_IO33, PEX_5400_NF_IO33 },
+ { 32, EMASK_UNIT_PEX_IO32, PEX_5400_NF_IO32 },
+ { 31, EMASK_UNIT_PEX_IO31, PEX_5400_NF_IO31 },
+ { 30, EMASK_UNIT_PEX_IO30, PEX_5400_NF_IO30 },
+ { 29, EMASK_UNIT_PEX_IO29, PEX_5400_NF_IO29 },
+ { 28, EMASK_UNIT_PEX_IO28, PEX_5400_NF_IO28 },
+ { 27, EMASK_UNIT_PEX_IO27, PEX_5400_NF_IO27 },
+ { 26, EMASK_UNIT_PEX_IO26, PEX_5400_NF_IO26 },
+ { 25, EMASK_UNIT_PEX_IO25, PEX_5400_NF_IO25 },
+ { 24, EMASK_UNIT_PEX_IO24, PEX_5400_NF_IO24 },
+ { 23, EMASK_UNIT_PEX_IO23, PEX_5400_NF_IO23 }
+};
+
static struct mch_error_code rp_pex_error_code[] = {
{ 17, EMASK_RP_PEX_IO17, PEX_NF_IO17 },
{ 11, EMASK_RP_PEX_IO11, PEX_NF_IO11 },
@@ -580,6 +724,139 @@ intel_pex_err(uint32_t pex_fat, uint32_t pex_nf_cor)
rt = -1;
return (rt);
}
+
+static struct mch_error_code fat_thr_error_code[] = {
+ { 2, EMASK_THR_F2, ERR_FAT_THR_F2 },
+ { 1, EMASK_THR_F1, ERR_FAT_THR_F1 }
+};
+
+static struct mch_error_code nf_thr_error_code[] = {
+ { 5, EMASK_THR_F5, ERR_NF_THR_F5 },
+ { 4, EMASK_THR_F4, ERR_NF_THR_F4 },
+ { 3, EMASK_THR_F3, ERR_NF_THR_F3 }
+};
+
+static int
+intel_thr_err(uint8_t err_fat_thr, uint8_t err_nf_thr)
+{
+ int rt = -1;
+ int nerr = 0;
+ uint16_t emask_thr = 0;
+ int i;
+ int sz;
+
+ sz = sizeof (fat_thr_error_code) / sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (err_fat_thr & fat_thr_error_code[i].error_bit) {
+ rt = fat_thr_error_code[i].intel_error_list;
+ emask_thr |= fat_thr_error_code[i].emask;
+ nerr++;
+ }
+ }
+
+ sz = sizeof (nf_thr_error_code) / sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (err_nf_thr & nf_thr_error_code[i].error_bit) {
+ rt = nf_thr_error_code[i].intel_error_list;
+ emask_thr |= nf_thr_error_code[i].emask;
+ nerr++;
+ }
+ }
+
+ if (emask_thr)
+ nb_thr_mask_mc(emask_thr);
+ if (nerr > 1)
+ rt = -1;
+ return (rt);
+}
+
+static int
+intel_pex_5400_err(uint32_t pex_fat, uint32_t pex_nf_cor)
+{
+ int rt = -1;
+ int nerr = 0;
+ int i;
+ int sz;
+
+ sz = sizeof (fat_pex_5400_error_code) / sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (pex_fat & fat_pex_5400_error_code[i].error_bit) {
+ rt = fat_pex_5400_error_code[i].intel_error_list;
+ nerr++;
+ }
+ }
+ sz = sizeof (fat_rp_5400_error_code) / sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (pex_fat & fat_rp_5400_error_code[i].error_bit) {
+ rt = fat_rp_5400_error_code[i].intel_error_list;
+ nerr++;
+ }
+ }
+ sz = sizeof (fat_unit_pex_5400_error_code) /
+ sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (pex_fat &
+ fat_unit_pex_5400_error_code[i].error_bit) {
+ rt = fat_unit_pex_5400_error_code[i].intel_error_list;
+ nerr++;
+ }
+ }
+ sz = sizeof (uncor_pex_5400_error_code) /
+ sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (pex_fat & uncor_pex_5400_error_code[i].error_bit) {
+ rt = uncor_pex_5400_error_code[i].intel_error_list;
+ nerr++;
+ }
+ }
+
+ sz = sizeof (rp_pex_5400_error_code) / sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (pex_nf_cor & rp_pex_5400_error_code[i].error_bit) {
+ rt = rp_pex_5400_error_code[i].intel_error_list;
+ nerr++;
+ }
+ }
+
+ sz = sizeof (cor_pex_5400_error_code1) / sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (pex_nf_cor & cor_pex_5400_error_code1[i].error_bit) {
+ rt = cor_pex_5400_error_code1[i].intel_error_list;
+ nerr++;
+ }
+ }
+
+ sz = sizeof (cor_pex_5400_error_code2) / sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (pex_nf_cor & cor_pex_5400_error_code2[i].error_bit) {
+ rt = cor_pex_5400_error_code2[i].intel_error_list;
+ nerr++;
+ }
+ }
+
+ sz = sizeof (cor_pex_5400_error_code3) / sizeof (struct mch_error_code);
+
+ for (i = 0; i < sz; i++) {
+ if (pex_nf_cor & cor_pex_5400_error_code3[i].error_bit) {
+ rt = cor_pex_5400_error_code3[i].intel_error_list;
+ nerr++;
+ }
+ }
+
+ if (nerr > 1)
+ rt = -1;
+ return (rt);
+}
+
static void
log_pex_err(uint64_t ferr, nb_regs_t *rp, int *interpose)
{
@@ -616,11 +893,9 @@ log_pex_err(uint64_t ferr, nb_regs_t *rp, int *interpose)
PEX_NF_FERR_WR(pex, rp->nb.pex_regs.pex_nf_corr_ferr);
if (rp->nb.pex_regs.pex_nf_corr_nerr)
PEX_NF_NERR_WR(pex, rp->nb.pex_regs.pex_nf_corr_nerr);
- if (rp->nb.pex_regs.uncerrsts || *interpose)
+ if (*interpose)
UNCERRSTS_WR(pex, rp->nb.pex_regs.uncerrsts);
- if (rp->nb.pex_regs.pexdevsts || *interpose)
- PEXDEVSTS_WR(pex, rp->nb.pex_regs.pexdevsts);
- if (rp->nb.pex_regs.rperrsts || *interpose)
+ if (*interpose)
RPERRSTS_WR(pex, rp->nb.pex_regs.rperrsts);
if (*interpose)
PEXDEVSTS_WR(pex, 0);
@@ -638,15 +913,15 @@ log_fat_fbd_err(nb_regs_t *rp, int *interpose)
branch = channel >> 1;
rp->nb.fat_fbd_regs.nerr_fat_fbd = NERR_FAT_FBD_RD(&t);
*interpose |= t;
- rp->nb.fat_fbd_regs.nrecmema = NRECMEMA_RD();
- rp->nb.fat_fbd_regs.nrecmemb = NRECMEMB_RD();
- rp->nb.fat_fbd_regs.nrecfglog = NRECFGLOG_RD();
- rp->nb.fat_fbd_regs.nrecfbda = NRECFBDA_RD();
- rp->nb.fat_fbd_regs.nrecfbdb = NRECFBDB_RD();
- rp->nb.fat_fbd_regs.nrecfbdc = NRECFBDC_RD();
- rp->nb.fat_fbd_regs.nrecfbdd = NRECFBDD_RD();
- rp->nb.fat_fbd_regs.nrecfbde = NRECFBDE_RD();
- rp->nb.fat_fbd_regs.nrecfbdf = NRECFBDF_RD();
+ rp->nb.fat_fbd_regs.nrecmema = NRECMEMA_RD(branch);
+ rp->nb.fat_fbd_regs.nrecmemb = NRECMEMB_RD(branch);
+ rp->nb.fat_fbd_regs.nrecfglog = NRECFGLOG_RD(branch);
+ rp->nb.fat_fbd_regs.nrecfbda = NRECFBDA_RD(branch);
+ rp->nb.fat_fbd_regs.nrecfbdb = NRECFBDB_RD(branch);
+ rp->nb.fat_fbd_regs.nrecfbdc = NRECFBDC_RD(branch);
+ rp->nb.fat_fbd_regs.nrecfbdd = NRECFBDD_RD(branch);
+ rp->nb.fat_fbd_regs.nrecfbde = NRECFBDE_RD(branch);
+ rp->nb.fat_fbd_regs.nrecfbdf = NRECFBDF_RD(branch);
rp->nb.fat_fbd_regs.spcps = SPCPS_RD(branch);
rp->nb.fat_fbd_regs.spcpc = SPCPC_RD(branch);
rp->nb.fat_fbd_regs.uerrcnt = UERRCNT_RD(branch);
@@ -661,14 +936,15 @@ log_fat_fbd_err(nb_regs_t *rp, int *interpose)
NERR_FAT_FBD_WR(rp->nb.fat_fbd_regs.nerr_fat_fbd);
/* if interpose write read-only registers to clear from pcii cache */
if (*interpose) {
- NRECMEMA_WR();
- NRECMEMB_WR();
- NRECFGLOG_WR();
- NRECFBDA_WR();
- NRECFBDB_WR();
- NRECFBDC_WR();
- NRECFBDD_WR();
- NRECFBDE_WR();
+ NRECMEMA_WR(branch);
+ NRECMEMB_WR(branch);
+ NRECFGLOG_WR(branch);
+ NRECFBDA_WR(branch);
+ NRECFBDB_WR(branch);
+ NRECFBDC_WR(branch);
+ NRECFBDD_WR(branch);
+ NRECFBDE_WR(branch);
+ NRECFBDF_WR(branch);
}
}
@@ -685,20 +961,36 @@ log_nf_fbd_err(nb_regs_t *rp, int *interpose)
rp->nb.nf_fbd_regs.nerr_nf_fbd = NERR_NF_FBD_RD(&t);
*interpose |= t;
rp->nb.nf_fbd_regs.redmemb = REDMEMB_RD();
- rp->nb.nf_fbd_regs.recmema = RECMEMA_RD();
- rp->nb.nf_fbd_regs.recmemb = RECMEMB_RD();
- rp->nb.nf_fbd_regs.recfglog = RECFGLOG_RD();
- rp->nb.nf_fbd_regs.recfbda = RECFBDA_RD();
- rp->nb.nf_fbd_regs.recfbdb = RECFBDB_RD();
- rp->nb.nf_fbd_regs.recfbdc = RECFBDC_RD();
- rp->nb.nf_fbd_regs.recfbdd = RECFBDD_RD();
- rp->nb.nf_fbd_regs.recfbde = RECFBDE_RD();
- rp->nb.nf_fbd_regs.recfbdf = RECFBDF_RD();
+ rp->nb.nf_fbd_regs.recmema = RECMEMA_RD(branch);
+ rp->nb.nf_fbd_regs.recmemb = RECMEMB_RD(branch);
+ rp->nb.nf_fbd_regs.recfglog = RECFGLOG_RD(branch);
+ rp->nb.nf_fbd_regs.recfbda = RECFBDA_RD(branch);
+ rp->nb.nf_fbd_regs.recfbdb = RECFBDB_RD(branch);
+ rp->nb.nf_fbd_regs.recfbdc = RECFBDC_RD(branch);
+ rp->nb.nf_fbd_regs.recfbdd = RECFBDD_RD(branch);
+ rp->nb.nf_fbd_regs.recfbde = RECFBDE_RD(branch);
+ rp->nb.nf_fbd_regs.recfbdf = RECFBDF_RD(branch);
rp->nb.nf_fbd_regs.spcps = SPCPS_RD(branch);
rp->nb.nf_fbd_regs.spcpc = SPCPC_RD(branch);
- rp->nb.nf_fbd_regs.cerrcnt = CERRCNT_RD(branch);
- rp->nb.nf_fbd_regs.cerrcnt_last = cerrcnt[branch];
- cerrcnt[branch] = rp->nb.nf_fbd_regs.cerrcnt;
+ if (nb_chipset == INTEL_NB_7300 || nb_chipset == INTEL_NB_5400) {
+ rp->nb.nf_fbd_regs.cerrcnta = CERRCNTA_RD(branch, channel);
+ rp->nb.nf_fbd_regs.cerrcntb = CERRCNTB_RD(branch, channel);
+ rp->nb.nf_fbd_regs.cerrcntc = CERRCNTC_RD(branch, channel);
+ rp->nb.nf_fbd_regs.cerrcntd = CERRCNTD_RD(branch, channel);
+ } else {
+ rp->nb.nf_fbd_regs.cerrcnta = CERRCNT_RD(branch);
+ rp->nb.nf_fbd_regs.cerrcntb = 0;
+ rp->nb.nf_fbd_regs.cerrcntc = 0;
+ rp->nb.nf_fbd_regs.cerrcntd = 0;
+ }
+ rp->nb.nf_fbd_regs.cerrcnta_last = cerrcnta[branch][channel & 1];
+ rp->nb.nf_fbd_regs.cerrcntb_last = cerrcntb[branch][channel & 1];
+ rp->nb.nf_fbd_regs.cerrcntc_last = cerrcntc[branch][channel & 1];
+ rp->nb.nf_fbd_regs.cerrcntd_last = cerrcntd[branch][channel & 1];
+ cerrcnta[branch][channel & 1] = rp->nb.nf_fbd_regs.cerrcnta;
+ cerrcntb[branch][channel & 1] = rp->nb.nf_fbd_regs.cerrcntb;
+ cerrcntc[branch][channel & 1] = rp->nb.nf_fbd_regs.cerrcntc;
+ cerrcntd[branch][channel & 1] = rp->nb.nf_fbd_regs.cerrcntd;
rp->nb.nf_fbd_regs.badrama = BADRAMA_RD(branch);
rp->nb.nf_fbd_regs.badramb = BADRAMB_RD(branch);
rp->nb.nf_fbd_regs.badcnt = BADCNT_RD(branch);
@@ -708,14 +1000,15 @@ log_nf_fbd_err(nb_regs_t *rp, int *interpose)
NERR_NF_FBD_WR(rp->nb.nf_fbd_regs.nerr_nf_fbd);
/* if interpose write read-only registers to clear from pcii cache */
if (*interpose) {
- RECMEMA_WR();
- RECMEMB_WR();
- RECFGLOG_WR();
- RECFBDA_WR();
- RECFBDB_WR();
- RECFBDC_WR();
- RECFBDD_WR();
- RECFBDE_WR();
+ RECMEMA_WR(branch);
+ RECMEMB_WR(branch);
+ RECFGLOG_WR(branch);
+ RECFBDA_WR(branch);
+ RECFBDB_WR(branch);
+ RECFBDC_WR(branch);
+ RECFBDD_WR(branch);
+ RECFBDE_WR(branch);
+ RECFBDF_WR(branch);
SPCPS_WR(branch);
}
}
@@ -746,6 +1039,10 @@ log_ferr(uint64_t ferr, uint32_t *nerrp, nb_logout_t *log, int willpanic)
} else if ((ferr & (GE_INT_FATAL | GE_INT_NF)) != 0) {
log_int_err(rp, &interpose);
*nerrp = nerr & ~(GE_INT_FATAL | GE_INT_NF);
+ } else if (nb_chipset == INTEL_NB_5400 &&
+ (ferr & (GE_FERR_THERMAL_FATAL | GE_FERR_THERMAL_NF)) != 0) {
+ log_thermal_err(rp, &interpose);
+ *nerrp = nerr & ~(GE_FERR_THERMAL_FATAL | GE_FERR_THERMAL_NF);
}
if (interpose)
log->type = "inject";
@@ -907,13 +1204,13 @@ nb_int_err_payload(const nb_regs_t *nb_regs, nvlist_t *payload,
char buf[32];
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FERR_FAT_INT,
- DATA_TYPE_UINT8, nb_regs->nb.int_regs.ferr_fat_int, NULL);
+ DATA_TYPE_UINT16, nb_regs->nb.int_regs.ferr_fat_int, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FERR_NF_INT,
- DATA_TYPE_UINT8, nb_regs->nb.int_regs.ferr_nf_int, NULL);
+ DATA_TYPE_UINT16, nb_regs->nb.int_regs.ferr_nf_int, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NERR_FAT_INT,
- DATA_TYPE_UINT8, nb_regs->nb.int_regs.nerr_fat_int, NULL);
+ DATA_TYPE_UINT16, nb_regs->nb.int_regs.nerr_fat_int, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NERR_NF_INT,
- DATA_TYPE_UINT8, nb_regs->nb.int_regs.nerr_nf_int, NULL);
+ DATA_TYPE_UINT16, nb_regs->nb.int_regs.nerr_nf_int, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NRECINT,
DATA_TYPE_UINT32, nb_regs->nb.int_regs.nrecint, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RECINT,
@@ -961,7 +1258,7 @@ nb_fat_fbd_err_payload(const nb_regs_t *nb_regs, nvlist_t *payload,
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FBD,
DATA_TYPE_UINT32, nb_regs->nb.fat_fbd_regs.nerr_fat_fbd, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NRECMEMA,
- DATA_TYPE_UINT16, nb_regs->nb.fat_fbd_regs.nrecmema, NULL);
+ DATA_TYPE_UINT32, nb_regs->nb.fat_fbd_regs.nrecmema, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NRECMEMB,
DATA_TYPE_UINT32, nb_regs->nb.fat_fbd_regs.nrecmemb, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NRECFGLOG,
@@ -1035,7 +1332,7 @@ nb_nf_fbd_err_payload(const nb_regs_t *nb_regs, nvlist_t *payload,
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NERR_NF_FBD,
DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.nerr_nf_fbd, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RECMEMA,
- DATA_TYPE_UINT16, nb_regs->nb.nf_fbd_regs.recmema, NULL);
+ DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.recmema, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RECMEMB,
DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.recmemb, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RECFGLOG,
@@ -1056,10 +1353,44 @@ nb_nf_fbd_err_payload(const nb_regs_t *nb_regs, nvlist_t *payload,
DATA_TYPE_UINT8, nb_regs->nb.nf_fbd_regs.spcps, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SPCPC,
DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.spcpc, NULL);
- fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_CERRCNT,
- DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcnt, NULL);
- fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_CERRCNT_LAST,
- DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcnt_last, NULL);
+ if (nb_chipset == INTEL_NB_7300 || nb_chipset == INTEL_NB_5400) {
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_CERRCNTA,
+ DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcnta, NULL);
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_CERRCNTB,
+ DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcntb, NULL);
+ if (nb_chipset == INTEL_NB_7300) {
+ fm_payload_set(payload,
+ FM_EREPORT_PAYLOAD_NAME_CERRCNTC,
+ DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcntc,
+ NULL);
+ fm_payload_set(payload,
+ FM_EREPORT_PAYLOAD_NAME_CERRCNTD,
+ DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcntd,
+ NULL);
+ }
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_CERRCNTA_LAST,
+ DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcnta_last,
+ NULL);
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_CERRCNTB_LAST,
+ DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcntb_last,
+ NULL);
+ if (nb_chipset == INTEL_NB_7300) {
+ fm_payload_set(payload,
+ FM_EREPORT_PAYLOAD_NAME_CERRCNTC_LAST,
+ DATA_TYPE_UINT32,
+ nb_regs->nb.nf_fbd_regs.cerrcntc_last, NULL);
+ fm_payload_set(payload,
+ FM_EREPORT_PAYLOAD_NAME_CERRCNTD_LAST,
+ DATA_TYPE_UINT32,
+ nb_regs->nb.nf_fbd_regs.cerrcntd_last, NULL);
+ }
+ } else {
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_CERRCNT,
+ DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcnta, NULL);
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_CERRCNT_LAST,
+ DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.cerrcnta_last,
+ NULL);
+ }
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_BADRAMA,
DATA_TYPE_UINT32, nb_regs->nb.nf_fbd_regs.badrama, NULL);
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_BADRAMB,
@@ -1085,6 +1416,34 @@ nb_dma_err_payload(const nb_regs_t *nb_regs, nvlist_t *payload)
}
static void
+nb_thr_err_payload(const nb_regs_t *nb_regs, nvlist_t *payload,
+ nb_scatchpad_t *data)
+{
+ char buf[32];
+
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FERR_FAT_THR,
+ DATA_TYPE_UINT8, nb_regs->nb.thr_regs.ferr_fat_thr, NULL);
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NERR_FAT_THR,
+ DATA_TYPE_UINT8, nb_regs->nb.thr_regs.nerr_fat_thr, NULL);
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FERR_NF_THR,
+ DATA_TYPE_UINT8, nb_regs->nb.thr_regs.ferr_nf_thr, NULL);
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_NERR_NF_THR,
+ DATA_TYPE_UINT8, nb_regs->nb.thr_regs.nerr_nf_thr, NULL);
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_CTSTS,
+ DATA_TYPE_UINT8, nb_regs->nb.thr_regs.ctsts, NULL);
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_THRTSTS,
+ DATA_TYPE_UINT16, nb_regs->nb.thr_regs.thrtsts, NULL);
+ if (data->intel_error_list >= 0) {
+ (void) snprintf(buf, sizeof (buf), "TH%d",
+ data->intel_error_list);
+ } else {
+ (void) snprintf(buf, sizeof (buf), "Multiple or unknown error");
+ }
+ fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_ERROR_NO,
+ DATA_TYPE_STRING, buf, NULL);
+}
+
+static void
nb_ereport_add_logout(nvlist_t *payload, const nb_logout_t *acl,
nb_scatchpad_t *data)
{
@@ -1111,6 +1470,9 @@ nb_ereport_add_logout(nvlist_t *payload, const nb_logout_t *acl,
case NB_REG_LOG_DMA:
nb_dma_err_payload(nb_regs, payload);
break;
+ case NB_REG_LOG_THR:
+ nb_thr_err_payload(nb_regs, payload, data);
+ break;
default:
fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FERR_GLOBAL,
DATA_TYPE_UINT64, nb_regs->ferr, NULL);
@@ -1153,7 +1515,6 @@ nb_pex_report(const nb_regs_t *nb_regs, char *class, nvlist_t *detector,
{
int hostbridge;
-
if (nb_regs->nb.pex_regs.pex == 0) {
fm_fmri_hc_set(detector, FM_HC_SCHEME_VERSION, NULL, NULL, 1,
"motherboard", 0);
@@ -1166,13 +1527,27 @@ nb_pex_report(const nb_regs_t *nb_regs, char *class, nvlist_t *detector,
if (nb_regs->nb.pex_regs.pex_fat_ferr == 0 &&
nb_regs->nb.pex_regs.pex_nf_corr_ferr == 0) {
- data->intel_error_list =
- intel_pex_err(nb_regs->nb.pex_regs.pex_fat_nerr,
- nb_regs->nb.pex_regs.pex_nf_corr_nerr);
+ if (nb_chipset == INTEL_NB_5400) {
+ data->intel_error_list =
+ intel_pex_5400_err(
+ nb_regs->nb.pex_regs.pex_fat_nerr,
+ nb_regs->nb.pex_regs.pex_nf_corr_nerr);
+ } else {
+ data->intel_error_list =
+ intel_pex_err(nb_regs->nb.pex_regs.pex_fat_nerr,
+ nb_regs->nb.pex_regs.pex_nf_corr_nerr);
+ }
} else {
- data->intel_error_list =
- intel_pex_err(nb_regs->nb.pex_regs.pex_fat_ferr,
- nb_regs->nb.pex_regs.pex_nf_corr_ferr);
+ if (nb_chipset == INTEL_NB_5400) {
+ data->intel_error_list =
+ intel_pex_5400_err(
+ nb_regs->nb.pex_regs.pex_fat_ferr,
+ nb_regs->nb.pex_regs.pex_nf_corr_ferr);
+ } else {
+ data->intel_error_list =
+ intel_pex_err(nb_regs->nb.pex_regs.pex_fat_ferr,
+ nb_regs->nb.pex_regs.pex_nf_corr_ferr);
+ }
}
if (nb_regs->nb.pex_regs.pex == 0) {
@@ -1285,6 +1660,20 @@ nb_dma_report(char *class, nvlist_t *detector)
FM_ERROR_CPU, FM_EREPORT_CPU_INTEL, "nb", "dma");
}
+void
+nb_thr_report(const nb_regs_t *nb_regs, char *class, nvlist_t *detector,
+ void *data)
+{
+ ((nb_scatchpad_t *)data)->intel_error_list =
+ intel_thr_err(nb_regs->nb.thr_regs.ferr_fat_thr,
+ nb_regs->nb.thr_regs.ferr_nf_thr);
+ fm_fmri_hc_set(detector, FM_HC_SCHEME_VERSION, NULL, NULL, 1,
+ "motherboard", 0);
+
+ (void) snprintf(class, FM_MAX_CLASS, "%s.%s.%s.%s",
+ FM_ERROR_CPU, FM_EREPORT_CPU_INTEL, "nb", "otf");
+}
+
nvlist_t *
nb_report(const nb_regs_t *nb_regs, char *class, nv_alloc_t *nva, void *scratch)
@@ -1310,6 +1699,9 @@ nb_report(const nb_regs_t *nb_regs, char *class, nv_alloc_t *nva, void *scratch)
case NB_REG_LOG_DMA:
nb_dma_report(class, detector);
break;
+ case NB_REG_LOG_THR:
+ nb_thr_report(nb_regs, class, detector, scratch);
+ break;
default:
fm_fmri_hc_set(detector, FM_HC_SCHEME_VERSION, NULL, NULL, 1,
"motherboard", 0);
diff --git a/usr/src/uts/i86pc/io/intel_nb5000/intel_nbdrv.c b/usr/src/uts/i86pc/io/intel_nb5000/intel_nbdrv.c
index c098ee7ea8..4a0f761b90 100644
--- a/usr/src/uts/i86pc/io/intel_nb5000/intel_nbdrv.c
+++ b/usr/src/uts/i86pc/io/intel_nb5000/intel_nbdrv.c
@@ -20,7 +20,7 @@
*/
/*
- * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
+ * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
@@ -173,6 +173,7 @@ inb_dimm(nb_dimm_t *nb_dimm, uint8_t channel, uint32_t dimm)
(int)(nb_dimm->dimm_size / (1024*1024)));
}
(void) nvlist_add_string(newdimm, "dimm-size", sbuf);
+ (void) nvlist_add_uint64(newdimm, "size", nb_dimm->dimm_size);
(void) nvlist_add_uint32(newdimm, "nbanks", (uint32_t)nb_dimm->nbanks);
(void) nvlist_add_uint32(newdimm, "ncolumn",
(uint32_t)nb_dimm->ncolumn);
@@ -265,6 +266,15 @@ inb_mc_name()
case INTEL_NB_7300:
mc = "Intel 7300";
break;
+ case INTEL_NB_5400:
+ mc = "Intel 5400";
+ break;
+ case INTEL_NB_5400A:
+ mc = "Intel 5400A";
+ break;
+ case INTEL_NB_5400B:
+ mc = "Intel 5400B";
+ break;
case INTEL_NB_5000P:
mc = "Intel 5000P";
break;
diff --git a/usr/src/uts/i86pc/io/intel_nb5000/nb5000.h b/usr/src/uts/i86pc/io/intel_nb5000/nb5000.h
index 459e8ed509..8bf469c71c 100644
--- a/usr/src/uts/i86pc/io/intel_nb5000/nb5000.h
+++ b/usr/src/uts/i86pc/io/intel_nb5000/nb5000.h
@@ -37,17 +37,19 @@ extern "C" {
#define NB_5000_MAX_MEM_CONTROLLERS 2
#define NB_MAX_DIMMS_PER_CHANNEL (nb_chipset == INTEL_NB_7300 ? 8 : 4)
-#define NB_MEM_BRANCH_SELECT 3
+#define NB_MEM_BRANCH_SELECT (nb_chipset == INTEL_NB_5400 ? 2 : 3)
#define NB_MAX_MEM_BRANCH_SELECT 3
#define NB_MEM_RANK_SELECT (nb_chipset == INTEL_NB_7300 ? 7 : 5)
#define NB_MAX_MEM_RANK_SELECT 7
#define NB_RANKS_IN_SELECT 4
-#define NB_PCI_DEV 8
+#define NB_PCI_DEV 10
#define NB_PCI_NFUNC 4
-#define DOCMD_PEX_MASK 0xc0
-#define DOCMD_PEX 0x3f
+#define DOCMD_PEX_MASK 0x00
+#define DOCMD_5400_PEX_MASK 0x000
+#define DOCMD_PEX 0xf0
+#define DOCMD_5400_PEX 0xff0
#define SPD_BUSY 0x1000
#define SPD_BUS_ERROR 0x2000
@@ -63,14 +65,20 @@ extern "C" {
#define TLOW_MAX 0x100000000ULL
-#define MTR_PRESENT(mtr) ((mtr) & 0x0100)
-#define MTR_ETHROTTLE(mtr) ((mtr) & 0x0080)
-#define MTR_WIDTH(mtr) (((((mtr) >> 6) & 1) + 1) * 4)
-#define MTR_NUMBANK(mtr) (((((mtr) >> 5) & 1) + 1) * 4)
-#define MTR_NUMRANK(mtr) ((((mtr) >> 4) & 1) + 1)
-#define MTR_NUMROW(mtr) ((((mtr) >> 2) & 3) + 13)
-#define MTR_NUMCOL(mtr) (((mtr) & 3) + 10)
-#define MTR_DIMMSIZE(mtr) ((1 << (MTR_NUMCOL(mtr) + MTR_NUMROW(mtr))) \
+#define MTR_PRESENT(mtr) \
+ ((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0400 : 0x0100))
+#define MTR_ETHROTTLE(mtr) \
+ ((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0200 : 0x0080))
+#define MTR_WIDTH(mtr) \
+ (((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0100 : 0x0040)) ? 8 : 4)
+#define MTR_NUMBANK(mtr) \
+ (((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0040 : 0x0020)) ? 8 : 4)
+#define MTR_NUMRANK(mtr) \
+ (((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0020 : 0x0010)) ? 2 : 1)
+#define MTR_NUMROW(mtr) ((((mtr) >> 2) & 3) + 13)
+#define MTR_NUMCOL(mtr) (((mtr) & 3) + 10)
+
+#define MTR_DIMMSIZE(mtr) ((1ULL << (MTR_NUMCOL(mtr) + MTR_NUMROW(mtr))) \
* MTR_NUMRANK(mtr) * MTR_NUMBANK(mtr) * MTR_WIDTH(mtr))
/* FERR_GLOBAL and NERR_GLOBAL */
@@ -83,10 +91,14 @@ extern "C" {
#define GE_DMA_FATAL 0x40000000 /* DMA engine Fatal Error */
#define GE_FSB1_FATAL 0x20000000 /* FSB1 Fatal Error */
#define GE_FSB0_FATAL 0x10000000 /* FSB0 Fatal Error */
+#define GE_FERR_FBD_FATAL 0x08000000 /* FBD channel Fatal Error */
#define GE_FERR_FBD3_FATAL 0x08000000 /* FBD3 channel Fatal Error */
#define GE_FERR_FBD2_FATAL 0x04000000 /* FBD2 channel Fatal Error */
#define GE_FERR_FBD1_FATAL 0x02000000 /* FBD1 channel Fatal Error */
#define GE_FERR_FBD0_FATAL 0x01000000 /* FBD0 channel Fatal Error */
+#define GE_FERR_THERMAL_FATAL 0x04000000 /* Thermal Fatal Error */
+#define GE_PCIEX9_FATAL 0x02000000 /* PCI Express device 9 Fatal Error */
+#define GE_PCIEX8_FATAL 0x01000000 /* PCI Express device 8 Fatal Error */
#define GE_PCIEX7_FATAL 0x00800000 /* PCI Express device 7 Fatal Error */
#define GE_PCIEX6_FATAL 0x00400000 /* PCI Express device 6 Fatal Error */
#define GE_PCIEX5_FATAL 0x00200000 /* PCI Express device 5 Fatal Error */
@@ -103,6 +115,10 @@ extern "C" {
#define GE_FERR_FBD2_NF 0x00000400 /* FBD channel 2 Non-Fatal Error */
#define GE_FERR_FBD1_NF 0x00000200 /* FBD channel 1 Non-Fatal Error */
#define GE_FERR_FBD0_NF 0x00000100 /* FBD channel 0 Non-Fatal Error */
+#define GE_FERR_FBD_NF 0x00000800 /* FBD channel Non-Fatal Error */
+#define GE_FERR_THERMAL_NF 0x00000400 /* Thermal Non-Fatal Error */
+#define GE_PCIEX9_NF 0x00000200 /* PCI Express dev 9 Non-Fatal Error */
+#define GE_PCIEX8_NF 0x00000100 /* PCI Express dev 8 Non-Fatal Error */
#define GE_PCIEX7_NF 0x00000080 /* PCI Express dev 7 Non-Fatal Error */
#define GE_PCIEX6_NF 0x00000040 /* PCI Express dev 6 Non-Fatal Error */
#define GE_PCIEX5_NF 0x00000020 /* PCI Express dev 5 Non-Fatal Error */
@@ -150,11 +166,13 @@ extern "C" {
/* configuration write error on retry */
#define ERR_FAT_FBD_MASK 0x007fffff
+#define ERR_NF_FBD_M29 0x02000000 /* M29Err DIMM-Isolation Completed */
#define ERR_NF_FBD_M28 0x01000000 /* M28Err DIMM-Spare Copy Completed */
#define ERR_NF_FBD_M27 0x00800000 /* M27Err DIMM-Spare Copy Initiated */
#define ERR_NF_FBD_M26 0x00400000 /* M26Err Redundant Fast Reset */
/* Timeout */
#define ERR_NF_FBD_M25 0x00200000 /* M25Err Memory write error on */
+#define ERR_NF_FBD_M24 0x00100000 /* M24Err refresh error */
/* redundant retry */
#define ERR_NF_FBD_M22 0x00040000 /* M22Err SPD protocol */
#define ERR_NF_FBD_M21 0x00020000 /* M21Err FBD Northbound parity on */
@@ -166,6 +184,7 @@ extern "C" {
/* data ECC */
#define ERR_NF_FBD_M17 0x00002000 /* M17Err Correctable Non-mirrored */
/* demand data ECC */
+#define ERR_NF_FBD_M16 0x00001000 /* M16Err channel failed over */
#define ERR_NF_FBD_M15 0x00000800 /* M15Err Memory or FBD configuration */
/* CRC read error */
#define ERR_NF_FBD_M14 0x00000400 /* M14Err FBD configuration write */
@@ -200,12 +219,14 @@ extern "C" {
ERR_NF_FBD_M17|ERR_NF_FBD_M15|ERR_NF_FBD_M21)
#define ERR_NF_FBD_SPARE (ERR_NF_FBD_M28|ERR_NF_FBD_M27)
+#define EMASK_FBD_M29 0x10000000 /* M29Err DIMM-Isolation Completed */
#define EMASK_FBD_M28 0x08000000 /* M28Err DIMM-Spare Copy Completed */
#define EMASK_FBD_M27 0x04000000 /* M27Err DIMM-Spare Copy Initiated */
#define EMASK_FBD_M26 0x02000000 /* M26Err Redundant Fast Reset */
/* Timeout */
#define EMASK_FBD_M25 0x01000000 /* M25Err Memory write error on */
/* redundant retry */
+#define EMASK_FBD_M24 0x00800000 /* M24Err refresh error */
#define EMASK_FBD_M23 0x00400000 /* M23Err Non-Redundant Fast Reset */
/* Timeout */
#define EMASK_FBD_M22 0x00200000 /* M22Err SPD protocol */
@@ -218,6 +239,7 @@ extern "C" {
/* data ECC */
#define EMASK_FBD_M17 0x00010000 /* M17Err Correctable Non-mirrored */
/* demand data ECC */
+#define EMASK_FBD_M16 0x00008000 /* M16Err channel failed over */
#define EMASK_FBD_M15 0x00004000 /* M15Err Memory or FBD configuration */
/* CRC read error */
#define EMASK_FBD_M14 0x00002000 /* M14Err FBD configuration write */
@@ -249,8 +271,9 @@ extern "C" {
#define EMASK_FBD_M1 0x00000001 /* M1Err memory write error on */
/* non-redundant retry or FBD */
/* configuration write error on retry */
-/* MCH 7300 errata 34 */
-#define EMASK_FBD_RES 0x00808000 /* reserved mask bits */
+/* MCH 7300 errata 34 (reserved mask bits) */
+#define EMASK_5000_FBD_RES (EMASK_FBD_M24|EMASK_FBD_M16)
+#define EMASK_FBD_RES (nb_chipset == INTEL_NB_5400 ? 0 : EMASK_5000_FBD_RES)
#define EMASK_FBD_FATAL (EMASK_FBD_M23|EMASK_FBD_M3|EMASK_FBD_M2|EMASK_FBD_M1)
#define EMASK_FBD_NF (EMASK_FBD_M28|EMASK_FBD_M27|EMASK_FBD_M26|EMASK_FBD_M25| \
@@ -258,17 +281,56 @@ extern "C" {
EMASK_FBD_M17|EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M13|EMASK_FBD_M12| \
EMASK_FBD_M11|EMASK_FBD_M10|EMASK_FBD_M9|EMASK_FBD_M8|EMASK_FBD_M7| \
EMASK_FBD_M6|EMASK_FBD_M5|EMASK_FBD_M4)
+#define EMASK_5400_FBD_FATAL (EMASK_FBD_M23|EMASK_FBD_M2|EMASK_FBD_M1)
+#define EMASK_5400_FBD_NF (EMASK_FBD_M29|EMASK_FBD_M28|EMASK_FBD_M27| \
+ EMASK_FBD_M26|EMASK_FBD_M25|EMASK_FBD_M24|EMASK_FBD_M22|EMASK_FBD_M21| \
+ EMASK_FBD_M20|EMASK_FBD_M19|EMASK_FBD_M18|EMASK_FBD_M17|EMASK_FBD_M16| \
+ EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M13|EMASK_FBD_M12| \
+ EMASK_FBD_M11|EMASK_FBD_M10|EMASK_FBD_M9|EMASK_FBD_M8|EMASK_FBD_M7| \
+ EMASK_FBD_M6|EMASK_FBD_M5|EMASK_FBD_M4)
-#define ERR_FAT_INT_B7 0x10 /* B7Msk Multiple ECC error in any of */
+#define ERR_FAT_INT_B14 0x0400 /* B14Msk SF Scrub DBE */
+#define ERR_FAT_INT_B12 0x0100 /* B12Msk Parity Protected register */
+#define ERR_FAT_INT_B25 0x0080 /* B25Msk illegal HISMM/TSEG access */
+#define ERR_FAT_INT_B23 0x0040 /* B23Msk Vt Unaffiliated port error */
+#define ERR_FAT_INT_B21 0x0020 /* B21Msk illegal way */
+#define ERR_FAT_INT_B7 0x0010 /* B7Msk Multiple ECC error in any of */
/* the ways during SF lookup */
#define ERR_FAT_INT_B4 0x08 /* B4Msk Virtual pin port error */
#define ERR_FAT_INT_B3 0x04 /* B3Msk Coherency violation error for EWB */
#define ERR_FAT_INT_B2 0x02 /* B2Msk Multi-tag hit SF */
#define ERR_FAT_INT_B1 0x01 /* B1Msk DM parity error */
-#define ERR_NF_INT_B8 0x04 /* B8Msk SF Coherency Error for BIL */
-#define ERR_NF_INT_B6 0x02 /* B6Msk Single ECC error on SF lookup */
-#define ERR_NF_INT_B5 0x01 /* B5Msk Address Map error */
+#define ERR_NF_INT_B27 0x4000 /* B27Msk Request received when in S1 */
+#define ERR_NF_INT_B24 0x2000 /* B24Msk DFXERR */
+#define ERR_NF_INT_B19 0x1000 /* B19Msk scrub SBE (SF) */
+#define ERR_NF_INT_B18 0x0800 /* B18Msk perfmon task completion */
+#define ERR_NF_INT_B17 0x0400 /* B17Msk JTAG/TAP error status */
+#define ERR_NF_INT_B16 0x0200 /* B16Msk SMBus error status */
+#define ERR_NF_INT_B22 0x0080 /* B22Msk Victim ROM parity */
+#define ERR_NF_INT_B20 0x0040 /* B20Msk Configuration write abort */
+#define ERR_NF_INT_B11 0x0020 /* B11Msk Victim Ram parity error */
+#define ERR_NF_INT_B10 0x0010 /* B10Msk DM Parity */
+#define ERR_NF_INT_B9 0x0008 /* B9Msk illeagl access */
+#define ERR_NF_INT_B8 0x0004 /* B8Msk SF Coherency Error for BIL */
+#define ERR_NF_INT_B6 0x0002 /* B6Msk Single ECC error on SF lookup */
+#define ERR_NF_INT_B5 0x0001 /* B5Msk Address Map error */
+
+#define NERR_NF_5400_INT_B26 0x0004 /* B26Msk Illeagl Access to */
+ /* non-coherent address space */
+
+#define EMASK_INT_RES 0x02000000 /* Do not change */
+#define EMASK_INT_B25 0x01000000 /* B25Msk illegal HISMM/TSEG access */
+#define EMASK_INT_B23 0x00400000 /* B23Msk Vt Unaffiliated port error */
+#define EMASK_INT_B22 0x00200000 /* B22Msk Victim ROM parity */
+#define EMASK_INT_B21 0x00100000 /* B21Msk illegal way */
+#define EMASK_INT_B20 0x00080000 /* B20Msk Configuration write abort */
+#define EMASK_INT_B19 0x00040000 /* B19Msk Scrub SBE */
+#define EMASK_INT_B14 0x00002000 /* B14Msk Scrub DBE */
+#define EMASK_INT_B12 0x00000800 /* B12Msk Parity Protected */
+#define EMASK_INT_B11 0x00000400 /* B11Msk Victim Ram parity error */
+#define EMASK_INT_B10 0x00000200 /* B10Msk DM Parity */
+#define EMASK_INT_B9 0x00000100 /* B9Msk Illegal Accesss */
#define EMASK_INT_B8 0x80 /* B8Msk SF Coherency Error for BIL */
#define EMASK_INT_B7 0x40 /* B7Msk Multiple ECC error in any of */
@@ -290,10 +352,11 @@ extern "C" {
#define EMASK_INT_FATAL (EMASK_INT_B7|EMASK_INT_B4|EMASK_INT_B3|EMASK_INT_B2| \
EMASK_INT_B1)
#define EMASK_INT_NF (EMASK_INT_B8|EMASK_INT_B6|EMASK_INT_B5)
-#define GE_FBD_FATAL (GE_FERR_FBD0_FATAL|GE_FERR_FBD1_FATAL| \
- GE_FERR_FBD2_FATAL|GE_FERR_FBD3_FATAL)
-#define GE_FBD_NF \
- (GE_FERR_FBD0_NF|GE_FERR_FBD1_NF|GE_FERR_FBD2_NF|GE_FERR_FBD3_NF)
+#define GE_FBD_FATAL ((nb_chipset == INTEL_NB_5400) ? GE_FERR_FBD_FATAL : \
+ (GE_FERR_FBD0_FATAL|GE_FERR_FBD1_FATAL|GE_FERR_FBD2_FATAL| \
+ GE_FERR_FBD3_FATAL))
+#define GE_FBD_NF ((nb_chipset == INTEL_NB_5400) ? GE_FERR_FBD_NF : \
+ (GE_FERR_FBD0_NF|GE_FERR_FBD1_NF|GE_FERR_FBD2_NF|GE_FERR_FBD3_NF))
#define EMASK_UNCOR_PEX_IO18 0x00200000 /* ESI Reset timeout */
#define EMASK_UNCOR_PEX_IO2 0x00100000 /* Received an unsupported */
@@ -309,7 +372,7 @@ extern "C" {
#define EMASK_UNCOR_PEX_IO0 0x00000010 /* data link protocol */
#define EMASK_UNCOR_PEX_IO3 0x00000001 /* training error */
-#define EMASK_COR_PEX_NF_EDM 0x00002000 /* Advisory Non Fatal */
+#define EMASK_COR_PEX_IO20 0x00002000 /* Advisory Non Fatal */
#define EMASK_COR_PEX_IO16 0x00001000 /* replay timer timeout */
#define EMASK_COR_PEX_IO15 0x00000100 /* replay num pollover */
#define EMASK_COR_PEX_IO14 0x00000080 /* bad DLLP */
@@ -320,6 +383,44 @@ extern "C" {
#define EMASK_RP_PEX_IO11 0x00000002 /* uncorrectable message */
#define EMASK_RP_PEX_IO17 0x00000001 /* correctable message */
+#define EMASK_UNIT_PEX_IO33 0x00002000 /* Link autonomous BW change */
+#define EMASK_UNIT_PEX_IO32 0x00001000 /* Received CA Posted Req */
+#define EMASK_UNIT_PEX_IO31 0x00000800 /* Received UR Posted Req */
+#define EMASK_UNIT_PEX_IO30 0x00000400 /* VT-d internal HW */
+#define EMASK_UNIT_PEX_IO29 0x00000200 /* MSI address */
+#define EMASK_UNIT_PEX_IO28 0x00000100 /* Link BW change */
+#define EMASK_UNIT_PEX_IO27 0x00000080 /* stop & scream */
+#define EMASK_UNIT_PEX_IO26 0x00000040 /* Received CA response */
+#define EMASK_UNIT_PEX_IO25 0x00000020 /* Received UR response */
+#define EMASK_UNIT_PEX_IO24 0x00000010 /* Outbound poisoned data */
+#define EMASK_UNIT_PEX_IO23 0x00000008 /* VTd fault */
+#define EMASK_UNIT_PEX_IO22 0x00000004 /* internal header/ctl parity */
+#define EMASK_UNIT_PEX_IO18 0x00000002 /* ESI reset timeout */
+#define EMASK_UNIT_PEX_VPP 0x00000001 /* correctable message detect */
+
+#define PEX_5400_FAT_IO32 0x00800000 /* Received CA Posted Request */
+#define PEX_5400_FAT_IO31 0x00400000 /* Received UR Posted Request */
+#define PEX_5400_FAT_IO30 0x00200000 /* VT-d Internal HW */
+#define PEX_5400_FAT_IO29 0x00100000 /* MSI Address */
+#define PEX_5400_FAT_IO27 0x00040000 /* Stop & Scream */
+#define PEX_5400_FAT_IO26 0x00020000 /* Received CA Response */
+#define PEX_5400_FAT_IO25 0x00010000 /* Received UR Response */
+#define PEX_5400_FAT_IO24 0x00008000 /* Outbound poisoned TLP */
+#define PEX_5400_FAT_IO23 0x00004000 /* VT-d Fault */
+#define PEX_5400_FAT_IO22 0x00002000 /* Internal Header/Control */
+ /* Parity */
+#define PEX_5400_FAT_IO18 0x00001000 /* ESI reset timeout */
+#define PEX_5400_FAT_IO1 0x00000400 /* received fatal error msg */
+#define PEX_5400_FAT_IO2 0x00000200 /* received unsupported req */
+#define PEX_5400_FAT_IO9 0x00000100 /* malformed TLP */
+#define PEX_5400_FAT_IO10 0x00000080 /* receiver buffer overflow */
+#define PEX_5400_FAT_IO8 0x00000040 /* unexpected completion */
+#define PEX_5400_FAT_IO7 0x00000020 /* completer abort */
+#define PEX_5400_FAT_IO6 0x00000010 /* completion timeout */
+#define PEX_5400_FAT_IO5 0x00000008 /* flow control protocol */
+#define PEX_5400_FAT_IO4 0x00000004 /* poisoned TLP */
+#define PEX_5400_FAT_IO19 0x00000002 /* surprise link down */
+#define PEX_5400_FAT_IO0 0x00000001 /* data link layer protocol */
#define PEX_FAT_IO19 0x00001000 /* surprise link down */
#define PEX_FAT_IO18 0x00000800 /* ESI reset timeout */
#define PEX_FAT_IO9 0x00000400 /* malformed TLP */
@@ -334,6 +435,36 @@ extern "C" {
#define PEX_FAT_IO1 0x00000002 /* received fatal error message */
#define PEX_FAT_IO0 0x00000001 /* data link layer protocol */
+#define PEX_5400_NF_IO33 0x20000000 /* link autonomous bandwidth */
+ /* change (correctable) */
+#define PEX_5400_NF_IO32 0x10000000 /* Received CA Posted Request */
+#define PEX_5400_NF_IO31 0x08000000 /* Received UR Posted Request */
+#define PEX_5400_NF_IO30 0x04000000 /* VT-d Internal HW */
+#define PEX_5400_NF_IO29 0x02000000 /* MSI Address */
+#define PEX_5400_NF_IO28 0x01000000 /* Link bandwidth change */
+#define PEX_5400_NF_IO27 0x00800000 /* Stop & Scream */
+#define PEX_5400_NF_IO26 0x00400000 /* Received CA Response */
+#define PEX_5400_NF_IO25 0x00200000 /* Received UR Response */
+#define PEX_5400_NF_IO24 0x00100000 /* Outbound poisoned TLP */
+#define PEX_5400_NF_IO23 0x00080000 /* VT-d Fault */
+#define PEX_5400_NF_IO11 0x00040000 /* received non fatal err msg */
+#define PEX_5400_NF_IO17 0x00020000 /* rec correctable error msg */
+#define PEX_5400_NF_IO2 0x00008000 /* Received unsupported req */
+#define PEX_5400_NF_IO9 0x00004000 /* Malformed TLP */
+#define PEX_5400_NF_IO10 0x00002000 /* Received buffer overflow */
+#define PEX_5400_NF_IO8 0x00001000 /* unexpected completion err */
+#define PEX_5400_NF_IO7 0x00000800 /* completion abort */
+#define PEX_5400_NF_IO6 0x00000400 /* completion timeout */
+#define PEX_5400_NF_IO5 0x00000200 /* flow control protocol */
+#define PEX_5400_NF_IO4 0x00000100 /* poisoned TLP */
+#define PEX_5400_NF_IO19 0x00000080 /* surprise link down */
+#define PEX_5400_NF_IO0 0x00000040 /* data link layer protocol */
+#define PEX_5400_NF_IO20 0x00000020 /* Advisory Non Fatel */
+#define PEX_5400_NF_IO16 0x00000010 /* replay timer timeout */
+#define PEX_5400_NF_IO15 0x00000008 /* replay num pollover */
+#define PEX_5400_NF_IO14 0x00000004 /* bad DLLP */
+#define PEX_5400_NF_IO13 0x00000002 /* bad TLP */
+#define PEX_5400_NF_IO12 0x00000001 /* receiver error mask */
#define PEX_NF_IO19 0x00020000 /* surprise link down */
#define PEX_NF_IO17 0x00010000 /* received correctable error message */
#define PEX_NF_IO16 0x00008000 /* replay timer timeout */
@@ -353,6 +484,19 @@ extern "C" {
#define PEX_NF_IO2 0x00000002
#define PEX_NF_IO0 0x00000001 /* data link layer protocol */
+#define ERR_FAT_TH2 0x02 /* >tmid thermal event */
+#define ERR_FAT_TH1 0x01 /* Catastrophic on-die thermal event */
+
+#define ERR_NF_TH5 0x10 /* timeout on cooling update */
+#define ERR_NF_TH4 0x08 /* TSMAX update */
+#define ERR_NF_TH3 0x04 /* on-die throttling event */
+
+#define EMASK_TH5 0x0010 /* TH5Msk timeout on cooling update */
+#define EMASK_TH4 0x0008 /* TH4Msk TSMAX update */
+#define EMASK_TH3 0x0004 /* TH3Msk on-die throttling event */
+#define EMASK_TH2 0x0002 /* TH2Msk >tmid thermal event */
+#define EMASK_TH1 0x0001 /* TH1Msk Catastrophic on-die thermal event */
+
#define GE_FERR_FSB(ferr) ( \
((ferr) & (GE_FSB0_FATAL|GE_FSB0_NF)) ? 0 : \
((ferr) & (GE_FSB1_FATAL|GE_FSB1_NF)) ? 1 : \
@@ -374,7 +518,7 @@ extern "C" {
#define GE_ERR_PEX(ferr) ( \
((ferr) & (GE_ESI_FATAL|GE_ESI_NF)) ? 0 : \
- ((nb_chipset == INTEL_NB_7300) && \
+ ((nb_chipset == INTEL_NB_7300 || nb_chipset == INTEL_NB_5400) && \
((ferr) & (GE_PCIEX1_FATAL|GE_PCIEX1_NF))) ? 1 : \
((ferr) & (GE_PCIEX2_FATAL|GE_PCIEX2_NF)) ? 2 : \
((ferr) & (GE_PCIEX3_FATAL|GE_PCIEX3_NF)) ? 3 : \
@@ -382,6 +526,9 @@ extern "C" {
((ferr) & (GE_PCIEX5_FATAL|GE_PCIEX5_NF)) ? 5 : \
((ferr) & (GE_PCIEX6_FATAL|GE_PCIEX6_NF)) ? 6 : \
((ferr) & (GE_PCIEX7_FATAL|GE_PCIEX7_NF)) ? 7 : \
+ (nb_chipset == INTEL_NB_5400) && \
+ ((ferr) & (GE_PCIEX8_FATAL|GE_PCIEX8_NF)) ? 8 : \
+ ((ferr) & (GE_PCIEX9_FATAL|GE_PCIEX9_NF)) ? 9 : \
-1)
#define GE_FERR_FATAL ((nb_chipset == INTEL_NB_7300) ? \
@@ -516,21 +663,46 @@ extern "C" {
#define NERR_NF_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \
nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc3 : 0x43, val) : \
nb_pci_putb(0, 16, 0, fsb ? 0x483 : 0x183, val))
-#define EMASK_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \
- nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd2 : 0x52, val) : \
- nb_pci_putw(0, 16, 0, fsb ? 0x492 : 0x192, val))
-#define ERR0_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \
- nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd4 : 0x54, val) : \
- nb_pci_putw(0, 16, 0, fsb ? 0x494 : 0x194, val))
-#define ERR1_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \
- nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd6 : 0x56, val) : \
- nb_pci_putw(0, 16, 0, fsb ? 0x496 : 0x196, val))
-#define ERR2_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \
- nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd8 : 0x58, val) : \
- nb_pci_putw(0, 16, 0, fsb ? 0x498 : 0x198, val))
-#define MCERR_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \
- nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xda : 0x5a, val) : \
- nb_pci_putw(0, 16, 0, fsb ? 0x49a : 0x19a, val))
+#define EMASK_FSB_WR(fsb, val) \
+ { \
+ if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putw(0, 17, ((fsb) & 2) ? 3 : 0, \
+ ((fsb) & 1) ? 0xd2 : 0x52, val); \
+ else \
+ nb_pci_putw(0, 16, 0, fsb ? 0x492 : 0x192, val); \
+ }
+#define ERR0_FSB_WR(fsb, val) \
+ { \
+ if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \
+ (fsb & 1) ? 0xd4 : 0x54, val); \
+ else \
+ nb_pci_putw(0, 16, 0, fsb ? 0x494 : 0x194, val); \
+ }
+#define ERR1_FSB_WR(fsb, val) \
+ { \
+ if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \
+ (fsb & 1) ? 0xd6 : 0x56, val); \
+ else \
+ nb_pci_putw(0, 16, 0, fsb ? 0x496 : 0x196, val); \
+ }
+#define ERR2_FSB_WR(fsb, val) \
+ { \
+ if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \
+ (fsb & 1) ? 0xd8 : 0x58, val); \
+ else \
+ nb_pci_putw(0, 16, 0, fsb ? 0x498 : 0x198, val); \
+ }
+#define MCERR_FSB_WR(fsb, val) \
+ { \
+ if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \
+ (fsb & 1) ? 0xda : 0x5a, val); \
+ else \
+ nb_pci_putw(0, 16, 0, fsb ? 0x49a : 0x19a, val); \
+ }
#define NRECSF_RD() (nb_chipset == INTEL_NB_5000X || \
nb_chipset == INTEL_NB_7300) ? ((uint64_t)( \
@@ -552,25 +724,87 @@ extern "C" {
nb_pci_putl(0, 16, 2, 0xb8, 0); \
}
-#define FERR_FAT_INT_RD(ip) nb_pci_getb(0, 16, 2, 0xc0, ip)
-#define FERR_NF_INT_RD(ip) nb_pci_getb(0, 16, 2, 0xc1, ip)
-#define NERR_FAT_INT_RD(ip) nb_pci_getb(0, 16, 2, 0xc2, ip)
-#define NERR_NF_INT_RD(ip) nb_pci_getb(0, 16, 2, 0xc3, ip)
-#define EMASK_INT_RD() nb_pci_getb(0, 16, 2, 0xcc, 0)
-#define ERR0_INT_RD() nb_pci_getb(0, 16, 2, 0xd0, 0)
-#define ERR1_INT_RD() nb_pci_getb(0, 16, 2, 0xd1, 0)
-#define ERR2_INT_RD() nb_pci_getb(0, 16, 2, 0xd2, 0)
-#define MCERR_INT_RD() nb_pci_getb(0, 16, 2, 0xd3, 0)
-
-#define FERR_FAT_INT_WR(val) nb_pci_putb(0, 16, 2, 0xc0, val)
-#define FERR_NF_INT_WR(val) nb_pci_putb(0, 16, 2, 0xc1, val)
-#define NERR_FAT_INT_WR(val) nb_pci_putb(0, 16, 2, 0xc2, val)
-#define NERR_NF_INT_WR(val) nb_pci_putb(0, 16, 2, 0xc3, val)
-#define EMASK_INT_WR(val) nb_pci_putb(0, 16, 2, 0xcc, val)
-#define ERR0_INT_WR(val) nb_pci_putb(0, 16, 2, 0xd0, val)
-#define ERR1_INT_WR(val) nb_pci_putb(0, 16, 2, 0xd1, val)
-#define ERR2_INT_WR(val) nb_pci_putb(0, 16, 2, 0xd2, val)
-#define MCERR_INT_WR(val) nb_pci_putb(0, 16, 2, 0xd3, val)
+#define FERR_FAT_INT_RD(ip) (((nb_chipset == INTEL_NB_5400) ? \
+ ((uint16_t)nb_pci_getb(0, 16, 2, 0xc1, ip) << 8) : (uint16_t)0) | \
+ nb_pci_getb(0, 16, 2, 0xc0, ip))
+#define FERR_NF_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \
+ ((uint16_t)nb_pci_getb(0, 16, 2, 0xc3, ip) << 8) | \
+ nb_pci_getb(0, 16, 2, 0xc2, ip) : \
+ (uint16_t)nb_pci_getb(0, 16, 2, 0xc1, ip))
+#define NERR_FAT_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \
+ ((uint16_t)nb_pci_getb(0, 16, 2, 0xc4, ip) << 8) | \
+ nb_pci_getb(0, 16, 2, 0xc5, ip) : \
+ (uint16_t)nb_pci_getb(0, 16, 2, 0xc2, ip))
+#define NERR_NF_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \
+ ((uint16_t)nb_pci_getb(0, 16, 2, 0xc6, ip) << 8) | \
+ nb_pci_getb(0, 16, 2, 0xc7, ip) : \
+ (uint16_t)nb_pci_getb(0, 16, 2, 0xc3, ip))
+#define EMASK_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \
+ nb_pci_getl(0, 16, 2, 0xd0, 0) : nb_pci_getb(0, 16, 2, 0xcc, 0))
+#define ERR0_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \
+ nb_pci_getl(0, 16, 2, 0xd4, 0) : nb_pci_getb(0, 16, 2, 0xd0, 0))
+#define ERR1_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \
+ nb_pci_getl(0, 16, 2, 0xd8, 0) : nb_pci_getb(0, 16, 2, 0xd1, 0))
+#define ERR2_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \
+ nb_pci_getl(0, 16, 2, 0xdc, 0) : nb_pci_getb(0, 16, 2, 0xd2, 0))
+#define MCERR_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \
+ nb_pci_getl(0, 16, 2, 0xe0, 0) : nb_pci_getb(0, 16, 2, 0xd3, 0))
+
+#define FERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \
+ nb_pci_putb(0, 16, 2, 0xc0, \
+ val & 0xff); \
+ nb_pci_putb(0, 16, 2, 0xc1, val >> 8); \
+ } else { \
+ nb_pci_putb(0, 16, 2, 0xc0, val); \
+ }
+#define FERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \
+ nb_pci_putb(0, 16, 2, 0xc2, \
+ val & 0xff); \
+ nb_pci_putb(0, 16, 2, 0xc3, val >> 8); \
+ } else { \
+ nb_pci_putb(0, 16, 2, 0xc1, val); \
+ }
+#define NERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \
+ nb_pci_putb(0, 16, 2, 0xc4, \
+ val & 0xff); \
+ nb_pci_putb(0, 16, 2, 0xc5, val >> 8); \
+ } else { \
+ nb_pci_putb(0, 16, 2, 0xc2, val); \
+ }
+#define NERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \
+ nb_pci_putb(0, 16, 2, 0xc6, \
+ val & 0xff); \
+ nb_pci_putb(0, 16, 2, 0xc7, val >> 8); \
+ } else { \
+ nb_pci_putb(0, 16, 2, 0xc3, val); \
+ }
+#define EMASK_5000_INT_WR(val) nb_pci_putb(0, 16, 2, 0xcc, val)
+#define EMASK_5400_INT_WR(val) nb_pci_putl(0, 16, 2, 0xd0, val)
+#define EMASK_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \
+ EMASK_5400_INT_WR(val); \
+ } else { \
+ EMASK_5000_INT_WR(val); \
+ }
+#define ERR0_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \
+ nb_pci_putl(0, 16, 2, 0xd4, val); \
+ } else { \
+ nb_pci_putb(0, 16, 2, 0xd0, val); \
+ }
+#define ERR1_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \
+ nb_pci_putl(0, 16, 2, 0xd8, val); \
+ } else { \
+ nb_pci_putb(0, 16, 2, 0xd1, val); \
+ }
+#define ERR2_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \
+ nb_pci_putl(0, 16, 2, 0xdc, val); \
+ } else { \
+ nb_pci_putb(0, 16, 2, 0xd2, val); \
+ }
+#define MCERR_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \
+ nb_pci_putl(0, 16, 2, 0xe0, val); \
+ } else { \
+ nb_pci_putb(0, 16, 2, 0xd3, val); \
+ }
#define NRECINT_RD() nb_pci_getl(0, 16, 2, 0xc4, 0)
#define RECINT_RD() nb_pci_getl(0, 16, 2, 0xc8, 0)
@@ -598,75 +832,179 @@ extern "C" {
#define ERR2_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb4, val)
#define MCERR_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb8, val)
-#define NRECMEMA_RD() nb_pci_getw(0, 16, 1, 0xbe, 0)
-#define NRECMEMB_RD() nb_pci_getl(0, 16, 1, 0xc0, 0)
-#define NRECFGLOG_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0x74 : 0xc4, 0)
-#define NRECFBDA_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc4 : 0xc8, 0)
-#define NRECFBDB_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc8 : 0xcc, 0)
-#define NRECFBDC_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xcc : 0xd0, 0)
-#define NRECFBDD_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd0 : 0xd4, 0)
-#define NRECFBDE_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd4 : 0xd8, 0)
-#define NRECFBDF_RD() \
- (nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xd8, 0) : 0)
-#define REDMEMB_RD() nb_pci_getl(0, 16, 1, 0x7c, 0)
-#define RECMEMA_RD() \
- nb_pci_getw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : 0xe2, 0)
-#define RECMEMB_RD() nb_pci_getl(0, 16, 1, 0xe4, 0)
-#define RECFGLOG_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0x78 : 0xe8, 0)
-#define RECFBDA_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe8 : 0xec, 0)
-#define RECFBDB_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xec : 0xf0, 0)
-#define RECFBDC_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf0 : 0xf4, 0)
-#define RECFBDD_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf4 : 0xf8, 0)
-#define RECFBDE_RD() \
- nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf8 : 0xfc, 0)
-#define RECFBDF_RD() \
- (nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xfc, 0) : 0)
-#define NRECMEMA_WR() nb_pci_putw(0, 16, 1, 0xbe, 0)
-#define NRECMEMB_WR() nb_pci_putl(0, 16, 1, 0xc0, 0)
-#define NRECFGLOG_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0x74 : 0xc4, 0);
-#define NRECFBDA_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc4 : 0xc8, 0);
-#define NRECFBDB_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc8 : 0xcc, 0);
-#define NRECFBDC_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xcc : 0xd0, 0);
-#define NRECFBDD_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd0 : 0xd4, 0);
-#define NRECFBDE_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd4 : 0xd8, 0);
-#define NRECFBDF_WR() \
- if (nb_chipset == INTEL_NB_7300) \
+#define NRECMEMA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getw(0, (branch) ? 22 : 21, 1, 0xbe, 0) : \
+ nb_pci_getw(0, 16, 1, 0xbe, 0))
+#define NRECMEMB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc0, 0) : \
+ nb_pci_getl(0, 16, 1, 0xc0, 0))
+#define NRECFGLOG_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x74, 0) : \
+ nb_pci_getl(0, 16, 1, 0xc4, 0))
+#define NRECFBDA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc4, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc4 : 0xc8, 0))
+#define NRECFBDB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc8, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc8 : 0xcc, 0))
+#define NRECFBDC_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xcc, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xcc : 0xd0, 0))
+#define NRECFBDD_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd0, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd0 : 0xd4, 0))
+#define NRECFBDE_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd4, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd4 : 0xd8, 0))
+#define NRECFBDF_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd8, 0) : \
+ nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xd8, 0) : 0)
+#define REDMEMB_RD() (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x7c, 0) : \
+ nb_pci_getl(0, 16, 1, 0x7c, 0))
+#define RECMEMA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe0, 0) & 0xffffff : \
+ nb_pci_getw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : 0xe2, 0))
+#define RECMEMB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe4, 0) : \
+ nb_pci_getl(0, 16, 1, 0xe4, 0))
+#define RECFGLOG_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x78, 0) : \
+ nb_chipset == INTEL_NB_7300 ? nb_pci_getl(0, 16, 1, 0x78, 0) : \
+ nb_pci_getl(0, 16, 1, 0xe8, 0))
+#define RECFBDA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe8, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe8 : 0xec, 0))
+#define RECFBDB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xec, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xec : 0xf0, 0))
+#define RECFBDC_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf0, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf0 : 0xf4, 0))
+#define RECFBDD_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf4, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf4 : 0xf8, 0))
+#define RECFBDE_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf8, 0) : \
+ nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf8 : 0xfc, 0))
+#define RECFBDF_RD(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xfc, 0) : \
+ nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xfc, 0) : 0)
+#define NRECMEMA_WR(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_putw(0, (branch) ? 22 : 21, 1, 0xbe, 0) : \
+ nb_pci_putw(0, 16, 1, 0xbe, 0))
+#define NRECMEMB_WR(branch) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc0, 0) : \
+ nb_pci_putl(0, 16, 1, 0xc0, 0))
+#define NRECFGLOG_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x74, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0x74, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xc4, 0)
+#define NRECFBDA_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc4, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xc4, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xc8, 0)
+#define NRECFBDB_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc8, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xc8, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xcc, 0)
+#define NRECFBDC_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xcc, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xcc, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xd0, 0)
+#define NRECFBDD_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd0, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xd0, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xd4, 0)
+#define NRECFBDE_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd4, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xd4, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xd8, 0)
+#define NRECFBDF_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd8, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
nb_pci_putw(0, 16, 1, 0xd8, 0);
-#define REDMEMB_WR() nb_pci_putl(0, 16, 1, 0x7c, 0)
-#define RECMEMA_WR() \
- nb_pci_putw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : 0xe2, 0)
-#define RECMEMB_WR() nb_pci_putl(0, 16, 1, 0xe4, 0)
-#define RECFGLOG_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0x78 : 0xe8, 0);
-#define RECFBDA_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe8 : 0xec, 0);
-#define RECFBDB_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xec : 0xf0, 0);
-#define RECFBDC_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf0 : 0xf4, 0);
-#define RECFBDD_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf4 : 0xf8, 0);
-#define RECFBDE_WR() \
- nb_pci_putl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf8 : 0xfc, 0);
-#define RECFBDF_WR() \
- if (nb_chipset == INTEL_NB_7300) \
+#define REDMEMB_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x7c, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0x7c, 0)
+#define RECMEMA_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe0, 0); \
+ else \
+ nb_pci_putw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : \
+ 0xe2, 0)
+#define RECMEMB_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe4, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xe4, 0)
+#define RECFGLOG_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x78, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0x78, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xe8, 0)
+#define RECFBDA_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe8, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xe8, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xec, 0)
+#define RECFBDB_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xec, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xec, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xf0, 0)
+#define RECFBDC_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf0, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xf0, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xf4, 0)
+#define RECFBDD_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf4, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xf4, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xf8, 0)
+#define RECFBDE_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf8, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
+ nb_pci_putl(0, 16, 1, 0xf8, 0); \
+ else \
+ nb_pci_putl(0, 16, 1, 0xfc, 0)
+#define RECFBDF_WR(branch) \
+ if (nb_chipset == INTEL_NB_5400) \
+ nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xfc, 0); \
+ else if (nb_chipset == INTEL_NB_7300) \
nb_pci_putw(0, 16, 1, 0xf8, 0); \
#define MC_RD() nb_pci_getl(0, 16, 1, 0x40, 0)
@@ -674,10 +1012,14 @@ extern "C" {
#define MCA_RD() nb_pci_getl(0, 16, 1, 0x58, 0)
#define TOLM_RD() nb_pci_getw(0, 16, 1, 0x6c, 0)
-#define MTR_RD(branch, dimm) ((branch) == 0) ? \
- nb_pci_getw(0, 21, 0, 0x80 + dimm * 4, 0) : \
+#define MTR_RD(branch, dimm) (nb_chipset == INTEL_NB_5400 ? \
+ nb_pci_getw(0, (branch) == 0 ? 21 : 22, 0, 0x80 + dimm * 2, 0) : \
+ ((branch) == 0) ? \
+ nb_pci_getw(0, 21, 0, \
+ dimm >= 4 ? 0x82 + (dimm & 3) * 4 : 0x80 + dimm * 4, 0) : \
(nb_number_memory_controllers == 2) ? \
- nb_pci_getw(0, 22, 0, 0x80 + dimm * 4, 0) : 0
+ nb_pci_getw(0, 22, 0, \
+ dimm >= 4 ? 0x82 + (dimm & 3) * 4 : 0x80 + dimm * 4, 0) : 0)
#define MIR_RD(reg) nb_pci_getw(0, 16, 1, 0x80 + ((reg)*4), 0)
#define DMIR_RD(branch, reg) \
@@ -685,34 +1027,51 @@ extern "C" {
(nb_number_memory_controllers == 2) ? \
nb_pci_getl(0, 22, 0, 0x90 + ((reg)*4), 0) : 0
-#define SPCPC_RD(branch) (nb_chipset != INTEL_NB_7300 ? \
+#define SPCPC_RD(branch) (nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? \
(((branch) == 0) ? \
(uint32_t)nb_pci_getb(0, 21, 0, 0x40, 0) : \
(nb_number_memory_controllers == 2) ? \
(uint32_t)nb_pci_getb(0, 22, 0, 0x40, 0) : 0) : \
nb_pci_getl(0, ((branch) == 0) ? 21 : 22, 0, 0x40, 0))
-#define SPCPC_SPARE_ENABLE (nb_chipset != INTEL_NB_7300 ? 1 : 0x20)
-#define SPCPC_SPRANK(spcpc) (nb_chipset != INTEL_NB_7300 ? \
+#define SPCPC_SPARE_ENABLE (nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? 1 : 0x20)
+#define SPCPC_SPRANK(spcpc) (nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? \
(((spcpc) >> 1) & 7) : ((spcpc) & 0xf))
#define SPCPS_RD(branch) ((branch) == 0) ? \
- nb_pci_getb(0, 21, 0, nb_chipset != INTEL_NB_7300 ? 0x41 : 0x43, 0) : \
+ nb_pci_getb(0, 21, 0, nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0) : \
(nb_number_memory_controllers == 2) ? \
- nb_pci_getb(0, 22, 0, nb_chipset != INTEL_NB_7300 ? 0x41 : 0x43, 0) : 0
+ nb_pci_getb(0, 22, 0, nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0) : 0
#define SPCPS_WR(branch) \
if ((branch) == 0) { \
- nb_pci_putb(0, 21, 0, nb_chipset != INTEL_NB_7300 ? 0x41 : \
- 0x43, 0); \
+ nb_pci_putb(0, 21, 0, nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || \
+ nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0); \
} else if (nb_number_memory_controllers == 2) { \
- nb_pci_putb(0, 22, 0, nb_chipset != INTEL_NB_7300 ? 0x41 : \
- 0x43, 0); \
+ nb_pci_putb(0, 22, 0, nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || \
+ nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0); \
}
-#define SPCPS_SPARE_DEPLOYED (nb_chipset != INTEL_NB_7300 ? 0x11 : 0x60)
-#define SPCPS_FAILED_RANK(spcps) (nb_chipset != INTEL_NB_7300 ? \
- (((spcps) >> 1) & 7) : ((spcps) & 0xf))
+#define SPCPS_SPARE_DEPLOYED (nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? 0x11 : 0x60)
+#define SPCPS_FAILED_RANK(spcps) (nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? (((spcps) >> 1) & 7) : ((spcps) & 0xf))
#define UERRCNT_RD(branch) ((branch) == 0) ? \
nb_pci_getl(0, 21, 0, 0xa4, 0) : \
@@ -722,6 +1081,20 @@ extern "C" {
nb_pci_getl(0, 21, 0, 0xa8, 0) : \
(nb_number_memory_controllers == 2) ? \
nb_pci_getl(0, 22, 0, 0xa8, 0) : 0
+#define CERRCNTA_RD(branch, channel) \
+ nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \
+ (channel & 1) == 0 ? 0xe0 : 0xf0, 0)
+#define CERRCNTB_RD(branch, channel) \
+ nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \
+ (channel & 1) == 0 ? 0xe4 : 0xf4, 0)
+#define CERRCNTC_RD(branch, channel) \
+ (nb_chipset == INTEL_NB_7300 ? \
+ nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \
+ (channel & 1) == 0 ? 0xe8 : 0xf8, 0) : 0)
+#define CERRCNTD_RD(branch, channel) \
+ (nb_chipset == INTEL_NB_7300 ? \
+ nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \
+ (channel & 1) == 0 ? 0xec : 0xfc, 0) : 0)
#define BADRAMA_RD(branch) ((branch) == 0) ? \
nb_pci_getl(0, 21, 0, 0xac, 0) : \
(nb_number_memory_controllers == 2) ? \
@@ -821,12 +1194,17 @@ extern "C" {
#define PCIDEVSTS_WR(val) nb_pci_putw(0, 8, 0, 0x76, val)
#define RANK_MASK (nb_chipset != INTEL_NB_7300 ? 7 : 0xf)
-#define CAS_MASK (nb_chipset != INTEL_NB_7300 ? 0xfff : 0x1fff)
-#define RAS_MASK (nb_chipset != INTEL_NB_7300 ? 0x7fff : 0xffff)
+#define CAS_MASK (nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? 0xfff : 0x1fff)
+#define RAS_MASK (nb_chipset == INTEL_NB_5000P || \
+ nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \
+ nb_chipset == INTEL_NB_5000Z ? 0x7fff : 0xffff)
#define BANK_MASK 7
#define DMIR_RANKS(dmir, rank0, rank1, rank2, rank3) \
- if (nb_chipset != INTEL_NB_7300) { \
+ if (nb_chipset == INTEL_NB_5000P || nb_chipset == INTEL_NB_5000X || \
+ nb_chipset == INTEL_NB_5000V || nb_chipset == INTEL_NB_5000Z) { \
rank0 = (dmir) & 3; \
rank1 = ((dmir) >> 3) & 3; \
rank2 = ((dmir) >> 6) & 3; \
@@ -838,6 +1216,48 @@ extern "C" {
rank3 = ((dmir) >> 12) & 0xf; \
}
+#define FERR_FAT_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf0, ip)
+#define FERR_NF_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf1, ip)
+#define NERR_FAT_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf2, ip)
+#define NERR_NF_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf3, ip)
+#define EMASK_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xf6, ip)
+#define ERR0_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xf8, ip)
+#define ERR1_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfa, ip)
+#define ERR2_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfc, ip)
+#define MCERR_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfe, ip)
+#define CTSTS_RD() nb_pci_getb(0, 16, 4, 0xee, 0)
+#define THRTSTS_RD() nb_pci_getw(0, 16, 3, 0x68, 0)
+
+#define FERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf0, val)
+#define FERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf1, val)
+#define NERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf2, val)
+#define NERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf3, val)
+#define EMASK_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf6, val)
+#define ERR0_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf8, val)
+#define ERR1_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfa, val)
+#define ERR2_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfc, val)
+#define MCERR_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfe, val)
+#define CTSTS_WR(val) nb_pci_putb(0, 16, 4, 0xee, val)
+#define THRTSTS_WR(val) nb_pci_putw(0, 16, 3, 0x68, val)
+
+#define ERR_FAT_THR_F2 0x02 /* >tnid thermal event with intelligent */
+ /* throttling disabled */
+#define ERR_FAT_THR_F1 0x01 /* catastrophic on-die thermal event */
+
+#define ERR_NF_THR_F5 0x10 /* deadman timeout on cooling update */
+#define ERR_NF_THR_F4 0x08 /* TSMAX Updated */
+#define ERR_NF_THR_F3 0x04 /* On-die throttling event */
+
+#define EMASK_THR_FATAL (ERR_FAT_THR_F2|ERR_FAT_THR_F1)
+#define EMASK_THR_NF (ERR_NF_THR_F5|ERR_NF_THR_F4|ERR_NF_THR_F3)
+
+#define EMASK_THR_F5 0x0010 /* deadman timeout on cooling update */
+#define EMASK_THR_F4 0x0008 /* TSMAX Updated */
+#define EMASK_THR_F3 0x0004 /* On-die throttling event */
+#define EMASK_THR_F2 0x0002 /* >tnid thermal event with intelligent */
+ /* throttling disabled */
+#define EMASK_THR_F1 0x0001 /* catastrophic on-die thermal event */
+
#ifdef __cplusplus
}
#endif
diff --git a/usr/src/uts/i86pc/io/intel_nb5000/nb5000_init.c b/usr/src/uts/i86pc/io/intel_nb5000/nb5000_init.c
index 68f071aaa0..c302a71231 100644
--- a/usr/src/uts/i86pc/io/intel_nb5000/nb5000_init.c
+++ b/usr/src/uts/i86pc/io/intel_nb5000/nb5000_init.c
@@ -74,7 +74,7 @@ static uint8_t nb_err0_int;
static uint8_t nb_err1_int;
static uint8_t nb_err2_int;
static uint8_t nb_mcerr_int;
-static uint8_t nb_emask_int;
+static uint32_t nb_emask_int;
static uint32_t nb_err0_fbd;
static uint32_t nb_err1_fbd;
@@ -88,6 +88,12 @@ static uint16_t nb_err2_fsb;
static uint16_t nb_mcerr_fsb;
static uint16_t nb_emask_fsb;
+static uint16_t nb_err0_thr;
+static uint16_t nb_err1_thr;
+static uint16_t nb_err2_thr;
+static uint16_t nb_mcerr_thr;
+static uint16_t nb_emask_thr;
+
static uint32_t emask_uncor_pex[NB_PCI_DEV];
static uint32_t emask_cor_pex[NB_PCI_DEV];
static uint32_t emask_rp_pex[NB_PCI_DEV];
@@ -97,17 +103,23 @@ static uint32_t uncerrsev[NB_PCI_DEV];
static uint8_t l_mcerr_int;
static uint32_t l_mcerr_fbd;
static uint16_t l_mcerr_fsb;
+static uint16_t l_mcerr_thr;
-uint_t nb5000_emask_fbd = EMASK_FBD_RES;
+uint_t nb5000_emask_fbd = EMASK_5000_FBD_RES;
+uint_t nb5400_emask_fbd = 0;
int nb5000_reset_emask_fbd = 1;
uint_t nb5000_mask_poll_fbd = EMASK_FBD_NF;
uint_t nb5000_mask_bios_fbd = EMASK_FBD_FATAL;
+uint_t nb5400_mask_poll_fbd = EMASK_5400_FBD_NF;
+uint_t nb5400_mask_bios_fbd = EMASK_5400_FBD_FATAL;
uint_t nb5000_emask_fsb = 0;
int nb5000_reset_emask_fsb = 1;
uint_t nb5000_mask_poll_fsb = EMASK_FSB_NF;
uint_t nb5000_mask_bios_fsb = EMASK_FSB_FATAL;
+uint_t nb5400_emask_int = 0;
+
uint_t nb7300_emask_int = EMASK_INT_7300;
uint_t nb7300_emask_int_step0 = EMASK_INT_7300_STEP_0;
uint_t nb5000_emask_int = EMASK_INT_5000;
@@ -115,12 +127,18 @@ int nb5000_reset_emask_int = 1;
uint_t nb5000_mask_poll_int = EMASK_INT_NF;
uint_t nb5000_mask_bios_int = EMASK_INT_FATAL;
+uint_t nb_mask_poll_thr = EMASK_THR_NF;
+uint_t nb_mask_bios_thr = EMASK_THR_FATAL;
+
int nb5000_reset_uncor_pex = 0;
uint_t nb5000_mask_uncor_pex = 0;
-int nb5000_reset_cor_pex = 1;
+int nb5000_reset_cor_pex = 0;
uint_t nb5000_mask_cor_pex = 0xffffffff;
+int nb_set_docmd = 1;
uint32_t nb5000_docmd_pex_mask = DOCMD_PEX_MASK;
+uint32_t nb5400_docmd_pex_mask = DOCMD_5400_PEX_MASK;
uint32_t nb5000_docmd_pex = DOCMD_PEX;
+uint32_t nb5400_docmd_pex = DOCMD_5400_PEX;
int nb_mask_mc_set;
@@ -621,12 +639,13 @@ static void
nb_pex_init()
{
int i;
+ uint32_t mask;
for (i = 0; i < NB_PCI_DEV; i++) {
switch (nb_chipset) {
case INTEL_NB_5000P:
case INTEL_NB_5000X:
- if (i == 1)
+ if (i == 1 || i > 8)
continue;
break;
case INTEL_NB_5000V:
@@ -637,7 +656,11 @@ nb_pex_init()
if (i == 1 || i > 5)
continue;
break;
+ case INTEL_NB_5400:
+ break;
case INTEL_NB_7300:
+ if (i > 8)
+ continue;
break;
}
emask_uncor_pex[i] = EMASK_UNCOR_PEX_RD(i);
@@ -650,8 +673,16 @@ nb_pex_init()
EMASK_UNCOR_PEX_WR(i, nb5000_mask_uncor_pex);
if (nb5000_reset_cor_pex)
EMASK_COR_PEX_WR(i, nb5000_mask_cor_pex);
- PEX_ERR_DOCMD_WR(i, (docmd_pex[i] & nb5000_docmd_pex_mask) |
- (nb5000_docmd_pex & ~nb5000_docmd_pex_mask));
+ if (nb_set_docmd) {
+ if (nb_chipset == INTEL_NB_5400) {
+ mask = (docmd_pex[i] & nb5400_docmd_pex_mask) |
+ (nb5400_docmd_pex & ~nb5400_docmd_pex_mask);
+ } else {
+ mask = (docmd_pex[i] & nb5000_docmd_pex_mask) |
+ (nb5000_docmd_pex & ~nb5000_docmd_pex_mask);
+ }
+ PEX_ERR_DOCMD_WR(i, mask);
+ }
}
}
@@ -664,7 +695,7 @@ nb_pex_fini()
switch (nb_chipset) {
case INTEL_NB_5000P:
case INTEL_NB_5000X:
- if (i == 1)
+ if (i == 1 && i > 8)
continue;
break;
case INTEL_NB_5000V:
@@ -675,14 +706,17 @@ nb_pex_fini()
if (i == 1 || i > 5)
continue;
break;
+ case INTEL_NB_5400:
+ break;
case INTEL_NB_7300:
+ if (i > 8)
+ continue;
break;
}
EMASK_UNCOR_PEX_WR(i, emask_uncor_pex[i]);
EMASK_COR_PEX_WR(i, emask_cor_pex[i]);
EMASK_RP_PEX_WR(i, emask_rp_pex[i]);
PEX_ERR_DOCMD_WR(i, docmd_pex[i]);
- UNCERRSEV_WR(i, uncerrsev[i]);
if (nb5000_reset_uncor_pex)
EMASK_UNCOR_PEX_WR(i, nb5000_mask_uncor_pex);
@@ -698,7 +732,7 @@ nb_int_init()
uint8_t err1_int;
uint8_t err2_int;
uint8_t mcerr_int;
- uint8_t emask_int;
+ uint32_t emask_int;
uint16_t stepping;
err0_int = ERR0_INT_RD();
@@ -735,11 +769,14 @@ nb_int_init()
if (nb_chipset == INTEL_NB_7300) {
stepping = NB5000_STEPPING();
if (stepping == 0)
- EMASK_INT_WR(nb7300_emask_int_step0);
+ EMASK_5000_INT_WR(nb7300_emask_int_step0);
else
- EMASK_INT_WR(nb7300_emask_int);
+ EMASK_5000_INT_WR(nb7300_emask_int);
+ } else if (nb_chipset == INTEL_NB_5400) {
+ EMASK_5400_INT_WR(nb5400_emask_int |
+ (emask_int & EMASK_INT_RES));
} else {
- EMASK_INT_WR(nb5000_emask_int);
+ EMASK_5000_INT_WR(nb5000_emask_int);
}
} else {
EMASK_INT_WR(nb_emask_int);
@@ -763,9 +800,9 @@ nb_int_fini()
}
void
-nb_int_mask_mc(uint8_t mc_mask_int)
+nb_int_mask_mc(uint32_t mc_mask_int)
{
- uint8_t emask_int;
+ uint32_t emask_int;
emask_int = MCERR_INT_RD();
if ((emask_int & mc_mask_int) != mc_mask_int) {
@@ -782,6 +819,8 @@ nb_fbd_init()
uint32_t err2_fbd;
uint32_t mcerr_fbd;
uint32_t emask_fbd;
+ uint32_t emask_bios_fbd;
+ uint32_t emask_poll_fbd;
err0_fbd = ERR0_FBD_RD();
err1_fbd = ERR1_FBD_RD();
@@ -803,25 +842,36 @@ nb_fbd_init()
if (nb_chipset == INTEL_NB_7300 && nb_mode == NB_MEMORY_MIRROR) {
/* MCH 7300 errata 34 */
- nb5000_mask_bios_fbd &= ~EMASK_FBD_M23;
+ emask_bios_fbd = nb5000_mask_bios_fbd & ~EMASK_FBD_M23;
+ emask_poll_fbd = nb5000_mask_poll_fbd;
mcerr_fbd |= EMASK_FBD_M23;
+ } else if (nb_chipset == INTEL_NB_5400) {
+ emask_bios_fbd = nb5400_mask_bios_fbd;
+ emask_poll_fbd = nb5400_mask_poll_fbd;
+ } else {
+ emask_bios_fbd = nb5000_mask_bios_fbd;
+ emask_poll_fbd = nb5000_mask_poll_fbd;
}
- mcerr_fbd &= ~nb5000_mask_bios_fbd;
- mcerr_fbd |= nb5000_mask_bios_fbd & (~err0_fbd | ~err1_fbd | ~err2_fbd);
- mcerr_fbd |= nb5000_mask_poll_fbd;
- err0_fbd |= nb5000_mask_poll_fbd;
- err1_fbd |= nb5000_mask_poll_fbd;
- err2_fbd |= nb5000_mask_poll_fbd;
+ mcerr_fbd &= ~emask_bios_fbd;
+ mcerr_fbd |= emask_bios_fbd & (~err0_fbd | ~err1_fbd | ~err2_fbd);
+ mcerr_fbd |= emask_poll_fbd;
+ err0_fbd |= emask_poll_fbd;
+ err1_fbd |= emask_poll_fbd;
+ err2_fbd |= emask_poll_fbd;
l_mcerr_fbd = mcerr_fbd;
ERR0_FBD_WR(err0_fbd);
ERR1_FBD_WR(err1_fbd);
ERR2_FBD_WR(err2_fbd);
MCERR_FBD_WR(mcerr_fbd);
- if (nb5000_reset_emask_fbd)
- EMASK_FBD_WR(nb5000_emask_fbd);
- else
+ if (nb5000_reset_emask_fbd) {
+ if (nb_chipset == INTEL_NB_5400)
+ EMASK_FBD_WR(nb5400_emask_fbd);
+ else
+ EMASK_FBD_WR(nb5000_emask_fbd);
+ } else {
EMASK_FBD_WR(nb_emask_fbd);
+ }
}
void
@@ -897,19 +947,21 @@ nb_fsb_init()
ERR1_FSB_WR(0, err1_fsb);
ERR2_FSB_WR(0, err2_fsb);
MCERR_FSB_WR(0, mcerr_fsb);
- if (nb5000_reset_emask_fsb)
+ if (nb5000_reset_emask_fsb) {
EMASK_FSB_WR(0, nb5000_emask_fsb);
- else
+ } else {
EMASK_FSB_WR(0, nb_emask_fsb);
+ }
ERR0_FSB_WR(1, err0_fsb);
ERR1_FSB_WR(1, err1_fsb);
ERR2_FSB_WR(1, err2_fsb);
MCERR_FSB_WR(1, mcerr_fsb);
- if (nb5000_reset_emask_fsb)
+ if (nb5000_reset_emask_fsb) {
EMASK_FSB_WR(1, nb5000_emask_fsb);
- else
+ } else {
EMASK_FSB_WR(1, nb_emask_fsb);
+ }
if (nb_chipset == INTEL_NB_7300) {
ERR0_FSB_WR(2, 0xffff);
@@ -928,19 +980,21 @@ nb_fsb_init()
ERR1_FSB_WR(2, err1_fsb);
ERR2_FSB_WR(2, err2_fsb);
MCERR_FSB_WR(2, mcerr_fsb);
- if (nb5000_reset_emask_fsb)
+ if (nb5000_reset_emask_fsb) {
EMASK_FSB_WR(2, nb5000_emask_fsb);
- else
+ } else {
EMASK_FSB_WR(2, nb_emask_fsb);
+ }
ERR0_FSB_WR(3, err0_fsb);
ERR1_FSB_WR(3, err1_fsb);
ERR2_FSB_WR(3, err2_fsb);
MCERR_FSB_WR(3, mcerr_fsb);
- if (nb5000_reset_emask_fsb)
+ if (nb5000_reset_emask_fsb) {
EMASK_FSB_WR(3, nb5000_emask_fsb);
- else
+ } else {
EMASK_FSB_WR(3, nb_emask_fsb);
+ }
}
}
@@ -1009,6 +1063,81 @@ nb_fsb_mask_mc(int fsb, uint16_t mc_mask_fsb)
}
}
+static void
+nb_thr_init()
+{
+ uint16_t err0_thr;
+ uint16_t err1_thr;
+ uint16_t err2_thr;
+ uint16_t mcerr_thr;
+ uint16_t emask_thr;
+
+ if (nb_chipset == INTEL_NB_5400) {
+ err0_thr = ERR0_THR_RD(0);
+ err1_thr = ERR1_THR_RD(0);
+ err2_thr = ERR2_THR_RD(0);
+ mcerr_thr = MCERR_THR_RD(0);
+ emask_thr = EMASK_THR_RD(0);
+
+ ERR0_THR_WR(0xffff);
+ ERR1_THR_WR(0xffff);
+ ERR2_THR_WR(0xffff);
+ MCERR_THR_WR(0xffff);
+ EMASK_THR_WR(0xffff);
+
+ nb_err0_thr = err0_thr;
+ nb_err1_thr = err1_thr;
+ nb_err2_thr = err2_thr;
+ nb_mcerr_thr = mcerr_thr;
+ nb_emask_thr = emask_thr;
+
+ mcerr_thr &= ~nb_mask_bios_thr;
+ mcerr_thr |= nb_mask_bios_thr &
+ (~err2_thr | ~err1_thr | ~err0_thr);
+ mcerr_thr |= nb_mask_poll_thr;
+ err0_thr |= nb_mask_poll_thr;
+ err1_thr |= nb_mask_poll_thr;
+ err2_thr |= nb_mask_poll_thr;
+
+ l_mcerr_thr = mcerr_thr;
+ ERR0_THR_WR(err0_thr);
+ ERR1_THR_WR(err1_thr);
+ ERR2_THR_WR(err2_thr);
+ MCERR_THR_WR(mcerr_thr);
+ EMASK_THR_WR(nb_emask_thr);
+ }
+}
+
+static void
+nb_thr_fini()
+{
+ if (nb_chipset == INTEL_NB_5400) {
+ ERR0_THR_WR(0xffff);
+ ERR1_THR_WR(0xffff);
+ ERR2_THR_WR(0xffff);
+ MCERR_THR_WR(0xffff);
+ EMASK_THR_WR(0xffff);
+
+ ERR0_THR_WR(nb_err0_thr);
+ ERR1_THR_WR(nb_err1_thr);
+ ERR2_THR_WR(nb_err2_thr);
+ MCERR_THR_WR(nb_mcerr_thr);
+ EMASK_THR_WR(nb_emask_thr);
+ }
+}
+
+void
+nb_thr_mask_mc(uint16_t mc_mask_thr)
+{
+ uint16_t emask_thr;
+
+ emask_thr = MCERR_THR_RD(0);
+ if ((emask_thr & mc_mask_thr) != mc_mask_thr) {
+ MCERR_THR_WR(emask_thr|mc_mask_thr);
+ nb_mask_mc_set = 1;
+ }
+}
+
void
nb_mask_mc_reset()
{
@@ -1020,6 +1149,9 @@ nb_mask_mc_reset()
MCERR_FSB_WR(2, l_mcerr_fsb);
MCERR_FSB_WR(3, l_mcerr_fsb);
}
+ if (nb_chipset == INTEL_NB_5400) {
+ MCERR_THR_WR(l_mcerr_thr);
+ }
}
int
@@ -1036,6 +1168,7 @@ nb_dev_init()
return (EAGAIN);
}
nb_int_init();
+ nb_thr_init();
dimm_init();
nb_dimms_init(label_function_p);
nb_mc_init();
@@ -1064,6 +1197,11 @@ nb_init()
case INTEL_NB_5000Z:
nb_number_memory_controllers = 1;
break;
+ case INTEL_NB_5400:
+ case INTEL_NB_5400A:
+ case INTEL_NB_5400B:
+ nb_chipset = INTEL_NB_5400;
+ break;
}
return (0);
}
@@ -1089,6 +1227,7 @@ nb_dev_reinit()
nb_mc_init();
nb_pex_init();
nb_int_init();
+ nb_thr_init();
nb_fbd_init();
nb_fsb_init();
nb_scrubber_enable();
@@ -1115,6 +1254,7 @@ nb_dev_unload()
nb_queue = NULL;
mutex_destroy(&nb_mutex);
nb_int_fini();
+ nb_thr_fini();
nb_fbd_fini();
nb_fsb_fini();
nb_pex_fini();
diff --git a/usr/src/uts/i86pc/io/intel_nb5000/nb_log.h b/usr/src/uts/i86pc/io/intel_nb5000/nb_log.h
index adbe6ca67c..c676df8377 100644
--- a/usr/src/uts/i86pc/io/intel_nb5000/nb_log.h
+++ b/usr/src/uts/i86pc/io/intel_nb5000/nb_log.h
@@ -71,10 +71,10 @@ typedef struct nb_pex_regs {
/* North Bridge memory controller hub internal error registers */
typedef struct nb_int {
- uint8_t ferr_fat_int; /* first fatal error */
- uint8_t ferr_nf_int; /* first non-fatal error */
- uint8_t nerr_fat_int; /* next fatal error */
- uint8_t nerr_nf_int; /* next non-fatal error */
+ uint16_t ferr_fat_int; /* first fatal error */
+ uint16_t ferr_nf_int; /* first non-fatal error */
+ uint16_t nerr_fat_int; /* next fatal error */
+ uint16_t nerr_nf_int; /* next non-fatal error */
uint32_t nrecint; /* non recoverable error log */
uint32_t recint; /* recoverable error log */
uint64_t nrecsf; /* non recoverable control information */
@@ -86,7 +86,7 @@ typedef struct nb_int {
typedef struct nb_fat_fbd {
uint32_t ferr_fat_fbd; /* fb-dimm first fatal error */
uint32_t nerr_fat_fbd; /* fb-dimm next fatal error */
- uint16_t nrecmema; /* non recoverable memory error log */
+ uint32_t nrecmema; /* non recoverable memory error log */
uint32_t nrecmemb; /* non recoverable memory error log */
uint32_t nrecfglog; /* non recoverable dimm configuration */
uint32_t nrecfbda; /* non recoverable dimm log A */
@@ -108,7 +108,7 @@ typedef struct nb_nf_fbd {
uint32_t ferr_nf_fbd; /* fb-dimm first non-fatal error */
uint32_t nerr_nf_fbd; /* fb-dimm next non-fatal error */
uint32_t redmemb; /* recoverable dimm data error log */
- uint16_t recmema; /* recoverable memory error log A */
+ uint32_t recmema; /* recoverable memory error log A */
uint32_t recmemb; /* recoverable memory error log B */
uint32_t recfglog; /* recoverable dimm configuration */
uint32_t recfbda; /* recoverable dimm log A */
@@ -119,8 +119,14 @@ typedef struct nb_nf_fbd {
uint32_t recfbdf; /* recoverable dimm log F */
uint32_t spcpc; /* spare copy control */
uint8_t spcps; /* spare copy status */
- uint32_t cerrcnt; /* correctable error count */
- uint32_t cerrcnt_last; /* saved copy of correctable error count */
+ uint32_t cerrcnta; /* correctable error count A */
+ uint32_t cerrcntb; /* correctable error count B */
+ uint32_t cerrcntc; /* correctable error count C */
+ uint32_t cerrcntd; /* correctable error count D */
+ uint32_t cerrcnta_last; /* saved copy of correctable error count A */
+ uint32_t cerrcntb_last; /* saved copy of correctable error count B */
+ uint32_t cerrcntc_last; /* saved copy of correctable error count C */
+ uint32_t cerrcntd_last; /* saved copy of correctable error count D */
uint32_t badrama; /* bad dram marker A */
uint16_t badramb; /* bad dram marker B */
uint32_t badcnt; /* bad dram counter */
@@ -131,6 +137,15 @@ typedef struct nb_dma {
uint16_t pexdevsts;
} nb_dma_t;
+typedef struct nb_thr {
+ uint8_t ferr_fat_thr;
+ uint8_t ferr_nf_thr;
+ uint8_t nerr_fat_thr;
+ uint8_t nerr_nf_thr;
+ uint8_t ctsts;
+ uint16_t thrtsts;
+} nb_thr_t;
+
typedef struct nb_regs {
int flag;
uint32_t chipset;
@@ -143,6 +158,7 @@ typedef struct nb_regs {
nb_fat_fbd_t fat_fbd_regs;
nb_nf_fbd_t nf_fbd_regs;
nb_dma_t dma_regs;
+ nb_thr_t thr_regs;
} nb;
} nb_regs_t;
@@ -153,6 +169,7 @@ typedef struct nb_regs {
#define NB_REG_LOG_FAT_FBD 4
#define NB_REG_LOG_NF_FBD 5
#define NB_REG_LOG_DMA 6
+#define NB_REG_LOG_THR 7
typedef struct nb_logout {
uint64_t acl_timestamp;
@@ -252,7 +269,8 @@ extern void nb_pci_putl(int, int, int, int, uint32_t);
extern void nb_fsb_mask_mc(int, uint16_t);
extern void nb_fbd_mask_mc(uint32_t);
-extern void nb_int_mask_mc(uint8_t);
+extern void nb_int_mask_mc(uint32_t);
+extern void nb_thr_mask_mc(uint16_t);
extern void nb_mask_mc_reset(void);
extern int nb_mask_mc_set;
diff --git a/usr/src/uts/intel/io/pciex/pcie_nb5000.h b/usr/src/uts/intel/io/pciex/pcie_nb5000.h
index 2c4c286f75..b37ed3d9d5 100644
--- a/usr/src/uts/intel/io/pciex/pcie_nb5000.h
+++ b/usr/src/uts/intel/io/pciex/pcie_nb5000.h
@@ -20,7 +20,7 @@
*/
/*
- * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
+ * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
@@ -38,7 +38,9 @@ extern "C" {
#define INTEL_NB5000_PCIE_DEV_ID(did) (((did) >= 0x3600 && (did) <= 0x360a) || \
((did) == 0x25d8 || (did) == 0x25d4 || (did) == 0x25c0 || \
(did) == 0x25d0 || ((did) >= 0x25e2 && (did) <= 0x25e7)) || \
- ((did) >= 0x25f7 && (did) <= 0x25fa))
+ ((did) >= 0x25f7 && (did) <= 0x25fa) || \
+ (did) == 0x4000 || (did) == 0x4001 || (did) == 0x4003 || \
+ ((did) >= 0x4021 && (did) <= 0x402e))
extern int pcie_intel_error_disable;
diff --git a/usr/src/uts/intel/os/driver_aliases b/usr/src/uts/intel/os/driver_aliases
index 1d4f1a9269..1a40c87679 100644
--- a/usr/src/uts/intel/os/driver_aliases
+++ b/usr/src/uts/intel/os/driver_aliases
@@ -40,4 +40,7 @@ intel_nb5000 "pci8086,25d4"
intel_nb5000 "pci8086,25c0"
intel_nb5000 "pci8086,25d0"
intel_nb5000 "pci8086,3600"
+intel_nb5000 "pci8086,4000"
+intel_nb5000 "pci8086,4001"
+intel_nb5000 "pci8086,4003"
xpv "pci5853,1.1"
diff --git a/usr/src/uts/intel/sys/mc_intel.h b/usr/src/uts/intel/sys/mc_intel.h
index ba955e1686..c7f17a03c1 100644
--- a/usr/src/uts/intel/sys/mc_intel.h
+++ b/usr/src/uts/intel/sys/mc_intel.h
@@ -127,10 +127,25 @@ extern "C" {
#define FM_EREPORT_PAYLOAD_NAME_RECFBDF "recfbdf"
#define FM_EREPORT_PAYLOAD_NAME_CERRCNT "cerrcnt"
#define FM_EREPORT_PAYLOAD_NAME_CERRCNT_LAST "cerrcnt_last"
+#define FM_EREPORT_PAYLOAD_NAME_CERRCNTA "cerrcnta"
+#define FM_EREPORT_PAYLOAD_NAME_CERRCNTB "cerrcntb"
+#define FM_EREPORT_PAYLOAD_NAME_CERRCNTC "cerrcntc"
+#define FM_EREPORT_PAYLOAD_NAME_CERRCNTD "cerrcntd"
+#define FM_EREPORT_PAYLOAD_NAME_CERRCNTA_LAST "cerrcnta_last"
+#define FM_EREPORT_PAYLOAD_NAME_CERRCNTB_LAST "cerrcntb_last"
+#define FM_EREPORT_PAYLOAD_NAME_CERRCNTC_LAST "cerrcntc_last"
+#define FM_EREPORT_PAYLOAD_NAME_CERRCNTD_LAST "cerrcntd_last"
#define FM_EREPORT_PAYLOAD_NAME_PCISTS "pcists"
#define FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS "pexdevsts"
#define FM_EREPORT_PAYLOAD_NAME_ERROR_NO "intel-error-list"
+#define FM_EREPORT_PAYLOAD_NAME_CTSTS "ctsts"
+#define FM_EREPORT_PAYLOAD_NAME_THRTSTS "thrtsts"
+#define FM_EREPORT_PAYLOAD_NAME_FERR_FAT_THR "ferr_fat_thr"
+#define FM_EREPORT_PAYLOAD_NAME_NERR_FAT_THR "nerr_fat_thr"
+#define FM_EREPORT_PAYLOAD_NAME_FERR_NF_THR "ferr_nf_thr"
+#define FM_EREPORT_PAYLOAD_NAME_NERR_NF_THR "nerr_nf_thr"
+
#define FM_EREPORT_PAYLOAD_NAME_ADDR "addr"
#define FM_EREPORT_PAYLOAD_NAME_BANK_NUM "bank-number"
#define FM_EREPORT_PAYLOAD_NAME_BANK_MISC "bank-misc"
@@ -179,6 +194,9 @@ extern "C" {
#define INTEL_NB_5000V 0x25d48086
#define INTEL_NB_5000X 0x25c08086
#define INTEL_NB_5000Z 0x25d08086
+#define INTEL_NB_5400 0x40008086
+#define INTEL_NB_5400A 0x40018086
+#define INTEL_NB_5400B 0x40038086
#define INTEL_NB_7300 0x36008086
#ifdef __cplusplus
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-21 09:09:52 +0000