6371650 pci capability ddi iterator (lint fix)

5 files changed, 18 insertions, 20 deletions

diff --git a/usr/src/uts/common/io/pci_cap.c b/usr/src/uts/common/io/pci_cap.c
index 43e0557f3a..ef9ec04624 100644
--- a/usr/src/uts/common/io/pci_cap.c
+++ b/usr/src/uts/common/io/pci_cap.c
@@ -191,30 +191,28 @@ pci_cap_get(ddi_acc_handle_t h, pci_config_size_t size,
 	uint32_t data;
 
 	if (PCI_CAP_BASE(h, id, &base) != DDI_SUCCESS)
-		return (DDI_FAILURE);
+		return (0xffffffff);
 
 	/*
-	 * Each access to a PCI Configuration Space is checked for
-	 * returned value of -1, in case the a device is offlined
-	 * or if it does not exist.
+	 * Each access to a PCI Configuration Space should be checked
+	 * by the calling function. A returned value of the 2's complement
+	 * of -1 indicates that either the device is offlined or it does not
+	 * exist.
 	 */
 	offset += base;
 
 	switch (size) {
 	case PCI_CAP_CFGSZ_8:
-		if ((data = pci_config_get8(h, offset)) == 0xff)
-			return (DDI_FAILURE);
+		data = pci_config_get8(h, offset);
 		break;
 	case PCI_CAP_CFGSZ_16:
-		if ((data = pci_config_get16(h, offset)) == 0xffff)
-			return (DDI_FAILURE);
+		data = pci_config_get16(h, offset);
 		break;
 	case PCI_CAP_CFGSZ_32:
-		if ((data = pci_config_get32(h, offset)) == 0xffffffff)
-			return (DDI_FAILURE);
+		data = pci_config_get32(h, offset);
 		break;
 	default:
-		return (DDI_FAILURE);
+		data = 0xffffffff;
 	}
 
 	PCI_CAP_DBG("pci_cap_get: %p[x%x]=x%x\n", (void *)h, offset, data);
diff --git a/usr/src/uts/common/io/pci_intr_lib.c b/usr/src/uts/common/io/pci_intr_lib.c
index 07d07bedac..aac81c058a 100644
--- a/usr/src/uts/common/io/pci_intr_lib.c
+++ b/usr/src/uts/common/io/pci_intr_lib.c
@@ -104,7 +104,7 @@ pci_get_msi_ctrl(dev_info_t *dip, int type, ushort_t *msi_ctrl,
 	if ((PCI_CAP_LOCATE(*h, PCI_CAP_ID_MSI, caps_ptr) == DDI_SUCCESS) &&
 		(type == DDI_INTR_TYPE_MSI)) {
 		if ((*msi_ctrl = PCI_CAP_GET16(*h, NULL, *caps_ptr,
-			PCI_MSI_CTRL)) == DDI_FAILURE)
+			PCI_MSI_CTRL)) == 0xffff)
 			goto done;
 
 		DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: MSI "
@@ -116,7 +116,7 @@ pci_get_msi_ctrl(dev_info_t *dip, int type, ushort_t *msi_ctrl,
 	if ((PCI_CAP_LOCATE(*h, PCI_CAP_ID_MSI_X, caps_ptr) == DDI_SUCCESS) &&
 		(type == DDI_INTR_TYPE_MSIX)) {
 		if ((*msi_ctrl = PCI_CAP_GET16(*h, NULL, *caps_ptr,
-			PCI_MSIX_CTRL)) == DDI_FAILURE)
+			PCI_MSIX_CTRL)) == 0xffff)
 			goto done;
 
 		DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: MSI-X "
@@ -491,7 +491,7 @@ pci_msi_set_mask(dev_info_t *rdip, int type, int inum)
 		    PCI_MSI_64BIT_MASKBITS : PCI_MSI_32BIT_MASK;
 
 		if ((mask_bits = PCI_CAP_GET32(cfg_hdle, NULL, caps_ptr,
-			offset)) == DDI_FAILURE)
+			offset)) == 0xffffffff)
 			goto done;
 
 		mask_bits |= (1 << inum);
diff --git a/usr/src/uts/common/io/pcie.c b/usr/src/uts/common/io/pcie.c
index b2108be2d8..649f478825 100644
--- a/usr/src/uts/common/io/pcie.c
+++ b/usr/src/uts/common/io/pcie.c
@@ -233,7 +233,7 @@ pcie_clear_errors(dev_info_t *dip, ddi_acc_handle_t config_handle)
 
 	/* 2. clear the PCIe Errors */
 	if ((device_sts = PCI_CAP_GET16(config_handle, NULL, cap_ptr,
-		PCIE_DEVSTS)) != DDI_FAILURE)
+		PCIE_DEVSTS)) != 0xffff)
 		PCI_CAP_PUT16(config_handle, PCI_CAP_ID_PCI_E, cap_ptr,
 			PCIE_DEVSTS, device_sts);
 
@@ -273,7 +273,7 @@ pcie_enable_errors(dev_info_t *dip, ddi_acc_handle_t config_handle)
 	 * Enable PCI-Express Baseline Error Handling
 	 */
 	if ((device_ctl = PCI_CAP_GET16(config_handle, NULL, cap_ptr,
-		PCIE_DEVCTL)) != DDI_FAILURE) {
+		PCIE_DEVCTL)) != 0xffff) {
 		PCI_CAP_PUT16(config_handle, NULL, cap_ptr, PCIE_DEVCTL,
 			pcie_base_err_default);
 
diff --git a/usr/src/uts/sun4u/io/pci/pci_pci.c b/usr/src/uts/sun4u/io/pci/pci_pci.c
index 3aaaae2971..5674c985b2 100644
--- a/usr/src/uts/sun4u/io/pci/pci_pci.c
+++ b/usr/src/uts/sun4u/io/pci/pci_pci.c
@@ -1020,7 +1020,7 @@ ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *pdip)
 	pmcap = PCI_CAP_GET16(conf_hdl, NULL, ppb->ppb_pm_cap_ptr,
 		PCI_PMCAP);
 
-	if (pmcap == DDI_FAILURE || pmcsr_bse == DDI_FAILURE) {
+	if (pmcap == 0xffff || pmcsr_bse == 0xff) {
 		pci_config_teardown(&conf_hdl);
 		return;
 	}
@@ -1178,7 +1178,7 @@ pci_pwr_current_lvl(pci_pwr_t *pwr_p)
 	    ddi_get_instance(pwr_p->pwr_dip));
 
 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL,
-		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == DDI_FAILURE)
+		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == 0xffff)
 		return (DDI_FAILURE);
 
 	switch (pmcsr & PCI_PMCSR_STATE_MASK) {
@@ -1255,7 +1255,7 @@ ppb_pwr(dev_info_t *dip, int component, int lvl)
 	}
 
 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL,
-		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == DDI_FAILURE)
+		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == 0xffff)
 		return (DDI_FAILURE);
 
 	/*
diff --git a/usr/src/uts/sun4u/io/pci/pcix.c b/usr/src/uts/sun4u/io/pci/pcix.c
index 33d2e0f98b..aa0fd24a6e 100644
--- a/usr/src/uts/sun4u/io/pci/pcix.c
+++ b/usr/src/uts/sun4u/io/pci/pcix.c
@@ -66,7 +66,7 @@ pcix_set_cmd_reg(dev_info_t *child, uint16_t value)
 	 * Read the PCI-X Command Register.
 	 */
 	if ((pcix_cmd = PCI_CAP_GET16(handle, NULL, pcix_cap_ptr, 2))
-		== DDI_FAILURE)
+		== 0xffff)
 		goto teardown;
 
 	DEBUG1(DBG_INIT_CLD, child, "pcix_set_cmd_reg: PCI-X CMD Register "